Personal_System_2_Hardware_Interface_Technical_Reference_May88 Personal System 2 Hardware Interface Technical Reference May88
User Manual: Personal_System_2_Hardware_Interface_Technical_Reference_May88
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First Edition (May 1988) The following paragraph does not apply to the United Kingdom or any country where such provisions are Inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION .. AS IS" WITHOUT WARRANTY OF ANY KIND. EITHER EXPRESS OR IMPLIED. INCLUDING. BUT NOT LIMITED TO. THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied warranties in certain transactions. therefore. this statement may not apply to you. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time. It is possible that this publication may contain reference to. or information about. IBM products (!'(Iachines and programs). programming. or services that are not announced in your country. Such references or information must not be construed to mean that IBM intends to announce such IBM products. programming. or services in your country. THE PUBLICATION OF THE INFORMATION CONTAINED HEREIN IS NOT INTENDED TO AND DOES NOT CONVEY ANY RIGHTS OR LICENSES, EXPRESS OR IMPLIED, UNDER ANY IBM PATENTS, COPYRIGHTS, TRADEMARKS, MASK WORKS OR ANY OTHER INTELLECTUAL PROPERTY RIGHTS. Requests for copies of this publication and for technical information about IBM products should be made to your IBM Authorized Dealer or your IBM Marketing Representative. Personal System/2 is a registered trademark of the International Business Machines Corporation. © Copyright International Business Machines Corporation 1988. All rights reserved. No part of this work may be reproduced or distributed in any form or by any means without prior permission in writing from the IBM Corporation. Preface This technical reference provides hardware and software interface information specifically for IBM Personal System/2 products. This manual contains both a PS/2™ family overview and system-specific information, and should be used with the IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference. This manual is divided into the following: "Micro Channel™ Architecture" describes the Micro Channel signals, timing, electrical characteristics, level-sensitive interrupts, and multidevice arbitration. "Programmable Option Select" describes adapter setup, system configuration utilities, and adapter description files. "Micro Channel Adapter Design" provides information such as adapter dimensions, power requirements, and design guidelines. "Microprocessors and Instruction Sets" describes the various processors used in the Personal System/2 family. Also included is a quick reference for microprocessor assembly instruction sets. "System Board I/O Controllers" describes the input and output interfaces ofthe system board controllers. "Keyboards (101- and 102-Key)" has layouts of the 101- and 102-key keyboards. Keyboard scan-code sets and keyboard specifications are also provided. "Characters and Keystrokes" supplies the decimal and hexadecimal values for ASCII characters. "Power Supply" provides the electrical input/output specifications and describes the theory of operations. Micro Channel and PS/2 are trademarks of the International Business Machines Corporation. "Compatibility" provides hardware and software information to take into consideration, and provides suggestions to aid you in developing your programs. System-specific information concerning hardware implementation and performance is also included. Note: Information added to the system-specific area of this manual may have new information about subjects covered in other parts of this manual. Refer to the system-specific area for information that could affect your hardware or software development decisions. A Bibliography is also provided. Technical Reference Library The technical reference library is intended for those who develop hardware and software products for IBM PS/2 systems and who understand computer architecture and programming concepts. The technical reference library for Personal System/2 products that incorporate the Micro Channel architecture consists of the following: • IBM Personal System/2 Hardware Interface Technical Reference: provides information to support the functions and architecture common to multiple models of the PS/2 family. In this manual, Type 1 refers to the initial hardware design level. Subsequent levels are designated as Type 2, Type 3, and so on. • System-specific technical references: provide information concerning hardware implementation and performance for a given model. • IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference: provides BIOS and Advanced BIOS interface information. • Option and Adapter Technical References: provide hardware and programming information about individual PS/2 options and adapters. II Suggested Reading: • • • • • BASIC for the IBM Personal Computer IBM Disk Operating System (DOS) IBM Operating System/2™ Macro Assembler for the IBM Personal Computer IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference. Additional publications relating to the information contained in this manual are listed in the Bibliography. In this technical reference, the term "Reserved" is used to describe certain signals, bits, and registers. Use of reserved areas can cause compatibility problems, loss of data, or permanent damage to the hardware. Warning: When modifying a register, the state of the reserved bits must be preserved. When possible, read the register first and change only the bits required. Operating System/2 is a trademark of the International Business Machines Corporation. III Notes: Iv Micro Channel Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions (16-Bit) . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions (32-Bit) . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions (Matched-Memory) . . . . . . . . . . . . . . . Signal Descriptions (Auxiliary Video Extension) .......... Micro Channel Connector (16-Bit) . . . . . . . . . . . . . . . . . . . Micro Channel Connector (Auxiliary Video Extension) ...... Micro Channel Connector (32-Bit Section) . . . . . . . . . . . . . . Micro Channel Connector (Matched-Memory Extension) .... Channel Signal Groups (16-Bit. 32-Bit. and Matched-Memory) Channel Signal Groups (Auxiliary Video Extension) ....... Bus Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Arbitration Control Point . . . . . . . . . . . . . . . . . . . . Local Arbiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Burst Mode Preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Fairness and the Inactive State .......... Arbitration Bus Priority Assignments . . . . . . . . . . . . . . . . . Channel Support .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Address Bus Translator . . . . . . . . . . . . . . . . . . . . . . . . . . Data Bus Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level-Sensitive Interrupt Sharing . . . . . . . . . . . . . . . . . . . . . Micro Channel Critical Timing Parameters . . . . . . . . . . . . . . . Basic-Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Basic-Transfer Cycle . . . . . . . . . . . . . . . . . . . . 1/0 and Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Cycle Return Signals . . . . . . . . . . . . . . . . . . . . . Synchronous Special Case of Extended Cycle ......... Synchronous-Extended Cycle (300 Nanoseconds Minimum Special Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous-Extended Cycle (General Case) ........ Asynchronous-Extended Cycle (~300 Nanoseconds Minimum - General Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First Cycle After Grant . . . . . . . . . . . . . . . . . . . . . . . . . Single DMA Transfer (DMA Controller Controlled) ...... Burst DMA Transfer (DMA Controller Terminated) ...... Micro Channel Architecture 1 2 4 11 12 13 15 17 18 19 19 22 23 23 25 28 29 30 30 32 32 32 34 36 36 36 39 40 42 43 44 47 48 50 50 52 54 Burst DMA Transfer (DMA Slave Terminated - Default Cycle 200 Nanoseconds) ........................... Burst DMA Transfer (DMA Slave TerminatedSynchronous-Extended Cycle 300 Nanoseconds) ...... Burst DMA Transfer (DMA Slave Terminated Asynchronous-Extended Cycle :<:!300 Nanoseconds) Arbitration Timing .............................. Arbitration Cycle ............................. Exiting from Inactive State ....................... Configuration Timing ............................ Additional Channel Timings ....................... Auxiliary Video Extension Timing ................... Index II ........................................ Micro Channel Architecture 56 58 60 62 62 62 64 66 67 69 Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. Micro Channel Connectors . . . . . . . . . . . . . . . . . . . . . . . I/O and Memory Transfer Controls . . . . . . . . . . . . . . . . . . Channel Connector Voltage and Signal Assignments (8-Bit Section) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Connector Voltage and Signal Assignments (16-Bit Section) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " Auxiliary Video Extension . . . . . . . . . . . . . . . . . . . . . . Channel Connector Voltage and Signal Assignments (32-Bit Section) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Connector Voltage and Signal Assignments (Matched-Memory Extension) . . . . . . . . . . . . . . . . . . . . Driver/Receiver Requirements and Options .......... Signal Driver Types . . . . . . . . . . . . . . . . . . . . . . . . . . . Distributed Arbitration Block Diagram . . . . . . . . . . . . . . Local Arbiter Example . . . . . . . . . . . . . . . . . . . . . . . . . Burst Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Preempt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration Bus Priority Assignments for Compatibility ... Steering Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Bus Steering Implementation ..... . . . . . . . . . . .. Typical Adapter Interrupt Sharing Implementation ...... Interrupt Sharing Sequence . . . . . . . . . . . . . . . . . . . . . Overview of the Basic-Transfer Cycle . . . . . . . . . . . . . . . Default I/O and Memory Cycle (200 Nanoseconds Minimum) Default Cycle Return Signals (200 Nanoseconds Minimum) Timing Sequence for the Synchronous Special Case of Extended Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous-Extended Cycle (300 Nanoseconds Minimum Special Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Sequence for the Asynchronous-Extended Cycle (General Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous-Extended Cycle (~300 Nanoseconds Minimum - General Case) . . . . . . . . . . . . . . . . . . . . . . First Cycle After Grant . . . . . . . . . . . . . . . . . . . . . . . . . Single DMA Transfer (DMA Controller Controlled) ...... Burst DMA Transfer (DMA Controller Terminated) ...... Burst DMA Transfer (DMA Slave Terminated - Default Cycle 200 Nanoseconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Channel Architecture 3 6 16 17 17 18 19 20 21 25 27 28 29 31 32 33 34 35 38 41 42 43 45 47 49 51 53 55 57 III 30. 31. 32. 33. 34. 35. Iv Burst DMA Transfer (DMA Slave Terminated Synchronous-Extended Cycle 300 Nanoseconds) ....... Burst DMA Transfer (DMA Slave TerminatedAsynchronous-Extended Cycle ~300 Nanoseconds) ..... Arbitration Cycle ..... . . . . . . . . . . . . . . . . . . . . . . .. Setup Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Channel Timings ..................... Auxiliary Video Connector Timing (DAC Signals) ....... Micro Channel Architecture 59 61 63 65 66 67 Description The Micro Channel architecture consists of an address bus, a data bus, a transfer control bus, an arbitration bus, and multiple support signals. It uses synchronous and asynchronous procedures for control and data transfer between memory, 1/0 devices, and the controlling master. The controlling master can be a DMA controller, the system microprocessor, or a bus master. See "Bus Ownership" on page 23 for more information about controlling masters. The following are characteristics of the Micro Channel architecture: • An 1/0 address width of 16 bits allows 8-, 16-, or 32-bit 1/0 transfers within a 64KB range. A memory address width of 24 and 32 bits allows 8-, 16-,24-, or 32-bit memory transfers within 16MB and 4GB ranges respectively (KB equals 1024 bytes; MB equals 1,048,576 bytes; GB equals 1,073,741,824 bytes). • Support of a central arbitration control point that enables up to 15 devices and the system microprocessor to arbitrate for control of the channel. • A direct memory access (DMA) procedure that supports multiple DMA channels with burst capability. • Level-sensitive interrupts with interrupt sharing on all levels. • Programmable Option Select (POS) registers that replace hardware jumpers and switches. These registers allow flexibility during system configuration. • Channel connector extensions that support the growth of additional channel features. • Improved electromagnetic compatibility. • Error reporting. Micro Channel Architecture 1 Channel Definition The channel provides all signal, power, and ground signals to adapters through 50-mil channel connectors. The channel provides two basic types of connectors: • 16-bit, which support 8- and 16-bit operations • 32-bit, which support 8-, 16-,24-, and 32-bit operations. Pins 01 through 45 support 8-bit operations. Pins 46 and 47 are keys. Pins 48 through 58 provide additional power and signals to support 16-bit operations. Pins 59 through 89 are used with pins 01 through 58 to support 32-bit operations and are only present on systems with a 32-bit system microprocessor. Side A of each connector is offset from side B by 2 pins, and every fourth pin on either side of each connector is at ac ground. This places each signal within 2.54 millimeters (0.1 inch) of a ground and minimizes current loop electromagnetic interference (EMI). The 50-mil connector reduces the required insertion force and matches the line spacing of surface mount technology. Extensions to the basic 16- and 32-bit connectors are implemented on a system-by-system basis. Refer to the system-specific technical references for additions to or deviations from the information presented in this section. Note: Adapter designs should not extend the card-edge connector beyond the basic 16- or 32-bit connector unless the signals provided by the extension are used by the adapter. Adapters for the Micro Channel architecture have special design criteria. See "Micro Channel Adapter Design." 2 Micro Channel Architecture, Channel Definition The following is a diagram of the two basic types of channel connectors with optional extensions. Video Extension (Optional) ------l[ fVW1 M4 ~ } M1 01 01 B-Bit Section B-Bit Section 45 16-Bit Section 16-B' Co,"",,>< w'" Matched Memory Extension (Optional) 45 -{ [:J Vldoo E>de",~" J 32-Bit Connector with Matched Memory 48 56 J- 16-Bit Section 59 32-Bit Section • 89 Figure 1. Micro Channel Connectors Warning: Any signals shown or described as "Reserved" should not be driven or received. These signals are reserved to allow compatibility with future implementations of the channel interface. Serious compatibility problems, loss of data, or permanent damage can result to features or the system if these signals are misused. Micro Channel Architecture, Channel Definition 3 Signal Descriptions (16-Bit) All of the logic signal lines are transistor-transistor logic (TTL) compatible. The following are the signals available on the channel. Timing information for the signals begins on page 36. Reserved: Any signals shown or described as "Reserved" should not be driven or received. These signals are reserved to allow compatibility with future implementations of the channel interface. Serious compatibility problems, loss of data, or permanent damage can result to features or the system if these signals are misused. AO - A23: Address Bits 0 through 23: These lines are used to address memory and I/O slaves attached to the channel. AO is the least-significant bit (LSB) and A23 is the most-significant bit (MSB). These 24 address lines allow access of up to 16MB of memory. Only the lower 16 address lines (AO - A15) are for I/O operations, and all 16 lines must be decoded by the I/O slave. AO through A23 are generated by the controlling master. Valid addresses generated by the controlling master are unlatched on the channel and, if required, must be latched by the slaves using either the leading or trailing edge of the '-address decode latch' signal (-AOL) or the leading edge of the 'command' signal (-CMO). AO through A23 must be driven with tri-state drivers. DO - D15: Data Bits 0 through 15: These lines provide data bus bits o through 7 (low byte) and 8 through 15 (high byte) for the controlling master and slaves. DO is the LSB and 015 the MSB. All 8-bit slaves on the channel must use DO through 07 to communicate with the controlling master. During read cycles, data is valid on these lines after the leading edge but before the trailing edge of -CMO, and must remain valid until after the trailing edge of -CMO. However, during write cycles, data is valid as long as -CMO is active. DO through 015 must be driven with tri-state drivers. -ADL: -Address Decode Latch: This line, driven by the controlling master, is provided as a convenient way for the slave to latch valid addresses and status bits. This signal can be used by slaves to latch the address from the bus. -AOL is not active during matched-memory cycles. -AOL is driven with a tri-state driver. 4 Micro Channel Architecture, Channel Definition -CD DS 16 (n): -Card Data Size 16: This line is driven by 16-bit and 32-bit memory, 110, or DMA slaves to provide an indication on the channel of a 16-bit or 32-bit data port at the location addressed. The (n) indicates this signal line is unique to each channel connector (one independent signal line per connector). This signal is unlatched and derived as a valid address decode. All system logic receives this signal to support communication with 16- and 32-bit slaves. -co os 16 is not driven by 8-bit slaves. All 16- and 32-bit slaves must drive this signal. -co os 16 is driven with a totem-pole driver. -DS 16 RTN: -Data Size 16 Return: This output signal is a negative OR of the -co os 16 signal from each channel connector. If any device drives its -co os 16 active, this output is active. This signal is provided to allow the controlling master to monitor the data size information. -os 16 RTN must be driven with a bus driver. -SBHE: -System Byte High Enable: This line indicates and enables transfer of data on the high byte of the data bus (08 - 015), and is used with AO to distinguish between high-byte transfers (08 - 015) and low-byte transfers (~o - 07). All 16-bit slaves decode this line, but 8-bit slaves do not. -SBHE is driven with a tri-state driver. MADE 24: Memory Address Enable 24: This line indicates when an extended address is used on the bus. If a memory cycle is in progress and MADE 24 is inactive, an extended address greater than 16MB is being presented; if MADE 24 is active, an unextended address less than or equal to 16MB is being presented. This line is driven by the controlling master and decoded by all memory slaves, regardless of their address space size. MADE 24 is driven with a tri-state driver. M/-IO: Memory/-Input Output: This signal distinguishes a memory cycle from an I/O cycle. When this signal is high, a memory cycle is in progress. When M/-IO is low, an 110 cycle is in progress. M/-IO is driven with a tri-state driver. -so, -S1: -Status Bits 0 and 1: These Ii nes indicate the start of a channel cycle and also define the type of channel cycle. When used with M/-IO, memory read/write operations are distinguished from 110 read/write operations. These signals are latched by the slave, as required, using the leading edge of -CMO or the trailing edge of -AOL. -so and -Sl are driven with a tri-state driver. Micro Channel Architecture, Channel Definition 5 Data is moved to or from the bus based on -CMD and a latched decode of the address, the status lines (-so exclusive or -S1), and M/-IO. Slaves must support a full decode of -so and -S1. The following figure shows the proper states of M/-IO, -so, and -S1 in decoding 110 and memory readlwrite commands. -so -S1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 M/-IO 1 0 1 1 Function Reserved I/O Write Command I/O Read Command Reserved Reserved Memory Write Command Memory Read Command Reserved Figure 2. 110 and Memory Transfer Controls An 110 Write command instructs an 110 slave to store the data on the data bus. The data must be valid on the bus from the leading edge of -CMD and must be held on the bus until after -CMD goes inactive. Addresses on the bus must be valid before -so goes active. An 110 Read command instructs an 110 slave to drive its data onto the data bus. The data must be placed on the bus following the leading edge of -CMD, must be valid before the trailing edge of -CMD, and must be held on the bus until -CMD goes inactive. Addresses on the bus must be valid before -S1 goes active. A memory Write command instructs the memory to read the data on the data bus. The data must be valid on the bus from the leading edge of -CMD and must be held on the bus until after -CMD goes inactive. Addresses on the bus must be valid before -so goes active. A memory Read command instructs the memory to drive its data onto the data bus. The data must be placed on the bus followtng, the leading edge of -CMD. The data must be valid before the trailing edge of -CMD, and must be held on the bus until -CMD goes inactive. Addresses on the bus must be valid before -S1 goes active. 6 Micro Channel Architecture, Channel Definition -CMD: -Command: This signal is used to define when data is valid on the data bus. The trailing edge of this signal indicates the end of the bus cycle. This signal indicates to the slave how long data is valid on the bus. During write operations, the data is valid on the bus as long as -CMD is active. During read operations, the data is valid on the bus between the leading and trailing edges of -CMD, and must be held on the bus until after -CMD goes inactive. This signal can be used by the slaves to latch the address on the bus. Latched status lines gated by -CMD provide the timing control of valid data. Slaves should use transparent latches to latch address and status information with the leading edge of -CMD. -CMD is not active during matched-memory cycles. It must be driven with a tri-state driver. -CD SFDBK (n): -Card Selected Feedback: When the controlling master addresses a memory slave or an 1/0 slave, the addressed slave drives -CD SFDBK active as a positive acknowledgment of its presence at the address specified. The (n) indicates this signal line is unique to each channel connector (one independent signal line per connector). This signal is unlatched by any slave with a valid select decode, and is driven by any slave selected by any select mechanism except -CD SETUP. The slave does not drive -CD SFDBK during the configuration cycle. -CD SFDBK is driven with a totem-pole driver. Note: Memory supporting diagnostic software must not drive -CD SFDBK during the diagnostic operation. CD CHRDY (n): Channel Ready: This line, normally active (ready), is pulled inactive (not ready) by a memory or 1/0 slave to allow additional time to complete a channel operation. The (n) indicates this signal line is unique to each channel connector (one independent signal line per connector). During a read operation, a slave ensures that data will be valid on the data bus within the time specified after releasing the line to a ready state. The slave also holds the data long enough for the controlling master to sample. A slave may also use this line during a write operation if more time is needed to store the data from the bus. This Signal is derived with a valid address decode ANDed with status. CD CHRDY is driven with a totem-pole driver. CHRDYRTN: Channel Ready Return: This output signal is a positive AND of the CD CHRDY signals. If all devices drive CD CHRDY active, this output is active. It is provided to allow the controlling master to monitor the ready information. CHRDYRTN must be driven with a bus driver. Micro Channel Architecture, Channel Definition 7 ARBO - ARB3: Arbitration Bus Priority Levels: These lines comprise the arbitration bus and are used to present priority levels for participants seeking control of the bus. ARBO through ARB3, the least-significant through most-significant bits respectively, support up to 16 priority levels. The highest hexadecimal value of the arbitration bus (hex F) has the lowest priority, and the lowest value (hex 0) has the highest priority. A participant is allowed to change the state of the arbitration bus only immediately after the rising edge of ARB/-GNT. All participants monitor the arbitration bus and the lower priority participants withdraw their priority levels by not activating less-significant arbitration bits. The hexadecimal code of the highest priority requester is valid on the arbitration bus after a settling time. After the channel is granted to a requester, the highest priority participant continues to drive its priority lines. These bidirectional lines are active high and must be driven with open collector drivers. ARB/-GNT: Arbitrate/-Grant: When high, this signal indicates an arbitration cycle is in process. When low, it is the acknowledgment from the central arbitration control point to an arbitrating bus participant (local arbiter) and the DMA controller that channel control has been granted. This signal is driven high by the central arbitration control point within a specified time after-so, -51, -BURST, and -CMD become inactive. The negative-to-positive transition of ARB/-GNT initiates an arbitration cycle; the positive-to-negative transition terminates the arbitration cycle. Only the central arbitration control pOint activates and deactivates this line. This signal must be used by all local arbiters to gate their address data and transfer control bus drivers off during arbitration cycles. ARB/-GNT is driven with a bus driver. -PREEMPT: -Preempt: This signal is used by arbitrating bus participants (local arbiters) to request use of the channel through arbitration. Any local arbiter with a channel request activates -PREEMPT and causes an arbitration cycle to occur. A local arbiter removes its -PREEMPT upon being granted the channel. This bidirectional line must be driven with an open collector driver. 8 Micro Channel Architecture, Channel Definition -BURST: -Burst: This signal indicates to the central arbitration control pOint the extended use of the channel for transferring a block of data. This type of data transfer is called a burst cycle. This line is shared by all local arbiters. -BURST is driven active by the local arbiter after being granted the channel. The local arbiter must deactivate -BURST during the last transfer cycle. -BURST must be driven with an open collector driver. -TC: -Terminal Count: This line provides a pulse during a Read or Write command to indicate that the terminal count of the current DMA channel has been reached. This indicates to the DMA slave the last cycle to be performed of a preprogrammed DMA block transfer. -TC is available on the channel only during DMA operations. It is driven with a tri-state driver by the DMA controller. -IRQ 3-7, -IRQ 9-12, and -IRQ 14-15: -Interrupt Request: These lines are used to signal that a device requires attention. They are prioritized with -IRQ 9 having the highest priority and -IRQ 7 having the lowest priority. The effective interrupt priority sequence is -IRQ (9-12,14,15,3-7). An interrupt request is generated when a slave drives one of the 'interrupt request' signals low. The polarity of 'interrupt request' signals makes it possible for multiple slaves to share the same interrupt level. This is called interrupt sharing. These lines must be driven with an open collector driver. -CD SETUP (n): -Card Setup: This signal is driven by system logic to individually select channel connectors during system configuration and error-recovery procedures. The (n) indicates this signal line is unique to each channel connector (one independent signal line per connector). When this signal is activated, a specific channel connector is selected and access to the adapter's configuration data space is obtained. The ID and configuration data can be obtained by an 110 read operation; the configuration data is stored by an 110 write operation. Each channel connector has a unique -CD SETUP. This line is driven with a totem-pole driver. -CHCK: -Channel Check: This line is used to indicate a serious error (such as a parity error) that threatens continued operation of the system. -CHCK is driven active to indicate the error condition and must remain active until the -CHCK interrupt handler resets it. -CHCK is driven with an open collector driver to allow sharing. Micro Channel Architecture, Channel Definition 9 AUDIO: Audio Sum Node: This line is an audio voltage sum node. It is used to drive audio signals from an adapter to the system audio output, or to transfer audio signals between adapters. The frequency response of the audio line is 50 Hz to 10 kHz ± 3 dB. The maximum signal amplitude is 2.5 Vac peak-to-peak, at a dc offset of 0 ± 50 millivolts. The noise level is limited to a maximum of 50 millivolts peak-to-peak. AUDIO GND: Audio Ground: This is a separate ground return for the audio subsystem. OSC: Oscillator: This line is a high-speed clock with a frequency of 14.31818 MHz ± 0.01 %. The high-level pulse width (more than 2.3 Vdc) and the low-level pulse width (less than 0.8 Vdc) must not be less than 20 nanoseconds each. CHRESET: Channel Reset: This signal is generated by the system logic to reset or initialize all adapters at power on or during a low line voltage condition. During a power-on sequence, CHRESET is active for a specified minimum time. The system can also activate this signal under program control. CHRESET is driven with a bus driver. -REFRESH: -Refresh: This line is driven by the system logic and is used to indicate that a memory refresh operation is in progress. While this line is active, a memory read operation occurs. The address lines contain the memory locations being refreshed. Nine lines, AO through A8, are activated. -REFRESH timing may be inconsistent and must not be used as a timing mechanism. -REFRESH is driven with a tri-state driver. 10 Micro Channel Architecture, Channel Definition Signal Descriptions (32-Bit) A24 - A31: Address Bits 24 through 31: These lines are used with AO through A23 to address memory attached to the channel. AO is the LSB and A31 is the MSB. These 32 address lines allow access of up to 4GB of memory. Only the lower 16 address lines (AO through A15) are used for I/O operations. A24 through A31 are generated by the controlling master. Valid addresses generated by the controlling master are unlatched on the channel and, if required, must be latched by the slaves using either the leading or trailing edge of -AOL or the leading edge of -CMO. AO through A31 must be driven with tri-state drivers. -BEO - -BE3: -Byte Enable 0 through 3: These lines are used during data transfers with 32-bit slaves to indicate which data bytes will be placed on the bus. Data transfers of 8, 16,24, or 32 contiguous bits are controlled by -BEO through -BE3 during transfers involving 32-bit slaves only. These lines are driven by the controlling master when TR 32 is inactive, and by the Central Translator Logic (for those operations involving a 16-bit master with a 32-bit slave) when TR 32 is active. These lines are unlatched on the bus and, if required, must be latched by 32-bit slaves. -BEO through -BE3 are driven with tri-state drivers. 016 - 031: Data Bits 16 through 31: These lines are used with 00 through 015 to provide data-bus bits to the controlling master and slaves. 00 is the LSB and 031 the MSB. All 32-bit transfers from the controlling master to 8-bit slaves are converted to four 8-bit transfers, and all are transmitted on lines 00 through 07. All 32-bit transfers from the controlling master to 16-bit slaves are converted to two 16-bit transfers, and all are transmitted on lines 00 through 015. During read cycles, data is valid on these lines after the leading edge of -CMO but before the trailing edge of-cMo. However, during write cycles, data is valid as long as -CMO is active. 00 through 031 must be driven with tri-state drivers. -co OS 32 (n): -Card Data Size 32: This line is driven by 32-bit slaves to provide an indication on the bus of a 32-bit data port at the location addressed. The (n) indicates this signal line is unique to a channel connector position (one independent signal per connector). -co os 32 is unlatched and derived from a valid address decode. All 32-bit Micro Channel Architecture, Channel Definition 11 slaves must drive this signal. -CO OS 32 is inactive for an 8- or 16-bit data port. -CD OS 32 must be driven with a totem-pole driver. -DS 32 RTN: -Data Size 32 Return: This output signal is a negative OR of the -CD OS 32 signal from each channel connector. If any device drives its -CD OS 32 active, then this output is active. This signal is provided to allow controlling masters to monitor data size information. -os 32 RTN must be driven with a bus driver. TR 32: Translate 32: This line is driven inactive by 32-bit controlling masters and received by the Central Translator Logic. TR 32 can also be received by any 32-bit slave. When TR 32 is inactive, a 32-bit controlling master drives -BED through -BE3. When TR 32 is active, the Central Translator Logic drives -BED through -BE3. TR 32 must be driven by a tri-state driver. See "Channel Support" on page 32 for more information about Central Translator Logic. Signal Descriptions (Matched-Memory) Matched memory is a function that allows enhanced data transfer capabilities between the system microprocessor and its channel-resident memory. Matched memory is not supported by all systems. The following signal definitions are system specific and may not apply to all systems that support matched-memory cycles. For more information, refer to the system-specific technical reference for the system you are dealing with. -MMC: -Matched Memory Cycle: This signal is driven by the system logic to indicate to the channel slaves that the system microprocessor is the controlling master and is able to run a matched-memory cycle. -MMCR: -Matched Memory Cycle Request: This is a bus cycle control-input signal. -MMCR is driven by a 16- or 32-bit channel slave to request the faster cycle available on the system bus. -MMC CMD: -Matched Memory Cycle Command: This output signal to the bus is generated for system microprocessor bus cycles only. -MMC CMO defines when data is valid on the bus during a matched-memory cycle. Note: Adapter designs should not extend the card-edge connector beyond the basic 16- or 32-bit connector unless the signals provided by the extension are used by the adapter. Adapters 12 Micro Channel Architecture, Channel Definition for the Micro Channel architecture have special design criteria. See "Micro Channel Adapter Design." Signal Descriptions (Auxiliary Video Extension) The following are signal descriptions for the auxiliary video extension of the channel connector. VSYNC: Vertical Synchronization: This signal is the vertical synchronization signal to the display. See also the ESYNC description. HSYNC: Horizontal Synchronization: This signal is the horizontal synchronization signal to the display. See also the ESYNC description. BLANK: Blanking Signal: This signal is connected to the BLANK input of the video digital-to-analog converter (DAC). When active (0 Vdc), this signal tells the DAC to drive its analog color outputs to 0 Vdc. See also the ESYNC description. PO - P7: Palette Bits: These eight signals contain video information and comprise the picture element (PEL) address inputs to the video DAC. See also the EVIDEO description. DCLK: Dot Clock: This signal is the PEL clock used by the DAC to latch the digital video signals, P7 through po. The signals are latched into the DAC on the rising edge of DCLK. This signal is driven through the EXTCLK input to the system board video when DCLK is driven by the adapter. If an adapter is providing the clock, it must also provide the video data to the DAC. See the EDCLK description. ESYNC: External Synchronization: This signal is the output-enable signal for the buffer that drives BLANK, VSYNC, and HSYNC. ESYNC is tied to +5 Vdc through a pull-up resistor. When ESYNC is high, the system board video drives BLANK, VSYNC, and HSYNC. When ESYNC is pulled low, the adapter drives BLANK,VSYNC, and HSYNC. Micro Channel Architecture, Channel Definition 13 EVIDEO: External Video: This signal is the output-enable signal for the buffer that drives P7 through PO. EVIDEO is tied to + 5 Vdc through a pull-up resistor. When EVIDEO is high, the system board video drives P7 through PO. When it is pulled low, the adapter drives P7 through po. EDCLK: External Dot Clock: This signal is the output-enable signal for the buffer that drives DCLK. EDCLK is tied to +5 Vdc through a pull-up resistor. When EDCLK is high, the system board video is the source of DCLK to the DAC and the adapter. When EDCLK is pulled low, the adapter drives DCLK. See "Video Subsystem" for more information. 14 Micro Channel Architecture, Channel Definition Micro Channel Connector (16-Bit) The 16-bit Micro Channel connector has two sections: • An 8-bit section • A 16-bit section. A key between the two sections is provided for mechanical alignment. The following figures show the signals and voltages assigned to the 16-bit channel connector. Micro Channel Architecture, Micro Channel Connectors 15 Rear of the System Board B AUDIOGND - AUDIO GND14.3 MHzOSC GNDA23 A22 A21 GNDA20 A 19 A 18 GNDA17 A 16 A 15 GNDA 14 A 13 A 12 GND-IRQ 09 -IRQ 03 -IRQ 04 GND-IRQ 05 -IRQ 06 -IRQ 07 GNDReserved Reserved -CHCK GND-CMD CHRDY RTN -CD SF DBK GNDDOl D03 D04 GNDCHRE SET Reserved Reserved OS 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 GNDKEY A 01 02 03 04 05 06 07 -CD SETUP MADE 24 I - - - GND All A 10 A09 r---- AOS A07 AOS r - - +5Vdc A05 A04 A03 ;--- +5Vdc A02 AOl AOO ;--- +12Vdc -ADL -PREEMPT -BURST ' - - - -12Vdc ARB 00 ARB 01 ARB 02 '"-- -12Vdc ARB 03 ARB/-GNT -TC r-- +5Vdc -so -Sl M/-IO r-- +12Vdc CDCHRDY DOO D02 r---- +5Vdc D05 DOS D07 r-- GND -DS 16 RTN -REFRESH KEY 45 46 ~ +5Vdc v Figure 3. Channel Connector Voltage and Signal Assignments (a-Bit Section) 16 Micro Channel Architecture, Micro Channel Connectors The following are the signals and voltages assigned to the channel connector 16-bit section. Rear of the System Board ~ KEY 008 009 48 GNO- 012 014 015 GNO-IRQ 10 -IRQ 11 -IRQ 12 GNOB 49 50 51 52 53 54 55 56 57 KEY - +5Vdc 010 011 013 - +12Vdc Reserved -SBHE -CO OS 16 - +5Vdc -IRQ 14 -IRQ 15 58 A Figure 4. Channel Connector Voltage and Signal Assignments (16-Bit Section) Micro Channel Connector (Auxiliary Video Extension) This extension to the Micro Channel connector accommodates video adapters that interface with the system-board video subsystem. Rear of the System Board B ESYNC GNOP5 P4 P3 GNO- P2 P1 PO GNO- A V10 V9 V8 I - - - GNO V7 V6 V5 V4 I - - GNO V3 V2 V1 KEY VSYNC HSYNC BLANK P6 EOCLK OCLK P7 EVIOEO ~ Channel Connector Figure 5. Auxiliary Video Extension Micro Channel Architecture, Micro Channel Connectors 17 Micro Channel Connector (32-Bit Section) This connector extends the 16-bit Micro Channel connector to accommodate 32-bit addressing and 32-bit data transfers. Rear of the System Board ~ Reserved Reserved Reserved Reserved 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 GND D 16 D17 D 18 GND D22 D23 Reserved GND D27 D28 D 29 GND -BE 0 -BE 1 -BE 2 77 GND - TR32 A24 A25 GND A29 A30 A31 GNDReserved Reserved B 78 79 80 81 82 83 84 85 86 87 88 89 Reserved Reserved -GND Reserved Reserved Reserved - +12Vdc D 19 D20 D 21 - +5 Vdc D24 D25 D26 - +5 Vdc D30 D31 Reserved - +12Vdc -BE3 -DS 32 RTN -CD DS 32 - +5 Vdc A26 A27 A28 - +5 Vdc Reserved Reserved Reserved -GND A Figure 6. Channel Connector Voltage and Signal Assignments (32-Bit Section) 18 Micro Channel Architecture, Micro Channel Connectors Micro Channel Connector (Matched-Memory Extension) This extension provides additional signals to accommodate matched-memory cycles. The following figure shows a connector with a typical set of matched-memory signals. Refer to the system-specific technical reference for the system you are dealing with for further information. Rear of the System Board B GND Reserved -MMCR Reserved A M4 M3 M2 M1 01 02 03 Reserved -MMCCMD GND -MMC ~ Channel Connector Figure 7. Channel Connector Voltage and Signal Assignments (Matched-Memory Extension) Channel Signal Groups (16-Bit, 32-Bit, and Matched-Memory) The following figure lists digital 16-bit, 32-bit, and matched-memory Micro Channel signals and shows what type of driver or receiver is required to be compatible with the system board. The 'audio' and 'audio ground' signals are analog signals; for further information about these signals refer to page 10. Micro Channel Architecture, Micro Channel Connectors 19 Signal Name Sys DMA Bus Logic enllr Master DMA MEM 1/0 Driver Slave Slave Slave Type A(0-23) 0(0-15) -ADL -CD OS 16 (n) -OS 16 RTN -SBHE MADE 24 M/-IO -SO,-S1 -CMD -CD SFDBK (n) CD CHRDY (n) CHRDYRTN ARB(0-3) -BURST -PREEMPT ARB/-GNT -TC -IRQ (*) -CD SETUP (n) -CHCK -REFRESH OSC CHRESET A(24-31) -BE(Q-3) 0(16-31) -CD OS 32 (n) -OS 32 RTN TR32 -MMC -MMCR -MMCCMD D/R 0/D/R 0/-/R 0/0/0/0/0/0/-/R O/R 0/O/R O/R O/R 0/-/-/R 0/-/R D/R 0/0/0/0/D/R -/R 0/-/0/-/R 0/- D/R -/R D/R -/0 #/-/-/# -/-/R -/R -/R 0/0/-/D/R #/0/# -/R -/0 0/-/R 0/-/0 -/0 -/R -/R -/R D/R #/-/-/-/-/-/- D/R -/R D/R -/0 #/-/-/# -/R -/R -/R -/R 0/0/-/-/-/-/-/-/-/-/R 0/-/R -/0 -/R -/R -/R D/R #/-/0/-/0 0/-/0 OC = TS =; TP = BD = CD = Open Collector Tri-State Totem-Pole Bus Driver Clock Driver o= D/R 0/D/R 0/-/R -/R 0/0/0/0/0/-/-/-/R -/R D/R -/-/R 0/0/-/# #/-/0 -/0 -/0 0/0/D/R -/R -/-/-/-/-/- D/R 0/D/R 0/-/R -/R 0/0/0/0/0/-/-/-/R D/R 0/D/R -/R -/0/-/R 0/0 -/0 -/0 -/R 0/0/D/R -/R -/0 -/0 -/-/-/- D/R -/R D/R -/0 #/-/-/# -/-/R -/R -/R 0/0/-/-/-/-/-/-/0/-/R 0/-/0 -/0 -/R -/R -/R D/R #/-/- 0/-/0 0/-/0 Signal Group TS (1) TS (2) TS (1) TP (3) BD (4) TS (1) TS (1) TS (1) TS (1) TS (1) TP (3) TP (3) BD (4) OC (5) OC (5) OC (5) BD (4) TS (1) OC (6) TP (7) OC (6) TS (1) CD (7) BD (4) TS (1) TS (1) TS (2) TP (3) BD (4) TS (1) ** ** ** KEY Drive Enabled 0= Optional R = Receive Enabled - = Not Implemented # = Some are Required * IRQ (9-12, 14, 15, 3-7) ** See the system-specific technical references for more information. Figure 8. Driver/Receiver Requirements and Options 20 Micro Channel Architecture, Micro Channel Connectors The following figure describes the signal driver types. Signal Group 1,2 3 4 5,6 7 Driver Type Tri-state (TS) with 24 mA sinking capacity. Totem-pole (TP) with current sinking capacity of 6 mAo Bus driver (BD) with current sinking capacity of 24 mAo Open collector (OC) with 24 mA sinking capacity. Unique drivers: Totem-pole (TP) or Tri-state (TS) with current sinking capacity of 6 mAo Clock driver (CD) with 24 mA sinking capacity. Figure 9. Signal Driver Types The following notes apply to the driver and receiver options listed on page 20. Notes: 1. During the Reset state, an active CHRESET must degate all bus drivers. 2. During the Reset state, the state of all signals is unknown. 3. -CD SETUP is driven to only one channel connector at a time. 4. All pull-up resistors are provided by the system logic and pulled up to +5 Vdc. 5. Loading Current: A maximum of 1.6 milliamperes per channel connector, except signal group 5. The maximum loading current of group 5 is 1.0 milliamperes per channel connector. 6. Loading Capacitance (average capacitance across a 0.1- to 2.3-volt interval): • 15 pF maximum permitted for adapter for osc and Group 5 signals (see Figure 9 for Group 5 definition) and 20 pF maximum permitted for adapter for all other signals. (The value refers to the capacitance from the adapter side of the connector to the adapter driver/receiver.) • Total capacitance seen by the driver is 200 pF maximum for Group 5 signals and osc, and 240 pF maximum for all other signals. Micro Channel Architecture, Micro Channel Connectors 21 7. An open collector can be either an open-collector device or a tri-state device wired with the input grounded and using the 'enable' line to control the output. 8. The electromagnetic interference (EMI) potential of a bus driver increases as the transition time of its voltage decreases. Therefore, the drivers with output transitions greater than 1 Vdc per nanosecond should be used only to meet channel timing requirements. The figure on page 20 lists the role of the driver or receiver while a given operation is being performed. The names of the physical packaging of the logic should not be confused with the performed functions. Channel Signal Groups (Auxiliary Video Extension) An adapter using the auxiliary video extension must not exceed the following loading limits for any auxiliary video-extension signal pin it is receiving: • C max = 15.0 pF • IlL min = -1.6 mA • IIH max = 50.0 pA An adapter using the auxiliary video extension must meet the following minimum requirements for any auxiliary video-extension signal pin it is driving: • C min = 150.0 pF • 10L min = 10.0 mA - VSYNC and HSYNC = 2.0 mA - All other signals • 10H max 22 = -4.0 mA - VSYNC and HSYNC = -0.25 mA - All other signals. Micro Channel Architecture, Micro Channel Connectors Bus Ownership Bus ownership is controlled by the central arbitration control pOint based on prioritized arbitration of up to 16 devices. These arbitrating devices can be DMA slaves, bus masters, or the system microprocessor. If either a bus master or the system microprocessor wins the arbitration, it owns the bus and becomes the controlling master. If a DMA slave wins the arbitration, the supporting DMA controller owns the bus and becomes the controlling master. An adapter can incorporate either a master function, a slave function, or a combination of both. For example, an adapter might be designed to operate primarily as a DMA slave. However, it would probably also respond to certain 110 read and lID write operations from the system microprocessor, making it an lID slave. If the adapter contained RAM or ROM that was in the system microprocessor address space, it would be a memory slave when that memory was accessed. Typically, a slave is selected by a decode of: • An address • Status (-80 exclusive or -81) • MADE 24 (if it is a memory slave) • M/-IO. The decode is latched at the leading or trailing edge of -ADL or the leading edge of -CMD. A DMA slave can also be selected by a latched decode of the same signals, using the arbitration level in place of the address. Central Arbitration Control Point The central arbitration control point (central arbiter) gives devices on the channel the ability to share and control the system. It allows burst data transfers and prioritization of control between devices. This central arbiter supports up to 16 devices, such as a DMA slave, a bus master, and the system microprocessor Note: Information about programming the central arbitration control point can be found in the system-specific technical references. Micro Channel Architecture, Arbitration 23 The central arbiter uses seven signals to coordinate arbitration for all devices from a single arbitration point on the system board. These signals are -PREEMPT, ARB/-GNT, -BURST, and ARBO through ARB3. Arbitrating devices (local arbiters) requesting use of the system channel, drive -PREEMPT active. The central arbiter initiates an arbitration cycle when the present device releases the channel. The central arbiter indicates an arbitration cycle by driving ARB/-GNT to the arbitrate state. The requesting local arbiters then drive their assigned 4-bit arbitration level onto the arbitration bus. When an arbitrating device sees a more significant bit low (inactive) on the arbitration bus than those driven low by itself, it stops driving its lower-order bits onto the arbitration bus. The arbitrating device driving the lowest arbitration level thereby wins control of the channel when ARB/-GNT goes to the grant state. Arbitrating devices with multiple transfers to perform must signal the central arbiter by driving -BURST active until all transfers have been completed or until another device drives -PREEMPT active, in which case further transfers are postponed until the device wins the system channel again. Because -PREEMPT and ARBO through ARB3 may be driven by multiple devices, they must be driven through an open collector driver. ARB/-GNT is driven by the central arbiter only. The central arbiter recognizes an end-of-transfer when both status signals (-so and -51), -BURST, and -CMD are inactive. Control of the channel is then transferred to the next higher priority device or to the system microprocessor by default. 24 Micro Channel Architecture, Arbitration The interaction between the central arbitration control point and the local arbiters is called distributed arbitration. The following is a block diagram of distributed arbitration. ~ ARB/-GNT Central Arbitration Point L A R B IB TU RS A T I Level X Local Arbiter o N -PREEMPT ~ LevelY Local Arbiter -BURST I Iflrbitrati~n BUS ARB 0-3 A R B ~MA Controll[2 Da~Add' BU~ l ~US ~ o LevelZ Local Arbiter 1 2 3 Transfer Controls Figure 10. Distributed Arbitration Block Diagram Local Arbiters Devices requesting the use of the channel must implement logic to drive the arbitration bus in a way that allows all competing devices to recognize the winner. This logic is known as a local arbiter. An arbitrating device should compete for control of the channel only if it has driven -PREEMPT active, and ARB/-GNT has subsequently gone to the arbitrate state. A competing local arbiter drives its arbitration level onto the arbitration bus, then compares, on a bit-by-bit basis, its arbitration level with the value appearing on the arbitration bus beginning with the most significant bit, ARB3. If the competing local arbiter detects a mismatch on one of the bits, it should immediately cease driving all lower-order bits. If the local arbiter subsequently Micro Channel Architecture, Arbitration 25 recognizes a match on that bit, it may continue driving lower-order bits until another mismatch is detected. Because the arbitration bus is driven by open-collector drivers, multiple arbiters can safely drive the bus. The following is an example of bus arbitration. 1. Two devices with arbitration levels 1010 and 0101 (hex A and 5) compete for the channel. Both devices drive their arbitration levels on the bus, which now appears as 0000. 2. The first device (1010) detects a mismatch on ARB3 and stops driving all lower-order arbitration bus bits (ARB2 and ARBO in this case). 3. The second device (0101) detects a mismatch on ARB2 and stops driving the lower-order arbitration bit (ARB1, in this case). The arbitration bus now shows 0111. 4. The second device now sees a match on ARB2 and resumes driving ARBl of the arbitration bus. 5. The arbitration bus now shows a value of 0101, and the second device wins control of the channel. 26 Micro Channel Architecture, Arbitration The following is a simplified example of a local arbiter. + COMPETE LATCH A +3 +ARB3 I N s s V i 9 n e d +ARB2 +2 I N V A r b AND +ARB1 +1 r I N V a t o n AND +0 I N +ARBO V L e v e ~--lAND I +ARB/-GNT + BUS WON I N V • Open-Collector Driven Figure 11. Local Arbiter Example Micro Channel Architecture, Arbitration 27 Burst Mode One of the most efficient ways for a device, such as a fixed disk drive, to transfer data is in bursts. These bursts are often separated by long inactive periods. The burst mode makes these devices more efficient. To use the burst mode, the local arbiter activates -BURST and does not release it until after the leading edge of the last -CMD pulse in the burst sequence. The following diagram shows a burst operation without interference. ARB/-GNT n ------------~ Arbitration Bus ARB 0,1,2,3 ~--------~ 1flL..---_ _ lOl'------ LflJ -CMD -BURST Figure 12. Burst Mode Timing 28 L Micro Channel Architecture, Arbitration Preemption Whenever an arbitrating device needs service, it activates -PREEMPT. The following timing diagram shows -PREEMPT occurring during a burst operation. ARB/-GNT n ----------------~ 4 Arbitration Bus Level A Local Arbiter ARB 0,1,2,3 -CMD n ~----------------~ 5 6 ~-------- Level B Local Arbiter LJlJlJ -BURST -PREEMPT 2 _-----If < - - - - I Figure 13. Preempt Timing The sequence is as follows: 1. Device A gains control of the channel. 2. Device B, nearing an overrun condition, requests preemption. 3. Device A, still in control of the channel, completes any partial transfers and removes -BURST. Device A does not participate in the next arbitration cycle if the fairness feature is active. See "Programmable Fairness and the Inactive State" on page 30. 4. When the central arbitration control point recognizes the end of transfer, it removes the grant. 5. Arbitration for channel control begins. 6. When ARB/-GNT is in the grant state, the new local arbiter gains control of the channel. 7. Device B, the preempting device, removes -PREEMPT in response to the grant. If an arbitrating device holds -BURST active for more than 7.8 microseconds after an active -PREEMPT, an error condition may exist, and a channel time-out may occur. ARB/-GNT is driven high Micro Channel Architecture, Arbitration 29 immediately and takes control of the channel from the controlling master. An NMI is driven active. The channel remains in the arbitration state under the control of the system microprocessor until released by a NMI handler. Programmable Fairness and the Inactive State A programmable fairness feature in bursting DMA slaves and bursting masters allows each device a share of the channel time. If the fairness feature is active and an arbitrating device that owns the channel is preempted, the device enters the Inactive state and must wait for an inactive -PREEMPT and an inactive (trailing) edge of status to compete for the channel again. The fairness feature allows the system to service all arbitrating devices in order of priority before the same device can gain control of the channel again. Arbitration Bus Priority Assignments The following figure identifies the arbitration level assignments that have been maintained to ensure hardware and software compatibility with existing products. The functions with the lowest arbitration level have the highest priority. 30 Micro Channel Architecture, Arbitration ARB Level Compatibility Assignment -2 -1 Memory Refresh NMI DMA Channel 0 (Programmable to any arbitration level) DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 (Programmable to any arbitration level) DMA Channel 5 DMA Channel 6 DMA Channel 7 Available Available Available Available Available Available Available System Microprocessor o 1 2 3 4 5 6 7 8 9 A B C D E F Figure 14. Arbitration Bus Priority Assignments for Compatibility DMA channels can be masked in order to install a bus master at the assignment specified for that DMA channel. Information about programming the central arbitration control point can be found in the system-specific technical references. NMI service is executed at a priority level higher than 0, called -1. Memory refresh is prioritized at -2, two levels higher than O. Levels -1 and -2 are reached on the system board only while ARB/-GNT is in the arbitrate state. When the central arbitration control point receives a level -1 request (NMI, a system-board internal signal), it may activate -PREEMPT, wait for the end of transfer, and then place ARB/-GNT in the arbitrate state, denying channel activity to arbitrating devices. The grant is then given to the level -1 request, and ARB/-GNT is held in the arbitrate state until the operation is complete and the NMI is reset. Micro Channel Architecture, Arbitration 31 Channel Support The 32-bit bus requires unique logic to permit masters with 16-bit data to communicate with slaves with 32-bit data. Address Bus Translator A 32-bit slave uses the '-byte enable' channel signals (-BED through as part of its address instead of AD and -SBHE. A 16-bit master does not provide these four '-byte enable' signals; the system generates them when a 16-bit master has control of the bus. -BE3) Data Bus Steering Eight-bit masters are not supported; however, an 8-bit microprocessor can be used as a 16-bit master if it does its own data steering of the two low-order data bytes. A 32-bit slave writes data to and reads data from data bits 0 through 31. A 16-bit master does not use data bits 16 through 31; the system board logic must cross data over from the low 16 data lines (~o through 015) to the high data lines (016 through 031) and back at the appropriate times. Compensation for the added delay is the responsibility of the 32-bit slave. AO 0 1 0 1 -SBHE 0 0 1 Description Byte 0 Only (DO - 07) Byte 1 Only (08 - 015) Byte 0 and Byte 1 (DO - 015) Invalid Figure 15. Steering Control TR 32: This signal is driven inactive by 32-bit masters only. When is active, it is used by: TR 32 • The Central Translator Logic to drive -BED through -BE3 • The Central Steering Logic to perform bus steering. 32 Micro Channel Architecture, Channel Support When TR 32 is active, 32-bit slaves can use it to recognize that the controlling master is not 32-bit and compensate for additional delay attributable to the Central Steering Logic. Central Steering Logic: Central Steering Logic uses AO, A1, -SBHE, -co os 16, and -co os 32 to steer data in support of 16-bit masters communicating with 32-bit slaves. Central Translator Logic: Central Translator Logic translates and -SBHE to -BEO through -BE3, when TR 32 is active. -BE(O-3): Signals -BEO through -BE3 AO, A1, are: • Driven by a 32-bit master that has control of the bus • Created by the Central Translator Logic when a 16-bit master has control of the bus • Used by 32-bit slaves only. The following block diagram shows the implementation of data bus steering. Channel r- AO,A1 AO,A1 Steering Control' I-- -CO OS 16/32 ,-- 1 Bus Crossover TR 32,-SBHE TR 32,-SBHE - -BE(G-3) 14-- Translator I 00-015 016-031 '-- * For 16-bit devices to 32-bit devices Figure 16. Data Bus Steering Implementation Micro Channel Architecture, Channel Support 33 Level-Sensitive Interrupt Sharing The main objectives of level-sensitive interrupt sharing are to: • • • • Simplify the logic-sharing design of adapters Reduce transient sensitivity of the interrupt controller Provide compatibility with existing software Allow for a mixture of sharing and nonsharing hardware on the same interrupt level. Each adapter designed for the Micro Channel architecture uses a level-sensitive, active-low, interface mechanism. This mechanism, an open-collector driver (or tri-state driver gated active-low), drives the interrupt request line for levels assigned for the adapter function. Note: Designers may want to limit the number of devices that share an interrupt level because of performance and latency reasons. An adapter must hold the level-sensitive interrupt active until it is reset as a result of servicing the interrupt (reset). Service routines must not issue an End of Interrupt instruction (EOI) to the interrupt controller until the interrupt line of the device being serviced is reset. All adapters must also provide an interrupt-pending latch that is readable at an 1/0 address bit position and can be reset by normal servicing of the device. Interrupting Device Addres~ Data / Control v ~ Other Device Interrupt Pending Register I Interrupt Request Open Collector Driver - Other Device Other Device -I RQx Figure 17. Typical Adapter Interrupt Sharing Implementation 34 Micro Channel Architecture, Interrupt Sharing Level-sensitive interrupts are interlocked between the hardware and software that support the interrupt service. Lost or spurious interrupts are more easily isolated. The following figure shows the sequence of interrupt sharing and the interaction of hardware and software when an interrupt is serviced by the system microprocessor. A bus master can also service interrupts in a similar manner. Interrupt requests to the interrupt controller can be masked off and the request can be serviced by a bus master. Hardware Operation Software Operation 1. An interrupt condition sets hardware interrupt line X to an active (low) level with an open-collector driver, and sets an interrupt-pending latch readable by code. 2. An interrupt controller presents the interrupt to the supporting microprocessor. 3. The supporting microprocessor begins executing code at the beginning of the appropriate chain of interrupt handlers. 4. The interrupt-handler code reads the interrupt-pending latch of the first device in the chain. If the latch is not pending, the next device in the chain is tested. When a reporting card is detected, the handler executes the appropriate service routine. 5. The interrupt service routine operates the device hardware. 6. The adapter hardware resets the interrupt-pending latch and the hardware interrupt line because of the interrupt service routine actions. 7. The interrupt service routine finishes executing code resetting the interrupt controller as its final action (End of Interrupt). 8. The interrupt controller resets. 9. If an interrupt is pending (IRQ active by another device), the interrupt controller sets immediately and the sequence starts again. Figure 18. Interrupt Sharing Sequence Micro Channel Architecture, Interrupt Sharing 35 Micro Channel Critical Timing Parameters This section provides timing diagrams for Micro Channel operations. All timings are related to a nominal cycle. The cycle may be changed by systems and adapters in various ways. Developers should ensure that hardware and software designs operate over the ranges specified and do not depend on a given performance level. Basic-Transfer Cycle This section provides the specification for critical timing parameters for the basic-transfer cycle. Simplified Basic-Transfer Cycle Most masters, including DMA controllers, transfer data with the same control sequence. Except for matched-memory transfers, the signals appear on the channel in the following sequence: 1. Address bus, MADE 24, M/-IO, and -REFRESH (if applicable) become valid, beginning the cycle. 2. The 'status' signals, SO and 51, become valid. 3. The 'address decode latch' signal (-ADL) becomes valid. A slave may latch decodes of address, status (so exclusive or 51), and M/-IO. 4. In response to an unlatched address decode, the adapter returns: • -CDSFDBK • -CD OS 16 • -CD OS 16 MADE 24, and M/-IO, (if the device is capable of 16-bit operations) and -CD OS 32 (if the device is capable of 32-bit operations). 5. In response to an unlatched address decode, MADE 24, M/-IO, and status, the adapter drives CD CHRDY inactive if the cycle is to be extended. 6. Write data appears on the bus (for the write cycle). 36 Micro Channel Architecture, Channel Timing 7. becomes active and -ADL becomes inactive. A slave must latch decodes of address, status (so exclusive or 51), and M/-IO if they were not latched at the fall of -ADL. -CMD 8. The 'status' signals become inactive. 9. The 'address' signals become invalid in preparation for the next cycle. 10. In response to an address change: • -CD 5FDBK • -CD • is set inactive by the device. os 16 is set inactive by the device. -CD os 32 is set inactive by the device. 11. If CD CHRDY has been set inactive, the system holds in this state until CD CHRDY is set active. This line should not be held inactive longer than specified. 12. The device places data on the bus in preparation for the trailing edge of -CMD (for the read cycle). 13. The address, 'status' signals, and become valid. 14. -CMD M/-IO for the next cycle may goes inactive, ending the cycle. Note: The address and status can be overlapped with the preceding cycle to minimize the memory access time impact on performance. Micro Channel Architecture, Channel Timing 37 The sequence for the basic-transfer cycle is as follows. ADDRESS M/-IO -REFRESH MADE 24 TR32 lrrrrrrri '.JJ1]] Next Cycle Y---------------------~ LLLL'L-_ __ STATUS -ADL ----++--...,--------------------------- --------,------Wait CDCHRDY State -CD OS 16/32 -CD SFDBK Write Data Valid [ from System'--__________---' '--______________________+-____~ -CMD Read Data to System _ _ _ _ _IB[ Figure 19. Overview of the Basic-Transfer Cycle 38 Micro Channel Architecture, Channel Timing 1/0 and Memory Cycle The timing diagrams for the basic 1/0 and memory cycle appear on the following pages in this sequence: • Default cycle (200 nanoseconds minimum) • Synchronous-extended cycle (300 nanoseconds minimum) Special case • Asynchronous-extended cycle General case. (~300 nanoseconds minimum) - The timing diagrams for the matched-memory cycle appear in the system-specific technical reference for those models that support matched-memory cycles. Whether a default, a synchronous-extended, or an asynchronous-extended cycle is performed depends on how a slave uses CD CHRDY. A default cycle occurs when a slave does not hold CD CHRDY inactive longer than the time specified after address valid and status active. A synchronous-extended cycle occurs when a slave releases synchronously within the specified time after the leading edge of -CMD. The slave provides the read data within a specified time from -CMD. CD CHRDY An asynchronous-extended cycle occurs when a slave releases asynchronously. However, the slave provides the read data within the specified time from CD CHRDY release. CD CHRDY Micro Channel Architecture, Channel Timing 39 Default Cycle -so, -S1 '\ "" '\'-1---' \- '----- / ~ T1~T2 "I" T10~T24----1 I-- T3 -.j...- T4 --I I---l T8 , -ADL IT5~T6~T7~ "" /7, ~~_~~ESS MADE 24 ~ ~ ~---- , -SBHE ~T11~ j--T9~ / "'----------- -BE (0-3) / I-T31-1 iT33 -CD DS 16/32 ~T13~~------'/ -CD SFDBK ~T14~~----J/ I ~TIO(CMDT~~~-~-I~E---·~ "" T:;'-=I1= T16---+!" _ ~ -CMD I WRITE DATA, DP(0-1) /-- T18 :J r- ~ < I---T20--l READ DATA, DP(0-1) I... 40 T23A_ T21--l ~ < T19 Micro Channel Architecture, Channel Timing ~I ~ ~ ...jT22 Timing Parameter T1 MiniMax Status active (low) from ADDRESS,M/-IO,-REFRESH valid T2 -CMD active (low) from Status active (low) T3 -ADL active (low) from ADDRESS,M/IO,-REFRESH valid T4 -ADL active (low) to -CMD active (low) T5 -ADL active (low) from Status active (low) T6 -ADL pulse width T7 Status hold from -ADL inactive (high) ADDRESS,M/-IO,-REFRESH,-SBHE hold from -ADL T8 inactive ADDRESS,M/-IO,-REFRESH,-SBHE hold from -CMD T9 active (low) T10 Status hold from -CMD active T11 -SBHE setup to -ADL inactive T12 -SBHE setup to -CMD active T13 -CD DS 16/32 active (n) (low) from ADDRESS,M/-IO,-REFRESH valid T14 -CD SFDBK active (low) from ADDRESS,M/-IO,-REFRESH valid T15 -CMD active (low) from ADDRESS valid T16 -CMD pulse width T17 Write data setup to -CMD active (low) T18 Write data hold from -CMD inactive (high) T19 Status to Read data valid (Access Time) T20 Read data valid from -CMD active (low) T21 Read data hold from -CMD inactive (high) T22 Read data bus tri-state from -CMD inactive (high) T23 -CMD active to next -CMD active T23A -CMD inactive to next -CMD active T23B -CMD inactive to next -ADL active T24 Next Status active (low) from Status inactive T25 Next Status active (low) to -CMD inactive T31 -BE(Q-3) active from ADDRESS valid (32-bit masters only) T32 -BE(Q-3) active from -SBHE, AO, A1 active T33 -BE(Q-3) active to -CMD active Note 101 - ns 551 - ns 451 - ns 401 121 401 251 251 - 2 ns ns ns ns ns 2 301 - ns 3 301 401 401 - 1 55 2 2 2 3 ns ns ns ns 2 - 1 60 ns 851 - ns 901 - ns 01 - ns 301 - ns - 1125 ns - I 60 ns 01 - ns - I 40 ns 1901 - ns 801 - ns 401 - ns 301 - ns - 1 20 ns - 1 40 ns 2 4 - 1 30 ns 101 - ns Figure 20. Default I/O and Memory Cycle (200 Nanoseconds Minimum) Notes: 1. When slaves are selected by the controlling master, they drive -CD SFDBK. Slaves do not drive -CD SFDBK when they are selected by the '-card setup' signal. 2. Slaves should use transparent latches to latch information with the leading or trailing edge of -ADL or with the leading edge of -CMD. Micro Channel Architecture, Channel Timing 41 3. and -CD SFDBK must be driven by unlatched address decodes because the next address may enter the current cycle early. -CD OS 16/32 4. Any controlling master, including the DMA controller, can operate at a performance level lower than the one specified. Designers should not design to a given performance level because the level can be reduced by CD CHRDY, a lower microprocessor rate, a lower DMA controller rate, or by system contention. Default Cycle Return Signals -CD OS 16/32 (n) T13RL -OS 16/32 RTN CD CHRDY (n) T26RL CHRDYRTN Timing Parameter ~r =1 / I: "" )j j t= "" / MiniMax -CD OS 16/32 (n) active to -OS 16/32 RTN active -/20 ns T13RT -/20 ns T26RL -CD OS 16/32 (n) inactive to -OS 16/32 RTN inactive CD CHRDY (n) inactive to CHRDYRTN inactive -/20 ns 2 T26RT CD CHRDY (n) active to CHRDYRTN active -/20 ns 2 Figure 21. Default Cycle Return Signals (200 Nanoseconds Minimum) Notes: 1. These signals, -OS 16 RTN and -os 32 RTN, are developed from a negative OR of signals received from each channel slave. 42 Micro Channel Architecture, Channel Timing T26RT Note T13RL 2. This signal, CHRDYRTN is developed from a positive AND of CD CHRDY signals received from each channel slave. T13RT Synchronous Special Case of Extended Cycle A synchronous-extended cycle occurs when a slave releases CD CHRDY synchronously within the specified time after the leading edge of -CMD. The slave provides the read data within a specified time from -CMD. The timing sequence is illustrated by the following figure. -so, -S1 -CMD CD CHRDY (n) READ DATA ---------------«'-_---'~~ ~1..I---T28D --~.. 1ooI1 Purely Synchronous Special Case Figure 22. Timing Sequence for the Synchronous Special Case of Extended Cycle Micro Channel Architecture, Channel Timing 43 Synchronous-Extended Cycle (300 Nanoseconds Minimum - Special Case) -80,-81 1',----------,/ I -ADL ADDRESS M/-IO -REFRESH, MADE 24 TR32 ~~----~~~--- " ------------7 -SBHE -CD DS 16132 "'-----'-L/f'""""'T"---- II+--IT13 ""'--_----J/ -CDSFDBK ~ 'T14 -CMD ~'---i+=~/_14 ~ T16A --------~,,~----------~~~-- I WRITE DATA -----1 I - - - - - - - - - « ' -_ _ _ _ _ _ _ _ _--"~~ I READ DATA - - - - - - - - - - - - - « ' - -___---'~~ f=3~---1 CDCHRDY 44 I- T26 -i,,~/ I 1------1 T27 Micro Channel Architecture, Channel Timing Timing Parameter T13 MinIMax Note - I 55 ns 2 - I 60 ns 2 -CD DS 16/32 (n) active (low) from ADDRESS,M/-IO,-REFRESH valid T14 -CD SFDBK (n) active (low) ADDRESS,M/-IO,-REFRESH valid T16A -CMD pulse width CD CHRDY (n) inactive (low) from ADDRESS valid T26 1901 - ns - 1 60 ns T27 T28 oI oI T28D CD CHRDY (n) inactive (low) from Status active CD CHRDY (n) release (high) from -CMD active (low) Read Data valid from -CMD active (when used with T28) 3, See T27 3 30 ns 30 ns 0/160 ns This figure shows only the parameters additional to the default cycle. All other parameters are the same as the default cycle. Figure 23. Synchronous-Extended Cycle (300 Nanoseconds Minimum Special Case) Notes: 1. is released by a slave performing a 300-nanosecond extended cycle that is synchronous with the leading edge of -CMD. Since CD CHRDY is generally an asynchronous signal, this is called a purely synchronous special case. CD CHRDY 2. This is the same as default cycle timing (listed here for emphasis). 3. T27 is valid only when status becomes active 30 nanoseconds or more after the address is valid. 4. If status overlaps with a previous -CMD, then the not valid during the overlapped period. 5. Slaves must not hold microseconds. CD CHRDY CD CHRDY state is inactive (low) more than 3.5 Micro Channel Architecture, Channel Timing 45 Notes: 46 Micro Channel Architecture, Channel Timing Asynchronous-Extended Cycle (General Case) An asynchronous-extended cycle occurs when a slave releases CD CHRDyasynchronously. However, the slave provides the read data within the specified time from CD CHRDY release. The timing sequence is illustrated by the following figure. -so, -S1 -CMD ,,,,"------------------ CDCHRDY j.-- T29S--l READDATA--------------------------~<~---.~~ Figure 24. Timing Sequence for the Asynchronous-Extended Cycle (General Case) Micro Channel Architecture, Channel Timing 47 Asynchronous-Extended Cycle General Case) (~300 Nanoseconds Minimum - ""''''~~-" -so, -51 -ADL ADDRESS M/-IO -REFRESH, MADE 24 TR32 1 ~---------------- T== / -SBHE -CD OS 16/32 -CDSFDBK -I-----~I'------'/ I ......-....,... ~T13 I- I ""T14 / "" -CMD / WRITE DATA ------« I »)>---- READ DATA ----------------~( »)>----- T29S CDCHRDY 48 --I f...- ~ ;j~'------'/ T26 I-T27 Micro Channel Architecture, Channel Timing T13 T14 T26 T27 T29S Timing Parameter MinIMax Note -CD DS 16/32 (n) active (low) from ADDRESS,M/-IO,-REFRESH valid -CD SFDBK (n) active (low) ADDRESS,M/-IO,-REFRESH valid CD CHRDY (n) inactive (low) from ADDRESS valid - 1 55 ns 2 - 1 60 ns 2 - lOOns See T27 CD CHRDY (n) inactive (low) from Status active Read data from slave valid from CD CHRDY (n) active (high) o 1 30 ns - lOOns This figure shows only the parameters additional to the default cycle. All other parameters are the same as the default cycle. Figure 25. Asynchronous-Extended Cycle General Case) (~300 Nanoseconds Minimum - Notes: 1. CD CHRDY is released asynchronously by a slave performing a 300-nanosecond minimum cycle. The slave must present the Read data within the time specified after the release of CD CHRDY. 2. This is the same as default cycle timing (listed here for emphasis). 3. T27 is valid only when status becomes active 30 nanoseconds or more after the address is valid. 4. If status overlaps with the previous -CMD, then the is not valid during the overlapped period. 5. Slaves must not hold microseconds. CD CHRDY CD CHRDY state inactive (low) more than 3.5 Micro Channel Architecture, Channel Timing 49 DMA Timing This section provides the specification for critical timing parameters for DMA timing. First Cycle After Grant READ ARB/-GNT ADDRESS M/-IO MADE 24 TR32 0'--------J/ -l r- I i-- -CMD 50 T43A "'-------7 ~--------~ -SBHE -so, -51 WRITE ~----------~ T43B ~----------7 =1 '" / Micro Channel Architecture, Channel Timing MinIMax Timing Parameter T43A ADDRESS valid from ARB/-GNT low T43B -CMD active from ARB/-GNT low 01 - ns 115/-ns Figure 26. First Cycle After Grant Note: A DMA controller must allow 30 nanoseconds after the grant, for a slave to generate an internal acknowledgment that it has been selected. During the first cycle, the DMA controller must allow this additional 30 nanoseconds before sampling -CD OS 16132 RTN and CHRDYRTN, if it places an address on the bus within 30 nanoseconds after the grant. However, if the DMA controller places the address on the bus 30 nanoseconds after the grant, the additional 30 nanosecond allowance is not needed. Micro Channel Architecture, Channel Timing 51 Single DMA Transfer (DMA Controller Controlled) ~'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _, / / / - ARB/-GNT ADDRESS M/-IO MADE 24 TR32 "'-------~ ~--------~ -SBHE DMA READ I MEMORY READ ~--------~ -so, -51 I 110 WRITE ""-------7 -CMD -BURST (High) (DMA Slave) -TC DMAWRITE I/O READ MEMORY WRITE "'" -------7 -so, -51 "''---~r_ -CMD -BURST (High) (DMA Slave) T52H . _ _ _ _ _ _ _ _~T~5~2D~ Tr5~3_ _ _ _ _ _ __ -TC 52 ~ Micro Channel Architecture, Channel Timing Timing Parameter T52 -TC setup to -CMD inactive T52D -TC setup to -CMD inactive T53 -TC hold to -CMD inactive MiniMax Note 301 - ns 151 - ns 101 - ns 2 Figure 27. Single DMA Transfer (DMA Controller Controlled) Notes: 1. Only those timing parameters additional to those specified for the basic-transfer cycle are included here. 2. Only for devices using a 200-nanosecond minimum default cycle. Micro Channel Architecture, Channel Timing 53 Burst DMA Transfer (DMA Controller Terminated) DMAREAD MEMORY READ ~----------~ -SO, -S1 "" -CMD 110 WRITE ~----------~ / "" T52 / T53 1--+--1 T52DH I ------------------~ -TC T54 -BURST -1 r-- ////---~~/'~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-<-L _____' (DMA Slave) DMAWRITE 1/0 READ MEMORY WRITE -so, -S1 -CMD T52ffJT53 T52D ----------~~~------------ -TC -BURST (DMA Slave) 54 T54 -l .~~----/-/T'_ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _L"_____ J Micro Channel Architecture, Channel Timing T52 T520 T53 T54 Timing Parameter MinIMax -TC setup to -CMO inactive -TC setup to -CMO inactive -TC hold from -CMO inactive -BURST released by the OMA slave from -TC active 30/15/10/-/30 ns ns ns ns Note 2 Figure 28. Burst OMA Transfer (OMA Controller Terminated) Notes: 1. Only those timing parameters additional to those specified for the basic-transfer cycle are included here. 2. Only for devices using a 200-nanosecond minimum default cycle. Micro Channel Architecture, Channel Timing 55 Burst DMA Transfer (DMA Slave Terminated - Default Cycle 200 Nanoseconds) DMA READ MEMORY READ ARB/-GNT ADDRESS M/-IO, MADE 24 TR32 1/0 WRITE ~~--------------~~ ~~-----J'~~-------'~ -SBHE -so, -S1 -CMD -BURST (DMASlave) DMAWRITE 1/0 READ ARB/-GNT ADDRESS M/-IO, MADE 24 TR32 ~~--------------~~ ~ __ -SBHE -so, -CMD I 56 -----J'~~ ~---- -S1 -BURST (DMASlave) MEMORY WRITE "" I / ~ ~~ ~------ "''-----'/ T55~ T55 / __ "" I-- T56 "" / / r (~~~=====/(7">----------- Micro Channel Architecture, Channel Timing Timing Parameter -BURST released by the DMA slave from the last 1/0 Status active (default cycle only) T55A -BURST released by the DMA slave from the last 1/0 ADDRESS valid (default cycle only) -BURST inactive (high) setup to -CMD inactive T56 T55 MinIMax Note -/40 ns 2 -/70 ns 2 35/- ns 3 Figure 29. Burst DMA Transfer (DMA Slave Terminated - Default Cycle 200 Nanoseconds) Notes: 1. Only those timing parameters additional to those specified for the basic-transfer cycle are included here. 2. If, after releasing -BURST and upon receiving -SBHE, the DMA slave has another cycle to perform, it must red rive -BURST. 3. inactive (high) setup time to the end of -CMD (T56) must be guaranteed during the last I/O write cycle to prevent the DMA controller from starting the next cycle. This setup time (T56) is guaranteed by the sum of -BURST release by the DMA slave (T55/T55A) and the -BURST resistor-capacitor restoration time. The resistor-capacitor restoration time must not exceed 70 nanoseconds. T56 is the same for the default and extended cycles. -BURST Micro Channel Architecture, Channel Timing 57 Burst DMA Transfer CDMA Slave Terminated - Synchronous-Extended Cycle 300 Nanoseconds) DMAREAD MEMORY READ 110 WRITE -so, -S1 -CMD ""~-----'/ CDCHRDY -1 I- t_~~6 -BURST T55E (DMA Slav_e..:.)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-<-L/ // DMAWRITE 1110 READ -so, I MEMORY WRITE I 110 READ I MEMORY WRITE -S1 -CMD -BURST (DMASlave) T56 T55EWi /F/'·----t" _ _ _ _ _ _ _ _ _ _ _ _ _ _- - L . ( ( CDCHRDY 58 Micro Channel Architecture, Channel Timing T55E T56 Timing Parameter MiniMax -BURST released by the DMA slave from the last -CMD active (extended cycles only) -BURST inactive (high) setup to -CMD inactive -/80 ns 35/- ns Note 2 Figure 30. Burst DMA Transfer (DMA Slave Terminated Synchronous-Extended Cycle 300 Nanoseconds) Notes: 1. Only those timing parameters additional to those specified for the basic-transfer cycle are included here. 2. inactive (high) setup time to the end of -CMD (T56) must be guaranteed during the last 1/0 write cycle to prevent the DMA controller from starting the next cycle. This setup time (T56) is guaranteed by the sum of -BURST release by the DMA slave (T55E) and the -BURST resistor-capacitor restoration time. The resistor-capacitor restoration time must not exceed 70 nanoseconds. T56 is the same for the default and extended cycles. -BURST Micro Channel Architecture, Channel Timing 59 Burst DMA Transfer (DMA Slave Terminated Asynchronous-Extended Cycle ~300 Nanoseconds) DMAREAD I -so, -Sl -CMD , ", , _______ J'", 110 WRITE '" / "" CD CHRDY (n) I MEMORY READ / ; /' -BURST (DMA Slave) DMAWRITE 11/0 READ -so, I MEMORY WRITE 11/0 READ -Sl -CMD -BURST (DMASlave) CD CHRDY (n) 60 /--,;' --------------------------~".-,/ Micro Channel Architecture, Channel Timing I MEMORY WRITE T55X T56 Timing Parameter MinIMax -BURST released by the DMA slave before CD CHRDY (n) active (high) (Async-Extended cycles only) -BURST inactive (high) setup to -CMD inactive 50/- ns 35/- ns Note 2 Figure 31. Burst DMA Transfer (DMA Slave Terminated Asynchronous-Extended Cycle ~300 Nanoseconds) Notes: 1. Only those timing parameters additional to those specified for the basic-transfer cycle are included here. 2. (high) setup time to the end of -CMD (T56) must be guaranteed during the last 1/0 write cycle to prevent the DMA controller from starting the next cycle. This setup time (T56) is guaranteed by the sum of -BURST release by the DMA slave (T55X) and the -BURST resistor-capacitor restoration time. The resistor-capacitor restoration time must not exceed 70 nanoseconds. T56 is the same for the default and extended cycles. -BURST Micro Channel Architecture, Channel Timing 61 Arbitration Timing This section provides the specification for critical timing parameters for arbitration protocol. Arbitration Cycle -PREEMPT -BURST ARB/-GNT -ARB(0-3) ----------~~~~--------- -so, -S1 -CMD Exiting from Inactive State I I ...... T42A -PREEMPT ARB/-GNT -so, S1 62 Micro Channel Architecture, Channel Timing T40 T41 T42 T42A T43 T44 T45 T45A T46 T47 T48 T49 Timing Parameter MiniMax Note -PREEMPT active (low) to End of Transfer ARB/-GNT high from End of Transfer -PREEMPT inactive (high) from ARB/-GNT low -PREEMPT inactive (high) to Status inactive -BURST active (low) from ARB/-GNT low (By Bursting DMA slave) ARB/-GNT high Driver turn-on delay from ARB/-GNT high Driver turn-on delay from lower priority line Driver turn-off delay from ARB/-GNT high Driver turn-off delay from higher priority line Arbitration bus stable before ARB/-GNT low Tri-state drivers from ARB/-GNT high o 17.8p.s 30 I- ns o 150 ns 20 I- ns - 150 ns 1 6 100 Io 150 o 150 o 150 o 150 10 I-/50 ns ns ns ns ns ns ns 5 4 2 3 3 3 3 Figure 32. Arbitration Cycle Notes: 1. The intent of this parameter is to limit the maximum non-preemptive ownership of the bus. 2. The value shown applies only to the special case implementation involving the central arbitration control point, and is provided for pulse width and portability considerations only. Arbitration can be extended by refresh or error recovery procedures. An arbiter should decode a win of the grant by a combined decode of the arbitration bus and the ARB/-GNT. The minimum arbitration time can be 100 nanoseconds when a level 0 arbiter and the central arbitration control point coordinate. In this special case, the central arbitration control point can terminate arbitration prematurely at 100 nanoseconds. 3. T45, T45A, T46, and T47 must be satisfied by arbitrating bus participants. ARB (0-3) drivers of all 4. This parameter applies to all bus winners. 5. This represents the timing requirement after the resistor-capacitor line delay. This window is available for devices to detect inactive -PREEMPT and exit from the Inactive state after the rising edge of status. 6. Because no maximum is specified, a controlling master must degate bus drivers at the end-of-transfer condition. The end-of-transfer condition must be held stable until arbitration begins. Micro Channel Architecture, Channel Timing 63 Configuration Timing This section provides the specification for critical timing parameters for the system configuration protocol. Setup Cycle CHRESET ADDRESS -SBHE MADE 24 TR32 ~~__________________________________ 1----1 T60 "''--__~r -so -S1 -ADL -l -CD SETUP -CMD j ~"....~--- CDCHRDY(n~ 64 '" ~T65~ I: T62 i--T63 / Micro Channel Architecture, Channel Timing T60 T61 T62 T63 T65 Timing Parameter MiniMax CHRESET active (high) pulse width -CD SETUP (n) active (low) to -ADL active (low) -CD SETUP (n) hold from -ADL inactive (high) -CD SETUP (n) hold from -CMD active (low) CD CHRDY (n) inactive (low) from -CD SETUP (n) active 100 151 251 301 1 - ms - ns - ns - ns - 1 100 ns Note 3 Figure 33. Setup Cycle Notes: 1. Only those timing parameters that are different or additional to those specified for the basic-transfer cycle are included here. 2. The setup cycle is 300 nanoseconds minimum (default). A valid non-adapter selecting address must be present on the bus during system configuration. 3. A slave is allowed to extend the setup cycle beyond 300 nanoseconds using CD CHRDY. The slave qualifies the leading edge of CD CHRDY with active status. 4. Setup cycles are restricted to 8-bit transfers. Micro Channel Architecture, Channel Timing 65 Additional Channel Timings Timing Parameter -CD CHRDY inactive Card 10 = 0000 (Indicating not ready) Retention of bus ownership after -PREEMPT active Data steering (high 16-bit/low 16-bit data crossover) Exiting Inactive state (driving -PREEMPT) after -PREEMPT inactive and the rising edge of Status MinIMax - 13.5 ps - 11 s - 17.8 Jls - 115 ns 0/- Note 1 2 3 4 Figure 34. Additional Channel Timings Notes: 1. An adapter may issue an 10 of hex 0000 for up to 1 second after channel reset to indicate it is not ready. Any adapter that continues to issue an adapter 10 of hex 0000 (not ready) for more than 1 second is considered defective. 2. Applies to bursting masters with the fairness feature active. 3. When a 16-bit master accesses a 32-bit slave, the 32-bit slave is responsible to compensate for this added delay. 4. Applies to bursting masters (with the fairness feature active) that were preempted and have entered the Inactive state. 66 Micro Channel Architecture, Channel Timing Auxiliary Video Extension Timing r= 1 T1 DCLK T2~ ~ P 0-7 A iT6~ ~ ~ ~T7 ~ -BLANK T8 Red Green Blue C / ~I A C B Symbol Description Min. Max. T1 T2 T3 T4 T5 T6 T7 T8 PEL Clock Period (tclk) Clock Pulse Width High (tch) Clock Pulse Width Low (tcl) PEL Set-Up Time (tps) PEL Hold Time (tph) Blank Set-Up Time (tbs) Blank Hold Time (tbh) Analog Output Delay (taod) 28 ns 7 ns 9 ns 4 ns 4 ns 4 ns 4 ns 3(11) + 5 ns 10,000 ns 10,000 ns 10,000 ns 3(11) + 30 ns Figure 35. Auxiliary Video Connector Timing (DAC Signals) Note: See "Video Subsystem" for additional video timing information. Micro Channel Architecture, Channel Timing 67 Notes: 68 Micro Channel Architecture, Channel Timing Index A C additional channel timings 66 address bus 4, 11 address bus translator 32 -ADL signal 4 ARB/-GNT signal 8, 28 arbiter mismatch 25 arbiter refresh 31 arbitration level 30, 31 arbitration timing 62 ARBO - ARB3 signal 8 asynchronous-extended cycle 47, 48 AUDIO GND signal 10 AUDIO signal 10 auxiliary video extension 17 auxiliary video extension timing 67 auxiliary video signals 13,22 AO - A23 signals 4 A24 - A31 signals 11 CD CHRDY signal 7 -CD OS 16 signal 5 -CD OS 32 signal 11 -CD SETUP signal 9 -CD SFDBK signal 7 central arbitration control point 23 central steering logic 33 central translator logic 33 channel connector diagram 3 channel connector voltages and signal assignments 15 channel connectors 2,15,17 channel definition 2 channelsupport 32 -CHCK signal 9 CHRDYRTN signal 7 CHRESET signal 10 -CMD signal 7,28 connector, auxiliary video extension 17 connector, matched-memory extension 19 connector, 16 bit 15 connector, 32-bit 18 connectors, channel 2 controlling master 1,23 critical timing parameters 36 cycle, asynchronous-extended 47, 48 cycle, default 40 cycle, synchronous-extended 44 B basic-transfer cycle 36 -BE signals 11, 32, 33 BLANK signal 13 -BURST signal 9 burst data transfers 23 burst DMA transfer 54 burst mode 28 burst mode timing 28 bus ownership 23 bus priority assignments bus, address 4 bus, data 4 byte enable 32 30 Index 69 D L data bus 4, 11 data bus steering 32, 33 OCLK signal 13 default cycle 40 default cycle return 42 description, micro channel distributed arbitration 25 distributed arbitration block diagram 25 OMA channels 31 OMA timing 50 -OS 16 RTN signal 5 -OS 32 RTN signal 12 00 - 015 signals 4 016 - 031 signal 11 level-sensitive interrupts local arbiters 24, 25, 27 M M/-IO signal 5 MAOE 24 signal 5 master, controlling 1, 23 matched-memory connector matched-memory signal description 12 memory cycle 39 memory refresh 31 micro channel description -MMC signal 12 -MMC CMO signal 12 -MMCR signal 12 multiple transfers 24 E EOCLK signal 14 electromagnetic interference ESYNC signal 13 EVIOEO signal 14 F fairness feature 30 first cycle after grant 50 H N NMI 30 NMI service 31 NMI signal 31 nominal cycle 36 o 13 P I 1/0 cycle 39 inactive state 30 inactive state, exiting 62 interrupt pending latch 34 interrupt sharing 34 -IRQ 14-15 signal 9 -IRQ 3-7 signal 9 -IRQ 9-12 signal 9 70 2 OSC signal 10 ownership, bus 23 HSYNC signal Index 34 -PREEMPT signal 8, 29 preempt timing 29 preemption 29 PO - P7 signals 13 19 R -REFRESH signal 10, 31 reserved signals 3, 4 S -SBHE signal 5 setup cycle timing 64 signal descriptions, auxiliary video 13 signal descriptions, matched-memory 12 signal descriptions, 16-bit 4 signal descriptions, 32-bit 11 signal groups 19 signals, reserved 3, 4 single DMA transfer 52 slave 23 steering control diagram 32 synchronous-extended cycle 43, 44 system configuration timing 64 -SO, -S1 signals 5 T -TC signal 9 timing parameters 36 timing, DMA 50 TR 32 signal 12, 32 V VSYNC signal 13 Numerics 16-bit connectors 32-bit connectors 2 2 Index 71 Notes: 72 Index Programmable Option Select Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Selected Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Board Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Required Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Selection for Setup . . . . . . . . . . . . . . . . . . . . . . . . Adapter POS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . POS Implementation Procedure . . . . . . . . . . . . . . . . . . . . . . . System Configuration Utilities . . . . . . . . . . . . . . . . . . . . . . . . Automatic Configuration Utility . . . . . . . . . . . . . . . . . . . . . Change Configuration Utility . . . . . . . . . . . . . . . . . . . . . . . View Configuration Utility . . . . . . . . . . . . . . . . . . . . . . . . . Backup and Restore Configuration Utilities ............. Copy an Option Diskette Utility . . . . . . . . . . . . . . . . . . . . . Adapter Description Files . . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Option Select 1 3 3 4 6 6 7 7 9 10 11 12 13 13 13 14 14 14 20 Figures 1. 2. 3. 4. 5. 6. 7. II POS 1/0 Address Space ......................... POS 1/0 Address Decode ........................ Channel-Check Active Indicator . . . . . . . . . . . . . . . . . . .. Typical Adapter Implementation of POS .............. Subaddressing POS Extension Example .............. Syntax Symbol Key ........................... Adapter Description File Syntax .................. Programmable Option Select 3 4 5 8 9 14 15 Description Programmable Option Select (POS) eliminates the need for switches from the system board and adapters by replacing their function with programmable registers. The System Configuration utilities (described on page 10) automatically create configuration data for the system board and each adapter. This is achieved by reading a unique adapter 10 number from each adapter, matching it with an adapter description file (AOF), and configuring the system accordingly. The resulting data and adapter 10 numbers are stored in battery-backed CMOS RAM. This data permits the power-on self-test (POST) to automatically configure the system whenever the system is powered on. The POST first verifies that the configuration has not changed by reading the adapter 10 numbers and comparing them with the values stored in the battery-backed CMOS. If the configuration has changed, it is necessary to rerun the System Configuration utilities. The adapters and the system board setup functions all share I/O addresses hex 0100 through 0107. Programmable Option Select 1 Warning: • IBM recommends that programmable options be set only through the System Configuration utilities. Directly setting the POS registers or CMOS RAM POS parameters can result in multiple assignment of the same system resource, improper operation of the feature, loss of data, or possible damage to the hardware. • Application programs should avoid using the adapter identification (10) whenever possible. Software compatibility problems with systems and options may result. • If an adapter and the system board are in setup mode at the same time, bus contention will occur, no useful programming can take place, and damage to the hardware can occur. • After setup operations are complete, the Adapter Enable/Setup register (hex 0096) should be set to hex 00, and the System Board Enable/Setup register (hex 0094) should be set to hex FF. • The channel reset bit (bit 7) in the Adapter Enable/Setup register must be 0 to program the adapters. Setup functions respond to I/O addresses hex 0100 through 0107 only when their unique setup signal is active. The system board does not support 16-bit I/O operations to 8-bit POS registers. Using 16-bit I/O instructions on 8-bit POS registers will cause erroneous data to be written to or read from the registers. Only 8-bit transfers are supported for setup operations. 2 Programmable Option Select The following figure shows the organization of the 1/0 address space used by the POS. Address (Hex) 0100 0101 0102 0103 0104 0105 0106 0107 Function P~S Register 0 - Adapter Identification Byte (Low byte) Register 1 - Adapter Identification Byte (High byte) P~S Register 2 - Option Select Data Byte 1 Bit 0 is designated as Card Enable. P~S Register 3 - Option Select Data Byte 2 P~S Register 4 - Option Select Data Byte 3 P~S Register 5 - Option Select Data Byte 4 Bit 7 is designated as channel check active. Bit 6 is designated as channel check status available. P~S Register 6 - Subaddress Extension (Low byte) P~S Register 7 - Subaddress Extension (High byte) P~S Figure 1. POS 1/0 Address Space Bits 6 and 7 of address hex 0105 and bit 0 of address hex 0102 are fixed. All other fields within the address range of hex 0102 and 0105 are free form. Card Selected Feedback When the adapter is addressed, it responds by setting the Card Selected Feedback signal (-CD SFDBK) to O. -CD SFDBK is derived by the adapter from the address decode, and driven by a totem pole driver. -CD SFDBK is latched by the system board and made available on subsequent cycles. -CD SFDBK may be used by automatic configuration or diagnostics to verify operation of an adapter at a given set of addresses. -CD SFDBK enables diagnostics to verify the operation of the adapter. System Board Setup The integrated 1/0 functions of the system board use POS information during the setup procedure. The bit assignments and functions may vary from system to system (refer to the system board setup information in the system-specific technical reference for the system you are dealing with). Programmable Option Select 3 Adapter Setup The '-card setup' signal (-CD SETUP (n) is unique for each channel connector. When -CD SETUP (n) is active, adapters recognize setup read and write operations. The adapter decodes -CD SETUP and all three low-order address bits (AO through A2) to determine the POS register to be read from or written to. -CD SETUP is enabled by an I/O operation on the address range 0100 through 0107. The figures in this section show the complete address. The setup routine (Automatic Configuration) obtains adapter information from ADFs and uses I/O addresses hex 0100 through 0107 to address the POS bytes of the adapter. The following figure shows the organization of the address space used by POS during adapter setup operations. Address (Hex) ·CDSETUP Address Bit A2A1 AO 0100 (POS Register 0) 0 0 0 0101 (POS Register 1) 0 0 0 0102 0103 0104 0105 0106 Register 2) Register 3) Register 4) Register 5) Register 6) 0 0 0 0 0 0 0 0107 (POS Register 7) 0 (POS (POS (POS (POS (POS 1 0 0 1 0 0 1 0 0 Function Adapter Identification Byte (Least-significant byte) Adapter Identification Byte (Most-significant byte) Option Select Data (Byte 1)' Option Select Data (Byte 2) Option Select Data (Byte 3) Option Select Data (Byte 4)' Subaddress Extension (Least-significant byte) Subaddress Extension (Most-significant byte) , These bytes contain one or more bits with specific assignments. Figure 2. POS 1/0 Address Decode Bytes hex 0100 and 0101 are 8-bit read-only. Bytes hex 0102 through 0107 are 8-bit read-only and read-write. All bits in bytes hex 0102 through 0105 are free-form, adapter-dependent, and implemented except for the following: • Hex 0102, Bit 0: Card Enable (CDEN): When this bit is set to 0, the adapter is disabled, responding only to setup read and write operations, and 'channel reset'. It does not respond to I/O or 4 Programmable Option Select memory read or write operations, nor does it make any interrupt requests. When this bit is set to 1, the adapter is fully enabled. • Hex 0105, Bit 7: Channel-Check Active Indicator (-CHCK): System memory and 1/0 functions that report a channel-check must set a channel-check active indicator to identify the source of the error. This indicator is bit 7 of address hex 0105 of each adapter POS address space. This bit can be interrogated by the nonmaskable interrupt (NMI) handler responding to 'channel check' for each adapter position until all reporting adapters have been identified. The following figure shows a typical implementation of the channel-check active indicator. Clear D Data Bit 7 lOW Channel Check r-- Setting Condition an AND I - - - ck Byte 105H Decode --r Set L-. Channel Reset I Ir AND - JS IOR -CD SETUP Figure 3. Channel-Check Active Indicator The indicator is set to 0 on a channel-check condition or when bit 7 of POS Register 5 is set to O. The indicator is set to 1 on a channel reset, or when bit 7 of hex 0105 is 1. This bit may be reset by any action occurring during the channel-check service routine. If the channel-check active indicator is used by an attachment, hex 0105 bit 6 must be used to indicate whether additional status is available through bytes hex 0106 and 0107. • Hex 0105, Bit 6: Channel-Check Status Indicator: When set to 0, this bit indicates channel-check exception status is available from POS Registers 6 and 7. When set to 1, this bit indicates no status is available. Registers 6 and 7 may be the status, a pointer to status, or a command port to present the address elsewhere (for example, in a subaddress area). Bit 6 is required by all devices supporting the channel-check active indicator (bit 7). If a device does not use the channel-check active indicator, bit 6 may be defined to contain Programmable Option Select 5 device-unique information. If a device uses the channel-check active indicator, but does not report status, bit 6 must be set to 1. Adapter Identification Each adapter has a unique 2-byte adapter 10. This enables diagnostic programs, configuration utilities, and POST routines to initialize the adapter when the system is powered on or reset. To minimize the need for hardware, only bits driven to 0 require drivers. Pull-up resistors on the system board provide a 1 for each remaining bit. See "Micro Channel Adapter Design" for more information. Required Fields Several fields are not assigned specific bit locations within the free form POS bytes. However, the following are required if the adapter supports the function: • Fairness Enable Bit: All bursting devices using the arbitration mechanism must support the fairness feature through a programmable fairness-enable bit. The default state of this bit is 1, requiring all devices to honor the fairness feature. When fairness-enable is set to 0, the fairness feature is disabled. • Arbitration Level Field: All devices (bursting and nonbursting) using the arbitration mechanism must support a programmable arbitration level through a 4-bit allocation. This field allows incorrectly prioritized devices to be reassigned by diagnostic or system programs to reduce impacts on performance. Only one device may be aSSigned to each arbitration level. • Device ROM Segment Address Field: All 1/0 devices containing memory-mapped 1/0 ROM must support a programmable Device ROM Segment Address field. This field can be up to 4 bits and provides the ROM of a device a starting address at anyone of sixteen aKB segments. • 110 Device Address Field: All 1/0 devices that can simultaneously reside in a system with a device of the same type must support programmable 1/0 device addresses. This field eliminates addressing conflicts. 6 Programmable Option Select Adapter Selection for Setup Each channel position has a unique 'setup' line (-CD SETUP) associated with it. See the system-specific technical references for more information. Adapter POS Implementation The following figure shows how an adapter typically implements POS. All designs must latch the least-significant bit of the device-dependent option-select byte. Bit 7 of POS Register 5 is set to 1 unless -CHCK is active from the adapter. The remaining bits can be implemented as required. Note: Any adapter that POS does not completely initialize should implement a second enable, which is activated by adapter ROM routines or loadable software. The card-disable function (PaS Register 2, bit 0) must override a second enable. Programmable Option Select 7 R EA:"-{J-- :> AND c o SETUP Decoder 3 2 1 0 A 01 AOO - Data Register Data Register -./ """"" ·· ·· ·· ·· ·· ·· ·· · I Data Gate 000: 007 r- Data Gate CDEN I t-- I Disable Adapter I I Decoder 3 2 - A02~ wRITE AND Enable Open Collector Or Tri-state 10 Bit Drivers High Byte Enable Open Collector Or Tri-state 10 Bit Drivers Low Byte - Figure 4. Typical Adapter Implementation of POS The P~S subaddressing extension allows the subaddressing of a block of initial program load (IPL) or setup information. Subaddressing bits (SADOO through SAD15) are used to address RAM, a register stack, or other devices. 8 Programmable Option Select The following figure shows the subaddressing extension for memory. The counter registers increment after each least-significant byte of option-select information is written. A 00 _ _ _ _ _--, lOR ------~H SAD 15 SAD 14 SAD 13 SAD 12 SAD 11 SAD 10 SAD 09 SAD 08 A01----i A02----l CD SETUP Data Gate 000007 SAD 07 SAD 06 SAD 05 SAD 04 SAD 03 SAD 02 SAD 01 SAD 00 10W-------if-t4>-i Data Gate Clk Gate Figure 5. Subaddressing POS Extension Example POS Implementation Procedure Although the design of POS circuitry is the designer's choice, the following is an example of a typical POS implementation. 1. Disable interrupts. 2. Select the adapter for subsequent setup cycles. See the system-specific technical references for more information. 3. Read the adapter ID by an 110 read at hex 0100 and hex 0101. 4. Disable the adapter and place it in setup by performing an 1/0 write to hex 0102 with bit 0 off. 5. Write POS data to hex 0103,0104, and 0105 in any order. 6. With bit 0 set to 1, write POS data to hex 0102. 7. Deselect the adapter. See the system-specific technical references for more information. 8. Enable interrupts. Programmable Option Select 9 The system microprocessor can communicate with the adapter, provided the adapter is enabled (bit 0 at hex 0102 set to 1). After the adapter has been set up, a subsequent 110 write does not affect these latches or permit the 10 circuitry of the adapter to operate, unless the adapter is returned to setup. System Configuration Utilities Each system has a Reference Diskette containing the System Configuration utilities. These utilities identify the installed hardware and interpret the system resources (1/0 ports, memory, interrupt levels, and arbitration levels) for each device. The System Configuration utilities are contained within the Set Configuration program. The Reference Diskette enables the user to configure the system in one of two ways: • Running the Automatic Configuration utility after a configuration error is displayed • Selecting Set Configuration from the Main Menu. The Set Configuration program uses information contained in adapter description files (ADFs) to track and allocate system resources. Each ADF describes the resources that can be allocated to a specific adapter and the POS setting used to indicate those resource assignments. When more than one device is configured to the same resource and that resource cannot be shared, only one of the conflicting devices is enabled. ADF data for the system board and some adapters is contained on the Reference Diskette. Before new adapters are installed, their associated ADFs must be merged onto a backup copy of the Reference Diskette by selecting Copy an Option Diskette from the Main Menu and following the instructions on the screen. Each adapter contains a 16-bit adapter 10 and one to four 8-bit POS registers. Adapter IDs and the POS information are stored in CMOS RAM by the Set Configuration program. The CMOS RAM locations used to hold this information are not the same for all systems. The Set Configuration program determines the system type and handles differences between systems such as the CMOS RAM storage and the 10 Programmable Option Select number of available adapter slots. If the system is identified as having only a 64-byte CMOS RAM, adapter IDs and POS data are stored in the 64-byte CMOS RAM. Each adapter slot is allocated 2 bytes for an adapter 10 and 4 bytes for POS data. If the system type is identified as having a 2KB CMOS RAM extension, adapter IDs and POS data are stored in the 2KB CMOS RAM. Automatic Configuration Utility Automatic Configuration can be run after a configuration error has occurred or by selecting Run Automatic Configuration from the Set Configuration menu. Each time the system is powered on, the POST compares the configuration of the system to the configuration indicated by CMOS RAM. If differences between the two are detected, an error is displayed and logged in system RAM. POST error message files contained on the Reference Diskette display text that provides further information about the POST error. Note: The Reference Diskette must be installed when the system is powered on to receive POST error messages. If a configuration error is caused by a battery failure or a bad cyclic-redundency check (CRC), Automatic Configuration is run immediately after the POST error is displayed. If the error is caused by a change to the configuration, the user is given a choice to either run Automatic Configuration or continue to the Main Menu. If the user continues with the Main Menu, the changed areas of the system are configured and CMOS RAM is updated when Set Configuration is selected from the Main Menu. Depending on the source of the error, Automatic Configuration either reconfigures the entire system or configures only the areas of the system that have been changed since the last time a configuration was performed. The following POST errors cause the system to be completely reconfigured: • 161 (battery failure) • 162 (bad CMOS CRC). Programmable Option Select 11 The following POST errors cause only the areas of the system that have changed to be reconfigured: • 162 (system configuration error not caused by a bad CMOS CRC) • 164 (memory configuration) • 165 (adapter configuration). An adapter is considered previously configured when the POS data stored in CMOS RAM matches a POS setting in the appropriate ADF. If an ADF for an installed adapter cannot be found, the adapter is configured as an empty slot. During Automatic Configuration, devices are configured to the first nonconflicting values as defined in the ADF. Adapters are configured in the order of the channel position in which they are installed. The system board is configured first, followed by each adapter slot starting with slot 1. If the interrupt level is the only resource defined for a specific adapter item, the choice of interrupt levels that are least used by other adapters are assigned. Automatic Configuration does not backtrack to previously configured adapters to resolve resource conflicts. If conflicts can be resolved, they must be done by choosing a nonconflicting resource option through the Change Configuration utility. Any adapter having a resource conflict that cannot be resolved by the Set Configuration program is disabled; the program sets bit 0 of POS Register 2 (hex 0102) to 0 in CMOS RAM. Change Configuration Utility The Change Configuration utility allows the user to change the default configuration settings from those set by Automatic Configuration. This utility is used to resolve unusual conflicts or to set items for personal preference. The user interface is through scrolling and paging screens. Changes are made by rotating field value names through a set of choices using the F5 (Previous) and F6 (Next) keys. Changes are not saved in CMOS until the F10 (Save) key is pressed. Help text is provided for each item by pressing the F1 (Help) key. 12 Programmable Option Select Resource conflicts are indicated by an asterisk (*) next to the conflicting items and also by the "* Conflicts" string in the upper right corner of the Change Configuration window. Conflicts with fixed resources have the asterisk (*) to the left of the slot number of the adapter. Adapters with conflicts are disabled; the program sets bit 0 of POS Register 2 (hex 0102) to 0 in CMOS RAM. View Configuration Utility The View Configuration utility is provided to view the configuration. This is the Change Configuration utility with the change capabilities disabled. Backup and Restore Configuration Utilities The Backup Configuration utility provides a means to back up the configuration data to a file on the Reference Diskette. If the battery fails or the battery is changed, the user can use the Restore utility to restore the configuration. Note: A copy of the Reference Diskette that is not write-protected is needed for this backup and restore process. Copy an Option Diskette Utility The Copy an Option Diskette utility is a separate program from the Set Configuration program and is accessible through the Main Menu. This utility is used to merge the following files from an option diskette onto a backup copy of the Reference Diskette: *.adf, *.dgs, *.pep, COMMAND.COM, DIAGS.COM, CMD.COM, and SC.EXE. The files found on the option diskette are compared to the files on the backup copy of the Reference Diskette. If the file does not exist on the Reference Diskette, it is copied. If the file already exists on the Reference Diskette, the dates of the two files are compared. The file on the option diskette is copied only if it has a date later than the corresponding file on the Reference Diskette. The option diskette must be a DOS formatted diskette. Programmable Option Select 13 Adapter Description Files Adapter description files provide P~S information and system resource information for Automatic Configuration. The adapter description files also provide text for System Configuration utilities, help screens, and prompts. This section provides guidelines for developing the adapter description files. Format • File names: @CAROIO.adf (high byte of the adapter 10 first). • Type of file: ASCII text. • Not case sensitive: Key words can be lowercase, uppercase, or mixed. The case is preserved within the user interface text strings. • Blanks, tabs, new lines: These are considered as white space and ignored, except when in text strings for the Change Configuration user interface. • Comments: Lines beginning with semicolons are comments and are ignored. Syntax The following figure shows the meaning of special symbols used in the adapter description file syntax. Symbol Meaning o an optional item 0.1.2 •... items allowed 1.2.3•... items allowed either x or y allowed n x's required one or more decimal digits 0* 0+ xlY x{n} [0-9]+ Figure 6. Syntax Symbol Key 14 Programmable Option Select adf_file => card_id card_name nbytes {fixed_resources} {named_item}* This defines the contents of an ADF. The following definitions describe each portion of an ADF in detail. card_id => Adapterld number Each ADF must contain a card_id. The character string 'Adapterld' is a keyword and must be present in the ADF. The Configuration program looks for this 10, which must match the 10 used in the filename. Example: Adapterld 0DEFFh card_name => AdapterName string Each ADF must contain a card_name. The character string 'AdapterName' is a keyword and must be present in the ADF. The string following the 'AdapterName' keyword is displayed as the adapter name in the Change Configuration and View Configuration screens. The length of the AdapterName string is limited to (74 - (length of 'Slot)( - ')) characters. (US English length = 66 characters) Example: AdapterName "I BM Multi -Protoco 1 Communi cat ions Adapter" nbytes => NumBytes number Each ADF must contain an nbytes. The character string 'NumBytes' is a keyword and must be present in the ADF. This is used to define the number of POS bytes used by the adapter. The number of POS bytes used should include all bytes from POS [0] to the last POS byte used. (If POS [3] is the only POS byte defined, NumBytes should be set to 4.) Example: NumBytes 4 fixed_resources => FixedResources pos_setting resource_setting A fixed_resources is not a requirement for ADFs. It is used to define resources required by an adapter and corresponding POS data. The character string 'FixedResources' is a keyword and must be present in the ADF only if the adapter needs to define resources that it requires. Example: FixedResources POS[1]=XXXX01XXb int 3 Figure 7 (Part 1 of 5). Adapter Description File Syntax Programmable Option Select 15 named_item => NamedItem prompt {named_choice}+ help A named_item is not a requirement for ADFs. The named_item is used to define a field providing a choice of one or more resources. Each choice sets specified P~S bits to a unique setting used to identify resources assigned to the adapter. The character string 'Namedltem' is a keyword and must be present in the ADF only if the adapter can be configured to use different resources. The adapter determines the resources it is configured to by how the P~S bytes are set. When a 'Named Item' is defined in an ADF it must be accompanied by a prompt (defined later), at least one named_choice (defined later), and help (defined later). Example: NamedItem Prompt "Communications Port" choi ce "SOLC_I" pos [e] =XXXHleeXb io e38eh-e38ch int 3 4 choi ce "SOLC_2" pos [e] =XXXleeIXb io e3aeh-e3ach int 3 4 choice "BISYNC_I" pos[e]=XXXlleeXb io e38eh-e389h int 3 4 choice "BISYNC_2" pos[e]=XXXlleIXb io e3aeh-e3a9h int 3 4 choice "SERIAL_I" pos[e]=xxXeeeeXb io e3f8h-e3ffh int 4 choice "SERIAL_2" pos[e]=XXXeeeIXb io e2f8h-e2ffh int 3 choice "SERIAL_3" pos[e]=XXXeeleXb io 322eh-3227h int 3 choice "SERIAL_4" pos[e]=XXXeellXb io 3228h-322fh int 3 choice "SERIAL_5" pos[e]=XXXeleeXb io 422eh-4227h int 3 choice "SERIAL_6" pos[e]=XXXeleIXb i 0 4228h-422fh int 3 choi ce "SERIALj" pos [e] =xxxelleXb io 522eh-5227h int 3 choice "SERIAL_8" pos[e]=XXXellIXb i 0 5228h-522fh int 3 Help "This port can be assigned as a: primary (SOLCI) or secondary (SOLC2) sdlc. primary (BISYNCI) or secondary (BISYNC2) bisync. or as a serial port (Serial I through Serial 8). Use the F5=Previous and the F6=Next keys to change this assignment in the 'Change configuration' window. Conflicting assignments are marked with an asterisk and must be changed to use the adapter." prompt => Prompt string The prompt is required when a Namedltem is defined. The prompt is used to define a title for a Namedltem field. The character string 'Prompt' is a keyword and must be present in the ADF when there is a Namedltem present. The string following the 'Prompt' keyword appears after the adapter name in the Change Configuration and View Configuration screens. Following the prompt string is a field that can be toggled in the Change Configuration screen if two or more named_items are defined. The length of the prompt string cannot exceed 38 characters. Example: (See the example for namedJtem). Figure 7 (Part 2 of 5). Adapter Description File Syntax 16 Programmable Option Select named_choice => Choice choice_name pos_setting resource_setting At least one named_choice is required when a Namedltem is defined. The character string 'Choice' is a keyword and must be present in the ADF when there is a Namedltem present. One or more named_choices must follow a prompt. Each named_choice must contain a string describing the current choice in the prompt field. Each named_choice must define a pos_setting, for at least one P~S byte, which will uniquely identify the resource_setting defined in the named_choice. The length of the named_choice string cannot exceed 28 characters. Example: (See the example for namedJtem). help -> Help string The help is a string of text used to give the user assistance at a prompt. This text is displayed in the Change Configuration and View Configuration screen when the cursor is at the associated prompt and the F1 key is pressed. The character string 'Help' is a keyword and must be present in the ADF when there is a Namedltem present. The string following the keyword 'Help' is the text describing the prompt defined in the same Namedltem as the help. The length of the help string is limited to 1000 characters. Example: (See the example for named_item). pos_setting => {pos_byte_setting}+ The pos_setting must contain at least one pos_byte_setting. See the definition of pos_byte_setting for more information. pos_byte_setting => pos[number]=pos_bit{8}b This is the definition of the pos_byte_setting in the ADF. The character string 'pos' is a keyword and must be present in a pos_byte_setting, followed by a number in brackets. The number in brackets refers to the following P~S bytes: number = 0, P~S byte at port 102h number = 1, P~S byte at port 103h number = 2, P~S byte at port 104h number = 3, P~S byte at port 105h The end bracket must be followed by an equal sign and then a bit definition of the P~S byte (See pos_bit for information on the bit definition). The bit definition must define all 8 bits of the byte. Bit 0 of pos[O] should always be defined as X in the ADF. Example: pos [0] =XXXlOOIXb Figure 7 (Part 3 of 5). Adapter Description File Syntax Programmable Option Select 17 pos_bit => X I xI 0 I 1 A pos_bit can be defined as a mask bit (x or X), a clear bit (0), or a set bit (1). Example: pos[0]=XXX1001Xb resource_setting => {ioblock_list} {interrupt_list} {arb_list} {memaddr_list} The resource_setting defines a list of system resources. They may be fixed resources required by the adapter or they may be resources the adapter uses when configured to a specific choice in a named_item. The resources can consist of the following: Range of 1/0 addresses (limited to 16). List of interrupt levels (limited to 16). List of arbitration levels (limited to 16). Range of memory addresses (limited to 2). Example: (See the following resource definitions). ioblock_list => 10 {range}+ The ioblock_list must be a list of one or more ranges of 1/0 addresses. The character string '10' is a keyword and must be present in the ioblock_list. Example: i 0 4220h-4227h Interrupt_list => INT {number}+ The interrupUist must be a list of one or more interrupt levels. The character string 'INT' is a keyword and must be present in the interrupUist. Example: INT 3 4 arb_list => ARB {number}+ The arb_list must be a list of one or more arbitration levels. The character string 'ARB' is a keyword and must be present in the arb_list. Example: ARB 1 memaddr_list => MEM {range}+ The memaddr_list must be a list of one or more ranges of RAM or ROM addresses. The character string 'MEM' is a keyword and must be present in the memaddUist. This keyword is used to allocate memory address space in the hex OOOCOOOO through hex OOODFFFF range. Example: MEM 0CC000h - 0CDFFFh range => number - number Figure 7 (Part 4 of 5). Adapter Description File Syntax 18 Programmable Option Select number => [0-9]+ {d} I [0-9a-f]+ h [0-9A-F]+ H string => " [ascii except for "]+ " A string is a set of ASCII characters beginning with a double quote (") and ending with a double quote. Example: "This port can be assigned as a: primary (SOLCI) or secondary (SOLC2) sdlc port. primary (BISYNCI) or secondary (BISYNC2) bisync port. or as a serial port (Serial 1 through Serial 8). Use the F5=Previous and the F6=Next keys to change this assignment in the 'Change configuration' window. Conflicting assignments are marked with an asterisk and must be changed to use the adapter." Figure 7 (Part 5 of 5). Adapter Description File Syntax Programmable Option Select 19 Example The following is an example of an adapter description file for the IBM Personal System/2 Multiprotocol Communications Adapter/A. The name of the file for this adapter is @DEFF.adf. An explanation of each numbered item begins on page 21. Adapterld 90EFFh D AdapterName "IBM Multiprotocol Communications Adapter" II NumBytes 211 Namedltem II Prompt "Communications Port" choi ce choice choi ce choi ce choice choi ce choi ce choi ce choice choice choi ce choice "SOLC]' "SOLC_2" "BISYNC_I" "BISYNC_2" "SERIAL_I" "SERIAL]' "SERIAL]' "SERIAL_4" "SERIAL_5" "SERIAL_6" "SERIAL]' "SERIAL_S" pos [9] =XXX1999Xb pos[G]=XXXI9GIXb pos [G] =XXXllGGXb pos [G] =XXXllGIXb pos[G]=XXXGGGGXb pos [G] =XXX999IXb pos [G] =XXXGG19Xb pos [G] =XXXGGllXb pos[G]=XXX919GXb pos[G]=XXX919IXb pos [G] =XXXGllGXb pos[G]=XXXGlllXb i0 io i0 i0 io i0 i0 i0 io io i0 io 93S9h-93Sch 93aGh-G3ach G3SGh-93S9h G3aGh-93a9h 93fSh-G3ffh G2fSh-G2ffh 322Gh-3227h 322Sh-322fh 422Gh-4227h 422Sh-422fh 522Gh-5227h 522Sh-522fh i nt int i nt i nt int i nt i nt i nt int int int int 34 34 34 34 4 3 3 3 3 3 3 3 Help "This port can be assigned as a: primary (SOLCl) or secondary (SOLC2) sdlc port, primary (BISYNCI) or secondary (BISYNC2) bisync port, or as a serial port (Serial I through Serial S). Use the F5=Previous and the F6=Next keys to change this assignment. Conflicting assignments are marked with an asterisk and must be changed." 20 Programmable Option Select Namedltem II Prompt "Arbitration Level for SOLC" choi ce choice choice choice choice choice choice choice choice choice choi ce choi ce choi ce choice choi ce "Level_I" "Level_0" "Level_2" "Level_3" "Level_4" "Level_5" "Level_6" "Level_7" "Level_a" "Level_9" "Level - 10" "Level _11" "Level_12" "Level_13" "Level_l4" pos[I]=XXXX0001b pos[I]=XXXX0000b pos [1] =XXXX0010b pos[I]=XXXX0011b pos[I]=XXXX0100b pos[I]=XXXX0101b pos [1] =XXXX0110b pos [1]=XXXX0111b pos[I]=XXXXI000b pos [1] =XXXX1001b pos[I]=XXXXI010b pos [1] =XXXX1011b pos[1]=XXXXI100b pos[I]=XXXXl101b pos [1] =XXXX1110b arb arb arb arb arb arb arb arb arb arb arb arb arb arb arb 1 0 2 3 4 5 6 7 a 9 10 11 12 13 14 Help "This assignment need only be changed if it is in conflict with another assignment. Conflicting assignments are marked with an asterisk. Use the F5=Previous and the F6=Next keys to change arbitration level assignments. Using arbitration levels. this adapter accesses memory directly without burdening the computer's main microprocessor. An arbitration level of 0 has the highest priority. and increasing levels have corresponding decreased priority" II The card_id for this adapter is hex OOEFF. This is an ASCII representation of the 10 generated by the adapter. The high byte is followed by the low byte. The card_id is required for all AOFs. II The card_name is "IBM Multiprotocol Communications Adapter." The card_name is required for all AOFs. 11 The nbytes (NumBytes 2) in this file indicates the adapter uses two POS bytes located at hex 0102 and 0103. II This is the first named_item for the adapter. The title of the field is "Communications Port." The user can toggle between the 12 named_choices. Each named_choice has a unique pos_setting assigned to it in bit locations 1 through 4 of POS byte hex 0102 (pos [0]). Also shown is a resource_setting that corresponds to the pos_setting of the named_choice. The resources allocated in this named_item are 110 addresses and interrupt levels. A help string for this named_item is provided below the last named_choice. Programmable Option Select 21 II This is the second named_item for the adapter. The title of the field is "Arbitration Level for SDLe." The user can toggle between the 15 named_choices. Each named_choice has a unique pos_setting assigned to it in bit locations 0 through 3 of POS byte hex 0103 (pos [1]). Also shown is a resource_setting that corresponds to the pos_setting of the named_choice. The resources allocated in this named_item are arbitration levels. A help string for this named_item is provided below the last named_choice. 22 Programmable Option Select Index A D adapter configuration, order of 12 adapter description files 1 adapter 10 number 1 adapter identification 6, 10 adapter POS implementation 7 adapter setup 4, 7 address decode 3 address space, POS 3 arbitration level field 6 automatic configuration 1, 4, 11 device ROM segment address field 6 B backup configuration utility battery failure 11 bus contention 2 13 C card enable 4 card selected feedback register 3 CO SETUP 4 COSFOBK 3 change configuration utility 12 channel-check active indicator 5 channel-check status indicator 5 CMOS RAM, card 10 bytes 10 configuration error 11 configuration utilities 6 copy an option diskette utility 13 CRC error 11 F fairness enable bit 6 fairness feature 6 H help text 12 I I/O address decode 4 I/O device address field initial program load 8 6 p POS I/O address space 3, 4 POS overview 1 POS registers 3 POST error message files 11 power-on self-test 1 R reference diskette 10 restore configuration utility 13 Index 23 S SADOO - SAD15 8 set configuration program 10 setup procedures 2 setup, system board 3 subaddressing bits 8 subaddressing extension 8 system board setup 3 system configuration utilities 2, 10 system resources 10 V view configuration 24 Index 13 Micro Channel Adapter Design General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Design Considerations . . . . . . . . . . . . . . . . . . . . . .. Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal .................................... Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index 1 19 20 20 20 21 21 22 22 ........................................ 25 Micro Channel Adapter Design I Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. II Adapter Dimensions (8- or 16-Bit) . . . . . . . . . . . . . . . . . . Connector Dimensions (8- or 16-Bit) . . . . . . . . . . . . . . . . . Adapter Dimensions (8- or 16-Bit with Video Extension) Connector Dimensions (8- or 16-Bit with Video Extension) .. Adapter Dimensions (32-Bit) . . . . . . . . . . . . . . . . . . . . . . Connector Dimensions (32-Bit) . . . . . . . . . . . . . . . . . . . . Adapter Dimensions (32-Bit with Matched Memory) ...... Connector Dimensions (32-Bit with Matched Memory) Connector (Common Detail) . . . . . . . . . . . . . . . . . . . . . Typical Adapter Assembly . . . . . . . . . . . . . . . . . . . . . . Adapter Holder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Retainer . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Bracket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Load Current . . . . . . . . . . . . . . . . . . . . . . . . . Channel Voltage Regulation . . . . . . . . . . . . . . . . . . . . . Vendor 10 Assignments . . . . . . . . . . . . . . . . . . . . . . . . Micro Channel Adapter Design 2 3 4 5 6 7 8 9 10 11 12 13 15 19 20 23 General Guidelines This section provides some basic guidelines to design adapters for the Micro Channel architecture 16- and 32-bit products. Topics include physical specifications, power requirements and limitations, and configuration program support. The system board provides channel connectors to support the following types of adapters. Some systems do not support all types of adapters. See the system-specific technical references for more information. • • • • 16-bit adapter 16-bit adapter with video extension 32-bit adapter 32-bit adapter with matched-memory extension. Connector contacts are not required for signals not used by an adapter. See "Micro Channel Architecture" for more information on channel connectors and signals. Dimensions The following figures show the dimensions of each type of adapter and the associated mounting hardware. The tolerances shown include all individual process tolerances and are not cumulative. The maximum height for components mounted on the adapter is 15 millimeters (0.6 inch) on the component (A) side. The maximum height for pins and components on the B side of the adapter is 2 millimeters (0.078 inch). Adapters using CMOS technology should have all plated connector contacts the same length to reduce the exposure of incorrect bias to modules. Micro Channel Adapter Design 1 N "TI Q 3: . .,c:;• 0 0 ':I" III .,c CD ~ » Co - III :::J :::J '0 CD » Co c ~ -., III ., 3" '0 CD CD :::J cCD :::J i!i Qij fI) :::J fI) 0" fI) I .,0 .... 9J m a 121 Primary Datum III (2X) 3. 1700 0.078 PTH .125*;003 "T1 10· ...m e: 'o" () :::I :::I & ... c 3· m :::I UI o· :::I UI Cjii .........o Cfl OJ E (2X) 0.25 ..0.13 .010"'.005 (2X) Both Sides 11.905 1[1] 2.275 1+10.025 (.001) OJ Dimensions CrlUoal 10 FunoUon ill Component Free Area Both Sides c III 10· :::I • (58X) Both Sides (Tab 10 Tab) [!] Carda Using CMOS Technology Should Make All Card Tabs the Same Length 10 Reduce the Exposure of Incorrect Blae 10 the Modulae 1[II ~ 3: n "TI if c: ~ (I) ~ ~ 0 » Q. 0 ::T I» ::::I ::::I !!. » Q. I» I» 't:I S' c ~ 3" (I) ¥ III cCD III ;Q CD I ~ III ::::I ::::I 0' ::::I 0 ... ~ t{I OJ ;:; :IE ;:; ::T a:CD< 0 m ~ CD ::::I III 0' 2. 121 Primary Datum III "T1 !C. c: ... Primary Datum CD [I) 0.927:0: 0.025 .0385:0:.001 ~ I_ 1.57:1: 0.127 (") 0.927:0: 0.025 .082:0:.005 0 ;:, [I) ;:, CD 0 -... 0 c 3· CD ;:, UI 0" ;:, UI co 0 ........ I s:: o· ... 0 (") J IIJ ;:, ;:, !!. > 0- -... IIJ "C CD cCD UI !C. ;:, UI 0) I OJ ;:+ :IE JI 2.275 12Xl0.25:o:D.13 ~ .010:0:.005 1---'--'-- ;:+ J < .02:0:.001 0: CD 0 m x I2Xl Both Sides ~ [I) 2.42 .075 CD ;:, 1... 10.025 (.001) 81 [I) 186X) Both Sides CTabtoTab) UI o· 2- IT] Dimensions CrlUcal to Function o o Component Free Area Both Sidee cards Using CMOS Technology Should Make All card Tabe the Same Length to Reduce the Exposure of Incorrect Bias to the Modulee CI) " rE' s::: c:;. ., 0 (") ~ I» :::J :::J ~ > a. I» 1J CD ., C CD UI rE' :::J c: ., CD ~ > a. ~ Primary Datum - I» 1J CD ., C 3' CD :::J UI O· :::J UI c;,) I\) I m e A IIJ "T1 ~i ... c: Primary Datum (I) m 1.57*0.127 .062"'.005 !» (") 0 :l :l -... CD 0 0 c 3" CD :l I/) 0" til 0 dd •• !i~ 7 :l I/) c;.; I\) • aJ (2X) 0.25"'0.13 .010*.005 (92X) Both Sides (Tab to Datum) .e Itl 0.025 /'001)81 (92X) Both Sides (Tab to Tab) [II Dimensions Critical to Function o Component Free Area Both Sides e!] Cards Using CMOS Technology Should Make All Card Tabs the Same Length to Reduce the Exposure of Incorrect Bias to the Modules lID ii: "... til" c: CD ... ;"'I n';1" » Co 5" 0 I» :::J :::J !!. ~ I» "9CD ... C m c:::J ~ Primary Datum I» "9CD ... C 3" CD :::J UI 0" :::J UI C3 I\) I m ;::; ~ ;:::;: ';1" ii: I» a- ';1" CD Co ii: CD 3 ...0 :$ A I1J ." ~. ...c::CD !lD (") 0 ::J ::J CD C"l -... 0 c 3" CD ::J UI o· ::J UI I2Xl 0.25",0.13 (;) .010'" .005 I\) I OJ ::+ 3: ;::;: 0 3: n ... (") ':J" ':J" ~':J" CD [I] Dimensions Critical to Function 3: 3 [!] Component Fraa Area Both Sides [I] Carda Using CMOS Taohnology ShOuld Make All Card TIlbII the Same I» ::J ::J Co )0- CD !. Co III '"0 ... CD C CD UI il ::J fa [1] ~ ...0 ~ l.8ngth to Reduce the Expoaura of Incorraot Bias to the Modules ~ 0 ~ O t!- +i ~ ~ (2X) 0.25:t:0.13 .010:t:.005 ~ ~ R TYP 80th Sides A 45 TYP 80th Sides 8 0.25:t:0.13 .010:t:.005 Figure 9. Connector (Common Detail) 10 Micro Channel Adapter Design Rlvet~'" "~~ ". ~t..... ~ .......... 0- • Holder l. Materials: Holder and Retainer· Polycarbonate UL 94 V-o Bracket - AISI Type 302 1/4 Hard Stainless Steel Figure 10. Typical Adapter Assembly Micro Channel Adapter Design 11 15.8 In (&X) R 1 N I" (4X) R 1 t:: -~ (5X) R 0.5 '" ~ CD ~ ~ to- Iii (2X)R2 (2X) 1.5 .0" 3.18 + 0.13thru 2X)1.5~ V82 0 .0" 4 10.6 -0.5 3 14 -0.5 (2X) R 1 R2 ~/II (12X) RO.5 ~ (4X) 1.5 D Figure 11. Adapter Holder 12 Micro Channel Adapter Design ij L~J t (5X) R3 53.5 A1 (2X)R3.5 J (3X) R2 /!.-, '--- ~ ~ +1 A "'! (2X) 5..().5 '" 25.2 U> '"ci I "": d'" +1 I ci0/50 JJS Figure 8. Receiving Data Timings System Sending Data The following describes the typical sequence of events when the system is sending data to the auxiliary device. A graphic representation showing the timing relationships is presented in Figure 9 on page 14. 1. The system checks for an auxiliary device transmission in process. If a transmission is in process and beyond the 10th clock, the system must receive the data. 2. The auxiliary device checks the 'clock' line. If the line is inactive, an I/O operation is not allowed. Keyboard and Auxiliary Device Controller (Type 1) 13 3. The auxiliary device checks the 'data' line. If the line is inactive, the system has data to transmit. The 'data' line is set inactive when the start bit (always 0) is placed on the 'data' line. 4. The auxiliary device sets the 'clock' line inactive. The system then places the first bit on the 'data' line. Each time the auxiliary device sets the 'clock' line inactive, the system places the next bit on the 'data' line until all bits are transmitted. 5. The auxiliary device samples the 'data' line for each bit while the 'clock' line is active. Data must be stable within 1 microsecond after the rising edge of the 'clock' line. 6. The auxiliary device checks for a positive level stop bit after the 10th clock. If the 'data' line is inactive, the auxiliary device continues to clock until the 'data' line becomes active, then clocks the line-control bit, and at the next opportunity sends a Resend command to the system. 7. The auxiliary device pulls the 'data' line inactive, producing the Ii ne-control bit. 8. The system can pull the 'clock' line inactive, inhibiting the auxiliary device. T7 T8 T9 Timing Parameter MinIMax Duration of ClK inactive Duration of ClK active Time from inactive to active elK transition. used to time when the auxiliary device samples DATA 30/50 ps 30/50 ps Figure 9. Sending Data Timings 14 Keyboard and Auxiliary Device Controller (Type 1) 5125 ps Signals The keyboard and auxiliary device signals are driven by open-collector drivers pulled to 5 Vdc through 10-kilohm resistors. The following lists the characteristics of the signals. Sink Current High-Level Output Voltage Low-Level Output Voltage High-Level Input Voltage Low-Level Input Voltage 20mA 5.0 Vdc minus pullup 0.5 Vdc 2.0 Vdc 0.8 Vdc Maximum Minimum Maximum Minimum Maximum Figure 10. Keyboard and Auxiliary Device Signals Connector The keyboard and auxiliary device connectors use 6-pin miniature DIN connectors. The signals and voltages are the same for both connectors, and are assigned as shown in the following figure. Pin 110 Signal Name 1/0 2 NA NA NA Data Reserved Ground +5Vdc Clock Reserved 3 4 5 6 1/0 NA Figure 11. Keyboard and Auxiliary Device Connector Information Keyboard and Auxiliary Device Controller (Type 1) 15 Notes: 16 Keyboard and Auxiliary Device Controller (Type 1) Serial Port Controller (Types 1 and 2) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communications Application . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Transmitter Holding Register (Hex nF8) ................ Receiver Buffer Register (Hex nF8) . . . . . . . . . . . . . . . . . . . Divisor Latch Registers (Hex nF8 and nF9) .............. Interrupt Enable Register (Hex nF9) . . . . . . . . . . . . . . . . . . . Interrupt Identification Register (Hex nFA) ... . . . . . . . . . . .. FIFO Control Register (Hex nFA) . . . . . . . . . . . . . . . . . . . . . Line Control Register (Hex nFB) . . . . . . . . . . . . . . . . . . . . Modem Control Register (Hex nFC) . . . . . . . . . . . . . . . . . . Line Status Register (Hex nFD) . . . . . . . . . . . . . . . . . . . . . Modem Status Register (Hex nFE) . . . . . . . . . . . . . . . . . . . Scratch Register (Hex nFF) . . . . . . . . . . . . . . . . . . . . . . . . FIFO Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Interrupt Mode Operation . . . . . . . . . . . . . . . . . . . . . FIFO Polled Mode Operation . . . . . . . . . . . . . . . . . . . . . . . Serial Port Controller Programming Considerations ......... Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem-Control Input Signals . . . . . . . . . . . . . . . . . . . . . . Modem-Control Output Signals . . . . . . . . . . . . . . . . . . . . . Voltage Interchange Information . . . . . . . . . . . . . . . . . . . . . . Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 20 21 21 21 22 22 23 Index 24 ........................................ Serial Port Controller (Types 1 and 2) 1 2 3 3 4 5 5 6 7 9 11 12 14 17 Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. II Serial Port Controller Block Diagram . . . . . . . . . . . . . . . . Serial Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Register Addresses . . . . . . . . . . . . . . . . . . . . Transmitter Holding Register . . . . . . . . . . . . . . . . . . . . . Receiver Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . Divisor Latch Register, Low Byte (Hex nF8) ............ Divisor Latch Register, High Byte (Hex nF9) ........... Baud Rates at 1.8432 MHz . . . . . . . . . . . . . . . . . . . . . . . Interrupt Enable Register (Hex nF9) . . . . . . . . . . . . . . . . . Interrupt Identification Register (Hex nFA) ............ Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . FIFO Control Register (Hex nFA) . . . . . . . . . . . . . . . . . . Trigger Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Control Register (Hex nFB) . . . . . . . . . . . . . . . . . . Stop Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Control Register (Hex nFC) . . . . . . . . . . . . . . . . Line Status Register (Hex nFD) . . . . . . . . . . . . . . . . . . . Modem Status Register (Hex nFE) . . . . . . . . . . . . . . . . . Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Connector Signal and Pin Assignments ...... Serial Port Controller (Types 1 and 2) 2 3 4 4 5 5 6 6 7 8 9 10 10 11 12 12 12 14 17 23 23 Description The serial port controller is programmable and supports asynchronous communications. The controller automatically adds and removes start, stop, and parity bits. A programmable baud-rate generator allows operation from 50 baud to 19,200 baud. The controller supports 5-, 6-, 7- and 8-bit characters with 1, 1.5, or 2 stop bits. A prioritized interrupt system controls transmit, receive, error, and line status and data-set interrupts. The serial port controller provides the following functions: • Full double buffering in the character mode, eliminating the need for precise synchronization • False-start bit detection • Line-break generation and detection • Modem control functions: Clear to send (CTS) Request to send (RTS) Data set ready (DSR) Data terminal ready (DTR) Ring indicator (RI) Data carrier detect (DCD). Two types of serial port controllers have been used on the system boards. To programs, the Type 1 controller appears to be identical to the serial portion of the IBM Personal Computer AT IBM Personal Computer Serial/Parallel Adapter. The Type 2 controller incorporates all functions of the Type 1 and also provides support of the first-in-first-out (FIFO) mode. Note: Some systems using the Type 2 controller do not support the FIFO mode. For information about individual systems refer to the system-specific technical reference manuals. Support for the Type 1 controller is restricted to the functions that are identical to the NS16450. Using the Type 1 controller in the FIFO mode may result in nondetectable data errors. See "Registers" on page 3 for detailed FIFO information. Serial Port Controller (Types 1 and 2) 1 The following figure is a block diagram of the serial port controller. Chip Select AO- A16 Address Decode Register Select Data Bus Interrupt Asynchronous Communications Controller 11.8432 Mhz Oscillator lElA Receivers I I I I 25-Pin II Connector - I J I I EIA Drivers ~ Figure 1. Serial Port Controller Block Diagram Communications Application The serial output port can be addressed as either serial output port 1 (Serial 1) or serial output port 2 (Serial 2). In this section, serial port register addresses contain an n. The n can be either 03 for Serial 1, or 02 for Serial 2. The port assignments are controlled by POS during system board setup. Two interrupt lines are provided to the system: Interrupt level 4 (IRQ4) is for Serial 1 and interrupt level 3 (IRQ3) is for Serial 2. For the serial port controller to send interrupts to the interrupt controller, bit 3 of the Modem Control register must be set to 1. Any interrupts allowed by the Interrupt Enable register will cause an interrupt. 2 Serial Port Controller (Types 1 and 2) The data format is shown in the following figure. Figure 2. Serial Port Data Format Data bit 0 (DO) is the first bit to be sent or received. The controller automatically inserts the start bit, the correct parity bit (if programmed to do so), and the stop bits (1, 1.5, or 2 depending on the command in the Line Control register). Programmable Baud-Rate Generator The controller has a programmable baud-rate generator that can divide the clock input (1.8432 MHz) by any divisor from 1 to 65,535. The output frequency of the baud-rate generator is the baud rate multiplied by 16. Two a-bit latches store the divisor in a 16-bit binary format. The divisor latches are loaded during setup to ensure desired operation of the baud-rate generator. When either of the divisor latches is loaded, a 16-bit baud counter is immediately loaded. This prevents long counts on the first load. Registers The controller has several accessible registers. These control the operations of the controller and transmit and receive data. The system programmer can gain access to or control any of the controller registers through the system microprocessor. The bit definitions of the Interrupt Enable register, Interrupt Identification register, and Line Status register have been modified from the NS16450 registers, and a FIFO Control register has been added to support the FIFO mode. Note: Using the Type 1 controller in the FIFO mode may result in nondetectable data errors. See "Interrupt Identification Register (Hex nFA)" on page 7 to see how programs can determine if the FIFO mode can be safely used. SerIal Port Controller (Types 1 and 2) 3 Specific registers are selected according to the following figure. DLAB State * 0 0 1 1 0 X X X X X X X Port Addre.. (Hex) RIW Register OnF8·· OnF8·· OnF8·· OnF9·· OnF9·· OnFA •• OnFA •• OnFB •• OnFC·· OnFD·· OnFE •• OnFF·· W R R/W RIW RIW R W RIW RIW R R RIW Transmitter Holding Register n Receiver Buffer Register n Divisor Latch, Low Byte Divisor Latch, High Byte Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register • The DLAB state is controlled by bH 7 of the Line Control register • •• The n determines the port selected; 3 is for Serial 1, and 2 is for Serial 2. Figure 3. Serial Port Register Addresses Transmitter Holding Register (Hex nFa) The Transmitter Holding register contains the character to be sent. Bit 0 is the least-significant bit and the first bit sent serially. as shown in the following figure. Bit FuncUon 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 4. Transmitter Holding Register 4 Serial Port Controller (Types 1 and 2) Receiver Buffer Register (Hex nF8) The Receiver Buffer register contains the received character. Bit 0 is the least-significant bit and the first bit received serially, as shown in the following figure. Bit Function 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 5. Receiver Buffer Register Divisor Latch Registers (Hex nF8 and nF9) The Divisor Latch registers are used to program the baud-rate generator. The values in these two registers form the divisor of the clock input (1.8432 MHz), which establishes the desired baud rate. Bit Function 7 6 5 4 3 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Figure 6. Divisor Latch Register, Low Byte (Hex nF8) Serial Port Controller (Types 1 and 2) 5 Bit Function 7 6 5 4 3 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Figure 7. Divisor Latch Register, High Byte (Hex nF9) The following figure illustrates the use of the baud-rate generator with a frequency of 1.8432 MHz. For baud rates of 19,200 and below, the error obtained is minimal. Note: Data speed should not exceed 19,200 baud. Desired Baud Rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 Divisor Used to Generate16x Clock (Decimal) (Hex) 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 Percent of Error Difference between Desired and Actual 0900 0600 0417 0359 0300 0180 0.026 0.058 ooeo 0060 0040 003A 0030 0020 0018 0010 0.69 oooe 0006 Figure 8. Baud Rates at 1.8432 MHz Interrupt Enable Register (Hex nF9) This 8-bit register allows the four types of controller interrupts to separately activate the 'chip interrupt' output signal. The interrupt system can be totally disabled by setting bits 0 through 3 of the Interrupt Enable register to O. Similarly, by setting the appropriate bits of this register to 1, selected interrupts can be enabled. 6 Serial Port Controller (Types 1 and 2) Disabling the interrupts inhibits the 'chip interrupt' output signal from the controller. All other system functions operate normally, including the setting of the Line Status and Modem Status registers. Bit Function 7-4 3 2 Reserved = 0 Modem-Status Interrupt Receiver-line-Status Interrupt Transmitter-Holding-Register-Empty Interrupt Received-Data-Available Interrupt (Character and FIFO Mode) and Time-Out Interrupts (FIFO Mode Only) o Figure 9. Interrupt Enable Register (Hex nF9) Bits 7 - 4 These bits are reserved and always set to O. Bit 3 When set to 1, this bit enables the modem-status interrupt. Bit 2 When set to 1, this bit enables the receiver-line-status interrupt. Bit 1 When set to 1, this bit enables the transmitter-holdingregister-empty interrupt. Bit 0 When set to 1, this bit enables the received-data-available interrupt. In the FIFO mode, this bit also enables the time-out interrupts. Interrupt Identification Register (Hex nFA) To minimize programming overhead during data character transfers, the controller prioritizes interrupts into four levels: • • • • • Priority 1 - Receiver-line-status Priority 2 - Received-data-available Priority 2 - Time-out (FIFO mode only) Priority 3 - Transmitter-holding-register-empty Priority 4 - Modem status. Information about a pending interrupt is stored in the Interrupt Identification register. When this register is addressed, the pending interrupt with the highest priority is held and no other interrupts are acknowledged until the system microprocessor services that interrupt. Serial Port Controller (Types 1 and 2) 7 BII Function 7,6 5, 4 3 2 1 FIFO Registers Enabled Reserved = 0 Interrupt ID, Bit 2 Interrupt ID, Bit 1 Interrupt ID, Bit 0 Interrupt Pending = 0 o Figure 10. Interrupt Identification Register (Hex nFA) Bits 7,6 Programs can determine whether a Type 1 or a Type 2 controller is present by reading these two bits when bit 0 of the FIFO Control register is set to 1. If bits 7 and 6 are set to 1, the Type 2 controller is present and FIFO support is provided. If bit 6 is set to 0, the controller is a Type 1 and FIFO mode should not be used. Note: Some systems using the Type 2 controller do not support the FIFO mode. For information about individual systems refer to the system-specific technical reference manuals. Bits 5, 4 These bits are reserved and always set to O. Bit 3 In the FIFO mode, this bit is set to 1, along with bit 2, to indicate that a time-out interrupt is pending. In the character mode, this bit is always set to O. Bits 2, 1 These two bits identify the pending interrupt with the highest priority, as shown in Figure 11 on page 9. Bit 0 When this bit is set to 1, no interrupt is pending, and polling (if used) continues. When this bit is set to 0, an interrupt is pending, and the contents of this register can be used as a pointer to the appropriate interrupt service routine. This bit can be used in either hard-wired, prioritized, or polled conditions to indicate if an interrupt is pending. 8 Serial Port Controller (Types 1 and 2) Bit. Priority Type Cau•• None None 3 210 o 001 Int.rrupt R•••t Control o 110 Highest Receiver Line Status Overrun, Parity, or Framing Error or Break Interrupt Read the Line Status Register. o 100 Second Received Data Available Data is in the Receiver Buffer or the Trigger Level Has Been Reached. Read the Receiver Buffer Register or the FIFO Register Drops Below the Trigger Level. 1* 1 00 Second Character Time-Out Indication No Characters Have Been Removed From or Put Into the Receiver FIFO Register During the Last Four Character Times, and at Least 1 Character is in it at This Time. Read the Receiver Buffer Register. o 010 Third Transmitter Holding Register Empty Transmitter Holding Register is Empty. Read the Interrupt Identification Register or Write to Transmitter Holding Register. 0000 Fourth Modem Status Change in Signal Status From Modem. Read the Modem Status Register. * FIFO Mode Only Figure 11. Interrupt Control Functions FIFO Control Register (Hex nFA) The FIFO Control register is a write-only register at the same location as the read-only Interrupt Identification register. The FIFO Control register enables the FIFO registers, clears the FIFO registers, and sets the Receiver FIFO register trigger level. Note: The Transmitter and Receiver FIFO registers are not accessible serial controller registers. Serial Port Controller (Types 1 and 2) 9 The contents of the FIFO Control register are shown in the following figure. Bit Function 7. 6 5-3 2 1 Receiver FIFO Register Trigger Reserved = 0 Transmitter FIFO Register Reset Receiver FIFO Register Reset FIFO Enable o Figure 12. FIFO Control Register (Hex nFA) Bits 7,6 BIts 7 6 These bits indicate the trigger level for the receiver-FIFO-register interrupt, as shown in the following figure. Receiver FIFO Register Trigger Level o0 o1 1 0 1 1 01 Byte 04 Bytes 08 Bytes 14 Bytes Figure 13. Trigger Level Bits 5 - 3 These bits are reserved and always set to O. Bit 2 When this bit is set to 1, all bytes in the Transmitter FIFO register are cleared and its counter logic is reset to O. The Transmitter Shift register is not cleared. The 1 written to this bit position is self-clearing. Bit 1 When this bit is set to 1, all bytes in the Receiver FIFO register are cleared and its counter logic is cleared to o. The Transmitter Shift register is not cleared. The 1 written to this bit position is self-clearing. Bit 0 When this bit is set to 1, both the Transmitter and Receiver FIFO registers are enabled. When set to 0, this bit clears all bytes in both FIFO registers. When the mode changes from the FIFO mode to the character mode or the character mode to the FIFO mode, data is automatically cleared from the FIFO registers. This bit must be set to 1 when other FIFO Control register bits are written or the bits will not be programmed. 10 Serial Port Controller (Types 1 and 2) Line Control Register (Hex nFB) The format of asynchronous communications is programmed through the Line Control register. Bit Function 7 Divisor Latch Access Bit Set Break Stick Parity Even Parity Select Parity Enable Number of Stop Bits Word Length Select, Bit 1 Word Length Select, Bit 0 6 5 4 3 2 1 0 Figure 14. Line Control Register (Hex nFB) Bit 7 This bit must be set to 1 during a read or write operation to gain access to the divisor latches of the baud-rate generator. This bit must be set to 0 to gain access to the Receiver Buffer, Transmitter Holding, or Interrupt Enable registers. Bit 6 When this bit is set to 1, set break is enabled. The serial output is forced to the spacing state and remains there regardless of other transmitter activity. When this bit is set to 0, set break is disabled. Bit 5 When bits 5, 4, and 3 are set to 1, the parity bit is sent and checked as a logical O. When bits 5 and 3 are set to 1, and bit 4 is set to 0, the parity bit is sent and checked as a logical 1. If bit 5 is set to 0, stick parity is disabled. Bit 4 When this bit and bit 3 are set to 1, an even number of logical 1's are transmitted and checked in the data word bits and parity bit. When this bit is set to 0, and bit 3 is set to 1, an odd number of logical1's are transmitted and checked in the data word bits and parity bit. Bit 3 When set to 1, a parity bit is generated (transmit data) or checked (receive data) between the last data-word bit and stop bit of the serial data. (The parity bit produces an even or odd number of 1's when the data-word bits and the parity bit are summed.) Serial Port Controller (Types 1 and 2) 11 Bit 2 This bit, with bits 0 and 1, specifies the number of stop bits in each serial character sent or received, as shown in the following figure. BIt2 Word Length • Number of Stop Bits 0 1 N/A 5-Bits 6-Bits 7-Bits 8-Bits 1 1.5 2 2 2 • Word length is specified by bits 1 and 0 in this register. Figure 15. Stop Bits Bits 1, 0 Bit 10 These bits specify the number of bits in each serial character sent or received. Word length is selected, as shown in the following figure. Word Length 5-Bits 6-Bits 7-Bits 8-Bits 00 01 10 11 Figure 16. Word Length Modem Control Register (Hex nFC) This 8-bit register controls the data exchange with the modem, data set, or peripheral device emulating a modem. Bit Function 7-5 4 3 2 1 Reserved = 0 Loop Out 2 Out 1 Request-to-Send Data-Terminal-ReadY o Figure 17. Modem Control Register (Hex nFC) Bits 7 - 5 12 These bits are reserved and always set to O. Serial Port Controller (Types 1 and 2) Bit 4 This bit provides a local loopback feature for diagnostic testing of the serial controller. When bit 4 is set to 1: • Transmitter-serial output is set to the marking state. • Receiver-serial input is disconnected. • Output of the Transmitter Shift register is "looped back" to the Receiver Shift register input. Note: The Transmitter and Receiver Shift registers are not accessible serial controller registers. • The modem control inputs (-CTS, -OSR, -OCO, and -RI) are disconnected. • The modem control outputs (-OTR, -RTS, -OUT 1, and -OUT 2) are internally connected to the four modem control inputs. • The modem control output pins are forced inactive. When the serial port is in diagnostic mode, transmitted data is immediately received. This mode allows the system microprocessor to verify the transmit-data and receive-data paths of the serial port. When the serial port is in diagnostic mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but their sources are the lower 4 bits of the Modem Control register instead of the four modem control input signals. The interrupts are still controlled by the Interrupt Enable register. Bit 3 This bit controls the '-output 2' signal (-OUT 2), which is an auxiliary user-designated interrupt enable signal. -OUT 2 controls the interrupt signal to the channel. Setting this bit to 1 enables the interrupt. Setting this bit to 0 disables the interrupt. Bit 2 This bit controls the '-output l' signal (-OUT 1), which is an auxiliary user-designated output signal. When this bit is set to 1, -OUT 1 is forced active. When this bit is set to 0, -OUT 1 is forced inactive. Bit 1 This bit controls the '-request to send' signal (-RTS) modem control output. When this bit is set to 1, -RTS is forced active. When this bit is set to 0, -RTS is forced inactive. Serial Port Controller (Types 1 and 2) 13 This bit controls the '-data terminal ready' signal (-DTR) modem control output. When this bit is set to 1, -DTR is forced active. When this bit is set to 0, -DTR is forced inactive. Bit 0 Line Status Register (Hex nFD) This 8-bit read-only register provides the system microprocessor with status information about the data transfer. Writing to this register can produce unpredictable results. Bit Function 7 6 5 4 3 2 1 Error in Receiver FIFO Register Transmitter Shift Register Empty Transmitter Holding Register Empty Break Interrupt Framing Error Parity Error Overrun Error Data Ready o Figure 18. Line Status Register (Hex nFO) Bit 7 This bit is set to 1 when there is at least one parity error, framing error, or break indication in the Receiver FIFO register. If there are no subsequent errors in the Receiver FIFO register, this bit is set to 0 when the system microprocessor reads the Line Status register. In the character mode, this bit is always set to O. Bit 6 This bit is set to 1 when the Transmitter Holding register and the Transmitter Shift register are both empty. This bit is set to 0 when either the Transmitter Holding register or the Transmitter Shift register contains a data character. In the FIFO mode, this bit is set to 1 when the Transmitter FIFO register and the Transmitter Shift register are both empty. Bit 5 14 This bit indicates that the serial port controller is ready to accept a new character for transmission. This bit is set to 1 when a character is transferred from the Transmitter Holding register to the Transmitter Shift register. This bit is set to 0 when the system microprocessor loads the Transmitter Holding register. Serial Port Controller (Types 1 and 2) This bit also causes the controller to issue an interrupt to the system microprocessor when bit 1 in the Interrupt Enable register is set to 1. In the FIFO mode, this bit is set to 1 when the Transmitter FIFO register is empty. It is set to 0 when at least 1 byte is written to the Transmitter FIFO register. 8114 This bit is set to 1 when the received data input is held in the spacing state for longer than a fullword transmission time (that is, the total time of start bit + data bits + parity + stop bits). This bit is set to 0 when the system microprocessor reads the contents of the Line Status register. When a break interrupt occurs, only one zero character is loaded into the Receiver FIFO register. The next character is loaded after the receiver serial input changes to the marking state and receives the next valid start bit. Nole: Bits 1 through 4 are the error conditions that produce a receiver-line-status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. 8113 This bit is set to 1 when the stop bit, following the last data bit or parity bit, is at a spacing level. This indicates that the received character did not have a valid stop bit. This bit is set to 0 when the system microprocessor reads the contents of the Line Status register. Nole: In the FIFO mode, the framing error (or parity error for bit 2) is associated with the particular character in the Receiver FIFO register it applies to. The error is indicated to the system microprocessor when its associated character is at the top of the Receiver FIFO register. 8112 This bit is set to 1 when a parity error is detected (the received character does not have the correct even or odd parity, as selected by the even-parity-select bit). This bit is set to 0 when the system microprocessor reads the contents of the Line Status register. See the note in bit 3 for more information. Serial Port Controller (Types 1 and 2) 15 Bit 1 When set to 1, this bit indicates that data in the Receiver Buffer register was not read by the system microprocessor before the next character was transferred into the Receiver Buffer register, destroying the previous character. This bit is set to 0 when the system microprocessor reads the contents of the Line Status register. If the FIFO mode data continues to fill the Receiver FIFO register beyond the trigger level, an overrun error will occur only after the Receiver FIFO register is full and the next character has been completely received in the Receiver Shift register. An overrun error is indicated to the system microprocessor when it happens. The character in the Receiver Shift register is overwritten, but it is not transferred to the Receiver FIFO register. Bit 0 16 This bit is the receiver data-ready indicator. It is set to 1 when a complete incoming character has been received and transferred into the Receiver Buffer register or the Receiver FIFO register. This bit is set to 0 by reading the Receiver Buffer register or the Receiver FIFO register. Serial Port Controller (Types 1 and 2) Modem Status Register (Hex nFE) This B-bit register provides the current state of the control lines from the modem (or external device) to the system microprocessor. Also, bits 3 through 0 of this register provide change information. These four bits are set to 1 whenever a control input from the modem changes state. They are set to 0 whenever the system microprocessor reads this register. Bit Function 7 6 Data-Carrier-Detect Ring Indicator Data-Set-Ready Clear-to-Send Delta-Data-Carrier-Detect Trailing Edge Ring Indicator Delta-Data-Set-Ready DeHa-Clear-to-Send 5 4 3 2 1 o Figure 19. Modem Status Register (Hex nFE) BI17 This bit is the inverted '-data carrier detect' signal (-DCD) modem control input. If bit 4 of the Modem Control register is set to 1, this bit is equivalent to bit 3 in the Modem Control register. BI16 This bit is the inverted '-ring indicator' signal (-RI) modem control input. If bit 4 of the Modem Control register is set to 1, this bit is equivalent to bit 2 in the Modem Control register. BI15 This bit is the inverted '-data set ready' signal (-DSR) modem control input. If bit 4 of the Modem Control register is set to 1, this bit is equivalent to bit 0 in the Modem Control register. BI14 This bit is the inverted '-clear to send' signal (-CTS) modem control input. If bit 4 of the Modem Control register is set to 1, this bit is equivalent to bit 1 in the Modem Control register. Bit 3 When set to 1, this bit indicates that the '-data carrier detect' signal (-DCD) modem control input has changed state since the last time it was read by the system microprocessor. Serial Port Controller (Types 1 and 2) 17 Note: Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is generated. Bit 2 When set to 1, this bit indicates that the '-ring indicator' signal (-RI) modem control input has changed from an active condition to an inactive condition. Bit 1 When set to 1, this bit indicates that the '-data set ready' signal (-DSR) modem control input has changed state since the last time it was read by the system microprocessor. Bit 0 When set to 1, this bit indicates that the '-clear to send' signal (-CTS) modem control input has changed state since the last time it was read by the system microprocessor. Scratch Register (Hex nFF) This register does not control the serial port controller in any way. It is used by the system microprocessor to temporarily hold data. FIFO Modes of Operation When in the FIFO mode, the controller can operate in either the interrupt mode or the polled mode. FIFO Interrupt Mode Operation When the Receiver FIFO register and the receiver interrupts are enabled (FIFO Control register bit 0 and Interrupt Enable register bit 0 are set to 1), receiver interrupts occur as follows: 1. A received-data-available interrupt is issued to the system microprocessor when the Receiver FIFO register has reached its programmed trigger level; it is cleared as the Receiver FIFO register drops below the programmed trigger level. 2. The Interrupt Identification register's received-data-available indication also occurs when the Receiver FIFO register's trigger level is reached and, like the interrupt, it is cleared when the Receiver FIFO register drops below the trigger level. 3. The receiver-line-status interrupt (Interrupt Identification register = hex 06), has higher priority than the received-data-available interrupt (Interrupt Identification register = hex 04). 18 Serial Port Controller (Types 1 and 2) 4. Bit 0 (data ready) of the Line Status register is set to 1 when a character is transferred from the Receiver Shift register to the Receiver FIFO register. It is set to 0 when the Receiver FIFO register is empty. When the Receiver FIFO register and receiver interrupts are enabled, register time-out interrupts occur as follows: 1. A FIFO time-out interrupt occurs if the following conditions exist: • At least 1 character is in the Receiver FIFO register. • The last character was received more than four continuous character times ago (if 2 stop bits are programmed, the second one is included in this time delay). • The most recent system microprocessor read of the Receiver FIFO register was longer than four continuous character times ago. This causes a maximum character-received to interrupt-issued delay of 160 ms at 300 baud with a 12-bit character. 2. Character times are calculated by using the 'receiver clock' (RCLK) input for a clock signal (this makes the delay proportional to the baud rate). 3. When a time-out interrupt has occurred, it is cleared, and the timer is reset when the system microprocessor reads one character from the Receiver FIFO register. 4. When a time-out interrupt has not occurred, the time-out timer is reset after a new character is received or after the system microprocessor reads the Receiver FIFO register. When the Transmitter FIFO register and transmitter interrupts are enabled (FIFO Control register bit 0 and Interrupt Enable register bit 1 are set to 1), transmitter interrupts occur as follows: 1. The transmitter-holding-register interrupt (02) occurs when the Transmitter FIFO register is empty; it is cleared when the Transmitter Holding register is written to (1 to 16 characters may be written to the Transmitter FIFO register while this interrupt is being serviced) or the Interrupt Identification register is read. 2. The transmitter-FIFO-register-empty indications are delayed one character time minus the last stop bit time whenever both of the following occur: Serial Port Controller (Types 1 and 2) 19 • Bit 5 (transmitter holding register empty) of the Line Status register is set to 1. • There have not been at least 2 bytes in the Transmitter FIFO register at the same time since the last time bit 5 of the Line Status register was set to 1. The first transmitter interrupt after changing bit 0 in the FIFO Control register is immediate, if enabled. Character time-out and Receiver FIFO register trigger-level interrupts have the same priority as the current received-data-available interrupt; transmitter-FIFO-register-empty has the same priority as the current transmitter-holding-register-empty interrupt. FIFO Polled Mode Operation To put the controller in the FIFO polled mode, set bit 0 of the FIFO Control register to 1 and set bits 0 through 3 of the Interrupt Identification register to O. The Receiver and Transmitter FIFO registers are controlled separately; either one or both can be in the polled mode of operation. In the FIFO polled mode of operation, the system microprocessor checks Receiver and Transmitter FIFO register status through the Line Status register: • Line Status register bit 0 is set to 1, as long as 1 byte is in the Receiver FIFO register. • Line Status register bits 1 through 4 specify which errors have occurred. Character error status is handled the same way as when in the interrupt mode; the Interrupt Identification register is not affected, because bit 2 of the Interrupt Enable register is set to O. • Line Status register bit 5 indicates when the Transmitter FIFO register is empty. • Line Status register bit 6 indicates that both the Transmitter FIFO register and Transmitter Shift register are empty. • Line Status register bit 7 indicates if any errors in the Receiver FIFO register; 20 Serial Port Controller (Types 1 and 2) There is no trigger level reached or time-out condition indicated in the FIFO polled mode; however, the Receiver and Transmitter FIFO registers are still fully capable of holding characters. Serial Port Controller Programming Considerations The serial port uses either the Type 1 or Type 2 serial communications controller. The following should be considered when programming the serial controller: • TheType 1 serial controller does not support the FIFO mode. For more information, refer to the "Interrupt Identification Register (Hex nFA)" on page 7. • Some systems using the Type 2 controller do not support the FIFO mode. For more information, refer to the system-specfic technical reference manuals. • The serial port can be configured to either Serial 1 or Serial 2 using the system configuration utilities programs. • Before changing the Line Control register, make sure the Transmitter Holding register is empty. See "Compatibility" for additional programming considerations. Signal Descriptions Modem-Control Input Signals The following are input signals from the modem or external device to the controller. Bits 7 through 4 in the Modem Status register indicate the condition of these signals. Bits 3 through 0 monitor these signals to indicate when the modem changes state. -Clear to Send (-CTS): When active, this signal indicates that the modem is ready for the serial port to transmit data. Serial Port Controller (Types 1 and 2) 21 -Data Set Ready (-DSR): When active, this signal indicates that the modem or data set is ready to establish the communications link and transfer data with the controller. -Ring Indicator (-RI): When active, this signal indicates that the modem or data set detected a telephone ringing signal. -Data Carrier Detect (-DCD): When active, this signal indicates that the modem or data set detected a data carrier. Modem-Control Output Signals The following are controller output signals. All are set inactive by a master reset operation. These signals are controlled by bits 3 through 0 in the Modem Control register. -Data Terminal Ready (-DTR): When active, this signal informs the modem or data set that the controller is ready to communicate. -Request to Send (-RTS): When active, this signal informs the modem or data set that the controller is ready to send data. -Output 1 (-OUT 1): This signal is pulled high. -Output 2 (-OUT 2): This is a user-designated output. This signal controls interrupts to the system. Voltage Interchange Information The signal is considered in the marking condition when the voltage on the interchange circuit, measured at the interface point, is more negative than -3 Vdc with respect to signal ground. The signal is considered in the spacing condition when the voltage is more positive than + 3 Vdc with respect to signal ground. The region between + 3 Vdc and -3 Vdc is defined as the transition region and is considered an Invalid level. Voltage that is more negative than -15 Vdc or more positive than + 15 Vdc is also considered an invalid level. 22 Serial Port Controller (Types 1 and 2) Interchange Vonage Binary State Positive VoHage Negative Voltage Binary 0 Binary 1 Interface Control Function Signal CondlUon On Spacing Marking Off Figure 20. Voltage Levels Connector The hardware interface uses the standard D-shell connector and pin assignments defined for RS-232C. The voltage levels are EIA only. Current loop interface is not supported. The following figure shows the pin configuration and signal assignments for the serial port in a communications environment. 1 13 \0000000000000] 000000000000 14 25 110 Signal Name PlnNo. 110 Signal Name Not Connected Transmit Data Receive Data Request to Send Clear to Send Data Set Ready Signal Ground 14 15 16 7 N/A 0 I 0 I I N/A 18 19 20 N/A N/A N/A N/A N/A N/A 0 8 9 10 11 12 13 I N/A N/A N/A N/A N/A Data Carrier Detect Not Connected Not Connected Not Connected Not Connected Not Connected 21 22 23 24 25 N/A I N/A N/A N/A Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected Data Terminal Ready Not Connected Ring Indicator Not Connected Not Connected Not Connected PlnNo. 1 2 3 4 5 6 17 Figure 21. Serial Port Connector Signal and Pin Assignments Serial Port Controller (Types 1 and 2) 23 Index A I applications 2 asynchronous communications Interface 23 interrupt enable register 6 interrupt identification register interrupts 6 interrupts, modem control 13 1 B baud-rate generator block diagram 2 break interrupt 15 3, 6 L line control register 11 line status register 14 C communications applications 2 compatibility 21 connector 23 considerations, programming 21 D data format 3 data speed 6 descriptions, signal 21 diagnostic capabilities 13 diagnostic mode 13 divisor latch access bit (OLAB) divisor latch registers 5 OLAB (divisor latch access bit) 11 F FIFO control register FIFO modes 18 framing error 15 24 7 Index 9 M marking condition, signal 22 modem control register 12 modem status register 17 o output port 1 (Serial 1) output port 2 (Serial 2) overrun error 16 2 2 11 p 4, parity error 15 pin assignments 23 programming considerations R receiver buffer register 5 21 S scratch register 18 signal descriptions 21 spacing condition, signal support 1 22 T transition region, signal 22 transmitter holding register 4 V voltage Interchange information voltages 23 22 W word length 12 Index 25 Notes: 28 Index Parallel Port Controller (Type 1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port Programmable Option Select ................ Parallel Port Extended Mode ....................... Parallel Port Controller Programming Considerations ........ Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port (Type 1) 1 2 2 2 3 4 5 6 7 8 Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. II Parallel Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port Address Assignments . . . . . . . . . . . . . . . . . Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel-Port Timing Sequence . . . . . . . . . . . . . . . . . . . . Data and Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port Connector Signal and Pin Assignments Parallel Port (Type 1) 1 2 3 4 5 6 7 7 8 Description The parallel port allows the attachment of devices that transfer 8 bits of parallel data at standard transistor-transistor levels. It has a 25-pin, O-shell connector. The primary function of the parallel port is to attach a printer with a parallel interface to the system. This port may be addressed as parallel port 1, 2, or 3, and is compatible with IBM Personal Computer parallel port implementations. The parallel port has an extended mode that supports bidirectional input and output. The port also supports level-sensitive interrupts and a readable interrupt-pending status. The following figure is a block diagram of the parallel port controller. Interrupt Data Bus r- ~ Data I/O Buffer i Direction Control I-- 25-pin Connector Control Output Buffer Control Wrap and Signal Input r--- Figure 1. Parallel Port Controller Parallel Port (Type 1) 1 Parallel Port Programmable Option Select The parallel port can be configured to the same three address spaces used by IBM Personal Computer products. These addresses are selected through Programmable Option Select (POS) registers during system board setup. The address assignments for each configuration are shown in the following figure. Parallel 1 Parallel 2 Parallel 3 Data Port (Hex Address) Status Port (Hex Address) Control Port (Hex Address) Reserved Address IRQ 038C 0378 0278 0380 0379 0279 038E 037A 027A 038F 0378 0278 7 7 7 Figure 2. Parallel Port Address Assignments Parallel Port Extended Mode The extended mode option is selected through the POS function during system board setup. The extended mode makes the parallel port an 8-bit parallel bidirectional interface. Direction is determined by bit 5 of the Parallel Control port. See "Parallel Control Port" on page 5. Parallel Port Controller Programming Considerations The following are some considerations for programming the parallel port controller. The interface responds to five 1/0 instructions: two output and three input. In the compatible mode, the output instructions transfer data into two latches whose output is presented on the pins of the D-shell connector. In the extended mode, the 8-bit data latch output to the D-shell connector is controlled by bit 5 in the Parallel Control port. In the compatible mode, two of the three input instructions allow the system microprocessor to read back the contents of the two latches. 2 Parallel Port (Type 1) In the extended mode, the read-back of the 8-bit data in the Data Address is controlled by bit 5 in the Parallel Control port. The third input instruction allows the system microprocessor to read the real-time status of a group of pins on the connector. The extended mode can be used by externally attached equipment. During the power-on self test (POST), the parallel port is configured as an output port. POST status information is written to this port during the power-on initialization or the initialization caused by a reset from the keyboard (Ctrl, Alt, Del). The following is a detailed description of each interface-port instruction. Data Port The Data port is the 8-bit data port for both the compatible and extended modes. In the compatible mode, a write operation to this port immediately presents data to the connector pins. In the compatible mode, a read operation from this port produces the last data written to it. In the extended mode, a write operation to this port latches the data, but the data is only presented to the connector pins if the direction bit was set to 0 (Write) in the Parallel Control port. A read operation in the extended mode produces either: • The data previously written if the direction bit in the Parallel Control port is set to 0 (Write). • The data on the connector pins from another device if the direction bit in the Parallel Control port is set to 1 (Read). Ian 7-0 Port Data Data Figure 3. Data Port Bits 7·0 These bits represent the 'data' (07 - DO) signal lines. Parallel Port (Type 1) 3 Status Port The Status port is a read-only port in both modes. A read operation to this port presents the system microprocessor with the interrupt-pending status of the interface, and the real-time status of the connector pins, as shown in the following figure. An interrupt is pending when bit 2 (-IRQ STATUS) is set to 0. Bit Port Data 7 6 -BUSY -ACK PE SLCT -ERROR -IRQ STATUS Reserved 5 4 3 2 1,0 Figure 4. Status Port Bit 7 This bit represents the state of the '-busy' signal (-BUSY). When this signal is active, the printer is busy and cannot accept data. Bit 6 This bit represents the current state of the printer '-acknowledge' signal (-ACK). When this bit is set to 0, the printer has received a character and is ready to accept another. Bit 5 This bit represents the current state of the printer 'paper end' signal (PE). When this bit is set to 1, the printer has detected the end of the paper. Bit 4 This bit represents the current state of the 'select' signal (SLCT). When this bit is set to 1, the printer has been selected. Bit 3 This bit represents the current state of the printer '-error' signal (-ERROR). When this bit is set to 0, the printer has encountered an error condition. Bit 2 When this bit is set to 0, the printer has acknowledged the previous transfer using the '-acknowledge' signal. An interrupt is pending when bit 2 (-IRQ STATUS) is set to 0. Bits 1, 0 These bits are reserved. 4 Parallel Port (Type 1) Parallel Control Port The Parallel Control port is a read/write port. A write operation to this port latches bits 0 through 5 of the bus. Bit 5 is the direction control bit used in the extended mode only. A read operation to the Parallel Control port presents the system microprocessor the data that was last written to it, except for the write-only direction bit. Bit Port Data 7,6 Reserved = 0 Direction IRQ EN Pin 17 (SLCT IN) Pin 16 (-INIT) Pin 14 (AUTO FD XT) Pin 1 (STROBE) 5 4 3 2 1 0 Figure 5. Parallel Control Port Bits 7,6 These bits are reserved and must be set to O. Bit 5 This write-only bit controls the direction of the data port. When this bit is set to 0, the data port is written to. When this bit is set to 1, the data port is read from. Bit 4 This bit enables the parallel port interrupt. When this bit is set to 1, an interrupt occurs when the '-acknowledge' signal changes from active to inactive. Bit 3 This bit controls the 'select in' signal bit is set to 1, the printer is selected. Bit 2 This bit controls the 'initialize printer' signal this bit is set to 0, the printer starts. Bit 1 This bit controls the 'automatic feed XT' signal (AUTO FD XT). When this bit is set to 1, the printer automatically spaces the paper up one line for every line return. Bit 0 This bit controls the 'strobe' signal (STROBE) to the printer. When this bit is set to 1, data is clocked into the printer. (SLCT IN). When this (-INIT). When Parallel Port (Type 1) 5 Parallel Port Timing Timing for the parallel port depends on the devices connected to the port. The following figure shows the sequence for typical parallel-port signal timing. BUSY -ACK DATA -STROBE Figure 6. Parallel-Port Timing Sequence For specific signal timing parameters, refer to the specifications for the equipment connected to the parallel port connector. 6 Parallel Port (Type 1) Signal Descriptions The following figures list characteristics of the signals. Sink Current Source Current High-Level Output Voltage Low-Level Output Voltage 24 rnA 15mA 2.4 Vdc 0.5 Vdc Maximum Maximum Minimum Maximum Figure 7. Data and Interrupt Signals Pins 1, 14, 16, and 17 are driven by open collector drivers pulled to 5 Vdc through 4.7 kilohm resistors. Sink Current Source Current High-Level Output Voltage Low-Level Output Voltage 20 rnA 0.55 rnA 5.0 Vdc minus pullup 0.5 Vdc Maximum Maximum Minimum Maximum Figure 8. Control Signals Parallel Port (Type 1) 7 Connector The parallel port connector is a standard 25-pin, D-shell connector. The data lines on the connector are driven by drivers capable of sourcing 15 milliamps and sinking 24 milliamps. The following figure shows the signal and pin assignments for the parallel port controller connector. 13 1 \0000000000000) 000000000000 25 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 110 Signal Name Pin No. 110 Signal Name 110 -STROBE Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 -ACK BUSY PE SLCT 14 15 16 17 18 19 20 21 22 23 24 25 0 -AUTO FDXT -ERROR -INIT -SLCT IN 1/0 1/0 1/0 110 110 110 110 110 I I I I I 0 0 NA NA NA NA NA NA NA NA Ground Ground Ground Ground Ground Ground Ground Ground Figure 9. Parallel Port Connector Signal and Pin Assignments 8 Parallel Port (Type 1) Video Subsystem (Type 1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Major Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Graphics Array Components . . . . . . . . . . . . . . . . . . . CRT Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attribute Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation .... . . . . . . . . . . . . . . . . . . . . . . . . . . .. Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Option Select . . . . . . . . . . . . . . . . . . . . . . Alphanumeric Modes .... . . . . . . . . . . . . . . . . . . . . . . .. Graphics Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 x 200 Four-Color Graphics (Modes Hex 4 and 5) ..... 640 x 200 Two-Color Graphics (Mode Hex 6) .......... 640 x 350 Graphics (Mode Hex F) . . . . . . . . . . . . . . . . . . 640 x 480 Two-Color Graphics (Mode Hex 11) .......... 16-Color Graphics Modes (Mode Hex 10, D, E, and 12) 256-Color Graphics Mode (Mode Hex 13) .... . . . . . . . .. Video Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . MemoryModes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes Hex 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes Hex 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes Hex 4, 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Hex 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Hex 7 · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Hex D Mode Hex E · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Hex F · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Hex 10 · . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. · .............................. Mode Hex 11 Mode Hex 12 Mode Hex 13 · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Subsystem (Type 1) 4 4 4 5 5 5 5 7 8 10 10 11 14 14 16 17 18 18 18 20 20 21 22 23 24 25 26 28 30 31 32 33 34 35 35 36 37 38 Miscellaneous Output Register . . . . . . . . . . . . . . . . . . . Input Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . Input Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . Feature Control Register . . . . . . . . . . . . . . . . . . . . . . . Video Subsystem Enable Register . . . . . . . . . . . . . . . . . Sequencer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequencer Address Register ... . . . . . . . . . . . . . . . . .. Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking Mode Register . . . . . . . . . . . . . . . . . . . . . . . . Map Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Map Select Register . . . . . . . . . . . . . . . . . . . Memory Mode Register . . . . . . . . . . . . . . . . . . . . . . . . CRT Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Horizontal Total Register . . . . . . . . . . . . . . . . . . . . . . . Horizontal Display-Enable End Register ............. Start Horizontal Blanking Register . . . . . . . . . . . . . . . . . End Horizontal Blanking Register . . . . . . . . . . . . . . . . . Start Horizontal Retrace Pulse Register ............. End Horizontal Retrace Register . . . . . . . . . . . . . . . . . . Vertical Total Register . . . . . . . . . . . . . . . . . . . . . . . . . Overflow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preset Row Scan Register . . . . . . . . . . . . . . . . . . . . . . Maximum Scan Line Register . . . . . . . . . . . . . . . . . . . . Cursor Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . Cursor End Register . . . . . . . . . . . . . . . . . . . . . . . . . . Start Address High Register . . . . . . . . . . . . . . . . . . . . . Start Address Low Register . . . . . . . . . . . . . . . . . . . . . Cursor Location High Register . . . . . . . . . . . . . . . . . . .. Cursor Location Low Register . . . . . . . . . . . . . . . . . . . . Vertical Retrace Start Register . . . . . . . . . . . . . . . . . . . Vertical Retrace End Register . . . . . . . . . . . . . . . . . . . . Vertical Display Enable End Register . . . . . . . . . . . . . . . Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Underline Location Register . . . . . . . . . . . . . . . . . . . . . Start Vertical Blanking Register . . . . . . . . . . . . . . . . . . . End Vertical Blanking Register . . . . . . . . . . . . . . . . . . . CRT Mode Control Register . . . . . . . . . . . . . . . . . . . . . Line Compare Register . . . . . . . . . . . . . . . . . . . . . . . . Graphics Controller Registers . . . . . . . . . . . . . . . . . . . . . . Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set/Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Set/Reset Register . . . . . . . . . . . . . . . . . . . . . . II Video Subsystem (Type 1) 38 40 40 41 41 42 42 43 43 45 46 48 49 50 50 51 51 51 53 53 54 55 56 57 58 58 59 59 59 60 60 60 61 62 62 63 63 64 67 68 68 69 69 Color Compare Register . . . . . . . . . . . . . . . . . . . . . . . . 70 Data Rotate Register . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Read Map Select Register . . . . . . . . . . . . . . . . . . . . . . 72 Graphics Mode Register . . . . . . . . . . . . . . . . . . . . . . . . 72 Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . 74 Color Don't Care Register .... . . . . . . . . . . . . . . . . . .. 75 Bit Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Attribute Controller Registers . . . . . . . . . . . . . . . . . . . . . . 76 Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Internal Palette Registers 0 through F . . . . . . . . . . . . . . . 77 Attribute Mode Control Register . . . . . . . . . . . . . . . . . . 78 Overscan Color Register . . . . . . . . . . . . . . . . . . . . . . . 80 Color Plane Enable Register . . . . . . . . . . . . . . . . . . . . . 80 Horizontal PEL Panning Register . . . . . . . . . . . . . . . . . . 81 Color Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . 82 VGA Programming Considerations . . . . . . . . . . . . . . . . . . . . 83 Programming the Registers . . . . . . . . . . . . . . . . . . . . . . . 86 RAM Loadable Character Generator . . . . . . . . . . . . . . . . . 87 Creating a Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Video Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . 90 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Video DAC to System Interface . . . . . . . . . . . . . . . . . . . . . 91 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . 92 Auxiliary Video Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Connector Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Display Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Index 107 Video Subsystem (Type 1) III Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. Iv Video Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attribute Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIOS Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double Scanning and Border Support . . . . . . . . . . . . . . .. IBM Direct-Drive Analog Displays ................. Character/Attribute Format ........ . . . . . . . . . . . . .. Attribute Byte Definitions . . . . . . . . . . . . . . . . . . . . . . . BIOS Color Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Memory Format . . . . . . . . . . . . . . . . . . . . . . . . . PEL Format, Modes Hex 4 and 5 . . . . . . . . . . . . . . . . . . Color Selections, Modes Hex 4 and 5 ............... PEL Format, Mode Hex 6 . . . . . . . . . . . . . . . . . . . . . . . Bit Definitions C2,CO . . . . . . . . . . . . . . . . . . . . . . . . . . Compatible Color Coding . . . . . . . . . . . . . . . . . . . . . . . 256KB Video Memory Map . . . . . . . . . . . . . . . . . . . . . . Data Flow for Write Operations . . . . . . . . . . . . . . . . . . . Color Compare Operations . . . . . . . . . . . . . . . . . . . . . . Video Subsystem Register Overview ............... General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Output Register, Hex 03CC/03C2 . . . . . . .. Display Vertical Size . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Select Definitions . . . . . . . . . . . . . . . . . . . . . . . . Input Status Register 0, Hex 03C2 ................. Input Status Register 1, Hex 03DA/03BA ............. Feature Control Register, Hex 03DA/03BA and 03CA Video Subsystem Enable Register, Hex 03C4 .......... Sequencer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Sequencer Address Register . . . . . . . . . . . . . . . . . . . . Reset Register, Index Hex 00 . . . . . . . . . . . . . . . . . . . . Clocking Mode Register, Index Hex 01 .............. Map Mask Register, Index Hex 02 . . . . . . . . . . . . . . . . . Character Map Select Register, Index Hex 03 ......... Character Map Select A . . . . . . . . . . . . . . . . . . . . . . . . Character Map Select B . . . . . . . . . . . . . . . . . . . . . . . . Memory Mode Register, Index Hex 04 .............. Map Selection, Chain 4 . . . . . . . . . . . . . . . . . . . . . . . . CRT Controller Registers . . . . . . . . . . . . . . . . . . . . . . . CRT Controller Address Register, Hex 03B4/03D4 ...... Video Subsystem (Type 1) 3 6 7 8 9 10 12 12 13 14 15 15 16 17 19 20 35 36 37 38 38 39 39 40 40 41 41 42 42 43 43 45 46 47 47 48 48 49 50 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. Horizontal Total Register, Index Hex 00 ............. Horizontal Display Enable-End Register, Index Hex 01 Start Horizontal Blanking Register, Index Hex 02 ....... End Horizontal Blanking Register, Index Hex 03 ........ Display Enable Skew .......................... Start Horizontal Retrace Pulse Register, Index Hex 04 End Horizontal Retrace Register, Index Hex 05 ........ Vertical Total Register, Index Hex 06 ............... CRT Overflow Register, Index Hex 07 ............... Preset Row Scan Register, Index Hex 08 ............. Maximum Scan Line Register, Index Hex 09 .......... Cursor Start Register, Index Hex OA ................ Cursor End Register, Index Hex OB ................ Start Address High Register, Index Hex OC ........... Start Address Low Register, Index Hex 00 ........... Cursor Location High Register, Index Hex OE .......... Cursor Location Low Register, Index Hex OF .......... Vertical Retrace Start Register, Index Hex 10 ......... Vertical Retrace End Register, Index Hex 11 .......... Vertical Display Enable End Register, Index Hex 12 ..... Offset Register, Index Hex 13 .................... Underline Location Register, Index Hex 14 ........... Start Vertical Blanking Register, Index Hex 15 ......... End Vertical Blanking Register, Index Hex 16 ......... CRT Mode Control Register, Index Hex 17 ............ CRT Memory Address Mapping ................... Line Compare Register, Index Hex 18 . . . . . . . . . . . . . .. Graphics Controller Register Overview ............. Graphics Controller Address Register, Hex 03CE ....... Set/Reset Register, Index Hex 00 .................. Enable Set/Reset Register, Index Hex 01 ............ Color Compare Register, Index Hex 02 .............. Data Rotate Register, Index Hex 03 ................ Operation Select Bit Definitions ................... Read Map Select Register, Index Hex 04 ............. Graphics Mode Register, Index Hex 05 .............. Write Mode Definitions ......................... Miscellaneous Register, Index Hex 06 .............. Video Memory Assignments ..................... Color Don't Care Register, Index Hex 07 ............. Bit Mask Register, Index Hex 08 .................. Attribute Controller Register Addresses ............. Address Register, Hex 03CO ..................... Video Subsystem (Type 1) 50 51 51 51 52 53 53 54 55 56 57 58 58 59 59 59 60 60 60 61 62 62 63 63 64 65 67 68 68 69 69 70 71 71 72 72 73 74 74 75 75 76 76 Y 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. vi Internal Palette Registers, Index Hex 00 - OF .......... Attribute Mode Control Register, Index Hex 10 ......... Overscan Color Register, Index Hex 11 .............. Color Plane Enable Register, Index Hex 12 ........... Horizontal PEL Panning Register, Index Hex 13 ........ Image Shifting .............................. Color Select Register, Index Hex 14 ................ Character Table Structure ...................... Character Pattern Example .. . . . . . . . . . . . . . . . . . . .. Split Screen Definition ......................... Screen Mapping within the Display Buffer Address Space Video DAC Register .......................... Auxiliary Video Connector ...................... Auxiliary Video Connector Timing (DAC Signals) ....... Display Connector ... . . . . . . . . . . . . . . . . . . . . . . . .. Display Connector Signals ...................... Vertical Size .............................. Vertical Timing, 350 Lines ..................... Vertical Timing, 400 Lines ..................... Vertical Timing, 480 Lines ..................... Horizontal Timing, 80 Column with Border .......... Horizontal Timing, 40/80 Column, without Border ...... Video Subsystem (Type 1) 77 78 80 80 81 81 82 87 88 88 89 90 95 98 99 99 100 101 102 103 104 105 Description System video is generated by the IBM Video Graphics Array (VGA) and its associated circuitry, which consists of a video buffer, a video digital-to-analog converter (DAC), and test circuitry. The 256KB video memory is mapped as four planes of 64Kb by 8 bits (maps 0 through 3). The video DAC drives the analog output to the display connector. The test circuitry is used to test for the type of display attached, color or monochrome. The video subsystem supports all video modes available on the IBM Monochrome Display Adapter, IBM Color/Graphics Monitor Adapter, and IBM Enhanced Graphics Adapter. When a monochrome display is attached, the colors for the color modes appear as shades of gray. The new modes available are: • • • • 640 720 360 320 x 480 16- and 2-color graphics x 400 16-color and monochrome alphanumeric x 400 16-color alphanumeric x 200 256-color graphics. In the 200-scan-line modes, the data for each scan line is scanned twice. This double scanning allows the 200-scan-line image to be displayed as 400 scan lines. The video subsystem serves as the interface between the system microprocessor and video memory. When the system microprocessor writes to or reads from video memory, all data passes through the video subsystem. The video subsystem controls the access to video memory from the system and the cathode-ray tube (CRT) controller. Therefore, programs do not need to wait for horizontal retrace to update the display buffer in order to preserve screen appearance. The system performs better when accessing the display buffer during nonactive display times because there is less interference from the CRT controller. The video subsystem also controls the system addresses assigned to video memory. Up to three different starting addresses can be programmed for compatibility with previous video adapters. Video Subsystem (Type 1) 1 In the graphics modes, the mode determines the way video information is formatted into memory, and the way memory is organized. In alphanumeric modes, the system writes the ASCII character code and attribute data to video memory maps 0 and 1, respectively. Memory map 2 contains the character font loaded by BIOS during an alphanumeric mode set. The font is used by the character generator to create the character image on the display. Three fonts are contained in ROM. Two of these fonts have dot patterns that are the same as previous IBM display adapters. The third font is a new 8-by-16 character font. Up to eight 256-character fonts can be loaded into video memory map 2 at one time; two fonts can be active at anyone time, allowing a 512-character font. The video subsystem formats the information in video memory and sends the output to the video DAC. For color displays, the video DAC sends three analog color signals (red, green, and blue) to the display connector. For monochrome displays, BIOS translates the color information in the DAC, and the DAC drives the summed signal onto the green output. The auxiliary video connector allows video data to be passed between the video subsystem and an adapter plugged into the channel connector. The video subsystem can be disabled through the POS registers. When it is disabled, the video subsystem will not respond to video memory or I/O reads or writes, and the video from the adapter can directly drive the video DAC. Note: Compatibility with other hardware is best achieved by using the BIOS interface or operating system interface whenever possible. 2 Video Subsystem (Type 1) The following is a block diagram of the video subsystem, which is part of the system board. j------------------------------------------------------------------------- Addre ss Mux CRT Controller Data f--- - f4Memory Maps I r--- I Graphics Controller Sequencer r-- I -ro4I ,-1- Four 8 bit Memory Maps '--- 64K Addresses ! ! Each r-:I 2f---~ 3f- I- L.,. I I Attribute Controller Ie+- • - Red Video DAC - Green - Blue I Ii -------------------- VGA ChI p -------------------------------, I Data Analog Outputs to Display Figure 1. Video Subsystem Video Subsystem (Type 1) 3 Major Components Most of the logic for the video subsystem is contained in one module, the video graphics array (VGA). This module contains all circuits necessary to generate the timing for the video memory, and generates the video information going to the video DAC. The major components are: ROM BIOS, the support logic, and the VGA. ROM BIOS Software support is provided by BIOS on the system board. BIOS contains the character fonts and the system interface to run the video subsystem. Support Logic The support logic consists of the video memory, the clocks, and the video DAC. The video memory consists of 256KB and its use and mapping depend on the mode selected. Two clock sources (25.175 MHz and 28.322 MHz) provide the dot rate. The clock source is selected in the Miscellaneous Output register. The video DAC contains the color palette that is used to convert the video data into the video signal sent to the display. Three analog signals (red, green, blue) are output from the DAC. The maximum number of colors displayed is 16 out of 256K (K equals 1024), except for mode hex 13, which can display 256 colors. The maximum number of gray shades is 16 out of 64, except for mode hex 13, which can display all 64 shades. 4 Video Subsystem (Type 1) Video Graphics Array Components The VGA has four major functional areas: the CRT controller, the sequencer, the graphics controller, and the attribute controller. CRT Controller The CRT controller generates horizontal and vertical synchronization signal timings, addressing for the regenerative buffer, cursor and underline timings, and refresh addressing for the video memory. Sequencer The sequencer generates basic memory timings for the video memory and the character clock for controlling regenerative buffer fetches. It allows the system to access memory during active display intervals by periodically inserting dedicated system microprocessor memory cycles between the display memory cycles. Map mask registers in the sequencer are available to protect entire memory maps from being changed. Graphics Controller The graphics controller is the interface between the video memory and the attribute controller during active display times, and between video memory and the system microprocessor during memory accesses. During active display times, memory data is latched and sent to the attribute controller. In graphics modes, the memory data is converted from parallel to serial bit-plane data before being sent; in alphanumeric modes, the parallel attribute data is sent. Video Subsystem (Type 1) 5 During system accesses of video memory, the graphics controller can perform logical operations on the memory data before it reaches video memory or the system data bus. These logical operations are composed of four logical write modes and two logical read modes. The logical operators allow enhanced operations, such as a color compare in the read mode, individual bit masking during write modes, internal 32-bit writes in a single memory cycle, and writing to the display buffer on non byte boundaries. Memory Map 0 Data Data -;~ Memory Map 1 Data Write Mode Logic Memory Map 2 Data Memory Map 3 Data Read ' - - Mode Logic r-- Parallel to Serial CO -Ie Parallel to Serial C1 -Is Parallel to Serial C2 -Ie Parallel to Serial C3 Latches Mux / ; - - Character Generator Data 8 / ; - - Attribute Data 8 Figure 2. Graphics Controller 6 Video Subsystem (Type 1) AHrlbute Controller The attribute controller takes in data from video memory through the graphics controller and formats it for display. Attribute data in alphanumeric mode and serialized bit-plane data in graphics mode are converted to an 8-bit color value. Each color value is selected from an internal color palette of 64 possible colors (except in 256-color mode). The color value is used as a pointer into the video DAC where it is converted to the analog signals that drive the display. Blinking, underlining, cursor insertion, and PEL panning are also controlled in the attribute controller. A/N Blink Logic Character Generator Data -la- Underline Logic APASerial --14 Data ~ 1X Mux Parallel to Serial 01 Cursor Logic 00 S S 1--0 APA= 1----1 PEL ;.{-. Panning Logic 0 1 2 3 IAr---. Color Plane Enable Logic Internal Palette 16x 6 APA Blink Logic =: 0 0 Overscan Logic - 4 - 5 Mux r-- Color Select Re~ter 0 I-- 2 '-'-- 3 1 1S Attribute Mode Register (Bit 7) Io~~ 256 Color Mode Logic To DAC 6 7 '-- Figure 3. Attribute Controller Video Subsystem (Type 1) 7 Modes of Operation Certain modes on previous IBM display adapters distingl'ished between monochrome and color displays. For example, mode 0 was the same as mode 1 with the color burst turned off. Because color burst is not supported by the PS/2 video, the mode pairs are exactly the same. The support logic for VGA recognizes the type of display, and adjusts the output accordingly. Mode 3+ is the default mode with a color display attached and mode 7+ is the default mode with a monochrome display attached. The following figure describes the alphanumeric (A/N) and all pOints addressable (APA) graphics modes supported by BIOS. Each color is selected from 256K possibilities, and gray shades from 64 possibilities. The variations within the basic BIOS modes are selected through BIOS calls that set the number of scan lines. The scan line count is set before the mode call is made. Mode (Hex) Type Colors Alpha Buffer Box Format Start Size 0, 1 0",1" 0+,1+ 2,3 2",3" 2+,3+ 4,5 6 7 7+ D E F 10 11 12 13 AIN A/N AlN AlN A/N A/N APA APA AlN AlN APA APA APA APA APA APA APA 40x25 B8000 8x8 40x 25 B8000 8x 14 40x25 B8000 9 x 16 80x25 B8000 8x8 80x25 B8000 8 x 14 8Ox25 B8000 9 x 16 40x25 B8000 8x8 80x 25 B8000 8x8 8Ox25 BOooo 9 x 14 80x25 BOooo 9 x 16 40x25 AOOoo 8x8 80x 25 AOOoo 8x8 80x25 AOooo 8x 14 80x25 AOOOO 8x 14 80x30 AOOOO 8 x 16 8Ox30 AOooO 8x 16 40x25 AOooO 8x8 16 16 16 16 16 16 4 2 - 16 16 16 2 16 256 Max. Pgs. Freq. 8 8 8 8 8 8 1 1 8 8 8 4 2 2 1 1 1 70 Hz 70Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70Hz 70 Hz 70 Hz 70Hz 70 Hz 60 Hz 60Hz 70Hz " Enhanced modes from the IBM Enhanced Graphics Adapter. + Enhanced modes Figure 4. BIOS Video Modes 8 Video Subsystem (Type 1) Vert. PELs 320 x 200 320 x 350 360 x 400 640 x 200 640 x 350 720 x 400 320 x 200 640 x 200 720 x 350 720 x 400 320 x 200 640 x 200 640 x 350 640 x 350 640 x 480 640 x 480 320 x 200 Border support and double scanning depend on the mode selected. The following shows which modes use double scanning and which support a border. Mode (Hex) 0,1 0*,1* 0+,1+ 2,3 2*,3* 2+,3+ 4,5 6 7 7+ D E F 10 11 12 13 Scan Double Border Support Yes No No Yes No No Yes Yes No No Yes Yes No No No No Yes No No No Yes Yes Yes No Yes Yes Yes No Yes Yes Yes Yes Yes Yes Figure 5. Double Scanning and Border Support Video Subsystem (Type 1) 9 Display Support The video subsystem supports direct-drive analog displays. The displays must have a horizontal sweep frequency of 31.5 kHz, and a vertical sweep frequency capability of 50 to 70 Hz. Displays that use a digital input, such as the IBM Color Display, are not supported. The following figure summarizes the display characteristics. Parameter Color Monochrome Horizontal Scan Rate Vertical Scan Rate Video Bandwidth Maximum Horizontal Resolution Maximum Vertical Resolution 31.5 kHz 50 to 70 Hz 28 MHz 720 PELs 480 PELs 31.5 kHz 50 to 70 Hz 28 MHz 720 PELs 480 PELs Figure 6. IBM Direct-Drive Analog Displays Since the color and monochrome displays run at the same sweep rate, all modes work on both displays. The vertical gain of the display is controlled by the polarity of the vertical and horizontal synchronization pulses. This is done so 350, 400, or 480 lines can be displayed without adjusting the display. See "Signal Timing" on page 100 for more information. Programmable Option Select The video subsystem supports programmable option select (POS). The video subsystem is placed in the setup mode through bit 5 of the System Board Enable/Setup register (hex 0094). While the video subsystem is in the setup mode, only POS Register 2 (hex 0102) is used; bit 0 of this register is the video enable bit. When this bit is set to 0, the video subsystem does not respond to commands, addresses, or data. If video output is being generated when the video enable bit is set to 0, the output is still generated. For information on BIOS calls to enable or disable the video, see the IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference. Note: Whenever the video subsystem is in setup mode, access to the video DAC registers is disabled. 10 Video Subsystem (Type 1) Alphanumeric Modes The alphanumeric modes are modes 0 through 3 and 7. The mode chart lists the variations of these modes. The data format for alphanumeric modes is the same as the data format on the IBM Color/Graphics Monitor Adapter, the IBM Monochrome Display Adapter, and the IBM Enhanced Graphics Adapter. BIOS initializes the video subsystem according to the selected mode and loads the color values into the video DAC. These color values can be changed to give a different color set to select from. Bit 3 of the attribute byte may be redefined by the Character Map Select register to act as a switch between character sets, giving the programmer access to 512 characters at one time. When an alphanumeric mode is selected, the BIOS transfers character font patterns from the ROM to map 2. The system stores the character data in map 0, and the attribute data in map 1. In the alphanumeric modes, the programmer views maps 0 and 1 as a single buffer. The CRT controller generates sequential addresses, and fetches one character code byte and one attribute byte at a time. The character code and row scan count are combined to make up the address into map 2, which contains the character font. The appropriate dot patterns are then sent to the attribute controller, where color is assigned according to the attribute data. Video Subsystem (Type 1) 11 Every display-character position in the alphanumeric mode is defined by two bytes in the display buffer. Both the color/graphics and the monochrome emulation modes use the following 2-byte character/attribute format. Display Character Code Byte 7 6 543 2 o Attribute Byte 7 6 Even Address 5 4 3 2 o I Odd Address Figure 7. Character/Attribute Format See "Characters and Keystrokes" for characters loaded during a BIOS mode set. The functions of the attribute byte are defined in the following table. Bit 7 can be redefined in the Attribute Mode Control register to give 16 possible background colors; its default is to control character blinking. Bit 3 can be redefined in the Character Map Select register to select between two character fonts; its default is to control foreground color selection. Bit Color 7 6 5 4 3 2 1 BII R G B IICS R G o B Function Blinking or Background Intensity Background Color Background Color Background Color Foreground Intensity or Character Font Select Foreground Color Foreground Color Foreground Color Figure 8. Attribute Byte Definitions For more information about the attribute byte, see "Character Map Select Register" on page 46 and" Attribute Mode Control Register" on page 78. 12 Video Subsystem (Type 1) The following are the color values loaded by BIOS for the 16-color modes. I R G B Color 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 Black Blue Green Cyan Red Magenta Brown White Gray Light Blue Light Green Light Cyan Light Red Light Magenta Yellow White (High Intensity) 1 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Figure 9. BIOS Color Set Both 40-column and 80-column alphanumeric modes are supported. The features of the 40-column alphanumeric modes (all variations of modes hex 0 and 1) are: • 25 rows of 40 characters • 2,000 bytes of video memory per page • One character byte and one attribute byte per character. The features of the 80-columnalphanumeric modes (all variations of modes hex 2, 3, and 7) are: • 25 rows of 80 characters • 4,000 bytes of video memory per page • One character byte and one attribute byte per character. Video Subsystem (Type 1) 13 Graphics Modes This section describes the graphics modes supported in BIOS. The colors in this section are generated when the BIOS is us&d to set the mode. BIOS initializes the video subsystem and the DAC palette to generate these colors. If the DAC palette is changed, different colors are generated. 320 x 200 Four-Color Graphics (Modes Hex 4 and 5) Addressing, mapping, and data format are the same as the 320 x 200 PEL mode of the IBM Color/Graphics Monitor Adapter. The display buffer is configured at hex B8000. Bit image data is stored in memory maps 0 and 1. The two bit planes (CO and C1) are each formed from bits from both memory maps. Features of this mode are: • • • • • • A maximum of 200 rows of 320 PELs, Double-scanned to display as 400 rows Memory-mapped graphics Four colors for each PEL Four PELs per byte 16,000 bytes of read/write memory. The video memory is organized into two banks of 8,000 bytes each using the following format. Address hex B8000 contains the PEL information for the upper-left corner of the display area. Memory Address Function 88000 Even Scans (0.2.4 •.....• 198) B9F3F Reserved BAOOO Odd Scans (1.3.5 •.....• 199) BBF3F Reserved BBFFF Figure 10. Video Memory Format 14 Video Subsystem (Type 1) The following figure shows the format for each byte. Bit 7 6 5 4 3 2 1 o Function C1 - First Display PEL CO - First Display PEL C1 - Second Display PEL CO - Second Display PEL C1 - Third Display PEL CO - Third Display PEL C1 - Fourth Display PEL CO - Fourth Display PEL Figure 11. PEL Format, Modes Hex 4 and 5 The color selected depends on the color set that is used. Color set 1 is the default. For information on changing the color set, see the IBM Personal Systeml2 and Personal Computer BIOS Interlace Technical Reference. Bits C1 CO Color Selected Color Set 1 Color Set 0 o o Black Light Cyan Light Magenta Intensified White Black Green Red Brown 1 1 0 1 0 1 Figure 12. Color Selections, Modes Hex 4 and 5 Video Subsystem (Type 1) 15 640 x 200 Two-Color Graphics (Mode Hex 6) Addressing, scan-line mapping, and data format are the same as the 640 x 200 PEL black and white mode of the IBM Color/Graphics Monitor Adapter. The display buffer is configured at hex B8000. Bit image data is stored in memory map 0 and comprises a single bit plane (CO). Features of this mode are: • • • • • • A maximum of 200 rows of 640 PELs Double scanned to display as 400 rows Same addressing and scan-line mapping as 320 x 200 graphics Two colors for each PEL Eight PELs per byte 16,000 bytes of read/write memory. The following shows the format for each byte. BII Function 7 6 5 4 3 2 1 First Display PEL Second Display PEL Third Display PEL Fourth Display PEL Fifth Display PEL Sixth Display PEL Seventh Display PEL Eighth Display PEL o Figure 13. PEL Format, Mode Hex 6 The bit definition for each PEL is 0 equals black and 1 equals intensified white. 16 Video Subsystem (Type 1) 640 x 350 Graphics (Mode Hex F) This mode emulates the EGA, graphics with the monochrome display and the following attributes: black, video, blinking video, and intensified video. A resolution of 640 x 350 uses 56,000 bytes of video memory to support the four attributes. This mode uses maps 0 and 2; map 0 is the video bit plane (CO), and map 2 is the intensity bit plane (C2). Both planes reside at address hex AOOOO. The two bits, one from each bit plane, define one PEL. The bit definitions are given in the following table. C2 CO PEL Color o o Black White Blinking White Intensified White 1 1 0 1 0 1 Figure 14. Bit Definitions C2,CO Memory is organi~ed with successive bytes defining successive PELs. The first eight PELs displayed are defined by the byte at hex AOOOO, the second· eight PELs at hex A0001, and so on. The most-significant bit In each byte defines the first PEL for that byte. Since both bit planes reside at address hex AOOOO, the user must select the plane to update through the Map Mask register of the sequence controller (see "Video Memory Organi~ation" on page 20). Video Subsystem (Type 1) 17 640 x 480 Two-Color Graphics (Mode Hex 11) This mode provides two-color graphics with the same data format as mode 6. Addressing and mapping are shown under "Video Memory Organization" on page 20. The bit image data is stored in map 0 and comprises a single bit plane (CO). The video buffer starts at hex AOOOO. The first byte contains the first eight PELs; the second byte at hex A0001 contains the second eight PELs, and so on. The bit definition for each PEL is 0 equals black and 1 equals intensified white. 16-Color Graphics Modes (Mode Hex 10, D, E, and 12) These modes support 16 colors. For all modes, the bit image data is stored in all four memory maps. Each memory map contains the data for one bit plane. The bit planes are CO through C3 and represent the following colors: CO = Blue C1 = Green C2 = Red C3 = Intensified The four bits define each PEL on the screen by acting as an address (pointer) into the internal palette in the VGA. The display buffer resides at address hex AOOOO. The Map Mask register selects any or all of the maps to be updated when the system writes to the display buffer. 256-Color Graphics Mode (Mode Hex 13) This mode provides graphics with the capability of displaying 256 colors at one time. The display buffer is sequential, starts at address hex AOOOO, and is 64,000 bytes long. The first byte contains the color information for the upper-left PEL. The second byte contains the second PEL, and so on, for 64,000 PELs (320 x 200). The bit image data is stored in all four memory maps and comprises four bit planes. The four bit planes are sampled twice to produce eight bit-plane values that address the video DAC. 18 Video Subsystem (Type 1) In this mode, the internal palette of the video subsystem is loaded by BIOS and should not be changed. The first 16 locations in external palette, which is in the video DAC, contain the colors compatible with the alphanumeric modes. The second 16 locations contain 16 evenly spaced gray shades. The next 216 locations contain values based on a hue-saturation-intensity model tuned to provide a usable, generic color set that covers a wide range of color values. The following figure shows the color information that is compatible with the colors in other modes. PEL Bits 76543210 Color Output 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 Black Blue Green Cyan Red Magenta Brown White Dark Gray Light Blue Light Green Light Cyan Light Red Light Magenta Yellow Intensified White Figure 15. Compatible Color Coding Each color in the palette can be programmed to one of 256K different colors. The features of this mode are: • • • • • • A maximum of 200 rows with 320 PELs Double scanned to display as 400 rows Memory-mapped graphics 256 of 256K colors for each PEL One byte per PEL 64,000 bytes of video memory. Video Subsystem (Type 1) 19 Video Memory Organization The display buffer consists of 256KB of dynamic read/write memory configured as four 64KB memory maps. Map o Map Map Map 1 2 3 64K Locations Per Map 8 Bits 8 Bits 8 Bits 8 Bits Figure 16. 256KB Video Memory Map The starting address and size of the display buffer can be changed to maintain compatibility with other display adapters and application software. There are three configurations used by other adapters: Address hex AOOOO for a length of 64KB Address hex BOOOO for a length of 32KB Address hex B8000 for a length of 32KB. The following pages show the memory organization for each of the BIOS modes. 20 Video Subsystem (Type 1) Modes Hex 0, 1 Address B8000 Display Buffer Storage Scheme (BAooo) B87CF (BA7CF) B8800 (BA800) ~ 2K ~ Reserved Page 2 (6) B8FCF (BAFCF) B9000 (BBooo) B97CF (BB7CF) B9800 (BB800) Attribute Byte 20001 Page 1 (5) Reserved Foreground Intensityl Character Select L -_ _ _ Background L-_ _ _ _ Blink/Intensity Page 3 (7) -16 colors per character Reserved Character Byte -Format is one character per byte Page 4 (8) B9FCF (BBFCF) B9FFF (BBFFF) Address Reserved Map 0 (char) B8000 Map 1 (attr) I 2000 B87CE B8800 B8FCE B9000 B97CE B9800 B9FCE BAOOO BA7CE BA800 BAFCE BBOOO BB7CE BB800 BBFCE BBFFE I Reserved Reserved Reserved Reserved I B8001 ~ B87CF 2K B8801 B8FCF Reserved Reserved B9001 B97CF B9801 B9FCF Reserved Reserved BA001 Reserved BA7CF Reserved BA801 Reserved Reserved BAFCF Reserved BB001 BB7CF Reserved BB801 Reserved BBFCF Reserved BBFFF Video Subsystem (Type 1) 21 Mode. Hex 2, 3 Address B8000 Display Buffer (BCOOO) ..0001 Page 1 (5) B8F9F B9000 Storage Scheme (BCF9F) (Boooo) ~4 Reserved Foreground Intensltyl Character Select L...-_ _ Background L..--_ _ _ _ Blink/Intensity Page 2 (6) B9F9F BAooo (BDF9F) (BEooo) BAF9F BBooo (BEF9F) (BFooo) Attribute Byte Reserved Page 3 (7) -16 colors per character Reserved Character Byte -Format is one character per byte Page 4 (8) BBF9F BBFFF Address (BFF9F) (BFFFF) Reserved Map o(char) Map 1 (attr) B8000 i 4000 B8F9E B9000 Reserved B9F9E BAOOO ----l...- I 4K 88001 B8F9F B9001 Reserved Reserved B9F9F BA001 Reserved BAF9E BBOOO Reserved BAF9F BB001 Reserved BBF9E BCOOO Reserved BBF9F BCOO1 Reserved BCF9E BDOOO Reserved BCF9F BDOO1 Reserved BDF9E BEooo Reserved BDF9F BE001 Reserved BEF9E BFooo Reserved BEF9F BF001 Reserved BFF9E BFFFE Reserved BFF9F BFFFF Reserved 22 Video Subsystem (Type 1) ...L Mode. Hex4,5 Address B8000 B9F3F BAOOO BBF3F BBFFF Address Storage Scheme Display Buffer Even Scans Reserved BAOOO Odd Scans Reserved BBFFE Reserved 4 [ _ I _I _I ] LSB MSB Map 1 Map 0 (CO) Even Scans 3 • 4 PELs per byte • 4 colors per PEL • First PEL Is the two MSBs Reserved Odd Scans BBF3E 8K ----L-~ (C1) B8000 B9F3E 2 I 8000 I 8000 B8001 8K -L-~ B9F3F BAOO1 BBF3F BBFFF Even Scans Reserved Odd Scans Reserved Video Subsystem (Type 1) 23 Mode Hex 6 Address Display Buffer B8000 B9F3F BAooo BBF3F BBFFF Address Even Scans Reserved Odd Scans Reserved MapO Bit Plane (CO) B8000 B9F3F BAooo BBF3F BBFFF 24 Even Scans Reserved Odd Scans Reserved Video Subsystem (Type 1) Storage Scheme 2 3 4 567 MSB • Eight PELs per byte • Two colors per PEL • First PEL is MSB 8 LSB Mode Hex 7 Address BOOOO (B4OOO) BOF9F (B4F9F) B1000 (B5OOO) Display Buffer Storage Scheme , Page 1 (5) I 4000 Attribute Byte 4K --'-- -L Reserved Page 2 (6) B1F9F (B5F9F) B2000 (66000) B2F9F (B6F9F) B3000 (B7000) B3F9F (B7F9F) B3FFF (B7FFF) - Reserved Page 3 (7) ~-L..-_ _ _ Reserved Foreground Intensityl Character Select Background Blink/Intensity Page 4 (8) -Four attributes per character Reserved Character Byte -Format is one character per byte. Address Map 0 (char) BOOOO Map 1 (attr) B0001 I 4000 BOF9F B1001 Reserved Reserved B1F9F B2001 Reserved Reserved B2F9F B3OO1 Reserved Reserved B3F9F B4OO1 Reserved Reserved B4F9F B5OO1 Reserved Reserved B5F9F B6001 Reserved B6F9E B7000 Reserved B6F9F B7001 Reserved B7F9E B7FFE Reserved B7F9F B7FFF Reserved -'-- BOF9E B1000 Reserved B1F9E B2000 B2F9E B3000 B3F9E 84000 B4F9E B5000 B5F9E B6000 4K -L Video Subsystem (Type 1) 25 Mode Hex D Display Buffer Address AOOOO (A8000) Page 1 (5) A1F3F (A9F3F) A2000 (AAOOO) A3F3F (ABF3F) - A4000 (ACOOO) - Reserved Page 2 (6) Reserved Page 3 (7) A5F3F (ADF3F) - A6000 (AEOOO) Reserved Page 4 (8) A7F3F (AFF3F) A7FFF (AFFFF) 26 Reserved Video Subsystem (Type 1) Storage Scheme I I 8000 8K 12345678 L J ----1-~._._._._._._. L ______ J L _____ ._.J L ______ MSb . . . . . CO C1 C2 JC3 (SB • Four bits per PEL • 16 colors per PEL • One bit from each bit plane (C3,C2,C1,CO) per PEL • First PEL is MSB of all four bit planes AOOOO Map 1 Green Bit Plane (C1) Map 0 Blue Bit Plane (CO) Address (A8000) - I I ---L- 8K AOOOO (A8000) - A1F3F (A9F3F) - A2000 (AAOOO) - A3F3F (ABF3F)- A4000 (ACOOO) - A5F3F (ADF3F)- A6000 (AEOOO) - A7F3F (AFF3F)- A7FFF (AFFFF)- 8000 A1F3F (A9F3F) - A2000 (AAOOO)- A3F3F (ABF3F)- A4000 (ACOOO)- A5F3F A6000 (ADF3F)(AEOOO) - A7F3F (AFF3F)- A7FFF (AFFFF)- ~ Reserved Reserved Reserved Reserved Map 2 Red Bit Plane (C2) AOOOO (A8000) - Reserved Reserved Reserved Reserved Map 3 Intensity Bit Plane (C3) I I ---L- 8K AOOOO (A8000) - A1F3F A2000 (A9F3F) (AAOOO)- A3F3F (ABF3F)- A4000 (ACOOO) - A5F3F (ADF3F)- A6000 (AEOOO) - A7F3F (AFF3F)- A7FFF (AFFFF)- 8000 A1F3F A2000 (A9F3F) (AAOOO)- A3F3F (ABF3F)- A4000 (ACOOO)- A5F3F (ADF3F)- A6000 (AEOOO) - A7F3F (AFF3F)(AFFFF)- A7FFF Reserved Reserved Reserved Reserved ~ Reserved Reserved Reserved Reserved Video Subsystem (Type 1) 27 Mode HexE Address AOOOO - Display Buffer Page 1 A3E7F - A4000 - Storage Scheme PEL 2 3 4 5 6 7 Reserved I I L.-.-.-.-.-.-.-J L.-.-.-.-.-.-.-J 16000 16K ~~ Page:;! A7E7F A8000 - 8 Reserved CO C1 L._._._._._._._.] C2 L._._._._._._._.] C3 Page 3 ABE7F ACOOO - Reserved MSB Page 4 AFE7F AFFFF - Reserved • • • • 28 Video Subsystem (Type 1) 4 bits per PEL 16 colors per PEL 1 bit from each bit plane (C3,C2,C1,CO) per PEL First PEL is MSB of all 4 bit planes LSB MapO Blue Bit Plane (CO) Address AOOOO - Map 1 Green Bit Plane (C1) I I AOOOO 16000 16K A3E7F Reserved A4000 A7E7F ~~ ABE7F ABOOO ABE7F Reserved ACOOO AFE7F ACOOO AFE7F Reserved AFFFF A4000 A7E7F Reserved ABOOO A3E7F AFFFF Map 2 Red Bit Plane (C2) AOOOO - Reserved Reserved Reserved Reserved Map 3 Intensity Bit Plane (C3) I I AOOOO 16000 16K A3E7F A4000 A7E7F A8000 ABE7F ACOOO AFE7F AFFFF Reserved Reserved Reserved Reserved ~~ A3E7F A4000 A7E7F ABOOO ABE7F ACooo AFE7F AFFFF Reserved Reserved Reserved Reserved Video Subsystem (Type 1) 29 Mode HexF Display Buffer Address AOOOO Page 1 A6D5F A8000 Storage Scheme ~32K 1 Reserved Map 0 Video Bit Plane (CO) Address AOOOO • • • Reserved L______ J CO L ______ J C2 LSB MSB • Page 2 AED5F AFFFF 1 234 5 6 7 8 I I 28000 Two bits per PEL Four attributes per PEL One bit from each bit plane (C2.CO) First PEL is MSB of video and intensity bit planes Map 2 Intensity Bit Plane (C2) - I I AOOOO 28000 32K A6D5F A8000 Reserved AED5F AFFFF Reserved 30 -Ll Video Subsystem (Type 1) A6D5F A8000 Reserved AED5F AFFFF Reserved Mode Hex 10 Address AOOOO Storage Scheme Display Buffer 12345678 Page 1 A6D5F A8000 Reserved I I ~32K ~ CO L._._._._. __ J C1 28000 L ______ J L ______ J Page 2 AED5F AFFFF L ______ J Reserved MSB . . .. C2 C3 LSB • Four bits per PEL • 16 colors per PEL • One bit from each bit plane (C3.C2.C1.CO) per PEL • First PEL is MSB of all four bit planes Mapa Blue Bit Plane (CO) Address AOOOO - ,....----.., -""TI-""TI- Map 1 Green Bit Plane (C1) AOOOO 28000 32K I-~R:-e-s-erv-ed--I ~~ A6D5F A8000 AED5F AFFFF A6D5F ABOOO AED5F AFFFF Reserved - Reserved Map3 Intensity Bit Plane (C3) Map 2 Red Bit Plane (C2) AOOOO Reserved I I ~~ AOOOO 28000 32K A6D5F A8000 Reserved AED5F AFFFF Reserved A6D5F A8000 Reserved AED5F AFFFF Reserved Video Subsystem (Type 1) 31 Mode Hex 11 -6:d Address AOOOO A95FF -_ _ AFFFF Address AOOOO Display Buffer Reserved Storage Scheme Joo I ~1 Bit Plane (CO) I AFFFF 32 I 64K MAPO A95FF 12345678 38400 I ~64K Reserved Video Subsystem (Type 1) 1 L ______ J MSB LSB • One bit per PEL • Two attributes per PEL • First PEL is MSB CO Mode Hex 12 Address AOOOO -6:] +1 Display Buffer A95FF - AFFFF - Reserved Storage Scheme 12345678 L ______ J CO L ______ J C3 ----L- I ~ MSB ..... LSB • Four bits per PEL • 16 colors per PEL • One bit from each bit plane (C3.C2.C1.CO) per PEL • First PEL is MSB of all four bit planes Address AOOOO Map 0 Blue Bit Plane (CO) -6:]J..1 = Map 1 Green Bit Plane (C1) AOOOO ~64K A95FF AFFFF Reserved ~ A95FF AFFFF Map 3 Intensity Plane (C3) Map 2 Red Bit Plane (C2) AOOOO -6:]J..1 = AOOOO ~64K A95FF AFFFF Reserved ~ 6:] A95FF AFFFF 6:] Video Subsystem (Type 1) 33 Mode Hex 13 Address Display Buffer ADOOO - . - - - - - - - - . AF9FF - 1 - - - - - - - 1 AFFFF _ L---:.R,::e;::s,:;erv:...:..:,ed=-----J IT II Storage Scheme MSB • • Address AOOOO - ...--------, Map 0 AF9FC AOOO1 IT 64000 • 64K ~-=---...j~1 - ----Reserved--Map 1 AF9FD AOOO2 Reserved Map 2 AF9FE AOOO3 Reserved Map 3 AF9FF AFFFF 34 Reserved Video Subsystem (Type 1) 8 Bits per PEL • 256 Colors per PEL • 1 PEL per Byte First PEL is at Address AOOOO LSB Memory Operations Write Operations When the system is writing to the display buffer, the maps are enabled by the logical decode of the memory address and the Map Mask register. The addresses used for video memory depend on the mode selected. The data flow for a system Write operation is illustrated in the following figure. Data Rotate Register Set/Reset Register Enable Set/Reset Register Graphics Data Mode Rotate Register Register 4 3 AND /.8 Logic Function !.: 32 Rotate Mux Quad Mux 32x 3/1 16/8 B Plane / - / - - - t - 'n' System Data ENA Bit Mask Register 17161514131211101 IsF---------~~O S Mux Octal 211 AND" Ll_----' ~-------~~ Figure 17. Data Flow for Write Operations Video Subsystem (Type 1) 35 Read Operations The two ways to read the video buffer are selected through the Graphics Mode register in the graphics controller. The Mode 0 Read operation returns the a-bit value determined by the logical decode of the memory address and, if applicable, the Read Map Select register. The Mode 1 Read operation returns the a-bit value resulting from the Color Compare operation controlled by the Color Compare and Color Don't Care registers. The data flow for the Color Compare operation is shown in the following figure. Color Compare Register H 1101 Color Don't Care Register 2 I I ,..... 0 I- 1 I2 l3 '-- SlS ~ IN 7ToO Compare '--< EN 7 ............. 0 - EJ 8 L...-. IN '---< r 7ToO Compare EN 7 .............. 0 8is t - - '---< IN 7ToO Compare EN 7 .............. 0 '---< IN 7ToO Compare EN 7 .............. 0 L-B~t AND r--- '--- to r--- Bit 7 AND '---- Figure 18. Color Compare Operations 36 Video Subsystem (Type 1) --- Registers There are six groups of registers in the video subsystem. All video registers are readable except the system data latches and the attribute address flip-flop. The following figure lists the register groups, their 1/0 addresses with the type of access (read or write), and page reference numbers. The question mark in the address can be a hex B or 0 depending on the setting of the 1/0 address bit in the Miscellaneous Output register, described in "General Registers" on page 38. Note: All registers in the video subsystem are read/write. The value of reserved bits in these registers must be preserved. Read the register first and change only the bits required. Register. RIW Port Addre•• General Reglste,. 38 Sequencer Regl.ter. Address Register Data Registers R/W R/W O3C4 03C5 CRT Controller Register. Address Register Data Registers R/W RIW 03?4 03?5 Graphic. Controller Register. Address Register Data Registers R/W RIW 03CE 03CF R/W W R 03CO 03CO 03C1 RIW W R/W R/W 03C8 03C7 03C9 03C6 AHrlbute Controller Register. Address Register Data Registers Video DAC Palette Reglste,. Write Address Read Address Data PEL Mask Page Reference 42 49 68 76 90 Figure 19. Video Subsystem Register Overview Video Subsystem (Type 1) 37 General Registers Register Read Addre•• Write Addre•• Miscellaneous Output Register Input Status Register 0 Input Status Register 1 Feature Control Register Video Subsystem Enable Register 03CC 03C2 03?A 03CA 03C3 03C2 03?A 03C3 Figure 20. General Registers Miscellaneous Output Register The read address for this register is hex 03CC and its write address is hex 03C2. Bit Function 7 6 5,4 3, 2 1 Vertical Sync Polarity Horizontal Sync Polarity Reserved Clock Select Enable RAM 110 Address Select o Figure 21. Miscellaneous Output Register, Hex 03CC/03C2 Bit 7 38 When set to 0, this bit selects a positive 'vertical retrace' signal. This bit works with bit 6 to determine the vertical size. Video Subsystem (Type 1) When set to 0, this bit selects a positive 'horizontal retrace' signal. Bits 7 and 6 select the vertical size as shown in the following figure. Bit 6 Bits 76 Vertical Size 00 01 10 11 Reserved 400 lines 350 lines 480 lines Figure 22. Display Vertical Size Blt8 5, 4 Reserved. Bits 3, 2 These two bits select the clock source according to the following figure. The external clock is driven through the auxiliary video extension. The input clock should be kept between 14.3 MHz and 28.4 MHz. Bits 32 o0 o1 10 11 Function Selects 25.175 MHz clock for 640/320 Horizontal PELs Selects 28.322 MHz clock for 720/360 Horizontal PELs Selects External Clock Reserved Figure 23. Clock Select Definitions Bit 1 When set to 0, this bit disables address decode for the display buffer from the system. Bit 0 This bit selects the CRT controller addresses. When set to 0, this bit sets the CRT controller addresses to hex 03Bx and the address for the Input Status Register 1 to hex 03BA for compatibility with the monochrome adapter. When set to 1, this bit sets CRT controller addresses to hex 03Dx and the Input Status Register 1 address to hex 03DA for compatibility with the color/graphics adapter. The Write addresses to the Feature Control register are affected in the same manner. Video Subsystem (Type 1) 39 Input Status Register 0 The address for this read-only register is address hex 03C2. Bit Function 7 6, 5 4 3-0 CRT Interrupt Reserved Switch Sense Bit Reserved Figure 24. Input Status Register 0, Hex 03C2 Bit 7 When set to 1, this bit indicates a vertical retrace interrupt is pending. Bits 6, 5 Reserved. Bit 4 This bit is used by BIOS in determining the type of display attached. Bits 3 - 0 Reserved. Input Status Register 1 The address for this read-only register is address hex 03DA or 03BA. Bit Function 7-4 3 2, 1 0 Reserved Vertical Retrace Reserved Display Enable Figure 25. Input Status Register 1, Hex 03DA/03BA Bits 7 - 4 Reserved. Bit 3 When set to 1, this bit indicates a vertical retrace interval. This bit can be programmed, through the Vertical Retrace End register, to generate an interrupt at the start of the vertical retrace. Bits 2, 1 Reserved. 40 Video Subsystem (Type 1) Bit 0 When set to 1, this bit indicates a horizontal or vertical retrace interval. This bit is the real-time status of the inverted 'display enable' signal. Programs have used this status bit to restrict screen updates to the inactive display intervals in order to reduce screen flicker. The video subsystem is designed to eliminate this software requirement; screen updates may be made at any time without screen degradation. Feature Control Register This register's write address is hex 03DA or 03BA; its read address is hex 03CA. All bits are reserved. Bit Function 7- 0 Reserved Figure 26. Feature Control Register, Hex 03DA/03BA and 03CA Video Subsystem Enable Register This register is at address hex 03C3. Accessing this register does not affect the video POS enable bit described in "Programmable Option Select" on page 10. Bit Function 7- 1 Reserved Video Subsystem Enable o Figure 27. Video Subsystem Enable Register, Hex 03C4 Bits 7 - 1 Reserved. Bit 0 When this bit is set to 1, the 1/0 and memory address decoding for the video subsystem are enabled. When set to 0, this bit disables the video 1/0 and memory address decoding. Video Subsystem (Type 1) 41 Sequencer Registers The Address register is at address hex 03C4 and the data registers are at address hex 03C5. All registers within the sequencer are read/write. Register Index (Hex) Sequencer Address Reset Clocking Mode Map Mask Character Map Select Memory Mode 00 01 02 03 04 Figure 28. Sequencer Registers Sequencer Address Register The Address register is at address hex 03C4. This register is loaded with an index value that points to the desired sequencer data register. Bit Function 7-3 2-0 Reserved Sequencer Address Figure 29. Sequencer Address Register Bits 7 - 3 Reserved. Bits 2 - 0 These bits contain the index value that points to the data register to be accessed. 42 Video Subsystem (Type 1) Reset Register This read/write register has an index of hex 00; its address is hex 03C5. Bit Function 7- 2 1 Reserved Synchronous Reset Asynchronous Reset o Figure 30. Reset Register, Index Hex 00 Bits 7 - 2 Reserved. Bit 1 When set to 0, this bit commands the sequencer to synchronously clear and halt. Bits 1 and 0 must be 1 to allow the sequencer to operate. To prevent the loss of data, bit 1 must be set to 0 during the active display interval before changing the clock selection. The clock is changed through the Clocking Mode register or the Miscellaneous Output register. Bit 0 When set to 0, this bit commands the sequencer to asynchronously clear and halt. Resetting the sequencer with this bit can cause loss of video data. Clocking Mode Register This read/write register has an index of hex 01; its address is hex 03C5. BH Function 7,6 5 Reserved Screen Off Shift 4 Dot Clock Shift Load Reserved 8/9 Dot Clocks 4 3 2 1 0 Figure 31. Clocking Mode Register, Index Hex 01 Bits 7, 6 Reserved. Video Subsystem (Type 1) 43 Bit 5 When set to 1, this bit turns off the display and assigns maximum memory bandwidth to the system. Although the display is blanked, the synchronization pulses are maintained. This bit can be used for rapid full~screen updates. Bit 4 When this bit and bit 2 are set to 0, the video serializers are loaded every character clock. When this bit is set to 1, the serializers are loaded every fourth character clock, which is useful when 32 bits are fetched per cycle and chained together in the shift registers. Bit 3 When set to 0, this bit selects the normal dot clocks derived from the sequencer master clock input. When this bit is set to 1, the master clock will be divided by 2 to generate the dot clock. All other timings are affected because they are derived from the dot clock. The dot clock divided by 2 is used for 320 and 360 horizontal PEL modes. Bit 2 When this bit and bit 4 are set to 0, the video serializers are loaded every character clock. When this bit is set to 1, the video serializers are loaded every other character clock, which is useful when 16 bits are fetchf:ld per cycle and chained together in the shift registers. Bit 1 Reserved. Bit 0 When set to 0, this bit directs the sequencer to generate character clocks 9 dots wide; when set to 1, it directs the sequencer to generate character clocks 8 dots wide. The 9 dot mode is for alphanumeric modes 0+, 1 +, 2 +, 3 +, 7 and 7 + only; the 9th dot equals the 8th dot for ASCII codes hex CO through OF. All other modes must use 8 dots per character clock. See the line graphics character bit in the Attribute Mode Control register on page 78. 44 Video Subsystem (Type 1) Map Mask Register This read/write register has an index of hex 02; its address is. hex 03C5. Bit Function 7-4 3 2 1 0 Reserved Map3 Enable Map2 Enable Map 1 Enable Map o Enable Figure 32. Map Mask Register, Index Hex 02 Bits 7 - 4 Reserved. Bits 3 - 0 When set to 1, these bits enable system access to the corresponding map. If all maps are enabled, the system can write its 8-bit value to all four maps in a single memory cycle. This substantially reduces the system overhead during display updates in graphics modes. Data scrolling operations can be enhanced by enabling all maps and writing the display buffer address with the data stored in the system data latches. This is a Read-Modify-Write operation. When odd/even modes are selected, maps 0 and 1 and maps 2 and 3 should have the same map mask value. When chain 4 mode is selected, all maps should be enabled. Video Subsystem (Type 1) 45 Character Map Select Register This register's index is hex 03; its address is hex 03C5. In alphanumeric modes, bit 3 of the attribute byte normally defines the foreground intensity. This bit can be redefined as a switch between character sets allowing 512 displayable characters. To enable this feature: 1. Set the extended memory bit in the Memory Mode register (hex 04) to 1. 2. Select different values for character map A and character map B. This function is supported by BIOS and is a function call within the character generator routines. Bit Function 7,6 5 4 3,2 1,0 Reserved Character Character Character Character Map A Select (MSB) Map B Select (MSB) Map A Select Map B Select Figure 33. Character Map Select Register, Index Hex 03 Bits 7, 6 Reserved. Bit 5 This bit is the most-significant bit for selecting the location of character map A. Bit 4 This bit is the most-significant bit for selecting the location of character map B. 46 Video Subsystem (Type 1) BI18 3, 2 Bits 532 000 001 010 01 1 100 101 110 1 11 These bits and bit 5 select the location of character map A. Map A is the area of map 2 containing the character font table used to generate characters when attribute bit 3 is set to 1. The selection is shown in the following figure. Map Selected o 1 2 3 4 5 6 7 Table Location 1st 8KB of Map 2 3rd 8KB of Map 2 5th 8KB of Map 2 7th 8KB of Map 2 2nd 8KB of Map 2 4th 8KB of Map 2 6th 8KB of Map 2 8th 8KB of Map 2 Figure 34. Character Map Select A 81181,0 These bits and bit 4 select the location of character map B. Map B is the area of map 2 containing the character font table used to generate characters when attribute bit 3 is set to O. The selection is shown in the following figure. Bits 410 Map Selected 000 001 010 011 100 101 1 10 111 o 2 3 4 5 6 7 Table Location 1st 8KB of Map 2 3rd 8KB of Map 2 5th 8KB of Map 2 7th 8KB of Map 2 2nd 8KB of Map 2 4th 8KB of Map 2 6th 8KB of Map 2 8th 8KB of Map 2 Figure 35. Character Map Select B Video Subsystem (Type 1) 47 Memory Mode Register This register's index is hex 04; its address is hex 03C5. Bit Function 7-4 Reserved Chain 4 Odd/Even Extended Memory Reserved 3 2 1 0 Figure 36. Memory Mode Register, Index Hex 04 Bits 7 - 4 Reserved. Bit 3 This bit controls the map selected during system Read operations. When set to 0, this bit enables system addresses to sequentially access data within a bit map by using the Map Mask register. When set to 1, this bit causes the two low-order bits to select the map accessed as shown in following figure. Addre.. Bits A1 AO Map Selected 00 0 1 0 1 1 2 3 o1 1 Figure 37. Map Selection, Chain 4 Bit 2 When this bit is set to 0, even system addresses access maps 0 and 2, while odd system addresses access maps 1 and 3. When this bit set to 1, system addresses sequentially access data within a bit map, and the maps are accessed according to the value in the Map Mask register (hex 02). Bit 1 When set to 1, this bit enables the video memory from 64KB to 256KB. This bit must be set to 1 to enable the character map selection described for the previous register. Bit 0 Reserved. 48 Video Subsystem (Type 1) CRT Controller Registers A data register is accessed by writing its index to the Address register at address hex 0304 or 03B4, and then writing the data to the access port at address hex 0305 or 03B5. The 1/0 address used depends on the setting of the 1/0 address select bit (bit 0) in the Miscellaneous Output register, which is described in "General Registers" on page 38. The following figure shows the variable part of the address as a question mark. Note: When modifying a register, the setting of reserved bits must be preserved. Read the register first and change only the bits required. Addre•• Index Reglater (Hex) (Hex) Address Horizontal Total Horizontal Display Enable End Start Horizontal Blanking End Horizontal Blanking Start Horizontal Retrace Pulse End Horizontal Retrace Vertical Total Overflow Preset Row Scan Maximum Scan Line Cursor Start Cursor End Start Address High Start Address Low Cursor Location High Cursor Location Low Vertical Retrace Start Vertical Retrace End Vertical Display Enable End Offset Underline Location Start Vertical Blanking End Vertical Blanking CRT Mode Control Line Compare 03?4 0315 0315 0315 03?5 0315 0315 0315 03?5 0315 03?5 0315 03?5 0315 03?5 0315 0315 0315 03?5 0315 0315 0315 0315 0315 0315 0315 00 01 02 03 04 05 06 07 08 09 OA OB OC 00 OE OF 10 11 12 13 14 15 16 17 18 Figure 38. CRT Controller Registers Video Subsystem (Type 1) 49 Address Register This register is at address hex 0384 or 0304, and is loaded with an index value that points to the data registers within the CRT controller. Bit Function 7- 5 4-0 Reserved Index 4 - 0 Figure 39. CRT Controller Address Register, Hex 0384/0304 Bits 7 - 5 Reserved. Bits 4 - 0 These bits are the index that points to the data register accessed through address hex 0305 or 0385. Horizontal Total Register This register's index is hex 00; its address is hex 0305 or 0385. It defines the total number of characters in the horizontal scan interval including the retrace time. The value directly controls the period of the 'horizontal retrace' signal. A horizontal character counter in the CRT controller counts the character clock inputs; comparators are used to compare the register value with the character's horizontal width to provide horizontal timings. All horizontal and vertical timings are based on this register. Bit Function 7-0 Horizontal Total Figure 40. Horizontal Total Register, Index Hex 00 Bits 7 - 0 50 The value of these bits is the total number of characters minus 5. Video Subsystem (Type 1) Horizontal Display-Enable End Register This register's index is hex 01; its address is hex 0305 or 0385. BII Function 7- 0 Horizontal Display Enable End Figure 41. Horizontal Display Enable-End Register, Index Hex 01 Bits 7 - 0 These bits define the length of the 'horizontal display-enable' signal, and determine the number of character positions per horizontal line. The value of these bits is the total number of displayed characters minus 1. Start Horizontal Blanking Register This register's index is hex 02; its address is hex 0305 or 0385. BII Function 7- 0 Start Horizontal Blanking Figure 42. Start Horizontal Blanking Register, Index Hex 02 Bits 7 - 0 This value is the horizontal character count where the 'horizontalbhtnking' signal goes active. End Horizontal Blanking Register This register's index is hex 03; its address is hex 0305 or 0385. It determines when the 'horizontal blanking' signal will go active. BII Function 7 Reserved Display Enable Skew Control End Blanking 6,5 4-0 Figure 43. End Horizontal Blanking Register, Index Hex 03 Bit 7 Reserved. Video Subsystem (Type 1) 51 Bits 6,5 Bits 65 o0 o1 10 11 These two bits determine the amount of skew of the 'display enable' signal. This skew control is needed to provide sufficient time for the CRT controller to read a character and attribute code from the video buffer, to gain access to the character generator, and go through the Horizontal PEL Panning register in the attribute controller. Each access requires the 'display enable' signal to be skewed one character clock so that the video output is synchronized with the horizontal and vertical retrace signals. The skew values are shown in the following figure. Amount of Skew No character clock skew One character clock skew Two character clock skew Three character clock skew Figure 44. Display Enable Skew Bits 4 - 0 These bits are the five low-order bits of a 6-bit value that is compared with the value in the Start Horizontal Blanking register to determine when the 'horizontal blanking' Signal will go inactive. The most-significant bit is bit 7 in the End Horizontal Retrace register (index hex 05). To program th~l:le bits for a signal width of W, the following algorithm is used: the width W, in character clock units, is added to the value from the Start Horizontal Blanking register. The six low-order bits of the result are the 6-bit value programmed. 52 Video Subsystem (Type 1) Start Horizontal Retrace Pulse Register This register's index is hex 04; its address is hex 03D5 or 03B5. Bit Function 7-0 Start Horizontal Retrace Pulse Figure 45. Start Horizontal Retrace Pulse Register, Index Hex 04 Bits 7 - 0 These bits are used to center the screen horizontally by specifying the character position where the 'horizontal retrace' signal goes active. End Horizontal Retrace Register This register's index is hex 05; its address is hex 03D5 or 03B5. Bit Function 7 6, 5 4-0 End Horizontal Blanking, Bit 5 Horizontal Retrace Delay End Horizontal Retrace Figure 46. End Horizontal Retrace Register, Index Hex 05 Bit 7 This bit is the most-significant bit of the end horizontal blanking value in the End Horizontal Blanking register (index hex 03). Bits 6,5 These bits control the skew of the 'horizontal retrace' signal. The value of these bits is the amount of skew provided (from 0 to 3 character clock units). For certain modes, the 'horizontal retrace' signal takes up the entire blanking interval. Some internal timings are generated by the falling edge of the 'horizontal retrace' signal. To ensure that the signals are latched properly, the 'retrace' signal is started before the end of the 'display enable' signal and then skewed several character clock times to provide the proper screen centering. Video Subsystem (Type 1) 53 Blla 4 - 0 These bits are compared with the Start Horizontal Retrace register to give a horizontal character count where the 'horizontal retrace' signal goes inactive. To program these bits with a signal width of W, the following algorithm is used: the width W, in character clock units, is added to the value in the Start Retrace register. The five low-order bits of the result are the 5-bit value programmed. V.rtlcal Total Reglst.r This register's index is hex 06; its address is hex 0305 or 03B5. Bit Funcllon 7- 0 Vertical Total Figure 47. Vertical Total Register, Index Hex 06 Blta 7 - 0 These are the eight low-order bits of a 10-bit vertical total. The value for the vertical total is the number of horizontal raster scans on the display, including vertical retrace, minus 2. This value determines the period of the 'vertical retrace' signal. Bits 8 and 9 are in the Overflow register (Index hex 07). 54 Video Subsystem (Type 1) Overflow Register This register's index is hex 07; its address is hex 0305 or 03B5. Bit Function 7 6 5 4 3 2 1 Vertical Retrace Start, Bit 9 Vertical Display Enable End, Bit 9 Vertical Total, Bit 9 Line Compare, Bit 8 Vertical Blanking Start, Bit 8 Vertical Retrace Start, Bit 8 Vertical Display Enable End, Bit 8 Vertical Total, Bit 8 o Figure 48. CRT Overflow Register, Index Hex 07 Bit 7 Bit 9 of the Vertical Retrace Start register (index hex 10). Bit 6 Bit 9 of the Vertical Display Enable End register (index hex 12). Bit 5 Bit 9 of the Vertical Total register (index hex 06). Bit 4 Bit 8 of the Li ne Com pare register (i ndex hex 18). Bit 3 Bit 8 of the Start Vertical Blanking register (index hex 15). Bit 2 Bit 8 of the Vertical Retrace Start register (index hex 10). Bit 1 Bit 8 of the Vertical Display Enable End register (index hex 12). Bit 0 Bit 8 of the Vertical Total register (index hex 06). Video Subsystem (Type 1) 55 Preset Row Scan Register This register's index is hex 08; its address is hex 0305 or 03B5. Bit Function 7 Reserved Byte Panning 1 Byte Panning 0 Starting Row Scan Count 6 5 4-0 Figure 49. Preset Row Scan Register, Index Hex 08 Bit 7 Reserved. Bits 6, 5 These two bits control byte panning in multiple shift modes. (Current BIOS modes do not use multiple shift operation.) These bits are used in PEL-panning operations, and should normally be set to O. The PEL Panning register in the attribute controller provides panning of up to eight individual PELs. In single-byte shift modes, to pan to the next higher PEL (8 or 9), the CRT controller start address is incremented and the PEL Panning register is reset to O. In multiple shift modes, the byte-panning bits are used as extensions to the PEL Panning register. This allows panning across the width of the video output shift. For example, in the 32-bit shift mode, the byte pan and PEL-panning bits provide up to 31 bits of panning capability. To pan from position 31 to 32, the CRT controller start address is incremented and the panning bits, both PEL and byte, are reset to O. Bits 4·0 These bits specify the row scan count for the row starting after a vertical retrace. The row scan counter is incremented every horizontal retrace time until the maximum row scan occurs. When the maximum row scan is reached, the row scan counter is cleared (not preset). Note: The CRT controller latches the start address at the start of the vertical retrace. These register values should be loaded during the active display time. 56 Video Subsystem (Type 1) Maximum Scan Line Register This register's index is hex 09; its address is hex 0305 or 03B5. Bit Function 7 6 5 4-0 200 to 400 Line Conversion Line Compare, Bit 9 Start Vertical Blanking, Bit 9 Maximum Scan Line Figure 50. Maximum Scan Line Register, Index Hex 09 Bit 7 When this bit is set to 1, 200-scan-line video data is converted to 400-scan-line output. To do this, the clock in the row scan counter is divided by 2, which allows the 200-line modes to be displayed as 400 lines on the display (this is called double scanning; each line is displayed twice). When this bit is set to 0, the clock to the row scan counter is equal to the horizontal scan rate. Bit 6 Bit 9 of the Line Compare register (index hex 18). Bit 5 Bit 9 of the Start Vertical Blanking register (index hex 15). Bits 4 - 0 These bits specify the number of scan lines per character row. The value of these bits is the maximum row scan number minus 1. Video Subsystem (Type 1) 57 Cursor Start Register This register's index is hex OA; its address is hex 0305 or 0385. BII Function 7,6 Reserved Cursor Off Row Scan Cursor Begins 5 4-0 Figure 51. Cursor Start Register, Index Hex OA Bits 7, 6 Reserved. Bit 5 When set to 1, this bit disables the cursor. Bits 4 - 0 These bits specify the row within the character box where the cursor begins. The value of these bits is the first line of the cursor minus 1. When this value is greater than that in the Cursor End register, no cursor is displayed. Cursor End Register This register's index is hex 08; its address is hex 0305 or 0385. BII Function 7 Reserved Cursor Skew Control Row Scan Cursor Ends 6,5 4-0 Figure 52. Cursor End Register, Index Hex OB Bit 7 Reserved. Bits 6, 5 These bits control the skew of the cursor. The skew value delays the cursor by the selected number of character clocks from 0 to 3. For example, a skew of 1 moves the cursor right one position on the screen. Bits 4 - 0 These bits specify the row within the character box where the cursor ends. If this value is less that the cursor start value, no cursor is displayed. 58 Video Subsystem (Type 1) Start Address High Register This register's index is hex OC; its address is hex 0305 or 0385. Bit Function 7-0 High Byte of the Start Address Figure 53. Start Address High Register, Index Hex OC Bits 7 - 0 These are the eight high-order bits of a 16-bit value that specifies the starting address for the regenerative buffer. The start address points to the first address after the vertical retrace on each screen refresh. Note: The CRT controller latches the start address at the start of the vertical retrace. These register values should be loaded during the active display time. Start Address Low Register This register's index is hex 00; its address is hex 0305 or 0385. Bit Function 7-0 Low Byte of the Start Address Figure 54. Start Address Low Register, Index Hex 00 Bits 7 - 0 These are the eight low-order bits of the starting address for the regenerative buffer. Cursor Location High Register This register's index is hex OE; its address is hex 0305 or 0385. Bit Function 7-0 High Byte of the Cursor Location Figure 55. Cursor Location High Register, Index Hex OE Bits 7 - 0 These are the eight high-order bits of the 16-bit cursor location. Video Subsystem (Type 1) 59 Cursor Location Low Register This register's index is hex OF; its address is hex 0305 or 03B5. Bit Function 7- 0 Low Byte of the Cursor Location Figure 56. Cursor Location Low Register, Index Hex OF Bits 7 ·0 These are the eight low-order bits of the cursor location. Vertical Retrace Start Register This register's index is hex 10; its address is hex 0305 or 03B5. Bit Function 7-0 Vertical Retrace Pulse Figure 57. Vertical Retrace Start Register, Index Hex 10 Bits 7 • 0 These are the eight low-order bits of the 9-bit start position for the 'vertlcal retrace' pulse; it is programmed in horizontal scan lines. Bit 8 is in the Overflow register (index hex 07). Vertical Retrace End Register This register's index is hex 11; its address is hex 0305 or 03B5. Bit Function 7 6 5 4 3- 0 Protect Registers 0-7 Select 5 Refresh Cycles -Enable Vertical Interrupt -Clear Vertical Interrupt Vertical Retrace End Figure 58. Vertical Retrace End Register, Index Hex 11 Bit 7 60 When set to 1, this bit disables write access to the CRT controller registers at index 00 through 07. The line compare bit in the Overflow register (index hex 07) is not protected. Video Subsystem (Type 1) Bit 6 When set to 1, this bit generates five memory refresh cycles per horizontal line. When set to 0, this bit selects three refresh cycles. Selecting five refresh cycles allows use of the VGA chip with 15.75 kHz displays. This bit should be set to 0 for supported operations. It is set to 0 by a BIOS mode set, a reset, or a power on. Bit 5 When set to 0, this bit enables a vertical retrace interrupt. The vertical retrace interrupt is IRQ2. This interrupt level can be shared; therefore, to determine whether the video generated the interrupt, check the CRT interrupt bit in Input Status Register O. Bit 4 When set to 0, this bit clears a vertical retrace interrupt. At the end of the active vertical display time, a flip-flop is set to indicate an interrupt. An interrupt handler resets this flip-flop by first setting this bit to 0, then resetting it to 1. Bits 3 - 0 The Vertical Retrace Start register is compared with these four bits to determine where the 'vertical retrace' signal goes inactive. It is programmed in units of horizontal scan lines. To program these bits with a signal width of W, the following algorithm is used: the width W, in horizontal scan units, is added to the value in the Start Vertical Retrace register. The four low-order bits of the result are the 4-bit value programmed. Vertical Display Enable End Register This register's index is hex 12; its address is hex 0305 or 03B5. Bit Function 7-0 Vertical Display Enable End Figure 59. Vertical Display Enable End Register, Index Hex 12 Bits 7 - 0 These are the eight low-order bits of a 10-bit value that defines the vertical-display-enable end position. The two high-order bits are contained in the Overflow register (index hex 07). The 10-bit value is equal to the total number of scan lines minus 1. Video Subsystem (Type 1) 61 Offset Register This register's index is hex 13; its address is hex 0305 or 0385. Bit Function 7- 0 Logical Line Width of the Screen Figure 60. Offset Register, Index Hex 13 Bits 7 - 0 These bits specify the logical line width of the screen. The starting memory address for the next character row is larger than the current character row by 2 or 4 times the value of these bits. Depending on the method of clocking the CRT controller, this address is either a word or doubleword address. Underline Locallon Register This register's index is hex 14; its address is hex 0305 or 0385. Bit Function 7 Reserved Doubleword Mode Count By 4 Start Underline 6 5 4-0 Figure 61. Underline Location Register, Index Hex 14 Bit 7 Reserved. Bit 6 When this bit is set to 1, memory addresses are doubleword addresses. See the description of the word/byte mode bit (bit 6) in the CRT Mode Control register on page 64. Bit 5 When this bit is set to 1, the memory-address counter is clocked with the character clock divided by 4, which is used when doubleword addresses are used. Bits 4 - 0 These bits specify the horizontal scan line of a character rowan which an underline occurs. The value programmed is the scan line desired minus 1. 62 Video Subsystem (Type 1) Start Vertical Blanking Register This register's index is hex 15; its address is hex 0305 or 03B5. Bit Function 7-0 Start Vertical Blanking Figure 62. Start Vertical Blanking Register, Index Hex 15 Bits 7 - 0 These are the eight low-order bits of a 10-bit value that specifies the starting location for the 'vertical blanking' signal. Bit a is in the Overflow register (index hex 07) and bit 9 is in the Maximum Scan Line register (index hex 09). The 10-bit value is the horizontal scan line count where the 'vertical blanking' signal becomes active minus 1. End Vertical Blanking Register This register's index is hex 16; its address is hex 0305 or 03B5. Bit Function 7-0 End Vertical Blanking Figure 63. End Vertical Blanking Register, Index Hex 16 Bits 7 - 0 This register specifies the horizontal scan count where the 'vertical blanking' signal becomes inactive. The register is programmed in units of the horizontal scan line. To program these bits with a 'vertical blanking' signal of width W, the following algorithm is used: the width W, in horizontal scan line units, is added to the value in the Start Vertical Blanking register minus 1. The eight low-order bits of the result are the a-bit value programmed. Video Subsystem (Type 1) 63 CRT Mode Control Register This register's index is hex 17; its address is hex 0305 or 0385. Bit Function 7 6 5 4 3 2 Hardware Reset Word/Byte Mode Address Wrap Reserved Count By Two Horizontal Retrace Select Select Row Scan Counter CMSO o Figure 64. CRT Mode Control Register, Index Hex 17 Bit 7 When set to 0, this bit disables the horizontal and vertical retrace signals and forces them to an inactive level. When set to 1, this bit enables the horizontal and vertical retrace signals. This bit does not reset any other registers or signal outputs. Bit 6 When this bit is set to 0, the word mode is selected. The word mode shifts the memory-address counter bits down one bit; the most-significant bit of the counter appears on the least-significant bit of the memory address outputs. The doubleword bit in the Underline Location register (hex 14) also controls the addressing. When the doubleword bit is 0, the word/byte bit selects the mode. When the doubleword bit is set to 1, the addressing is shifted by two bits. 64 Video Subsystem (Type 1) When set to 1, bit 6 selects the byte address mode. See the following figures for address output details. Clock Add ress Cou nter MAO _ to MA15 - Byte, Word, DoubleWord Mux MAO to ~ MA15 Output Mux MAO to --MA15 Bit 5- Address Wrap Bit 6- Wordl Byte Bit 6 - Double word Mode_ Row Sean Oa nd 1 Bit 0 CMS 0 Bit 1 SRSC Control Memory Address Outputs Modes of Addressing Byte Word Doubleword MAO/RFA0 MA 1/RFA 1 MA21RFA2 MA 3/RFA 3 MA4/RFA4 MA5/RFA5 MA6/RFA6 MA 7/RFA 7 MA 8/RFA8 MA9 MA 10 MA 11 MA 12 MA 13 MA 14 MA 15 MAO MA 1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MAiO MA 11 MA 12 MA 13 MA14 MA 15 MA 12 MA 13 MAO MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MAiO MA 11 MA 12 MA 13 MA 150r 13 MAO MA 1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MAiO MA 11 MA 12 MA 13 MA 14 Figure 65. CRT Memory Address Mapping Bit 5 This bit selects the memory-address bit, bit MA 13 or MA 15, that appears on the output pin MA 0, in the word address mode. If the VGA is not in the word address mode, bit 0 from the address counter appears on the output pin, MA O. Video Subsystem (Type 1) 65 When set to 1, this bit selects MA 15. In odd/even mode, this bit should be set to 1 because 256KB of video memory is installed on the system board. (Bit MA 13 is selected in applications where only 64KB is present. This function maintains compatibility with the IBM Color/Graphics Monitor Adapter.) Bit 4 Reserved. Bit 3 When this bit is set to 0, the address counter uses the character clock. When this bit is set to 1, the address counter uses the character clock input divided by 2. This bit is used to create either a byte or word refresh address for the display buffer. Bit 2 This bit selects the clock that controls the vertical timing counter. The clocking is either the horizontal retrace clock or horizontal retrace clock divided by 2. When this bit is set to 1, the horizontal retrace clock is divided by 2. Dividing the clock effectively doubles the vertical resolution of the CRT controller. The vertical counter has a maximum resolution of 1024 scan lines because the vertical total value is la-bits wide. If the vertical counter is clocked with the horizontal retrace divided by 2, the vertical resolution is doubled to 2048 scan lines. Bit 1 66 This bit selects the source of bit 14 of the output multiplexer. When this bit is set to 0, bit 1 of the row scan counter is the source. When this bit is set to 1, the bit 14 of the address counter is the source. Video Subsystem (Type 1) BIIO This bit selects the source of bit 13 of the output multiplexer. When this bit is set to 0, bit 0 of the row scan counter is the source, and when this bit is set to 1, bit 13 of the address counter is the source. The CRT controller used on the IBM Color/Graphics Adapter was capable of using 128 horizontal scan-line addresses. For the VGA to obtain 640-by-200 graphics resolution, the CRT controller is programmed for 100 horizontal scan lines with two scan-line addresses per character row. Row scan address bit 0 becomes the most-significant address bit to the display buffer. Successive scan lines of the display image are displaced in 8KB of memory. This bit allows compatibility with the graphics modes of earlier adapters. Line Compare Reglsler This register's index is hex 18; its address is hex 0305 or 03B5. Bit Function 7- 0 Line Compare Target Figure 66. Line Compare Register. Index Hex 18 Blls 7 - 0 These bits are the eight low-order bits of the 10-bit compare target. When the vertical counter reaches the target value, the internal start address of the line counter is cleared. This creates a split screen where the lower screen is immune to scrolling. Bit 8 is in the Overflow register (index hex 07), and bit 9 is in the Maximum Scan Line register (index hex 09). Video Subsystem (Type 1) 67 Graphics Controller Registers The Address register for the graphics controller is at address hex 03CE. The data registers are at address hex 03CF. All registers are read/write. Register Name Addre•• (Hex) Address Set/Reset Enable Set/Reset Color Compare Data Rotate Read Map Select Graphics Mode Miscellaneous Color Oon't Care Bit Mask 03CE 03CF 03CF 03CF 03CF 03CF 03CF 03CF 03CF 03CF Index (Hex) 00 01 02 03 04 05 06 07 08 Figure 67. Graphics Controller Register Overview Address Register The Address register is at address hex 03CE. This register is loaded with the index value that pOints to the desired data register within the graphics controller. Bit Function 7- 4 3- 0 Reserved Register Index Figure 68. Graphics Controller Address Register, Hex 03CE Bits 7 - 4 Reserved. Bits 3 - 0 These bits contain the index value that points to the data registers. 68 Video Subsystem (Type 1) Set/Reset Register This register's index is hex 00; its address is hex 03CF. Bit Function 7-4 Reserved Set/Reset Set/Reset Set/Reset Set/Reset 3 2 1 0 Map 3 Map 2 Map 1 Map 0 Figure 69. Set/Reset Register, Index Hex 00 Bits 7 - 4 Reserved. Bits 3 - 0 When write mode 0 is selected, the system writes the value of each set/reset bit to its respective memory map. For each Write operation, the set/reset bit, if enabled, is written to all eight bits within that map. Set/reset operation can be enabled on a map-by-map basis through the Enable Set/Reset register. Enable Set/Reset Register The index for this register is hex 01; its address is hex 03CF. Bit Function 7- 4 3 2 1 Reserved Enable Set/Reset Enable Set/Reset Enable Set/Reset Enable Set/Reset o Map Map Map Map 3 2 1 0 Figure 70. Enable Set/Reset Register, Index Hex 01 Bits 7 - 4 Reserved. Bits 3 - 0 These bits enable the set/reset function used when write mode 0 is selected in the Graphics Mode register (index hex 05). When the bit is set to 1, the respective memory map receives the value specified in the Set/Reset register. When Set/Reset is not enabled for a map, that map receives the value sent by the system. Video Subsystem (Type 1) 69 Color Compare Register This register's index is hex 02; its address is hex 03CF. Bit Function 7- 4 3 2 1 Reserved Color Compare Color Compare Color Compare Color Compare o Map 3 Map 2 Map 1 Map 0 Figure 71. Color Compare Register, Index Hex 02 Bits 7 - 4 Reserved. Bits 3 - 0 These bits are the 4-bit color value to be compared when the read mode bit in the Graphics Mode register is set to 1. When the system does a memory read, the data returned from the memory cycle will be a 1 in each bit position where the four maps equal the Color Compare register. If the read mode bit is 0, the data is returned without comparison. The color compare bit is the value that all bits of the corresponding map's byte are compared with. Each of the eight bit positions in the selected byte are compared across the four maps, and a 1 is returned in each position where the bits of all four maps equal their respective color compare values. 70 Video Subsystem (Type 1) Data Rotate Register This register's index is hex 03; its address is hex 03CF. Bit Function 7- 5 4, 3 2- 0 Reserved Function Select Rotate Count Figure 72. Data Rotate Register, Index Hex 03 Bits 7 - 5 Reserved. Bits 4, 3 Data written to the video buffer can be operated on logically by data already in the system latches. Data can be any of the choices selected by the write mode bits except system latches, which cannot be modified. If rotated data is selected also, the rotate is performed before the logical operation. The logical operations selected are shown in the following table. Bits Function 43 o0 o1 10 11 Data Unmodified Data ANDed with Latched Data Data ORed with Latched Data Data XORed with Latched Data Figure 73. Operation Select Bit Definitions Bits 2 - 0 In write mode 0, these bits select the number of positions the system data is rotated to the right during a system Memory Write operation. To write data that is not rotated in mode 0, all bits are set to O. Video Subsystem (Type 1) 71 Read Map Select Register This register's index is hex 04; its address is hex 03CF. Bit Function 7- 2 1. 0 Reserved Map Select Figure 74. Read Map Select Register. Index Hex 04 Bits 7 - 2 Reserved. Bits 1, 0 These bits select the memory map for system Read operations. This register has no effect on the color compare read mode. In odd/even modes, the value can be a binary 00 or 01 to select the chained maps 0, 1 and the value can be a binary 10 or 11 to select the chained maps 2,3. Graphics Mode Register This register's index is hex 05; its address is hex 03CF. Bit Function 7 Reserved 256-Color Mode Shift Register Mode Odd/Even Read Mode Reserved Write Mode 6 5 4 3 2 1.0 Figure 75. Graphics Mode Register. Index Hex 05 Bit 7 Reserved. Bit 6 When set to 0, this bit allows bit 5 to control the loading of the shift registers. When set to 1, this bit causes the shift registers to be loaded in a manner that supports the 256-color mode. 72 Video Subsystem (Type 1) Bit 5 When set to 1, this bit directs the shift registers in the graphics controller to format the serial data stream with even-numbered bits from both maps on even-numbered maps, and odd-numbered bits from both maps on the odd-numbered maps. This bit is used for modes 4 and 5. Bit 4 When set to 1, this bit selects the odd/even addressing mode used by the IBM Color/Graphics Monitor Adapter. Normally, the value here follows the value of Memory Mode register bit 2 in the sequencer. Bit 3 When this bit is set to 1, the system reads the results of the comparison of the four memory maps and the Color Compare register. When this bit is set to 0, the system reads data from the memory map selected by the Read Map Select register, or by the two low-order bits of the memory address (this selection depends on the chain-4 bit in the Memory Mode register of the sequencer). Bit 2 Reserved. Bits 1, 0 The write mode selected and its operation are defined in the following figure. The logic operation specified by the function select bits is performed on system data for modes 0,2, and 3. Blta 10 00 o1 10 11 Mode Description Each memory map Is written with the system data rotated by the count in the Data Rotate register. Ifthe set/reset function is enabled for a specific map. that map receives the 8-blt value contained in the Set/Reset register. Each memory map Is written with the contents of the system latches. These latches are loaded by a system Read operation. Memory map n (0 through 3) Is filled with eight bits of the value of data bit n. Each memory map Is written with the 8-bit value contained In the Set/Reset register for that map (the Enable Set/Reset register has no effect). Rotated system data is ANDed with the Bit Mask register to form an 8-bit value that performs the same function as the Bit Mask register In write modes 0 and 2 (see also Bit Mask register on page 75). Figure 76. Write Mode Definitions Video Subsystem (Type 1) 73 Miscellaneous Register This register's index is hex 06; its address is hex 03CF. BII Function 7-4 Reserved Memory Map 1 Memory MapO Odd/Even Graphics Mode 3 2 1 0 Figure 77. Miscellaneous Register, Index Hex 06 Bits 7 - 4 Reserved. Bits 3,2 These bits control the mapping of the regenerative buffer into the system address space. The bit functions are defined in the following figure. Blls 32 Addrelling AIIlgnmenl 00 o1 10 11 AOOOO for AOOOO for BOOOO for B8000 for 128KB 64KB 32KB 32KB Figure 78. Video Memory Assignments Bit 1 When set to 1, this bit directs the system address bit, AO, to be replaced by a higher-order bit. The odd map is then selected when AO is 1, and the even map when AO is O. Bit 0 This bit controls alphanumeric mode addressing. When set to 1, this bit selects graphics modes, which also disables the character generator latches. 74 Video Subsystem (Type 1) Color Don't Care Register This register's index is hex 07; its address is hex 03CF. Bit Function 7-4 3 2 1 0 Reserved Map 3 is Don't Map 2 is Don't Map 1 is Don't Map 0 is Don't Care Care Care Care Figure 79. Color Don't Care Register. Index Hex 07 Bits 7 - 4 Reserved. Bits 3 - 0 These bits select whether a map is going to participate in the color compare cycle. When the bit is set to 1. the bits in that map are compared. Bit Mask Register This register's index is hex 08; its address is hex 03CF. Bit Function 7-0 -Bit Mask 7 - 0 Figure 80. Bit Mask Register. Index Hex 08 Bits 7 - 0 When the bit is set to 1, the corresponding bit position in each map can be changed. When the bit set to 0, the bit position in the map is masked to prevent change, provided that the location being written was the last location read by the system microprocessor. The bit mask applies to write modes 0 and 2. To preserve bits using the bit mask, data must be latched internally by reading the location. When data is written to preserve the bits. the most current data in the latches is written in those positions. The bit mask applies to all maps simultaneously. Video Subsystem (Type 1) 75 Attribute Controller Registers Each register for the attribute controller has two addresses. Address hex 03CO is the write address and hex 03C1 is the read address. The individual data registers are selected by writing their index to the Address register. Register Name Address Internal Palette Attribute Mode Control Overscan Color Color Plane Enable Horizontal PEL Panning Color Select Write Addre.. Read Addre.. 03CO 03C1 Index 00- OF 10 11 12 13 14 Figure 81. Attribute Controller Register Addresses Address Register This register is read through address hex 03C1, and written to through address hex 03CO. The attribute controller registers do not have an input bit to control selection of the address and data registers. An internal address flip-flop controls this selection. Reading Input Status Register 1 clears the flip-flop and selects the Address register. After the Address register has been loaded with the index, the next Write operation to 03CO loads the data register. The flip-flop toggles for each Write operation to address hex 03CO. It does not toggle for Read operations to 03C1. (Also see "VGA Programming Considerations" on page 83.) Bit Function 7, 6 5 4-0 Reserved Internal Palette Address Source Register Index Figure 82. Address Register, Hex 03CO Blls 7,6 76 Reserved. Video Subsystem (Type 1) Bit 5 This bit is set to 0 to load color values to the registers in the internal palette. For normal operation of the attribute controller, set this bit to 1, which allows the video data to use the internal palette for output. Bits 4 - 0 These bits contain the index to the data registers in the attribute controller. Internal Palette Registers 0 through F These registers are at indexes hex 00 through OF. Their write address is hex 03CO; their read address is hex 03C1. Bit Function 7,6 Reserved 5 4 3 P5 P4 P3 P2 P1 PO 2 1 0 Figure 83. Internal Palette Registers, Index Hex 00 - OF Bits 7, 6 Reserved. Bits 5 - 0 These 6-bit registers allow a dynamic mapping between the text attribute or graphic color input value and the display color on the CRT screen. When set to 1, this bit selects the appropriate color. The Internal Palette registers should be modified only during the vertical retrace interval to avoid problems with the displayed image. These internal palette values are sent off-chip to the video DAC, where they serve as addresses into the DAC registers. (Also see the attribute controller block diagram on page 7.) Video Subsystem (Type 1) 77 Anrlbute Mode Control Register This read/write register is at index hex 10. Its write address is hex 03CO; its read address is hex 03C1. Bit Function 7 6 5 4 3 2 1 P5. P4 Select PEL Width PEL Panning Compatibility Reserved Enable Blink/-Select Background Intensity Enable Line Graphics Character Code Mono Emulation Graphics/-Alphanumeric Mode o Figure 84. Attribute Mode Control Register. Index Hex 10 Bit 7 This bit selects the source for the P5 and P4 video bits that act as inputs to the video DAC. When this bit is set to 0, P5 and P4 are the outputs of the Internal Palette registers. When this bit is set to 1, P5 and P4 are bits 1 and 0 of the Color Select register. For more information, refer to "VGA Programming Considerations" on page 83. Bit 6 When this bit is set to 1, the video data is sampled so that eight bits are available to select a color in the 256-color mode (hex 13). This bit is set to 0 in all other modes. Bit 5 When this bit is set to 1, a successful line-compare in the CRT controller forces the output of the PEL Panning register to 0 until a vertical synchronization occurs, at which time the output returns to its programmed value. This bit allows a selected portion of a screen to be panned. When this bit is set to 0, line compare has no effect on the output of the PEL Panning register. Bit 4 Reserved. Bit 3 When this bit is set to 0, the most-significant bit of the attribute selects the background intensity (allows 16 colors for background). When set to 1, this bit enables blinking. 78 Video Subsystem (Type 1) Bit 2 When this bit is set to 0, the ninth dot will be the same as the background. When set to 1, this bit enables the special line-graphics character codes for the monochrome emulation mode. This emulation mode forces the ninth dot of a line graphic character to be identical to the eighth dot of the character. The line-graphics character codes for the monochrome emulation mode are hex CO through hex OF. For character fonts that do not utilize these line-graphics character codes, bit 2 should be set to 0 to prevent unwanted video information from displaying on the CRT screen. BIOS will set this bit, the correct dot clock, and other registers when the 9-dot alphanumeric mode is selected. Bit 1 When this bit is set to 1, monochrome emulation mode is selected. When this bit is set to 0, color emulation mode is selected. Bit 0 When set to 1, this bit selects the graphics mode of operation. Video Subsystem (Type 1) 79 Overscan Color Register This read/write register is at index hex 11. Its write address is hex 03CO; its read address is hex 03C1. This register determines the border (overscan) color. Bit Function 7-0 P7-PO Figure 85. Overscan Color Register, Index Hex 11 Bits 7 - 0 These bits select the border color used in the SO-column alphanumeric modes and in the graphics modes other than modes 4, 5, and D. Color Plane Enable Register This read/write register is at index hex 12. Its write address is hex 03CO; its read address is hex 03C1. Bit Function 7- 4 3-0 Reserved Enable Color Plane Figure 86. Color Plane Enable Register, Index Hex 12 Bits 7 - 4 Reserved. Bits 3 - 0 Setting a bit to 1, enables the corresponding display-memory color plane. 80 Video Subsystem (Type 1) Horizontal PEL Panning Register This read/write register is at index hex 13. Its write address is hex 03CO; its read address is hex 03C1. Bit Function 7- 4 3- 0 Reserved Horizontal PEL Panning Figure 87. Horizontal PEL Panning Register, Index Hex 13 Bits 7 - 4 Reserved. Bits 3 - 0 These bits select the number of PELs that the video data is shifted to the left. PEL panning is available in both alphanumeric and graphics modes. The following figure shows the number of bits shifted for each mode. Number 01 PEL. Shifted to the Left Register Value Mode 13 0 0 AlN Mod•• - All Other Mode. 0 2 1 2 3 2 3 4 3 4 2 5 4 5 6 5 6 7 3 6 7 8 7 8 0 * Only mode 7 and the AlN modes with 400 scan lines. 1 Figure 88. Image Shifting Video Subsystem (Type 1) 81 Color Select Register This read/write register is at index hex 14. Its write address is hex 03CO; its read address is hex 03C1. Bit Function 7-4 3 2 Reserved S_color 7 S_color 6 S_color 5 S_color 4 1 0 Figure 89. Color Select Register, Index Hex 14 Bits 7 - 4 Reserved. Bits 3, 2 In modes other than mode hex 13, these are the two most-significant bits of the 8-bit digital color value to the video DAC. In mode hex 13, the 8-bit attribute is the digital color value to the video DAC. These bits are used to rapidly switch between sets of colors in the video DAC. (For more information, refer to "VGA Programming Considerations" on page 83.) Bits 1, 0 These bits can be used in place of the P4 and P5 bits from the Internal Palette registers to form the 8-bit digital color value to the video DAC. Selecting these bits is done in the Attribute Mode Control register (index hex 10). These bits are used to rapidly switch between colors sets within the video DAC. 82 Video Subsystem (Type 1) VGA Programming Considerations The following are some programming considerations for the VGA: • The following rules must be followed to guarantee the critical timings necessary to ensure the proper operation of the CRT controller: The value in the Horizontal Total register must be at least hex 19. The minimum positive pulse width of the 'horizontal synchronization' signal must be four character clock units. The End Horizontal Retrace register must be programmed such that the 'horizontal synchronization' signal goes to a at least one character clock time before the 'horizontal display enable' signal goes active. The End Vertical Blanking register must be set to a minimum of one horizontal scan line greater than the line-compare value. • When PEL panning compatibility is enabled in the Attribute Mode Control register, a successful line compare in the CRT controller forces the output of the Horizontal PEL Panning register to a's until a vertical synchronization occurs. When the vertical synchronization occurs, the output returns to the programmed value. This allows the portion of the screen indicated by the Line Compare register to be operated on by the Horizontal PEL Panning register. • A write to the Character Map Select register becomes valid on the next whole character line. This will prevent deformed character images when changing character generators in the middle of a character scan line. • For mode hex 13, the attribute controller is configured so that the 8-bit attribute in video memory becomes the 8-bit address (POP7) into the video DAC. The user should not modify the contents of the Internal Palette registers when using this mode. Video Subsystem (Type 1) 83 • The following is the sequence for accessing the attribute data registers: 1. Disable interrupts. 2. Reset the flip-flop for the Attribute Address register. 3. Write the index. 4. Access the data register. 5. Enable interrupts. • The Color Select register in the attribute controller section allows the programmer to rapidly switch color sets in the video DAC. Bit 7 of the Attribute Mode Control register controls the number of bits in the Color Select register used to address the color information in the video DAC (either two or four bits are used). By cl"langing the value in the Color Select register, an application can switch color sets in graphics and alphanumeric modes (mode hex 13 does not use this feature). Note: For multiple color sets, the user must load the color values. • An application that saves the video state must store the four bytes of information contained in the system microprocessor latches in the graphics controller subsection. These latches are loaded with 32 bits from video memory (8 bits per map) each time the system reads from video memory. The application needs to: 1. Use write mode 1 to write the values in the latches to a location in video memory that is not part of the display buffer, such as the last location in the address range. 2. Save the values of the latches by reading them back from video memory. Note: If memory addressing is in the chain-4 or odd/even mode, reconfigure the memory as four sequential maps prior to performing the sequence above. BIOS provides support for completely saving and restoring the video state. Refer to the IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference for more information. 84 Video Subsystem (Type 1) • The Horizontal PEL Panning register controls the number of PELs shifted left. Further panning, beyond that shown under the register control, can be accomplished by changing the start-address value in the CRT Controller registers, Start Address High and Start Address Low. The sequence is: 1. Use the Horizontal PEL Panni ng register to shift the maximum number of bits to the left. 2. Increment the start address. 3. Set the Horizontal PEL Panning register so that no bits are shifted. The screen will now be shifted one PEL to the left of the position it was in at the end of Step 1. Step 1 through Step 3 are repeated as often as necessary. • When using a split-screen application that scrolls a second screen on top of the first screen and operating in a mode with 200 scan lines, the Line Compare register (CRT Controller register hex 19) must contain an even value. This is a requirement of the double scanning logic in the CRT controller. • If the value in the Cursor Start register (CRT Controller register hex OA) is greater than that in the Cursor End register (CRT Controller register hex OB), the cursor is not displayed. • In 8-dot character modes, the underline attribute produces a solid line across adjacent characters. In 9-dot character modes, the underline across adjacent characters is dashed. In 9-dot modes with the line-graphics characters (CO - OF character codes), the underline is solid. Video Subsystem (Type 1) 85 Programming the Registers Each of the video components has an address register and a number of data registers. The data registers have addresses common to all registers for that component. The individual registers are selected by a pointer (index) in its Address register. To write to a data register, the Address register is loaded with the index of the desired data register, then the data register is loaded by writing to the common 1/0 address. The general registers do not share a common address; they each have their own 1/0 address. See "Video DAC to System Interface" on page 91 for details on programming the video DAC. For compatibility with the IBM Enhanced Graphics Adapter (EGA), the internal video subsystem palette is programmed the same as the EGA. Using BIOS to program the palette will produce a color compatible to that produced by the EGA. Mode hex 13 (256 colors) is programmed so that the first 16 locations in the DAC produce compatible colors. When BIOS is used to load the color palette for a color mode and a monochrome display is attached, the color palette is changed. The colors are summed to produce shades of gray that allow color applications to produce a readable screen. Modifying the following bits must be done while the sequencer is held in a synchronous reset through its Reset register. The bits are: • Bits 3 and a of the Clocking Mode register. • Bits 3 and 2 of the Miscellaneous Output register. 86 Video Subsystem (Type 1) RAM Loadable Character Generator The character generator is RAM loadable and can support characters up to 32 scan lines high. Three character fonts are stored in BIOS, and one is automatically loaded when an alphanumeric mode is selected. The Character Map Select register can be programmed to redefine the function of bit 3 of the attribute byte to be a character-font switch. This allows the user to select between any two character sets residing in map 2, and effectively gives the user access to 512 characters instead of 256. Character fonts can be loaded offline, and up to eight fonts can be loaded at anyone time. The structure of the character fonts is described in the following figure. The character generator is in map 2 and must be protected using the map mask function. Map 2 I I I I I I I I I I I I I I I I I I I I I + OKB + BKB I I I I I I I +16KB I I I +32KB I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Font 0 I I I I IJJLII I I I I I I LllliLL I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I JJ I I I I I I I I I I I I I I I I I I I II I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I +48KB I I I I Font 4 Font Font 5 Font 2 Font 6 Font 3 I JJJ L I Font 7 +64KB Figure 90. Character Table Structure Video Subsystem (Type 1) 87 The following figure illustrates the structure of each character pattern. If the CRT controller is programmed to generate 16 row scans, then 16 bytes must be filled in for each character in the font. The example below assumes eight row scans per character. Address Data Byte Image CC*32+0 X x X X X 18H 3EH X 2 X X X X 66H 3 X X X X 66H 4 X X X X 7EH 5 X X X X 66H 6 X X X X 66H 7 X X X X 66H X X Figure 91. Character Pattern Example CC equals the value of the character code. For example, hex 41 equals an ASCII A." II Creating a Split Screen The VGA hardware supports a split screen. The top portion of the screen is designated as screen A, and the bottom portion is designated as screen B, as in the following figure. Screen A Screen B Figure 92. Split Screen Definition The following figure shows the screen mapping for a system containing a 32KB alphanumeric storage buffer, such as the VGA. 88 Video Subsystem (Type 1) Information displayed on screen A is defined by the Start Address High and Low registers of the CRT controller. Information displayed on screen B always begins at video address hex 0000. OOOOH Screen B Buffer Storage Area OFFFH 1000H Screen A Buffer Storage Area 7FFFH Figure 93. Screen Mapping within the Display Buffer Address Space The Line Compare register of the CRT controller performs the split screen function. The CRT controller has an internal horizontal scan line counter and logic that compares the counter value to the value in the Line Compare register and clears the memory address generator when a comparison occurs. The linear address generator then sequentially addresses the display buffer starting at location O. Each subsequent row address is determined by the 16-bit addition of the start-of-line latch and the Offset register. Screen B can be smoothly scrolled onto the display by updating the Line Compare register in synchronization with the 'vertical retrace' signal. Screen B information is not affected by scrolling operations that use the Start Address registers to scroll through the screen A information. When PEL-panning compatibility is enabled (Attribute Mode Control register), a successful line comparison forces the output of the Horizontal PEL Panning register to O's until vertical synchronization occurs. This feature allows the information on screen B to remain unaffected by PEL-panning operations on screen A. Video Subsystem (Type 1) 89 Video Digital-to-Analog Converter The video digital-to-analog converter (DAC) integrates the function of a color palette with three internal DACs for driving an analog display. The DAC has 256 registers containing 18 bits each to allow the display of up to 256 colors from a possible 256K colors. Each output signal is driven by a 6-bit DAC. Register Name RIW Address (In Hex) Palette Address (Write Mode) Palette Address (Read Mode) DAC State Palette Data PEL Mask R/W W R R/W R 03C8 03C7 03C7 03C9 03C6 Figure 94. Video DAC Register Device Operation The palette address (P7 - PO) and the blanking input are sampled on the rising edge of the PEL clock. After three more PEL clock cycles, the video reflects the state of these inputs. During normal operation the palette address is used as a pointer to one of the 256 data registers in the palette. The value in each data register is converted to an analog signal for each of the three outputs (red, green, blue). The blanking input is used to force the video output to 0 volts. The blanking operation is independent of the palette operation. Each data register is 18 bits wide: 6 bits each for red, green, and blue. The data registers are accessible through the system interface. 90 Video Subsystem (Type 1) Video DAC to System Interface The Palette Address register holds an S-bit value that is used to address a location within the video DAC. The Palette Address register responds to two addresses; the address depends on the type of palette access, Read or Write. Once the address is loaded, successive accesses to the data register automatically increment the address register. For palette Write operations, the address for the Palette Address register is hex 03CS. A write cycle consists of three successive bytes written to the Data register at address hex 03C9. The six least-significant bits of each byte are concatenated to form the 1S-bit palette data. The order is red value first, then green, then blue. For palette Read operations, the address for the Palette Address register is hex 03C7, which is read only. A read cycle consists of three successive bytes read from the Data register at address hex 03C9. The six least-significant bits of each byte contain the corresponding color value. The order is red value first, then green, then blue. If the Palette Address register is written to during a Read or Write cycle, a new cycle is initialized and the unfinished cycle is terminated. The effects of writing to the Data register during a Read cycle or reading from the Data register during a Write cycle are undefined and can change the palette contents. The DAC State register is a read-only register at address hex 03C7. Bits 1 and 0 return the last active operation to the DAC. If the last operation was a Read operation, both bits are set to O. If the last operation was a Write, both bits are set to 1. Reading the Read Palette Address register at hex 03CS or the DAC State register at hex 03C7 does not interfere with read or write cycles. Video Subsystem (Type 1) 91 Programming Considerations • As explained in "Video DAC to System Interface," the effects of writing to the Data register during a read cycle or reading from the Data register during a write cycle are undefined and may change the palette contents. Therefore, the following sequence must be followed to ensure the integrity of the color palette during accesses to it: 1. Write the address to the PEL Address register. 2. Disable Interrupts. 3. Write or read three bytes of data. 4. Go to Step 3, repeat for the desired number of locations. 5. Enable interrupts. Note: The above sequence assumes that any interrupting process will return the DAC in the correct mode (write or read). If this is not the case, the sequence shown below should be followed: 1. Disable interrupts. 2. Write the address to PEL Address register. 3. Write or read three bytes of data. 4. Go to Step 2, repeat for the desired number of locations. 5. Enable interrupts. • The minimum time from one Read or Write command to the DAC to the next Read or Write command i§ 6 dot clocks. Depending on how the dot clock is derived, this time can be up to 480 nanoseconds (dot clock divided by 2). To ensure enough time, assembler language programmers can place a JMP $+2 between successive accesses to the DAC. 92 Video Subsystem (Type 1) • To prevent "snow" on the screen, an application reading data from or writing data to the DAC registers should ensure that the blank input to the DAC is asserted. This can be accomplished either by restricting data transfers to retrace intervals (use Input Status register 1 to determine when retrace is occurring) or by using the Screen Off bit located in the Clocking Mode register in the sequencer. Note: BIOS provides read and write interfaces to the Video DAC. • Do not write to the PEL Mask register (hex 03C6). Palette information can be changed as a result. This register is correctly initialized to hex FF during a mode set. Video Subsystem (Type 1) 93 Auxiliary Video Connector The auxiliary video connector is a 20-pin connector located in-line with one of the channel connectors on the system board. This connector allows video data to be passed to and from an adapter. The video buffers can be turned off, and video output from the adapter can be sent through the video DAC to the display connector. The full channel is available for use by the adapter. Video output can be passed in only one direction at a time. The 'dot clock' signal cannot drive both EXTCLK to the VGA and PCLK to the DAC. The pin assignments and a functional block diagram of the auxiliary video connector and timing diagrams for the display control signals appear on the following pages. 94 Video Subsystem (Type 1) VGA PO P1 P2 P3 P4 - PO B u f f e r Analo9 Outputs P1 P2 Red P3 P4 Green P5 P5 P8 P6 Blue P7 P7 /8 rDCLK EXTCLK To 0 Isplay Video DAC BLANK Ia-~... BD(7~) A(1~) D7-DO A1-AO DACIOW WR DACIOR RD VSYNC f--- PCLK ,Ji BLANK HSYNC f--- I To Display I ,J '---' ~[J= --;=:ll-~ ... Auxiliary Video Connector ~ ~ PO P1 ~ P2 ~ P3 0------ P4 ~ P5 ~ P6 ' - - - P7 ' - - - - BLANK DCLK HSYNC +5V L L VSYNC ESYNC AA EDCLK L.AvA Ground EVIDEO 5 Ground Pins Figure 95. Auxiliary Video Connector Video Subsystem (Type 1) 95 Signal Descriptions The following are signal descriptions for the Auxiliary Video extension of the channel connector. VSYNC: Vertical Synchronization: This signal is the vertical synchronization signal to the display. Also see the ESYNC description. HSYNC: Horizontal Synchronization: This signal is the horizontal synchronization signal to the display. Also see the ESYNC description. BLANK: Blanking Signal: This signal is connected to the BLANK input of the video DAC. When active (0 Vdc), this signal tells the DAC to drive its analog color outputs to 0 Vdc. Also see the ESYNC description. P7· PO: Palette Bits: These eight signals contain video information and comprise the PEL address inputs to the video DAC. See also the EVIDEO description. DCLK: Dot Clock: This signal is the PEL clock used by the DAC to latch the digital video signals, P7 through po. The signals are latched into the DAC on the rising edge of DCLK. This signal is driven through the EXTCLK input to the VGA when DCLK is driven by the adapter. If an adapter is providing the clock, it must also provide the video data to the DAC. Also see the EDCLK description. ESYNC: External Synchronization: This signal is the output-enable signal for the buffer that drives BLANK, VSYNC, and HSYNC. ESYNC is tied to + 5 Vdc through a pull-up resistor. When ESYNC is high, the VGA drives BLANK, VSYNC, andHSYNc. When ESYNC is pulled low, the adapter drives BLANK, VSYNC, andHSYNC. 96 Video Subsystem (Type 1) EVIDEO: External Video: This signal is the output-enable signal for the buffer that drives P7 through po. EVIDEO is tied to + 5 Vdc through a pull-up resistor. When EVIDEO is high, the VGA drives P7 through po. When it is pulled low, the adapter drives P7 through po. EDCLK: External Dot Clock: This signal is the output-enable signal for the buffer that drives DCLK. EDCLK is tied to + 5 Vdc through a pull-up resistor. When EDCLK is high, the VGA is the source of DCLK to the DAC and the adapter. The Miscellaneous Output register (see "System Board 1/0 Controllers") should not select clock source 2 (010 binary) when EDCLK is high. When EDCLK is pulled low, the adapter drives DCLK. If the adapter is driving the clock, it must also provide the video data to the DAC, and the Miscellaneous Output register must select clock source 2 (010 binary). Video Subsystem (Type 1) 97 P 0-7 A iT6~ ~ ~ ~ -BLANK Red Green Blue C / ~T7 -I T8 A B C Symbol Description Mln.(n.) Max.(n.) Tl T2 T3 T4 T5 T6 T7 T8 PEL Clock Period Clock Pulse Width High Clock Pulse Width Low PEL Set-Up Time PEL Hold Time Blank Set-Up Time Blank Hold Time Analog Output Delay 28 7 10,000 10,000 10,000 9 4 4 4 4 3(Tl) + 5 3(Tl) + Figure 96. Auxiliary Video Connector Timing (DAC Signals) 98 Video Subsystem (Type 1) 30 Display Connector The synchronization signals to the display are TTL levels. The video signals are 0 to 0.7 volts. 5 00000 6 10 15 11 Figure 97. Display Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1/0 Output Display Type Monochrome Color 0 0 0 Red Green Blue Reserved Ground Red Ground Green Ground No Pin Mono No Pin No Pin Self Test Dummy Pin Mono Ground Red Green Blue No Pin Self Test Red Ground Green Ground Blue Ground Plug Ground Monitor Sense 0 Monitor Sense 1 Hsync Vsync Reserved No Pin No Pin Ground No Pin Ground Hsync Vsync No Pin Blue Ground No Pin Ground Ground No Pin Hsync Vsync No Pin N/A N/A N/A N/A N/A N/A N/A I 0 0 N/A Figure 98. Display Connector Signals Video Subsystem (Type 1) 99 Signal Timing BIOS sets the video subsystem according to the video mode. All modes use a 70-Hz, vertical retrace except for modes 11 and 12. These two modes use 60 Hz. The video subsystem generates the signal timings required by the displays according to the mode selected. The following timing diagrams represent only the vertical frequencies set by BIOS. Note: The vertical size of the display is encoded using the polarity of the synchronization signals, as shown in the following figure. VSYNC HSYNC Polarity Polarity + + + + Vertical Size Reserved 400 lines 350 lines 480 lines Figure 99. Vertical Size 100 Video Subsystem (Type 1) Video fC V-i~-;o-Ar-ea----"~~ T1 1r---Act-lv-e ~ t:= - Vertical Sync Signal TIme 11 2.765 ms 11.504 ms 0.985 ms 14.268 ms 0.064 ms T5 " T5 T4 ===J Vertical Timing (ms) - 362 Lines, 70 Hz Symbol T2 T3 T4 T3 __ Figure 100. Vertical Timing, 350 Lines Video Subsystem (Type 1) 101 r-T1~ ~ ;('~I~~___A_m_iv_e_v~:_o_A_re_a ~~~1~________ Video __ -T4-~~1 -1I4--C-:-----;-T-5 + Vertical Sync Vertical Timing (ms) - 414 Lines, 70 Hz Symbol Signal Time T2 T3 T4 1.112 ms 13.156 ms 0.159 ms 14.268 ms 0.064 ms T1 T5 Figure 101. Vertical Timing, 400 Lines 102 Video Subsystem (Type 1) Video - Vertical Sync Vertical Timing (ms) - 496 Lines, 60 Hz Symbol Signainma T1 T2 T3 T4 T5 0.922 ms 15.762 ms 0.064 ms 16.683 ms 0.064 ms Figure 102. Vertical Timing, 480 Lines Video Subsystem (Type 1) 103 Video + Horizontal Sync or • Horizontal Sync Horizontal Timing(/ls) - 80 Column. With Border Symbol Signainme T1 T2 T3 5.720 JIS 26.058 /ls 0.318/ls 1.589J1S 3.813 JIS 31.778 JIS 3.813/ls T4 T5 T6 T7 Figure 103. Horizontal Timing, 80 Column with Border 104 Video Subsystem (Type 1) Video rsJ:J= ~T.j" ~ / . Active Video Area 12 ~ ·1 '---- + Horizontal Sync or - Horizontal Sync TI1" Horizontal Timing(Jls) - 40/80 Column, No Border Symbol Signal Time Tl 6.356 Jls T2 T3 T4 T5 T6 17 25.422 Jls 0.636 JlS 1.907 Jls 3.813 Jls 31.778 JlS 3.813 Ils Figure 104. Horizontal Timing, 40/80 Column, without Border Video Subsystem (Type 1) 105 Notes: 106 Video Subsystem (Type 1) Index A B address registers attribute controller 76 palette 90 sequencer 42 address select 74 all points addressable (APA) modes 14 mds.graphics 14 alphanumeric memory mapping 22 alphanumeric modes 11 AND data select 71 asynchronous reset 43 attribute controller 7 blink enable 78 block diagram 7 registers 76 attribute controller registers 76 address 76 color plane enable 80 color select 82 horiz PEL panning 81 internal palette O-F 77 mode control 78 overscan color 80 reserved bits 37 attribute definition 12 auxiliary video connector 94 connector timing 98 signals 96 BIOS 4 BIOS video modes 8 bit mask register 75 blanking signal 96 blink enable 78 block diagram address mapping 65 attribute controller 7 auxiliary video connector graphics controller 6 memory read 36 memory write 35 subsystem 3 border color select 80 buffer address 59 buffer address select 74 95 C chain 4 bit 48 character generator 46, 79 character generator, RAM loadable 87 character map select register 46 clocking mode register 43 color compare operations 36 color compare register 70 color don't care register 75 color graphics modes 640 x 480, 2 color 18 color modes 8 color plane enable register 80 color select register 82 color/graphics modes 14 compare, line 67 compatibility 86 components, subsystem 4 Index 107 connector timing 98 connector, display 99 considerations, programming 83 control cursor 58 control cursor skew 58 controller attribute 7 CRT 5 graphics 5 count by two 64 count by 4 62 creating a split screen 88 CRT controller 5 address mapping 65 horiz skew 52 registers 49 CRT controller compatibility 67 CRT controller registers 49 address 50 cursor location 59 cursor start and end 58 end horiz blanking 51 end horiz retrace 53 end vert blank 63 horizontal end 51 horizontal total 50 line compare 67 max scan line 57 mode control 64 offset 62 overflow 55 preset row scan 56 reserved bits 37 start address 59 start horiz blanking 51 start horiz retrace 53 start vert blank 63 start vert total 54 underline location 62 vert retrace end 60 vert retrace start 60 vertical end 61 CRT mode control register 64 108 Index cursor location register 59 cursor off bit 58 cursor skew 58 cursor start/end register 58 o DAC palette 90 operation 90 programming considerations register 90 state register 91 DAC state register 91 data rotate register 71 DCLK signal 96 description 1 device operation, DAC 90 digital-to-analog converter (DAC) 90 display connector 99 display connector timing 100 display support 10 display synchronization signals 100 display, vertical gain 39 display, vertical size 100 don't care, color 75 double scanning 57 doubleword mode 62 92 E EDCLK signal 97 enable bit, video subsystem 10 enable blink 78 enable line graphics 79 enable register 41 enable set/reset register 69 end horizontal blanking register 51 end horizontal retrace register 53 end vertical blanking register 63 ESYNC signal 96 EVIDEO signal 97 F graphics modes, 16-color 18 graphics modes, 320 x 200, four-color 14 guidelines, programming 83 feature control 41 font, RAM loadable 87 format, video mode F 17 mode 11 18 mode 13 19 mode4,5 14 mode 6 16 16 color modes 18 full-screen updates 44 horizontal display enable end register 51 horizontal PEL panning register horizontal retrace select 64 horizontal skew 52 horizontal total register 50 HSYNC signal 96 G I general description 1 general registers 38 input status 40,41 miscellaneous output 38 reserved bits 37 video enable 41 graphics controller 5 block diagram 6 register 68 graphics controller registers 68 bit mask 75 color compare 70 color don't care 75 data rotate 71 enable set/reset 69 miscellaneous 74 mode 72 read map select 72 reserved bits 37 set/reset 69 graphics mode register 72 graphics mode, 256-color 18 graphics modes 14 graphics modes 640 x 200, 2-color 16 graphics modes 640 x 350 17 image shift 81 input status register 40 interface, system to DAC 91 internal palette select 77 interrupt enable 61 H 81 L line compare register 67 line graphics 79 line graphics character 78 logic, support 4 logical operator select 71 M major components 4 map mask register 45 map select register 46 map select, read 72 mapping, memory 65 mapping, split screen 89 maps, memory 21 maximum scan line register memory address select 74 memory maps 21, 65 memory mode register 48 57 Index 109 memory read/writes 35 methods for programming 86 miscellaneous output register 38 miscellaneous register 74 mode control register (CRT) 64 mode control register, attribute 78 mode hex F, 640 x 350 graphics 17 mode hex 11, 640 x 480 two color graphics 18 mode hex 13, 256-color 18 mode register, graphics 72 mode 16-color graphics 18 mode 6, 640 x 200 two-color 16 modes alphanumeric 11 BIOS 8 count by two 64 count by 4 62 doubleword 62 memory maps 20 odd/even 73 read and write 73 word/byte 64 512 char font 87 modes 4 and 5, 320 x 200 four-color 14 modes, new 1 monochrome modes 8 N new modes o odd/even address bit 48 odd/even mode 73 offset register 62 OR data select 71 organization, video memory overflow register, CRT controller 55 overscan color register 80 110 Index 20,21 p palette address select 77 palette operation 90 palette registers 77 palette, DAC 90 PEL panning 81 polarity, sync·· 38 POS information 10 preset row scan register 56 programming considerations 83 programming registers 86 protect registers 61 P4,P5 select 78 P7 - PO signal 96 R RAM loadable character generator 87 read map select register 72 read modes 73 read/writes, memory 35 refresh select 61 regen buffer address 59 registers 37 attribute controller 76 CRT controller 49 DAC 90 feature control 41 general 38 input status 40 miscellaneous output 38 programming 86 reserved bits 37 video enable 41 write protect 61 reset bit 64 reset register 43 retrace polarity 38 ROM BIOS 4 rotate data 71 row scan counter 64 S T scanning, double 57 screen off bit 44 select address 74 select horizontal retrace 64 select operator 71 select P4,P5 78 select row scan 64 sequencer 5 registers 42 sequencer registers 42 address 42 clocking mode 43 map mask 45 map select 46 memory mode 48 reserved bits 37 reset 43 set/reset register 69 setting modes 8 setup mode 10 shift image 81 signal, auxiliary video 96 skew control, cursor 58 skew control, horizontal 52 source select 77 specifications, display 10 split screen, creating 88 start address high register 59 start address low register 59 start address register 59 start horizontal blanking register 51 start horizontal retrace pulse register 53 start vertical blanking register 63 support logic 4 support, display 10 sync polarity 39,100 synchronization signals 100 synchronous reset 43 system interface, DAC to 91 timing, display 100 timing, video 98 U underline location register updates, full-screen 44 62 V vertical display enable end register 61 vertical gain 39 vertical interrupt 60 vertical retrace end register 60 vertical retrace interrupt 61 vertical retrace start register 60 vertical size 100 vertical total register 54 VGA programming considerations 83 video connector 95, 99 video DAC programming considerations 92 video enable bit 10 video graphics array 1, 5 video modes 8 video registers 86 video subsystem enable register 41 VSYNC signal 96 W word/byte mode 64 write modes 73 write operations 35 Index 111 Numerics 16 background colors 78 512 character fonts 87 112 Index Keyboards (101- and 102-Key) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Keyboard Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 101-Key Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 102-Key Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Belgian Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Canadian French Keyboard . . . . . . . . . . . . . . . . . . . . . . . . 5 Danish Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Dutch Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 French Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 German Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Italian Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latin American Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . 11 Norwegian Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Portuguese Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Spanish Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Swedish Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Swiss Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 U.K. English Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 U.S. English Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sequential Key-Code Scanning . . . . . . . . . . . . . . . . . . . . . . . 19 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-On Routine .... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 Power-On Reset (PaR) .. . . . . . . . . . . . . . . . . . . . . . . . .. 20 Basic Assurance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Commands from the System . . . . . . . . . . . . . . . . . . . . . . . . . 21 Commands to the System . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Scan Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Set 1 Scan-Code Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Set 2 Scan-Code Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Set 3 Scan Code Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Encode and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Extended Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Shift States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Special Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Keyboards (101- and 102-Key) System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Print Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Characteristics ..... . . . . . . . . . . . . . . . . . . . . . .. Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 48 48 49 49 50 51 Index 52 II ........................................ Keyboards (101- and 102-Key) Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. Keyboard Commands from the System .............. Set All Keys Commands . . . . . . . . . . . . . . . . . . . . . . . . Set Key Type Commands . . . . . . . . . . . . . . . . . . . . . . . Set/Reset Status Indicators .. . . . . . . . . . . . . . . . . . . .. Typematic Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Commands to the System ...... . . . . . . . . .. Keyboard Scan Codes, Set 1 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 1 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 1 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 1 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 1 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 2 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 2 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 2 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 2 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 2 . . . . . . . . . . . . . . . . . . . . . Keyboard Scan Codes, Set 3 . . . . . . . . . . . . . . . . . . . . . Keyboard Data Stream Bit Definitions .............. Character Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Character Codes . . . . . . . . . . . . . . . . . . . . . . . Keyboard Extended Functions . . . . . . . . . . . . . . . . . . . . Keyboard Connectors Signal and Voltage Assignments ... 21 23 24 24 26 27 29 30 31 31 31 32 33 33 34 34 35 39 42 44 45 50 Keyboards (101- and 102-Key) III Notes: Iv Keyboards (101- and 102-Key) Description The keyboard has 102 keys (101 in the U.S.). At system power-on, the keyboard monitors the signals on the 'clock' and 'data' lines and establishes its line protocol. A bidirectional serial interface in the keyboard converts the 'clock' and 'data' signals and sends this information to and from the keyboard through the keyboard cable. Keyboard Layouts Keyboard layouts are in alphabetic order on the following pages. Nomenclature is on both the top and front face of the keybuttons. • • • • • • • • • • • • • • • Belgian Canadian French Danish Dutch French German Italian Latin American Norwegian Portuguese Spanish Swedish Swiss U.K. English U.S. English. Keyboard Layouts (101-and 102-Key) 1 .... ....• o " ~ co ~ '< I» a ;IIIl:; CD ~ o c: ~--------------------------~g r Cil' ...... ..... o..... I I» :::J a. ..... o N I " (I) $ '< a8BaS 8888 8888 888 a 8G8G8mGmm8G88QD B88 8888 E]E]BB8B88B88B8~ EDB8BB88B88BB~ ~8E]888BBBE]8~ ~ GJ 8B8 B888 888 8888 G 08 06 57 G~ 61 ~G '-------' ..... ~ f ~ ~----------------------------------~~ o (8) 8888 8B88 8888 888. w It a. •iiat ii :::II i o I) a. Insert Han! PIg- Ib ~ Lade / Delete := 7 .,.8 End tbIe 4 .. 5 1 2 ErII + * 9 .PIIIP . 6 3 1'111), 0 Ins + Del Enter n II :::s I i" . :::s '"II CD :::s n :::r ~ '< Inslr " CD '< c:r 0 I» Cl. ... r ~ Ent.... ~ SUppr ~ Fin t ~ !Un 7 II. 5 1 • fit 0 0 ...... I I» :::J Cl. ...... 0 I\) I !" en 'I' 4 Fin c:: 8 .. 0 ...... ...... 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It .,.8 4 5 7 / +- 1 Fin. 2 • * 9 pag+ . 6 + 3 pag. ImlD 0 Ins - cane " ~ tT 0 I» ... Q. r~ 0 c fit .... 0 .... ~ I I» :::J Q. .... 0 I\) I " CD ~ .... .... ~ Bloq May.. * .-J Insert InltlD ~ S\Jpr PII!I Fin A~ BIDq ton I 7 .,.8 4 .. 5 1 2 InltlD Fin ... * 9 Rl!Pig .. 6 + 3 AvPig IntrD 0 Ins - S\Jpr z o j i' ~ £go El Insert - Delete End •a Page ~ lUI Lock PIgI! IIIMI Han! 7 / .,.8 4 .. 5 1 2 End 0 Ins * - 9 Pg~ .. 6 + 3 PgIl1 '" . Del Enter I I "r::r CD '< 0 I» ...C. r~ 0 c \ ~ taps Lade ~ ur ..... 0 .....I I» :::I C. ..... 0 I\) I " ~ ... W Orl .-J Insert IbIe Plge l.\> IiIn Lack I Delete End Page bn 7 Ibne .,.8 4 5 ..6 2 3 • 1 End ... * 9 PIll.\> + PIlI)! Enter 0 Ins - Del ~ Insert Inlclo Q \ ~ .-J '~r Fin AI! IIaq Pig lUI Aw Pig Inlel 7 I 8 9 '1' ' AI! MllJu. 4 .. 5 6 ... -<>. 1 2 3 Iloq Fin • - * Aw Pili Pili 0 Ins ,~r + Intra I'z "cr CD '< 0 III Co ... ,... ~ S ~ ClIps Lock 0 .0 ..... 0 .....I Ctrl c: fit ~ III ::J Co ..... 0 I\) I " CD ~ .. en Enter .-J Insert Han! lII!lete End Page l.Il Page !bon lUll LDck .... 7 Han! .,.8 9 LPg l.Il. 4 5 6 2 3 +- 1 End )( + -+ ... Pgl)o a , Ins "lII!l Enter 0 Insert IbIe g ~ ~ ¢. Ctrl +-1 Dol_t_ End PIIg~ !'age lUI LD[k I Ibne 7 .,.8 ... 4 5 1 2 "- End * 9 LPg ~ . 6 + 3 PgDn 0 Ins - Dol Ent_r c: ~ m ~ ce.;" :::r J . o Dt Do " CD '< go . 0 I» -: ~ C. Ups Lotlc 0 <> r~ c: fit ...... ... " ~ C I I» ::J C. C I\) I CD ~ ...• Ctrl t-l Insert IDle Delete End Page ~ lUI Lotlc Page IDn 1m! 7 I * - B 9 4 + 5 1 2 3 '" Pgl)! .- EIII 0 Ins Pg~ .. 6 + Enter Del .... 011 m ~ -::::r fa iii' f a" ....... ..... o..... I o I» I» :::J Q. ..... Insert o N I " ~ Del.te End a. Page ~ ttJn Lock / Pago Ibm 7 8 9 Ibno .-4 '" Pg~ 5 1 ... End 0 Ins 2 * .. 6 + 3 PgDn Enter Del Sequential Key-Code Scanning The keyboard detects all keys pressed and sends each scan code in the correct sequence. When not being serviced by the system, the keyboard stores the scan codes in its buffer. Buffer A 16-byte first-in-first-out (FIFO) buffer in the keyboard stores the scan codes until the system is ready to receive them. A buffer-overrun condition occurs when more than 16 bytes are placed in the keyboard buffer. An overrun code replaces the 17th byte. If more keys are pressed before the system allows keyboard output, the additional data is lost. When the keyboard is allowed to send data, the bytes in the buffer are sent as in normal operation, and new data entered is detected and sent. Response codes do not occupy a buffer position. If keystrokes generate a multiple-byte sequence, the entire sequence must fit into the available buffer space, or the keystroke is discarded and a buffer-overrun condition occurs. Keys Except for the Pause key, all keys are make/break. The make scan code of a key is sent to the keyboard controller when the key is pressed. When the key is released, its break scan code is sent. Also, except for the Pause key, all keys are typematic. When a key is pressed and held down, the keyboard sends the make code for that key, delays 500 milliseconds ±20%, and begins sending a make code for that key at a rate of 10.9 characters per second ±20%. The typematic rate and delay can be modified (see "Set Typematic Rate/Delay (Hex F3)" on page 25). If two or more keys are held down, only the last key pressed repeats at the typematic rate. Typematic operation stops when the last key pressed is released, even if other keys are still held down. If a key is pressed and held down while keyboard transmission is inhibited, only Keyboards (101- and 102-Key). Sequential Key-Code Scanning 19 the first make code is stored in the buffer. This prevents buffer overflow because of typematic action. Note: Scan-code set 3 allows key types to be changed by the system. See "Set 3 Scan Code Tables" on page 35 for the default settings. Power-On Routine The following activities take place when power is first applied to the keyboard: Power-On Reset (POR) The keyboard logic generates a 'power-on reset' signal (POR) when power is first applied to the keyboard. POR takes a minimum of 150 milliseconds and a maximum of 2.0 seconds from the time power is first applied to the keyboard. Basic Assurance Test The basic assurance test (BAT) consists of a keyboard processor test, a checksum of the read-only memory (ROM), and a random-access memory (RAM) test. During the BAT, activity on the 'clock' and 'data' lines is ignored. The LEOs are turned on at the beginning and off at the end of the BAT. The BAT takes a minimum of 300 milliseconds and a maximum of 500 milliseconds. This is in addition to the time required by the POR. On satisfactory completion of the BAT, a completion code (hex AA) is sent to the system, and keyboard scanning begins. If a BAT failure occurs, the keyboard sends an error code to the system. The keyboard is then disabled pending command input. Completion codes are sent between 450 milliseconds and 2.5 seconds after POR, and between 300 and 500 milliseconds after a Reset command is acknowledged. Immediately following POR, the keyboard monitors the signals on the keyboard 'clock' and 'data' lines and sets the line protocol. 20 Keyboards (101- and 102-Key), Power-On Routine Commands from the System The following figure shows the commands that the system may send and their hexadecimal values. Command Hex Value Set/Reset Status Indicators Echo Invalid Command Select Alternate Scan Codes Invalid Command Read 10 Set Typematic Rate/Delay Enable Default Disable Set Default Set All Keys - Typematic - Make/Break - Make - Typematic/Make/Break Set Key Type - Typematic - Make/Break - Make Resend Reset ED EE EF FO F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Figure 1. Keyboard Commands from the System These commands can be sent to the keyboard at any time. The keyboard responds within 20 milliseconds, except when performing the BAT, or executing a Reset command. Note: Mode 1 accepts only the Reset command. The following commands are in alphabetic order. They have different meanings when issued by the keyboard (see "Commands to the System" on page 27). Default Disable (Hex FS): The Default Disable command resets all conditions to the power-on default state. The keyboard responds with ACK, clears its output buffer, sets the default key types (scan-code set 3 operation only) and typematic rate/delay, and clears the last typematic key. The keyboard stops scanning and awaits further instructions. Keyboards (101- and 102-Key), Commands 21 Echo (Hex EE): Echo is a diagnostic aid. When the keyboard receives this command, it issues a hex EE response if previously enabled, it continues scanning. Enable (Hex F4): On receipt of this command, the keyboard responds with ACK, clears its output buffer, clears the last typematic key, and starts scanning. Invalid Command (Hex EF and F1): Hex EF and hex F1 are invalid commands and are not supported. If one of these is sent, the keyboard does not acknowledge the command but returns a Resend command and continues in its prior scanning state. No other activities occur. Read ID (Hex F2): This command requests identification information from the keyboard. The keyboard responds with ACK, stops scanning, and sends the two keyboard 10 bytes. The second byte must follow completion of the first by no more than 500 microseconds. After the output of the second 10 byte, the keyboard resumes scanning. Resend (Hex FE): The system sends this command when it detects an error in any transmission from the keyboard. It is sent only after a keyboard transmission and before the system allows the next keyboard output. When a Resend command is received, the keyboard sends the previous output again (unless the previous output was Resend command, in which case the keyboard sends the last byte before the Resend command). Reset (Hex FF): The system issues a Reset command to start a program reset and a keyboard internal self-test. The keyboard acknowledges the command with an ACK and ensures the system accepts ACK before executing the command. The system Signals acceptance of ACK by raising the 'clock' and 'data' lines for a minimum of 500 microseconds. The keyboard is disabled from the time it receives the Reset command until ACK is accepted, or until another command is sent that overrides the previous command. Following acceptance of ACK, the keyboard is reinitialized and performs the BAT. After returning the completion code, the keyboard defaults to scan-code set 2. 22 Keyboards (101- and 102-Key), Commands Select Alternate Scan Codes (Hex FO): This command instructs the keyboard to select one of three sets of scan codes. The keyboard acknowledges receipt of this command with ACK and clears both the output buffer and the typematic key (if one is active). The system then sends the option byte and the keyboard responds with another ACK. An option byte value of hex 01 selects scan code set 1, hex 02 selects scan code set 2, and hex 03 selects scan code set 3. An option byte value of hex 00 causes the keyboard to acknowledge with an ACK and send a byte telling the system which scan code set is currently in use. To prevent the controller from translating this byte, disable the keyboard controller translate mode. After establishing the new scan code set, the keyboard returns to the scanning state it was in before receiving the Select Alternate Scan Codes command. Set All Keys (Hex F7, F8, F9, FA) These commands instruct the keyboard to set all keys to a condition listed in the following figure. Hex Value F7 Fa F9 FA Command Set All Set All Set All Set All Keys - Typematic Keys - Make/Break Keys - Make Keys-Typematic/Make/Break Figure 2. Set All Keys Commands The keyboard responds with ACK, clears its output buffer, sets all keys to the condition indicated by the command, and continues scanning (if it was previously enabled). Although these commands can be sent using any scan-code set, they affect only the operation of scan-code set 3. Set Default (Hex F6): The Set Default command resets all conditions to the power-on default state. The keyboard responds with ACK, clears its output buffer, sets the default key types (scan-code set 3 operation only) and typematic rateldelay, clears the last typematic key, and continues scanning. Keyboards (101- and 102-Key), Commands 23 Set Key Type (Hex FB, Fe, FD): These commands instruct the keyboard to set individual keys toa condition listed in the following figure. Hex Value FB FC FD Command Set Key Type - Typematic Set Key Type - Make/Break Set Key Type - Make Figure 3. Set Key Type Commands The keyboard responds with ACK, clears its output buffer, and prepares to receive key identification. The system identifies each key by its scan-code value, as defined in scan-code set 3. Only scan code set 3 values are valid for key identification. The type of each identified key is set to the value indicated by the command. These commands can be sent using any scan code set, but affect only the operation of scan code set 3. SetlReset Status Indicators (Hex ED): Three status indicators on the keyboard-Num Lock, Caps Lock, and Scroll Lock-are accessible by the system. The keyboard activates or deactivates these indicators when it receives a valid command-code sequence from the system. The command sequence begins with the command byte (hex ED). The keyboard responds with ACK, stops scanning, and waits for the option byte from the system. The bit assignments for this option byte are as follows. Bit Function 7- 3 2 1 Reserved (must be D's) Caps Lock Indicator Num Lock Indicator Scroll Lock Indicator o Figure 4. SetlReset Status Indicators If a bit for an indicator is set to 1, the indicator is turned on. If a bit is set to 0, the indicator is turned off. The keyboard responds to the option byte with ACK, sets the indicators and, if the keyboard was previously enabled, continues scanning. The state of the indicators reflect the bits in the option byte 24 Keyboards (101- and 102-Key), Commands and can be activated or deactivated in any combination. If another command is received in place of the option byte, execution of the Set/Reset Mode Indicators command is stopped, with no change to the indicator states, and the new command is processed. Immediately after power-on, the lights default to the Off state. If the Set Default and Default Disable commands are received, the lamps remain in the state they were in before the command was received. Set Typematlc Rate/Delay (Hex F3): The system issues the Set Typematic Rate/Delay command to change the typematic rate and delay. The keyboard responds to the command with ACK, stops scanning, and waits for the system to issue the rate/delay value byte. The keyboard responds to the rate/delay value byte with another ACK, sets the rate and delay to the values indicated, and continues scanning (if it was previously enabled). Bits 6 and 5 indicate the delay, and bits 4, 3, 2, 1, and 0 (the least-significant bit) the rate. Bit 7, the most-significant bit, is always O. The delay is equal to 1 plus the binary value of bits 6 and 5, multiplied by 250 milliseconds ±20%. The period (interval from one typematic output to the next) is determined by the following equation: Period = (8 + A) x (2B) x 0.00417 seconds ±20%. where: A = binary value of bits 2, 1, and O. B = binary value of bits 4 and 3. Keyboards (101- and 102-Key), Commands 25 The typematic rate (make codes per second) is 1 for each period. Bit 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Typematlc 20% Rate ± Bit 30.0 26.7 24.0 21.8 20.0 18.5 17.1 16.0 15.0 13.3 12.0 10.9 10.0 9.2 8.6 8.0 Typematlc 20% Rate 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 ± 7.5 6.7 6.0 5.5 5.0 4.6 4.3 4.0 3.7 3.3 3.0 2.7 2.5 2.3 2.1 2.0 Figure 5. Typematic Rate The default values for the system keyboard are as follows: Typematic rate = 10.9 characters per second Delay = 500 milliseconds ± 20%. ± 20%. The execution of this command stops without change to the existing rate if another command is received instead of the rate/delay value byte. 26 Keyboards (101- and 102-Key). Commands Commands to the System The following figure shows the commands that the keyboard may send to the system, and their hexadecimal values. Command Hex Value Key Detection Error/Overrun Keyboard ID BAT Completion Code BAT Failure Code Echo Acknowledge (ACK) Resend Key Detection Error/Overrun 00 (Code Sets 2 and 3) 83AB AA FC EE FA FE FF (Code Set 1) Figure 6. Keyboard Commands to the System The commands the keyboard sends to the system are described in alphabetic order. They have different meanings when issued by the system. Acknowledge (Hex FA): The keyboard issues ACK to any valid input other than an Echo, or Resend command. If the keyboard is interrupted while sending ACK, it discards ACK and accepts and responds to the new command. BAT Completion Code (Hex AA): Following satisfactory completion of the BAT, the keyboard sends hex AA. Any other code indicates a failure of the keyboard. BAT Failure Code (Hex FC): If a BAT failure occurs, the keyboard sends this code, stops scanning, and waits for a system response or reset. Echo (Hex EE): The keyboard sends this code in response to an Echo command. Keyboard ID (Hex 83AB): The Keyboard 10 consists of 2 bytes, hex 83AB. The keyboard responds to the Read 10 command with ACK, stops scanning, and sends the 210 bytes. The low byte is sent first followed by the high byte. Following the output of the Keyboard 10, the keyboard begins scanning. Because of keyboard controller Keyboards (101- and 102-Key), Commands 27 translation, the keyboard 10 may not be returned to the system as hex B3AS. Key DetectIon Error (Hex 00 or FF): The keyboard sends a key detection error character if conditions in the keyboard make it impossible to identify a switch closure. If the keyboard is using scan-code set 1, the code is hex FF. For sets 2 and 3, the code is hex 00. Overrun (Hex 00 or FF): An overrun character is placed in the keyboard buffer and replaces the last code when the buffer capacity has been exceeded. The code is sent to the system when it reaches the top of the buffer queue. If the keyboard is using scan code set 1, the code is hex FF. For sets 2 and 3, the code is hex 00. Resend (Hex FE): The keyboard issues a Resend command following receipt of an invalid input, or any input with incorrect parity. If the system sends nothing to the keyboard, no response is required. Scan Codes The following figures list the key numbers of the three scan code sets and their hexadecimal values. The system defaults to scan set 2, but can be switched to set 1 or set 3 (see "Select Alternate Scan Codes (Hex FO)" on page 23). Set 1 Scan-Code Tables In scan-code set 1, each key is assigned a base scan code and, sometimes extra codes to generate artificial shift states in the system. The typematic scan codes are identical to the base scan code for each key. The following figure shows the codes sent for the keys, regardless of any shift states in the keyboard or system. Refer to "Keyboard Layouts" beginning on page 1 to determine the character associated with each key number. 28 Keyboards (101- and 102-Key), Scan Codes Key Number Make Code Break Code 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A9 82 47 83 49 50 51 52 29' 30 31 32 33 34 35 36 37 38 39 40 41 42 " 43 44 45 " 46 29 02 03 04 05 06 07 08 09 OA OB OC 00 OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 2B 3A 1E 1F 20 21 22 23 24 25 26 27 28 2B 1C 2A 56 2C , 101-key keyboard only, Key Number Make Code 84 85 86 87 48 53 20 2E 2F 30 31 32 33 88 54 34 89 8A 8B 8C 80 8E 8F 90 91 92 93 55 57 35 36 10 38 39 EO 38 EO 10 45 47 4B 4F 58 60 61 62 64 90 91 92 93 94 96 97 95 96 98 99 97 100 98 101 99 9A 102 103 9B 104 AB 105 BA 106 9E 108 9F 110 AO 112 A1 113 A2 114 A3 115 A4 116 A5 A6 117 118 A7 119 A8 AB 120 121 9C AA 122 123 06 125 AC " 102-key keyboard only. 48 4C 50 52 37 49 40 51 53 4A 4E EO 1C 01 3B 3C 3D 3E 3F 40 41 42 43 44 57 58 46 Break Code AD AE AF BO B1 B2 B3 B4 B5 B6 90 B8 B9 EOB8 E090 C5 C7 CB CF C8 CC DO 02 B7 C9 CO 01 03 CA CE E09C 81 BB BC BO BE BF CO C1 C2 C3 C4 07 08 C6 Figure 7. Keyboard Scan Codes, Set 1 Keyboards (101- and 102-Key), Scan Codes 29 The remaining keys send a series of codes that are dependent on the state of the various shift keys (Ctrl, Alt, and Shift), and the state of Num Lock (On or Off). Because the base scan code is identical to another key, an extra code (hex EO) has been added to the base code to make it unique. Key No. 75 76 79 80 81 83 84 85 86 89 Ba.e ea.e, or Shift + Num Lock MakefBreak Shift Ca.e MakefBreak • Num Lock on MakefBreak EO 52 EOAAE052 E02A EO 52 lEO D2 lEO D2 EO 2A lEO D2 EOAA EO 53 EOAA EO 53 E02A EO 53 lEO D3 lEO D3 EO 2A lEO D3 EOAA EOAA E04B E02A E04B IEOCB EOAA EO 2A EO 47 IEOC7EOAA E02A E04F lEO CF EO AA EO 2A EO 48 lEO C8 EOAA EO 2A EO 50 lEO DO EOAA EO 2A EO 49 IEOC9 EOAA EO 2A EO 51 lEO D1 EO AA E02A E04D lEO CD EOAA E04B IEOCB EO 47 IEOC7 E04F IEOCF EO 48 IEOC8 EO 50 lEO DO EO 49 IEOC9 EO 51 lEO 01 E04D lEO CD lEO CB E02A EOAA EO 47 lEO C7 EO 2A EOAA E04F lEO CF EO 2A EOAA EO 48 lEO C8 E02A EOAA EO 50 lEO DO E02A EOAA EO 49 lEO C9 EO 2A EOAA EO 51 lEO D1 EO 2A EOAA E04D lEO CD E02A • If the left Shift key is held down, the AAl2A shift make and break are sent with the other scan codes. If the right Shift key is held down, B6/36 is sent. If both Shift keys are down, both sets of codes are sent with the other scan code. Figure 8. Keyboard Scan Codes, Set 1 30 Keyboards (101- and 102-Key), Scan Codes Key No. Scan Code MakefBreak Shift Ca.e MakefBreak • 95 EO 35/EO B5 EO AA EO 35/EO B5 EO 2A • If the left Shift key is held down, the AAl2A shift make and break are sent with the other scan codes. If the right Shift key is held down, B6/36 is sent. If both Shift keys are down, both sets of codes are sent with the other scan code. Figure 9. Keyboard Scan Codes, Set 1 Key No. 124 Scan Code MakefBreak Ctrl Ca.e, Shift ea.e MakefBreak EO 2A EO 37 EO 37/EO B7 , AICa.e MakefBreak 54104 lEO B7 EOAA Figure 10. Keyboard Scan Codes, Set 1 Key No. 126· Ctr. Key Prened Make Code E1 10 45 E1 90 C5 E046E0C6 • This key is not typematic. All associated scan codes occur on the make of the key. Figure 11. Keyboard Scan Codes, Set 1 Set 2 Scan-Code Tables In scan-code set 2, each key is assigned a unique a-bit make scan code, which is sent when the key is pressed. Each key also sends a break code when the key is released. The break code consists of 2 bytes, the first of which is the break code prefix, hex FO; the second byte is the same as the make SCan code for that key. The typematic scan code for a key is the same as the key's make code. The following figure shows the codes sent for the keys, regardless of any shift states in the keyboard or system. Refer to "Keyboard Layouts" beginning on page 1 to determine the character associated with each key number. Keyboards (101- and 102-Key) , Scan Codes 31 Key Number Make Code 1 OE 2 16 lE 3 4 26 5 25 6 2E 7 36 8 3D 3E 9 10 46 11 45 12 4E 13 55 15 66 16 00 17 15 18 10 19 24 20 20 21 2C 22 35 23 3C 24 43 25 44 26 40 27 54 28 5B 29· 50 30 58 31 32 33 34 lC lB 23 2B 35 34 36 37 33 3B 42 4B 4C 52 50 5A 12 61 lA 38 39 40 41 42 •• 43 44 45 •• 46 • 101-key keyboard only, Break Code FOOE FO 16 FO lE F026 F025 F02E F036 F030 F03E F046 F045 F04E F055 F066 FOOD FO 15 FO 10 F024 F020 F02C F035 F03C F043 F044 F040 F054 F05B F050 F058 FO lC FO lB F023 F02B F034 F033 F03B F042 F04B F04C F052 F050 F05A FO 12 F061 FO lA Key Number Make Code 47 22 21 46 2A 49 50 32 51 31 52 3A 53 41 54 49 4A 55 57 59 58 14 11 80 61 29 62 EO 11 EO 14 64 90 n 91 92 6C 6B 93 96 69 97 98 99 100 101 102 103 104 105 106 108 110 112 113 114 115 116 117 118 119 120 121 122 123 125 •• 102-key keyboard only. Figure 12. Keyboard Scan Codes, Set 2 32 Keyboards (101- and 102~Key), Scan Codes 75 73 72 70 7C 70 74 7A 71 7B 79 E05A 76 05 06 04 OC 03 OB 83 OA 01 09 78 07 7E Break Code F022 F021 F02A F032 F031 F03A F041 F049 F04A F059 FO 14 FO 11 F029 EO FO 11 EO FO 14 FOn F06C F06B F089 F075 F073 F072 F070 F07C F070 F074 F07A F071 F07B F079 EO F05A F076 F005 F006 FOO4 FOOC F003 FOOB FOSS FOOA FOOl FOO9 F078 F007 F07E The remaining keys send a series of codes that are dependent on the state of the shift keys (Ctrl, Alt, and Shift), and the state of Num Lock (On or Off). Because the base scan code is identical to another key, an extra code (hex EO) is added to the base code to make it unique. Key No. 75 Ba.e Ca.e, or Shift + Num Lock MakefBreak EO 70 lEO F070 76 80 EO 68 EO FO 12 EO 68 lEO FO 68 EO 12 E06C EO FO 12 EO 70 lEO FO 70 EO 12 E07A lEO FO 7A 89 EO FO 12 EO 72 lEO FO 72 EO 12 EO 70 lEO FO 7D 86 EO FO 12 EO 75 lEO FO 75 EO 12 EO 72 lEO FO 72 85 EO FO 12 EO 69 lEO FO 69 EO 12 EO 75 lEO F075 84 EO FO 12 E06C lEO FO 6C EO 12 EO 69 lEO FO 69 83 EO FO 12 EO 71 lEO FO 71 EO 12 lEO FO 68 lEO F06C 81 EO FO 12 EO 70 lEO FO 70 EO 12 E071 lEO FO 71 79 Shift Ca.e MakefBreak * EOFO 12 E07A lEO FO 7A EO 12 EO FO 12 EO 74 EO 74 lEO F074 lEO FO 74 EO 12 NumLockon Make/Break EO 12 EO 70 lEO FO 70 EO FO 12 EO 12 E071 lEO FO 71 EO FO 12 EO 12 EO 68 lEO FO 68 EO FO 12 EO 12 EO 6C lEO FO 6C EO FO 12 EO 12 EO 69 lEO FO 69 EO FO 12 EO 12 EO 75 lEO FO 75 EO FO 12 EO 12 EO 72 lEO FO 72 EO FO 12 EO 12 EO 70 lEO FO 70 EO FO 12 E012E07A lEO FO 7A EO FO 12 EO 12 EO 74 lEO FO 74 EO FO 12 • If the left Shift key is held down. the FO 12/12 shift make and break are sent with the other scan codes. If the right Shift key is held down. FO/59/59 is sent. If both Shift keys are down. both sets of codes are sent with the other scan code. Figure 13. Keyboard Scan Codes, Set 2 Key No. 95 Scan Code MakefBreak EO 4A1EO FO 4A Shift Ca.e MakefBreak * EO FO 12 EO 4A/EO FO 4A EO 12 • If the left Shift key is held down. the FO 12112 shift make and break are sent with the other scan codes. If the right Shift key is held down. FO 59/59 is sent. If both Shift keys are down. both sets of codes are sent with the other scan code. Figure 14. Keyboard Scan Codes, Set 2 Keyboards (101- and 102-Key). Scan Codes 33 Key No. Scan Code Make/Break EO 12 EO 7C lEO FO 7C EO FO 12 124 Ctrl Case, Shift Case Make/Break EO 7C/EO FO 7C Aft Case Make/Break 84/F084 Figure 15. Keyboard Scan Codes, Set 2 Key No. 126· Make Code Ctrl Key Pressed E1 1477 E1 FO 14 FO 77 EO 7E EO FO 7E • This key is not typematic. All associated scan codes occur on the make of the key. Figure 16. Keyboard Scan Codes, Set 2 34 Keyboards (101- and 102-Key), Scan Codes Set 3 Scan Code Tables In scan-code set 3, each key is assigned a unique a-bit make scan code, which is sent when the key is pressed. Each key also sends a break code when the key is released. The break code consists of 2 bytes, the first of which is the break-code prefix, hex FO; the second byte is the same as the make scan code for that key. The typematic scan code for a key is the same as the key's make code. With this scan-code set, each key sends only one scan code, and no keys are affected by the state of any other keys. The following figure shows the codes sent for the keys, regardless of any shift states in the keyboard or system. Refer to "Keyboard Layouts" beginning on page 1 to determine the character associated with each key number. Key Number 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Make Code OE 16 1E 26 25 2E 36 3D 3E 46 45 4E 55 66 OD 15 10 24 2D 2C 35 3C 43 44 4D 54 58 Break Code Default Key State FOOE FO 16 FO 1E F026 F025 F02E F036 F03D F03E F046 F045 F04E F055 F066 FOOD FO 15 FO 10 F024 F02D F02C F035 F03C F043 F044 F04D F054 F05B Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Figure 17 (Part 1 of 3). Keyboard Scan Codes, Set 3 Keyboards (101- and 102-Key), Scan Codes 35 Key Number 29- Make Code 49 50 51 52 53 54 55 57 58 60 61 62 64 75 76 79 80 81 83 5C 14 1C 1B 23 2B 34 33 3B 42 4B 4C 52 53 5A 12 13 1A 22 21 2A 32 31 3A 41 4\l 4A 59 11 19 29 39 58 67 64 61 6E 65 63 84 60 85 86 89 90 91 92 6F 60 6A 76 6C 6B 30 31 32 33 34 35 36 37 38 39 40 41 42 -43 44 45 -46 47 48 Break Code Default Key State F05C FO 14 FO 1C FO 1B F023 F02B F034 F033 F03B F042 F04B F04C F052 F053 F05A FO 12 FO 13 FO 1A F022 FO 21 F02A F032 FO 31 F03A F041 F049 F04A F059 FO 11 FO 19 F029 F039 F058 F067 F064 FO 61 F06E F065 F063 F060 F06F F06D F06A F076 F06C F06S Figure 17 (Part 2 of 3). Keyboard Scan Codes, Set 3 36 Keyboards (101- and 102-Key), Scan Codes Typematic Make/Break Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Make/Break Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Typematic Make/Break Make/Break Make/Break Typematic Make only Make only Make only Typematic Typematic Make only Make only Typematic Typematic Make only Make only Typematic Make only Make only Make only Key Number 93 95 96 97 98 99 100 101 102 103 104 105 106 108 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Make Code 69 n 75 73 72 70 7E 70 74 7A 71 84 7C 79 08 07 OF 17 1F 27 2F 37 3F 47 4F 56 5E 57 5F 62 Break Code Delaun Key State F069 Fon F075 F073 FO 72 F070 F07E F070 F074 F07A F071 F084 F07C F079 F008 F007 FOOF FO 17 FO 1F F027 FO 2F F037 F03F F047 F04F F056 F05E F057 F05F F062 Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Typematic Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only Make only • 101-key keyboard only . •• 102-key keyboard only. Figure 17 (Part 3 of 3). Keyboard Scan Codes, Set 3 Keyboards (101- and 102-Key), Scan Codes 37 Clock and Data Signals The keyboard and system communicate over the 'clock' and 'data' lines. The source of each of these lines is an open-collector device on the keyboard that allows either the keyboard or system to force a line to an inactive (low) level. When no communication is occurring, the 'clock' line is at an active (high) level. The state of the 'data' line is held active (high) by the keyboard. When the system sends data to the keyboard, it forces the 'data' line to an inactive level and allows the 'clock' line to go to an active level. An inactive signal will have a value of at least 0, but not more than +0.7 volts. A signal at the inactive level is a logical O. An active signal will have a value of at least +2.4, but not more than +5.5 volts. A signal at the active level is a logical 1. Voltages are measured between a signal source and the dc network ground. When the keyboard sends data to, or receives data from the system, it generates the 'clock' signal to time the data. The system can prevent the keyboard from sending data by forcing the 'clock' line to an inactive level; the 'data' line may be active or inactive during this time. During the BAT, the keyboard allows the 'clock' and 'data' lines to go to an active level. Data Stream Data transmissions to and from the keyboard consist of an 11-bit data stream (Mode 2) sent serially over the 'data' line. The following figure shows the functions of the bits. 38 Keyboards (101 and 102 Key), Clock and Data Signals Bit 11 10 9 8 7 6 5 4 3 2 Function Stop bit (always 1) Parity bit (odd parity) Data bit 7 (most-significant) Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 (least-significant) Start bit (always 0) Figure 18. Keyboard Data Stream Bit Definitions The parity bit is either 1 or 0, and the 8 data bits, plus the parity bit, always have an odd number of 1's. Note: Mode 1 is a 9-bit data stream that does not have a parity bit or stop bit, and the start bit is always 1. Data Output When the keyboard is ready to send data, it first checks for a keyboard-inhibit or system request-to-send status on the 'clock' and 'data' lines. If the 'clock' line is inactive (low), data is stored in the keyboard buffer. If the 'clock' line is active (high) and the 'data' line is inactive (request-to-send), data is stored in the keyboard buffer, and the keyboard receives system data. If the 'clock' and 'data' lines are both active, the keyboard sends the 0 start bit, 8 data bits, the parity bit, and the stop bit. Data is valid before the trailing edge and beyond the leading edge of the clock pulse. During transmission, the keyboard checks the 'clock' line for an active level at least every 60 milliseconds. If the system lowers the 'clock' line from an active level after the keyboard starts sending data, a condition known as line contention occurs, and the keyboard stops sending data. If line contention occurs before the leading edge of the 10th clock signal (parity bit), the keyboard buffer returns the 'clock' and 'data' lines to an active level. If contention does not occur by the 10th clock signal, the keyboard completes the transmission. Following line contention, the system mayor may not request the keyboard to resend the data. Keyboards (101 and 102 Key), Clock and Data Signals 39 Following a transmission, the system can inhibit the keyboard until the system processes the input, or until it requests that a response be sent. Data Input When the system is ready to send data to the keyboard, it first checks to see if the keyboard is sending data. If the keyboard is sending, but has not reached the 10th 'clock' signal, the system can override the keyboard output by forcing the keyboard 'clock' line to an inactive (low) level. If the keyboard transmission is beyond the 10th 'clock' signal, the system must receive the transmission. If the keyboard is not sending, or if the system elects to override the keyboard's output, the system forces the keyboard 'clock' line to an inactive level for more than 60 microseconds while preparing to send data. When the system is ready to send the start bit (the 'data' line will be inactive), it allows the 'clock' line to go to an active (high) level. The keyboard checks the state of the 'clock' line at intervals of no more than 10 milliseconds. If a system request-to-send signal (RTS) is detected, the keyboard counts 11 bits. After the 10th bit, the keyboard checks for an active level on the 'data' line, and if the line is active, forces it inactive, and counts one more bit. This action signals the system that the keyboard has received its data. On receipt of this signal, the system returns to a ready state, in which it can accept keyboard output, or goes to the inhibited state until it is ready. If the keyboard 'data' line is found at an inactive level following the 10th bit, a framing error has occurred, and the keyboard continues to count until the 'data' line becomes active. The keyboard then makes the 'data' line inactive and sends a Resend command. Each system command or data transmission to the keyboard requires a response from the keyboard before the system can send its next output. The keyboard will respond within 20 milliseconds unless the system prevents keyboard output. If the keyboard response is invalid or has a parity error, the system sends the command or data again. However, two-byte commands require special handling. If hex F3 (Set Typematic Rate/Delay), hex FO (Select Alternate Scan Codes), or hex ED (Set/Reset Mode Indicators) have been sent and acknowledged, and the value byte has been sent but the response is 40 Keyboards (101 and 102 Key), Clock and Data Signals invalid or has a parity error, the system resends both the command and the value byte. Encode and Usage The keyboard routine, provided in the ROM BIOS, is responsible for converting the keyboard scan codes into what is called Extended ASCII. The extended ASCII codes returned by the ROM routine are mapped to the U.S. English keyboard layout. Some operating systems may make provisions for alternate keyboard layouts by providing an interrupt replacement routine, which resides in the read/write memory. This section discusses only the ROM routine. Extended ASCII encompasses 1-byte character codes with possible values of 0 to 255, an extended code for certain extended keyboard functions, and functions handled within the keyboard routine or through interrupts. Keyboards (101 and 102 Key), Clock and Data Signals 41 The character codes are passed through the BIOS keyboard routine to the system or application program. In the following figure "-1" means the combination is suppressed in the keyboard routine. The codes are returned in the AL register. Key Base Case 1 2 3 4 5 6 7 8 9 10 11 12 13 15 , - 1 2 3 4 5 6 7 8 9 0 ! @ = Backspace (008) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Caps Lock 31 32 33 34 35 36 37 38 39 40 41 Uppercase -I (009) q # $ % A & * ( ) - + Backspace (008) 1-(*) Q w w e r t E R T Y y u i U 1 0 0 p [ I P { } \ I -1 a s d -1 A 8 D F G H f 9 h j k 1 ; , J K L : " Ctrl -1 -1 Null(OOO) (*) -1 -1 -1 R8(030) -1 -1 -1 -1 U8(031) -1 Del(127) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) DC1(017) ETB(023) ENQ(005) DC2(018) DC4(020) EM(025) NAK(021) HT(009) 81(015) DLE(016) Esc(027) G8(029) F8(028) -1 80H(001) DC3(019) EOT(004) ACK(006) BEL(007) B8(008) LF(010) VT(011) FF(012) -1 -1 (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) -1 (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) Figure 19 (Part 1 of 2). Character Codes 42 AH Keyboards (101 and 102 Key), Clock and Data Signals Key Ba.eCa.e Upperca.e Ctrl Aft 43 44 Shift (Left) CR(013) -1 CR(013) -1 LF(010) -1 SUB(026) CAN(024) ETX(003) SYN(022) STX(002) SO(014) CR(013) -1 -1 -1 -1 -1 -1 Space -1 -1 -1 (*) (*) (*) (*) LF(010) Esc Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) -1 Break(**) (*) -1 (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) -1 -1 -1 Space -1 -1 -1 (*) (*) (*) (*) (*) (*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) Null(*) -1 Pause(**) 46 z z 47 48 49 50 51 52 x c v b n m X C 53 54 55 57 Shift (Right) 58 Ctrl (Left) 60 Alt (Left) 61 62 Alt (Right) 64 Ctrl (Right) 90 Num Lock 95 100 105 106 108 110 112 113 114 115 116 117 118 119 120 121 122 123 125 Scroll Lock 126 . I -1 -1 -1 Space -1 -1 -1 I * - + Enter Esc Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) NIJII (*) Null (*) Null (*) Null (*) Null (*) -1 Pause(**) V B N M < > ? -1 -1 ~1 Space -1 -1 -1 I * - + Enter Esc Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*) Null (*j Null (*) Null (*) Null (*) -1 Pause(**) (*) Refer to "Extended Functions" on page 44. (**) Refer to "Special Handling" on page 48. Figure 19 (Part 2 of 2). Character Codes Keyboards (101 and 102 Key). Clock and Data Signals 43 The following figure is a list of keys that have meaning only in Num Lock, Shift, or Ctrl states. The Shift key temporarily reverses the current Num Lock state. Num Key Lock aase Case 91 92 93 96 97 98 99 101 102 103 104 105 106 7 4 1 8 5 2 0 9 6 3 Home (.) + <- (.) End (.) i (.) (.) j. (.) Ins Page Up (.) -+ (.) Page Down (.) Delete (.... ) Sys Request + (.) AR -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 ( ) .. -1 -1 Ctrl Clear Screen Reverse Word(*) Erase to EOL(') (.) (.) (*) (.) Top of Text and Home Advance. Word (.) Erase to EOS (.) ( ) .. -1 -1 (.) Refer to "Extended Functions." (•• ) Refer to "Special Handling" on page 48. Figure 20. Special Character Codes Extended Functions For certain functions that cannot be represented by a standard ASCII code, an extended code is used. A character code of 000 (null) is returned in AL. This indicates that the system or application program should examine a second code, which indicates the actual function. Usually, but not always, this second code is the scan code of the primary key that was pressed. This code is returned in AH. 44 Keyboards (101 and 102 Key), Extended Functions The following figure is a list of the extended codes and their functions. Second Code 1 3 14 15 16-25 26-28 30-38 39-41 43 44-50 51-53 55 59-68 71 72 73 74 75 76 77 78 79 80 81 82 83 84-93 94-103 104-113 114 115 116 117 118 119 120-131 132 133-134 135-136 137-138 139-140 141 Function Alt Esc Null Character Alt Backspace (Back-tab) Alt Q, w, E, R, T, Y, U, I, 0, P Alt [1.,J Alt A, S, D, F, G, H, J, K, l Alt ; , , Alt \ Alt Z, X, C, V, B, N, M Alt , . / Alt Keypad' Fl to FlO Function Keys (Base Case) Home t (Cursor Up) Page Up Alt Keypad+- (Cursor left) Center Cursor -+ (Cursor Right) Alt Keypad + End ! (Cursor Down) Page Down Ins (Insert) Del (Delete) Shift Fl to FlO Ctrl Fl to FlO Alt Fl to FlO Ctrl PrtSc (Start/Stop Echo to Printer) Ctrl +- (Reverse Word) Ctrl -+ (Advance Word) Ctrl End (Erase to End of Line-EOl) Ctrl PgDn (Erase to End of Screen-EOS) Ctrl Home (Clear Screen and Home) Alt 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, = keys 2-13 Ctrl PgUp (Top 25 Lines of Text and Cursor Home) F11, F12 Shift Fl1, F12 Ctrl F11, F12 Alt F11, F12 Ctrl Up/8 1- Figure 21 (Part 1 of 2). Keyboard Extended Functions Keyboards (101 and 102 Key), Extended Functions 45 Second Code 142 143 144 145 146 147 148 149 150 151 152 153 155 157 159 160 161 162 163 164 165 166 Function Girl Girl Girl Girl Ctrl Girl Girl Girl Girl All All All All All All All All All All All All All KeypadKeypad 5 Keypad + Down/2 InslO Dell. Tab Keypad I Keypad· Home Up Page Up Left Righi End Down Page Down Insert Delele Keypad I Tab Enler Figure 21 (Part 2 of 2). Keyboard Extended Functions Shift States Most shift states are handled within the keyboard routine and are not apparent to the system or application program. In any case, the current status of active shift states is available by calling an entry point in the BIOS keyboard routine. The following keys result in altered shift states: Shift: This key temporarily shifts keys 1 through 13, 16 through 29, 31 through 41, and 46 through 55, to uppercase (base case if in Caps Lock state). Also, the Shift key temporarily reverses the Num Lock or non-Num Lock state of keys 91 through 93, 96, 98, 99, and 101 through 104. Ctrl: This key temporarily shifts keys 3, 7, 12, 15 through 29, 31 through 39, 43, 46 through 52, 75 through 89, 91 through 93, 95 through 108,112 through 124, and 126 to the Ctrl state. The Ctrl key is also used with the Alt and Del keys to initiate the system-reset function, with the Scroll Lock key to initiate the break function, and with the Num Lock key to initiate the pause function. The system-reset, break, 46 Keyboards (101 and 102 Key), Extended Functions and pause functions are described under "Special Handling" on page 48. All: This key temporarily shifts keys 1 through 29, 31 through 43, 46 through 55, 75 through 89, 95, 100, and 105 through 124 to the Alt state. The Alt key is also used with the Ctrl and Del keys to cause a system reset. The Alt key also allows the user to enter any character code from 1 to 255. The user holds down the Ait key and types the decimal value of the characters desired on the numeric keypad (keys 91 through 93, 96 through 99, and 101 through 103). The Alt key is then released. If the number is greater than 255, a modu10-256 value is used. This value is interpreted as a character code and is sent through the keyboard routine to the system or application program. Alt is handled internally in the keyboard routine. Caps Lock: This key shifts keys 17 through 26, 31 through 39, and 46 through 52 to uppercase. When Caps Lock is pressed again, it reverses the action. Caps Lock is handled internally in the keyboard routine. When Caps Lock is pressed, it changes the Caps Lock mode indicator. If the indicator was on, it goes off; if it was off, it goes on. Scroll Lock: When interpreted by appropriate application programs, this key indicates that the cursor-control keys will cause windowing over the text rather than moving the cursor. When the Scroll Lock key is pressed again, it reverses the action. The keyboard routine simply records the current shift state of the Scroll Lock key. It is the responsibility of the application program to perform the function. When Scroll Lock is pressed, it changes the Scroll Lock mode indicator. If the indicator was on, it goes off; if it was off, it goes on. Num Lock: This key shifts keys 91 through 93,96 through 99, and 101 through 104 to uppercase. When Num Lock is pressed again, it reverses the action. Num Lock is handled internal to the keyboard routine. When Num Lock is pressed, it changes the Num Lock mode indicator. If the indicator was on, it goes off; if it was off, it goes on. Shift Key Priorities and Combinations: If combinations of the Alt, Ctrl, and Shift keys are pressed and only one is valid, the priority is: Alt key first, Ctrl key, and Shift key third. The only valid combination is Alt and Ctrl, which is used in the system-reset function. Keyboards (101 and 102 Key), Extended Functions 47 Special Handling System Reset The combination of Alt, Ctrl, and Del keys results in the keyboard routine that starts a system reset or restart. System reset is handled by system BIOS. Break The combination of the Ctrl and Pause/Break keys results in the keyboard buffer being cleared, then the keyboard routine signals interrupt 1B, and finally the extended characters AL = hex 00, and AH = hex 00 are stored in the buffer. Pause The Pause key causes the keyboard interrupt routine to loop, waiting for any character or function key to be pressed. This provides a method of temporarily suspending an operation, such as listing or printing, and then resuming the operation. The method is not apparent to either the system or the application program. The key stroke used to resume operation is discarded. Pause is handled internally in the keyboard routine. Print Screen The Print Screen key results in an interrupt invoking the print-screen routine. This routine works in the alphanumeric or graphics mode, with unrecognizable characters causing blanks. 48 Keyboards (101 and 102 Key), Special Handling System Request When the System Request (Alt and Print Screen) key is pressed, a hex 8500 is placed in AX, and an interrupt hex 15 is executed. When the System Request key is released, a hex 8501 is placed in AX, and another interrupt hex 15 is executed. If an application is to use System Request, the following rules must be observed: Save the previous address. Overlay interrupt vector hex 15. Check AH for a value of hex 85: If yes, process may begin. If no, go to previous address. The application program must preserve the value in all registers, except AX, on return. System Request is handled internally in the keyboard routine. Other Characteristics The keyboard routine does its own buffering, and the keyboard buffer is large enough to support entries by a fast typist. However, if a key is pressed when the buffer is full, the key will be ignored and the alarm will sound. The keyboard routine also suppresses the typematic action of the following keys: Ctrl,Shift, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins. During each interrupt hex 09 from the keyboard, an interrupt hex 15, function (AH) = hex 4F is generated by the BIOS after the scan code is read from the keyboard adapter. The scan code is passed in the AL register with the carry flag set. This is to allow an operating system to intercept each scan code before it is being handled by the interrupt hex 09 routine and have a chance to change or act on the scan code. If the carry flag is changed to 0 on return from interrupt hex 15, the scan code is ignored by the interrupt handler. Keyboards (101 and 102 Key), Special Handling 49 Cables and Connectors The keyboard cable connects to the system with a 6-pin miniature DIN connector and to the keyboard with a 6-position connector. The following figures show the pin configuration and signal assignments. System Connector Keyboard Connector 6 1 2 DIN Connector Pins 1 2 3 4 5 6 Shield FEDCBA Signal Name Keyboard Connector Pins +KBDDATA Reserved Ground +5.0Vdc +KBDCLK Reserved Frame Ground B F C E 0 A Shield Figure 22. Keyboard Connectors Signal and Voltage Assignments 50 Keyboards (101 and 102 Key). Special Handling Specifications Specifications for the keyboard are as follows: Power Requirements • +5 Vdc ± 10% • 275 mAo Size • Length: 492 millimeters (19.4 inches) • Depth: 210 millimeters (8.3 inches) • Height: 58 millimeters (2.3 inches), legs extended. Weight • 2.25 kilograms (5.0 pounds). Keyboards (101 and 102 Key), Specifications 51 Index E A acknowledge (ACK) command alternate key 47 ASCII, extended 41 27 B basic assurance test (BAT) 20 BAT completion code command BAT failure code 27 Belgian keyboard 4 break code 19 break key 48 buffer overrun condition 19 27 echo command 22, 27 enable command, keyboard 22 encode,keyboard 41 extended ASCII 41 extended codes, keyboard 44 F FIFO (first-in-first-out) French keyboard 8 G German keyboard C Canadian keyboard 5 caps lock key 47 character codes 42 clock and data signals 38 combinations, shift key 47 commands from the system control key 46 ctrl state 44 D Danish keyboard 6 data and clock signals 38 data input, keyboard 40 data output, keyboard 39 data stream 38 default disable command 21 delay, typematic 19 Dutch keyboard 7 52 Index 19 9 I Invalid command 22 Italian keyboard 10 21 K key detection error command key encode 41 key-code scanning 19 keyboard buffer overrun condition 19 keyboard description 1 keyboard ID command 27 keyboard layouts 1 28 L S Latin American keyboard 11 line contention, keyboard 39 line protocol, keyboard 20 scan code set 2 31 scan code set 3 35 scan codes, keyboard 28 scanning, key-code 19 scroll lock key 47 select alternate scan codes command 23 sequential key-code scanning set all keys command 23 set default command 23 set key type command 24 set typematic rate/delay 25 set/reset status indicators command, keyboard 24 shift key 46 shift key priorities 47 shift state 44, 46 Spanish keyboard 14 stream, data 38 Swedish keyboard 15 Swiss keyboard 16 system request key 49 system reset 48 M make/break codes 19 mode, keyboard data stream 21 N Norwegian keyboard num lock state 44 number lock key 47 12 o outputs, keyboard 28 overrun command 28 overrun condition, keyboard buffer 19 p pause key 48 Portuguese keyboard 13 power-on reset (POR) 20 power-on routine, keyboard print screen key 48 priorities, shift key 47 protocol, keyboard 20 T 20 test, basic assurance (BAT) typematic delay 19 typematic keys 19 typematic rate 19,25 20 U R rate, typematic 19,25 read 10 command, keyboard resend command 22, 28 reset command 22 reset, power-on (POR) 20 reset, system 48 routine, keyboard 49 19 22 U.K. English keyboard U.S. English keyboard 17 18 Index 53 Numerics 101-key keyboard 102-key keyboard 54 Index 2 3 Characters and Keystrokes Character Codes Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 8 Characters and Keystrokes I Notes: II Characters and Keystrokes Character Codes The following figures show the decimal values, hexadecimal values, and keystrokes for each character. The notes referred to in the figures are on page 7. Characters and Keystrokes 1 Value ~ Characters Value ~ Hell Dec armbol 18 24 19 25 t I 1A 26 1B '0 - Character. Ke,.lrok.. NoID CtrIX CtrlY CtrIZ Ctrl[ Esc, Shift Esc,Crtl Esc 1C 28 10 29 1E 30 1F 31 20 32 21 33 22 23 Backspace, Shift Backspace 09 - Characters and Keystrokes etrl CtrIJ • '" Ctrl6 Ctrl- Blank Space Space Bar, Shift, Space, Ctrl Space, AltSpace I .. Shift 34 .. 35 # # Shift 24 36 $ S Shift 25 37 % % Shift 26 36 & & Shift Shift Shift Clrll OA 2 L- I '0 39 , , 28 40 ( ( 29 41 ) 42 . ) 2A 2B . 43 + + 2C 44 , , 20 45 - - 2E 46 Shift Note 1 Shift Note 2 Value All Characters Value N_ He. Dec Symbol 2F 47 I I 30 48 0 0 NoteS 31 48 1 1 NoteS 32 50 2 2 NoteS 33 51 3 3 Notes 34 52 4 4 NoteS Keplrok. 35 53 5 5 NoteS 36 54 6 6 NoteS 37 55 7 7 NoteS 36 56 8 8 NoteS 39 57 9 9 NOIaS SA 58 : : SB 59 ; ; 3C 60 < < SD 61 = = 3E 62 > > 3F 40 41 63 64 65 ? @ A ? @ A 42 66 B B 43 67 C C All Characters He. Dec Symbol Ke,.trok. Not. 4B 75 K K Note 4 4C 76 L L Note 4 4D n M M Note 4 4E 78 N N 4F 79 0 0 Note 4 50 60 P P Note 4 51 81 Q Q Note 4 52 62 R R Note 4 53 63 S S Note 4 54 64 T T Note 4 55 65 U U Note 4 56 66 V V Note 4 57 67 W W Note 4 58 88 X X Note 4 59 89 V V Note 4 Note 4 Shift Shift Shift Shift Shift Note 4 Note 4 Note 4 44 66 D D Note 4 45 sa E E Note 4 SA 90 Z Z SB 91 [ [ 5C 92 \ \ 50 93 I I SE 94 A A Shift SF 95 - - Shift 60 96 • • 61 97 e a NoteS 88 b b NoteS 48 70 F F Note 4 47 71 e e Note 4 62 Note 4 48 72 H H Note 4 63 99 c c NoteS 49 73 I I Note 4 64 100 d d NoteS 4A 74 J J Note 4 65 101 e e NoteS 66 102 f f NoteS Characters and Keystrokes 3 Value Hex 67 103 Symbol 9 Ka,atro.... 9 HotH Note 5 66 104 h h Note 5 89 105 I i Note 5 6A 106 j j Note 5 68 107 k k Note 5 6C 106 I I Note 5 60 109 m m Note 5 6E 110 n n Note 5 6F 111 0 0 Note 5 70 112 P P Note 5 71 113 q q Note 5 72 114 r r Note 5 73 115 8 8 Note 5 M Character. He. Dec Symbol Ke,..,... 80 128 Ii Alt128 Note 6 81 129 ii Alt129 Note 6 82 130 6 Alt130 Note 6 83 131 a Alt131 Note 6 84 132 Ii Alt132 Note 6 85 133 Altl33 Note 6 66 134 Ali 134 Note 6 • • HotH 87 135 c; Altl35 Note 6 66 136 6 Altl36 Note 6 89 137 i Alt137 Note 6 6A 136 6 All 136 Note 6 88 139 T All 139 Note 6 6C 140 , All 140 Note 6 80 141 -. I All 141 Note 6 74 116 t t Note 5 75 117 u u Note 5 8E 142 II Altl42 Note 6 76 118 v v Note 5 8F 143 II All 143 Note 6 77 119 w w Note 5 90 144 £ Altl44 Note 6 78 120 x x Note 5 91 145 ae Altl45 Note 6 146 ~ All 146 Note 6 79 121 y y Note 5 92 7A 122 z z Note 5 83 147 G Alt147 Note 6 123 { { Shift 94 146 (I All 146 Note 6 7C 124 I I I I Shift 115 149 () All 149 Note 6 70 125 } } 96 150 0 Alt150 Note 6 7E 128 - - Shift Shift 97 151 Ci' Alt151 Note 6 7F 127 t::. Ctrl- 96 152 9 Altl52 Note 6 99 153 Q All 153 Note 6 9A 154 0 Altl54 Note 6 78 4 Dec Value M Character. Characters and Keystrokes Value He,. Dec Nole6 B7 183 r--n All 183 Nole6 Nole 6 B8 184 R All 184 NOle6 All 157 Nole6 B9 185 Nole6 PI All 158 Nole 6 f All 159 Nole6 BA 186 =l All 185 All 186 Nole6 II All 160 Nole6 BB 187 F=i1 All 187 Nole6 188 ~ All 188 NOle6 All 189 Nole6 All 190 Nole6 Symbol Key.lroke. 9B 155 ¢ All 155 9C 156 £ All 156 9D 157 ¥ 9E 158 9F 159 AO 160 A1 161 I All 161 Nole6 BC A2 162 6 All 162 Nole 6 BD 189 A3 163 oJ All 163 Nole6 A4 164 n All 164 Nole6 BE 190 AS A6 A7 f:I 165 .!l 166 .2. 167 A8 168 A9 169 AA 170 l r-, All 165 All 166 All 167 Nole6 Nole6 Nole6 BO 176 B1 1n B2 178 !II I C1 193 All 193 Nole6 C2 194 All 194 Nole6 195 All 195 Nole6 196 All 196 Nole6 197 All 197 Nole6 C6 198 All 198 Nole6 C7 199 All 199 Nole6 C8 200 All 200 Nole6 C9 201 All 201 Nole6 CA 202 All 202 Nole6 CB 203 All 203 NOle6 CC 204 All 204 Nole6 CD 205 All 205 Nole6 CE 206 All 206 Nole6 Nole6 Nole6 NOle6 ... ... ... Nole6 I C5 All 172 » All 192 C4 Yo 175 Nole6 L- Nole6 172 AF All 191 192 All 170 AC « 191 CO C3 Nole6 174 ,...--, BF Nole6 All 171 AE P Nole. All 169 Yo I WJ Kay.lroke. Nole6 171 173 Symbol All 168 AB AD As Characlar. Nole. Dec He,. Value Aa Characler. All 173 Nole6 All 174 Nole6 All 175 Nole6 All 176 Nole6 AI11n Nole6 All 178 Nole6 B3 179 All 179 Nole6 B4 180 f- All 180 Nole6 B5 181 ~ All 181 Nole6 B6 182 HI All 182 Nole6 /---1== I- ~ II I--' ' - - h rL..- r-- ~~ CF 207 All 207 DO 208 All 208 Characters and Keystrokes 5 Value As Characte... Valua Hell Dec Symbol EC 236 GO All 236 Note 6 ED 237 All 237 Note 6 EE 238 '" f All 238 Note 6 EF 239 n All 238 NoleS FO 240 ;;; All 240 Nole6 F1 241 ± All 241 Note 6 F2 242 :l! All 242 Note 6 F3 243 S All 243 Nole6 F4 244 r All 244 Nole6 All 245 Nole6 + All 246 Nole6 Characters and Keystrokes J Ka,.lrok. . NOI. . F5 245 F6 246 F7 247 = All 247 Nole6 FB 246 0 All 246 Nole6 F9 249 • All 246 Nole6 FA 250 All 250 Note 6 FB 251 All 251 Nole6 252 n All 252 NoteS FD 253 2 All 253 Note 6 FE 254 • All 254 Nole6 FF 255 BLANK All 255 Nole6 FC 6 As Characler. • r Notes: 1. Asterisk (*) can be typed by pressing the * key or, in the shift state, pressing the 8 key. 2. Period (.) can be typed by pressing the. key or, in the shift or Num Lock state, pressing the Del key. 3. Numeric characters 0-9 can be typed by pressing the numeric keys on the keyboard or, in the shift or Num Lock state, pressing the numeric keys in the keypad portion of the keyboard. 4. Uppercase alphabetic characters (A-Z) can be typed by pressing the character key in the shift state or the Caps Lock state. 5. Lowercase alphabetic characters (a-z) can be typed by pressing the character key in the normal state or in Caps Lock and shift state combined. 6. The three digits are typed on the numeric keypad while pressing the Alt key. Character codes 001-255 may be entered in this fashion (with Caps Lock activated, character codes 97-122 display in uppercase). Characters and Keystrokes 7 Quick Reference I~~AL ... 8 • 0 16 32 48 64 80 96 112 I~~~AL 0 IVALUE 1 2 3 4 5 6 7 BLANK (SPACE) 0 0 BLANK (NULL) ~ 1 1 ~ ~ 2 2 3 3 4 4 -• " 5 5 4- § 6 6 ~ 7 7 8 8 9 9 10 A 11 B 12 C 13 D ~ L ~ +-+ 14 E ].J 15 F : • .. ~ • t - i 0 ! , 0 . 1 II 2 # 3 $ 4 0/0 5 & 6 7 ( 8 ) 9 I * ·· ---+ c! * +- + · 'I ,• @ p A Q B R C S D T E U F V G W H X I Y J Z K [ , < L -- - . M > N / ? · 0 Characters and Keystrokes, Quick Reference , P a q b r c s d t e u f v g W h x . 1 Y J k z 1 I I { '" m } /\ n '" - 0 ] 6 • • e:~~AL 128 144 160 176 192 208 224 240 I;~~AL 8 0 0 1 1 2 2 3 3 4 4 5 5 6 6 9 , A B <; E a ..u re 1, - 0 , U 0 8 8 e" 9 9 10 A e 0 , •• e U 11 B ..1 ¢ 12 c "1 £ Y4 :::L 13 D 14 E 15 F , 1 .. y •• ~ ~ F == I ~ ~ - » -.lJ d I a J . J1 -. y "" "" lL n < ::::: , , E ex: - ........... e JE 0 l!! , a" 0'" u .. .. a 0 n r-, , a 0 N""" ~ a u" a .. D 000 7 7 C , r-- e 0 • Q • 6 -v00 n cjJ 2 E I n BLANK oFF" Characters and Keystrokes, Quick Reference 9 Notes: 10 Characters and Keystrokes, Quick Reference Power Supply (Types 1 and 2) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No-Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Connector (Type 1) . . . . . . . . . . . . . . . . . . . . . . Power Supply Connectors (Type 2) . . . . . . . . . . . . . . . . . . . . . Power Supply (Types 1 and 2) 1 1 1 2 2 2 2 3 4 Figures 1. 2. 3. 4. 5. 6. II Power Supply Connector (Type 1) .................. Power Supply Connector Voltages and Signal Assignments . System Board Power Supply Cable Connector (Type 2) .... System Board Power Supply Connector Voltage and Signal Assignments ................................ Fixed Disk Drive Power Supply Cable Connectors (Type 2) Fixed Disk Drive Power Supply Connectors Voltage and Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .. Power Supply (Types 1 and 2) 3 3 4 4 5 5 Description The power supply converts the ac input voltage to three dc outputs. A description of the input voltage ranges to the power supply is in the system-specific technical references. The power supply provides power for the following: • • • • • • System board Channel adapters Diskette drives Fixed disk drives Auxiliary device Keyboard. The power switch and two light-emitting diodes (LEOs) are on the front of the system unit. The green LED indicates that the power supply is operating. The yellow LED indicates fixed disk drive activity. Input Protection The input power line is protected against an overcurrent condition by an internal fuse. Ground Leakage Current The system unit ground leakage current does not exceed 500 microamperes at any nominal input voltage. Power Supply (Types 1 and 2) 1 Outputs The power supply provides three voltages: +5, + 12, and -12 Vdc. Output Protection A short circuit placed on any dc output (between outputs or between an output and dc return) latches all dc outputs into a shutdown state with no damage to the power supply. If an overvoltage fault occurs (internal to the power supply), the power supply latches all dc outputs into a shutdown state before any output exceeds 130% of its nominal value. If either of these shutdown states is actuated, the power supply returns to normal operation only after the fault has been removed and the power switch has been turned off for at least ten seconds. Voltage Sequencing At power-on time, the output voltages track within 50 milliseconds of each other when measured at the 50% points. No-Load Operation The power supply is capable of operation with "no load" on the outputs. The output regulation is ± 25% and the 'power-good' signal can be either active or inactive. 2 Power Supply (Types 1 and 2) Power Supply Connector (Type 1) The Type 1 power supply uses a 50-pin card-edge connector mounted on the side of the power supply. The system board plugs into the card-edge connector, eliminating the need for separate cabling. 1 ~ 2 50 ~:::ggg: XXX: XXXX::::::: X~ ~ Figure 1. Power Supply Connector (Type 1) Pin 1/0 Signal Pin 1/0 Signal 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A -12 Vdc + 12 Vdc + 12 Vdc + 12 Vdc +12 Vdc +12Vdc +12Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc +5Vdc System Status 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Power Good I 38 40 42 44 46 48 50 0 Figure 2. Power Supply Connector Voltages and Signal Assignments Power Supply (Types 1 and 2) 3 Power Supply Connectors (Type 2) The Type 2 power supply uses a 15-pin connector for the system board and two 4-pin connectors for the two fixed-disk-drive locations. 9 ~ IQ)@@@@ 2 - @@@@@ 1 - IQ)@@@@ 3- -15 -14 -13 I 7 Figure 3. System Board Power Supply Cable Connector (Type 2) Pin 1/0 Signal 1 3 5 7 9 11 13 15 N/A N/A N/A N/A N/A N/A N/A +5Vdc +12Vdc Signal Ground +5Vdc -12Vdc Signal Ground +5Vdc System Status I Pin UO Signal 2 4 N/A N/A N/A N/A N/A Signal Ground +5Vdc Signal Ground Signal Ground +5Vdc Power Good Signal Ground 6 8 10 12 14 0 N/A Figure 4. System Board Power Supply Connector Voltage and Signal Assignments 4 Power Supply (Types 1 and 2) ((~ @@ @) IIII 1 234 Figure 5. Fixed Disk Drive Power Supply Cable Connectors (Type 2) Pin 1/0 Signal Pin 1/0 Signal N/A N/A + 12 Vdc 2 Signal Ground 4 N/A N/A Signal Ground 3 +5Vdc Figure 6. Fixed Disk Drive Power Supply Connectors Voltage and Signal Assignments Power Supply (Types 1 and 2) 5 Notes: 6 Power Supply (Types 1 and 2) Power Supply (Type 3) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No-Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 'Power Good' Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply (Type 3) 1 2 2 2 2 2 3 Notes: ii Power Supply (Type 3) Description The Type 3 power supply provides power for the following: • • • • • • System board Channel adapters Diskette drive Fixed disk drive Auxiliary device Keyboard. Inputs The Type 3 power supply operates with two ranges of input power. They are selected through the use of a mechanical switch. The following table shows both ranges of input power. Table 1-1. Input Voltage (Vac) Nominal Range 100 - 125 200 - 240 90 - 137 180 - 265 The system-unit-ground leakage current does not exceed 500 microamperes at any nominal input voltage. Refer to the system-specific technical references for additional electrical information. Power Supply (Type 3) 1 Outputs The power supply provides three voltages to the system board: +5, +12. and -12 Vdc. Output Protection A short circuit placed on any dc output (between outputs or between an output and dc return) latches all dc outputs into a shut-down state with no damage to the power supply. If an overvoltage fault occurs (internal to the power supply), the supply latches all dc outputs into a shut-down state before any output exceeds 130% of its nominal value. If either of these shut-down states is actuated. the power supply returns to normal operation only after the fault has been removed and the power switch has been turned off for at least 10 seconds. Voltage Sequencing At power-on time, all voltage must be within the regulation tolerance for a minimum of 200 milliseconds before the 'power good' signal goes active. No-Load Operation The power supply is capable of operation with no load on the outputs. The output regulation is ± 25%, and the 'power good' signal can be either active or inactive. 'Power Good' Signal A 'power good' signal indicates proper operation of the power supply and is active (high) during normal operation. The 'power good' signal is pulled up with a 10-kilohm resistor on the system board. This signal also resets system logic. At power-on time, this signal is low for a minimum of 200 milliseconds but not greater than 650 milliseconds after all outputs have reached specified operating limits. 2 Power Supply (Type 3) Power Supply Connectors The power supply is attached to the system board through a 12-pin connector (J7) and a 6-pin connector (J14). The following table shows the signals and voltages assigned to the power supply output connectors. Table 1-2. Power Supply Connectors J7 Pin 1 2 3 4 5 6 7 8 9 10 11 12 J14 Assignments Power Good Ground +12 Vdc -12 Vdc Ground Ground Ground Ground No Connection +5Vdc +5Vdc +5Vdc Pin 1 2 3 4 5 Assignments Ground Ground +5Vdc +5Vdc +5Vdc Power Supply (Type 3) 3 Notes: 4 Power Supply (Type 3) Compatibility Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Level Language Considerations .................... Assembler Language Programming Considerations .......... Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80286 Anomalies ............. . . . . . . . . . . . . . . . . . .. 80386 Anomalies ...... . . . . . . . . . . . . . . . . . . . . . . . . .. ROM BIOS and Operating System Function Calls ......... Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multitasking Provisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Machine-Sensitive Programs ........................ Math Coprocessor Compatibility ...................... 80287 to 80387 Compatibility ....................... Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8087 to 80287 Compatibility ......... . . . . . . . . . . . . . .. Diskette Drives and Controller ....................... Fixed Disk Drives and Controller ...................... 1 1 1 3 3 3 4 8 8 15 18 19 19 20 21 22 22 23 24 25 27 28 Index 29 ........................................ Compatibility Figures 1. 2. 3. 4. 5. II String Instruction/Register Size Mismatch ...... . . . . .. Write and Format Head Settle Time . . . . . . . . . . . . . . . . Functional Code Assignments . . . . . . . . . . . . . . . . . . . . Math Coprocessor Software Compatibility . . . . . . . . . . .. Diskette Drive Read, Write, and Format Capabilities ..... Compatibility 11 17 21 23 27 Description The differences in system microprocessors, math coprocessors, general system architecture, and diskette drive capabilities must be taken into consideration when designing application programs exclusively for a specific model or programs compatible across the IBM Personal Computer and Personal System/2 product lines. This section discusses these major differences and provides some suggestions to aid you in developing your program. Application Guidelines Use the following information to develop application programs for the IBM Personal Computer and Personal System/2 products. Whenever possible, BIOS should be used as an interface to hardware in order to provide maximum compatibility and portability of applications across systems. Hardware Interrupts Hardware interrupts are level-sensitive for systems using the Micro Channel architecture while systems using the Personal Computer type 1/0 channel design have edge-triggered hardware interrupts. The interrupt controller clears its in-service register bit when the interrupt routine sends an End-of-Interrupt (EOI) command to the controller. The EOI command is sent whether the incoming interrupt request to the controller is active or inactive. In level-sensitive systems, the interrupt-in-progress latch is readable at an 110 address bit position. This latch is read during the interrupt service routine and may be reset by the read operation or may require an explicit reset. Note: Designers may want to limit the number of devices sharing an interrupt level for performance and latency considerations. Compatibility, Applications Guidelines 1 The interrupt controller on level-sensitive systems requires the interrupt request to be inactive at the time the EOI command is sent; otherwise, a "new" interrupt request will be detected and another microprocessor interrupt caused. To avoid this problem, a level-sensitive interrupt handler must clear the interrupt condition (usually by a Read or Write to an 1/0 port on . the device causing the interrupt). After clearing the interrupt condition, a JMP $+2 should be executed prior to sending the EOI command to the interrupt controller. This ensures that the interrupt request is removed prior to re-enabling the interrupt controller. Another JMP $+2 should be executed after sending the EOI command, but prior to enabling the interrupt through the Set Interrupt Enable Flag (STI) command. In the level-sensitive systems, hardware prevents the interrupt controllers from being set to the edge-triggered mode. Hardware interrupt IRQ9 is defined as the replacement interrupt level for the cascade levellRQ2. Program interrupt sharing should be implemented on IRQ2, interrupt hex OA. The following processing occurs to maintain compatibility with the IRQ2 used by IBM Personal Computer products: 1. A device drives the interrupt request active on IRQ2 of the channel. 2. This interrupt request is mapped in hardware to IRQ9 input on the second interrupt controller. 3. When the interrupt occurs, the system microprocessor passes control to the IRQ9 (interrupt hex 71) interrupt handler. 4. This interrupt handler performs an EOI command to the second interrupt controller and passes control to IRQ2 (interrupt hex OA) interrupt handler. 5. This IRQ2 interrupt handler, when handling the interrupt, causes the device to reset the interrupt request prior to performing an EOI command to the master interrupt controller that finishes servicing the IRQ2 request. 2 Compatibility, Applications Guidelines Software Interrupts With the advent of software interrupt sharing, software interrupt routines must daisy chain interrupts. Each routine must check the function value and if it is not in the range of function calls for that routine, it must transfer control to the next routine in the chain. Because software interrupts are initially pointed to 0:0 before daisy chaining, it is necessary to check for this case. If the next routine is pointed to 0:0 and the function call is out of range, the appropriate action is to set the carry flag and do a RET 2 to indicate an error condition. High-Level Language Considerations The IBM-supported languages of IBM C, BASIC, FORTRAN, COBOL, and Pascal are the best choices for writing compatible programs. If a program uses specific features of the hardware, that program may not be compatible with all IBM Personal Computer and Personal System/2 products. Specifically, the use of assembler language subroutines or hardware-specific commands (for example In, Out, Peek, and Poke) must follow the assembler language rules. See "Assembler Language Programming Considerations." Any program that requires precise timing information should obtain it through an operating system or language interface; for example, TIME$ in BASIC. If greater precision is required, the assembler techniques in "Assembler Language Programming Considerations" are available. The use of programming loops may prevent a program from being compatible with other IBM Personal Computer products, IBM Personal System/2 products, and software. Assembler Language Programming Considerations This section describes fundamental differences between the systems in the Personal Computer and Personal System/2 product lines that may affect program development. Compatibility, Applications Guidelines 3 Opcodes The following opcodes work differently on systems using either the 80286 or 80386 microprocessor than they do on systems using the 8088 or 8086 microprocessor. • PUSH SP The 80286 and 80386 microprocessors push the current stack pointer; the 8088 and 8086 microprocessors push the new stack pointer, that is, the value of the stack pointer after the PUSH SP instruction is completed. • Single step interrupt (when TF=1) on the interrupt instruction (Opcode hex CC, CD): The 80286 and 80386 microprocessors do not perform a single-step interrupt on the INT instruction; the 8088 and 8086 microprocessors do perform a single-step interrupt on the INT instruction. • The divide error exception (interrupt 0): The 80286 and 80386 microprocessors push the CS:IP of the instruction that caused the exception; the 8088 and 8086 microprocessors push the CS:IP of the instruction following the instruction that caused the exception. • Shift counts for the 80286 and 80386 microprocessors: Shift counts are masked to 5 bits. Shift counts greater than 31 are treated mod 32. For example, a shift count of 36 shifts the operand four places. • LOCK prefix: When the LOCK prefix is used with an instruction, the system microprocessor executes the entire instruction before allowing interrupts. If a Repeat String Move instruction is locked, interrupts may be disabled for a long duration. The 8088, 8086, and 80286 microprocessors allow the LOCK prefix to be used with most instructions. However, the 80386 microprocessor restricts the use of LOCK to the following instructions: - 4 Bit Test and Set Memory, Register/Immediate Bit Test and Reset Memory, Register/Immediate Compatibility, Applications Guidelines Bit Test and Complement Memory, Register/Immediate XCHG Register, Memory XCHG Memory, Register ADD, OR, ADC, SBB, Memory, Register/Immediate AND, SUB, XOR Memory, Register/Immediate NOT, NEG, INC, DEC Memory. An undefined opcode trap (INT 6) is generated if the LOCK prefix is used in the 80386 environment with an instruction not listed. When the 80286 is operating in the virtual memory mode, the LOCK prefix is 10PL-sensitive. Since the 80386 restricts the use of the LOCK prefix to a specific set of instructions, the LOCK prefix is not 10PL-sensitive in the 80386 environment. • Multiple lockout instructions: There are several microprocessor instructions that, when executed, lock out external bus signals. DMA requests are not honored during the execution of these instructions. Consecutive instructions of this type prevent DMA activity from the start of the first instruction to the end of the last instruction. To allow for necessary DMA cycles, as required by the diskette controller in a multitasking system, multiple lock-out instructions must be separated by a JMP SHORT $+2. • Back-to-back I/O commands: Back-to-back I/O commands to the same I/O ports do not permit enough recovery time for some 110 adapters. To ensure enough time, a JMP SHORT $+2 must be inserted between IN/OUT instructions to the same I/O adapters. Note: MOV AL,AH type instruction does not allow enough recovery time. An example of the correct procedure follows: OUT JMP MOV OUT 10 ADD.AL SHORT $+2 AL.AH 10_ADD.AL • 110 commands followed by an STI instruction: I/O commands followed immediately by an STI instruction do not permit enough recovery time for some system board and channel Compatibility. Applications Guidelines 5 operations. To ensure enough time, a JMP SHORT $+2 must be inserted between the 110 command and the STI instruction. Note: MOV AL,AH type instruction does not allow enough recovery time. An example of the correct procedure follows: OUT IO_ADD,Al JMP SHORT $+2 MOV Al,AH STI • NT bit and 10PL bits: When the 80286 is operating in the Real Address mode, the NT and 10PL bits in the flag register cannot be changed; the bits are zero. The 80386 allows the NT bit and the 10PL bits to be modified by POP stack into flags, and other instructions, while operating in the Real Address mode. This has no effect on the Real Address mode operation. However, upon entering Protected Mode operation, the NT bit should be cleared to prevent erroneous execution of the IRET instruction. If NT is set, the IRET attempts to perform a task switch to the previous task. • Overlap of OUT and following instructions: The 80386 has a delayed write to memory and delayed output-to-IIO capability. It is possible for the actual output cycle to 1/0 devices to occur after the completion of instructions following the Out instruction. Under certain conditions, this may cause some programs to behave in an undesirable manner. For example, an interrupt handler routine may output an EOI command to the interrupt controller to drop the interrupt request. If the interrupt handler has an STI instruction following the output instruction, the 80386 may re-enable interrupts before the interrupt controller drops the interrupt request. This could cause the interrupt routine to be reentered. To avoid this problem, either of the following procedures may be used: Place a JMP SHORT $+2 instruction between the OUT instruction and the STI instruction, or 6 Compatibility. Applications Guidelines - Read back the status from the interrupt controller before executing the STI instruction. • Math coprocessor instructions: In 80386-based systems, the mode of the microprocessor and math coprocessor are tightly coupled. This is not the case for 80286-based systems. The 80286-based systems require the math coprocessor FSETPM instruction to be executed to enable the 80287 to operate in the Protected mode. The 80287 remains in the Protected mode until it is reset. The mode of the 80287 determines the format in which the math coprocessor state information is saved by the FSTENV and FSAVE instructions. In the Protected mode, the instruction and data operand pointers are saved as selector/offset pairs; in the Real Address mode, the physical address and opcode are saved. If the FSETPM instruction is encountered in the 80386 environment, it is ignored. The formatting is performed by the 80386, which internally maintains the instruction and data operand pointers. The Real Address mode format image is saved when the 80386 is operating in the Real Address mode or Virtual 8086 mode. The Protected mode format is used otherwise. See also "Math Coprocessor Compatibility" on page 22 for more information. • Use of 32-bit registers and the 32-bit addressing mode: It is possible to use the 32-bit registers and 32-bit addressing mode in all operating modes of the 80386 through the use of the operand-size prefix or address-size prefix. In a multitasking environment, extreme care must be taken to avoid conflicts with other tasks that use extended registers. If the operating system saves the extended 32-bit registers and new segment registers in the task context save area, conflicts will be avoided; if the operating system does not provide this function, another method must be implemented. One possible method is to disable the interrupts while using the extended registers. The extended registers should be saved before use and restored immediately after use while the interrupts are still disabled. The time that interrupts are disabled should be kept as short as possible. Compatibility, Applications Guidelines 7 • Operand Alignment: When multiple bus cycles are required to transfer a multibyte logical operand (for example, a word operand beginning at an address not evenly divisible by 2), the 80386 transfers the highest order bytes fi rst. This characteristic may affect adapters with memory-mapped 1/0 that require or assume that sequential memory accesses are made to the memory 1/0 ports. This problem may be avoided by using a REP MOV8(yte) instead of a REP MOVSW(ord). 80286 Anomalies In the Protected mode, when any of the null selector values (hex 0000, 0001, 0002, and 0003) are loaded into the OS or ES registers with a MOV or POP instruction or a task switch, the 80286 always loads the null selector hex 0000 into the corresponding register. If a coprocessor (80287) operand is read from an "executable and readable" and conforming (ERe) code segment, and the coprocessor operand is sufficiently near the segment limit that the second or subsequent byte lies outside the limit, an interrupt 9 will not be generated. The following describes the operation of all 80286 parts: • Instructions longer than 10 bytes (instructions using multiple redundant prefixes) generate an interrupt 13 (General Purpose Exception) in both the Real Address mode and Protected mode. • If the second operand of an ARPL instruction is a null selector, the instruction generates an interrupt 13. 80386 Anomalies The following describes anomalies that apply to the 8-1 stepping level of the 80386 microprocessor. 80386 Real Address Mode Operation • FSAVE/FSTENV opcode field incorrect: 8 Compatibility, Applications Guidelines The opcode of some numeric instructions is saved incorrectly in the FSAVE/FSTENV format image when the 80386 is operating in the Real Address mode or Virtual 8086 mode. The power-on self-test (POST) code in the system ROM enables hardware interrupt 13 and sets up its vector (INT hex 75) to point to a math coprocessor exception routine in ROM. Any time this routine is executed as a result of an exception, it repairs the opcode field by performing the following sequence: 1. 2. 3. 4. 5. 6. 7. 8. Clears the 'busy' signal latch Executes FNSTENV (save image on stack) Extracts instruction pointer from FSTENV memory image Skips over prefix bytes until opcode is found Inserts correct opcode information in the memory image Executes FLDENV to restore the corrected opcode field Writes the EOI command to the interrupt controller Transfers control to the address pointed to by the NMI handler. Any math coprocessor application containing an NMI handler should require its NMI handler to read the status of the coprocessor to determine if the NMI was caused by the coprocessor. If the interrupt was not generated by the coprocessor, control should be passed to the original NMI handler. Applications do not require any modification for this errata because the BIOS exception routine repairs the opcode field after exceptions. However, if a debugger is used to display the math coprocessor state information, the opcode field will contain an incorrect value for some math coprocessor instructions. • Single stepping repeated MOVS: If a repeated MOVS instruction is executed when single-stepping is turned on (TF = 1 in the EFLAGS register), a single-step interrupt is taken after two move steps on the 80386 microprocessor. The 8088,8086, and 80286 microprocessors take a single-step interrupt after every iteration step. However, for the 80386, if a data breakpoint is encountered on the fi rst iteration of a repeated MOVS, the data break is not taken until after the second iteration. Data Compatibility, Applications Guidelines 9 breakpoints encountered on the second and subsequent iterations stop immediately after the step causing a break. • Wrong register size for string instructions: One of the (E)CX, (E)51, or (E)OI registers will not be updated properly if certain string and loop instructions are followed by instructions that either: Use a different address size (that is, either the string instruction or the following instruction uses an address size prefix), or Reference the stack (such as PU5H/POP/CALLIRET) and the "B" bit in the 55 descriptor is different from the address size used by the instructions. The size of the register (16 bits or 32 bits) is taken from the instruction following the string instruction rather than from the string instruction itself. This could result in one of the following conditions: Only the lower 16 bits of a 32-bit instruction updated (if the 32-bit string instruction was followed by an instruction using a memory operand addressed with a 16-bit address). All 32 bits of a register updated rather than just the lower 16 bits. The following is a list of the instructions and the affected registers: Instruction Register REP MOVS MOVS STOS INS REP INS (E)SI (E)OI (E)OI (E)OI (E)CX Notes: 1. A 32-bit effective address size specified with a string instruction indicates that the 32-bit ESI and EOI registers should be used for forming addresses, and the 32-bit ECX register should be used as the count register. 2. A 32-bit operand size on a repeated string move (MOVS) should be used only if the compiler or programmer can guarantee that the strings do not overlap destructively. An 8-bit or 16-bit MOVS has a predictable effect when the strings overlap destructively. 10 Compatibility, Applications Guidelines Figure 1. String Instruction/Register Size Mismatch The problem only occurs if instructions with different address sizes are mixed, or if a code segment of one size is used with a stack segment of the other size. To avoid this problem, add a NOP instruction after each of the instructions listed in Figure 1 on page 10 and ensure that the NOP instruction has the same address size as the string/loop instruction. If necessary, an address size prefix hex 67 may precede the NOP instruction. • Wrong ECX update with REP INS: ECX (or CX in a 16-bit address size) is not updated correctly in the case of a REP INS1 followed by an early start instruction2 • After executing any repeat-prefixed instruction, the contents of ECX is supposed to be 0, but in the case of an REP INS instruction, ECX is not updated correctly and its contents become hex FFFFFFFF for 32-bit address size operations and hex OFFFF for 16-bit address size operations. INS is still executed the correct number of times and EDI is updated properly. To avoid this problem, one of the following procedures may be used: Insert an explicit MOV ECX,O (or MOV CX,O) instruction after any REP INS instruction. This ensures that the contents of ECX or CX are O. Do not rely on the count in ECX (or CX) after a REP INS instruction but instead, move a new count into ECX (or CX) before using it again. • Test register access fails: Accessing the Translate Lookaside Buffer (TLB) test registers, TR6 and TR7, may not function properly. Avoid using test registers TR6 and TR7 to test the TLB. 1 REP INS refers to any input string Instruction with a repeat prefix. 2 An early start instruction refers to PUSH, POP, or memory reference instructions. Compatibility, Applications Guidelines 11 80288 Compatible Protected Mode Operation • Math coprocessor Save/Restore environment operands: If either of the last two bytes of an FSAVE/FRSTOR or FSTENVlFLDENV is not accessible, the instruction cannot be restarted. An FNINIT instruction must be issued to the math coprocessor before any other math coprocessor instruction can be executed. This problem arises only in demand-paged systems, or demand-segmented systems that increase the segment size on demand. • Wrap-around math coprocessor operands: The 80386 architecture does not permit a math coprocessor operand, or any other operand, to wrap around the end of a segment. If such an instruction is issued in a protected segmented system, and the operand starts and ends in valid parts of a segment, but passes through an inaccessible region of the segment, the math coprocessor may be put in an indeterminate state. Under these conditions, an FCLEX or FINIT must be sent before any other math coprocessor instruction is issued. • Load Segment Limit instruction cannot precede PUSH/POP: If the instruction executed immediately after a Load Segment Limit (LSL) instruction does a stack operation, the value of (E)SP may be incorrect after the operation. Note: Stack operations resulting from noninstruction sources, such as exceptions or interrupts following the LSL, do not corrupt (E)SP. To avoid this problem, make sure that the instruction following an LSL Instruction Is never one that does a push to or pop off the stack. This includes PUSH, POP, RET, CALL, ENTER, and other such Instructions. This can be achieved by always following an LSL Instruction with a NOP Instruction. Even if a forbidden instruction is used, (E)SP may be updated correctly since the problem is data-dependent and only occurs If the LSL operation succeeds (tl'lat Is, sets the ZF flag). 12 Compatibility, Applications Guidelines • LSLlLARIVERRIVERW malfunction with a NULL selector: An LSL, LAR, VERR, or VERW executed with a NULL selector (that is, bits 15 through 2 of the selector set to 0) operates on the descriptor at entry 0 of the Global Descriptor Table (GOT) instead of unconditionally clearing the ZF flag. This problem can be avoided by filling in the "NULL descriptor" (that is, the descriptor at entry 0 of the GOT) with all zeroes, which is an invalid descriptor type. The access to the "NULL descriptor" is made but fails since the descriptor has an invalid type. The failure is reported with ZF cleared, which is the desired behavior. 80386 Extended Protected Mode Operation The following problems exist for operation in the Virtual 8086 mode. • Task switch to Virtual 8086 mode does not set prefetch limit: The 80386 prefetch unit limit is not updated when doing a task switch to the Virtual 8086 mode. This may cause an incorrect segment limit violation to be reported if the microprocessor instruction fetches the segment limit that existed before the task switch. This problem can be avoided by using an IRET with the appropriate items on the stack to start the Virtual 8086 task in place of the task switch method. • FAR jump near page boundary in Virtual 8086 mode: When paging is enabled in the Virtual 8086 mode, and a direct FAR jump (opcode EA) instruction is located at the end of a page (or within 16 bytes of the end), and the next page is not cached in the TLB internal to the 80386, the FAR jump instruction leaves the prefetcher limit at the "end" of the old code segment instead of setting it at the "end" of the new code segment. This can allow execution off the end of the new segment to trigger a segment limit violation, or cause a spurious GP fault if the old and new segments overlap and a prefetch crosses the old segment limit. There is no way to detect code "walking off" the end of a code segment. However, the spurious GP fault can be avoided by simply performing an IRET back to the instruction Compatibility, Applications Guidelines 13 causing the fault. The IRET will set the prefetch limit correctly, provided the exception handler has the ability to determine a spurious GP fault from a "real" GP fault. The following problems exist for operations with paging enabled. • Coprocessor operands: To avoid having a nonstartable instruction involving math coprocessor operands in demand-paged systems, ensure the operands do not cross page boundaries. This can be accomplished by aligning math coprocessor operands in 12S-byte boundaries within a segment, and aligning the start of segments on 12S-byte physical boundaries. • Page fault error code on stack is not reliable: When a page fault (exception 14) occurs, the three defined bits in the error code can be unreliable if a certain sequence of prefetches occurred at the same time. Although the page-fault error code pushed onto the page-fault handler stack is sometimes unreliable, the page-fault linear address stored in register CR2 is always correct. The page-fault handler should refer to the page-fault linear address in register CR2 to access the corresponding page table entry and thereby determine whether the page fault was due to a page-not-present condition or a usage violation. • 1/0 relocated in paged systems: When paging is enabled (PG = 1 in CRO), accessing 1/0 addresses in the range hex 00001000 to hex OOOOFFFF, or accessing a 803S7 math coprocessor using ESC instructions (1/0 addresses hex SOOOOOFS to hex SOOOOOFF) can generate incorrect 1/0 addresses on A12 through A31 if the 1/0 address is the same as a memory linear address that is mapped by the TLB. The physical address corresponding to the memory linear address mapped by the TLB is ANOed with the 1/0 address, causing the 1/0 address to be incorrect in most cases. A suggested method for handling normal 1/0 addresses between hex 00000 and hex OFFFF is as follows: The operating system is required to map the lowest (first) 64KB of linear address space to 16 pages, which are defined such that bits 12 through 15 of the linear and physical addresses are 14 Compatibility, Applications Guidelines equal. This requires that the pages be aligned on a 64KB physical boundary (the physical address associated with the first page has address bits 15 through a equal to 0). A suggested method for handling the math coprocessor 1/0 addresses requires that the memory page at linear address hex 80000000 always be marked "not present" so it cannot be cached in the TLB. This may be accomplished in one of the following ways: Require the operating system to handle a 4KB "hole" in the linear address space at the 2GB boundary. Restrict the linear address space to a 2GB maximum instead of 4GB. No segments will have a linear address above the 2GB boundary. • Spurious page level protection fault: This problem only occurs when the page table and the directory entries that map the stacks for the inner levels of a task are marked as supervisor access only, and an external bus HOLD comes during the cycle that pops (E)SP off the stack during an inter-level RET or IRET. This problem can be avoided by marking the pages that map the inner level stacks (level a, 1, and 2) to permit the user read access. The segmentation protection mechanism can be used to prevent user access to the linear addresses containing these stacks, if required. ROM BIOS and Operating System Function Calls For maximum portability, programs should perform all 1/0 operations through operating system function calls. In environments where the operating system does not provide the necessary programming interfaces, programs should access the hardware through ROM BIOS function calls, if permissible. • In some environments, program interrupts are used for access to these functions. This practice removes the absolute addressing from the program. Only the interrupt number is required. • The coprocessor detects six different exception conditions that can occur during instruction execution. If the appropriate exception mask within the coprocessor is not set, the coprocessor Compatibility, Applications Guidelines 15 sets the 'error' signal. This 'error' signal generates a hardware interrupt 13 (IRQ 13) causing the 'busy' signal to be held in the busy state. The 'busy' signal can be cleared by an 8-bit I/O Write command to address hex OOFO with bits DO through 07 equal to O. The power-on self-test code in the system ROM enables hardware IRQ 13 and sets up its vector to point to a routine in ROM. The ROM routine clears the 'busy' signal latch and then transfers control to the address pointed to by the NMI vector. This maintains code compatibility across the IBM Personal Computer and Personal System/2 product lines. The NMI handler reads the status of the coprocessor to determine if the NMI was caused by the coprocessor. If the interrupt was not caused by the coprocessor, control is passed to the original NMI handler. • In systems using the 80286 or 80386 microprocessor, IRQ 9 is redirected to INT hex OA (hardware IRQ 2). This ensures that hardware designed to use IRQ 2 will operate in these systems. See "Hardware Interrupts" on page 1 for more information. • The system can mask hardware sensitivity. New devices can change the ROM BIOS to accept the same programming interface on the new device. • In cases where BIOS provides parameter tables, such as for video or diskette, a program can substitute new parameter values by building a new copy of the table and changing the vector to point to that table. However, the program should copy the current table, using the current vector, and then modify those locations in the table that need to be changed. In this way, the program does not inadvertently change any values that should be left the same. • The Diskette Parameters table pointed to by INT hex 1E consists of 11 parameters required for diskette operation. It is recommended that the values supplied in ROM be used. If it becomes necessary to modify any of the parameters, build another parameter block and modify the address at INT hex 1E (0:78) to point to the new block. The parameters were established to allow: Some models of the IBM Personal Computer to operate both the 5.25-inch high capacity diskette drive (96 tracks per inch) and the 5.25-inch double-sided diskette drive (48 tracks per inch). 16 Compatibility, Applications Guidelines Some models of the Personal System/2 to operate both the 3.5-inch 1.44M diskette drive and the 3.5-inch 720KB diskette drive. The Gap Length Parameter is not always retrieved from the parameter block. The gap length used during diskette read, write, and verify operations is derived from within diskette BIOS. The gap length for format operations is still obtained from the parameter block. Note: Special considerations are required for format operations. Refer to the diskette section of the IBM Personal Systeml2 and Personal Computer BIOS Interface Technical Reference for the required details. If a parameter block contains a head settle time parameter value of 0 milliseconds, and a write or format operation is being performed, the following minimum head settle times are enforced. Drive Type Head Settle TIme 5.25-lnch Diskette Drives: Double Sided (48 TPI) High Capacity (96 TPI) 20ms 15 ms 3.5-lnch Diskette Drives: 720K 1.44M 20ms 15 ms Figure 2. Write and Format Head Settle Time Read and verify operations use the head settle time provided by the parameter block. If a parameter block contains a motor-start wait parameter of less than 500 milliseconds (1 second for a Personal Computer product) for a write or format operation, diskette BIOS enforces a minimum time of 500 milliseconds (1 second for a Personal Computer product). Verify and write operations use the motor-start time provided by the parameter block. • Programs may be designed to reside on both 5.25-inch or 3.5-inch diskettes. Since not all programs are operating-system dependent, the following procedure can be used to determine the type of media inserted into a diskette drive: Compatibility, Applications Guidelines 17 1. Verify Track 0, Head 0, Sector 1 (1 sector): This allows diskette BIOS to determine if the format of the media is a recognizable type. If the verify operation fails, issue the reset function (AH = 0) to diskette BIOS and try the operation again. If another failure occurs, the media needs to be formatted or is defective. 2. Verify Track 0, Head 0, Sector 16 (1 sector). If the verify operation fails, either a 5.25-inch (48 TPI) or 3.5-inch 720KB diskette is installed. The type can be determined by verifying Track 78, Head 1, Sector 1 (1 sector). A successful verification of Track 78 indicates a 3.5-inch 720KB diskette is installed; a verification failure indicates a 5.25-inch (48 TPI) diskette is installed. Note: Refer to the DOS Technical Reference for the File Allocation Table parameters for single-sided and double-sided diskettes. 3. Read the diskette controller status in BIOS starting with address 40:42. The fifth byte defines the head that the operation ended with. If the operation ended with head 1, the diskette is a 5.25-inch high capacity (96 TPI) diskette; if the operation ended with head 0, the diskette is a 3.5-inch 1.44M diskette. Software Compatibility To maintain software compatibility, the interrupt polling mechanism used by IBM personal computer products is retained. Software that interfaces with the reset port for the IBM personal computer positive-edge interrupt sharing 3 does not create interference. Level-sensitive interrupt hardware allows several devices to simultaneously set a common interrupt line active (low) without interference. Application code that deals directly with the interrupt controller may try to reset the controller to the positive edge-sensitive mode when 3 18 Hex address 02FX or 06FX, where X is the interrupt level. Compatibility, Applications Guidelines relinquishing control. The interrupt control circuitry of the system board prevents setting the controller to the edge-sensitive mode by blocking positive edge-sensitive commands to the interrupt controllers. Multitasking Provisions The BIOS contains a feature to assist multitasking implementation. "Hooks" are provided for a multitasking dispatcher. Whenever a busy (wait) loop occurs in the BIOS, a hook is provided for the program to break out of the loop. Also, whenever BIOS services an interrupt, a corresponding wait loop is exited, and another hook is provided. Thus a program can be written that employs the bulk of the device driver code. The following is valid only in the Real Address mode and must be taken by the code to allow this support. • The program is responsible for the serialization of access to the device driver. The BIOS code is not reentrant. • The program is responsible for matching corresponding Wait and Post calls. Warning: 32-bit operations to the video subsystem can cause a diskette overrun in the 1.44M mode because data width conversions may require more than 12 microseconds. If an overrun occurs, BIOS returns an error code and the operation should be retried. Interfaces There are four interfaces to be used by the multitasking dispatcher: Startup: First, the startup code hooks interrupt hex 15. The dispatcher is responsible to check for function codes of AH = hex 90 or 91. The "Wait" and "Post" sections describe these codes. The dispatcher must pass all other functions to the previous user of interrupt hex 15. This can be done by a JMP or a CALL. If the function code is hex 90 or 91, the dispatcher should do the appropriate processing and return by the IRET instruction. Serialization: It is up to the multitasking system to ensure that the device driver code is used serially. Multiple entries into the code can result in serious errors. Compatibility, Multitasking Provisions 19 Walt: Whenever the BIOS is about to enter a busy loop, it first issues an interrupt hex 15 with a function code of hex 90 in AH. This signals a wait condition. At this point, the dispatcher should save the task status and dispatch another task. This allows overlapped execution of tasks when the hardware is busy. The following is an outline of the code that has been added to the BIOS to perform this function. MOV AX, 90XXH ; ; INT I5H ; JC TIMEOUT ; ; ; NORMAL TIMEOUT LOGIC ; wait code in AH and type code in AL issue call optional: for time-out or if carry is set. time-out occurred normal time-out Post: Whenever the BIOS has set an interrupt flag for a corresponding busy loop, an interrupt hex 15 occurs with a function code of hex 91 in AH. This signals a Post condition. At this point, the dispatcher should set the task status to "ready to run" and return to the interrupt routine. The following is an outline of the code added to BIOS that performs this function. MOV AX. 9IXXH INT I5H ; post code AH and ; type code AL ; issue call Classes The following types of wait loops are supported: • The class for hex 0 to 7F is serially reusable. This means that for the devices that use these codes, access to the BIOS must be restricted to only one task at a time. • The class for hex 80 to BF is reentrant. There is no restriction on the number of tasks that can access the device. • The class for hex CO to FF is noninterrupt. There is no corresponding interrupt for the wait loop. Therefore, it is the responsibility of the dispatcher to determine what satisfies this condition to exit from the loop. 20 Compatibility, Multitasking Provisions Function Code Classes Type Code (AL) Description OOH->7FH Serially reusable devices; the operating system must serialize access. 80H->OBFH Reentrant devices; ES:BX is used to distinguish different calls (multiple 1/0 calls are allowed simultaneously). OCOH->OFFH Wait-only calls; there is no complementary Post for these waits--these are time-out only. Times are function-number dependent. Function Code Assignments: The following are specific assignments for the Personal System/2 BIOS. Times are approximate. They are grouped according to the classes described under "Function Code Classes." Type Code (AL) TimeOut Description OOH Yes Yes No Yes Yes Yes Fixed Disk Diskette Keyboard Fixed Disk Reset Diskette Motor Start Printer 01H 02H OFCH OFDH OFEH (12 seconds) (2 seconds) (50Q-ms Read/Write) (20 seconds) Figure 3. Functional Code Assignments The asynchronous support has been omitted. The serial and parallel controllers generate interrupts, but BIOS does not support them in the interrupt mode. Therefore, the support should be included in the multitasking system code if that device is to be supported. Time-Outs To support time-outs properly, the multitasking dispatcher must be aware of time. If a device enters a busy loop, it generally should remain there for a specific amount of time before indicating an error. The dispatcher should return to the BIOS wait loop with the carry bit set if a time-out occurs. Compatibility, Multitasking Provisions 21 Machine-Sensitive Programs Programs can select machine-specific features, but they must first identify the machine and model type. IBM has defined methods for uniquely determining the specific machine type. The location of the machine model bytes can be found through interrupt 15 function code (AH) = hex CO. See the IBM Personal Systeml2 and Personal Computer BIOS Interface Technical Reference for a listing of model bytes for IBM Personal Computer and Personal System/2 products. Math Coprocessor Compatibility IBM systems use three math coprocessors: the 8088- and 8086-based systems use the 8087, the 80286-based systems use the 80287, and the 80386-based systems use the 80387. In the Real Address mode and Virtual 8086 mode, the 80386/80387 is upward object-code compatible with software for the 808618087 and 80286/80287 Real-Address mode systems; in the Protected mode, the 80386/80387 is upward object-code compatible with software for the 80286/80287 Protected-mode systems. However, if a math coprocessor instruction other than FINIT, FSTSW, or FSTCW is executed by an 80386-based system without an 80387 present, the 80386 waits indefinitely for a response from the 80387. This causes the system to stop processing without providing an error indication. To prevent this problem, software should check for the presence of the 80387 before executing math coprocessor instructions. The BIOS equipment function should be used when possible as the method for detecting the presence of the math coprocessor. The only other differences of operation that may appear when 8086/8087 programs are ported to a Protected-mode 80386/80387 system (not using the Virtual 8086 mode), are in the format of operands for the administration instructions FLDENV, FSTEN, FRSTOR, and FSAVE. These instructions are normally used only by exception handlers and operating systems, not by application programs. 22 Compatibility, Math Coprocessor Operating Mode. 8087 Real Mode 80287 Real Mode 80387 Real Mode 80387 8086 Virtual Mode 80287 Protected Mode 80387 Protected Mode Software Written for: 8087 Real 80287 Real 80287 Protected Yes Yes' Yes' Yes Yes" Yes" Yes" No No No No No Yes Yes" Yes*** Yes*·* No No • See "8087 to 80287 Compatibility." •• See "80287 to 80387 Compatibility." "'See "8087 to 80287 Compatibility" and "80287 to 80387 Compatibility." Figure 4. Math Coprocessor Software Compatibility Many changes have been designed into the 80387 to directly support the IEEE standards in hardware. These changes result in increased performance by eliminating the need for software that supports the IEEE standard. 80287 to 80387 Compatibility The following summarizes the differences between the 80387 and 80287 Math Coprocessors, and provides details showing how 80287 software can be ported to the 80387 Math Coprocessor: Note: Any migration from 8087 directly to the 80387 must also take into account the differences between the 8087 and the 80287. This information is provided on page 25. • The 80387 supports only affine closure for infinity arithmetic, not projective closure. • Operands for FSCALE and FPATAN are no longer restricted in range (except ±oo); F2XM1 and FPTAN accept a wider range of operands. • Rounding control is in effect for FLO constant. • Software cannot change entries of the tag word to values (other than empty) that differ from actual register contents. • In conformance with the IEEE standard, the 80387 does not support special data formats pseudozero, pseudo-NaN, pseudoinfinity, and unnormal. Compatibility, Math Coprocessor 23 Exceptions When the overflow or underflow exception is masked, the only difference from the 80287 is in rounding when overflow or underflow occurs. The 80387 produces results that are consistent with the rounding mode. For exceptions that are not masked, a number of differences exist due to the IEEE standard and to functional improvements to the architecture of the 80387: • There are fewer invalid-operation exceptions due to denormal operands, because the instructions FSQRT, FOIV, FPREM, and conversions to BCO or to integer normalize denormal operands before proceeding. • The FSQRT, FBSTP, and FPREM instructions may cause underflow, because they support denormal operands. • The denormal exception can occur during the transcendental instructions and the FXTRACT instruction. • The denormal exception no longer takes precedence over all other exceptions. • When the operand is zero, the FXTRACT instruction reports a zero-divide exception and leaves - 0 0 in ST(1). • The status word has a new bit (SF) that signals when invalid-operation exceptions are due to stack underflow or overflow. • FLO extended precision no longer reports denormal exceptions, because the instruction is not numeric. • FLO single/double precision when the operand is denormal converts the number to extended precision and signals the denormalized operand exception. When loading a signaling NaN, FLO singie/double precision signals an invalid-operation exception. • The 80387 only generates quiet NaNs (as on the 80287); however, the 80387 distinguishes between quiet NaNs and signaling NaNs. Signaling NaNs trigger exceptions when they are used as operands; quiet NaNs do not (except for FCOM, FIST, and FBSTP, which also raise IE for quiet NaNs). 24 Compatibility, Math Coprocessor • Most 80387 numeric instructions are automatically synchronized by the 80386. No explicit Wait instructions are required for these instructions. To mairitain compatibility with systems using the 8087, an explicit Wait is required before each numeric instruction. • The FLDENV and FRSTOR instructions should be followed by an explicit Wait when used in the 80387 environment. An explicit Wait is not required after these instructions in the 80287 environment. • The 80287 FSETPM (set Protected mode) instruction performs no useful purpose in the 80387 environment; if encountered, it is ignored. • The format of the FSAVE and FSTENV instructions is determined by the current mode of the 80386; the Real Address mode format is used when the 80386 is in the Real Address mode, and the Protected mode format is used when the 80386 is in the Protected mode. • The following applies only to the 81 stepping level 80386: An interrupt 9 does not occur for an operand outside a segment size; an interrupt 13 occurs. 8087 to 80287 Compatibility The 80287 operating in the Real Address mode can execute 8087 software without major modifications. However, because of. differences in the handling of numeric exceptions by the 80287 and the 8087, exception-handling routines may need to be changed. The following summarizes the differences between the 80287 and 8087 Math Coprocessors, and provides details showing how 8087 software can be ported to the 80287 Math Coprocessor. • The 8087 instructions FENl/FNENi and FDISI/FNDISI perform no useful function in the 80287 environment. If the 80287 encouriters one of these opcodes in its instruction stream; the instruction is effectively ignored; none of the 80287 internal states are updated. While 8086 code containing these instructions may be executed on an 80287, it is unlikely that the exception-handling routines containing these instructions will be completely portable to the 80287. Compatibility, Math Coprocessor 25 • The ESC instruction address saved in the 80287 includes any leading prefixes before the ESC opcode. The corresponding address saved in the 8087 does not include leading prefixes. • In the Protected mode, the format of the 80287 saved instruction and address pointers is different from the format of the 8087. The instruction opcode is not saved in the Protected mode; exception handlers have to retrieve the opcode from memory if needed. • Interrupt 7 occurs in the 80286 when executing ESC instructions with either TS (task switched) or EM (emulation) of the 80286 MSW set (TS = 1 or EM = 1). If TS is set, then a Wait instruction also causes interrupt 7. An exception handler should be included in 80286 code to handle these exceptions. • Interrupt 9 occurs if the second or subsequent words of a floating-point operand fall outside a segment size. Interrupt 13 occurs if the starting address of a numeric operand falls outside a segment size. An exception handler should be included in the 80286 code to report these programming errors. • Most 80287 numeric instructions are automatically synchronized by the 80286. The 80286 automatically tests the 'busy' signal from the 80287 to ensure that the 80287 has completed its previous instruction before executing the next ESC instruction. Explicit Wait instructions are not required to ensure this synchronization. An 8087 used with 8086 and 8088 system microprocessors requires explicit Waits before each numeric instruction to ensure synchronization. Although 8086 software having explicit Wait instructions executes perfectly on the 80286 without reassembly, these Wait instructions are unnecessary. The processor control instructions for the 80287 may be coded using either a WAIT or No-WAIT form of the mnemonic. The WAIT forms of these instructions cause the assembler to precede the ESC instruction with a microprocessor Wait instruction. 26 Compatibility, Math Coprocessor Diskette Drives and Controller The following figure shows the read, write, and format capabilities for each type of diskette drive. DllkaH. Drlv.Type 180/180KB Mod. 320/380KB Mod. 5.25-lnch Diskette Drive: Single Sided (48 TPI) Double Sided (48 TPI) RWF RWF RWF 3.5-lnch Diskette Drive: 720KB Drive 1.44MB Drive 1.44MB Mod. 720KB Mod. RWF RWF RWF R-Read W-Write F-Format Figure 5. Diskette Drive Read, Write, and Format Capabilities Notes: 1. 5.25-inch diskettes designed for the 1.2M mode cannot be used in either a 1601180KB or a 320/360KB diskette drive. 2. 3.5-inch diskettes designed for the 1.44M mode cannot be used in a 720KB diskette drive. Warning: 32-bit operations to the video subsystem can cause a diskette overrun in the 1.44M mode because data width conversions may require more than 12 microseconds. If an overrun occurs, BIOS returns an error code and the operation should be retried. Copy Protection The following methods of copy protection may not work on systems using the 3.5-inch 1.44M diskette drive. • Bypassing BIOS Routines: Data Transfer Rate: BIOS selects the proper data transfer rate for the media being used. Diskette Parameters Table: Copy protection, which creates its own Diskette Parameters table, may not work on these drives. Compatibility, Diskette Drive Controller 27 • Diskette Drive Controls: Rotational Speed: The time between two events on a diskette is a function of the controller. Access Time: Diskette BIOS routines must set the track-to-track access time for the different types of media used in the drives. Diskette Change Signal: Copy protection may not be able to reset this signal. • Write Current Control-Copy protection that uses write current control will not work because the controller selects the proper write current for the media being used. Detailed information about specific diskette drives is available in separate technical references. Fixed Disk Drives and Controller Reading from and writing to the fixed disk drive is initiated in the same way as with IBM Personal Computer products; however, new functions are supported. Detailed information about specific fixed disk drives and fixed disk adapters is available in system-specific technical references. 28 Compatibility, Fixed Disk Drive Controller Index A H application guidelines assembler language programming considerations 3 hardware interrupts high-level language considerations 3 B I back-to-back I/O commands BASIC 3 busy loop 20 bypassing BIOS 27 5 C classes, wait loop 20 COBOL 3 condition, wait 20 copy protection 27 D diskette change signal 28 diskette compatibility 27 diskette write current 28 divide error exception 4 E 110 commands and STI instructions 5 IBM C 3 interfaces, multitasking 19 interrupt, single step 4 IRQ 2 16 IRQ 9 16 L level-sensitive interrupts loop, busy 20 M machine model bytes 22 machine-sensitive programs 22 math coprocessor compatibility 22 model bytes 22 multiple lockout instructions 5 edge-triggered interrupts exception, divide error 4 o F opcodes 4 operating system 3 operating system function calls 15 fixed disk controller 28 FORTRAN 3 function calls, operating system 15 function calls, ROM BIOS 15 function codes, multitasking 21 Index 29 p paging 13 parameter tables, BIOS 16 Pascal 3 polling mechanism 18 post 20 provisions, multitasking 19 PUSHSP 4 S serialization, multitasking shift counts 4 single step interrupt 4 software Interrupts 3 startup, multitasking 19 STI instruction 5 system compatibility 1 T time-outs 21 W wait condition 20 wait loop classes 20 write current, diskette Numerics 80286 anomalies 80386 anomalies 30 Index 8 8 28 19 Bibliography Microprocessor and Peripheral Handbook. INTEL Corporation, 210844.001 Introduction to the iAPX 286. INTEL Corporation, 210308.001 iAPX 286 Operating Systems Writer's Guide. INTEL Corporation, 121960.001 iAPX 286 Programmer's Reference Manual. INTEL Corporation, 210498.001 80287 Support Library Reference Manual. INTEL Corporation, 122129 80386 Hardware Reference Manual. INTEL Corporation, 231732.001 Introduction to the 80386. INTEL Corporation, 231252.001 80386 Programmer's Reference Manual. INTEL Corporation, 230985.001 80386 System Software Writer's Guide. INTEL Corporation, 231499 iAPX 286 Hardware Reference Manual. INTEL Corporation, 210760.001 National Semiconductor Corporation, NS16550 Numeric Processor Extension Data Sheet. INTEL Corporation, 210920 Motorola Microprocessor's Data Manual. Motorola Inc. Series B Bibliography 1 Notes: 2 Bibliography --------- ----- - ----- ----_.----® © Copyright International Business Machines Corporation, 1988 All Rights Reserved Printed in the United States of America References in this Publication to IBM products or services do not imply that IBM intends to make them available outside the United States. OOF9809
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