QM_CycloneV_EP4CE15_User_Manual(DaughterBoard) V01 QMTECH Cyclone IV EP4CE15 User Manual(Daughter Board)
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QM_CYCLONE_IV_EP4CE15 DB USER MANUAL Preface The QMTech® Cyclone IV SDRAM Development Board uses Intel(Altera) EP4CE15F23 device to demonstrate Intel’s leadership in offering power-efficient FPGAs. With enhanced architecture and silicon, advanced semiconductor process technology, and power management tools, power consumption for Cyclone IV FPGAs has been reduced by up to 25 percent compared to Cyclone® III FPGAs. The result is the lowest power consumption of any comparable FPGA. QM_CycloneIV_EP4CE15 Daughter Board User Manual Table of Contents 1. QM_CYCLONEIV_EP4CE15 DB INTRODUCTION................................... 3 1.1 1.2 KIT OVERVIEW........................................................................... 3 DAUGHTER BOARD TOP VIEW ....................................................... 3 2. EXPERIMENT (1): USB TO SERIAL PORT............................................... 4 3. EXPERIMENT (2): VGA DISPLAYS ......................................................... 7 1. EXPERIMENT (3): GMII ETHERNET TEST ............................................ 10 2. EXPERIMENT (4): MICROSD CARD TEST ............................................ 15 3. REFERENCE........................................................................................ 18 4. REVISION .......................................................................................... 19 QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 1. QM_CycloneIV_EP4CE15 DB Introduction 1.1 Kit Overview QM_CycloneIV_EP4CE15 provides several user interfaces to meet different customer needs. Below section lists the detailed info of these user interfaces: 1.2 USB to UART Serial Port, by using Silicon Labs’ CP2102-GMR chip. 16bit(RGB565) VGA display interface, by using resistor dividers; GMII ethernet interface, by using Realtek’s RTL8211EG chip; CMOS/CCD camera interface, by using 18pin female header; Two Digilent PMOD standard compatible female headers; MicroSD card slot; Daughter Board Top View Below figure shows the daughter board of QM_CycloneIV_EP4CE15 development kit. The daughter board’s dimension is 108.71mm x 134.62mm. All the functional chips’ power supply is injected from the 64P female connector, detailed connection refer to the hardware schematic. Camera Interface 16bit VGA PMOD GMII Ethernet PMOD MicroSD/ TF Slot CP2102 USB to UART User Keys and LEDs 7-SEG LEDs Figure 1-1. QM_CycloneIV_EP4CE15 Daughter Board QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 2. Experiment (1): USB to Serial Port The CP2102-GMR is a USB 2.0 to serial port bridge chip designed by Silicon Labs. The CP2102-GMR includes a USB 2.0 full-speed function controller, USB transceiver, oscillator, UART and eliminates the need for other external USB components are required for development. Below figure shows the hardware design of CP2102-GMR on the QM_CycloneIV_EP4CE15 daughter board. R34 22 21 20 19 18 NC11 NC10 NC9 NC8 NC7 U5 6 4.7K VDD C35 RST 9 100nF 3 29 GND GND_TP CTS RTS TXD RXD GND 23 24 26 25 IO_J2 IO_J1 GND 9 8 7 6 G4 Vcc G3 DD+ G2 ID GND G1 1 2 3 4 5 VBUS REGIN DD+ DTR SUSPEND SUSPEND RI DCD DSR 10 13 14 15 16 17 MINI_USB 8 7 5 4 NC1 NC2 NC3 NC4 NC5 NC6 C36 4.7uF J4 28 12 11 2 1 27 CP2102-GM GND Figure 2-1. CP2102 Hardware Design Before start to test the CP2102-GMR’s USB to UART serial communication function, make sure all the hardware connections of the development kit are correctly connected. Altera USB Blaster’s JTAG cable shall be connected to QM_CycloneIV_EP4CE15 core board’s JTAG interface. Then power on the development kit with 5V DC power source and plug the Mini-USB cable in the daughter board, below figure shows an example hardware setup: 5V DC Source JTAG Cable Mini-USB Cable QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 All the test examples are developed in the Quartus II 15.1environment. Open the CP2102 test project located in this release folder: /Software/ Project05_CP2102_UART_V2. Below figure shows the example project of uart_top: Figure 2-2. CP2102 UART Communication Test Example In this example project, the default communication parameters are: 9600bps, 8 data bit, No Parity Check, 1 stop bit. If users want to test other communication parameters, change the source code accordingly. QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 After the CP2102 communication test project correctly synthesized, implemented and generated *.sof file, users could use Quartus program tool to program the generated *.sof file into FPGA. Below image shows the FPGA program status with program tool. Figure 2-3. Program *.sof File The CP2102 example test project’s main functionality is performing an UART loopback communication. The FPGA program will send the received UART data back to the PC. Below figure shows user employees some PC based UART test tool to send data to FPGA: http://www.cmsoft.cn QQ:10865600. After a short while the PC UART test tool will receive the same data stream from FPGA, which means the CP2102 loopback test program is running correctly. Figure 2-4. UART Loopback Test QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Experiment (2): VGA Displays The RGB signal accepted by the color monitor is an analog signal, one for each color, in the range 0V to 0.7V according to the VGA spec. So the digital color signal generated by the video controller should be converted to an analog signal. The daughter board uses resistor to form a voltage divider circuit in combination with the 75 ohm load resistance of VGA monitor. Below image shows the hardware design. J7 IO_B21 1 2 3 4 1K 8 7 6 5 IO_D22 IO_E21 1 2 3 4 1K 8 7 6 5 IO_H21 IO_H22 1 2 3 4 1K RN1 RN2 RN3 2K 2K 2K 8 7 6 5 IO_J21 R66 IO_J22 R67 IO_M20 IO_N19 IO_M19 1 2 3 4 1 2 3 4 8 7 6 5 IO_C22 IO_D21 1 2 3 4 RN5 RN4 2K 2K 8 7 6 5 IO_C21 1 2 3 4 RN8 8 7 6 5 1 2 3 4 2K IO_F22 1 2 3 4 8 7 6 5 GND 11 10 15 5 CONN_VGA RN6 8 7 6 5 RN7 IO_B22 IO_F21 100R 100R 6 1 16 IO_N20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 3. IO_E22 1 2 3 4 2K 8 7 6 5 C39 100nF GND RN9 8 7 6 5 RN10 1 2 3 4 2K 8 7 6 5 RN11 Figure 3-1. VGA Display Hardware Designs Before start to test the VGA display function, make sure all the hardware connections of the development kit are correctly connected. Altera USB Blaster’s JTAG cable shall be connected to QM_CycloneIV_EP4 CE15 core board’s JTAG interface. Then power on the development kit with 5V DC power source and the VGA cable shall also be plugged in the board, below figure shows an example hardware setup: 5V DC Source VGA Cable JTAG Cable SW2 Button QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Open the VGA test project located in this release folder: /Software/ Project08_VGA. Below figure shows the example project of VGA_test: Figure 3-2. VGA Display Function Test In this example project, the default VGA output resolution parameter is 1024x768@60Hz. If users want to test other display parameters, change the source code accordingly. Figure 3-3. VGA Display Parameters After the VGA display test project correctly synthesized, implemented and generated *.sof file, users could use Altera Quartus program tool to program the generated *.sof file into FPGA. Below image shows the FPGA program status with program tool. QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Figure 3-4. Program FPGA After the FPGA correctly loaded the vga_test.sof file and users pressed the SW2 button on core board, the VGA monitor will display different color patterns. Below image shows the example color bar pattern. Figure 3-5. VGA Display Test QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Experiment (3): GMII Ethernet Test 1. The daughter board uses RTL8211EG to implement the 10M/100M/1000M triple speed ethernet interface. It provides all the necessary physical layer functions to transmit and receive ethernet packets over the CAT.5 UTP cable. The data transfer between PHY and FPGA is via the Gigabit Media Independent Interface(GMII) for 1000Base-T. The RTL8211EG-VB chip supports 3.3V signaling for GMII interface. Below image shows the hardware design of TRL8211EG: 3V3 4.7uH C45 4.7uF 3V3 19 21 22 23 25 27 28 29 R47 R59 4.7K 4.7K 4.7K 4.7K 4.7K IO_R22 4.7K IO_U21 IO_W21 4.7K 38 56 DVDD10 DVDD10 33 48 TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 MDI[3]MDI[3]+ MDI[2]MDI[2]+ RXDV/PHY _AD2 RXCLK RXER_AN1 MDI[1]MDI[1]+ RTL8211EG MDI[0]MDI[0]+ RXD0 RXD1 RXD2 RXD3 RXD4/SELRGV RXD5/TXDLY RXD6/RXDLY RXD7_AN0 CKXTAL1 INTB R65 0R 3V3 4.7K 50 51 52 4.7K R57 3V3 CKXTAL2 CLK125 PMEB ENSWREG RSET R43 HR911130A 14 13 12 11 530R GND R56 GND R44 530R 15 14 9 8 12 11 6 5 9 8 7 4 6 5 3 2 1 C12 61 22pF 3 C40 100nF 4 Y2 25MHz COL/Mode CRS PHY RSTB DVDD10_1 DVDD10_2 AVDD10 AVDD10 AVDD10 7 13 59 20 26 37 49 DVDD33_1 DVDD33_2 DVDD33_3 DVDD33_4 3 REG_OUT AVDD33_1 AVDD33_2 64 LED0_PHY AD0 LED1_PHY AD1 LED2 2 4 63 3V3 R58 31 32 GTX_CLK TXEN TXCLK TXER GND_TP R50 R51 R52 R53 IO_K22 IO_L21 IO_L22 IO_M21 IO_N21 IO_N22 IO_P21 IO_P22 3V3 MDC MDIO 10 60 REG_OUT R54 18 24 30 R55 GND 3V3 36 39 40 41 43 44 45 46 4.7K IO_K21 IO_M22 4.7K IO_R21 GND 3V3 3V3 3V3 3V3 34 35 42 47 65 IO_V22 IO_W22 IO_Y 21 IO_Y 22 IO_AA20 IO_AB19 IO_AA19 IO_AB18 100R GND_1 GND_2 GND_3 GND R61 IO_V21 IO_AB20 4.7K IO_AA18 VDDREG U6 53 54 IO_AB17 IO_AA17 GNDGND GND R48 1.5K R60 3V3 GND AVDD10_1 AVDD10_2 AVDD10_3 3V3 IO_U22 C44 100nF 62 MDI_3MDI_3+ MDI_2MDI_2+ MDI_1MDI_1+ MDI_0MDI_0+ TCT P1 2 1 GND C11 1 Y ellow_LED+ Y ellow_LEDGreen_LEDGreen_LED+ 10 15 16 C42 100nF NC1 NC2 C43 4.7uF DVDD10 SHLD1 SHLD2 SHLD3 AVDD10 22pF 55 57 R46 R45 4.7K 4.7K 3V3 58 R42 2.49K GND GND 16 17 L3 REG_OUT GND Figure 1-1. RTL8211 Hardware Design Before start to test the GMII ethernet communication function, make sure all the hardware connections of the development kit are correctly connected. Altera USB Blaster’s JTAG cable shall be connected to QM_CycloneIV_EP4CE15 core board’s JTAG interface. The ethernet cable shall be plugged in the board and the test computer simultaneously. Then power on the development kit with 5V DC power source. Below figure shows an example hardware setup: QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 5V DC Power Ethernet Cable JTAG Cable Figure 1-2. Test Setup Use Quartus II 15.1 to open the GMII ethernet test project located in this release folder: /Software/ Project09_GMII_Ethernet. Below figure shows the example project of ethernet_test: QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 After the ethernet test project correctly synthesized, implemented and generated *.sof file, users could use Altera Quartus program tool to program the generated *.sof file into FPGA. Below image shows the FPGA program status with program tool. Figure 1-3. FPGA Program Users could check the ethernet connection status in the Windows OS. Below images shows the ethernet communication speed between the FPGA development board and the test computer is 1Gbps based. QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 In order to finish this ethernet test, users need to set the Windows’s Static IP into 192.168.0.3: Figure 1-4. 配置电脑端 IP Run Windows Command Console as administrator. In that DOS type command window bind the development board’s IP address(192.168.0.2) and MAC address (00-0a-35-01-fe-c0) by typing command: ARP -s 192.168.0.2 00-0a-35-01-fe-c0: Figure 1-5. Binding IP and MAC QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Open the NetAssist ethernet debug tool and set the communication parameters as shown in below figure. Then press the【Send】button to send the test data http://www.cmsoft.cn QQ:10865600 to the FPGA development board. In response, the FPGA will send back test data “HELLO QMTECH BOARD” to the test PC. Figure 1-6. GMII Ethernet Test Result QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Experiment (4): MicroSD Card Test The daughter board provides a MicroSD slot to extend MicroSD or TF card. In this experiment, we uses 8GB Micro SDHC card provided by Kingston. The Micro SDHC card meets the specification of SD V2.0. Below image shows the hardware design of MicroSD slot: J9 GND 4.7k IO_AB16 4.7k IO_AA16 4.7k IO_AB15 R71 DNP IO_AA15 R70 R69 4.7k IO_AB14 4.7k IO_AA14 1 2 3 4 5 6 7 8 R68 4.7k IO_AB13 9 DAT2 CD/DAT3 CMD VDD CLK VSS DAT0 DAT1 CD GND1 GND2 GND3 GND4 3V3 R74 R73 R72 10 11 12 13 2. Micro SD_2 GND Figure 2-1. MicroSD Hardware Design Before start to test the MicroSD read/write function, make sure all the hardware connections of the development kit are correctly connected. Altera USB Blaster’s JTAG cable shall be connected to QM_CycloneIV_EP4CE15 core board’s JTAG interface. The Kinston 8 GB micro SD card shall be plugged in the board. Then power on the development kit with 5V DC power source. Below figure shows an example hardware setup: MicroSD Card JTAG Cable Figure 2-2. Test Environment Setup In this test example, the MicroSD card is working under SPI mode which could be easily handled by FPGA. SPI interface only has four wires: CS, MOSI, MISO, CLK. The clock frequency for the SPI interface is 25MHz which is divided by the on board 50MHz crystal directly. After Power-On, the MicroSD card enters SD mode and users need to send command to make the MicroSD switch to SPI mode. Then users need to follow the sequence shown in below figure to initialize the MicroSD card. Users may refer to the SD v2.0 spec for more details regarding to the Read and Write protocol. QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 Figure 2-3. Initialize Sequence After correctly initialized the MicroSD, the test program will write a batch of test data into the MicroSD card and then read back all these written value for further comparison. Here we use Signaltap to monitor these data transfer between the FPGA and the MicroSD card. Users may follow the Signaltap settings shown in below figure to observe the transactions. The sampling clock frequency is using on board 50MHz crystal and the trigger signal for sampling is data_come. When data_come goes high, there will be data comes from MicroSD card. QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 After the MicroSD test project correctly synthesized, implemented and generated *.sof file, users could use Altera Quartus SignalTap tool to program the generated *.sof file into FPGA. And then press the button SW2 on FPGA core board to trigger the test. After a short while, the SignalTap will stop capturing the data immediately after the data_come goes high. Then we can see the init_o is already in high status which means the MicroSD has already been correctly initialized. And the data signal mydata_o displays the data read out from MicroSD card. Figure 2-4. Data Write and Read Waveform QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 3. Reference [1] [2] [3] [4] [5] [6] [7] [8] ep4ce15f23-sdram.pdf db-fpga-ep4ce15f23-v01.pdf an592.pdf an592_ch.pdf cyiv-5v1.pdf cyiv-5v2.pdf cyiv-5v3.pdf pcg-01008.pdf QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01 4. Revision Doc. Rev. Date Comments 0.1 1/1/2018 Initial Version. 1.0 12/1/2018 V1.0 Formal Release. 2.0 28/12/2018 V2.0 Formal Release. QM_CycloneIV_EP4CE15 Daughter Board User Manual-V01
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