R23 2659_7040 44_CPU_Preliminary_Customer_Engineering_Reference_Manual_Jul63 2659 7040 44 CPU Preliminary Customer Engineering Reference Manual Jul63
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R23-2659_7040-44_CPU_Preliminary_Customer_Engineering_Reference_Manual_Jul63 R23-2659_7040-44_CPU_Preliminary_Customer_Engineering_Reference_Manual_Jul63
User Manual: R23-2659_7040-44_CPU_Preliminary_Customer_Engineering_Reference_Manual_Jul63
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FIGURE LIST
INSTRUCTION
FIGURE
INSTRUCTION
ACIJ/
ADDI/
ALSv'
ANA'
ARSV'
4-1&\
3 -{]'C
46- ,c "i
22-\,,0
AXTX
35
12 -- S
23-1.M;r.,
19-
CALv~
CAPV
CASv~
CCS..J
CHS
CLAV
CLSy
COM/
DC TV'
DFAD
DFDP
DFMP
DFSB
DVPY'
ENB .'
ENK/
ETTA
FADv
FDPV
FMP:/
FSB\f
26-b~
29"~
24.·v; ,
28 "
32"
5,"
44'-'
61,
55
32-~
45,~
44~-'
45-'
32"
32 .
31,,7~ !
27
27 .-
?<-;)
20'Y~.
33'-~,i,
33
28··07;,
20
33-- ff,)-
16·~'b
15-'1'';
52-Ii &
26--(,,3
17~~q'1
15 _~'yl_1
58- /J,(;;;15-";"" If
330" 710
18
18-u .
56-- 1
56-
57- 1
37-'JO
41-51-, (b
37~
q
40
42=,,1 (lC
41··'1,,&'
43-iC
57'- ,
\.,.
59 -, G~
59 ~11,~
~'"~
TSU
17'-':i,~
TSX'/'
TXH/'
3938 3638-'-')
40-'::}·'9
TXI""'~
TXL,/'"
TZE\\P'UFAJ
UFMJ
UFS\,,'
CDP
VLM'
VMA·
XECj
Contents by logic group on next page.
7 -I!J
49c-\\:';"
INDEX
TITLE
Arithmetic
CLA,CLS,CAL
CAP
ADD,SUB
ACL
LDQ
ENK
MPY, VLM, VMA
DVP,VDP
FAD, UFA, FSB, UFS
FMP,UFM
FDP
DFAD,DFSB
DFMP
DFDP
FIGURE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Store
STZ,STQ,STO,SLW
SLP
STA, STD, STL, TSL
SXA.,SXD
15
16
17
18
Character Handling
CCS
PCS
SAC
19
20
21
L()gical Operations
ORA
ANA
CAS
LAS
COM
20
22
23
24
25
Sign Alteration and Test
CHS,SSP
MSM,MSP
LBT,PBT
DCT
SWT
MIT,PLT
26
27
28
29
30
31
Index Register Loading
LXA,LXD,LAC,LDC
PAX, PDX, PAC, PDC
PXA,PXD
AXT
32
33
34
35
TITLE
FIGURE
Transfer
TXI
TIX,TNX
TXH,TXL
TSX
TZE,TNZ
TPL, TMI
TOV
TRA
36
37
38
39
40
41
42
43
Shift
LLS,LGL
LRS,LGR
ALS
ARS
RQL
44
45
46
47
48
Miscellaneous
XEC
HPR
TMT
49
50
51
Memory Protect
SPM
RPM
52
53
Miscellaneous Data Channel
ETTA
IOT
TCOA,TDOA
TRCA,TEFA
54
55
56
57
Trapping
STR
TRT,TRP
ENB
RCT,ICT
58
59
60
61
Clear and Add (CLA +0500)
TO MEMORY DATA REG
Replaces the contents of the accumulator (5, 1-35) with the contents of
the effective address.' Bit positions P and Q of the accumulator are set to
O. The contents of memory are unchanged.
Clear and Subtract (CLS +0502)
Replaces the contents of the accumulator (5, 1-35) with the negative of
the contents of the effective address. P and Q of the accumulator ore set
to O. The contents of memory are unchanged.
Clear and Add Logical Ward (CAL -0500)
Replaces the contents of the accumulator (P, 1-35) with the contents of
the effective address. The sign of the memory word goes to bit P of the
accumulator. Bits Sand Q of the accumulator are set to 0'5. The contents
of memory are unchanged.
INSTR COUNTER (IC)
CLA
21
NO
YES
CLS
35
CAL
ADDRESS REG (AR)
35
21
21
35
LS
(LA
CLS
CAL
TO
MAR
MUL TlPLIER - QUOTIENT REG (MQ)
INST
LEGEND
+0500 CLEAR AND ADD
ALPHA CODE,
-------...
1 CYCLE
-------.
E CYCLE
CYCLES,
CLA
-t{)500
SI
CLS, CLA
=======.7.
L CYCLE
-------------.
CONTROL
I, E
IF~TI
11B
Y
18 21
20
35
CAL
SEQUENCE NOTES,
THE C(AC) S, 1-35 ARE REPLACED WITH C(y). POSITIONS P AND Q OF AC
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
ARE SET TO ZERO.
C(y) ARE UNCHANGED.
INST
INST
+0502 CLEAR AND SUBTRACT
ALPHA CODE,
CYCLES,
CLS
"FIRST CELL DRIVER PULSE FOLLOWING THE INDICATED
TIMING LEVEL SETS THE RECEIVING REGISTER.
IF~T
+0502
SI
I, E
11 12
13
I
18-20 21
SEQUENCE NOTES,
THE NEG OF C(Y) REPLACES THE C(AC)S, 1-35.
POSITIONS P AND Q OF THE AC ARE SET TO ZERO.
THE C(y) ARE UNCHANGED.
ifSB(S)--+SR(S)
FIGURE I. CLA, CLS,CAL
-0500 CLEAR AND ADD LOGICAL WORD
ALPHA CODE,
CYCLES, __~I,_E____________________
CAL
Y
-0500
35
SI
11 12
13
18
20
21
35
SEQUENCE NOTES,
THE C(Y) REPLACE THE C(AC)p 1-35 THE 'SIGN OF Y APPEARS IN POSITION
P OF THE AC. POSITIONS SAND Q ARE SET TO ZEROS, C(Y) ARE UNCHANGED.
r,
!>P
P
O!p
P
I~ !
O!
I A LY
location
Switches
M ST RI
00000
00001
00002
00003
00004
00005
00006
OTCE
'
"T
~
i
I
00
E
I
00002
- 500 000
0
00002
707070707070
307070707070 01
I
I
00003
+020
000
0
00000
002000000000
307070707070 01
I
E
00001
- 500 000
0
00005
450000000005
307070707070 01
-
TO MEMORY DATA REG
Clear and Add Losical Word with Pority (CAP -1510)
Replaces the contents of bits 5, P, 1-35 of the accumulator with bits C,
5,1-35 of the effective address. The sign of the memory location and the
parity bit go to bits P ana S, respectively I of the accumulator. Accumulator Q is reset to O. The contents of the effective address are not checked
for parity and do not cause a parity trap tequest. The contents of memory
are unchanged.
INSTR COUNTER (IC)
I TIME
POD 50
PR 6
21
35
I
E TIME
02.15.34.(3A)
ADDRESS REG (AR)
I
3
21
21
35
35
BLOCK PARITY
CHECK
1506
02.05.45(51)
I
1
I
SB (S-35) TO SR
E3DI'
02.12.01. (4C,4F)
MDR 36 TO
SR 36
E3Dl
02.05.36. (IC,31)
I
I
1
I
I
FIGURE 2. CAP
8
'1st CELL DRIVER PULSE
FOLLOWING INDICATED
TIMING LEVEL SETS THE
RECEIVING REGISTER
INST
CLEAR AND ADD LOGICAL WORD WITH PARITY
ALPHA CODE,
--------------11..
1 CYCLE
------__
E CYCLE
•
-------------.
I
SR 36 TO AC S
ESDI'
02.02.00 (4A)
XFERS INCLUDE All BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
_I~,_E______~_____________
Y
-1510
L CYCLE
CONTROL
CYCLES,
CAP
S1
SR (S-35) TO AD
(P-35)
E7D2
02.12.08. (4A,4G)
AD (Q-35) TO AC
(Q-35)
ESDI'
02.12.20. (41)
MULTIPLIER-QUOTIENT REG (MQ)
LEG E NO
END OP
E306
02.15.35. (3C)
1
TO
MAR
11 12
13
IS
20
21
35
SEQUENCE NOTES,
THE C(Ylc,S,I-35 REPLACE THE C(AC)S,p 1-35. THE PARITY BIT OF LOC Y
REPLACES S OF THE AC. AC(Q) IS SET T6 A ZERO.
Ao AI A2 A. A. A. A( AI A2 A. A. A. Ao AI A. A. A. A. Ao A I A2 A. A. A. Ao AI A2 A. A. A. Ao AI A2 A. A. A. Ao AI A2 A. A. A.
fl
ct
Il
ct
ct
Il
ct
1 f R]v
1 l TE
PR p~
(0 .1 .3 .1
GtE
I AS ER 1
~
AS ER E
( E Rl
ct E Rl
Il L TE
ct
fJ
E R
l T
Iv
III
E RY
jt..T
jA.T
: E. Rl
1 E RY
h
TE
Il T
ME~ EL
(0 .1 .5 .1
"'"
"'" "'"
A
M R
C L· PR .p S
02.0
.~.I
E AR Y·I'>I............I-I
PR ~-
bl cks lip rit C ec
II
(02.0!.3 .1)
U
TEl,
o 5) -+';1-1..........-1
f'H[--
END (P
E"P
(0 .1 .3 .1)
A4.5 I
ICI L
R P S· ~"'" _
(2. 5. 5. )
P G
SR", A P
(
.1 .C8.1
E II.T ·A 0 --
P 0 0"/::;","","
E IA E·II 2
S 3c~·,
C L·pR .p S+-- "'"
P 61-1
E ~ E· 20'1'
2.12. 0.1)
SR':jr< A 1_ 5 (0.1 .0.1
SR~ol+
C
(0 .O.C .1
Pc OJ;o·b~
iLTfA21
PC 0
10· PR~· R S
gn -
9
FROM MDR
FROM MDR
(ADD,
NO
FROM MDR
YES
Add (ADD +0400)
Algebraically odds the contents of the effective address to the contents
of the accumulator. The resulting sum is placed in the accumulator. The
contents of memory ore unchanged. Numbers of the some magnitude but
different signs give a resultant sign the same as the sign of the original
12
1
accumulator.
1
1
Subtract (SUB +0402)
Algebraically subtracts the contents of the effective address from the contents
of the accumulator. The difference replaces the contents of the accumulator.
1
I
I
I
I
The contents of memory are unchanged.
t
I
10
I
ADDER (AD)
Ip I
I
4*
NO
13
(0::35)
(0-35)
(0-35)
1
1
I
1
1
I
ACCUMULATOR REG (A C)
JI
14
I
1
1
1
1
0-35)
ACCUMULATOR REG (A C)
UNLIKE SIGNS, AC ~ SR
LIKE SIGNS
UNLIKE SIGNS,
*4 AC OVFL TGR SET IF CARRY INTO P ON ADD, LIKE SIGNS
5R
> AC
* 5. C(AC)0_35 AND HOT I TO ADDER (CI 35)
FROM MDR.
YES
SR )AC
NO
AC~ SR
(SUM IS IN COMP
FORM)
INST
+0400 ADD
ALPHA CODE, _A_D_D_ _ _ _ _ _ CYCLES, _I:...,_E_ _ _ _ _ _ _ _ __
Y
+0400
SI
SEOUENCE
II 12
13
18 21
20
35
t~OTES,
THE C(Y) ARE ALGEBRAICALLY ADDED TO C(AC). THE RESULTING SUM IS
PLACED IN THE AC. C(Y) ARE UNCHANGED. NUMBERS OF THE SAME MAGNITUDE BUT DIFFERENT SIGNS GIVE RESULTANT SIGN OF THE ORIGINAL AC.
,2
TO ADDER
INST
+D402 SUBTRACT
LEGEND
ALPHA CODE,
INSTRUCTION
COMPLETE
*FIRST CELL DRIVER PULSE FOLLOWING THEINDICATED
TIMING LEVEL SETS THE RECEIVING REGISTER.
SUB
CYCLES,
I, E
I CYCLE
+0402
-------.
E CYCLE
SI
Y
IFf%aTI
11 12
13
IB
20
21
35
L CYCLE
-------------.
CONTROL
FIGURE 3. ADD,SUB
*1 C(SB)S--+SRS'
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
10
REMAINDER OF SUB INSTRUCTION IS THE SAME AS "ADD".
OVERFLOW POSSIBLE WHEN SUBTRACTING VALUES WITH UNLIKE SIGNS.
location
Switches
Ao AI A. A, A. A. Ac AI A. A, A. A. Ao AI A. A, A. A. AoAI A. A, A. A. Ao AJ A.A, A.A. Ao AI A. A, A. A. AoAI A.A, A4 A.
NC 0
45D
IE RL
I LA E
00000
00001
00002
00003
00004
00005
00006
,,-" EA L~'
2[ I
Nle P Tf"R
P ON
I
"\
~.
(0 TO E
{ I~-
0
1 .3<.1
Iw ST
AWl
A TER E
~
~~
~~ S~
ER ~ f-I
PD
AIR- ~~ AR (0 .1 .5 .1)
:6IW
E~
~~
"
( 2. 10. 0.1)
T U S k- SR
"
cm P Bs
~~ )~
3D
e mp SB ...... SR-
E AT •
ADD SU "-
""'
'E A
f+
( 2. pl. 00.1)
I~V RT I( N B
( 2. pl. 00.1)
E~D
)1- ~
POD 4P',
E' 4D I'"'" I-
PO 4
SU
E AT 'A D
~I-
S 1-
~
., D
Cp~ A Q p.
_-:;r
A
ApC; .p l-
is ~~
eo~
A Q p. -):-1 A
.
~1
C0F~
2
o 40
SU Q
E AT .~ 2D
POD4
E
AT'~
S '1D
.....-
PO)4
E AT 'A2Dl
ig IA ikE
A'-Q p.
~~ I;:::
"""
A D+ )4(
FQ[ 40
Pu
AIlD 'i>' '8
SUB P 8
l-
-r
A
SRf---4 AC s
15 "AD
S 1- 35 f+! D
~- ~
POp4 S~ "
I'-D 1
o er ti n
'-1(j
I.....'X
c;~?
Q;;'~
Y
"{'
E
00001
t500
000
o
00005
050000000005
000000000000 00
I
00001
t500
000
o
0000 I
00000000000 I
00000000000
100
I
E
00002
400
000
o I 00006
o·
00000000000 I
)0
E
I
00002
>400
000
o I 00002
I
I
00003
t020
000
o
,:t
0 /; jl!lllllll/
8'~~ A~ ?~f
"{'~
E
~
)0
,77777777777
~
00000
002000000000
000000000000 ~I
J?
0::5
./
~
'"
~
0
~&
~
§ J9
0
#~<8'°/(j1ll/. ~n,
q;:
y
<)
G
~
0,.
I
I
I
I
0
0
I
E
00001
+500
000
o
00005
050000000005
000000000000
I
( 2. 12.08.1)
E
I
00001
+500
000
o
0000 I
00000000000 I
000000000000
po
I
( 2. 12.11.1)
I
E
00002
+400
000
o
00006
040000000006
000000000000
0
I
Location
Switches
( 2. 12.11.1)
00000
00001
00002
00003
00004
00005
00006
( 2. 12.12. 1)
POD4 S • l- IA"C; .p 1E AT .~ 1D .....ig I A ik
-...;
~
~
Q,
~ ~
( 2. 12.20.1)
PCp4 S (
l- I- e 3!
E LA IE' 11Y
P D4 S
E L~ TE'
""'::0
'-'
o~
,,~~
~,<";y"C
I
DC 40 SU N '-1- IE A E' H 2/
Q car y
<
,?
I
Q co ry
ig ,U 11
g
~
p~ ~~f f~ i8f0 ~f
tv
J
CONSOLE INDICATORS
( 2. 15.35.1)
0
'nnl
ell
j'i«i~0.
~
R,
S~:1 :~
PO 4
E A E' 4D
~
000000 000001
377777 777777
I
;-
EN SE E( T ( 2. 2. O. )
P D XO
N
I AT
T
E
l- I-
050000 000005
040000 000006
002000 000000
'"
AT
IE RY
. E, RL
"
00005
00006
00000
Pottern
Pattern
E RY
AR Y
IlLA E
I--' ~
Octal Equiv
LA E
~
~
eLA
ADD
TRA
Address
RI
a'A'
:~ ~
_..
I>E RL
E RL
M ST R
E RL .~ OD
M ST R
OD
E
To
Inst
AD ~~e
0\ T R
( 2. 12.10.1)
( 2. 12.25.1)
lnst
Tog
CLA
SUB
TRA
Addre;ss
Octal Equiv
00005
00006
00000
050000 000005
040200 000006
002000 000000
000000 000001
377777 777777
Pattern
Pattern
( 2. 12.10.1)
Subtract (SUBL
I
( 2. 12.08.1)
( 2. 12. 20. 1)
( 2. 10.41.1)
;ii«i~~~~ /t:! I/:J /;l;tl!lllllll/
E
00001
+500
000
o
00005
050000000005
E
I
00001
+500
000
o
00001
00000000000 I
00000000000 I
00
I
E
00002
+402
000
o
00006
040200000006
00000000000 I
pO
I
I
CONSOLE INDICATORS
+ Ol1P2
000000000000 00
E
I
00002
+402
000
o
00002
777777777777
77777777777.
0
I
I
I
I
00003
+020
000
o
00000
002000000000
777777777776
pO
0
0
I
E
00001
t500
000
o
00005
050000000005
777777777776
0
0
0
11
TO MEMORY DATA REG
Add and Carry Logical Word (ACL +0361)
Adds the contents of the memory location (5, 1-35) to the contents of
the accumulator (P 11-35). The resultant sum replaces the contents of
the accumulator (P I 1-35). The sign bit of the memory word is added
to accumulator P bit; a carry out of P is added beck to accumulotor
35. Accumulator 5 and Q are not affected.
INSTR COUNTER (IC)
21
'SR (S-35) TO
'AD (P-35)
E3 (06)
35
•
AC (Q-35) TO
AD (Q-35)
t:J,(tI6j','>'
02, Hl.OO.l
t
!,.
INDEX REGS (XR)
ADDER (AD)
02.12.10.1 (4G)
02.12.08.1 (4C,3B)
XR 1
XR 2
ADDRESS REG (AR)
•
YES
1
XR 4
I I 1'3
1HOT 1
II
L _ _ _ _ _ _ ~-------~
NO
21
I
35
2
l"
'\
\)4
I)
TO
MAR
I
21
1
1(Q-35)
11
1
1
12
1
35
14
1
ACCUMULATOR REG (A C)
MULTIPLIER-QUOTIENT REG (MQ)
AD (P-35) TO AC
AND RESTORE
AC (Q)
E8 (01)'
02.12.20.1 J?Ft
* FIRST CELL DRIVER PULSE FO LLOWING THE INDICATED TIMING LEVEL
SETS THE RECEIVING REGISTER.
INST
LEGEND
+0361 ADD AND CARRY LOGICAL WORD
ALPHA CODE,
------------.~..
1 CYCLE
-------.
E CYCLE
ACL
-------
L CYCLE
-------------...
CONTROL
XFERS INCLUDE All BITS CONTAINED IN
THE SMAllER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
12
____________________
Y
11 12
13
18 21
20
35
SEQUENCE NOTES,
THE C (Y) ARE ADDED TO THE C (Ae) P 1-35 THE RESULTANT SUM REPLACES
THE C (Ae) P 1-35. THE SIGN OF Y IS' ADD~D TO POSITION P OF THE AC.
A CARRY FROM AC(P) IS ADDED TO AD(35). POS SAND Q OF AC ARE NOT
AFFECTED. C(y) ARE UNCHANGED.
*3 P CARRY_CI35.
FIGURE 4. ACL
~I,~E
+0361
SI
=======:;.~
CYCLES,
Location
Switches
Ao AI A. A, A4 As Ac AI A. A, A. As Ao AI A. A, A. A. AoAI A. A, A4 A. Ao AJ A. A, A. A. Ao AI A. A, A4 A. AoAI A2 A, A4 A.
~
~
~
'"
a
"'~
~
Inst
CAL
ACL
TRA
00000
00001
00002
00003
00004
00005
00006
I A LY
I LA E
Tag
Address
Octal Equiv,.
00005
00006
00000
450000 000005
036100 000006
002000 000000
525252 525252
252525 252525
Pattern
Pattern
P Ot-<
PO'
PO'
PO'
~ r~
~V
G
Tin
M ST RI
M S ER E
5DlE~
c E R Iv
RL
Add and Carry Loaical Word (Ar:T.I
c U TE
'" JAT
~
~
E RL
~
,
L TE
I
Ep RL
~
L TE
0;£~id~ ~' t;0
J)
~
l;
o:§
:::
~f
AJJ
;/?:0
~(j
H Id the co te ts ftC
~
C S·
R Iv
.
o
A PI
S C S • N tP ,6fr-
('P 02 02 37)
S S. T:3~
I~
SR .1 35 (0 .1 .0 .1
f---"f---
UTE
"C
SR,_ -----0
PPp
02 12 01 1)
P
fJ2 12 01 I)
00-
IA- E
I
f\c L-I--
<
0
t;"
q,-
I
E AT
S?<
~
lEA L
E RL
CONSOLE INDICATORS
v
I
E
"8
00001
~
ci5 (;:,f
¢;::["0
.?
e-;8
0
J......'f
~
$
cJ
T
- 500
000
o
00005
'-0
~~
G$~:Y
t;8..:.
~0
,
~
~~
~
~ Q.
(55 Q
(]~c}J
v"-
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~
&
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000
o
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525252525252
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o
00006
036100000006
125252525252 01
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I
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361
000
o
00002
252525252525
377777777777 01
1
I
I
00003
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000
o
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002000000000
377777777777 01
T
F:
00001
- 500
000
o
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450000000005
377777777777 01
U
UTE
C ,." ~
SR ,-,; ",A 1- 5
1-3
["\,
AC Q. ---:ji-y
V
L-fE
AC L· ~
Pc rr
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D ).
-3 (0 .1 f·
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(02.12 1.1)
C 35
E~ D DP
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ELA E.
;~ 1- ~I-
Dp ra io
r~
AI p.
1-:3J--.
C p. _
nl + 03 1
PC D 6 R \
13
Load MQ (LDQ +0560)
TO MEMORY DATA REG
The contents of the specified memory location to the MQ register (5,1-35).
The contents of memory are unchanged.
'FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
2
21
--------------,
I
I
I
INSTR COUNTER (IC)
I
I
I
I
I
35
L.... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,
I
I
I
I
ADDER (AD)
I
ADDRESS REG (AR)
21
I
I
21
I
I
I
IL _____ ,
35
35
I
IL __
TO
MAR
ACCUMULATOR REG (A C)
INST
LEGEND
-Hl560
ALPHA CODE:
- - - - - -.......
I CYCLE
------__
E CYCLE
LOADMQ
LDQ
-Hl56O
SI
L CYCLE
-------------.
CONTROL
CYCLES:
Id~%~b I
1112
13
18 21
20
I, E
Y
35
SEQUENCE NOTES:
THE C(Y) IS LOADED INTO THE MQ. THE C(y) ARE UNCHANGED.
XFERS INCLUDE ALL 81TS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
FIGURE5. LDQ
14
Location
Ao AI A2 A, A4 A. Ao AI A2A, A. A. Ao AI A2A, A. A. AoAI A2 A, A.A. Ao AI A2A, A4 A. Ao AI A2 A, A4 As AoAI A2 A, A.A.
f>:-
~
a
a.
~
a
$
E RL
Switches
Inst
00000
00001
00002
00003
00004
00005
00006
LDQ
LDQ
TRA
Tag
Address
Octal Equiv
00005
00006
00000
056000 000005
056000 000006
002000 000000
777777 777777
Pattern
Pattern
000000 000000
I L T
PR p~
pry :0.
G
PO' 'I.':>
PO'
T
E
t?V
PR
A TE
~j
sT R I
t>
AR Y
E
a AR Y
a UTE
MO
'- LATE
I
$ EA L
E RL
t
$! UTE
L TE
I AR Y
E E.A L
-r.- ::=
E RL
i_
-I--
...
sB .1
"35-'1
E .A E·
I~ ~H
X·
Et--D
c-
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c., (j
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v:
Q;:'
~
v: ~'v:
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00001
+560
000
o
00005
056000000005
000000000000
E
I
00001
560
000
o
00001
777777777777
777777777777
E
00002
+560
000
o
00006
056000000006
777777777777
E
I
00002
+560
000
o
00002
000000000000
000000000000
I
I
00003
+020
000
o
00000
002000000000
000000000000
,,"'<
-...:: {:I
Q;
v:
Q
G
~
0,
0,
~
0
~
-f"I
NDC P GR
L TE
DC • r- L-- ::-5Dfi- f-
~Q
"
1
(0 .1 .3 .1
t 5( 1 f-
pp ra io
U
I
(C .1 • 1.1
5 s. -3
CONSOLE INDICATORS
l~i~i#tj,;~~ /;}#II~~ /;/1,liliiii/
s
I L TE
E AT
IPii 7·A 1f'Dl
',no'
ARLY
'.A Dl
sR I:]
35 M
5'1-
( 2. 2. 6. )
LPQ + 05 0
pop
6
15
Enter Keys (ENK +0760 .•• 0004)
Places the contents of the console word bank keys into the MQ register.
Address modification may change the operation.
I TIME
POD 76,760 NULL
UA4
02.04.07(3G)
02.04.40(3F)
02.04.42(2E)
FIGURE 6. ENK
16
'F IRST CELL DRIVER PULSE
FOLLOWING THE INDICATED
TIMING LEVEL SETS THE
RECEIVING REGISTER
WORD BANK
AoAI A. A. A. A. AoAI A.A. A. A. AoAI A.A. A. A. AoAI A. A. A. A. AoA.I A.A. A.A. AoAI A. A. A. A. AoAI A.A. A. A.
TO MEMORY DATA REG
~A
" E
~
E I
Rl
01
01
AS ER I
A lY
LTE
AT
~
E.I Rl
AR Y
/l ~'E
/l
II l
IL T
E
0
P~
N
60 NL II b2. 442 1)
PCD 6' 0
IE R •
A3
35
0
~- S (0 .1 .0 1.1
:::::. ~
1--
I l te
TE
IE RY
1 AR Y
INSTR COUNTER ( IC)
l)
-
R "JD
2.12.
pa.1l
A4 3 PO)
I l te
A5 1
'-..
1--1-
ADDRESS REG (AR)
28
U
35
21
21
35
-
35
I l te
I(f' '1"51:
P D
GC
TO
MAR
~
.*.
7.1)
4 (0 .0 •
•1
Ai-' S (C
Gp 0
M ST R
blo k.
E
EJRl
LJ E
ute
ACCUMULATOR REG (AC)
0
0
I- I--
-
I-- t::
Ef-lD 0
(0 .1 .3 .1
N '0 P T3R
((~.
INST
lEGEND
1 CYCLE
------__
E CYCLE
(0 .1 ~. 1.)
S1
(C .1 l2.c I.)
4
-Kl760
11
18-20
24
CONTROL
(( .1 ~. 6. )
SEQUENCE NOTES,
MAY CHANGE THE INSTRUCTION ITSELF.
1:- p
~~
C 11~ ~
O·
~,
N + 07bO
III
En '"
~~D
TE K YS
--
P E S ~:
ey •
::::-
SB .... SR
e •
--::::
AC'D t- ~
En
E~
~
35
THE C(WORD BANK) IS PLACED IN THE C(MQ) , ADDRESS MODIFICATION
XFERS INCLUDE All BITS CONTAINED IN
THE SMAllER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED,
U 4·
I arl
~lD
l CYCLE
~~--~--~~~~~~.
2. )
ENTER KEYS
ALPHA CODE, ...,:E:.;N.:.:,K_ _ _ _ _ CYCLES, _.;.:I,_l"--_ _ _ _ _ _ __
-------tl...
~.
-r-
-
SR'" ~C
7[ OJ
17
Variable-Length Multiply (VLM +0204)
Multiplies the contents of the specified memory location (multiplicand) by
the C low-order bits of the MQ to produce a 35-plus-C bit product. C denotes the number of bits in the MQ to be used as the multiplier indicated
by bits 12-17 in the instruction word. The 35 most significant bits of the
product replace the contents of the accumulatol (1-35), and the C least
significant bits replace the contents of the MQ register (I-C). Accumulator positions Q and P are cleared. The remaining 35 minus C positions
of the MQ register contain the original 35 minus C high-order bits of the
MQ register. The signs of the occumulator and the MQ register are set to
the algebraic sign of the product.
If C is 0, the instruction is interpreted as no-operation and the computer
proceeds to the next instruction in sequence, leaving the accumulator unchanged.
If C is not O,but the contents of the memory location are 0, the contents
of the accumulator and the MQ register are cleared.
""vI
Variable-Length Multiply and Accumulate (VMA -1204)
VMA is similar to VLM except that the contents of the accumulator (Q, P,
1-35) are not cleared before the multiplication process begins. This results
i'n adding the 35-plus-C bit product onto the original contents of the accumulotor (Q, P, 1-35). If accumulator bit positions P and Q both originally concontained 1 's, a carry may be lost during the accumulation and the overflow
indicator is not turned on. The C least significant bits of the result replace
the contents of MQ I-C. The 36 most significant bits replace the contents
of the accumulator (P, 1-35), Accumulator bit position Q is cleared. The
remaining 35 minus C positions of the MQ contain the originol 35 minus C
high-order bits. The signs of the accumulator and MQ are set according
to the algebraic sign of the product.
If C is 0, the instruction is interpreted as no-operation and the computer
proceeds to the next instruction in sequence, leaving the accumulator unchanged.
I
~!tiii~~ ~ '/I ~ ~
~I-....
~0',§
.1-0'
u
u;}j
~ ,-E
E
I
I
E
MY PY
LL
E Rl
.
/
AS 3
MPYG TE •
qat
l3 3
--
Y"
l
ar
AD 3 - -~ I-
lC D3 (e .1 ~. 15.1
A'103 ~
( 2.1 • 5.1
--
f'lP E
lO 3
C D
( 2. O. 1. )
MY DC R
Re et
wi h
~ iJ~
Eo A5Pl
~
5C N T [."
T R Pf .M 3 ,-
:-"
G
0
P
f
P A lY
(12. o. 0.1l
LDQ
MPY
TRA
00005
PaUern
Pattern
00006
-~~
I-
--
~
N'l
!
- ......
~
~I--
8
° ~ff
/;?§~~"'l
I-....~
( 2. 2. 1. )
~P
( 2. 2. 8.1)
5T P C
/-
-
A D T '-.
l D7
MY ar! /
M Y fat
~"
H
( 2. 2. 2.1)
M
l IN E
A
A
o
'r
D 0
00001
+560
000
a
00005
056000000005
000000000000 00
000000000000
00001
+560
000
a
00001
400000777777
000000000000 00
400000777777
00006
020000000006
000000000000 00
400000777777
a
00006
000000777777
400000000000 00
400000777777
2
0000
+lOO
040
a
00006
000000777777
400000677777 00
440000077777
L 3
0000
+lOO
035
a
00006
000000777777
4000G0767777 00
404000007777
L 3
L4
OOOOl
+200
032
a
00006
000000777777
400000716777 00
400400000777
Address
Octal Equiv
L 4)
L(5)
OOOOl
+200
027
a
00006
000000777777
400000717617 00
400040000077
00005
00006
00000
056000 000005
020000 000006
002000 000000
Ll5)
Llo)
00002
+200
024
a
00006
000000777777
400000777767 00
400004000007
7
00002
+200
021
a
00006
000000771777
400000777776 00
400000400000
8
00002
+200
0)3
a
00006
000000771777
400000007777
00
770000004000
00002
+200
OOS
a
0000,
000000777777
00002
+200
000
a
00006
000000771777
400000 777777
000000 777777
'.101
.rAl
---
10'
\
Rlpl T ( 2. 2. 7.1)
AD RT AC/"-
NQ
o
3
1
/
~
1
0
o 0
-
1 0
~
1
-~
0
~
DD RT
00
717776000001
+200
000
a
00002
000000777777
I
I
00003
+020
000
a
00000
002000000000
400000000001
00
777770000QOJ
I
E
00001
+560
000
a
00005
056000000005
400000000001
00
777776000001
E
I
00001
+
a
000
a
00001
400000777777
40000000000
100
I
E
00002
+200
000
a
00006
020000000000
40000000000
100
772
~
r---
I-
enllth
ultiplv (VLML
CONSOlE INDICATORS
~!tiii~0 ~ ~
Q
'-<-J;p
.:$
uQ;;-
4:
~<
!
~jl
~
~
S
0
,-~t
~
4:
E
00001
+560 000
a
00005
056000000005
000000000000 00
000000000000
I
00001
+560 000
a
00001
000000777771
000000000000 00
000000777777
E
00002
+204
000
a
00005
020422000005
000000000000 00
000000777777
16
1C
T.11\
00002
+204
022
0
00005
000000777777
000000000000 00
000000777777
16
~(1)
L(2)
00002
+204
017
a
00005
000000777777
000000677777 00
040000077777
10
L 3
00002
+204 014
a
00005
000000777777
000000767777 00
004000007777
10
00002
+20'
10
00005
00000077nn
\000077(,777 00
Octal Equiv
.m
01
056000 000005
020422 000005
w
,
00002
+204 000
a
00005
000000777777
000000777677 00
000040000077
10
00000
002000 000000
L 5
Lo
00002
+204 003
a
00005
000000777777
000000777767 00
000004000007
10
L 0
L7
00002
+204
000
a
00005
000000777777
000000777776 00
000000400000
16
L7
I
00002
+204
000
a
00002
000000777777
000000777776 00
000000400000
10
00003
+020 000
a
00000
002000000000
000000771776 00
000000400000
P - VLM VM
i:
-
00040000077
00005
00005
000000 m777
0~~
~~t l~~
E
L2
Inst
&
I
(C~22)
MP
400000000001
00002
ct1l" ~~p f~d;~~
MY
G TE
1
777776000001
I
i:
P E rly
~~
00
L 10
MC 3
SHifT M
10
40000000000 I
I
l D3 'NPY La
-
50
)77 100
I'
~
I-....'<:f"
a
7
~(j
f'.!::2'~
000
I- ~ -I-
'0"5
~Q
043
-
I-
""Fa P s l
pDO
Wi Q'
SHifT AC RI
~
~
.i?'
q,;
~
&
~ ~
V
1M Gi'T (0 .1 .1.1
-
~
Gi"T
(j --!
~~'
Q..
" (3
v,
AC R A(
~
rY~
$'
.:f/?l'
+200
-
I-
%S
~
~
0'~
sJ" t:; P>'-
Vj
;:;
+lOO
Ci"
t;l
l D3
C D
~
TE
Inst
00000
00001
00002
00003
00004
Tag
i!j
0000
"I
Location
Switches
~
§
0".
I-....
0000
TE
E fAT
f
~O
,Y
1
Ao AI A2 A3 A4 A5 Ac AI A2A3 A4 A, Ao AJ Az A, A. A, AoAI A2 A3 A4 A'J Ao AJ A2 A3 A4 A5 Ao AI A2 A3 A4A'J Ao Al A2 A3 A4A'J
2
~
J
J' ~<54:
f!j
Q
'-<-J f!j
E
0
CONSOlE INDICATORS
I
E
00001
+560 000
0
00005
056000000005
000000777776 00
000000400000
E
T
00001
+560 000
a
00001
000000777777
000000777776 00
000000717777
E
00002
+204 000
a
OOOO!
020472000005
000000777776 00
000000777777
10_
19
Divide or Proceed (DVP +0221)
Treats the contents of the accumulator (0, P, 1-35) and the coritents of the
MQ register 0-35) as a 70-bit dividend, plus sign, and the contents of
the memory location as a 35-bit divisor. If the memory word (divisor) is
greater than the accumulator (high-order half of the dividend),division
occurs. A 35-bit quotient replaces the contents of the MQ (1-35) and the
remainder replaces the contents of the accumulator 0-35). The MQ sign
is the algebraic sign of the quotient, and the accumulator sign is the sign
of the dividend. If the memory word (divisor) is less than or equal to the
accumulator (high-order half of the dividend), division does not occur
and the divide-check indicator is turned oni the computer proceeds to the
next instruction.
Variable-Length Divide or Proceed (VDP +0225)
Variable divide is the some as straight divide (DVP) except that bits 12-17
of the instruction word determine the number of partial divisions that are
to occur. A C-Iength quotient (C determined by instruction word bits
12-17) with a sign replaces the C low-order positions of the MQ. The remainder replaces the contents of accumulator 1-35 and the 35 minus C
high-order positions of the MO. Initially, C rather than 438 is placed
in the shift counter. If C is 0, the instruction is interpreted as no-operation and the computer proceeds directly to the next instruction in sequence.
o
I
2
3 4
5 0
I
E A
234 5 0
I
2 3 4 501
2 3 4 501
2 3 450
I
2 3
450
I
234 5
Y
YES
L TE
LEA L
L TE
L AR Y
k~
0P -[ IVk~.I2- Ztj+
c!"'" l'"
E AR y · t 2
0
ET',L
.~
.
,2i11"-
I" ,-D V·
NO
E
D( I
1-+
C
P -DV' E"L' R7 _~I"'; S
1""
2[ r"
HIID .E EA LY
L LA
(0.1 '.( )
2/ 6/
7
(2-7) (0
02 12 3
1.3
lEA LY
A~'-~~
E A y. A3pl
jl5)
A
t-~ - )
I--s
A I..... A
E LA E 'A4 I' CeM Pll-t-~
L TE
(2.2. I)
(S 35
(2. 2. I)
(2. 2.10)
E~'~'NCNT,-~~~M(~~0
~~f'.o (0.1 .0)
SHIFT AC (P-35)
TOAC (Q-34) AND
MQ (2-35) TO MQ
(1-34)
L2 (DI) L5 (DI)'
02. 12.23. 1(3C, 3D)
02.12.28.1(3D,3E)
~ or G
0 L 02 15 34
o
TP E 'E Lt E
jAv '-1 IV T~ R 02. 10.20)
E LA E'/AP - IV SC N T ' .II
I--+-~""+-""H~~:.r-+-FFF'!-+-+~
A
-IfA!
E~O OPT( R'I'Q[ I
2. 2, 0
SR=", D J9 ,I .om
D P flD.
LEAl
NO
R SE S --"2. 2.Bn
tiET MrS (0 • I .7)
DiY· COO E JAT • ID' iCARf-~
DI 'S:
~PT O· L TE'A DI.( Cl"tF~' Q M N S 02 1271
R- C ut-tD V· COO LAY A DI +
IV CN T ·LLAE·A5
Q LT DI
L L T ·D V· C+ • ~~
'FIRST CELL DRIVE~ PULSE FOLLOWING THE INDICATED
TiMING LEVEL SETS THE RECEIVING REGISTER.
D
• c~
,
I-
1-1It-~~r-
r-
•
+ I-j---r-I=I-
E ~L'
2[ I
~I~
-
) ~ 12 23~
!vtQ~~)t--~
I
4)~
C(fOii)
Jl
FIGURE 8. DVP,VDP
20
D
02~
A
d'"
, Py
P 01
+02
~ 12.38)_
S
~ E ~'~
DVpAE'LEJARy.IQ~'AD + 4
D~
I
M< t;!lt-- C~ (2, ~)
2~)
II-
02.10,22
( - b)-~I C 0212.20 .
/""".
DI • C('A DI'E
T _~p
P 02 15 35
1 AR y. AI 2 DI p_ DP
'i'""l'g:jiiiooD;-jo'!lD 0 1 II
1 AR Y A2 1 C( M
~~I"';
DV
A
(2. 2. 0)
Location
Switches
00000
00001
00002
00003
00004
00005
00006
Tag
Inst
CLA
LDQ
DVP
TRA
Address
Octal Equiv
00004
00005
00006
00000
050000
056000
022100
002000
000000
007777
000000
Pattern
Pattern
Pattern
Location
Switches
00000
00001
00002
000004
000005
000006
000000
000000
600001
077777
00003
00004
00005
00006
Divide or Proceed DVP
I
Variab
I
CONSOLE INDICATORS
Tag
Inst
CLA
LDQ
VDP
(C=24)
TRA
Address
Octal Equiv
00004
00005
00006
050000 000000
056000 000005
022524 000006
00000
002000 000000
000000 000000
00m7600001
400000 077777
Pattern
Pattern
Pattern
L no'}; Divide" Prn,eed 'VDPI
I
CONSOLE INDICATORS
jiii1J{~~# /1 II~} /;/;£liliiii/ Vtii1~~ ~~ J<#} /;/;/;liliiii/
"',f?
~
+500 1000
o
0000. 05000000000.
000000000000
00
000000000000
1
E
00001
+500 000
0
00004
050000000004
000000000000 00
000000000000
0000.
+500 000
0
00001 1000000000000
000000000000
00
000000000000
E
I
0000
+500 000
o
00001
000000000000
000000000000 00
000000000000
1
E
10000?
>5(,0 1000
0
I 00005
)5
00
E
T
10000'
>%0 1000
0
I nooo,
'"
100001
1000
00002
+560 1000
o
00005
00002
+560 1000
0
00002 100777760000
00
0000.
+2>
o
00001
00
L(I)
00003
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21
Floating Add (FAD +0300)
Adds the floating-point number in the specified memory location to the
accumulator. The most significant portions of the result appear as a normalized floating-point number in the accumulator. The least significant portion of the result appears in the MQ register as a floating-point number
with a characteristic 338 less than the a"ccumulator characteristic. The signs
of the accumulator and the MQ are set to the sign of the larger factor. The
sum in the accumulator and MQ is always normal.ized whether the original
factors are normalized or not. If the contents of the accumulator (1-35)
contain OIS, the FAD instruction may be used to normalize an unnormalized
floating-point number.
Unnormalized Floating Add (UFA -0300)
Same as FAD except that the sum is not normalized.
Floating Subtract (FSB +0302)
Algebraically subtracts the floating-point number in the specified memory
location from the floating-point number in the accumulator. The results
are normalized.
TC14
OBJECTIVE, STEP 4 ~
SUBTRACT FRACTIONS
TC13
OBJECTIVE, STEP 3 (]§I)
ADD FRACTIONS
Unnormalized Floating Subtract (UFS -0302)
Same as FSB except that the difference is not normalized.
'FIRST CELL DRIVER PULSE FOLLOWING THE INDICATED
TIMING LEVEL SETS THE RECEIVING REGISTER.
YES
NO
FAD, UFA
NO
OBJECTIVES, STEP I (TClI)
RESET MQ
(S, 1-35)
E5 (01)'
02.20.30.1 (JA)
02.15.21.1 (SE)
(SR
1. RESET MQ REG ISTER
2. PLACE REGISTER WITH
LARGEST CHARACTERISTIC
IN THE STORAGE
REGISTER AND CHARACTER DIFFERENCE IN
SHIFT COUNTER IF
LESS THAN 100S '
NO
> AC)
YES
(CHARACT[:R==.
DIFFEREN<::E
> 100)INO
AD TO AC (Q-35)
(RESEn
E6 (01)'
02.20.09.1 (3H)
02.15.22.1 (
)
._
TC1G.
OBJECTIVE, STEP 6 ~
NORMALIZE FRACTIONS
- - - --- --- ---olliCTNE~ 2(iU2i - - - YES
1. EQUALIZE FRACTIONS
2. DETERMINE ADD OR SUBTRACT
"
NO
CHARACTER
DIFFERENCE
100
=
\
NO
CHARACTER
AD (9-35 TO A
DIFFERENCE ' -_ _ _-oJ
(RESET AC FRACTION)
100
L2 (01)'
02.20.63.1 (SA)
02,12,20,1
>
YES
SHIFT MQ (9-35)"
AC (9-35) RIGHT
EACH CLOCK
PULSE
02.20.11.1 i4E)
(SUB) NO
TURN ON FPl
TGR
A3 (01)
02.20.07.1 (4B)
leIISP END oP
A4 (01)
02.20.09 (20)
FIGURE 9. FAD,UFA,FSB,UFS
22
SHIFT AC (9-35).
MQ (9-35) LEFT
CLOCK RATE
02.20.20.1 (2H)
02.15.25.1 (3G)
STEP SC CLOCK
RATE
02.20.12.1 (21)
02.12.37.1 (3F)
I'S AD (Q, P,
1 &2)
02.20.12.1 (21)
02.20.66,1
(2A, 2B, 2C)
SClO AD (3-8)
02.20.12.1 (2H)
OBJECTIVE,
OBTAIN 2'S
COMPLEMENT OF MO
(RESULT OF SUBTRACTING
MO FROM ZERO)
Ao AI A2 A, A. A. A, AI A. A, A. A. Ao AI A2 A, A. A. AoAI A2 A, A. A. Ao AJ A2A, A. A. Ao AI A2 A, A. A. AoAI A2 A, A.A.
V-
CO 0
JAA TE
E
E RL
E JAT
"-
( 2. O. O. )
I~ T S EP EA L
ITS EP LA E
I
1
(02.12.01.1)
SBS_ 5 j.S
( 2. O. 2. )
( 2. O. 2.1)
S 1- 5 j.1 D
~
F S • UTE
~ ~ l-
C RY 0
~
~
D
( 2. O. 1.1)
D
( 2. O. 6.1)
( 2. o.bo.l)
R SE MP
A Q -3 - AC ( 2. O. 3.1)
( 2. O. 1.1)
A I 35f- R
( 0 OL
~
~
8 j..
A 0
~ ~ f~ ~ I-
fM ST R
• LE R Y
S S
A(S
( 2. O. O. )
AT!
t-
AC
- -SR
F -
I
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3 I
I ....
--
-
AS 1 N C:/
A Dl
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or y t
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C
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F S T me
0 E D PP
A DI
YES
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I's TO AD (0, P,
1,2,3 & 6)
AO (D2)
02.20.66.1 (5B)
HOT 1 TO AD S
10 (D2)
02.20.66.1 (21)
I-- I--
S EP EA LY (0 .2 .0 .1 TC4
S EP LAE
~-
Ap
AC 9 _ 5
SR -36 .... A
"""-
V
-
V- V-
V
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(0 .2 .6 .1
(0 .2 .6 .1
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(0 .2 .6.1
9- 5 •
CI 5
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AC 9 _ 5
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(0 .2 .6 .1
(0 .2 .6 .1
A S
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6T~
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2DI
t-t--
I TIME OF NEXT
INSTRUCTION
OBJECTIVE, CHARACTERISTIC
ADJUSTMENT
02 20 10 I)
4T
--
II
PS
C
~ CD
pl-
II
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I
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D
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( 2.20.60.1)
·1·2 3 ·6·S
( 2.20.02.1)
( 2.20.63.1)
0
( 2.20.70.1)
23
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FIGURE 9, FAD, UFA, FSB, UFS
(CONTINUED)
24
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CLA
FSB
TRA
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Address
Octal Equiv
00004
00005
00000
050000 000004
030200 000005
002000 000000
606065 44321 0
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Pattern
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Tog
Address
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00004
00005
00006
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Switches
- I--I ...1-
. "'"'0'
I
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I & 10
25
Floating MultiplY (FMP +0260)
Mul tipJ ies the contents of the specified memory location by the contents .
of the MQ register. The most significant part of the product appears in the
accumulator, and the least significant part appears in the MQ register.
The product of two normalized numbers is in normalized form. If either
number is not normalized, the product mayor may not be in normalized
form.
OBJECTIVES,
NORMALIZE END
OPERATION
NO
Un normalized floating Multiply (UFM -0260)
Multip\ ies the contents of the specified memory location by the contents
of the MQ register. The result is not normalized.
OBJECTIVES, ( E TIME)
1. ZERO TEST MULTlPLlER IF AC FR IS CLEARED
2. ASSIGN PRODUCT SIGN
3. ENSURE NORMAL ZERO PRODUCT IF UFM
WITH NORMALIZED ZERO MULTIPLICAND
SHIFT AC (9-35) •
MO(9-35) LEFT 1
A5 (01)*
02.20.20.1 (3G)
END OP
END OP
~A4.5(D~
02.20.09.1
(2E +4E +4F)
OBJECTlVE:(1 TIME)
ASSIGN MO SIGN
A>JD
(TCllh','
OBJECTIVES'STEP 1 (B!!II""
1. MULTIPLY
2. CHARACTERISTIC C'6MPUTATION
.,,!.,
YES
NO
FIRST CELL DRIVER FOLLOWING THE INDICATED
TIMING LEVEL SETS THE RECEIVING REGISTER.
NOTE,
THIS BLOCK IS INTERROGATED WITH CONSECUTIVE
CELL DRIVER OUTPUT PULSES BEGINNING WITH THE
PULSE THAT GENERATES THE FIRST L3 LEVEL
FIGURE 10. FMP, UFM
26
HOT 1 TOAD8
AC (0-8) TO AD
10(02)
02.20.66.1 (5C)
10 (02)
02 .20.60.1 (4H)
I'S TO AD (O,P, 1,
2,3 & 6)
10 (02)
02.20.66.1 (5C)
AD (0-8) TO AC
II (01)*
02.20.64.1 (4F)
CHA~ACTEItISTIC
Location
Switches
00000
00001
00002
00003
00004
00005
00006
Inst
CLA
LDa
FMP
TRA
Tag
Address
Octal Equiv
00005
00005
00006
00000
050000
056000
026000
002000
Location
Switches
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27
Floating Divide or Proceed (FDP +0241)
.
Divides the contents of the accumulatOr (dividend) by the contents of the
specified memory location (divisor). The quotient appears in the MQ
register, and the remainder appears in the accumul-ator. If the dividend
fraction is greater than or equal to twice that of the divisor fraction, or
if the divisor fraction is 0, division does not occur and the computer tokes the next
instruction in sequence. The quotient is in normal form if both the dividend
ond the divisor ore in I)ormal form. The sign of the MQ is the algebraic
sign of the quotient. If the dividend fraction is 0, the contents of the
accumulator (Q, P, 1-35) are cleared and the sign is set plus.
OBJECTIVES, TC 2
OBTAIN TRUE CHARACTERISTIC DIFFERENCE
PERFORM 1ST OF 2710 DIVIDE CYCLE
/"
OBJECTIVE, RESET MQ REG ISTER
PREPARE FOR DIVIDE CHECK TEST
I
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E2(DI)'
02.20.11.1 (5E)
(DIVIDEND
DIVISOR)
=
MQ(9) TO AC(35)
A4 (Dl)'
02.20.31.1 (SA)
SHIFT AC (9-35)&
MQ (9-35) LEFT 1
A 4 (Dl)'
02.20.20.1 (3H)
! ;
OBJECTIVES,
STEP I (TCII)
1. CHECK FOR LEGAL DIVIDE
2. DIVIDEND ZERO TEST
3. OBTAINCHe>,RACTERISTIC DIFFERE!:,!CE
~t~~1'Ir:~
c
,\1"1
END OP
'FIRST CELL DRIVER PULSE FOLLOWING THE IND ICATED TIMING
LEVEL SETS THE RECEIVING REG ISTER,
FIGURE II. FOP
28
~
)."11
c
'7
~
______~____________~
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lWlCE THE
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~~.
OBJECTIVE, TC J3
REMAINDER OF
DIVIDE CYCLE
<
To::v:- -TC 13 AND TC 15,
1. 200 PLUS CHARACTER
DIFFERENCE TO MQ
2. OBTAIN ORIGINAL
CHARACTERISTIC
OF DIVIDEND
Location
Switches
lnst
00000
00001
00002
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00005
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Tag
Address
Octo! Equiv
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Live Reg
---
000007
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(I TIME)
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FRACTION OF
ACC UMULA TO R
AC (9-35) TO AD
10 (02)
02.20.61,1 (28)
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10 (02)
02.20.60.1 (4C)
1 '5 TO AD (Q, p.
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'0
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Oouble-Precision Floating Add (OFAD +0301)
Adds the double-precision number in the specified memory location and
the next higher location to the number in the accumulator and MQ registers.
The result is a normalized double-precision number with the major answer
in the accumulator and the minor in the MQ. The sign of the accumulator
and MQ is that of the algebraic sign.
OBJECTIVE: STEP 10 (TC 10 & 2)
REGISTER SWAP OR REGISTER
SWAP AND INTERCHANGE FOR
MINoRrA_D_D_.____________~------------------~~~~~-----N~O_<
YES
Q CARRV
Double-Precision Floating Subtract (DFSB +0303)
The same as DFAD except that the sign of the double-precision number in
memory is inverted at the beginning of the operation.
DFAD
.\.
INHIBIT
SB(s) TO SR(S)
CHAR DIFF
< 100
OBJECTIVES, STEP II (TC I & 10)
I. PLACE LARGEST CHARACTERISTIC IN SR.
2. CHARACTER DIFFERENCE IN SC IF LESS THAN 100.
r:BJ:::'S;:T::::) - 1
EQUALIZE FRACTICNS
2. SIGN DETERMINATlCN (ADD
OR SUBTRACT)
I
I
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FIGURE 12. DFAD,DFSB
30
*
FIRST CELL DRIVER PULSE FOLLOWING
THE INDICATED TIMING LEVEL SETS
HIE RECE IVING REGISTER.
15~----------~1----------~
I
21~------------------------------
__--------~
OBJECTIVES:STE.P IS (TC 10.s. 5)
1. MINOR ADD
2, SWAP FOR Iv\AJOR ADD
OBJECTIVE: STEP 24 (TC 20 & 4)
COMPLEMENT CORRECTION
OBJECTIVES:STEP21 (TC 20 & 1)
t
1. MINOR SUBTRACT.
2. SWAP FOR MAJOR SUBTRACT.
OBJECTIVE: STEP 16 (TC 10 & 6)
MAJOR ADD
-----~-=+==~~=---=~
-- -- -- --- --OBJECTIVE: STEP 22 (TC 20 & 2)
MAJOR SUBTRACT
--- --- -----
OBJECTIVE: STEP 25 (TC 20 & 5)
COMPLETE.'Z' COMPLEMENT
CORRECTION
~------~--------------~
NO
YES
YFS
SHIFT AC (9-35) &
MQ (9-35) RIGHT
A3 (01)'
02.30,69,1 (4F)
YES
NO
END OP
02.30,09,1
(3A + 4A)
YES
END OP
02,30,09.1
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I 00003
+301
000
a
00005
233012345670
233024713561
00
233530643752
LIS
LIG)
00003
+301
374
0
00005
233012345670
233516273432
00
,n,
',""'40
'H'
"","0
374
a
00003
233 0 1234S 67 0
22<"""""
I 00
1
1
00004
+020
000
a
00000
002000000000
227516273432
00
~~~--r-l~t;;~~----------~~----~-----~~~,-~~~~~~,~-~:i:-~g'-e~~~-----------;'~~~~~IorI~II."-~-'-- ~:~--~~~__II_~~_I-I~:e,-}-------N~~L-------~~~--------------------------------------------1
1
E
00001
+560
000
a
00005
056000000005
227516273432
I 00
"", com40
-;:;~--~~~5~-N~,--------~----~---e~~o~,~r1M~,~~o~e~N~~-----------ir--t·---
E
I
00001
+560
000
a
00001
000654321765
22751627341)
: 00
'00,"",,0{-
I
E
00002
+500
000
a
00004
050000000004
22" "'''4 U
100
I I I
I
~:;*"'--...CTERIST1C OF AC AND
FRACTION OF AC TO SR
7- REGISTER SWAP IN PREPARATION
FOR axc
YES
SR (1-35) TO MQ
(F
j :
)
E5 (Dl)'
02.30.65.1 (5B)
AD (9-35) TO AC
(ACC RESEll
AS (DJ)'
02.30.62.1 (41)
MULTIPLY CYCLE
(AXD + axc + AXe)
OJECTIVES: STEP 15 (TC 10 & 5)
OBJECTIVES: (2ND E TIME)
I. ZERO TEST HIGH ORDER MULTIPLIER
AND MULTIPLICAND
1. MUL TPL Y BXC
2. ORIGINAL FRACTION OF MQ
2. COMPUTE FINAL CHARACTERISTIC
BACK TO MQ
OF PRODUCT
3. SWAP THE FRACTIONS Of THE
EFFECTIVE ADDRESS AND
EFFECTIVE ADDRESS + I.
4. RESTORE SR CHARACTERISTIC
5. DETERMINE PRODUCT SIGN
NO
INHIBIT
~--------l se(s) TO SR (5)
SET AC & MQ
02.15.25.1
CONDITION
AD(9-35) TO AC(10-3S)
ond MQ 9 TRANSFER
LINES
*'" '" SIMULTANEOUS OPERATION
*** '" GAT ING OCCURS WITH FPI ONi
IT ONLY OCCURS ONCE
(STEP 12, AXD)
" FIRST CELL DRIVER
PULSE FOLLOWING
THE INDICATED TIMING
LEVEL SETS THE
RECEIVING REG ISlER
FIGURE 13. DFMP
34
NOTE:
THIS BLOCK IS INTERROGATED WITH CONSECUTIVE CELL DRIVER
OUTPUT PULSES BEGINNING WITH ruE PULSE THAT GENERATES
THE FIRST L3 LEVEL.
14
21
Location
Switches
00000
00001
00002
00003
00004
00005
Double Precision Floatinil Multiplv (DFMP)
Tog
Inst
ClA
lDO
DFMP
TRA
Address
Octal Equiv
00004
00005
00004
00000
050000
056000
0261 00
002000
211 777
200777
Pattern
Pattern
0~ii~~
uS
I
E
OBJECT1VES:STEP 16 (Te 10 & 6)
~
1
2 - REGISTER SWAP FOR Axe
~
8
AC (9) == O?
C
SHIFT MQ (9-35).
AC (9-35) LEFT 1
A3 (01)*
02,30,69,1 (5E)
I
I
OBJECTIVES;STEP·21 (TC 20 &_1)
I
I
I - MULTIPLY Axe WITH INHERENT AD TO SUM
000000000000
00
000000000000
I
211777777777
00
000000000000
E
OOODZ
t560
000
0
00005
056000000005
211777777777
00
000000000000
0000'
+060
000
0
00002
200777777777
211777777777
00
200777777777
00003
.,,,
000
0
'000
I "')0000000'
211777777777
00
200777777777
1&10
00003
+261
033
0
00005
211777777777
211777777777
00
211777777777
1&10
F '"
I
"'
OF Bxe + E!:mAXD
I
,"
'"
I
AC (0-8) TO AD
AD (D2)
02,20.60.1 (4F)
1
T
AD(J-8) TO MO
AJ (DJ)'
02.20.63. J (SI)
I
1
I
J.
T
1
1
.
I
AC(S) TO MO IS)
Al (01)*
02.20,70.1 (4F)
J.
J
J 0~ r5'<;~"'
Q.'V
"QO-\-o.o.~1<.
re-
t261
033
0
00005
211777777777
211777777777
00
211777777777
1&10
033
0
00005
211777777777
211000000000
00
211777777777
2&10
00003
tZ61
030
0
Oa005
211777777777
Z11677777777
00
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)
00003
+'bl
0>5 I 0
JO005 '
211777177777
211767717777
00
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Z&10
1
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Z 11776777777
00
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00003
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017
0
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211777777777
Z11777677777
00
ZII000177777
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7
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211777767777
00
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L
SI
00003
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0
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211717776177
00
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2&JO
LI8I
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211777777677
00
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003
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211777777767
00
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or
0
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00 I "1000000001
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• " 1777777777
LUll \
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4&10
,
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I J3\ 00003
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033
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211000000000
00
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5&10
,
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0
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00
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0
,115\ 00003
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00003
I, ,,"
171
000"'
I
t261
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00
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5&10
+Zb
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211777777777
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00
Z11001777777
5~JO
"76
017
,,, 777777777
00 I ,,, 000 177777
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0
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AD (Q-8) TO MQ
AD (Dj»
02.30.65. J (5G)
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1&20
1
1
L (2<)
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i ,,, 777777777
I L IZB\
(
§ ~~
0
,*"
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AD (0-8) TO AC
AO (01)*
02.30.61.1 (3D)
02.20,66,1 (5B)
J
«.:
-*
~ ~
+Z61
YES
1'5 TOAD (Q,I,2,
3,6 & 8)
AD (D2)
'<:'
t
00003
" 1777777777
\
l~!;:}
0!NV
00003
2 - CARRY CORRECTION
AC (9-35) == o.
MO (9-35) "O?
:tJ;y s;;<
l
3 - NORMALIZE
Nol
\
0
LI7
I L ""
END OP
02,30.09.1
~
J? ~"&-
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1-
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1
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II I I I I I I I I I
Double-Precision Floating Divide or Proceed (DFPD -0241)
Divides the double-precision num:.er in the occumulator and MQ (dividend)
08JECT1VES:STEP 11 (TC 10 & 1)
G8JECTIVES:STEP 13 (TC 10 & 3)
by the double-precision number in the specified memory location and locotion plus 1 (divisor). The result is a double quotient in the accumulotor and
MQ registers with an associated algebraic sign.
OBJECTlVES:(E TIMES)
1. SAVE EFFECTIVE ADDRESS
2. SAVE EFFECTIVE ADDRESS +1
3. DIVIDEND ZERO TEST
NO
(ILLEGAL DIVIDE)
INHIBIT
1 - - - - 1 5B(5) TO 5R(5)
08JECTIVES:STEP 12 (TC 10 &, 2)
1. COMPLEMENT AC
2. TRIAL REDUCTICN
OBJECTIVES:STEP 16 (Te 10 & 6)
1. REGISTER SWAP FeR 01
xD
2. PUT Rl IN CORRECT FORM
Q"'01+ Q 2
A
+,
0," -C-
R] - 01 D
Q
"---
2
C
A+'
R "" REMAINDER OF - ,
C
35
50
Ii
35
II!
II
C
A
AC
A+B
SWR
MO
Rl -01 D
0" - - +
C
C
* FIRST CELL DRIVER PULSE FOLLOWING THE
INDICATED TIMING LEVEL SETS THE RECEIVING
REG ISTER
26
* FIRST CELL DRIVER PULSE FOLLCWING THE INDICATED
TIMING LEVEL SETS THE RECEIVING REGISTER
FIGURE 14. DFDP
38
C?
Nol
"
3. REG ISTER SWAP FOR
AD (9-35) TO AC
(ACC RESEl)
'1
1
I
I
I
I
SET FPl TGR
A4 (Dl)
02.20.08.1 (4A)
AS (D1)*
02.30.62.1 (4G)
I
SET TC20
AS (D2)
02.20.03.1 (5D)
1AS
SET TCI
(D2)
RESET TC6
AS (D2)
02.20.02.1 (3C)
02.20.00.1 (IB)+
I
SET TC20
A5 (D2)
02.20.03.1 (5D)
1AS
SET TC2
(D2)
1MPY
SR (9-35) TO AD
CYCLE
02.12.08.1
Sc == 0 ?
J
I
AC9-35 TOAD
MPY CYCLE
02.12.10 1
1
-
I
1
02.20,04.1 (3A)
I
- - - - - - - - - r--- - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - rOBJECTIVE'STEP 21 (TC 20 & I)
MULTIPLY CYCLE 01 XD
~
\NO
NOTE
/
.YESI
I •
SET Fl'li .;.
f'
2. SUBTRACT R] - Q] D
I
I
..,
RESET TC
AS (D2)
02.20.05.1 (4F)
r<
YES
C
AC (9-35) TO SR
AS (Dl)'
02.30.67.1 (4B)
I
1
I
I
.\
=Oe. /
'.
)
-
1. CHECK FOR LEGAL DIVIDE FOR
MQ 9-35
\
I
OBJECTiVES,STEP 24 (TC 20 & 4)
A4 (Dl)(
,"
02.2Il.08.h.. ".
K );
\
~:
I
MQ (35)
=1 ?
\
NO
I
OBJECTIVES.STEP 2S (TC 20 & S)
ft
1. COMPLEMENT ACCUMULATOR
2. TRAIL REDUCTiON FOR Rl - 01 f
--C--
.
3"
AD (9-35) RIGHT TO AC
AD (35) TO MQ (9)
MQ (9-35) RIGHT ONE
02.15.25.1
REDUCE SC Xl
02.12.38.1
REDUCE SC Xl
02.12.38.1
SH 1FT AC (9-35) •
MQ (9-35) RIG HT
WlT!1 AC 35 TO
MO (9)
02.12.22.1 .
r
STEP 2S BRINGS UP FDP STEP 2.
WITH THE EXCEPTION OF SETTING THE
FP2 TGR THE NO 9 CARRY CASE DOES
NOT APPLY TO STEP 25. AD (0-8) TO
AC IS CONDITIONAL ON NOT STEP 25.
SET FPI 1GR
]
A4 (DI)
02.20.08.1 (5e)
1 AS
SET T C 2 ]
(D2)
02.20.04.1 (5B)
END OP
02.30.09.1 (2C)
(DIVIDEND
S~II'T M:f9-3$).
MQI'{-,tl5/'RI<:$f\T
WItH~C'3S. TQ,
< DIVISOR)
YES
NO (DIVIDEND.:>DIVISOR)
MO(j').· '-:',
01'.12;27,1'
SHIFT AC (9-35).
MO (9-3S) LEFT 1
A4 (Dl)'
02.20.20.1 (3H)
NOTE,
THIS BLOCK IS INTERROGATED WITH CONSECUTiVE CELL DRIVER
OUTPUT PULSES BEGINNING WITH THE PULSE THAT GENERATES
THE FIRST L3 LEVEL
22--
39
OBJECTIVE'STEP 4 AND
STEP 30 (TC 4) FSB
SUBTRACT Q 1 - Q 2
ASSIGN MQ CHARACTERISTIC
OBJECTIVES'STEP 26 (TC 20 & 6)
d ,,"
1. DIVIDE
<,I<'y_j'\"
2. LINE UP FOR 0, + 02
YES
NO
,-------
I
I
AC (Q-8) TO AD
AO (D2)
02.30.63.1 (4C)
----1
OBJECTIVE:STEP 3
& STEP 30 (TC3)
FAD
,
I
I
I
I
OBJECTIVE'STEP '30 (TC +,30)
I
SAVE AC (Q-8) DURING STEPS
3AN!H
(FLOATING POINT ADD AND
SUBTRACT)
I
'------ -- -- - - - - - -
INSTRUCTION COMPLETE
FIGURE 14.
DFDP
(CONTINUED)
40
I
I
I
I
I
I
I
I
I
I
STEP51SA
CONTINUATION
OF STEP 4
?
Location
Switches
Inst
00000
00001
00002
00003
00004
00005
00006
CLA
LDO
DFDP
TRA
Pattern
Pattern
Pattern
Tag
Address
Octal Equiv
00005
00006
00004
00000
050000
056000
424100
002000
176777
173777
173777
000005
000006
000004
000000
777777
777777
777776
Double Precision Divide a.nd Proceed (DFDP)
l
CONSOLE INDICATORS
J _
:::
;
~
~
IflolA I iA21A.IA.IA.IAoiA
IIA~IA.'A • .0.5 Ao~AI A~ A3 A4'A, ~olAI A2 A, A• .0.5 Ao A, 1.0.2 A3 A41A5 Ao'A, M
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YES
Store (STO +0601 )
Stores the contents of the accumulator (5, 1-35) into the specified
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Store Logical Word (5LW +0602)
Stores the 36-bit logical word of the accumulator (P, 1-35) into the
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INHIBIT SR TO SB
STZ
02.12.40.1 (4A)
(1-35)
INSTR COUNTER (IC)
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FIGURE 15.
44
STZ,STO,STO,SLW
*
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*FIRST CElL DRIVER PULSE
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Store logical Word with Parity (SLP -1612)
Stores the 36-bit logical word of the accumulator (P, 1-35) into the spedfied memory location (5, 1-35). In addition, the sign bit of the accumulator
is stored into the C bit position of the memory location. Unlike other store
operations, parity is not generated on SLP.
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02.15.34(3A)
SR TO SB
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02.12.40 (4B)
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02.12.02 (4E)
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02.12.02.(4C)
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XR 4
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BRING UP "GEN
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02.05.45 (lE)
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ADDRESS REG (AR)
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INSTR COUNTER (IC)
2 3 4 501
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CIRCUITS
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02.05.45(5E,1 E)
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02.12.50 (3F)
S, M R 6
1 19 10)
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lNST
LEGEND
STORE LOGICAL WORD WITH PARITY
I
ALPHA CODE:
SET MDR 36
E2Dl
01.19.10 (4A)
02.05.45 (18)
02.12.50 (2A)
SB (S, 1-35)
TOMDR
E2Dl
02.12.50 (2A)
------___
1 CYCLE
------......
E CYCLE
SLP
CYCLES:
-1612
S1
IF~T
11 12
13
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F rtj II
Y
18 21
20
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(
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S P - 61
-------------..
CONTROL
SEQUENCE NOTES,
THE C(AClS,P, 1-35 ARE STORED INTO THE C(Y)C,S, 1-35.
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
END OP
02,15.35 (2E)
AC(P) -+ Y(S).
I
I
AC IS UNCHANGED AND PARITY IS NOT CHECKED.
INSTRUCTION
COMPLETED
)
FIGURE 16. SLP
47
TO MEMORY DATA REG
I TIME
POD 62
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FOlLOWING THE
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LEVEL SETS THE
RECEIVING REGISTER
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SET PARTIAL
STORE TGR
16(02)
02.15.34.1 (3H)
rr-
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TIME
02.15.34.1 (3A)
(TSL STL)
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E 3 (01) *
02.12.05.1 (3E)
Store Decrement (STD +0622)
Stores the decrement portion of the accumulator (3-17) into positions 3-17 of
the specified memory location. The rest of the memory word and the accumulator are unchanged.
AC (3-17) TO SR
(3-17)
E 3 (01) *
02.12.02.1 (3F)
SB (S-20) TO
SR (S-20)
E 3 (01) •
4F
02.12.01.1 (4C,4G)
)
.I
21
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35
YES
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(PR9")
+
ADDER (AD)
SB (S-2, 18-35 • C)
TO SR
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02.12.01.1 (4C,4D,
4F)
INDEX REGS (XR)
XR 1
XR 2
ADDRESS REG (AR)
AC (21-35) TO SR
E 3 (01) *
02.12.02.1 (4H)
SB (S-20. C) TO SR
E 3 (01) *
02.12.01.1 (4C,4G,
4F)
XR 4
11
21
1
1(21-35)
35
35
1
I
I
I
TO
MAR
SECOND
E TIME
02.15.34.1 (3C)
Transfer and Store Instruction Counter (TSL -1627)
Stores the contents of the instruction counter (the location of the TSL instruction plus 1) into positions-21-35 of the specified memory location. The rest
af the memory word is unchanged. The computer tokes its next instruction
from the specified memory location plus 1.
35
INSTR COUNTER (Ie)
I
l
Store Instruction location COJnter (STL -0625)
Stores the contents of the instruction counter (the location of the STL instruction plus 1) into po:;itions 21-35 of the specified memory location. The rest
of the memory word is unchanged.
MULTIPLIER-QUOTIENT REG (MQ)
RESET PARTIAL
STORE TGR
E 6 (01)
02.15.34.1 (5H)
l
'i AR TO I:
IEI(DI)*
.102.12.36.1 (4E)
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02.12.40.1 (4C)
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0~.I2.36.1 (4H)
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02.12.50.1 (3F)
INST
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+0621 STORE ADDRESS
ALPHA CODE:
- - - - - - -..
~
1 CYCLE
-------.
E CYCLE
STA
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(
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L CYCLE
-------------.
,
END OP
02.15.35.1 (2E)
\
1
\
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IC TO AR
E 5 (DI)
02.12.34.1 (40)
C
INSTRUCTION
COMPLETE
CONTROL
I, E, E
CYCLES:
+0621
S1
SB TO MDR
E 2 (01)
02.12.50.1 (2A)
\
48
\
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I
I
Store Address (ST A +0621)
Stores the address portion of the accumulator (21-35) into positions 21-35
of the specified memory location. The rest of the memory word and the accumulator are unchanged.
I
THE PARTIAL STORE TGR CAUSES A
SECOND E CYCLE, PREVENTS END
OP AT END OF FIRST E CYCLE,
INHIBITS SB TO MDR, AND PREVENTS
PARITY GENERATION DURING THE
FIRST E CYCLE
02.15.34.1 (2E) 02.12.50.1 (5G)
Him I
T
11 12
13
18
20
21
SEQUENCE NOTES:
THE C(AC)21-35 ARE PLACED INTO C(Y)21-35'
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMAllER OF THE NlO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
THE C(Y)s, 1-20 AND THE ClAC) ARE UNCHANGED.
Y
35
TO MEMORY DATA REG
r------.
21
r------
IN5TR COUNTER (Ie)
INSTR COUNTER (IC)
---------~~~-------
STEP IC
35
35
35
ADDER (AD)
INDEX REGS (XR)
lADDER (AD)
ADDRESS REG (AR)
I
XR I
21
XR 1
XR 2
XR 4
XR 4
21
I
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I
35
,
INDEX REG 5 (XR)
XR 2
ADDRESS REG (AR)
XR 4
11
•
7
______ .J
INDEX REG S (XR)
XR 1
XR 2
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21
35
21
21
35
35
35
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MAR
TO
MAR
ACCUMUlATOR REG (A C)
MULTIPLIER-QUOTIENT REG (MQ)
INST
LEGEND
+0622 STORE DECREMENT
ALPHA CODE, ...:S:..:T.:D_ _ _ _ __
CYCLES:
S1
Y
11
12
13
18
20
21
-------.
CONTROL
SEQUENCE NOTES,
THE C(AC)3_17 ARE PLACED INTO C(Y)3-17.
XFERS INCLUDE All BITS CONTAINED IN
THE SMAllER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
ACCUMULATOR REG (A C)
I, E, E
CYCLES:
THE C(Y)S-2, 18-35 AND THE C(AC) ARE UNCHANGED.
-0625
SI
11
Hr~a
H
L CYCLE
-------------...
CONTROL
INST
LEGEND
-1627 TRANSFER AND STORE INSTRUCTION LOCATION COUNTER
ALPHA CODE:
CYCLES:
TSL
T
18
20
I
21
Y
------......
-1627
E CYCLE
S1
35
I, E, E
SEOUENCE NOTES,
-------------.
CONTROL
THE LOCATION OF THE STL INSTRUCTION +1 IS PLACED IN C(Y)21-35.
H?!ta I
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11 12
Y
18-20 21
35
13
L CYCLE
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPEC!FIED.
MULTlPLIER-OUOTIENT REG (MO)
1 CYCLE
E CYCLE
35
L CYCLE
- ------------.
STL
TO
MAR
1 CYCLE
+0622
E CYCLE
-0625 STORE INSTRUCTION LOCATION CTR
ALPHA CODE:
~I,_E~,_E_ _ _ _ _ _ _ _ _ ____
I CYCLE
- - - - - - __
INST
LEGEND
MULTIPLIER-QUOTIENT REG (MQ)
SEQUENCE NOTES,
THE LOCATION OF THE TSL +1 IS STORED IN C(Y)21-35.
XFERS INCLUDE ALL BITS CONTAINED IN
THE C(Y)s, 1-20 ARE UNCHANGED.
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED,
POSITIONS 5, 1-20 OF Y ARE UNCHANGED.
THE COMPUTER TAKES ITS NEXT INSTRUCTION FROM Y+1.
49
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(CONTINUED)
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SeliC (02.12.36)
SR __ MDR (02.12.50)
SR ..... SB (02.12.40)
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Partial Store prevents:
E arl -A Dl·
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End Op (02.15.35)
5et IC (02.12.36)
5R_5B (02.12.40)
5B _ MDR (02.12.50)
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00
000000000000
)0000
'"
,
00002
+601
000
a
00007
060100000007
042000'777777
00
000000000000
00000
on007
hnl
OnO
0
00002
042000777777
042000777777
a
000000000000
no non
T
0000,
+774
377
7
00003
077400777777
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00
000000000000
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nnnM
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0000
1':1
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nn
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0
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77777
77
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0.7000777777
00
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00001
+500
000
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0000,
0'7.00n777777
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00007
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nn
77
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I
00002
+601
000
a
00002
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00
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00003
+774
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00003
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nno
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00007
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0, >Onn777777
no
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77777
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-
77777
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00004
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000
7
00004
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00
077777777777
77777
E
00005
+560
000
a
QQQQL-'l56000000007
042000777777
00
077777777777
77777
77777
I
53
Compare Character with Storage (CCS -1341)
TO MEMORY DATA REG
Compares the character in positions 30-35 of the acclI11ulator with the
character (specified by bits 15-17 of the instruction word) in the specified memory location.
If
the
accumulator character bits are greater than
the character in memory, the computer takes the next sequential i!lstruction; if these bits aTe equal to the specified character, the computer skips
the next instruction and proceeds from there; if they are less than the specified character, the computer skips the next two instructions. The contents
of the accumulator and memory are unchanged.
9
SELECT CHAR
13D(lNST)
02.04.19
"FIRST CELL DRIVER PULSE
FOLLOWING THE INDICATED
TIMING LEVEL SETS THE
RECEIVING REGISTER
E TIME
02.15.34(3A)
(AD 30 CAR)
STEP IC
21
SEL SB CHAR TO SR (30-35)
E3Dl"
02.12.07(4C)
02.01.40 & 41
2,4
INSTR COUNTER (IC)
CLEAR SR (S-29)
E3 (DI)*
35
*3,*5
ADDRESS REG (AR)
21
35
35
TO
MAR
MULTIPLIER-QUOTIENT REG (MQ)
NO
AC~SR
INST
LEGEND
-1341 -- C COMPARE CHARACTER WITH STORAGE
ALPHA CODE:
--------1...
1 CYCLE
------__
E CYCLE
~C:..:C:..:S_ _ _ _ _ __
-1341
S1
L CYCLE
-------------.
NO
AC>SR
CONTROL
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
CYCLES: .;;I,,--,"E,,-(:;;L,-)_ _ _ _ _ _ __
Y
11 12
13
> CHARACTER IN Y, TAKE THE
NEXT INSTRUCTION. IF C(AC)3O_35 = TO THE SPECIFIED CHAR, SKIP 1
7044: I, E, L
'54'
35
THE CHARACTER IN LOCATION Y SPECIFIED BY THE "C" FIELD IS COMPARED
WITH THE C(AC)30-35. IF C(AC)30-35
INSTRUCTION. IF THE C(AC)30_35
FIGURE 19. CCS
21
SEQUENCE NOTES:
CYCLES REQUIRED 7040: I, E
NOTE: THE EQUAL CONDITION
EXISTS ONLY IF THERE WAS NO
30 CARRY AT LIDI
15 18
17 20
<
CHAR, SKIP 2 INSTRUCTIONS.
C ompare Charac er
AoAI A2 A,A.A. Ac AI A2A,A. A. AoA, A.A.A.A.AoA, A2A,A.A.AoAJ A.A,A.A.AoA, A2A,A.A.AoA, A.A.A.A.
~i~i~~ ~ la~
'-v
~
c..>.
'V
l:::?
~
~ 4S" ~ ~ ~
lJl~;
(}.f J J. rf r5 ,,-' «.,,-'"
q,;:
« "f <:> 0- -\0..
0.
((
17
i5&
17
15&
17
I'"
E RL
«(
• PC 5 01 ....
51 SR C
• PC 5 I ... SB SR CI
• PC 5 2'" 51 SR C
E C.
BC-SR (R SE 5 1-
CS bl ck .h
B
5 nlrm 10 .1.(1.1
.li2. 7.1)
~ (0.1 .0 .1)
SB
--
(0 0 L
1-011-01..........-+0-1
~ A
1~f2R ~
SB SR Cp
rS!
SB
5 30
5 31
-- -- -
5 35
--
SB 0
SB I
R3
R3
SB 5
R3
-
-- -- --
E L L AR Y
0
L LA E
5
ie'
~
(0 I
E (02 .1 .3
-
E eo Iy' 3[ 1·
PC S 5
lAc
o
1+ +34
""'"
Free
tor
~
(3C 35 1-; SR (se lee ed po tic) p2. 12.b6)
B
f.: R s
Ie te
po iti n
c cl
SRI .... SB (08 .1
2.12. ~11 2 06)
•
e"
Partio I Store prevents:
~
E
~
~
'r~'
~
~
"u
"'"
E
0000 1
+500
000
0
00006
050000000006
000000000000
00
000000000000
T
0000
+500
000
0
00001
675747372717
675747372717
00
000000000000
OOOOZ
+601
000
0
00007
060100000007
675747372717
00
000000000000
OOOIlZ
+601
000
0
00002
675747372717
675747372717
00
000000000000
~. Q!C007
562300000007
675747372717
00
000000000000
175747372717
675747372717
00
000000000000
I
t.--.J (j
"(
Q;'
I
EO)
OOOO:~
_+~L
00.0
E I
E2
00003
-623
000
0
00007
E(2)
I
0000.3
-623
000
0
00003
175747372717
675747372717
00
000000000000
I
E
00004
+560
000
0
00007
056000000007
675747372717
00
000000000000
E
I
00004
+560
000
0
00004
175747372717
675747372717
00
175747372717
002000000000
I
T
00005
+020
000
0
00000
675747372717
00
175747372717
I
E
00001
+500
000
0
00006
050000000000
675747372717
00
175747372717
E
I
00001
+500
000
0
00001
675747372717
675747372717
00
175747372717
I
E
00002
+601
000
0
00007
060100000007
675747372717
00
175747372717
E
T
00002
+60
000
0
00002 I A7574"7>717
A75747,7>717
00
17<;74"77717
T
""
DOnO,
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Onn
In
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'7Q47,77717
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17<;74"777>7
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000.
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'7<;747'77717
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-623
000 10
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8I11III/
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ry
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Ie rly AO 1
1.4(
f
P( D Xor ia St re
End ap (02.15.35)
SeliC (02.12.36)
SR ..... 58 (02.12.40)
S8 _MDR (02.12.50)
SR (3 -3 )( 2. 2. 2)
St re yc e ( 2. 2. 0)
E ear y' 2Dl
10
,...
~
10
v
~
FOe 62 E or y.
F rl 01
E
(30 35
'=~;I
;f AC (3 -3 ;)-; SR sel ct d
po iti n
A Dl • PJD 6X'
rna ter E
~
B f.~ R ( 2. 2. 1)
Iy'~ l'
D O· R ~
;f PO
01 lor E 101
';;;;;1-
Fi ~
CONSOLE INDICATORS
'i1ijilJ~~ Ii' J/;:~j /r/
(0 .1 .3)
or
o
I 10 e E;;;r:
P!:JD OX:l
Store AccuITlUlator Character (SAC)
. ! D (0 .1 .5 )
d p 02 1535
0 ' nnnO?
0
S C - 62
59
TO MEMORY DATA REG
AND to Accumulotor (ANA -0320)
Logically ANDis each bit of the specified memory location with the
corresponding bits of the accumulator. The memory word sign bit is AND'ed
with the accumulator P bit. The AND'ed result of the two words appears
in the accumulator. Bits 5 and Q of the accumulator are cleared, and the
contents of the memory word ore unchanged. logical AND'ing is as follows:
1,1 ~ I
1,0 ~ 0
0, I
~
0
0,0
~
0
12
INSTR COUNTER (IC)
1
1
I TIME
POD 32
21
1
35
1
I
E TIME
02. 15.34. 1(3A)
IQ
ADDRESS REG (AR)
I
21
I
SR (S) TO AD (P)
E 3 (D6)
02.12.08.1 (36).
SR TO AD
E 3 (D6)
02.12.08.1 (4C)
AC (P, 1-35) TO
AD (P, 1-35)
E 3 (D6)
02.12.10.1 (4G)
1
I
l
35
\
TO
MAR
T
I
SET AC (S,O) PLUS
E 7 (DI)*
02.15.22.1 (4E)
I
1
AD GEN TO AC
(P-35)
E7(DI)*
02.02.01-36
ANA LEVEL
TOAC
E 7 (DI) *
02.12.24.1 (46)
T
INSTRUCTION
COMPLETE
FIGURE 22. ANA
60
I
35
I
1
I
I
I
1
1
I
1
I
-------.~
1 CYCLE
-------.
E CYCLE
-ANA
-----
L CYCLE
-------------.
CONTROL
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
CYCLES,
~I~,~E_ _ _ _ _ _ _ _ __
-0320
S1
=======..
MULTIPLIER-QUOTIENT REG (MQ)
-0320 AN D TO ACCUMULATOR
ALPHA CODE,
T
1
\
1*3
1 (AD-GEN)
1-35
1
INST
LEGEND
1
I
12
ACCUMULATOR REG (AC)
1
END OP
02.15.35.1.(5E)
I~I
1 *3
\ (AD-GEN)
S6 TO SR
E 3 (DI)*
02.12.01.1(4C,4F)
1
r
"N"~'"
1
*FIRST CelL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVel SETS THE
RECEIVING REGISTER
Y
11 12
13
18
20
21
SEQUENCE NOTES,
LOGICAL MULTIPLICATION OF ACp, 1-35 AND C(Y)S, 1-35.
AC(S) AND AC(Q) ARE CLEARED. THE C(y) ARE UNCHANGED.
35
location
AOA, A2 A,A.A. AoA, A2A,A. A. AoA, A2A,A.A.AoA, A2A,A.A.AoA.I A2A,A.A.AoA, A2A,A.A.AoA, A2A,A.A.
EA L
L TE
-I~
E RL
!AT
f
A LY
E~ L
~
~
: L TE
E RL
~ L
LA E
Switches
Inst
00000
00001
00002
00003
00004
00005
00006
CLA
STO
CAL
ANA
TRA
Arr"~ul."
.N
Tog
Pattern
Pattern
Address
Octol Equiv
00005
00007
00006
00007
00000
050000
0601 00
450000
432000
002000
525252
652525
006005
000007
000006
000007
000000
252525
252525
TE
I AR Y
I /AT
o
TC E
M~
ST R
And to
E A LY
I
E AR Y.I--r--,
SBI ..... SR
(12.
,$'
2. I. )
A3PII-I-I--"""
N A.t---t-"tl---:::I--+-!-+-+~ 5
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E V
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I 000 10
onnn>
nn
I
E
00003
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450000000006
525252252525 00
000
0
oooot.
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00
E
I
00003
-500
000
0
00003
652525252525
252525252525 01
I
E
00004
-320
000
0
00007
432000000007
252525252525 01
E
I
00004
-320
000
0
00004
525252252525
000000252525 01
I
I
00005
+020
i 000
0
00000
002000000000
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I
E
00001
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000
0
00005
050000000005
000000252525 01
I
?
0;:
E
.
~
Q;.-
/:?
J'"
I
02 12 10 I)
E v C(y), THE COMPUTER TAKES NEXT INSTRUCTION.
C(AC) = C(y), THE COMPUTER SKIPS 1 INSTRUCTION.
C(AC)
< C(y), THE COMPUTER SKIPS 2 INSTRUCTIONS.
A PLUS ZERO (+0) IS' CONSIDERED GREATER THAN A MINUS ZERO (-0).
CYCLES REQUIRED: 7040: I, E
7044: I, E, L
NOTE 1: THE EQUAL CONDITION
~ EXIST ONLY 1
IF (ACS-)(Q CARRy)
NOTE 2: THE EQUAL CONDITION
~ EXIST ONLY IF
(ACS+)(SRS+)(Q CARRy)
FIGURE 23. CAS·
62
*3,'5
AC(S)-, Q CAR
SR(S)+, Q CAR
Ao AI A2 A, A. A. A, AI A2A, A. A. AoAI A2A, A. A. AoAI A2 A, A. A. Ao AJ A2 A, A. A. Ao AI A2 A, A. A. AoAI A2A, A.A.
lEA L)
ill
E
C} S
( A)
PR 0
01341
Location
Switches
Tag
Inst
00000
00001
00002
00003
00004
00005
00006
CLA
CAS
TRA
If x. ~ ~ l-
Octal Equiv
00005
00006
00000
050000 000005
034000 000006
002000 000000
Pattern
177777 777777
777777 777777
Pattern
(7\44
I a.
Ai«>
Address
....
S P C 02 12 36 I)
---
I a'
t----
~
I;~ fj"x.
p[m tox t7
GC T DE (0 .1 .3 .1
E RL
M 5 R
Compare Accumulator to Storage (CA51
E LA E
E !;AI LY
AD 11- ~ ~
ELA E'
OrO E
I
~~:~i; j;;8 .~~tfl~/!~:/rl/f~~~'p
i/;{i~1d~
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5B-- 5R (02 12.01 .1)
#'
I'-
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MIST R
EA L
L (AT
Lea Iy'
C 51'-
R-~I 0(02 .12. pa.l)
rc-I+
Lea Iy'
C 5
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C 5
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I
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00001
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000
o
00005
050000000005
000000000000
0
E
I
00001
,500
000
o
00001
177777777777
177777777777
0
I
E
00002
+340
000
o
00006
034000000006
177777777777
0
E
L
00002
+340
000
o
00006
777777777777
177777777777
0
L
I
00002
+340
000
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00002
777777777777
177777777777
I
I
I
00003
020
000
o
00000
ooznonnnonnn
177777777777
n
I
E
00001
+500
000
o
00005
050000000005
177777777777
n
5 EP IC (02 I .3 .1)
I
\ \ r'-5'
\
1\
L lear y' 4
o
CONSOLE INDICATORS
o
5 p2 12 12 I)
2 J l e rl
I~
,..
TE I (0 .I~ •
•1
L ,-" •.
N I ( P ( 2. 5. 5. )
Ak
Et 0 PP G
~!
5T R I
63
TO MEMORY DATA REG
Logical Cam pare Accumulator with Storage (LAS -0340)
Compares the contents of the accumulator (Q,P 1'1-35) with the contents
of the specified memory location (5,1-35). The accumulator is treated as
an unsigned 37-bit number and the memory word is treated as an unsigned
36-bit number.
If the accumulator is the greater I the computer )takes the
next sequential instruction. If tl-e accumulator equals memory, 'the computer skips the next instruction and proceeds from there. If tl-e ,accumulator is less than memory, the computer skips the next two instructions and
proceeds from there.
"FIRST CEll DRIVER PULSE
FOLLOWING THE INDICATED
TIMING LEVEL SETS THE
RECEIVING REGISTER
INSTR COUNTER (IC)
4
*3, *5
21
35
ADDRESS REG (AR)
2
35
21
21
35
(Q-35)
(Q-35)
HOT I
TOAD 35
TO
MAR
MULTIPLIER-QUOTIENT REG (MQ)
NO
INST
LEGEND
..
HOT I TO
AD 35
L2D3
02.12.12(4B)
I CYCLE
------.-.
E CYCLE
r-----'---..,
AC
NOTE
CYCLES:
11 12 13
L CYCLE
CONTROL
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
SR
18 21
20
C(AC)Q
P 1-35
,
I
>
C(y)
5, 1-
35' THE COMPUTER TAKES NEXT INSTRUCTION.
C(AC)Q, P, 1_35=C(Y)S, 1-35' THE COMPUTER SKIPS I INSTRUCTION.
C(AC)Q P 1-35
,
,
<
C(y)
_ ' THE COMPUTER SK IPS 2 INSTRUCTIONS.
5, 1 35
THE AC IS TREATED AS AN UNSIGNED 37-BIT REGISTER.
THE C(y) IS TREATED AS AN UNSIGNED 36-BIT REGISTER.
CYCLES REQUIRED: 7040: I, E
7044: I, E, L
NOTE:
THE EQUAL CONDITION
ISTS ONLY IF THERE
AS NO Q CARRY AT
L DI
W
FIGURE 24. LAS
64
35
SEQUENCE NOTES:
IF:
>
I, E" (l)
Y
-0340
SI
YES
~
lAS
-----
ALPHA CODE:
-----~__II~
-------------.
SR
-0340 LOGICAL COMPARE ACCUMULATOR WITH STORAGE
"3, "5 (Q CAR)
Location
Switclles
Ao AI Az A. A4 A. Ao AI Az A. A. A. Ao AI Az A. A. A. Ao AI Az A.A. A. Ao AI Az A. A. A. Ao AI Az A. A4 A. Ao AI Az A. A4 A.
00000
00001
00002
00003
00004
00005
00006
I AR V
I f"-T
P~
0
~
M - 3a
(A
( 104 )
I at
A Dl
.--- p:~
Inst
Tag
CLA
LAS
TRA
Address
Octal Equiv
00005
00006
00000
050000 000005
434000 000006
002000 000000
Pattern
Pattern
377777 777777
377777 777776
S EP IC 02 12 36 I)
-
o TC
E (0 .1 .3 .1
Lg~cal Co~are
I
ATE E E AR V
3D
L ."
B ~. R ( 2. 12. 1.1)
I-I-- ~
4.,
L Ei"R V·
~~
Y
'< -t?\
Y
00001
+500
000
a
00005
05000000000 5
000000000000 00
00001
+500
000
o
0000 I
377777777R77
377777777777 00
L LAT
I
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00002
0
000
o 00006
434000000006
TIll1ll1U]'L
.,
T.
lonnn?
10
OllO .lL WalLO/'
~~
D ( 2. 2.pa.l)
L
I
100002
10
000
a
I
I
00003
+02.0
000
D
(0 .1 .0 .1
I
E
00001
+500
000
a
a
~
~
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q;
y
Q
G
--\-
0.
0..
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~
0
.l7"L7777tl7'L76.
3372777.17117 DQ.
)0002
3777771777771
377777777777 00
00000
002Q.QOOOOOOO
377777777777 00
0000 5
0500uOOOOO05
377777777777 00
-
C~ D 02 12 11 1)
LA ·C C RR
L Ei"R V·lAl 1
~~
L E R V.i"-2 3·
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IE Ie (0 .1 .3 .1
I
D 35 (02 12 12 1)
-I- -I-
LA ·c C R
L
,,'<
I
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L Ei"-R V."
R V· 1"-4
LA·
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E
R,
LA;- I--
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v,
I
L Ei"R V·
LA;-
~
E
R
LAI- f-
-...; (j
I
I--
LA·
(;
AS ER L· LE R V
Gp 0
~
CONSOLE INDICATORS
~ii«1~~:~ At//.;.) /;l"l111111/
Elf-T
E E~
Accumulator to Storage LAS
-I--
T'- I-
.1- I--
I I -I- ~
-
;::::-
TE IC (0 .1 .3 .1
N[ 0
N[ 0
( 2. 5. 5.1)
T R
M ST R I ·1 EA LV
I fAE
65
TO MEMORY DATA REG
Complement Magnitude (COM +0760 •.• 0006)
Replaces all l's with O's, and all O~s with lis, in the accumulator
Q,P ,1-35 positions. Accumulator sign is unchanged.
'FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
INSTR COUNTER (IC)
35
21
28
ADDRESS REG (AR)
35
5
35
21
21
35
(Q-35)
TO
MAR
MULTIPLIER-QUOTIENT REG (MQ)
UN IT ADDRESS
DECODER
UA=6
INST
LEGEND
+0760--6
COMPLEMENT MAGNITUDE
ALPHA CODE, ......:C~O::M.::..-_ _ _ __
- - - - - - -...~
1 CYCLE
-------...
E CYCLE
======~p"
L CYCLE
-------------.
CONTROL
~
+0760
11
S1
CYCLES,
......;1:..'.::(L;:..)_ _ _ _ _ _ __
~OO 000
T
18-20
28
1101
35
SEQUENCE NOTES,
THE C(AC)Q, P, 1-35 ARE COMPLEMENTED. THE AC(S) IS UNCHANGED.
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
INDEXING MAY CHANGE THE INSTRUCTION.
'SAVE AC(S)
CYCLES REQUIRED, 7040,
7044, I, L
FIGURE 25. COM
66
L
o
I
2 3 4
5
o
I
2 3 4
5
0
I
2 3 4
5 0
/3
'"
Location
Switches
2 3 4
I
5
o
I
1"/3
2 3 4
501
2 3 4
5 0
2 3 4
00000
00001
00002
00003
00004
00005
00006
I arl
llorl
I I te
I I te
Inst
Tag
Address
Octal Equiv
00006
00006
00001
050000 000006
076000 000006
002000 000001
5
~
/3
'"
I
CLA
COM
TRA
777m m777
Pattern
L Iorl
Lite
'"'"
~~ ~
I lat·
140
I
a~
'A
PC 0
~.
l,j
G ~ Fe·
b~ Foii ffa;
2 12 01)
SBi- R
Ie rly 'A 01
POP5 • P 9
~1
~
Complement Magnitude ern,.. ,
(0 .1.0 )
(28 3
~--<
I
:;{ii11J~~~ /1·1!.~} j,lilfllllllll
S( (0 .1 .31'>
G, h L 02 15 34)
Late·
SO 0
Er~
0
( 2.1
b.
T
"
00001
+500 000
o
00006
050000000000
000000000000 00
E
I
00001
+500 000
o
00001
777777777777
777777777777 00
I
L
00002
+760 00&
o
00006
076000000006
777777777777 00
L
I
00002
+760 006
o
00002
076000000006
777777777777 00
o
00001
002000000001
400000000000 11
5)
I ear Iy' 1[
( 01
I ar yo 2D
C iJ~
2-~ ~ P
.~
~
1- 5)
P'l- ~)
o (0
.1.1 )
I
I
00003
+020 000
I
L
00002
+760 006
0
00006
076000000006
400000000000 11
L
I
00002
+760 006
o
00002
076000000006
400000000000 11
I
I
00003
+020 000
o
00001
002000000001
777777777777 00
I
L
00002
+760 006
o
00006
076000000006
777777777777 00
I
00002
+760 006:
o
00002
076000000006
777777777777 00
07~O
I
-
C (0 .1 .2 )
L
em
CONSOLE INDICATORS
•• )OC~
67
Charge Sign (CHS +0760 ••• 0002)
Makes the accumulator sign negative if it is plus, and plus if it is negative.
The rest of the accumulator is unchanged.
TO MEMORY DATA REG
TO MEMORY DATA REG
Set Sign PI us (SSP +0760
00031
Sets the accumulator sign to plus.
I TIME POD 76,
760 NULL UA 2 + 3
02.04.07.1
02.04.40.1
02.04.42.1
"FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
2
21
21
35
21
21
35
TO
MAR
ACCUMULATOR REG (A C)
10
35
ADDRESS REG (AR)
ADDRESS REG (AR)
SC TO UNIT
ADDRESS DECODER
02.04.40.1
02.04.41;1
2
INSTR COUNTER ( IC)
INSTR COUNTER (Ie)
35
TO
MAR
ACCUMULATOR REG (AC)
17
4
5
COMPLEMENT
UNIT ADR DECODER
UA =02
INST
SSP
CHS
UA 3
UA 2
ALPHA CODE:
CHS
-------
SI
1(7040)
CYClES: I, L (7044)
~
+0760
l"2(DJ)"
02.10.71.1 (48)
02.02.00.1 (4E)
INST
+0760--02 CHANGE SIGN
COMPLEMENT AC(S)
r------------~
UNIT ADDR DECODER
UA = 03
11
T
18
20
I
+0760--03 SET SIGN PLUS
ALPHA CODE:
SSP
-------
00002
21
SET +
~
+0760
3S
SEQUENCE NOTES:
SI
CYCLES:
11
T
FIGURE 26. CHS,SSP
68
I
18
20
21
SEQUENCE NOTES:
CHANGE THE SIGN OF THE ACCUMULATOR. INDEXING MAY CHANGE
THE SIGN OF THE AC IS SET TO PLUS (0).
THE OPERATION. THE C(AC)Q, P, 1-35 ARE UNCHANGED.
INDEXING MAY CHANGE THE OPERATION.
THE C(AC)Q,P,I_35 ARE UNCHANGED.
INSTRUCTION
COMPLETE
L~~J.w)
----------------00003
35
~.
Ao AI A2 A. A A. AoA IA 2A.A4AsAoA IA 2A 3A 4A .AoA IA 2A 3A .A .AoA IA 2A 3A.A sA o AI A2 A.A4A sA oA IA 2A 3A.A.
fA.
lolA TE I
bt E R Iv
TE
Ci
lAi
fJ
i3 E RL
tiL
Ie rly
A3 1
T
~-t::: ~
sEi ... SR
l--"
000006
000002
000002
000000
377777 777777
Pattern
~iiV,11%~
~
!
00000
00001
00002
00003
00004
00005
00006
R~ D 02 12 08 1)
--
AD .... SC 10 17 02 12 37 .1)
:-
h4 ' S r
Is< Ir4 'lloj
IS'
~
~
Inst
CLA
SSP
SSP
TRA
Pattern
Tog
Address
Octal Equiv
00006
00003
00003
00000
050000
076000
076000
002000
. 5 ""r
.1 5
rr
~
TP
l- t-
0
'- ~ ~
a· t-
60N LL
L AR Y.A DI-
-I(](p
0
J......~
~"2
~
t?§. ?'
..Ci
~~
::t $
~
"Y
I--
I---
. I A3
u
'"
000006
000003
000003
000000
L ~T
£!~
~&<
J!
u
I
0
k. G
g
0
G~
~ J:::i
::
t';§'
0'
P •• ~ N
location
Switches
CONSOLE INDICATORS
...
~
G
... J:::i
~
02 1201 1)
5
o
050000
076000
076000
002000
V
POp
.tI L Ie
fAS 1
10
00006
00002
00002
00000
. Sian Ir.....~\
I
E
6( N LL (0 .0 .4 .1)
I L Ie ./-
tx
Octal Equiv
I LA E
A43 ~
lLa e'
CLA
CHS
CHS
TRA
Address
B LA E
'1-
'sc 'rrlr
Tog
I E RL
I
SOp (
Inst
E RL
E
I E RL
:P( D
00000
00001
00002
00003
00004
00005
00006
I
E RLW
T
Location
Switches
-...;; (j
-..;:
(..) (j
~
y
Q;:=
~
Y
-t?'
y
I
E
00001
+500
000
o
00006
050000000006
000000000000 00
E
I
00001
+500
000
o
00001
777777777777
777777777777 00
I
L
00002
+760
003
o
00003
076000000003
777777777777 00
L
I
00002
+760
003
o
00002
076000000003
777777777777 00
I
L
00003
+760
003
o
00003
076000000003
377777777777 00
377777777777 00
L
I
00003
+760
003
o
00003
076000000003
I
I
00004
+020
000
o
00000
002000000000
377777777777 00
E
00001
+500
000
0
00006
050000000006
377777777777 00
I
~
/;/
"v:-
C'----
I---
69
Make Storoge Sign Minus (MSM -1623.6)
TO MEMORY DATA REG
TO MEMORY DATA REG
Makes the specified memory location sign minus. The rest of the memory
word is Ulchanged.
Mak. Storog. Sign Plus (MSP -1623.7)
tv\akes the specified memory location sign plus. The rest of the memory
word is unchanged.
'FIRST CElL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
SET PARTIAL
STORE TGR
16 (D2)
02.15.34.1 (3H)
MAKE MINUS
RESET TO ZERO
ADDER (AD)
ADDER (AD)
'-.
YES
NO
ACCUMULATOR REG (A C)
ACCUMULATOR REG (A C)
INST
RESET PARTIAL
STORE TGR
E 6 (01)
02.15.34.1 (5H)
-1623--6 MAKE STORAGE SIGN MINUS
ALPHA CODE, ....;.M_S_M_ _ _ _ __ CYClES,
INST
I, E, E
-1623--7
ALPHA CODE, ....;.;M.;;;S.;.P_ _ _ _ __ CYClES,
-1623
S1
15 18 21
17 20
35
S1
11 12
13
15 18 21
17 20
SEQUENCE NOTES,
THE SIGN BIT OF C(y) IS REPLACED BY A 1 BIT (MINUS).
THE SIGN BIT OF C(y) IS REPLACED BY A ZERO BIT (PLUS).
THE REMAINDER OF Y IS UNCHANGED.
THE REMAINDER OF Y IS UNCHANGED.
POSITIONS 15-17 MUST CONTAIN
70
I, E, E
-1623
11 12
13
SEQUENCE- NOTES,
FIGURE 27. MSM,MSP
MAKE STORAGE SIGN PlUS
6a.
POSITIONS 15-17 MUST CONTAIN
35
E
o
I
2 3
4
5
o
I
2 3
4
5
0
I
2 3
4
5
o
I
E
2 3
4
0" I
5
2 3
450
I
2 3
450
I
2 3
4
location
Switches
Inst
00000
00001
00002
00003
MSM,6
MIT, 6
HPR
TRA
Tag
Address
Octal Equiv
00007
00007
562306
534106
042000
002000
5
I arl
00000
000007
000007
000000
00<)000
Ilple
~
e ,I
Make Stora g e S"'gn M"mu s (MSM)
I
E I Ie
E eo "Iy
I
~iv.1~
~
E 101
II Ie' 0 2·
0 6
t,;- '0' ftg
I
PC 0
kjf" IX -• 7 ~
C
,A' ,ti I ta, (
~~
no 1":"1=:: === ~
E oarl
E 01•• 501'
0 6· • RI
Ma ter E A1Pl0 6
-
~S
.
~ P
0'
E 101
Ell)
T
Ell)
(C .1 ~. 1)
E12}
o
p,
~~ R(
( 2.1 5. 0)
Q~SP
i:
0
<::-
t .Q
~!!
!;" ~
~~<
00001
"'"
'"
0«-
q,-cf",J",!~'~'V
! ;~
-
e tor c cl
~S/
)
~
15
16
15
16
15
16
15
16
15
1-1 S~ (S) (02.15 .20
.J9~~
~
~ Ol:'
0
0 ~(j ~ ~ ~ $'
i:
0
If>-
1
r-----
(0 .1.5<)
I. rI A 01
Location
E oed .ppO 62 I- tP II SI",e
-
==
. .- -
S"', cyple
20
ea Iy l- II Ie
l-
S I'" SB (0 .1.M)
S-I M R 02 12 50
_r-
or 16) ' /
I
Switches
Inst
00000
00001
00002
00003
00004
00005
00006
CLA
STO
MSP,7
PLT, 7
HPR
TRA
Tag
Address
Octal Equiv
00006
00007
00007
00007
050000
060100
562307
534107
042000
002000
400000
00000
Pattern
000006
000007
000007
000007
000000
000000
000000
En o (0 .1 .3)
Po ia Sh ,e
IV
I
Storue Si2n Plus MSP}
-
0-
CONSOLE INDICATORS
jiiv.1~~~~ /If I/.~~ j;lilfllllllll
I
Partial Store prevents:
End OP (02.12.35)
SeliC (02.12.36)
SR .... SB (02.12.40)
SB .... MOR (02.12.50)
~! M;M p
E
I
E
I
E
II
E..
II
E(I)
00001
+500
000
o
00006
050000000006
000000000000
00
00001
+500
000
o
00001
400000000000
400000000000
00
00002
+601
000
o
00007
060100000007
400000000000
00
00002
+601
000
0 00002
400000000000
400000000000
00
00003
·623
000
o
562307000007
400000000000
00
E(2)
00003
-623
000
0 00007
000000000000
400000000000
00
E(2)
I
00003
-623
000
0 00003
000000000000
400000000000
00
I
E
00004
-341
000
o
00007
534107000007
400000000000
00
E
L
00004
-341
000
0 00007
000000000000
400000000000
00
o
00005
000000000000
400000000000
00
+020
000
o
00000
002000000000
400000000000
00
+500
000
0 OOOO~
050000000006
400000090000
00
00005
-341
I
I
00006
E
E
00001
..
617
15
617
15
617
,.
,.617
617
000
I
~
617
00007
.,,"
L
I
,.
J
1
71
Low-Order Bi. Tes. (LBT +0760"
00011
TO MEMORY DATA REG
If accumulator bit 35 is a 1-, the computer skips the next instruction. If
bit 35 is a 0, the canputer takes the next sequential instruction.
P-Bi. Test (PBT -0760 ••• 00011
If accumulator P-bit is a 1, the computer skips the next instruction. If
is a zero, the canputer takes the next sequential instruction.
the P-bit
I TIME POD 76
UA 1, 760 NULL
02.04.07.1 (3G)
02.04.40.1 (3B)
02.04.45 (4A)
02.04.42 (3G)
*FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
2
2
INSTR COUNTER (Ie)
INSTR COUNTER (Ie)
+1 IF AC{P) = 1
21
21
35
*4
5
5
ADDRE SS REG (AR)
ADDRESS REG (AR)
3
21
21
35
3
35
seTO UNIT
ADDRESS DECODER
02.04.40.1
02.04.41.1
TO
MAR
TO
MAR
ACCUMULATOR REG (Ae)
ACCUMULATOR REG (A C)
UA DECODER
UA=OI
INST
-+0760--001
UA DECODER
UA=OI
ALPHA CODE: _LB_T_ _ _ _ __
PBT
NO
CYCLES:
~I,'-(~L)!...__ _ _ _ _ _ __
YES
S1
YES
11
18-20
28
35
PBT
CYCLES: --..:',:....:.:(L::..)_ _ _ _ _ _ _ __
~
-0760
S1
11
T
~ooOOOooll
18-20
28
35
NO
SEQUENCE NOTES:
IF AC(35) = 1, THE COMPUTER SK IPS THE NEXT INS TRUCTION AN D CONTINUES.
IF AC(35) = 0, THE COMPUTER TAKES THE NEXT SEQUENTIAL INSTRUCTION.
INDEXING MAY CHANGE THE INSTRUCTION.
*4 STEP I. C. BY 1 IF AC(35) = 1.
CYCLES REQUIRED: 7040: I
7044: I, L
72
ALPHA CODE:
~T ~oooooooll
SEQUENCE NOTES:
FIGURE 28. LBT,PBT
-0760--001 P BIT TEST
(LBT)
-+0760
NO
INST
LOW ORDER BIT TEST
IF AC{P) = 1, THE COMPUTER SKIPS THE NEXT INSTRUCTION AND
CONTINUES.
IF AC{p) = 0, THE COMPUTER TAKES THE NEXT SEQUENTIAL INSTRUCTION.
INDEXING MAY CHANGE THE INSTRUCTION.
*4. STEP I. C. BY 1 IF AC{P) = 1.
CYCLES REQUIRED: 7040: I
7044: I, L
L
I
0
I
2 3 4 5 0
I
2 3 4 5 0
I
2 3 4
5 0
I
2 3 4
5 0
2 3 450
I
c,~
~
"
I
2 3 450
I
Location
Switches
234 5
00000
00001
00002
00003
00004
00005
00006
P-
I or
I lot
L e rl
Inst
Tag
CLA
LBT
HPR
TRA
Address
Octal Equiv
00006
00001
00000
00000
050000
076000
042000
002000
000006
000001
000000
000000
000000 00000 I
Pattern
Lite
Low- rl
3 I·
y' ~
Ipcjb'5 l-'-~
• R9
I I teo
A D3
~
e·
G
S
( 2. 2. 7)
0
l.tv
~
Lite
SC D (0
L eprl 'A DI
En
N
RS ~~
RS 7
N
nc
s nc gr
a :.3!
• ra
/.....v:
~
y
~
v:
DOOO 1
+500
000
o
00006
050000000006
000000000000 00
I
+500 000
o
0000 I
000000000001
00000000000 I 00
OOOOc.
+760 001
0
00001
076000000001
00000000000 I
"v:
\:?
-...;;~
<1..0
v: Q-
G
-\- <\
<\
~ ~
00
L
I
00003
+760 001
o
00003
076000000001
000000000001 00
I
I
00004
+020 000
o
00000
002000000000
00000000000 I
Innflfll
500 000
o
00006
050000000006
000000000001 00
00
gr 02 10 74)
LL A( 35
Ll A( P
Late A5DI
a y rap·
~
XE
~(j
(0 .1 .3 )
0
SKIP
L ad ·A D'
Sk;
"
DO()O 1
lC
UA
CONSOLE INDICATORS
E
En OF tg
+ UA
'0
to L ( 2. 5. 4)
_S'~ ci
p~,
t:iiiilil:,~ ~~! jll~ /;l;tl!llllll/
(0 .1 .0)
II teo 5 I· A[ (2 -3 )
PC D X~
r
~,
I
- R 102 12 01)
~ ~~
V
5=
IC (02 .12.36
N(YI'
• Tf R'
135 in tl
accu
ulata
e uals ze o
this routine
an!!s UP with cv,
Ie t" be
L Indicator ON
I~: AR (0 . I .3)
Location
Switches
iref--
00000
00001
00002
00003
00004
00005
00006
L T; P 1
Tag
Inst
CAL
PBT
HPR
TRA
Address
Octal Equiv
00006
00001
00000
00000
450000
476000
042000
002000
000006
000001
000000
000000
400000 000000
Pattern
P-Bit TF'st (PR'T'1
I
CONSOLE INDICATORS
0;;{iiili~~ l,lll~~ ll;tl!llllll/
E
0000 l
- 500 000
o
00006
450000000006
000000000000 00
E
I
00001
- 500 000
0
00001
400000000000
000000000000 01
I
L
00002
-760 001
o
00001
476000000001
000000000000 01
L
I
00003
-760 001
0
00003
476000000001
000000000000 01
I
I
00004
+020 000
0
00000
002000000000
000000000000 01
I
E
00001
- 500 000
0
00006
450000000006
000000000000 01
I
f4-I
I
r
NOT] . If p_
7,er
t.h'
en'
'e
bn,
e
nn =ith curl
I~
T. ;nd;c,'n
W
nn
73
Divide Check Test (DCT +0760 ... 0012)
If the divide check indicator is on, it is turned off oro the computer takes
the next sequential instruction. If the divide check indicator is off, the
computer skips the next instruction.
I TIME POD 76
UA 12, 760 NULL
02.04.07.1 (3G)
02.04.41.1 (3F)
02.04.42 (4H)
*FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
2
INSTR COUNTER (IC)
' -_ _ _......._ _ _...J,. .+=I=I"'F=D=V=D=CHK TGR OFF
21
3S
*4
ADDRESS REG (AR)
SC TO UNIT
ADDRESS DECODER
02.04.40.1
02.04.41.1
21
21
JS
35
3
TO
MAR
ACCUMULATOR REG (AC)
MULTIPLIER-QUOTIENT REG (MQ)
UNIT ADDR DECODER
UA ~ 12
YES
NO
INST
lEGEND
+0760--012 DIVIDE CHECK TEST
ALPHA CODE, -:D"'C"'Tc......._ _ _ __
- - - - - - -..
~
I CYCLE
-------.
E CYCLE
•
-------------.
~
+0760
S I
STEP IC
L 4 (DI)*
02.12.36.1 (4F)
CYCLES, _:.!..I,....:(;::L)'----_ _ _ _ _ _ __
11
T
~OO 0010101
18-20
28
JS
L CYCLE
CONTROL
SEQUENCE NOTES,
IF THE DVD CHK INDICATOR IS ON, THE INDICATOR IS TURNED OFF AND
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMAllER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
THE COMPUTER TAKES THE NEXT SEQUENTIAL INSTRUCtiON. IF THE
INDICATOR IF OFF, THE COMPUTER SKIPS THE NEXT INSTRUCTION AND
CONTINUES. INDEXING MAY CHANGE THE INSTRUCTION.
CYCLES REQUIRED, 7040, I
7044, I, L
RESET DIVIDE
CHECK TGR
1101
02.10.22 (4B)
RESET SKIP
SYNC TGR
1201
02.10.74 (4F)
74
FIGURE 29. DCT
INSTRUCTION
COMPLETE
Location
Switches
Ao AI A2 A3 A. As Ao AI A2 A. A4 Ae Ao AI A2 A.A. As Ao AI A2 A.A. A. Ao AI A2 A. A4 A. Ao AI A2 A. A4 As Ao AI A2 A3 A4 As
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TO MEMORY DATA REG
Sens. Swi.ch T.s' (SWT +0760 ••• 0161 '00166)
If the switch tested is off, the computer takes the next sequential instruction.
If the switch is on, the computer skips the next instruction.
I TIME POD 76,
SOD 00
UA 1 - 6, SC 13
02.04.07.1
02.04.40-42
02.04.45
'FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
INSTR COUNTER (IC)
+1 IF SW ON
21
35
*4
5
ADDRESS REG (AR)
3
21
21
35
35
SC TO UNIT
ADDRESS DECODER
02.04.40.1
02.04.41.1
TO
MAR
ACCUMULATOR REG (A C)
MULTIPLIER-QUOTIENT REG (MQ)
U
ADDRESS DECODER
UA= I
6
'f
INST
LEGEND
NO
0161
+0760--0166 SENSE SWITCH TEST
ALPHA CODE:
-------t~.
1 CYCLE
-------.
E CYCLE
SWT
------+0760
S1
.
CYCLES: .....;I,'"'('"'L)'-_ _ _ _ _ _ __
W%iJ WA
II
T
18-20
016(X)
21
35
L CYCLE
-------------.
CONTROL
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
SEQUENCE NOTES:
IF SENSE SWITCH IS ON (1-6), THE COMPUTER SKIPS THE NEXT INSTRUCTION
AND CONTINUES.
IF THE SWITCH IS OFF, THE COMPUTER TAKES THE NEXT SEQUENTIAL INSTRUCTION.
INDEXING MAY CHANGE THE INSTRUCTION.
CYCLES REQUIRED:
7040: I
7044: I, L
FIGURE 30. SWT
76
L
o
I
2
3 4
5
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3 450
I
2
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Switches
I 2 3 4
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TRA
ADD
TRA
00000
00001
00002
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Address
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TO MEMORY DATA REG
TO MEMORY DATA REG
Storage Minus Test (MIT -1341.6)
If the sign of the specified memory location is minus, the computer skips the
next instruction. If tl-e sign is plus, the computer takes the next instruction.
Storege Plus Test (PLT -1341.7)
If the sign of the specified memory location is plus, the computer skips the next
instruction. Ifrthe sign is minus, the computer takes the next instruction.
II
I
I
'FIRST CelL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVel SETS THE
RECEIVING REGISTER
INSTR COUNTER (IC)
INSTR COUNTER (IC)
*2 IF SR(S) +
*2 IF SR{S)21
21
STEP +1
35
35
STEP + 1
ADDER (AD)
ADDER (AD)
ADDRESS REG (AR)
ADDRESS REG (AR)
21
35
21
TO
MAR
TO
MAR
(PLT)
NO
NO
YES
YES
NO
(MIT)
YES
-1341--6 STORAGE MINUS TEST
ALPHA CODE,
~M-"I.:.T_ _ _ _ __
INST
CYCLES,
1, E, (L)
-1341--7 STORAGE PLUS TEST
ALPHA CODE, ....:..PL::;T....:.._ _ _ __
11 12
13
15
17
18 21
20
CYCLES,
35
SEQUENCE NOTES,
IF THE SIGN OF LOCATION Y IS MINUS, THE COMPUTER SKIPS THE NEXT
INSTRUCTION.
S1
I, E, (L)
Y
-1341
Y
-1341
S1
78
ACCUMULATOR REG (A C)
ACCUMULATOR REG (A C)
INST
FIGURE 31. MIT,PLT
35
11 12
13
15
17
18 21
20
SEQUENCE NOTES,
IF THE SIGN OF LOCATION Y IS PLUS, THE COMPUTER SKIPS
THE NEXT INSTRUCTION.
IF THE SIGN IS PLUS, TAKE THE NEXT INSTRUCTION.
IF THE SIGN IS MINUS, TAKE THE NEXT INSTRUCTION.
CYCLES REQUIRED, 7040, I, E
7044, I, E, L
CYCLES REQUIRED,
7040, I, E
7044, I,E,L
35
l
E
o
I
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I 2 3 4
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5 0 I 2 3 450 I 2 3 4 5 0 I 2 3 4 5
o
I 2 3 4
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Inst
00000
00001
00002
00003
00004
00005
00006
CLA
STO
MIT
HPR
TRA
Tag
Address
Octol Equiv
00006
00007
00007
050000
060100
534106
042000
002000
5
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16
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02 12 36
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TRA
Address
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00006
00007
00007
050000
060100
534107
042000
002000
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Address
Octal Equiv
LXD
LXD
TRA
3'
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i
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Location
SWitches
077n7 000000
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00000
00001
00002
00003
00004
00005
00006
"Change tag to test remaining index register.
2~ ~
Tag
Inst
LDC
TRA
5'
Pattern
Address
Octol Equiv
00006
00000
453500 000006
002000 000000
000001 000000
*Chcn~e tag to test remaining index register.
X ( +B+C)
02 12 .16)
A ; D
,. ,e 'no.
i
from. Decre:ment (LXD)
CONSOLE INDICATORS
I
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'?' complement of accumulator bits 3-17 into the specified i:-tdex
register. The occumulotor is unchanged.
+0734 PLACE ADDRESS IN INDEX
A LPHA CODE: _'-PA"X'-'-_ _ _ __
CYCLES, _,,',..:(l,,'_ _ _ _ _ _ __
11
18 21
+{l737 PLACE COMPLEMENT OF ADDRESS IN INDEX
ALPHA CODE
y
.0734
S1
INST
~
PAC
CYCLES:
35
20
~TI
+{l737
S,
*FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
11
THE C(AC)21_35 ARE PLACED INTO THE SPECIFIED INDEX REGISTER(S).
**RESET OCCURS AT
BEGINNING OF DELAY
35
SEQUENCE NOTES·
lEVEL SETS THE
THE C(AC) ARE UNCHANGED.
Y
18 21
20
SEQUENCE NOTES:
RECEIVING REGISTER
" (ll
(S, 1-351
(S, 1-35)
THE 2'5 COMPLEMENT OF C(AC)21_35 ARE PLACED INTO THE SPECIFIED INDEX
REGISTER(S).
A TAG OF ZERO RESULTS IN A NO-OP,
1
THE C(AC) ARE UNCHANGED.
CYCLES REQUIRED: 7040: I
7044: I, L
A TAG OF ZERO RESULTS IN A NO-OP.
CYCLES KEQUIRED: 7040:
7044:
I, L
LEGEND
(PDX, PDC)
NO
YES
(PAX~ PAC)
COMPLEMENT TRANSFER PLUS "HOT I" TO ADDER
CAUSES 2'5 COMPLEMENT.
- - - - - - - I..~
1 CYCLE
-------..
E CYCLE
L CYCLE
SR (3-171 TO
-------------.-
SR (1-35) TO AD
l4 (D21
AD (21-35)
l4 (D21
02.12.09.1 (4C)
CONTROL
MULTIPLlER~QUOTIENT
02.12.08.1 (41)
MULTIPLIER-QUOTIENT REG (MQ)
REG (MQ)
XFER5 INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
TO MEMORY DATA REG
INST
(PAX, PDX)
NO
-0734 PLACE DECREMENT IN INDEX
ALPHA CODE: --'-P"-D"X_ _ _ _ __
-0734
~)TOAD
S1
_
11
INST
CYCLES, --",'-'(l,,'_ _ _ _ _ _ _ __
T
I
18-20 21
ALPHA CODE: _'-P"-DC-'--_ _ _ __
CYCLES, --':'"-'-'(l::.'_ _ _ _ _ _ __
y
y
-0737
35
5 ,
10 D2
02.12.13,I(SB)
(3-17)
18 21
11
20
35
(3-17)
SEQUENCE NOTES:
THE C(AC)3_17 ARE PLACED INTO THE SPECIFIED INDEX REGISTERS.
THE 2'S COMPLEMENT OF C{AC)3_17 ARE PLACED INTO THE SPECIFIED
INDEX REGISTER(S).
THE C(AC) ARE UNCHANGED.
THE C(AC) ARE UNCHANGED.
A TAG OF ZERO RESULTS IN A NO-OP.
CYCLES REQUIRED:
-0737 PLACE COMPLEMENT OF DECREMENT IN INDEX
A TAG OF ZERO RESULTS IN A NO-OP.
7040: I
7044: I
CYCLES REQUIRED: 7040:
I
7044: I
COMPLEMENT TRANSFER PLUS "HOT I" TO ADDER
CAUSES 2'S COMPLEMENT.
21
35
INSTRUCTION
COMPLETE
MULTIPLIER-QUOTIENT REG (MQ)
82
FIGURE 33.
PAX, PDX, PAC, pDC
MULTIPLIER-QUOTIENT REG (MQ)
L
o
2 3 4 5 0
I
I
2 3 4
5
0
2 3 4
I
5
0
I
/3
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a
Location
Switches
2 3 4 5
112 3 4 5 0
0
I~
a
I
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I
2 3 4 5 0
I
~rl~
I
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CLA
PAX
CLA
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L
Tag
Address
Octal Equiv
00006
00000
00007
00000
00000
050000
073400
050000
073400
002000
Locarion
Switches
I'
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00002
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00006
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100000
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100000
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02 12 20
et C (S) +
I ar y' 2D'
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Pattern
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Inst
00000
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Address
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(LA
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PI\A P~D
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Transfer on Index {T IX +20001
If the contents of the specified index register are greater than the decrement
fi,ld of the instruction word, the decrement is subtracted from the index
register and the computer takes the next instruction from the location specified by the address field of the instruction word. If the contents of the
specified index register are equal to or less than the decrement, the index
register is not decremented and the computer takes the next sequential instruction.
TO MEMORY DATA REG
I TIME
POD 00
"FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED nMING
LEVEL SETS THE
RECEIVING REGISTER
I
SB (S, 1-35) TO SR
13 (01)"
02.12.01.1
""RESET OCCURS AT
BEGINNING OF DELAY
I
Transfer on No Index (TNX -2000)
If the contents of the specified index register are greater than the decrement
field of the instruction word, the decrement is subtracted from the index
register and the computer takes thenect sequential instruction. If the contents of the specified index register are equal to or less than the decrement,
the index register is not decremented and the computer takes the next instruction from the location specified by tl-e address field of the instruction word.
SR (1-35) TO AD
14 (03)
02.12.0B.l (4E)
I
<
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AD (21-35) TO AR
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L 2 (03)
02.12.09.1 (4A)
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L2 (03)
02.12.13.1 (20)
02.12.13.1 (SO)
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02.10.41.1
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02.1S,35.1 (3A)
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X CARRY = DECREMENT ~ XR
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AS (01)
02.12.34.1 (40)
INST
LEGEND
(NO TRANSFER)
+2000 TRANSFER ON INDEX
ALPHA CODE, -'T.:;IX-'-_ _ _ __
I
(
MULTIPLIER-QUOTIENT REG (MQ)
(TIX)
/
\. NO
/
ACCUMULATOR REG (A C)
NEXT SEQUENTIAL
INSTRUCTION
)
-------I~~
1 CYCLE
----~-'"-
E CYCLE
o
SI 2 3
I
I
-------------.
XRX TO XR (A+B+C)"
L S (01) DELAYED
02.12.16.1 (48)
I TIME
.NEXT INSTR
I TIME
NEXT INSTR
HOT I TO AD 3S
L 6 (02)
HOT 1 TOAD 35
L6 (02)
sc
02.12.13.1 (Ie)
02.12.13.1 (SC)
Y
17
M 21
L CYCLE
NEXT INSTRUCTION
FROM MEMORY INDICATED
BY BITS 21-35
XR (A+II-!C) TO
AD (21-3S)
L 6 (02)
02.12.13.1 (SC)'
CYCLES, _...:I,..;(...:L)_ _ _ _ _ _ __
~TO
AD (21-35)
L 6 (02)
CONTROL
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
SEQUENCE NOTES,
IF THE CONTENTS OF THE SPECIFIED XR(S) ARE GREATER THAN THE 0, THE
INDEX REGISTER(S) IS REDUCED BY 0 AND THE COMPUTER TAKES ITS NEXT
INSTRUCTION FROM Y.
~
REDUCTIO~
IF C(XR)
0, NO
is.MADE AND THE COMPUTER TAKES THE
NEXT SEQUENTIAL INST.WITH A TAG OF ZERO, NO TRANSFER
CYCLES REQUIRED, 7040, I
7040, I, L
IF TAG = 0, TRANSFER 2', COMPLEMENT OF ZERO
TO AD FROM XR. X CARRY WILL ALWAYS OCCUR
02.12.13.1 (SC)
•• COMPLEMENT TRANSFER PLUS" HOT I" TO
ADDER CAUSES 2', COMPLEMENT
AR TO IC
II (01)'
02.12.36.1 (40)
AD (21-35) TO XRX"
L6 (01) DELAYED
02.12.IS.1 (4F)
ARTQIC
11 (01)"
02.12.36.1 (4D)
XRX TO XR (A+B+C)"
12 (01) DELAYED
02.12.16.1 (4G)
FIGURE 37. TlX, TNX
90
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y
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SI
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17
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18
20
21
I
35
N:I + I
-------------.
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XFERS INCLUDE ALL BITS CONTAINED IN
IF THE CONTENTS OF THE SPECIFIED XR(S) ARE GREATER THAN THE 0, THE
XR(S) IS REDUCED BY D, AND THE COMPUTER PERFORMS THE NEXT SEQ INST.
THE SMALLER OF THE TWO REGISTERS IN-
VOLVED, UNLESS OTHERWISE SPECIFIED,
I
ES T R
( E
IF
C(XR)~D,
NO REDUCTION IS MADE AND THE C'OMPUTER TAKES ITS NEXT
INSTRUCTION FROM Y.
I
I
_ _ A TAG OF ZERO Will RESULT "IN A TRANSFER.
I
CYCLES REQUiRED:
1
7040: r
7044: I, L
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C
0
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Transfer an Index TTY\
L
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ON XCAR
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I
"STEPS 4,5,6 CONDITIONAL
1
L fAT
I
SR -1
Octal Equiv
00003
00001
I
TP EI
L f"R Y
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Address
7
7
(D=l)
I
I
ER
I
Tag
AXT
TlX
I
02 15 34 1)
M ~S
Inst
00000
00001
00002
00003
00004
00005
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02 12 oa 1)
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TNX -
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Location
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~
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1/IIIIIIII~~O
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DEC
I I
D
SI 2 3
CONTROL
17
T
18
20
Y
21
------_.
IF THE CONTENTS OF THE SPECIFIED XR(S) ARE GREATER THAN D, THE
COMPUTER TAKES ITS NEXT INSTRUCTION FROM LOCATION Y.
CYCLES REQUIRED, 7040, I
7044, I, L
•
COMPLEMENT TRANSFER PLUS "HOT I" TO ADDER
CAUSES 21 s COMPLEMENT
92
TXL
I, (L)
CYCLES,
H
D
51 2 3
CONTROl
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
I I
T
17 IS
20
L CYCLE
-------------.
IF C(XR) IS ~ D, THE COMPUTER TAKES. ITS NEXT SEQUENTIAL
INSTRUCTION. WITH A TAG OF ZERO, NO TRANSFER OCCURS.
E CYCLE
35
SEQUENCE NOTES,
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
FIGURE 3S. TXH, TXL
-3000 TRANSFER ON INDEX LOW OR EQUAL
ALPHA CODE,
L CYCLE
-------------.-
(NO TRANSFER)
1 CYCLE
1 CYCLE
DEC ~ XR
INST
LEG E ND
CYCLES:
>DECREMENT
MULTIPLIER-QUOTIENT REG (MQ)
21
Y
35
SEQUENCE NOTES,
IF THE CONTENTS OF THE SPECIFIED XR(S) ARE LESS THAN OR EQUAL TO D,
THE COMPUTER TAKES ITS NEXT INSTRUCTION FROM LOCATION Y.
>
IF C(XR)
D, THE COMPUTER TAKES ITS NEXT SEQUENTIAL INSTRUCTION.
WITH A TAG OF ZERO, A TRANSFER OCCURS.
CYCLES REQUIRED, 7040, I
7044, I, L
COMPLEMENT TRANSFER PLUS" HOT I" TO ADDER
CAUSES 2'. COMPLEMENT
Location
Switches
Ao AI Az A3 A4 As Ao AI Az A3 A. As Ao AI A2 A, A. As Ao AI A2 A, A. As Ao AI A2 A, A4 As Ao AI A2 A, A4 As Ao AI A2 A, A. As
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00006
I
Inst
Tog
Address
Octal Equiv
AXT
TXH
(D=76)
HPR
HPR
AXT
TXH
(D=O)
TRA
7
7
00077
00004
077400 700077
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042000
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300000
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1 35
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Accumu otor LfSh
e t ift (AS
L +0767l
Couses the contents of the OC~t,l11')~9.!9i. (Q, P, 1-35) to be shifted left the
I TIME
POD 76
SOD 07
umber of ploces specified in bits 28-35 of the oddress portion of the instruc':"
ion word. The sign position is unchonged.
Ao AI Az As A4 A!S A AI Az As A4 A!S Ao AI Az A.A. A!SAo AI Az AsA4 A!SAo A.I A2 AsA4 A5Ao AI Az As A4 A5 Ao AI Az A. A. A.
'FIRST CELL DRIVER PULSE
FOLLOWING THE INDICATED
TIMING LEVEL SETS THE
RECI'IVIN"G REGISTER
I
M S RI
E, RL
"
SB TO SR
13 D1 ..
02.12.01 (4B,4E)
"
a
E
I~ E RL
~
SR TO AD
14D3
AS ER I
"
V
M ST R
ADDRESS REG (AR)
E RL
L iAT
I
/
YES
SC=O
?
\.
I
BLOCK SETTING
MQ.AC.SC
02.15.21(3A,4A,4B)
21
S~
/
/
\.
AC(I) =
1?
STEP SC
CLOCK RATE
D(SHIFT'GATE)
02.12.38(4A)
AC(P-35)LEFT
CLOCK RATE
D(SHIFT GATE)'
02.12.23(3B)
I
1
YES
I
YES
SC
10-15
ZERO
ENDOP
02.15.35(5G)
I
I TIME
OF NEXT
INSTRUCTION
I
T
SET AC
OVERFLOW
TRIGGER
02.10.41(38)
I
/
.
1
4 (SC AND
REDUCE BY I
CCUMULA TOR REG (A C)
C EF p.l 2. 3. )
~ -~
07
C T·
E A
FILL WITH
ZEROS
OVFLOW
scilo 1-1
Vi
(C • 5. 5- 2)
C LL DR VE
TE S T
2 ER
ET SC (0 .1 .3 .1
C LL pRI
INST
LEGEND
ALPHA CODE, -:.A;:L::.S_ _ _ __
- - - - - -__
.~
CYCLES:
S1
11
18-20
CONTROL
10 7 6 5 4 3 2
12
SC
28
=~~
o .1
AC 0 E L W
35
ENfl
SEQUENCE NOTES,
P 02 15 35 1)
sFl -1 =0',
S ift ns '
A 01--
/
E D
THE C(AC)Q,p, 1-35 ARE SHIFTED LEFT THE NUMBER OF PLACES INDICATED
IN 28-35. SIGN POSITION IS UNCHANGED. VACATED BITS FILLED WITH
ZEROS. A "I" SHIFTED OUT OF POS 1 TURNS ON AC OVFLOW.
7040 1-22/3
7044 2-7
0
1
S 1 -1 =
SC
C T N
L CYCLE
-------------.
14
~C
~T ~
+0767
~I
pi
I, L----
1 CYCLE
E CYCLE
~:
.O·
./
SC = IS
+0767 ACCUMULATOR LEFT SHIFT
CYCLES REQUIRED,
108
~
4
------~
c
-
~ -~
S EP C 0 ZE 0
~te "
spe
MULTIPLIER-QUOTIENT REG (MQ)
L4Dl
?
,
S E SC (0 .1 .3 .1
OC 7 P 9'
OJ
TO
MAR
~
qat 'A 03 I"
Sift Gote ~
hi
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
FIGURE 46. ALS
IF G TE (0 .1 .1.1
E d ~A D37
e fly "
A 03
\.
~:I~:~i;f">'
I
35
NC
.
YES
21
35
A
(r Ul
067
)
C
18
Ll'T
P G
.4 .1
Location
Switches
00000
00001
00002
00003
00004
00005
00006
. I
Inst
CLA
ALS
TRA
Pottern
Tag
Address
Octal Equiv
00006
00044
00000
050000 000006
076000 000044
002000 000000
377777 777777
~ft ~hHt
r
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NOT : To c ear ace mulat r Dve flo
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n
n
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depre • RESET.
109
TO MEMORY DATA REG
Accumulator Right Shift (ARS +0771)
Causes the contents of the accumulator (Q, P, 1-35) to be shifted right the
number of places specifi eel in bits 28-35 of the address portion of the instruction word. The sign position is unchanged.
'F IRST CELL DRIVER PULSE
FOLLOWING THE INDICATED
TIMING LEVEL SETS THE
RECEIVING REGISTER
2
INSTR COUNTER (IC)
21
35
AD(28-35)
TO SC(10-17)
15Dl'
02. 12.37(3D)
ADDRESS REG (AR)
35
21
21
35
3
(SCIO)
BRING UP
SHIFT GATE
LO-I3
02. 15.15(1G)
4
TO
MAR
ACCUMULATOR REG (A C)
REDUCE BY 1
4
MULTIPLIER-QUOTIENT REG (MQ)
4
FILL WITH ZEROS
NO
BLOCK SETTING
MQ.AC.SC
02. 15.21(3A,4A,4B
02. 15.25(2A)
STEP SC
CLOCK RATE
D(SHIFT GATE)'
02. 12.38(4A)
O~.liL,:J7
AC(Q-:4)RIGHT
CLOCK RATE
D(SHIFT GATE)'
INST
LEGEND
02.12.22(~)
ALPHA CODE:
1 CYCLE
"",""" , ! . , - - - - - - - - - - - -.....---;rr:--......
+0771 ACCUMULATOR RIGHT SHIFT
------__
ARS
-----S1
=======••~
L CYCLE
-------------.
CONTROL
Wf@T~
+0771
E CYCLE
CYCLES:~I,~L,~-_-_--_________________
11
18-20
28
SC
35
YES
YES
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
SEQUENCE NOTES:
THE C(AC)Q P 1-35 ARE SHIFTED RIGHT THE NUMBER OF PLACES INDICATED
IN 28-35. T~E SIGN POSITION IS UNCHANGED. VACATED BITS ARE FILLED
WITH ZEROS.
CYCLES REQUIRED: 7040 1-22/3
7044 2-7
FIGURE 47. ARS
110
L
o
Location
Switches
I 2 3 4 5 0 I 234 5 0
I 234 501 234 501
00000
00001
00002
00003
00004
00005
00006
a
a
I
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Tag
Inst
Address
Octal Equiv
00006
00042
00000
050000 000006
077100 000042
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CLA
ARS
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I I te'I---i-+-+-~ (2E-3 I) ..... S( (0 • I • 7)
fo.5 I' POp
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I
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2 12 39)
( -3 )IT( 2.2.2)
I
E
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500
000
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000000000000
00
E
I
00001
t
sao
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0
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nnnnn I nn?nnnnnoonn
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00
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00
~.-----~
I
E
0001
050000000006
Shift Counter == 0 prevents:
Set MQ (02.15.21)
Set AC (02.15.25)
Set SC (02.12.37)
~R:>
071
111
Rotote MQ Left (RQL -0773)
The contents of the MQ register (5,1-35) are shifted left the number of
places specified by the address portion of the instruction word. The sign
position shifts into position 35; thus, the register becomes a closed loop.
TO MEMORY DATA REG
I TIME
POD 76
SOD 13
I
*FIRST CELL DRIVER PULSE
FOLLOWING THE INDICATED
TIMING LEVEL SETS THE
RECEIVING REGISTER
SB TO SR
13 DI*
02.12.01(4B,4E)
I
SR TO AD
14D3
0.<.1l..01l (4£)
I
AD(28-35)
TO SC(IO-I7)
15DI*
02.12.37(3D)
I
L TIME
02.15.34(3G)
I
BRING UP
SHIFT GATE
LO-13
02.15.15(lG)
I
~~N°--~l------+i-----==~
BLOCK SETTING
MQ .AC. SC
02.15.2l(3A,4A,4B)
~i.1NWtJ)
STEP SC
CLOCK RATE
D(SHIFT GATE)*
02.12.38(4A)
MQ(l-35)LEFT
CLOCK RATE
D(SHIFT GATE)*
02.12.28(3B)(3F)
I
1
REDUCE BY I
ACCUMULATOR REG (A C)
4
MQ S TO MQ35
CLOCK RATE
D(SHIFT GATE)*
02.12.28(5H)
INST
-0773 ROTATE MQ LEFT
ALPHA CODE:
YES
I
END OP
02.15.35(5G)
I
I TIME
OF NEXT
INSTRUCTION
FI GURE 48. RQL
112
4
MULTIPLIER-QUOTIENT REG (MQ)
4
lEGEND
YES
0
SC
TO
MAR
I
SC
10-15
ZERO
/
L4DI
\
?
-------.~..
1 CYCLE
-------...
E CYCLE
RQL
-------
CYCLES:
I, L, ---
-0773
S,
SC
11
18-20
28
35
l CYCLE
-------------.
CONTROL
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
SEQUENCE NOTES:
THE C(MQ)S,I-35 ARE SHIFTED LEFT THE NUMBER OF PLACES INDICATED IN 28-35.
THE SIGN BIT IS CONNECTED TO THE 35 BIT FORMING A CLOSED SHIFTING LOOP.
NO BITS ARE LOST.
CYCLES REQUIRED:
7040: I - 2 2/3
7044: 2-7
Rotate MO Left (R.OL)
I
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M ST R I
M ST R
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o L
E
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~
~
EA LY
EA L
~ I ul~E
I ~T
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P: C N PO)
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A3Dl
/'~
I L Ie
'
A43
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r.::: f;;
OC 7 bl ck
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7 . R 9 ... SH FT IN T ( 2. 12. 8.1)
B .. ~ R ( 2. 2. 1. )
PCD ~,
1 L Ie
A5 1
I La
R
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10.,
02. 1237 1) SC = 1 18 )
D 8- 5 .. S 1(-1
'
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<:0 TO lEI
I or
o
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3/
---
TC L
M ST R
• L EI'-R
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TE S
TE S
Sift gat ,
0
0[1
M:;)'S
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S EF SC T( Z RC
S ;i O'rELC RI E
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L"Taf.
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S I .1 = 0,
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AD
HD
II
+- f-
~
~
~
N[ 0
Q:'
-!:2
"r~"
lnst
LDO
ROL
TRA
Tag
Address
Octal Equiv
00006
00377
00000
056000 000006
477300 000377
002000 000000
777777 m777
Pattern
-t?
00001
+560
000
0
00006 056000000006
000000000000
00001
+560
000
0
00001
777777777776
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377
0
00377
477300000377
777777777776
L(l}
L(Z}
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-773
371
0
00377
477300000377
77777777ID'L
L(Z)
L(3)
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-773
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0
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Rotate MO Left (R.OL)
1777777767777
~(3)
L(4)
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-773
355
0
00377
477300000377
L(4)
L(5)
OOOOZ
-773
347
a
00377
477300nno377
L(5)
L(6)
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341
0
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I
lonn,.
-TI3
3113
LIiZI
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l;l13}
L(14}
L 14
0
I
CONSOLE INDICATORS
jiiV,1it~ ~ ~'j0, ~
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Switches
00000
00001
00002
00003
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CONSOLE INDICATORS
jii«1it;4~ /!'!/tJ
t.v
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Location
"ezz'
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-773
173
0
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L(Z3)
L(Z4)
10000,
-773
165
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P G
L(31)
OOOOZ
-773
113
0
00377
477300000377
77777777776
I..L311. L.l3Z)
OOOOZ
-773
lOS
0
00377
477300000377
'r177777777677
Lin)
L(33)
OOOOZ
-773
077
0
00377
477300000377
77777767777
LI331
L1341
OOOOZ
"773
071
0
00377 477300000377
77776777777
I..(34)
L(35)
OOOOZ
-773
063
0
00377 477300000377
77677777777
351
36
Oooz
_77'
OS'
.IL
477300000377
67777777777
on~77
113
Execute (XEC +0522)
Causes the computer to execute the instruction at the location specified by
the address portion of the instruction word. The computer then returns to
the location plus 1 of the Execute instruction.
"
lAli
0000~
IH
Il
L TE
IE RL
Il
L
Il
TE
E
I A LY'
l"'3 1~
S
I L TE "
EC
fi1
A45D
I.....
(
S~
050000
052200
052200
052200
002000
040000
042000
000006
000005
000005
000004
000000
000006
000000
~""'"
I A
T R
S Ef IC
1-'- I-
11fo-DlT
l-
.12. 1.1
1M TE
~ l-
A4 1
I L TE
A4 3 ~
I~ -t/2D
RS T
R
r.
Y
b oc ed
OF TC R'
I L T 'A ~1
C
~""'"
i--
if
34. l' p2. 12·iJs·l)
P2. 12. 1
(0.1 .3 .1)
1:- ~AR
( 2. 2. 4. )
i:-
( 55 N EC)
A
II
10 ke
b XfC
~~
I
~
t- I
~~~-
I AT
A D2
~'- l-
(2.1 2.
R SE
~. )
I« 1'- f::" l-
TFx V
10
! D2
he
ft
l-:J~! R (
~.
3 •1
R o toi s 00)
ad" et R' Tr nsf r
(7 0)
~
SR.
ti not e j str cti n pe ifi d Y t e on ent of 70 , pe
ucton in 0' (st pi).
r e ec
(0 .1
k d; C, m ins 50
It.:!p" SB I-- SR
r
t
S EP IC
ro ror
c ntj ue ur til
he ne, t
5
qu ntj I
$>
1
02. 14.06(4F)
HP'
0
St rt gr
l-.....-+-~B~0:iic~t~~((i;,. .I4115i.;<•.ol;:;!99).........~~_~!-+-~1 m7tei-;";
II teO 5 l'
~a te st
10 e'
0 Itor (0 .1 .0
4 2
0
«
0[
lAs
p t r ,.
P 0 sto t . (I 2. 4. 6)
l'
H R·lfti,tit
L
234 5
p'
1
Slart tgr
r
TIME"
I I te
j~~gr'
0 ... 15".34 (3G)
(0
L (0 .1 .3)
G, to E
Sartke'
a y ey
St rt ~r
21402)
A 01
L at·
r PR
Block tgr prevents:
the generation of E- L early (02.1S.31)
Master Stop tgr prevents:
memory select (02.15.16), except for
B or C cycles.
set of I late tgr (02.15.30)
En
0
(0 .1 • 3~)
I I teo 5[ l'
En 0 tg·
E -T ns er
,... ast r I
J 0
I ~or y'
301
I lot·
SB TO PR,
TAG,POS REGS
13D2
02. 12.32(4E)
• FIRST CELL DRIVER PULSE
FOLLOWING THIS INDICATED
TIMING LEVEL SETS THE
RECE IVI NG REG I STER
SB TO SR
1301'
(4£),
02.12.01(4B)
~f.+ R 02 1234
I....:~~
Fo ce ra
SBL... R ~.!:. 32
RESET MASTER
STOP TGR
A4D2
02.14.05(4E)
RESET START
TGR
A5Dl
02. 14.02(4H)
RESET BLOCK
TGR
A5Dl
02.15.39(5D)
FIGURE 50. HPR
115
Transmit (TMT -1704)
This instruction moves words from one area of storage to another. Bits 28-35
of the address portion of the instruction word specify the number of words to
be transmitted. Prior to executing the Transmit instruction, the accumulator
must be set up so that bits 3-17 contain the starting "from" address, and bits
21-35 contain the starting tltoll address. As each word is transmitted f the
from and to addresses are incremented one, and the word count is decremented
one. Words are transmitted until the word count (shift counter) reaches zero.
A maximum of 255 words can be transmitted by a single transmit instruction.
At the completion of the transmission, AC 3-17 contains the address of the
last word read, plus 1, and AC 21-35 contains the address of the last word
stored, plus 1. Another TMT instruction can be given to transmit more words.
Ao AI Az A. A. A. Ac AI A2 A. A. A. Ao AI Az A. A. A. Ao A I A. A. A. A. Ao AJ A. A. A. A. Ao AI A. A. A. A. Ao AI A. A. A4 A.
I
L
ERA
5 Of
'E f EA
E TO E
I
I I6.T
:J~
PR
POD 71<'
......... 5R 1- 5 A (0: I .0 .1 )
I ilAT~.ApD ~~
AD 28 35
C (0.1 .3 .1
POD 7X Blocks ( 0 TO E WITH I,LATE) (02.15.34.1)
f.:
pC TC L
~~-I-++-I
M 5T R
f
• L E Riff
lI1'-T
Tf,HI ___
L A LY A
*FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
",cr·.
fDli-(::::,~
R (0 .1 .90.1
M ·E +l at •
TI T EA'
~ ~Ej~l--
T.T·+Lae·
E DOl TC R.~_
16.5 I
NOTE,
AFTER INITIALL CYCLE,
E CYCLE ARE REQU IRED
UNTIl 5C = O.
( 2. 2. 9. I)
5 3- 7 ~ 0 1- 5
R5
,_
R
fAD\-t A
I-
(2. 2. 5.) _
1_
(2. 2. 4. ) _
PCD O' + ,LTE·,
EN
T~
Et'lO 0
T~T
NO
AD (21-35) TO AR
EORL5(DI)
02.12.34.1 (4C)
5ET TMT READ
EARLYTGR_
RE5ET TMT READ
LATE TGR
E\J'l!)c})
E 3 (DI)
02. 10.90. It4B)
02.10.90.1 (4E)
E
I~
TRA
-:t~~I ..""""-+--+--1
AD·
P G • ?
L T
E RL •
3 I·
( 2. 2. I)
5T
M
(0 .1 .9 .1
I>
t-
D
(0 .1 .4 .1
5 ~- ~5
E
02 15 34.1)
~~~--I~~~~~~-+-+-+-+-+++~-I--I--I-~~
L at\-
5BI- 5R
o TC
.bl-l-+-+-++-I
Te R•
02 10 90. I)
M R AD EA
5~-
A
~ I-
-
~
xc pt 3- 7
R AC EJ L
E
E·
AD j-
qA ~
1-
e
T.UA
LT
( 2. 2. O. I)
T, T·
M
1
E RL •
REj'.D EA LY \-r-5
TI T EA
5B TO 5R
E 3(DI) *
02.12.01.1(4C,4F)
E fAT
ce~-1
A DI
M·
I--
M 5T R • E EA L
CJi;C
02 12 50
P5
E RL
q,
fAA TE
o-+-++.X"-t1D1 ~-~
Pr te ted Lol-J.-
5ET TMT READ
LATE TGR
E 3 (D2)
02.10.90.1 (4D)
TNTfea< Lae.t--f:::::~!I" I 2 J.- 1-1-
AD G N
--::i-
AD - t A
M
R AC LI TE
~2 I· c.--'
5 0 E yc e'
J 201-
10 3 A
8
A DI
T~
L
(0 .1 .!P.I)
(0 .1 .1 .1
I 0
(0 .0 .1 .1)
I)
-
c-="""
TAT E AR y.~ blocks 5B.-, 5 3- 7
M
T( RE C
__ O[ I
M ·E A LY,_
T REA
E R
y-p:p:_
(0 .Ie .9(.1)
(0 .1 .5 .1)
5T P C (02.1 .3 .1)
(0.1 .0.1
R AC EI> RL
( 2.15. 5. I)
*~!-....
Tr T
+, L
N 'C P
TEI...-.jP01""-+-l-+-~E~D 0
IAlmll'
I E Riff
FIGURE 51.
116
T
INSTR COUNTER (IC)
21
35
,-----------,
I
I
I
INDEX REGS (XR)
XR 1
I
I
Il ____________ _
XR 2
XR 4
21
21
35
35
CI17
TO
MAR
MULTIPLIER-QUOTIENT REG (MQ)
INST
LEGEND
-1704--C
ALPHA CODE:
- - - - - - - - . . . ,..
~
1 CYCLE
------__
E CYCLE
TRANSMIT
TMT
-------
CYCLES:
I, (L)
+ ZN
-1704
S1
Y
11
18-20 21
28
35
L CYCLE
-----~-------.
CONTROL
SEQUENCE NOTES:
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
117
Set Protect Mode (SPM -11 '0)
Causes the field register to be set to the high-order seven positions of instruction word 21-35, and the count register to be set,to instruction word 32-35.
Count register posi.tion 32 determines the mode of protection (1 for trap on
equal, 0 for trap on unequal). Count register positions 33-35 determine the
number of high-order positions of the field register that are to be compared
with any store address. An attempt to store into a protected area of memory
results in a memory protect trap.
If the computer is already in the memory-protect mode when the SPM instruction is given, an instruction trap results, placing the location of the SPM
instruction plus 1 in the address part of location 32. Bit 16 is set on (indicating a violation), protect-mode is turned off" and the computer takes its next
instruction from location 33.
If SPM is gIven on a machine that does not have the memory-protect option, a
no-operation results and the computer tokes its next instruction from the next
sequential location.
1 TIME
POD 16
NO
IS MP MODE
SET ?
END OP
14 (01)
02.15.35.1 (2A)
RESET COUNT
FIELD REGS
A4.5 (01)
02.16.02.1 (51)
YES
I
SET MP
VIOLATION
15 (01)
02.16.05.1
I
t
END OP
02.15.35.1 (2A)
I
TRAP
I CYCLE
SR TO AD
14 (03)
02.12.08.1 (4E)
I
TRAP
E CYCLE
I
AD (21-24) TO
FIELD REG (21-24)
15 (01)
02.16.02.1
AD (25-27) TO
FIELD REG (25-27)
15 (01)
02.16.03.1
SR (32-35) TO
COUNT REG
15 (D1)
02.16.01.1 (51)
I
RESET MPV
E5 (01)
02.16.05.1 (4H)
I
I
ENOOP
E3 (06)
02.15.35.1 (38)
SET MP MODE TGR
16 (01)
02.16.05.1 (4A)
(
FIGURE 52. SPM
118
SPECIFIED AREA IN )
MEMORY PROTECTED
I
o
I
2 3 4 5
o
2 3 450
I
I
2 3 4 5
I
o
I
2 3 450
;;~
~
"
2 3 450
I
2 3 450
I
~
Ie rI
I
2 3 4 5
c~
~
1 e rI
I I Ie
I I Ie
En
I ate.·A ·5!>1·
SM
I I Ie (4.41 3
I lot -A D1
sFf,I
I I te [A5 1SPf'I
0
I I Ie
(0 .1 .3 )
I~ r:.e
S
. cc~nl
.... ~(o
l-I-
fi~ld re
(0 .1 .0)
.1 .01)
D 2137 -+ iel r~ ( 1- 7) 02 .1.
l-
~
32 35
I eprl •
APD'
SM
.... 0
nt iet
/(~)
(0 .1 .01)
Ii 'r d tg (0 .1 .0)
~\ Plop
SIMI
I
r set
I
I
I
Location
Address
Octal Equiv
SPM
TRA
00000
00104
TRA
SPM
HPR
TRA
00106
00000
00100
516000
002000
000000
002000
516000
042000
002000
00106
002000 000106
Switches
Inst
00100
00101
00102
00103
00104
00105
00106
00032
00033
TRA
I
Tag
- - --- ... ----
000000
000104
000000
000106
000000
000000
000100
,-, '"
I
CONSOLE INDICATORS
jii~tjlJh~/JIJl-:~ //~ftlllllll/
I
1
bOloO
+OZO
000
o
00100
I
1
0101
-160
000
a
00101
516000000000
0
I
1
a 10Z
+OZO
000
o
00104
OOZOOOOOO 104
I
I
1
00105
-160
000
a
00105
516000000000
I
I
E
bOlOS
000
000
o
0003Z
04Z000000000
1
Ii'
T
'n In'
I nnn
nnn In
nnn"
nonnn >on~ !(L5
0
T
Oon34
I
+OZO
000 10
onlnb
onznnnnnn 106
0
T
nn 1n7
.nzn
onn In
nnlnn
I nn>nnnnon IOn
0
OOZOOOOOO 100
f.4--
f--
119
Release Protect Mode (RPM -1004)
If the computer is in memory-protect mode, this instruction turns the memoryprotect mode off and traps to location 32 (sets bit 15). if the computer is not
in memory-protect mode, this instruction traps to location 32 and sets bit 14.
In either case, the computer takes its next instruction from location 33.
'FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
NO
1 TO AR (35)
E 5 (02)
02.13.09.1 (50)
FIGURE 53. RPM
120
YES
RESET MP
VIOLATION TGR
RESET MP
MOOE TGR
E 5 (01)
E 5 (01)
02.16.05.1 (4H)
02.16.05.1 (48)
E
011
2 :3 4 5 0 I 2 :3 4 5 0
I
p~
~
ct
2 :3 4 5 0
I
2 3 4 5 0
I
Location
Switches
2 :3 4 5 0
<#l
~
Ci
Mjm de tgr (02 16.0S
5 M
2 3 4 5 0
I
I
Ci
5 M'
I
larl
'A DI
a d e ad r
PR
o
~... RF
·0 • FR
f.;..
5 or ge ra
(0 • 1.( V>
I I~te A5PI
~
ro
PI '1 lot
I I~te ·A D
t P S[~
res t
la e.
I D2 (0 .1 .0 )
~~
516000 000000
500400 000000
bit 3 an 3 ((iz.l .(9)
C0
P E (0
.1 .3 )
rrl
·A D
m ste
E
~~
f,\A
e rI 'A D2
ma te I
( 2. 2. 0)
I
e rl
an tr p
~
~
g
Rf-o B ( 2. 2. 0)
II 9 S~ 1 ( 2.1 3. 2)
RM E e rI •
, P od
II g S~ 1 ( 2. 3. 1)
E or y·t OD •
,;, f.. R ( I- S) (0
a y top
~
S or cy Ie.
A Dl
00033
<
~..Q
v~
~
?:- ~
:i:..J
""l
vO
(5
,,'I:
~
$
c§>
'<
~
~
~{?
<5 t $
t; J? ..-!,
Q.:
~
I
I
{)0100
+020
000
0
00100
002000000100
I
E
00 t 0 I
-004
000
0
00032
500400000000
E
I
00 I () I
-004
000
0
00033
000010000101
'<
.$'
(]~ r7
(j
......
'< ~\
~
(j
'<
0-'
0:
~ '-->~
"-.:
A
0
.;l 4;~
J....:..~
~¢;
;:::..j~Q?.{5~~
19 cf
& ~
0'<
J J
6"
Q..'
Q.'V
~,2 1I~
T R
( 2. 12. 4- 5)
ICf-o AR (0 .1 .3 .1)
Bi::'S'T CT-
a
U E
AR- C 02 12 36 .1)
G
II
:::::1-
1
IS
( 3. O. O. )
Transfer on _Redundancy Check (TRCA +0022)
(TRCB
(TRCC
(TRCD
(TRCE
-0022)
+0024)
-0024)
+0026)
Ao AI A2 A, A4 A. Ao AI A2 A, A. A. AoAI A2A, A. A. AoAI A2 A, A. A. Ao A.o A2A, A. A. Ao AI A2 A, A.A. AoAI A2 A, A. A.
~A TEl
If the redundancy-check indicator for the specified channel is on, it is
turned off and the computer takes its next instructiom from the address
portion of the instruction word. If the indicator is off, the computer takes
the next sequential instruction.
ATE I
01 EA L
E~RL
AT
'" LA E
E R
[i3 EA L'I
If channel parity is enabled, the TRC will not transfer and will not turn the
redundancy-check indicator off.
(TEFA +0030)
(TEfB
(TEfC
(TEfD
(TEfE
I
I E RL
-0030)
+0031)
-0031)
+0032)
I
If the end-of-file indicator for the specified channel is on, it is turned off
and the computer takes its next instruction from the address portion of the
instruction word. If the indicator is off, the computer takes the next sequential instruction.
If channel end is enabled, the TEF will not transfer and will not turn off the
end-of-file indicator.
( 2. 14. 18. )
P D 2 ' 1" '1;. +. RC
( 2. 4.18. )
D~
I Lat •
hi ck
R 02 12 34 1)
}C TC L
Got 'l':
Gpt E
L E
R ~I D p2. 12 08 1)
-
I Lot·
ASD
oeo
I
P 6 ..' EF
I Lat·
A4D:I-
E
A~LY
T
P D 2
R )N
( H ELA 2. 4.48 I)
[LA
f3
f3 UTE
Transfer on End of File
MAS ER L' L Ef'R Y
L /AT
[fRCA)
NO
YES
[fEfA)
I at
P D
H D PP 02 15 35 1)
~>
END ( P G
YES
YES
NO
/ EF •
-I eo Iy
( 3. O. 4. )
E F G
A DI·
'~ft; IT
E~ ~ ,'-Ef ,-
-
( H
C,"D M T 03 30 04.1)
f--
I
/I~~ I~
R T R 03 30 03 I)
"INB P
qlB A IT ~
H
CN
A D •
IT
M T (03 .30.0 .1)
TR A
CH A N I ~ ET·
PCD 2
"-
H N
R~NS
(0 .1 .0 .1
RA~S ~C NC M T ( 2.12. 02.1)
,
I
N 0 T ~R
LLa • A5 [:1I ....'I
TR N C N ~ ET
-
-~
E ET
R (02 12 34 35
C +, R 15 N EC
fA 000
R A 002
E D pP "
rly Al
pi V ~
~R
.1
( 2. 2. 6. )
II e
YES
RESET RC IND TGR
12 (DI)
03.30.03.1 (41)
FIGURE 57. TRCA,TEFA
NO
NO
RESET EOF TGR
12 (Dl)
03.30.04.1 (5C)
125
TO MEMORY DATA REG
Store location and Trap (STR -1000)
Execution of this instruction causes trapping to location 00000, where the
instruction counter count (location of the STR plus 1) is stored in positions
21-35. The computer then transfers to location 00002. Bits 12-35 of the
instruction word are not interpreted by the computer.
*FIRST CELL DRIVER PULSE
FOLLOWING THE
INDICATED TIMING
LEVEL SETS THE
RECEIVING REGISTER
YES
RESET
NO
I------'---'-L ________
~C..:.IL
____ _
+1
,
2
ADR GEN
00000
ADR GEN 00002
ADDER (AD)
INDEX REG S (XR)
XR 1
XR 2
XR 4
35
21
21
35
RESET
4
TO
MAR
ACCUMULATOR REG (A C)
INST
LEGEND
MULTIPLIER-QUOTIENT REG (MQ)
-1000 (+0000) STORE LOCATION AND TRAP
(-000&)
CYCLES,
ALPHA CODE, .....:.S:.:.TR=--_ _ _ __
- - - - - - -..
~..
1 CYCLE
-------...
E CYCLE
-1000
S1
=======..
L CYCLE
-------------.
CONTROL
_~I,~E_ _ _ _ _ _ _ _ __
11
12
35
SEQUENCE NOTES,
THE LOCATION OF THE STR INSTRUCTION + 1 IS PLACED IN C(OOOOO)21_35.
XFERS INCLUDE ALL BITS CONTAINED IN
THE SMALLER OF THE TWO REGISTERS INVOLVED, UNLESS OTHERWISE SPECIFIED.
C(00000)S_20 ARE CLEARED.
THE COMPUTER TRANSFERS TO LOC 00002.
FIGURE 58.
126
STR
,
I
E
0 I 2 3 4 5 0 I 2 3 4 5 0
I 2
p~
~
Ol
3 4 5 0 I 2 3 4 5 0 I 2 3 4 5 0
2 3 4 5 0
r-~
~
Ol
Ol
E ate
I Ie
I I Ie M
Fira
(0
~
AR re
Octal Equiv
TRA
TRA
00100
00103
002000 000100
002000 000103
STR
00000
500000 000000
Tag
I
~
I E (02 .15.3
rf
O~
E eor y' 001'
a y t ap
'" rly·
an ljap
~~
~
f.:
R ( 1- 5)(0 .1 .0
R f.~ B ( 2. 2. 0)
m st r I
2!!
c e rly
M R ( 2. 2. 0)
i'-o
~~:J
~- ~D
(
.12.
o 0
E I Ie
En
0
(0 .1 .3 )
~~
Q;-
~
?:.F
I
I
00100
+020
000
o
00100
02000000100
I
I
00101
+020
000
o
00103
02000000103
I
E
00104
-000
000
o
00000
500000000000
E
I
00104
-000
000
o
00002
00000000104
I
I
00003
+020
000
o
00100
02000000100
O:j
..;u
~
0
J? {i:',y
Q;;'
~0',p
~
0
~¥ ;!?II:u:~~cf:'0Oy
f.4-I---
M. R
P)
S ~re cy Ie
A2 1
E I Ie • 5 2'
ST •
a y rap
f;:.
/; jlllllll/
$
,,~<
<
~
i:;-
foY
a y t op
I
CONSOLE INDICATORS
t/ G~~ ~~l 3;~~ iF ff? ~~~$ ~
~:~
jii~1#'~
I ( 2. 13.pa)
rrosl r E'
c e rly 'A D2
Address
lnst
Store Location and Trap (STR)
1~ I (0 .1 .3 )
I I Ie jA5 l'
S R'
Ira ~
IIC + 1 --00000
00000
00002
00100
00101
00102
00103
E arl
I eprl
I I Ie
I
Location
Switches
I 2 3 4 5
34 (02 .13.01
I
Xler __ 00002
5 R
127
Transfer and Restore Traps (TRT -1164)
Turns on the trap-control trigger. The computer transfers to the location
specified by the address portion of the instruction word.
Transfer and Restore Parity and Traps (TRP 1165)
Turns on the trap-control and parity-mode triggers. The computer transfers
to the location specified by the address portion of the instruction word.
FIGURE 59. TRT, TRP
128
Enable ham Y (ENS +0564)
The contents of Y (location specified by address portion of imtruction word)
0
ore used to set the channel mask bits to 1 or O. Execution of each enable
instruction cancels the effect of previous enable instructions. The enable
instruction turns on channel trap control.
I
2 3 4 5 0 I 2 3 4 5 0
I
2 3 4 5 0
O!
I
2 3 4 5 0
I
E
I or
O!
E alE
E S'
A DI
I TIME
POD 56
I
RESET TRAP
PRIORITY TGR
(D INST)
03.30.09.1 (4C)
1
I
Ie'
~0 ~
'Ed fp"t,
1
SET PRIV
INST TGR
A5 (D2)
02.13.04.1 (5H)
RESET TRAP ENA8LES
TGRS 15 (D1)
03.30.06.1 (5H)
I
I
T
ENS AT
I E
«p.3 .C )
(0 .3p.06)
(5- 5)
1
1
SB (35) TO ENB
END
E5 (D1)
03.30.06.1 (4E)
1
I
I
RESET PRIV INST TGR
15 (D1)
)
I
UI~T
(0 .3( .0 )
EtS
E S'
d)l
SS (8) Eto- S·
t'-5 1
E~
S
E~
S
E~
S END (0 .3 .0 )
~
TT 03 30 06
ri
~~ ~; Ix
En
0
(0 .1 •
(13. O. 6\
i st. Eto- B
Ne
II
peD
SB (17) TO ENB
PARITY
E5 (D1)
03.30.06.1 (4C)
R 02 12 01
SR (-) Eto- S·
t'-5 1
fpm pre io si st. Eto- S
1
I
b t e i 51 CT
E S'
I!P1
58 (3 H~S'
~5 1
INSTRUCTION
COMPLETE
t
C cl
2.15.b4
E 8'
A D1
I TIME OF
NEXT
INSTRUCTION
ENS
G
ENS END ( 3. O. 6)
END OP
02.15.35.1 (3C)
FIGURE 60.
es
I
1
(
ho ne Irlp c nt 01 gr 02 13 03
SE (1 'E~S
t'-5 1
58 (8) TO ENB
ATT
E5 (D1)
03.30.06.1 (4A)
1
I
N'
or 1
E 8'
A D1
I
SR(S) TO ENS
BUF INT
E 5 (DI)
03.30.06.1 (4G)
es to A 101 of he fol ow ng
Ef-IS po,ly 03 30 06
SB (5-35) TO SR
E3 (D1)
02.12.01.1
T
riv ins Ig (0 .1 .0)
SET CHANNEL
TRAP CONTROL TGR
AO (D1)
02.13.03.1 (3C)
E TIME
02.15.34.1 (3A)
I
NE'
5C
:~ ~I .:,:~1 ~
ENS SU IN
O!
rI
I I Ie
Ipp ri< it Ig (0 .3 .0 )
2 3 450 I 2 3 4 5
2 3 450 I
{3
O!
)
!!!.!~~f' S.I.~~.l(~l_ll~l?~ 1~J_.'0160 ... 0(14)
TUllu nil dlOlll1el trap \'01111\,1. lhi~ ollowli tlnp5 III OCCll1" Oli !\p(>cified by Ih"
pl('vhlll5 (,,!lablE' imllUdi('ll1. It concel!, the inhibiting l'Iffed nf 011 ('I~("(·"t('ld
hop III un IC T imlluditll1.
Ao AI A, A. A. A. Ac AI AI A, A. As Ao AI AlA, A. As AoAI Az A, A. A. Ao AI A,A, A. As Ao AI Az A, A. A. AoAI A.A, A. A.
VvlI ST R I
NjAS ER I
l!!.bl~;.! t"hol1fwl IIt1p~ {It"l -.1;6l1 ..~
, lIAR Y
, E RL
lUlm (,H \'l1ulIlI(>III(111 nmlltll. Ihh inhibih oil ('hanfll"1 tlopsl1l1d nirec:t dotl1
IIOpli until UI1 Rt"I in51nrclilm 111 II II(>W I NA illlilnrdinll h given.
, It)
'L TE
E
/1 [ RL
/' Ell L
/1 LA E
/' LA [
I E Riv
RY
I
I L TE
LTE
R bN
I TIME
rOD 76
SO::> 00
CI S
1
I l to·
T
A43
SR TO AD
14 (D3)
02.12.08.1
I l to·
pcp
AS I
I
I
rR TO CHA NN cL
DECODER
02.04.48.1
I
o
~ ~ I- ~
~
i--'-- ~
l[(
o
~ ~::
b' I\..
.1
C ()_ 7 (0 .1 .3- .1)
8- 5
l
I~H 2. 4. 1.
m~ ~.--"
o
TC L
A TE L L A LY
L LA E
SCD 10' ~A 14~
L at 'A DI 'P S '-
-t:::: ~
R T
H N
/OC Q{.
~E T V-P CT L 06.13 03.1)
/
I
\.
PR(S) PLUS?
'\ NO
/
I
RESET CHANNEL
TRAP CONTROL TGR
LO (DI)
02.13.03.1 (4E)
I
I
I
(
I
r
SET PRIV INST TGR
LO DI
02.13.04.1 (4H)
( C + CT
IC
RS-
1
I TIME OF NEXT
INSTRUCTION
S D)Q
U
1\
RI
I~
A DI
ST (0 .1 .0 .1)
A5i)2
L at
"l'-
£tD bp 02 15 35 I)
S DOl---
R T . ( 6 1- 0114
Un-
END OP
02.15.35.1 (2D)
RESET PRIV INST TGR
15 (D1)
02.13.04.1 (41)
AI4
A DI'
ICT
SET CHANNEL
TRAP CONTROL TGR
LO (DI)
02.13.03.1 (3D)
INSTRUCTION
COMPLETE
Lc t.
"
T
YES/
I
CHA NHL R P TR (0 .I.C p.I
T
L TlM[
02.15.34.1 (3G)
130
.c
70 NU L 0204 42 I)
0 '-1-- f::::
SC TO UNIT
ADDRESS DECODER
02.04.40. I
02.04.41.1
1
FIGURE61. RCT,ICT
T ( 2.IM. 1m.1)
S - A (0 .1
I-
Sh 4·
1
SC TO CLASS
ADDRESS DECODER
02.04.42.1
RCT
76 S D 01
~I'
liD (26-35) TO SC
10 (DI)
02.12.37.1
I
I( be
1 60 -004
N
I~~
OP Tj;R
COMMENT SHEET
IBM 7040-44 CENTRAL PROCESSING UNIT
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