STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs And STM8L151/L152, STM8L162, STM8AL31, STM8AL3L Lines Reference Manual
User Manual:
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- 1 Central processing unit (CPU)
- 2 Boot ROM
- 3 Flash program memory and data EEPROM
- 3.1 Flash and EEPROM introduction
- 3.2 Flash and EEPROM glossary
- 3.3 Main Flash memory features
- 3.4 Memory organization
- 3.4.1 Low-density device memory organization
- 3.4.2 Medium-density device memory organization
- 3.4.3 Medium+ density device memory organization
- 3.4.4 High-density device memory organization
- 3.4.5 Proprietary code area (PCODE)
- 3.4.6 User boot area (UBC)
- 3.4.7 Data EEPROM (DATA)
- 3.4.8 Main program area
- 3.4.9 Option bytes
- 3.5 Memory protection
- 3.6 Memory programming
- 3.7 Flash low-power modes
- 3.8 ICP (in-circuit programming) and IAP (in-application programming)
- 3.9 Flash registers
- 4 Single wire interface module (SWIM) and debug module (DM)
- 5 Memory and register map
- 6 Power control (PWR)
- 7 Low power modes
- 8 Reset (RST)
- 9 Clock control (CLK)
- 9.1 Introduction
- 9.2 HSE clock
- 9.3 HSI clock
- 9.4 LSE clock
- 9.5 LSI clock
- 9.6 System clock sources
- 9.7 Peripheral clock gating (PCG)
- 9.8 Clock security system (CSS)
- 9.9 RTC and LCD clock
- 9.10 BEEP clock
- 9.11 Configurable clock output capability (CCO)
- 9.12 Clock-independent system clock sources for TIM2/TIM3
- 9.13 CLK interrupts
- 9.14 CLK registers
- 9.14.1 System clock divider register (CLK_CKDIVR)
- 9.14.2 Clock RTC register (CLK_CRTCR)
- 9.14.3 Internal clock register (CLK_ICKCR)
- 9.14.4 Peripheral clock gating register 1 (CLK_PCKENR1)
- 9.14.5 Peripheral clock gating register 2 (CLK_PCKENR2)
- 9.14.6 Peripheral clock gating register 3 (CLK_PCKENR3)
- 9.14.7 Configurable clock output register (CLK_CCOR)
- 9.14.8 External clock register (CLK_ECKCR)
- 9.14.9 System clock status register (CLK_SCSR)
- 9.14.10 System clock switch register (CLK_SWR)
- 9.14.11 Switch control register (CLK_SWCR)
- 9.14.12 Clock security system register (CLK_CSSR)
- 9.14.13 Clock BEEP register (CLK_CBEEPR)
- 9.14.14 HSI calibration register (CLK_HSICALR)
- 9.14.15 HSI clock calibration trimming register (CLK_HSITRIMR)
- 9.14.16 HSI unlock register (CLK_HSIUNLCKR)
- 9.14.17 Main regulator control status register (CLK_REGCSR)
- 9.14.18 CLK register map and reset values
- 10 General purpose I/O ports (GPIO)
- 10.1 Introduction
- 10.2 GPIO main features
- 10.3 Port configuration and usage
- 10.4 Reset configuration
- 10.5 Unused I/O pins
- 10.6 Low power modes
- 10.7 Input mode details
- 10.8 Output mode details
- 10.9 GPIO registers
- 11 Routing interface (RI) and system configuration controller (SYSCFG)
- 11.1 RI and SYSCFG introduction
- 11.2 RI main features
- Figure 23. Routing interface (RI) block diagram (medium+ and high-density devices)
- Figure 24. Routing interface (RI) block diagram (medium-density devices)
- Figure 25. Routing interface (RI) block diagram (low-density devices)
- 11.2.1 RI functional description
- 11.2.2 I/O groups
- 11.2.3 TIM1 input capture routing
- 11.2.4 TIM2 & TIM3 routing
- 11.2.5 Comparator routing
- 11.2.6 DAC routing
- 11.2.7 Internal reference voltage routing
- 11.3 RI interrupts
- 11.4 RI registers
- 11.4.1 Timer input capture routing register 1 (RI_ICR1)
- 11.4.2 Timer input capture routing register 2 (RI_ICR2)
- 11.4.3 I/O input register 1 (RI_IOIR1)
- 11.4.4 I/O input register 2 (RI_IOIR2)
- 11.4.5 I/O input register 3 (RI_IOIR3)
- 11.4.6 I/O control mode register 1 (RI_IOCMR1)
- 11.4.7 I/O control mode register 2 (RI_IOCMR2)
- 11.4.8 I/O control mode register 3 (RI_IOCMR3)
- 11.4.9 I/O switch register 1 (RI_IOSR1)
- 11.4.10 I/O switch register 2 (RI_IOSR2)
- 11.4.11 I/O switch register 3 (RI_IOSR3)
- 11.4.12 IO group control register (RI_IOGCR)
- 11.4.13 Analog switch register 1 (RI_ASCR1)
- 11.4.14 Analog switch register 2 (RI_ASCR2)
- 11.4.15 Resistor control register (RI_RCR)
- 11.4.16 Control register (RI_CR)
- 11.4.17 IO mask register 1 (RI_IOMR1)
- 11.4.18 IO mask register 2 (RI_IOMR2)
- 11.4.19 IO mask register 3 (RI_IOMR3)
- 11.4.20 IO mask register 4 (RI_IOMR4)
- 11.4.21 I/O input register 4 (RI_IOIR4)
- 11.4.22 I/O control mode register 4 (RI_IOCMR4)
- 11.4.23 I/O switch register 4 (RI_IOSR4)
- 11.4.24 RI register map and reset values
- 11.5 SYSCFG registers
- 12 Interrupt controller (ITC)
- 12.1 ITC introduction
- 12.2 Interrupt masking and processing flow
- 12.3 Interrupts and low power modes
- 12.4 Activation level/low power mode control
- 12.5 Concurrent and nested interrupt management
- 12.6 External interrupts
- 12.7 Interrupt instructions
- 12.8 Interrupt mapping
- 12.9 ITC and EXTI registers
- 12.9.1 CPU condition code register interrupt bits (CCR)
- 12.9.2 Software priority register x (ITC_SPRx)
- 12.9.3 External interrupt control register 1 (EXTI_CR1)
- 12.9.4 External interrupt control register 2 (EXTI_CR2)
- 12.9.5 External interrupt control register 3 (EXTI_CR3)
- 12.9.6 External interrupt control register 4 (EXTI_CR4)
- 12.9.7 External interrupt status register 1 (EXTI_SR1)
- 12.9.8 External interrupt status register 2 (EXTI_SR2)
- 12.9.9 External interrupt port select register (EXTI_CONF1)
- 12.9.10 External interrupt port select register (EXTI_CONF2)
- 12.9.11 ITC and EXTI register map and reset values
- 13 Direct memory access controller (DMA)
- 13.1 DMA introduction
- 13.2 DMA main features
- 13.3 DMA functional description
- 13.3.1 DMA transactions
- 13.3.2 DMA arbiter
- 13.3.3 DMA channels
- Figure 34. Endianess in 16-bit mode
- Figure 35. Regular channel (medium-density devices)
- Figure 36. Regular channel (medium+ and high-density devices)
- Figure 37. Memory channel with MEM=0 (medium-density devices)
- Figure 38. Memory channel with MEM=0 (medium+ and high-density devices)
- Figure 39. Memory channel with MEM=1 (medium-density devices)
- Figure 40. Memory channel with MEM=1 (medium+ and high-density devices)
- Table 36. Source and destination addresses
- 13.3.4 DMA1 request mapping
- 13.3.5 DMA hardware request description
- 13.4 DMA low power modes
- 13.5 DMA interrupts
- 13.6 DMA registers
- 13.6.1 DMA global configuration & status register (DMA_GCSR)
- 13.6.2 DMA global interrupt register 1 (DMA_GIR1)
- 13.6.3 DMA channel configuration register (DMA_CxCR)
- 13.6.4 DMA channel status & priority register (DMA_CxSPR)
- 13.6.5 DMA number of data to transfer register (DMA_CxNDTR)
- 13.6.6 DMA peripheral address high register (DMA_CxPARH)
- 13.6.7 DMA peripheral address low register (DMA_CxPARL)
- 13.6.8 DMA channel 3 peripheral address high & memory 1 address high register (DMA_C3PARH_C3M1ARH)
- 13.6.9 DMA channel 3 peripheral address low & memory 1 address low register (DMA_C3PARL_C3M1ARL)
- 13.6.10 DMA memory 0 address high register (DMA_CxM0ARH)
- 13.6.11 DMA memory 0 address low register (DMA_CxM0ARL)
- 13.6.12 DMA channel 3 memory 0 extended address register (DMA_C3M0EAR)
- 13.6.13 DMA register map and reset values
- 14 Analog-to-digital converter (ADC)
- 14.1 ADC introduction
- 14.2 ADC main features
- 14.3 ADC functional description
- 14.3.1 General description
- 14.3.2 Number of analog channels
- 14.3.3 ADC on-off control
- 14.3.4 Single conversion mode
- 14.3.5 Continuous conversion mode
- 14.3.6 ADC clock
- 14.3.7 Analog watchdog
- 14.3.8 Interrupts
- 14.3.9 Channel selection (Scan mode)
- 14.3.10 Data integrity
- 14.3.11 DMA transfer
- 14.3.12 Configurable resolution
- 14.3.13 Data alignment
- 14.3.14 Programmable sampling time
- 14.3.15 Schmitt trigger disabling
- 14.3.16 Temperature sensor
- 14.3.17 Internal reference voltage conversion
- 14.4 ADC low power modes
- 14.5 ADC interrupts
- 14.6 ADC registers
- 14.6.1 ADC configuration register 1 (ADC_CR1)
- 14.6.2 ADC configuration register 2 (ADC_CR2)
- 14.6.3 ADC configuration register 3 (ADC_CR3)
- 14.6.4 ADC status register (ADC_SR)
- 14.6.5 ADC data register high (ADC_DRH)
- 14.6.6 ADC data register low (ADC_DRL)
- 14.6.7 ADC high threshold register high (ADC_HTRH)
- 14.6.8 ADC high threshold register low (ADC_HTRL)
- 14.6.9 ADC low threshold register high (ADC_LTRH)
- 14.6.10 ADC low threshold register low (ADC_LTRL)
- 14.6.11 ADC channel sequence 1 register (ADC_SQR1)
- 14.6.12 ADC channel sequence register 2 (ADC_SQR2)
- 14.6.13 ADC channel select scan 3 (ADC_SQR3)
- 14.6.14 ADC channel select scan 4 (ADC_SQR4)
- 14.6.15 ADC trigger disable 1 (ADC_TRIGR1)
- 14.6.16 ADC trigger disable 2 (ADC_TRIGR2)
- 14.6.17 ADC trigger disable 3 (ADC_TRIGR3)
- 14.6.18 ADC trigger disable 4 (ADC_TRIGR4)
- 14.6.19 ADC register map and reset values
- 15 Digital-to-analog converter (DAC)
- 15.1 DAC introduction
- 15.2 DAC main features
- 15.3 DAC functional description
- 15.3.1 DAC channel x enable
- 15.3.2 DAC output buffer enable
- 15.3.3 DAC output switch configuration
- 15.3.4 DAC data format
- 15.3.5 DAC conversion sequence
- 15.3.6 DAC output voltage
- 15.3.7 DAC trigger selection
- 15.3.8 DAC DMA request
- 15.3.9 DAC DMA underrun interrupt
- 15.3.10 Noise generation
- 15.3.11 Triangle-wave generation
- 15.3.12 Dual DAC conversion
- 15.4 DAC registers
- 15.4.1 DAC channel x control register 1 (DAC_CHxCR1)
- 15.4.2 DAC channel x control register 2 (DAC_CHxCR2)
- 15.4.3 DAC software trigger register (DAC_SWTRIGR)
- 15.4.4 DAC status register (DAC_SR)
- 15.4.5 DAC channel x right aligned data holding register high (DAC_RDHRH)
- 15.4.6 DAC channel x right aligned data holding register low (DAC_CHxRDHRL)
- 15.4.7 DAC channel x left aligned data holding register high (DAC_CHxLDHRH)
- 15.4.8 DAC channel x left aligned data holding register low (DAC_CHxLDHRL)
- 15.4.9 DAC channel x 8-bit data holding register (DAC_CHxDHR8)
- 15.4.10 DAC channel x dual mode right aligned data holding register high (DAC_DCHxRDHRH)
- 15.4.11 DAC channel x dual mode right aligned data holding register low (DAC_DCHxRDHRL)
- 15.4.12 DAC channel x dual mode left aligned data holding register high (DAC_DCHxLDHRH)
- 15.4.13 DAC channel x left aligned data holding register low (DAC_DCHxLDHRL)
- 15.4.14 DAC channel x dual mode 8-bit data holding register (DAC_DCHxDHR8)
- 15.4.15 DAC channel x data output register high (DAC_CHxDORH)
- 15.4.16 DAC channel x data output register low (DAC_CHxDORL)
- 15.4.17 DAC register map and reset values
- 16 Comparators (COMP)
- 16.1 COMP introduction
- 16.2 COMP main features
- 16.3 Comparator 1 (COMP1)
- 16.4 Comparator 2 (COMP2)
- 16.5 Using the comparators in window mode
- 16.6 COMP low power modes
- 16.7 COMP interrupts
- 16.8 COMP registers
- 16.8.1 Comparator control and status register 1 (COMP_CSR1)
- 16.8.2 Comparator control and status register 2 (COMP_CSR2)
- 16.8.3 Comparator control and status register 3 (COMP_CSR3)
- 16.8.4 Comparator control and status register 4 (COMP_CSR4)
- 16.8.5 Comparator control and status register 5 (COMP_CSR5)
- 16.8.6 COMP register map and reset values
- 17 LCD controller
- 17.1 LCD controller introduction
- 17.2 LCD controller main features
- 17.3 LCD functional description
- 17.3.1 General description
- 17.3.2 Frequency generator
- 17.3.3 Common driver
- Figure 57. 1/3 bias, 1/4 duty
- Figure 58. Static duty
- Figure 59. Liquid crystal display and terminal connection (static duty)
- Figure 60. Liquid crystal display and terminal connection (1/2 duty, 1/2 bias)
- Figure 61. Liquid crystal display and terminal connection (1/3 duty, 1/3 bias)
- Figure 62. Liquid crystal display and terminal connection (1/4 duty, 1/3 bias)
- Figure 63. Liquid crystal display and terminal connection (1/8 duty, 1/4 bias)
- 17.3.4 Segment driver
- 17.3.5 Enabling a segment
- 17.3.6 Blink
- 17.3.7 Multiplexing COM[7:4] and SEG[43:40], SEG[39:36], or SEG[31:28]
- 17.3.8 Generation of LCD voltage levels
- 17.3.9 LCD buffer update
- 17.4 LCD controller low power modes
- 17.5 LCD controller interrupts
- 17.6 LCD controller registers
- 18 Timer overview
- 19 16-bit advanced control timer (TIM1)
- 19.1 TIM1 introduction
- 19.2 TIM1 main features
- 19.3 TIM1 time base unit
- 19.4 TIM1 clock/trigger controller
- Figure 79. Clock/trigger controller block diagram
- 19.4.1 Prescaler clock (CK_PSC)
- 19.4.2 Internal clock source (fSYSCLK)
- 19.4.3 External clock source mode 1
- 19.4.4 External clock source mode 2
- 19.4.5 Trigger synchronization
- 19.4.6 Synchronization between timers
- Figure 89. Timer chaining system implementation example
- Figure 90. Trigger/master mode selection blocks
- Figure 91. Master/slave timer example
- Figure 92. Gating timer B with OC1REF of timer A
- Figure 93. Gating timer B with the counter enable signal of timer A (CNT_EN)
- Figure 94. Triggering timer B with the UEV of timer A (TIMERA-UEV)
- Figure 95. Triggering timer B with counter enable CNT_EN of timer A
- Figure 96. Triggering Timer A and B with Timer A TI1 input
- 19.5 TIM1 capture/compare channels
- Figure 97. Capture/compare channel 1 main circuit
- Figure 98. 16-bit read sequence for the TIM1_CCRi register in capture mode
- 19.5.1 Write sequence for 16-bit TIM1_CCRi registers
- 19.5.2 Input stage
- 19.5.3 Input capture mode
- 19.5.4 Output stage
- 19.5.5 Forced output mode
- 19.5.6 Output compare mode
- 19.5.7 PWM mode
- Figure 106. Edge-aligned counting mode PWM mode 1 waveforms (ARR = 8)
- Figure 107. Center-aligned PWM waveforms (ARR = 8)
- Figure 108. Example of one-pulse mode
- Figure 109. Complementary output with deadtime insertion
- Figure 110. Deadtime waveforms with a delay greater than the negative pulse
- Figure 111. Deadtime waveforms with a delay greater than the positive pulse
- Figure 112. Six-step generation, COM example (OSSR = 1)
- 19.5.8 Using the break function
- 19.5.9 Clearing the OCiREF signal on an external event
- 19.5.10 Encoder interface mode
- 19.5.11 Timer input XOR function
- 19.5.12 Interfacing with Hall sensors
- 19.6 TIM1 interrupts
- 19.7 TIM1 DMA
- 19.8 TIM1 registers
- 19.8.1 Control register 1 (TIM1_CR1)
- 19.8.2 Control register 2 (TIM1_CR2)
- 19.8.3 Slave mode control register (TIM1_SMCR)
- 19.8.4 External trigger register (TIM1_ETR)
- 19.8.5 DMA request enable register (TIM1_DER)
- 19.8.6 Interrupt enable register (TIM1_IER)
- 19.8.7 Status register 1 (TIM1_SR1)
- 19.8.8 Status register 2 (TIM1_SR2)
- 19.8.9 Event generation register (TIM1_EGR)
- 19.8.10 Capture/compare mode register 1 (TIM1_CCMR1)
- 19.8.11 Capture/compare mode register 2 (TIM1_CCMR2)
- 19.8.12 Capture/compare mode register 3 (TIM1_CCMR3)
- 19.8.13 Capture/compare mode register 4 (TIM1_CCMR4)
- 19.8.14 Capture/compare enable register 1 (TIM1_CCER1)
- 19.8.15 Capture/compare enable register 2 (TIM1_CCER2)
- 19.8.16 Counter high (TIM1_CNTRH)
- 19.8.17 Counter low (TIM1_CNTRL)
- 19.8.18 Prescaler high (TIM1_PSCRH)
- 19.8.19 Prescaler low (TIM1_PSCRL)
- 19.8.20 Auto-reload register high (TIM1_ARRH)
- 19.8.21 Auto-reload register low (TIM1_ARRL)
- 19.8.22 Repetition counter register (TIM1_RCR)
- 19.8.23 Capture/compare register 1 high (TIM1_CCR1H)
- 19.8.24 Capture/compare register 1 low (TIM1_CCR1L)
- 19.8.25 Capture/compare register 2 high (TIM1_CCR2H)
- 19.8.26 Capture/compare register 2 low (TIM1_CCR2L)
- 19.8.27 Capture/compare register 3 high (TIM1_CCR3H)
- 19.8.28 Capture/compare register 3 low (TIM1_CCR3L)
- 19.8.29 Capture/compare register 4 high (TIM1_CCR4H)
- 19.8.30 Capture/compare register 4 low (TIM1_CCR4L)
- 19.8.31 Break register (TIM1_BKR)
- 19.8.32 Deadtime register (TIM1_DTR)
- 19.8.33 Output idle state register (TIM1_OISR)
- 19.8.34 DMA control register 1 (TIM1_DCR1)
- 19.8.35 DMA control register 2 (TIM1_DCR2)
- 19.8.36 DMA address for burst mode (TIM1_DMAR)
- 19.8.37 TIM1 register map and reset values
- 20 16-bit general purpose timers (TIM2, TIM3, TIM5)
- 20.1 TIM2, TIM3 and TIM5 introduction
- 20.2 TIMx main features
- 20.3 TIMx functional description
- 20.4 TIMx interrupts
- 20.5 TIMx registers
- 20.5.1 Control register 1 (TIMx_CR1)
- 20.5.2 Control register 2 (TIMx_CR2)
- 20.5.3 Slave mode control register (TIMx_SMCR)
- 20.5.4 External trigger register (TIMx_ETR)
- 20.5.5 DMA request enable register (TIMx_DER)
- 20.5.6 Interrupt enable register (TIMx_IER)
- 20.5.7 Status register 1 (TIMx_SR1)
- 20.5.8 Status register 2 (TIMx_SR2)
- 20.5.9 Event generation register (TIMx_EGR)
- 20.5.10 Capture/compare mode register 1 (TIMx_CCMR1)
- 20.5.11 Capture/compare mode register 2 (TIMx_CCMR2)
- 20.5.12 Capture/compare enable register 1 (TIMx_CCER1)
- 20.5.13 Counter high (TIMx_CNTRH)
- 20.5.14 Counter low (TIMx_CNTRL)
- 20.5.15 Prescaler register (TIMx_PSCR)
- 20.5.16 Auto-reload register high (TIMx_ARRH)
- 20.5.17 Auto-reload register low (TIMx_ARRL)
- 20.5.18 Capture/compare register 1 high (TIMx_CCR1H)
- 20.5.19 Capture/compare register 1 low (TIMx_CCR1L)
- 20.5.20 Capture/compare register 2 high (TIMx_CCR2H)
- 20.5.21 Capture/compare register 2 low (TIMx_CCR2L)
- 20.5.22 Break register (TIMx_BKR)
- 20.5.23 Output idle state register (TIMx_OISR)
- 20.5.24 TIMx register map and reset values
- 21 8-bit basic timer (TIM4)
- 21.1 TIM4 introduction
- 21.2 TIM4 main features
- 21.3 TIM4interrupts
- 21.4 TIM4 clock selection
- 21.5 TIM4 registers
- 21.5.1 Control register 1 (TIM4_CR1)
- 21.5.2 Control register 2 (TIM4_CR2)
- 21.5.3 Slave mode control register (TIM4_SMCR)
- 21.5.4 DMA request enable register (TIM4_DER)
- 21.5.5 Interrupt enable register (TIM4_IER)
- 21.5.6 Status register 1 (TIM4_SR)
- 21.5.7 Event generation register (TIM4_EGR)
- 21.5.8 Counter (TIM4_CNTR)
- 21.5.9 Prescaler register (TIM4_PSCR)
- 21.5.10 Auto-reload register (TIM4_ARR)
- 21.5.11 TIM4 register map and reset values
- 22 Infrared (IRTIM) interface
- 23 Beeper (BEEP)
- 24 Real-time clock (RTC)
- 24.1 RTC introduction
- 24.2 RTC main features
- 24.3 RTC functional description
- 24.3.1 Clock and prescalers
- 24.3.2 Real-time clock and calendar
- 24.3.3 Programmable alarm
- 24.3.4 Periodic auto-wakeup
- 24.3.5 RTC initialization and configuration
- 24.3.6 Reading the calendar
- 24.3.7 Resetting the RTC
- 24.3.8 RTC synchronization (low, medium+ and high-density devices only)
- 24.3.9 RTC smooth digital calibration (low, medium+ and high density devices only)
- 24.3.10 Tamper detection (low, medium+ and high-density devices only)
- 24.3.11 Calibration clock output
- 24.3.12 Alarm output
- 24.4 RTC low power modes
- 24.5 RTC interrupts
- 24.6 RTC registers
- 24.6.1 Time register 1 (RTC_TR1)
- 24.6.2 Time register 2 (RTC_TR2)
- 24.6.3 Time register 3 (RTC_TR3)
- 24.6.4 Date register 1 (RTC_DR1)
- 24.6.5 Date register 2 (RTC_DR2)
- 24.6.6 Date register 3 (RTC_DR3)
- 24.6.7 Subsecond register high (RTC_SSRH)
- 24.6.8 Subsecond register low (RTC_SSRL)
- 24.6.9 Control register 1 (RTC_CR1)
- 24.6.10 Control register 2 (RTC_CR2)
- 24.6.11 Control register 3 (RTC_CR3)
- 24.6.12 Initialization and status register 1 (RTC_ISR1)
- 24.6.13 Initialization and status register 2 (RTC_ISR2)
- 24.6.14 Synchronous prescaler register high (RTC_SPRERH)
- 24.6.15 Synchronous prescaler register low (RTC_SPRERL)
- 24.6.16 Asynchronous prescaler register (RTC_APRER)
- 24.6.17 Wakeup timer register high (RTC_WUTRH)
- 24.6.18 Wakeup timer register low (RTC_WUTRL)
- 24.6.19 Write protection register (RTC_WPR)
- 24.6.20 RTC shift control register high (RTC_SHIFTRH)
- 24.6.21 RTC shift control register low (RTC_SHIFTRL)
- 24.6.22 Alarm A register 1 (RTC_ALRMAR1)
- 24.6.23 Alarm A register 2 (RTC_ALRMAR2)
- 24.6.24 Alarm A register 3 (RTC_ALRMAR3)
- 24.6.25 Alarm A register 4 (RTC_ALRMAR4)
- 24.6.26 Alarm A sub second register high (RTC_ALRMASSRH)
- 24.6.27 Alarm A sub second register low (RTC_ALRMASSRL)
- 24.6.28 Alarm A subsecond masking register (RTC_ALRMASSMSKR)
- 24.6.29 Calibration register high (RTC_CALRH)
- 24.6.30 Calibration register low (RTC_CALRL)
- 24.6.31 Tamper control register 1 (RTC_TCR1)
- 24.6.32 Tamper control register 2 (RTC_TCR2)
- 24.6.33 RTC register map and reset values
- 25 Independent watchdog (IWDG)
- 26 Window watchdog (WWDG)
- 27 AES hardware accelerator (AES)
- 28 Inter-integrated circuit (I2C) interface
- 28.1 I2C introduction
- 28.2 I2C main features
- 28.3 I2C general description
- 28.4 I2C functional description
- 28.4.1 I2C slave mode
- 28.4.2 I2C master mode
- Figure 146. Transfer sequence diagram for master transmitter
- Figure 147. Method 1: transfer sequence diagram for master receiver
- Figure 148. Method 2: transfer sequence diagram for master receiver when N >2
- Figure 149. Method 2: transfer sequence diagram for master receiver when N=2
- Figure 150. Method 2: transfer sequence diagram for master receiver when N=1
- 28.4.3 Error conditions
- 28.4.4 SDA/SCL line control
- 28.4.5 SMBus
- 28.4.6 DMA requests
- 28.4.7 Packet error checking
- 28.5 I2C low power modes
- 28.6 I2C interrupts
- 28.7 I2C registers
- 28.7.1 Control register 1 (I2C_CR1)
- 28.7.2 Control register 2 (I2C_CR2)
- 28.7.3 Frequency register (I2C_FREQR)
- 28.7.4 Own address register LSB (I2C_OAR1L)
- 28.7.5 Own address register MSB (I2C_OAR1H)
- 28.7.6 Own address register 2 (I2C_OAR2)
- 28.7.7 Data register (I2C_DR)
- 28.7.8 Status register 1 (I2C_SR1)
- 28.7.9 Status register 2 (I2C_SR2)
- 28.7.10 Status register 3 (I2C_SR3)
- 28.7.11 Interrupt and DMA register (I2C_ITR)
- 28.7.12 Clock control register low (I2C_CCRL)
- 28.7.13 Clock control register high (I2C_CCRH)
- 28.7.14 TRISE register (I2C_TRISER)
- 28.7.15 PEC register (I2C_PECR)
- 28.7.16 I2C register map and reset values
- 29 Universal synchronous/asynchronous receiver transmitter (USART)
- 29.1 USART introduction
- 29.2 USART main features
- 29.3 USART functional description
- Figure 152. STM8L05xx/15xx/16xx USART block diagram
- 29.3.1 USART character description
- 29.3.2 Transmitter
- 29.3.3 Receiver
- 29.3.4 High precision baud rate generator
- 29.3.5 USART receiver’s tolerance to clock deviation
- 29.3.6 Parity control
- 29.3.7 Multi-processor communication
- 29.3.8 USART synchronous communication
- 29.3.9 Single wire half duplex communication
- 29.3.10 Smartcard
- 29.3.11 IrDA SIR ENDEC block
- 29.3.12 Continuous communication using DMA
- 29.4 USART low power modes
- 29.5 USART interrupts
- 29.6 USART registers
- 29.6.1 Status register (USART_SR)
- 29.6.2 Data register (USART_DR)
- 29.6.3 Baud rate register 1 (USART_BRR1)
- 29.6.4 Baud rate register 2 (USART_BRR2)
- 29.6.5 Control register 1 (USART_CR1)
- 29.6.6 Control register 2 (USART_CR2)
- 29.6.7 Control register 3 (USART_CR3)
- 29.6.8 Control register 4 (USART_CR4)
- 29.6.9 Control register 5 (USART_CR5)
- 29.6.10 Guard time register (USART_GTR)
- 29.6.11 Prescaler register (USART_PSCR)
- 29.6.12 USART register map and reset values
- 30 Serial peripheral interface (SPI)
- 30.1 SPI introduction
- 30.2 SPI main features
- 30.3 SPI functional description
- 30.3.1 SPI general description
- 30.3.2 Configuring the SPI in slave mode
- 30.3.3 Configuring the SPI master mode
- 30.3.4 Configuring the SPI for simplex communications
- 30.3.5 Data transmission and reception procedures
- Figure 175. TXE/RXNE/BSY behavior in full duplex mode (RXONLY = 0). Case of continuous transfers
- Figure 176. TXE/RXNE/BSY behavior in slave / full duplex mode (BDM = 0, RXONLY = 0). Case of continuous transfers
- Figure 177. TXE/BSY in master transmit-only mode (BDM = 0 and RXONLY = 0). Case of continuous transfers
- Figure 178. TXE/BSY in slave transmit-only mode (BDM = 0 and RXONLY = 0). Case of continuous transfers
- Figure 179. RXNE behavior in receive-only mode (BDM = 0 and RXONLY = 1). Case of continuous transfers
- Figure 180. TXE/BSY behavior when transmitting (BDM = 0 and RXLONY = 0). Case of discontinuous transfers
- 30.3.6 CRC calculation
- 30.3.7 Status flags
- 30.3.8 Disabling the SPI
- 30.3.9 SPI communication using DMA (direct memory addressing)
- 30.3.10 Error flags
- 30.3.11 SPI low power modes
- 30.3.12 SPI interrupts
- 30.4 SPI registers
- 30.4.1 SPI control register 1 (SPI_CR1)
- 30.4.2 SPI control register 2 (SPI_CR2)
- 30.4.3 SPI interrupt control register (SPI_ICR)
- 30.4.4 SPI status register (SPI_SR)
- 30.4.5 SPI data register (SPI_DR)
- 30.4.6 SPI CRC polynomial register (SPI_CRCPR)
- 30.4.7 SPI Rx CRC register (SPI_RXCRCR)
- 30.4.8 SPI Tx CRC register (SPI_TXCRCR)
- 30.5 SPI register map and reset values
- 31 Revision history