STM32H7x3 Advanced ARM® Based 32 Bit MCUs Reference Manual
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RM0433 Reference manual STM32H7x3 advanced ARM®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32H7x3 microcontroller memory and peripherals. The STM32H7x3 is a line of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets. For information on the ARM® Cortex®-M7 with FPU cores, please refer to the corresponding ARM Technical Reference Manuals. Related documents • ARM® Cortex®-M7 Technical Reference Manual, available from www.arm.com. • Cortex®-M7 programming manual (PM0253). August 2017 DocID029587 Rev 3 1/3178 www.st.com 1 Contents RM0433 Contents 1 2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.1 2.2 3 2/3178 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.1.1 Bus matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.1.2 Bus-to-bus bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.1.3 Inter-domain buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.1.4 CPU buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.1.5 Bus master peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.1.6 Clocks to functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . 105 2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.4 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 2.5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.3.2 Pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.3.3 Flash memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.3.4 Flash read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3.3.5 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.3.6 Cyclic redundancy check module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.3.7 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.3.8 Changing user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.3.9 Flash interface error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DocID029587 Rev 3 RM0433 Contents 3.3.10 Simultaneous read/program/erase on bank1 and bank2 . . . . . . . . . . . 130 3.3.11 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.12 Protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.3.13 Flash bank swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.4 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.5 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.5.1 FLASH access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . 140 3.5.2 FLASH key register for bank 1 (FLASH_KEYR1) . . . . . . . . . . . . . . . . 141 3.5.3 FLASH option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . 142 3.5.4 FLASH control register for bank 1 (FLASH_CR1) . . . . . . . . . . . . . . . . 142 3.5.5 FLASH status register for bank 1 (FLASH_SR1) . . . . . . . . . . . . . . . . . 146 3.5.6 FLASH clear control register for bank 1 (FLASH_CCR1) . . . . . . . . . . 149 3.5.7 FLASH option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . 150 3.5.8 FLASH option status register (current value) (FLASH_OPTSR_CUR) 151 3.5.9 FLASH option status register (value to program) (FLASH_OPTSR_PRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.5.10 FLASH option clear control register (FLASH_OPTCCR) . . . . . . . . . . . 156 3.5.11 FLASH protection address for bank 1 (current value) (FLASH_PRAR_CUR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.5.12 FLASH protection address for bank 1 (value to program) (FLASH_PRAR_PRG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.5.13 FLASH secure address for bank 1 (current value) (FLASH_SCAR_CUR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.5.14 FLASH secure address for bank 1 (value to program) (FLASH_SCAR_PRG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.5.15 FLASH write sector protection for bank 1 (current value) (FLASH_WPSN_CUR1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.16 FLASH write sector protection for bank 1 (value to program) (FLASH_WPSN_PRG1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.17 FLASH register with boot address (current value) (FLASH_BOOT_CURR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.5.18 FLASH register with boot address (value to program) (FLASH_BOOT_PRGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.5.19 FLASH CRC control register for bank 1 (FLASH_CRCCR1) . . . . . . . . 162 3.5.20 FLASH CRC start address register for bank 1 (FLASH_CRCSADD1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 3.5.21 FLASH CRC end address register for bank 1 (FLASH_CRCEADD1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 3.5.22 FLASH CRC data register (FLASH_CRCDATAR) . . . . . . . . . . . . . . . . 164 3.5.23 FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) . . . . . . . . . 165 DocID029587 Rev 3 3/3178 68 Contents RM0433 3.6 4 FLASH key register for bank 2 (FLASH_KEYR2) . . . . . . . . . . . . . . . . 166 3.5.25 FLASH control register for bank 2 (FLASH_CR2) . . . . . . . . . . . . . . . . 166 3.5.26 FLASH status register for bank 2 (FLASH_SR2) . . . . . . . . . . . . . . . . . 170 3.5.27 FLASH clear control register for bank 2 (FLASH_CCR2) . . . . . . . . . . 173 3.5.28 FLASH protection address for bank 2 (current value) (FLASH_PRAR_CUR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 3.5.29 FLASH protection address for bank 2 (value to program) (FLASH_PRAR_PRG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.5.30 FLASH secure address for bank 2 (current value) (FLASH_SCAR_CUR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.5.31 FLASH secure address for bank 2 (value to program) (FLASH_SCAR_PRG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 3.5.32 FLASH write sector protection for bank 2 (current value) (FLASH_WPSN_CUR2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 3.5.33 FLASH write sector protection for bank 2 (value to program) (FLASH_WPSN_PRG2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 3.5.34 FLASH CRC control register for bank 2 (FLASH_CRCCR2) . . . . . . . . 178 3.5.35 FLASH CRC start address register for bank 2 (FLASH_CRCSADD2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.5.36 FLASH CRC end address register for bank 2 (FLASH_CRCEADD2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 3.5.37 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) . . . . . . . . . 180 FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Security memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.3 Flash protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.4 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.5 4.6 4/3178 3.5.24 4.4.1 Associated features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.4.2 Boot state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.4.3 Secure access mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Root secure services (RSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.5.1 Calling root secure services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.5.2 Root secure services description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Secure user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.6.1 Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.6.2 Setting secure user memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.6.3 Removing secure user memory areas . . . . . . . . . . . . . . . . . . . . . . . . . 193 DocID029587 Rev 3 RM0433 Contents 4.6.4 4.7 5 Selecting secure user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Summary of Flash protection mechanisms . . . . . . . . . . . . . . . . . . . . . . 195 AXI interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.1 AXI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.2 AXI interconnect main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.3 AXI interconnect functional description . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.4 5.3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.3.2 ASIB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.3.3 AMIB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 5.3.4 Quality of service (QoS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 5.3.5 Global programmer view (GPV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 AXI interconnect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.4.1 AXI interconnect - peripheral ID4 register (AXI_PERIPH_ID_4) . . . . . 199 5.4.2 AXI interconnect - peripheral ID0 register (AXI_PERIPH_ID_0) . . . . . 199 5.4.3 AXI interconnect - peripheral ID1 register (AXI_PERIPH_ID_1) . . . . . 200 5.4.4 AXI interconnect - peripheral ID2 register (AXI_PERIPH_ID_2) . . . . . 200 5.4.5 AXI interconnect - peripheral ID3 register (AXI_PERIPH_ID_3) . . . . . 201 5.4.6 AXI interconnect - component ID0 register (AXI_COMP_ID_0) . . . . . 201 5.4.7 AXI interconnect - component ID1 register (AXI_COMP_ID_1) . . . . . 202 5.4.8 AXI interconnect - component ID2 register (AXI_COMP_ID_2) . . . . . 202 5.4.9 AXI interconnect - component ID3 register (AXI_COMP_ID_3) . . . . . 203 5.4.10 AXI interconnect - TARG x bus matrix issuing functionality register (AXI_TARGx_FN_MOD_ISS_BM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.4.11 AXI interconnect - TARG x bus matrix functionality 2 register (AXI_TARGx_FN_MOD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.4.12 AXI interconnect - TARG x long burst functionality modification register (AXI_TARGx_FN_MOD_LB) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 5.4.13 AXI interconnect - TARG x issuing functionality modification register (AXI_TARGx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 5.4.14 AXI interconnect - INI x functionality modification 2 register (AXI_INIx_FN_MOD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 5.4.15 AXI interconnect - INI x AHB functionality modification register (AXI_INIx_FN_MOD_AHB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 5.4.16 AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS) . . 206 5.4.17 AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS) . 207 5.4.18 AXI interconnect - INI x issuing functionality modification register (AXI_INIx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DocID029587 Rev 3 5/3178 68 Contents RM0433 5.5 6 AXI interconnect register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6.2 PWR main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6.3 PWR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.3.1 6.4 6.5 6.6 6.7 6/3178 PWR pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 6.4.1 System supply startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.4.2 Core domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.4.3 PWR external supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.4.4 Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4.5 VBAT battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6.4.6 Analog supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6.4.7 USB regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 6.5.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 230 6.5.2 Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 6.5.3 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 231 6.5.4 Analog voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.5.5 Battery voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.5.6 Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 6.6.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 6.6.2 Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.6.3 Power control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 6.6.4 Power management examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 6.7.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 6.7.2 Controlling peripheral clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 6.7.3 Entering low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 6.7.4 Exiting from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 6.7.5 CSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 6.7.6 CStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 6.7.7 DStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 6.7.8 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 DocID029587 Rev 3 RM0433 Contents 6.8 7 DStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 6.7.10 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 PWR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 6.8.1 PWR control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 261 6.8.2 PWR control status register 1 (PWR_CSR1) . . . . . . . . . . . . . . . . . . . . 262 6.8.3 PWR control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 263 6.8.4 PWR control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 264 6.8.5 PWR CPU control register (PWR_CPUCR) . . . . . . . . . . . . . . . . . . . . 266 6.8.6 PWR D3 domain control register (PWR_D3CR) . . . . . . . . . . . . . . . . . 267 6.8.7 PWR wakeup clear register (PWR_WKUPCR) . . . . . . . . . . . . . . . . . . 268 6.8.8 PWR wakeup flag register (PWR_WKUPFR) . . . . . . . . . . . . . . . . . . . 268 6.8.9 PWR wakeup enable and polarity register (PWR_WKUPEPR) . . . . . . 269 6.8.10 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Low-power D3 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.2 EXTI, RCC and PWR interconnections . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.3 7.4 8 6.7.9 7.2.1 Interrupts and wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 7.2.2 Block interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 7.2.3 Role of D3 domain DMAMUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Low-power application example based on LPUART1 transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.3.1 Memory retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.3.2 Memory-to-peripheral transfer using LPUART1 interface . . . . . . . . . . 275 7.3.3 Overall description of the low-power application example based on LPUART1 transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 7.3.4 Alternate implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Other low-power applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Reset and Clock Control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 8.1 RCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 8.2 RCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 8.3 RCC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 8.4 RCC reset block functional description . . . . . . . . . . . . . . . . . . . . . . . . . 286 8.4.1 Power-on/off reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 8.4.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 8.4.3 Local resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 DocID029587 Rev 3 7/3178 68 Contents RM0433 8.5 8/3178 8.4.4 Reset source identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 8.4.5 Low-power mode security reset (lpwr_rst) . . . . . . . . . . . . . . . . . . . . . . 290 8.4.6 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 8.4.7 Power-on and wakeup sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 RCC clock block functional description . . . . . . . . . . . . . . . . . . . . . . . . . 294 8.5.1 Clock naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 8.5.2 Oscillators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 8.5.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 8.5.4 Clock output generation (MCO1/MCO2) . . . . . . . . . . . . . . . . . . . . . . . 302 8.5.5 PLL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 8.5.6 System clock (sys_ck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 8.5.7 Handling clock generators in Stop and Standby mode . . . . . . . . . . . . 309 8.5.8 Kernel clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 8.5.9 General clock concept overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 8.5.10 Peripheral allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 8.5.11 Peripheral clock gating control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 8.5.12 CPU and bus matrix clock gating control . . . . . . . . . . . . . . . . . . . . . . . 334 8.6 RCC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 8.7 RCC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 8.7.1 Register mapping overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 8.7.2 RCC Source Control Register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . 338 8.7.3 RCC Internal Clock Source Calibration Register (RCC_ICSCR) . . . . . 342 8.7.4 RCC Clock Recovery RC Register (RCC_CRRCR) . . . . . . . . . . . . . . 343 8.7.5 RCC Clock Configuration Register (RCC_CFGR) . . . . . . . . . . . . . . . . 344 8.7.6 RCC Domain 1 Clock Configuration Register (RCC_D1CFGR) . . . . . 347 8.7.7 RCC Domain 2 Clock Configuration Register (RCC_D2CFGR) . . . . . 349 8.7.8 RCC Domain 3 Clock Configuration Register (RCC_D3CFGR) . . . . . 350 8.7.9 RCC PLLs Clock Source Selection Register (RCC_PLLCKSELR) . . . 351 8.7.10 RCC PLLs Configuration Register (RCC_PLLCFGR) . . . . . . . . . . . . . 353 8.7.11 RCC PLL1 Dividers Configuration Register (RCC_PLL1DIVR) . . . . . . 356 8.7.12 RCC PLL1 Fractional Divider Register (RCC_PLL1FRACR) . . . . . . . 358 8.7.13 RCC PLL2 Dividers Configuration Register (RCC_PLL2DIVR) . . . . . . 359 8.7.14 RCC PLL2 Fractional Divider Register (RCC_PLL2FRACR) . . . . . . . 361 8.7.15 RCC PLL3 Dividers Configuration Register (RCC_PLL3DIVR) . . . . . . 362 8.7.16 RCC PLL3 Fractional Divider Register (RCC_PLL3FRACR) . . . . . . . 364 8.7.17 RCC Domain 1 Kernel Clock Configuration Register (RCC_D1CCIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 DocID029587 Rev 3 RM0433 Contents 8.7.18 RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 8.7.19 RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 8.7.20 RCC Domain 3 Kernel Clock Configuration Register (RCC_D3CCIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 8.7.21 RCC Clock Source Interrupt Enable Register (RCC_CIER) . . . . . . . . 374 8.7.22 RCC Clock Source Interrupt Flag Register (RCC_CIFR) . . . . . . . . . . 376 8.7.23 RCC Clock Source Interrupt Clear Register (RCC_CICR) . . . . . . . . . 378 8.7.24 RCC Backup Domain Control Register (RCC_BDCR) . . . . . . . . . . . . 380 8.7.25 RCC Clock Control and Status Register (RCC_CSR) . . . . . . . . . . . . . 382 8.7.26 RCC AHB3 Reset Register (RCC_AHB3RSTR) . . . . . . . . . . . . . . . . . 383 8.7.27 RCC AHB1 Peripheral Reset Register(RCC_AHB1RSTR) . . . . . . . . . 385 8.7.28 RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR) . . . . . . . . 387 8.7.29 RCC AHB4 Peripheral Reset Register (RCC_AHB4RSTR) . . . . . . . . 388 8.7.30 RCC APB3 Peripheral Reset Register (RCC_APB3RSTR) . . . . . . . . 390 8.7.31 RCC APB1 Peripheral Reset Register (RCC_APB1LRSTR) . . . . . . . 391 8.7.32 RCC APB1 Peripheral Reset Register (RCC_APB1HRSTR) . . . . . . . 394 8.7.33 RCC APB2 Peripheral Reset Register (RCC_APB2RSTR) . . . . . . . . 395 8.7.34 RCC APB4 Peripheral Reset Register (RCC_APB4RSTR) . . . . . . . . 397 8.7.35 RCC Global Control Register (RCC_GCR) . . . . . . . . . . . . . . . . . . . . . 399 8.7.36 RCC D3 Autonomous mode Register (RCC_D3AMR) . . . . . . . . . . . . 400 8.7.37 RCC Reset Status Register (RCC_RSR) . . . . . . . . . . . . . . . . . . . . . . 403 8.7.38 RCC AHB3 Clock Register (RCC_AHB3ENR) . . . . . . . . . . . . . . . . . . 405 8.7.39 RCC AHB1 Clock Register (RCC_AHB1ENR) . . . . . . . . . . . . . . . . . . 407 8.7.40 RCC AHB2 Clock Register (RCC_AHB2ENR) . . . . . . . . . . . . . . . . . . 409 8.7.41 RCC AHB4 Clock Register (RCC_AHB4ENR) . . . . . . . . . . . . . . . . . . 411 8.7.42 RCC APB3 Clock Register (RCC_APB3ENR) . . . . . . . . . . . . . . . . . . 414 8.7.43 RCC APB1 Clock Register (RCC_APB1LENR) . . . . . . . . . . . . . . . . . 415 8.7.44 RCC APB1 Clock Register (RCC_APB1HENR) . . . . . . . . . . . . . . . . . 419 8.7.45 RCC APB2 Clock Register (RCC_APB2ENR) . . . . . . . . . . . . . . . . . . 421 8.7.46 RCC APB4 Clock Register (RCC_APB4ENR) . . . . . . . . . . . . . . . . . . 424 8.7.47 RCC AHB3 Sleep Clock Register (RCC_AHB3LPENR) . . . . . . . . . . . 427 8.7.48 RCC AHB1 Sleep Clock Register (RCC_AHB1LPENR) . . . . . . . . . . . 429 8.7.49 RCC AHB2 Sleep Clock Register (RCC_AHB2LPENR) . . . . . . . . . . . 431 8.7.50 RCC AHB4 Sleep Clock Register (RCC_AHB4LPENR) . . . . . . . . . . . 433 8.7.51 RCC APB3 Sleep Clock Register (RCC_APB3LPENR) . . . . . . . . . . . 436 8.7.52 RCC APB1 Low Sleep Clock Register (RCC_APB1LLPENR) . . . . . . 437 DocID029587 Rev 3 9/3178 68 Contents RM0433 8.8 9 8.7.53 RCC APB1 High Sleep Clock Register (RCC_APB1HLPENR) . . . . . . 441 8.7.54 RCC APB2 Sleep Clock Register (RCC_APB2LPENR) . . . . . . . . . . . 443 8.7.55 RCC APB4 Sleep Clock Register (RCC_APB4LPENR) . . . . . . . . . . . 446 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 9.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 9.3 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 9.3.1 9.4 10 10/3178 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 CRS internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 9.4.1 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 9.4.2 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 9.4.3 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 462 9.4.4 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 9.5 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 9.6 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 9.7 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 9.7.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 9.7.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 465 9.7.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 466 9.7.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 468 9.7.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 10.1 Hardware semaphore introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 10.2 Hardware semaphore main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 10.3 HSEM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 10.3.1 HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 10.3.2 HSEM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 10.3.3 HSEM lock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 10.3.4 HSEM Write/Read/ReadLock register address . . . . . . . . . . . . . . . . . . 473 10.3.5 HSEM Clear procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 10.3.6 HSEM MasterID semaphore clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 10.3.7 HSEM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 10.3.8 AHB bus master ID verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 DocID029587 Rev 3 RM0433 Contents 10.4 11 HSEM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 10.4.1 HSEM register (HSEM_R0 - HSEM_R31) . . . . . . . . . . . . . . . . . . . . . . 478 10.4.2 HSEM Read lock register (HSEM_RLR0 - HSEM_RLR31) . . . . . . . . . 479 10.4.3 HSEM Interrupt enable register (HSEM_CnIER) . . . . . . . . . . . . . . . . . 480 10.4.4 HSEM Interrupt clear register (HSEM_CnICR) . . . . . . . . . . . . . . . . . . 480 10.4.5 HSEM Interrupt status register (HSEM_CnISR) . . . . . . . . . . . . . . . . . 480 10.4.6 HSEM Masked interrupt status register (HSEM_CnMISR) . . . . . . . . . 481 10.4.7 HSEM Clear register (HSEM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 10.4.8 HSEM Interrupt clear register (HSEM_KEYR) . . . . . . . . . . . . . . . . . . . 482 10.4.9 HSEM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 11.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 11.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 11.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 11.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 487 11.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 11.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 11.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 11.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 11.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 11.3.11 I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 11.3.12 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 11.3.13 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 11.3.14 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 493 11.3.15 Using the GPIO pins in the backup supply domain . . . . . . . . . . . . . . . 493 11.4 .GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 11.4.1 GPIO port mode register (GPIOx_MODER) (x =A..K) . . . . . . . . . . . . . 494 11.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..K) . . . . . . . 494 11.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 11.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 DocID029587 Rev 3 11/3178 68 Contents RM0433 11.4.5 GPIO port input data register (GPIOx_IDR) (x = A..K) . . . . . . . . . . . . 496 11.4.6 GPIO port output data register (GPIOx_ODR) (x = A..K) . . . . . . . . . . 496 11.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..K) . . . . . . . . . 496 11.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 11.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 11.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..J) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 11.4.11 12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 502 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 12.2 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 12.3 SYSCFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 12.3.1 SYSCFG peripheral mode configuration register (SYSCFG_PMCR) . 502 12.3.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 12.3.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 12.3.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 12.3.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 12.3.6 SYSCFG compensation cell control/status register (SYSCFG_CCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 12.3.7 SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . . . 509 12.3.8 SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . . . 509 12.3.9 SYSCFG package register (SYSCFG_PKGR) . . . . . . . . . . . . . . . . . . 510 12.3.10 SYSCFG user register 0 (SYSCFG_UR0) . . . . . . . . . . . . . . . . . . . . . . 511 12.3.11 SYSCFG user register 2 (SYSCFG_UR2) . . . . . . . . . . . . . . . . . . . . . . 511 12.3.12 SYSCFG user register 3 (SYSCFG_UR3) . . . . . . . . . . . . . . . . . . . . . . 512 12.3.13 SYSCFG user register 4 (SYSCFG_UR4) . . . . . . . . . . . . . . . . . . . . . . 512 12.3.14 SYSCFG user register 5 (SYSCFG_UR5) . . . . . . . . . . . . . . . . . . . . . . 513 12.3.15 SYSCFG user register 6 (SYSCFG_UR6) . . . . . . . . . . . . . . . . . . . . . . 513 12.3.16 SYSCFG user register 7 (SYSCFG_UR7) . . . . . . . . . . . . . . . . . . . . . . 514 12.3.17 SYSCFG user register 8 (SYSCFG_UR8) . . . . . . . . . . . . . . . . . . . . . . 514 12.3.18 SYSCFG user register 9 (SYSCFG_UR9) . . . . . . . . . . . . . . . . . . . . . . 515 12.3.19 SYSCFG user register 10 (SYSCFG_UR10) . . . . . . . . . . . . . . . . . . . . 515 12/3178 DocID029587 Rev 3 RM0433 Contents 12.3.20 SYSCFG user register 11 (SYSCFG_UR11) . . . . . . . . . . . . . . . . . . . . 516 12.3.21 SYSCFG user register 12 (SYSCFG_UR12) . . . . . . . . . . . . . . . . . . . . 516 12.3.22 SYSCFG user register 13 (SYSCFG_UR13) . . . . . . . . . . . . . . . . . . . . 517 12.3.23 SYSCFG user register 14 (SYSCFG_UR14) . . . . . . . . . . . . . . . . . . . . 518 12.3.24 SYSCFG user register 15 (SYSCFG_UR15) . . . . . . . . . . . . . . . . . . . . 519 12.3.25 SYSCFG user register 16 (SYSCFG_UR16) . . . . . . . . . . . . . . . . . . . . 520 12.3.26 SYSCFG user register 17 (SYSCFG_UR17) . . . . . . . . . . . . . . . . . . . . 520 12.3.27 SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 13 Block interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 13.1 14 Peripheral interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 13.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 13.1.2 Connection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 13.2 Wakeup from low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 13.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 13.3.1 MDMA (D1 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 13.3.2 DMAMUX1, DMA1 and DMA2 (D2 domain) . . . . . . . . . . . . . . . . . . . . 551 13.3.3 DMAMUX2, BDMA (D3 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 MDMA controller (MDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 14.1 MDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 14.2 MDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 14.3 MDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 14.3.1 MDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 14.3.2 MDMA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 14.3.3 MDMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 14.3.4 MDMA channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 14.3.5 Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 563 14.3.6 Pointer update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 14.3.7 MDMA buffer transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.3.8 Request arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.3.9 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.3.10 Block transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.3.11 Block repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.3.12 Linked list mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.3.13 MDMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.3.14 MDMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 DocID029587 Rev 3 13/3178 68 Contents RM0433 14.3.15 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 14.4 MDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 14.5 MDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 14.5.1 MDMA Global Interrupt/Status Register (MDMA_GISR0) . . . . . . . . . . 568 14.5.2 MDMA channel x interrupt/status register (MDMA_CxISR) (x = 0..15) 569 14.5.3 MDMA channel x interrupt flag clear register (MDMA_CxIFCR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 14.5.4 MDMA Channel x error status register (MDMA_CxESR) (x = 0..15) . . 571 14.5.5 MDMA channel x control register (MDMA_CxCR) (x = 0..15) . . . . . . . 573 14.5.6 MDMA channel x Transfer Configuration register (MDMA_CxTCR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 14.5.7 MDMA Channel x block number of data register (MDMA_CxBNDTR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 14.5.8 MDMA channel x source address register (MDMA_CxSAR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 14.5.9 MDMA channel x destination address register (MDMA_CxDAR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 14.5.10 MDMA channel x Block Repeat address Update register MDMA_CxBRUR (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 14.5.11 MDMA channel x Link Address register (MDMA_CxLAR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 14.5.12 MDMA channel x Trigger and Bus selection Register (MDMA_CxTBR) (x = 0..15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 14.5.13 MDMA channel x Mask address register (MDMA_CxMAR) (x = 0..15) 585 14.5.14 MDMA channel x Mask Data register (MDMA_CxMDR) (x = 0..15) . . 585 14.5.15 MDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 15 14/3178 Direct memory access controller (DMA1, DMA2) . . . . . . . . . . . . . . . . 588 15.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 15.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 15.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.3.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.3.2 DMA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.3.3 DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 15.3.4 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 15.3.5 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 15.3.6 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 15.3.7 DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 15.3.8 Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 592 DocID029587 Rev 3 RM0433 Contents 15.3.9 Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 15.3.10 Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 15.3.11 Double buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 15.3.12 Programmable data width, packing/unpacking, endianness . . . . . . . . 597 15.3.13 Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 15.3.14 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 15.3.15 DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 15.3.16 DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 15.3.17 Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 15.3.18 Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 605 15.3.19 Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 15.3.20 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 15.4 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.5 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 15.5.1 DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 608 15.5.2 DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 609 15.5.3 DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 610 15.5.4 DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 610 15.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7) . . . . . . . 611 15.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) . . . 614 15.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . 615 15.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) 615 15.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) 615 15.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) . . . . . . 616 15.5.11 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16 Basic direct memory access controller (BDMA) . . . . . . . . . . . . . . . . 621 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 16.2 BDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 16.3 BDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 16.3.1 BDMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 16.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 16.3.3 BDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 16.3.4 Programmable data width, data alignment and endianness . . . . . . . . 625 16.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 16.3.6 BDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 DocID029587 Rev 3 15/3178 68 Contents RM0433 16.4 17 16.4.1 DMA interrupt status register (BDMA_ISR) . . . . . . . . . . . . . . . . . . . . . 627 16.4.2 DMA interrupt flag clear register (BDMA_IFCR) . . . . . . . . . . . . . . . . . 628 16.4.3 DMA channel x configuration register (BDMA_CCRx) (x = 1..8, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . 629 16.4.4 DMA channel x number of data register (BDMA_CNDTRx) (x = 1..8, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 16.4.5 DMA channel x peripheral address register (BDMA_CPARx) (x = 1..8, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 16.4.6 DMA channel x memory address register (BDMA_CMARx) (x = 1..8, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 16.4.7 BDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 636 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 17.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 17.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 17.4 16/3178 BDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 17.3.1 DMAMUX1 and DMAMUX2 instantiation . . . . . . . . . . . . . . . . . . . . . . . 637 17.3.2 DMAMUX1 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 17.3.3 DMAMUX2 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.4.1 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.4.2 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.4.3 DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.4.4 DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.4.5 DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 17.5 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 17.6 DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 17.6.1 DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 17.6.2 DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 17.6.3 DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 17.6.4 DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 17.6.5 DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 DocID029587 Rev 3 RM0433 Contents 17.6.6 DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 17.6.7 DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 17.6.8 DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 17.6.9 DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.6.10 DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.6.11 DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 17.6.12 DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 17.6.13 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18 Chrom-Art Accelerator™ controller (DMA2D) . . . . . . . . . . . . . . . . . . 657 18.1 DMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2 DMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 18.3 DMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 18.3.1 18.4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 DMA2D pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 18.4.1 DMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 18.4.2 DMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 660 18.4.3 DMA2D foreground and background pixel format converter (PFC) . . . 660 18.4.4 DMA2D foreground and background CLUT interface . . . . . . . . . . . . . 663 18.4.5 DMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 18.4.6 DMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 18.4.7 DMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 18.4.8 DMA2D AXI master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 18.4.9 DMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 18.4.10 DMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 18.4.11 YCbCr support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 18.4.12 DMA2D transfer control (start, suspend, abort and completion) . . . . . 669 18.4.13 Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 18.4.14 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 18.4.15 AXI dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 18.5 DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 DocID029587 Rev 3 17/3178 68 Contents RM0433 18.6 DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.6.1 DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 672 18.6.2 DMA2D Interrupt Status Register (DMA2D_ISR) . . . . . . . . . . . . . . . . 674 18.6.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 675 18.6.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . . 676 18.6.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 676 18.6.6 DMA2D background memory address register (DMA2D_BGMAR) . . 677 18.6.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 677 18.6.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 678 18.6.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 680 18.6.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 681 18.6.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 683 18.6.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 18.6.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 18.6.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 684 18.6.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 685 18.6.16 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 686 18.6.17 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 687 18.6.18 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 687 18.6.19 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 688 18.6.20 DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . 688 18.6.21 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 19 Nested Vectored Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . 691 19.1 20 NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 19.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 19.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 699 20.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 20.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 20.2.1 20.3 18/3178 EXTI connections between peripherals, CPU, and D3 domain . . . . . . 700 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 20.3.1 EXTI Configurable event input CPU wakeup . . . . . . . . . . . . . . . . . . . . 702 20.3.2 EXTI configurable event input Any wakeup . . . . . . . . . . . . . . . . . . . . . 703 DocID029587 Rev 3 RM0433 Contents 20.3.3 EXTI direct event input CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . 705 20.3.4 EXTI direct event input Any wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . 706 20.3.5 EXTI D3 pending request clear selection . . . . . . . . . . . . . . . . . . . . . . 707 20.4 EXTI event input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 20.5 EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 20.6 20.5.1 EXTI CPU interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 20.5.2 EXTI CPU event procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 20.5.3 EXTI CPU wakeup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 20.5.4 EXTI D3 domain wakeup for autonomous Run mode procedure . . . . 712 20.5.5 EXTI software interrupt/event trigger procedure . . . . . . . . . . . . . . . . . 712 EXTI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 20.6.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 713 20.6.2 EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . . 713 20.6.3 EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . . 714 20.6.4 EXTI D3 pending mask register (EXTI_D3PMR1) . . . . . . . . . . . . . . . . 714 20.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L) . . . . 715 20.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H) . . . 715 20.6.7 EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . . 716 20.6.8 EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . . 717 20.6.9 EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . . 717 20.6.10 EXTI D3 pending mask register (EXTI_D3PMR2) . . . . . . . . . . . . . . . . 718 20.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L) . . . . 719 20.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H) . . . 719 20.6.13 EXTI rising trigger selection register (EXTI_RTSR3) . . . . . . . . . . . . . . 720 20.6.14 EXTI falling trigger selection register (EXTI_FTSR3) . . . . . . . . . . . . . 720 20.6.15 EXTI software interrupt event register (EXTI_SWIER3) . . . . . . . . . . . 721 20.6.16 EXTI D3 pending mask register (EXTI_D3PMR3) . . . . . . . . . . . . . . . . 721 20.6.17 EXTI D3 pending clear selection register low (EXTI_D3PCR3L) . . . . 722 20.6.18 EXTI D3 pending clear selection register high (EXTI_D3PCR3H) . . . 722 20.6.19 EXTI interrupt mask register (EXTI_CPUIMR1) . . . . . . . . . . . . . . . . . 723 20.6.20 EXTI event mask register (EXTI_CPUEMR1) . . . . . . . . . . . . . . . . . . . 723 20.6.21 EXTI pending register (EXTI_CPUPR1) . . . . . . . . . . . . . . . . . . . . . . . 724 20.6.22 EXTI interrupt mask register (EXTI_CPUIMR2) . . . . . . . . . . . . . . . . . 724 20.6.23 EXTI event mask register (EXTI_CPUEMR2) . . . . . . . . . . . . . . . . . . . 725 20.6.24 EXTI pending register (EXTI_CPUPR2) . . . . . . . . . . . . . . . . . . . . . . . 725 20.6.25 EXTI interrupt mask register (EXTI_CPUIMR3) . . . . . . . . . . . . . . . . . 726 20.6.26 EXTI event mask register (EXTI_CPUEMR3) . . . . . . . . . . . . . . . . . . . 727 DocID029587 Rev 3 19/3178 68 Contents RM0433 20.6.27 EXTI pending register (EXTI_CPUPR3) . . . . . . . . . . . . . . . . . . . . . . . 727 20.6.28 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 21 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 731 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 21.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 21.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 21.4 22 21.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 21.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 21.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 21.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 21.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 734 21.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 21.4.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 21.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 21.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 22.1 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 22.2 FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 22.3 FMC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 22.4 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 22.5 AXI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 22.5.1 22.6 22.7 20/3178 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 740 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 22.6.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 22.6.2 NAND Flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 744 22.6.3 SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 22.7.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 22.7.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 751 22.7.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 22.7.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 752 22.7.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 22.7.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 DocID029587 Rev 3 RM0433 Contents 22.8 22.9 NAND Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 22.8.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 22.8.2 NAND Flash supported memories and transactions . . . . . . . . . . . . . . 788 22.8.3 Timing diagrams for NAND Flash memories . . . . . . . . . . . . . . . . . . . . 789 22.8.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 22.8.5 NAND Flash prewait feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 22.8.6 Computation of the error correction code (ECC) in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 22.8.7 NAND Flash controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 22.9.1 SDRAM controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 22.9.2 SDRAM External memory interface signals . . . . . . . . . . . . . . . . . . . . . 799 22.9.3 SDRAM controller functional description . . . . . . . . . . . . . . . . . . . . . . . 800 22.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 22.9.5 SDRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.10 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 23 Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.2 QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.3 QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 23.3.1 QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 23.3.2 QUADSPI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 23.3.3 QUADSPI Command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 23.3.4 QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 824 23.3.5 QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 23.3.6 QUADSPI status flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.3.7 QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.3.8 QUADSPI Free running clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . 829 23.3.9 QUADSPI Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 829 23.3.10 QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 23.3.11 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 23.3.12 QUADSPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 23.3.13 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 23.3.14 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 23.3.15 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 833 23.3.16 nCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 DocID029587 Rev 3 21/3178 68 Contents RM0433 23.4 QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 23.5 QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 23.5.1 QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 836 23.5.2 QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 839 23.5.3 QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 840 23.5.4 QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 841 23.5.5 QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 841 23.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 842 23.5.7 QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 844 23.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) . . . . . . . . . . . . 845 23.5.9 QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 845 23.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) . . . . . . . 846 23.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) . . . . . . 846 23.5.12 QUADSPI polling interval register (QUADSPI _PIR) . . . . . . . . . . . . . . 847 23.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 847 23.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 24.2 DLYB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 24.3 DLYB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 24.4 25 24.3.1 DLYB diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 24.3.2 DLYB pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 24.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 24.3.4 Delay line length configuration procedure . . . . . . . . . . . . . . . . . . . . . . 851 24.3.5 Output clock phase configuration procedure . . . . . . . . . . . . . . . . . . . . 851 DLYB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 24.4.1 DLYB control register (DLYB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 24.4.2 DLYB configuration register (DLYB_CFGR) . . . . . . . . . . . . . . . . . . . . 852 24.4.3 DLYB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 25.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 25.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 25.3.1 22/3178 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 DocID029587 Rev 3 RM0433 Contents 25.3.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 25.3.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 25.3.4 ADC1/2/3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 25.3.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 25.3.6 ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 25.3.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 865 25.3.8 Calibration (ADCAL, ADCALDIF, ADCALLIN, ADCx_CALFACT) . . . . 865 25.3.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 871 25.3.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 872 25.3.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 25.3.12 Channel preselection register (ADCx_PCSEL) . . . . . . . . . . . . . . . . . . 873 25.3.13 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 873 25.3.14 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 25.3.15 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 875 25.3.16 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 876 25.3.17 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 25.3.18 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 877 25.3.19 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 25.3.20 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882 25.3.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 884 25.3.22 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 885 25.3.23 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 893 25.3.24 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 893 25.3.25 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 893 25.3.26 Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 25.3.27 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 25.3.28 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . . 902 25.3.29 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 25.3.30 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) . . 907 25.3.31 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 25.3.32 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 25.3.33 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 25.3.34 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 25.3.35 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 934 DocID029587 Rev 3 23/3178 68 Contents RM0433 25.4 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 25.5 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 25.5.1 ADC x interrupt and status register (ADCx_ISR) (x=1 to 3) . . . . . . . . . 937 25.5.2 ADC x interrupt enable register (ADCx_IER) (x=1 to 3) . . . . . . . . . . . 939 25.5.3 ADC x control register (ADCx_CR) (x=1 to 3) . . . . . . . . . . . . . . . . . . . 941 25.5.4 ADC x configuration register (ADCx_CFGR) (x=1 to 3) . . . . . . . . . . . . 946 25.5.5 ADC x configuration register 2 (ADCx_CFGR2) (x=1 to 3) . . . . . . . . . 950 25.5.6 ADC x sample time register 1 (ADCx_SMPR1) (x=1 to 3) . . . . . . . . . . 952 25.5.7 ADC x sample time register 2 (ADCx_SMPR2) (x=1 to 3) . . . . . . . . . . 953 25.5.8 ADC x channel preselection register (ADCx_PCSEL) (x=1 to 3) . . . . . 954 25.5.9 ADC x watchdog threshold register 1 (ADCx_LTR1) (x=1 to 3) . . . . . . 954 25.5.10 ADC x watchdog threshold register 1 (ADCx_HTR1) (x=1 to 3) . . . . . 955 25.5.11 ADC x regular sequence register 1 (ADCx_SQR1) (x=1 to 3) . . . . . . . 956 25.5.12 ADC x regular sequence register 2 (ADCx_SQR2) (x=1 to 3) . . . . . . . 957 25.5.13 ADC x regular sequence register 3 (ADCx_SQR3) (x=1 to 3) . . . . . . . 958 25.5.14 ADC x regular sequence register 4 (ADCx_SQR4) (x=1 to 3) . . . . . . . 959 25.5.15 ADC x regular Data Register (ADCx_DR) (x=1 to 3) . . . . . . . . . . . . . . 960 25.5.16 ADC x injected sequence register (ADCx_JSQR) (x=1 to 3) . . . . . . . . 961 25.5.17 ADC x offset register (ADCx_OFRy) (x=1 to 3) . . . . . . . . . . . . . . . . . . 963 25.5.18 ADC x injected data register (ADCx_JDRy) (x=1 to 3) . . . . . . . . . . . . 964 25.5.19 ADC x Analog Watchdog 2 Configuration Register (ADCx_AWD2CR) (x=1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 25.5.20 ADC x Analog Watchdog 3 Configuration Register (ADCx_AWD3CR) (x=1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 25.5.21 ADC x watchdog lower threshold register 2 (ADCx_LTR2) (x=1 to 3) . 965 25.5.22 ADC x watchdog higher threshold register 2 (ADCx_HTR2) (x=1 to 3) 966 25.5.23 ADC x watchdog lower threshold register 3 (ADCx_LTR3) (x=1 to 3) . 966 25.5.24 ADC x watchdog higher threshold register 3 (ADCx_HTR3) (x=1 to 3) 967 25.5.25 ADC x Differential Mode Selection register (ADCx_DIFSEL) (x=1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 25.5.26 ADC x Calibration Factors register (ADCx_CALFACT) (x=1 to 3) . . . . 968 25.5.27 ADC x Calibration Factor register 2 (ADCx_CALFACT2) (x=1 to 3) . . 968 25.6 24/3178 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 25.6.1 ADC x common status register (ADCx_CSR) (x=12 or 3) . . . . . . . . . . 970 25.6.2 ADC x common control register (ADCx_CCR) (x=12 or 3) . . . . . . . . . 972 25.6.3 ADC x common regular data register for dual mode (ADCx_CDR) (x=12 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 DocID029587 Rev 3 RM0433 26 Contents 25.6.4 ADC x common regular data register for 32-bit dual mode (ADCx_CDR2) (x=12 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 25.6.5 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 26.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 26.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 26.3.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 26.3.2 DAC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 26.3.3 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 26.3.4 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 26.3.5 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 26.3.6 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 26.3.7 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 26.3.8 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 26.3.9 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 26.3.10 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 26.3.11 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 26.3.12 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 26.3.13 Dual DAC channel conversion (if available) . . . . . . . . . . . . . . . . . . . . 993 26.4 DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 26.5 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 26.6 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 26.6.1 DAC x control register (DACx_CR) (x=1 to 2) . . . . . . . . . . . . . . . . . . . 998 26.6.2 DAC x software trigger register (DACx_SWTRGR) (x=1 to 2) . . . . . . 1001 26.6.3 DAC x channel1 12-bit right-aligned data holding register (DACx_DHR12R1) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 26.6.4 DAC x channel1 12-bit left aligned data holding register (DACx_DHR12L1) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 26.6.5 DAC x channel1 8-bit right aligned data holding register (DACx_DHR8R1) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 26.6.6 DAC x channel2 12-bit right aligned data holding register (DACx_DHR12R2) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 26.6.7 DAC x channel2 12-bit left aligned data holding register (DACx_DHR12L2) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 26.6.8 DAC x channel2 8-bit right-aligned data holding register (DACx_DHR8R2) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 DocID029587 Rev 3 25/3178 68 Contents RM0433 26.6.9 Dual DAC x 12-bit right-aligned data holding register (DACx_DHR12RD) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 26.6.10 Dual DAC x 12-bit left aligned data holding register (DACx_DHR12LD) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 26.6.11 Dual DAC x 8-bit right aligned data holding register (DACx_DHR8RD) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005 26.6.12 DAC x channel1 data output register (DACx_DOR1) (x=1 to 2) . . . . 1005 26.6.13 DAC x channel2 data output register (DACx_DOR2) (x=1 to 2) . . . . 1006 26.6.14 DAC x status register (DACx_SR) (x=1 to 2) . . . . . . . . . . . . . . . . . . . 1006 26.6.15 DAC x calibration control register (DACx_CCR) (x=1 to 2) . . . . . . . . 1007 26.6.16 DAC x mode control register (DACx_MCR) (x=1 to 2) . . . . . . . . . . . 1008 26.6.17 DAC x Sample and Hold sample time register 1 (DACx_SHSR1) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 26.6.18 DAC x Sample and Hold sample time register 2 (DACx_SHSR2) (x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 26.6.19 DAC x Sample and Hold hold time register (DACx_SHHR)(x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 26.6.20 DAC x Sample and Hold refresh time register (DACx_SHRR)(x=1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 26.6.21 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 27 28 26/3178 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . 1014 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 27.2 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 27.3 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 27.3.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . 1015 27.3.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . 1016 27.3.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 28.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 28.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 28.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 28.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 28.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 28.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 28.3.5 Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 28.3.6 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 DocID029587 Rev 3 RM0433 Contents 28.3.7 Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . 1021 28.3.8 Comparator output on GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 28.3.9 Comparator output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 28.3.10 COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 29 28.4 COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 28.5 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 28.5.1 Interrupt through EXTI block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 28.5.2 Interrupt through NVIC of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 28.6 SCALER function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 28.7 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 28.7.1 Comparator status register (COMP_SR) . . . . . . . . . . . . . . . . . . . . . . 1026 28.7.2 Comparator interrupt clear flag register (COMP_ICFR) . . . . . . . . . . . 1026 28.7.3 Comparator option register (COMP_OR) . . . . . . . . . . . . . . . . . . . . . 1027 28.7.4 Comparator configuration register 1 (COMP_CFGR1) . . . . . . . . . . . 1028 28.7.5 Comparator configuration register 2 (COMP_CFGR2) . . . . . . . . . . . 1030 28.7.6 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 29.2 OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 29.3 OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 29.3.1 OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 29.3.2 Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 29.3.3 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 29.3.4 OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 29.3.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042 29.4 OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 29.5 OPAMP PGA gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 29.6 OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 29.6.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . 1044 29.6.2 OPAMP1 trimming register in normal mode (OPAMP1_OTR) . . . . . . 1046 29.6.3 OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR) 1047 29.6.4 OPAMP option register (OPAMP_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1047 29.6.5 OPAMP2 control/status register (OPAMP2_CSR) . . . . . . . . . . . . . . . 1047 29.6.6 OPAMP2 trimming register in normal mode (OPAMP2_OTR) . . . . . . 1049 29.6.7 OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR) 1050 DocID029587 Rev 3 27/3178 68 Contents RM0433 29.6.8 30 OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . 1052 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052 30.2 DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053 30.3 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 30.4 DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 30.4.1 DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 30.4.2 DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 30.4.3 DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 30.4.4 Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058 30.4.5 Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 1067 30.4.6 Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 30.4.7 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 30.4.8 Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 30.4.9 Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 30.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072 30.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 30.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 30.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 30.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 30.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 30.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . 1077 30.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 30.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079 28/3178 30.5 DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079 30.6 DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 30.7 DFSDM channel y registers (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 30.7.1 DFSDM channel configuration y register (DFSDM_CHyCFGR1) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 30.7.2 DFSDM channel configuration y register (DFSDM_CHyCFGR2) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 30.7.3 DFSDM channel analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 30.7.4 DFSDM channel watchdog filter data register (DFSDM_CHyWDATR) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 30.7.5 DFSDM channel data input register (DFSDM_CHyDATINR) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 DocID029587 Rev 3 RM0433 Contents 30.8 DFSDM filter x module registers (x=0..3) . . . . . . . . . . . . . . . . . . . . . . . 1086 30.8.1 DFSDM control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . . . . . . . 1086 30.8.2 DFSDM control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . . . . . . . 1089 30.8.3 DFSDM interrupt and status register (DFSDM_FLTxISR) . . . . . . . . . 1090 30.8.4 DFSDM interrupt flag clear register (DFSDM_FLTxICR) . . . . . . . . . . 1092 30.8.5 DFSDM injected channel group selection register (DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 30.8.6 DFSDM filter control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . . 1093 30.8.7 DFSDM data register for injected group (DFSDM_FLTxJDATAR) . . . 1094 30.8.8 DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095 30.8.9 DFSDM analog watchdog high threshold register (DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 30.8.10 DFSDM analog watchdog low threshold register (DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 30.8.11 DFSDM analog watchdog status register (DFSDM_FLTxAWSR) . . . 1097 30.8.12 DFSDM analog watchdog clear flag register (DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097 30.8.13 DFSDM Extremes detector maximum register (DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 30.8.14 DFSDM Extremes detector minimum register (DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 30.8.15 DFSDM conversion timer register (DFSDM_FLTxCNVTIMR) . . . . . . 1099 30.8.16 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109 31.1 DCMI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109 31.2 DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109 31.3 DCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109 31.4 DCMI functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109 31.4.1 DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 31.4.2 DCMI internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 31.4.3 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 31.4.4 DCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 31.4.5 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 31.4.6 Capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116 31.4.7 Crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 31.4.8 JPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118 31.4.9 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118 DocID029587 Rev 3 29/3178 68 Contents RM0433 31.5 Data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 31.5.1 Data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 31.5.2 Monochrome format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 31.5.3 RGB format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 31.5.4 YCbCr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 31.5.5 YCbCr format - Y only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 31.5.6 Half resolution image extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 31.6 DCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1121 31.7 DCMI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1121 31.7.1 DCMI control register (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 31.7.2 DCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 31.7.3 DCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . . 1126 31.7.4 DCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . 1127 31.7.5 DCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . 1128 31.7.6 DCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . 1129 31.7.7 DCMI embedded synchronization code register (DCMI_ESCR) . . . . 1130 31.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR) . 1131 31.7.9 DCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . 1132 31.7.10 DCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . 1132 31.7.11 DCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 31.7.12 DCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134 32 LCD-TFT Display Controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . 1135 32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1135 32.2 LTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1135 32.3 LTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1136 32.4 30/3178 32.3.1 LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 32.3.2 LCD-TFT internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 32.3.3 LCD-TFT pins and external signal interface . . . . . . . . . . . . . . . . . . . 1137 32.3.4 LTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137 LTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1139 32.4.1 LTDC Global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . 1139 32.4.2 Layer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141 32.5 LTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1145 32.6 LTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1146 32.7 LTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1148 DocID029587 Rev 3 RM0433 Contents 32.7.1 LTDC Synchronization Size Configuration Register (LTDC_SSCR) . 1148 32.7.2 LTDC Back Porch Configuration Register (LTDC_BPCR) . . . . . . . . . 1148 32.7.3 LTDC Active Width Configuration Register (LTDC_AWCR) . . . . . . . . 1149 32.7.4 LTDC Total Width Configuration Register (LTDC_TWCR) . . . . . . . . . 1150 32.7.5 LTDC Global Control Register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . 1150 32.7.6 LTDC Shadow Reload Configuration Register (LTDC_SRCR) . . . . . 1152 32.7.7 LTDC Background Color Configuration Register (LTDC_BCCR) . . . 1152 32.7.8 LTDC Interrupt Enable Register (LTDC_IER) . . . . . . . . . . . . . . . . . . 1153 32.7.9 LTDC Interrupt Status Register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . 1154 32.7.10 LTDC Interrupt Clear Register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . 1154 32.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR) 1155 32.7.12 LTDC Current Position Status Register (LTDC_CPSR) . . . . . . . . . . . 1155 32.7.13 LTDC Current Display Status Register (LTDC_CDSR) . . . . . . . . . . . 1156 32.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) . . . . . . 1157 32.7.15 LTDC Layerx Window Horizontal Position Configuration Register (LTDC_LxWHPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1157 32.7.16 LTDC Layerx Window Vertical Position Configuration Register (LTDC_LxWVPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1159 32.7.17 LTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159 32.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160 32.7.19 LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 32.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 32.7.21 LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 32.7.22 LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 32.7.23 LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 32.7.24 LTDC Layerx ColorFrame Buffer Line Number Register (LTDC_LxCFBLNR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 32.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 32.7.26 LTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 33 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1170 DocID029587 Rev 3 31/3178 68 Contents RM0433 33.2 JPEG codec main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1170 33.3 JPEG codec block functional description . . . . . . . . . . . . . . . . . . . . . . . .1171 33.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 33.3.2 JPEG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 33.3.3 JPEG decoding procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172 33.3.4 JPEG encoding procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 33.4 JPEG codec interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175 33.5 JPEG codec registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1176 33.5.1 JPEG codec control register (JPEG_CONFR0) . . . . . . . . . . . . . . . . 1176 33.5.2 JPEG codec configuration register 1 (JPEG_CONFR1) . . . . . . . . . . 1176 33.5.3 JPEG codec configuration register 2 (JPEG_CONFR2) . . . . . . . . . . 1177 33.5.4 JPEG codec configuration register 3 (JPEG_CONFR3) . . . . . . . . . . 1178 33.5.5 JPEG codec configuration register 4-7 (JPEG_CONFR4-7) . . . . . . . 1178 33.5.6 JPEG control register (JPEG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179 33.5.7 JPEG status register (JPEG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 33.5.8 JPEG clear flag register (JPEG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 1181 33.5.9 JPEG data input register (JPEG_DIR) . . . . . . . . . . . . . . . . . . . . . . . . 1182 33.5.10 JPEG data output register (JPEG_DOR) . . . . . . . . . . . . . . . . . . . . . . 1182 33.5.11 JPEG codec register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183 34 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . 1185 34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1185 34.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1185 34.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1186 34.3.1 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 34.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 34.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187 34.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190 34.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 34.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 34.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 34.4 RNG low-power usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193 34.5 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 34.6 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 34.7 Entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 34.7.1 32/3178 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 DocID029587 Rev 3 RM0433 Contents 34.8 35 34.7.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 34.7.3 Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196 34.8.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196 34.8.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197 34.8.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 34.8.4 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 Cryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199 35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1199 35.2 CRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1199 35.3 CRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 35.3.1 CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 35.3.2 CRYP internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 35.3.3 CRYP DES/TDES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . 1202 35.3.4 CRYP AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 35.3.5 CRYP procedure to perform a cipher operation . . . . . . . . . . . . . . . . . 1209 35.3.6 CRYP busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212 35.3.7 Preparing the CRYP AES key for decryption . . . . . . . . . . . . . . . . . . . 1213 35.3.8 CRYP stealing and data padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213 35.3.9 CRYP suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 35.3.10 CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . . . . . . . . 1216 35.3.11 CRYP AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . 1221 35.3.12 CRYP AES counter mode (AES-CTR) . . . . . . . . . . . . . . . . . . . . . . . . 1226 35.3.13 CRYP AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . 1230 35.3.14 CRYP AES Galois message authentication code (GMAC) . . . . . . . . 1235 35.3.15 CRYP AES Counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . 1236 35.3.16 CRYP data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . 1242 35.3.17 CRYP key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 35.3.18 CRYP initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 35.3.19 CRYP DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248 35.3.20 CRYP error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 35.4 CRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 35.5 CRYP processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 35.6 CRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 35.6.1 CRYP control register (CRYP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 DocID029587 Rev 3 33/3178 68 Contents RM0433 35.6.2 CRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255 35.6.3 CRYP data input register (CRYP_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1255 35.6.4 CRYP data output register (CRYP_DOUT) . . . . . . . . . . . . . . . . . . . . 1256 35.6.5 CRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . 1257 35.6.6 CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . 1257 35.6.7 CRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . 1258 35.6.8 CRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . 1258 35.6.9 CRYP key register 0L (CRYP_K0LR) . . . . . . . . . . . . . . . . . . . . . . . . 1259 35.6.10 CRYP key register 0R (CRYP_K0RR) . . . . . . . . . . . . . . . . . . . . . . . . 1260 35.6.11 CRYP key register 1L (CRYP_K1LR) . . . . . . . . . . . . . . . . . . . . . . . . 1260 35.6.12 CRYP key register 1R (CRYP_K1RR) . . . . . . . . . . . . . . . . . . . . . . . . 1260 35.6.13 CRYP key register 2L (CRYP_K2LR) . . . . . . . . . . . . . . . . . . . . . . . . 1261 35.6.14 CRYP key register 2R (CRYP_K2RR) . . . . . . . . . . . . . . . . . . . . . . . . 1261 35.6.15 CRYP key register 3L (CRYP_K3LR) . . . . . . . . . . . . . . . . . . . . . . . . 1262 35.6.16 CRYP key register 3R (CRYP_K3RR) . . . . . . . . . . . . . . . . . . . . . . . . 1262 35.6.17 CRYP initialization vector register 0L (CRYP_IV0LR) . . . . . . . . . . . . 1262 35.6.18 CRYP initialization vector register 0R (CRYP_IV0RR) . . . . . . . . . . . 1263 35.6.19 CRYP initialization vector register 1L (CRYP_IV1LR) . . . . . . . . . . . . 1263 35.6.20 CRYP initialization vector register 1R (CRYP_IV1RR) . . . . . . . . . . . 1263 35.6.21 CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) 1264 35.6.22 CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . . . . . . 1264 35.6.23 CRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266 36 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 36.2 HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 36.3 HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 36.3.1 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 36.3.2 HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 36.3.3 About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 36.3.4 Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 36.3.5 Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 36.3.6 Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 36.3.7 HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 36.3.8 Context swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277 36.3.9 HASH DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 36.3.10 HASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 34/3178 DocID029587 Rev 3 RM0433 37 Contents 36.4 HASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 36.5 HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 36.6 HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281 36.6.1 HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1281 36.6.2 HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1284 36.6.3 HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285 36.6.4 HASH digest registers (HASH_HR0..7) . . . . . . . . . . . . . . . . . . . . . . . 1286 36.6.5 HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . 1288 36.6.6 HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 36.6.7 HASH context swap registers (HASH_CSRx) . . . . . . . . . . . . . . . . . . 1290 36.6.8 HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 High-Resolution Timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 37.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293 37.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 37.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 37.3.2 HRTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 37.3.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297 37.3.4 Timer A..E timing units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 37.3.5 Master timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317 37.3.6 Set/reset events priorities and narrow pulses management . . . . . . . 1318 37.3.7 External events global conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 37.3.8 External event filtering in timing units . . . . . . . . . . . . . . . . . . . . . . . . 1324 37.3.9 Delayed Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329 37.3.10 Register preload and update management . . . . . . . . . . . . . . . . . . . . 1335 37.3.11 Events propagation within or across multiple timers . . . . . . . . . . . . . 1338 37.3.12 Output management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 37.3.13 Burst mode controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 37.3.14 Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 37.3.15 Fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 37.3.16 Auxiliary outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 37.3.17 Synchronizing the HRTIM with other timers or HRTIM instances . . . 1360 37.3.18 ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363 37.3.19 DAC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 37.3.20 HRTIM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366 DocID029587 Rev 3 35/3178 68 Contents RM0433 37.3.21 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 37.3.22 HRTIM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 37.3.23 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372 37.4 37.5 Application use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 37.4.1 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 37.4.2 Buck converter with synchronous rectification . . . . . . . . . . . . . . . . . . 1374 37.4.3 Multiphase converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 37.4.4 Transition mode Power Factor Correction . . . . . . . . . . . . . . . . . . . . . 1377 HRTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379 37.5.1 HRTIM Master Timer Control Register (HRTIM_MCR) . . . . . . . . . . . 1379 37.5.2 HRTIM Master Timer Interrupt Status Register (HRTIM_MISR) . . . . 1382 37.5.3 HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR) . . . . . 1383 37.5.4 HRTIM Master Timer DMA / Interrupt Enable Register (HRTIM_MDIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384 37.5.5 HRTIM Master Timer Counter Register (HRTIM_MCNTR) . . . . . . . . 1386 37.5.6 HRTIM Master Timer Period Register (HRTIM_MPER) . . . . . . . . . . . 1386 37.5.7 HRTIM Master Timer Repetition Register (HRTIM_MREP) . . . . . . . . 1387 37.5.8 HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R) . . . . 1387 37.5.9 HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R) . . . . 1388 37.5.10 HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R) . . . . 1388 37.5.11 HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R) . . . . 1389 37.5.12 HRTIM Timerx Control Register (HRTIM_TIMxCR) . . . . . . . . . . . . . . 1390 37.5.13 HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR) . . . . . . . 1394 37.5.14 HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR) . . . . . . . 1396 37.5.15 HRTIM Timerx DMA / Interrupt Enable Register (HRTIM_TIMxDIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397 37.5.16 HRTIM Timerx Counter Register (HRTIM_CNTxR) . . . . . . . . . . . . . . 1400 37.5.17 HRTIM Timerx Period Register (HRTIM_PERxR) . . . . . . . . . . . . . . . 1400 37.5.18 HRTIM Timerx Repetition Register (HRTIM_REPxR) . . . . . . . . . . . . 1401 37.5.19 HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR) . . . . . . . . . . 1401 37.5.20 HRTIM Timerx Compare 1 Compound Register (HRTIM_CMP1CxR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402 37.5.21 HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR) . . . . . . . . . . 1402 37.5.22 HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR) . . . . . . . . . . 1403 37.5.23 HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR) . . . . . . . . . . 1403 37.5.24 HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR) . . . . . . . . . . . 1404 37.5.25 HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR) . . . . . . . . . . . 1404 37.5.26 HRTIM Timerx Deadtime Register (HRTIM_DTxR) . . . . . . . . . . . . . . 1405 36/3178 DocID029587 Rev 3 RM0433 Contents 37.5.27 HRTIM Timerx Output1 Set Register (HRTIM_SETx1R) . . . . . . . . . . 1407 37.5.28 HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R) . . . . . . . . 1409 37.5.29 HRTIM Timerx Output2 Set Register (HRTIM_SETx2R) . . . . . . . . . . 1409 37.5.30 HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R) . . . . . . . . 1410 37.5.31 HRTIM Timerx External Event Filtering Register 1 (HRTIM_EEFxR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411 37.5.32 HRTIM Timerx External Event Filtering Register 2 (HRTIM_EEFxR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413 37.5.33 HRTIM Timerx Reset Register (HRTIM_RSTxR) . . . . . . . . . . . . . . . . 1414 37.5.34 HRTIM Timerx Chopper Register (HRTIM_CHPxR) . . . . . . . . . . . . . 1417 37.5.35 HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR) . . . . 1419 37.5.36 HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR) . . . . 1420 37.5.37 HRTIM Timerx Output Register (HRTIM_OUTxR) . . . . . . . . . . . . . . . 1423 37.5.38 HRTIM Timerx Fault Register (HRTIM_FLTxR) . . . . . . . . . . . . . . . . . 1426 37.5.39 HRTIM Control Register 1 (HRTIM_CR1) . . . . . . . . . . . . . . . . . . . . . 1427 37.5.40 HRTIM Control Register 2 (HRTIM_CR2) . . . . . . . . . . . . . . . . . . . . . 1429 37.5.41 HRTIM Interrupt Status Register (HRTIM_ISR) . . . . . . . . . . . . . . . . . 1430 37.5.42 HRTIM Interrupt Clear Register (HRTIM_ICR) . . . . . . . . . . . . . . . . . 1431 37.5.43 HRTIM Interrupt Enable Register (HRTIM_IER) . . . . . . . . . . . . . . . . 1432 37.5.44 HRTIM Output Enable Register (HRTIM_OENR) . . . . . . . . . . . . . . . 1433 37.5.45 HRTIM Output Disable Register (HRTIM_ODISR) . . . . . . . . . . . . . . 1434 37.5.46 HRTIM Output Disable Status Register (HRTIM_ODSR) . . . . . . . . . 1435 37.5.47 HRTIM Burst Mode Control Register (HRTIM_BMCR) . . . . . . . . . . . 1436 37.5.48 HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR) . . . . . . . . . 1438 37.5.49 HRTIM Burst Mode Compare Register (HRTIM_BMCMPR) . . . . . . . 1440 37.5.50 HRTIM Burst Mode Period Register (HRTIM_BMPER) . . . . . . . . . . . 1440 37.5.51 HRTIM Timer External Event Control Register 1 (HRTIM_EECR1) . 1441 37.5.52 HRTIM Timer External Event Control Register 2 (HRTIM_EECR2) . 1443 37.5.53 HRTIM Timer External Event Control Register 3 (HRTIM_EECR3) . 1444 37.5.54 HRTIM ADC Trigger 1 Register (HRTIM_ADC1R) . . . . . . . . . . . . . . 1445 37.5.55 HRTIM ADC Trigger 2 Register (HRTIM_ADC2R) . . . . . . . . . . . . . . 1446 37.5.56 HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) . . . . . . . . . . . . . . 1447 37.5.57 HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) . . . . . . . . . . . . . . 1449 37.5.58 HRTIM Fault Input Register 1 (HRTIM_FLTINR1) . . . . . . . . . . . . . . . 1451 37.5.59 HRTIM Fault Input Register 2 (HRTIM_FLTINR2) . . . . . . . . . . . . . . . 1453 37.5.60 HRTIM Burst DMA Master timer update Register (HRTIM_BDMUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 37.5.61 HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR) . . . 1456 DocID029587 Rev 3 37/3178 68 Contents RM0433 37.5.62 HRTIM Burst DMA Data Register (HRTIM_BDMADR) . . . . . . . . . . . 1457 37.5.63 HRTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 38 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 1467 38.1 TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467 38.2 TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467 38.3 TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469 38.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469 38.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471 38.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 38.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484 38.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485 38.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 38.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492 38.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 38.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 38.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494 38.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 38.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498 38.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499 38.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 38.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1501 38.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503 38.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 38.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1509 38.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511 38.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512 38.3.21 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . 1513 38.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514 38.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516 38.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517 38.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517 38.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 38.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524 38.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524 38.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525 38.4 38/3178 TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526 DocID029587 Rev 3 RM0433 Contents 38.4.1 TIM1/TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 1526 38.4.2 TIM1/TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 1527 38.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 1530 38.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 1532 38.4.5 TIM1/TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1534 38.4.6 TIM1/TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 1536 38.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 1537 38.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 1541 38.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 1543 38.4.10 TIM1/TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 38.4.11 TIM1/TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 38.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . 1547 38.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . 1548 38.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . 1548 38.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . 1549 38.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . 1549 38.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . 1550 38.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 1550 38.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . 1553 38.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 1554 38.4.21 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3) . . . . . 1555 38.4.22 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5) . . . . . . . . . . . 1556 38.4.23 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6) . . . . . . . . . . . 1557 38.4.24 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . . . . . . . . 1557 38.4.25 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . . . . . . . . . . . . . 1559 38.4.26 TIM8 Alternate function option register 1 (TIM8_AF1) . . . . . . . . . . . . 1560 38.4.27 TIM8 Alternate function option register 2 (TIM8_AF2) . . . . . . . . . . . . 1562 38.4.28 TIM1 timer input selection register (TIM1_TISEL) . . . . . . . . . . . . . . . 1564 38.4.29 TIM8 timer input selection register (TIM8_TISEL) . . . . . . . . . . . . . . . 1564 38.4.30 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 38.4.31 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569 39 General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 1572 39.1 TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572 39.2 TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . 1572 39.3 TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . 1574 39.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574 DocID029587 Rev 3 39/3178 68 Contents RM0433 39.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576 39.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586 39.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590 39.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592 39.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593 39.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594 39.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594 39.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595 39.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599 39.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599 39.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1600 39.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602 39.3.14 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . 1603 39.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604 39.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606 39.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606 39.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 1607 39.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610 39.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614 39.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615 39.4 TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616 39.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 1616 39.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 1617 39.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . 1619 39.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . 1622 39.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623 39.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . 1624 39.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . 1625 39.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . 1629 39.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 1631 39.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632 39.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633 39.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . 1633 39.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . 1634 39.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . 1634 39.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . 1635 39.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . 1635 40/3178 DocID029587 Rev 3 RM0433 Contents 39.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . 1636 39.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . 1636 39.4.19 TIM2 alternate function option register 1 (TIM2_AF1) . . . . . . . . . . . . 1637 39.4.20 TIM3 alternate function option register 1 (TIM3_AF1) . . . . . . . . . . . . 1637 39.4.21 TIM5 alternate function option register 1 (TIM5_AF1) . . . . . . . . . . . . 1638 39.4.22 TIM2 timer input selection register (TIM2_TISEL) . . . . . . . . . . . . . . . 1638 39.4.23 TIM3 timer input selection register (TIM3_TISEL) . . . . . . . . . . . . . . . 1639 39.4.24 TIM5 timer input selection register (TIM5_TISEL) . . . . . . . . . . . . . . . 1640 39.4.25 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641 40 General-purpose timers (TIM12/TIM13/TIM14) . . . . . . . . . . . . . . . . . 1644 40.1 TIM12/TIM13/TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 40.2 TIM12/TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 40.3 40.2.1 TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 40.2.2 TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645 TIM12/TIM13/TIM14 functional description . . . . . . . . . . . . . . . . . . . . . 1647 40.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647 40.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649 40.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652 40.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 40.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656 40.3.6 PWM input mode (only for TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657 40.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658 40.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659 40.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660 40.3.10 Combined PWM mode (TIM12 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1661 40.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 40.3.12 Retriggerable one pulse mode (OPM) (TIM12 only) . . . . . . . . . . . . . 1664 40.3.13 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 40.3.14 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 40.3.15 TIM12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 1665 40.3.16 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 1668 40.3.17 Timer synchronization (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669 40.3.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669 40.4 TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669 40.4.1 TIM12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 1669 40.4.2 TIM12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 1670 DocID029587 Rev 3 41/3178 68 Contents RM0433 40.4.3 TIM12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . 1672 40.4.4 TIM12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 40.4.5 TIM12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 1673 40.4.6 TIM12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . 1674 40.4.7 TIM12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 1678 40.4.8 TIM12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679 40.4.9 TIM12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679 40.4.10 TIM12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 1680 40.4.11 TIM12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . 1680 40.4.12 TIM12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . 1680 40.4.13 TIM12 timer input selection register (TIM12_TISEL) . . . . . . . . . . . . . 1681 40.4.14 TIM12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682 40.5 TIM13/TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684 40.5.1 TIM13/TIM14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . 1684 40.5.2 TIM13/TIM14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . 1685 40.5.3 TIM13/TIM14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 1685 40.5.4 TIM13/TIM14 event generation register (TIMx_EGR) . . . . . . . . . . . . 1686 40.5.5 TIM13/TIM14 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687 40.5.6 TIM13/TIM14 capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689 40.5.7 TIM13/TIM14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 1690 40.5.8 TIM13/TIM14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . 1691 40.5.9 TIM13/TIM14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 1691 40.5.10 TIM13/TIM14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691 40.5.11 TIM13 timer input selection register (TIM13_TISEL) . . . . . . . . . . . . . 1692 40.5.12 TIM14 timer input selection register (TIM14_TISEL) . . . . . . . . . . . . . 1692 40.5.13 TIM13/TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693 41 42/3178 General-purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . 1695 41.1 TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695 41.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695 41.3 TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696 41.4 TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . 1699 41.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699 41.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701 DocID029587 Rev 3 RM0433 Contents 41.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705 41.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706 41.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708 41.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711 41.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712 41.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713 41.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713 41.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714 41.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1715 41.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1717 41.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719 41.4.14 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723 41.4.15 Retriggerable one pulse mode (OPM) (TIM15 only) . . . . . . . . . . . . . 1724 41.4.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725 41.4.17 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 1726 41.4.18 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 1727 41.4.19 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 1729 41.4.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729 41.4.21 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731 41.4.22 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731 41.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732 41.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1732 41.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1733 41.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 1735 41.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 1736 41.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1737 41.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 1739 41.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . 1740 41.5.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 1743 41.5.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746 41.5.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746 41.5.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 1746 41.5.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 1747 41.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 1747 41.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 1748 41.5.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 1748 41.5.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1751 DocID029587 Rev 3 43/3178 68 Contents RM0433 41.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1751 41.5.18 TIM15 alternate register 1 (TIM15_AF1) . . . . . . . . . . . . . . . . . . . . . . 1752 41.5.19 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 1753 41.5.20 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754 41.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756 41.6.1 TIM16/TIM17 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . 1756 41.6.2 TIM16/TIM17 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . 1757 41.6.3 TIM16/TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 1758 41.6.4 TIM16/TIM17 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 1759 41.6.5 TIM16/TIM17 event generation register (TIMx_EGR) . . . . . . . . . . . . 1760 41.6.6 TIM16/TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . 1761 41.6.7 TIM16/TIM17 capture/compare enable register (TIMx_CCER) . . . . . 1763 41.6.8 TIM16/TIM17 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 1765 41.6.9 TIM16/TIM17 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . 1766 41.6.10 TIM16/TIM17 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 1766 41.6.11 TIM16/TIM17 repetition counter register (TIMx_RCR) . . . . . . . . . . . 1767 41.6.12 TIM16/TIM17 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 1767 41.6.13 TIM16/TIM17 break and dead-time register (TIMx_BDTR) . . . . . . . . 1768 41.6.14 TIM16/TIM17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . 1770 41.6.15 TIM16/TIM17 DMA address for full transfer (TIMx_DMAR) . . . . . . . . 1771 41.6.16 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . 1772 41.6.17 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . 1773 41.6.18 TIM17 alternate function register 1 (TIM17_AF1) . . . . . . . . . . . . . . . 1774 41.6.19 TIM17 input selection register (TIM17_TISEL) . . . . . . . . . . . . . . . . . 1775 41.6.20 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776 42 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778 42.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778 42.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778 42.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779 42.4 42.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779 42.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781 42.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784 42.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784 42.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785 42.4.1 44/3178 TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 1785 DocID029587 Rev 3 RM0433 43 Contents 42.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 1787 42.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 1787 42.4.4 TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1788 42.4.5 TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 1788 42.4.6 TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788 42.4.7 TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789 42.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . 1789 42.4.9 TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791 43.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791 43.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791 43.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791 43.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792 43.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792 43.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794 43.4.3 LPTIM input and trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794 43.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797 43.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797 43.4.6 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798 43.4.7 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799 43.4.8 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799 43.4.9 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801 43.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801 43.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802 43.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803 43.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803 43.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804 43.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804 43.5 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806 43.6 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807 43.6.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . 1807 43.6.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . 1808 43.6.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1808 43.6.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1809 43.6.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1812 DocID029587 Rev 3 45/3178 68 Contents RM0433 43.6.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1814 43.6.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1814 43.6.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1814 43.6.9 LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . 1815 43.6.10 LPTIM3 configuration register 2 (LPTIM3_CFGR2) . . . . . . . . . . . . . 1816 43.6.11 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817 44 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1819 44.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819 44.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819 44.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819 44.4 45 46/3178 44.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 44.3.2 WWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 44.3.3 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 44.3.4 Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 44.3.5 Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . 1821 44.3.6 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1821 44.3.7 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822 .WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823 44.4.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823 44.4.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 1824 44.4.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824 44.4.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826 45.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826 45.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826 45.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826 45.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826 45.3.2 IWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827 45.3.3 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827 45.3.4 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828 45.3.5 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828 45.3.6 Behavior in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . 1828 45.3.7 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828 45.3.8 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828 DocID029587 Rev 3 RM0433 Contents 45.4 46 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829 45.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829 45.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830 45.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831 45.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832 45.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833 45.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835 46.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835 46.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836 46.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836 46.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836 46.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838 46.3.3 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839 46.3.4 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841 46.3.5 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842 46.3.6 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842 46.3.7 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842 46.3.8 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1843 46.3.9 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845 46.3.10 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846 46.3.11 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846 46.3.12 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847 46.3.13 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848 46.3.14 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850 46.3.15 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850 46.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852 46.3.17 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853 46.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853 46.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853 46.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854 46.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854 46.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855 46.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857 46.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . 1860 DocID029587 Rev 3 47/3178 68 Contents RM0433 46.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1863 46.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1864 46.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1865 46.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1866 46.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1867 46.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1867 46.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1868 46.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1869 46.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1870 46.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . 1871 46.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1872 46.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . 1873 46.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1876 46.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1877 46.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878 46.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . 1878 46.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879 47 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1881 47.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881 47.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881 47.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882 47.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882 47.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883 47.4.2 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884 47.4.3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884 47.4.4 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886 47.4.5 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890 47.4.6 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891 47.4.7 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893 47.4.8 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902 47.4.9 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1914 47.4.10 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915 47.4.11 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918 47.4.12 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1920 47.4.13 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921 47.4.14 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . 1929 48/3178 DocID029587 Rev 3 RM0433 Contents 47.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929 47.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931 47.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932 47.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932 47.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933 47.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934 47.7.1 Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934 47.7.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937 47.7.3 Own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 1940 47.7.4 Own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 1941 47.7.5 Timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1942 47.7.6 Timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1943 47.7.7 Interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . . . 1944 47.7.8 Interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946 47.7.9 PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947 47.7.10 Receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1948 47.7.11 Transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1948 47.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949 48 Universal synchronous asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951 48.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951 48.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952 48.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953 48.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953 48.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954 48.5.1 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954 48.5.2 USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955 48.5.3 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956 48.5.4 USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1958 48.5.5 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1958 48.5.6 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962 48.5.7 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1969 48.5.8 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1970 48.5.9 USART Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1971 48.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 1973 DocID029587 Rev 3 49/3178 68 Contents RM0433 48.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975 48.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975 48.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1976 48.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1979 48.5.15 USART single-wire Half-duplex communication . . . . . . . . . . . . . . . . 1983 48.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983 48.5.17 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984 48.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988 48.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . 1991 48.5.20 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1993 48.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1995 48.6 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999 48.7 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001 48.7.1 USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . 2001 48.7.2 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 2006 48.7.3 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 2009 48.7.4 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 2014 48.7.5 USART guard time and prescaler register (USART_GTPR) . . . . . . . 2014 48.7.6 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 2015 48.7.7 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 2016 48.7.8 USART interrupt and status register (USART _ISR) . . . . . . . . . . . . . 2017 48.7.9 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 2024 48.7.10 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 2025 48.7.11 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 2026 48.7.12 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 2026 48.7.13 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028 49 50/3178 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2030 49.1 LPUART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2030 49.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2031 49.3 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2032 49.3.1 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2032 49.3.2 LPUART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033 49.3.3 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033 49.3.4 LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035 49.3.5 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035 DocID029587 Rev 3 RM0433 Contents 49.3.6 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039 49.3.7 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043 49.3.8 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 2044 49.3.9 LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 2045 49.3.10 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047 49.3.11 LPUART single-wire Half-duplex communication . . . . . . . . . . . . . . . 2048 49.3.12 Continuous communication using DMA and LPUART . . . . . . . . . . . . 2048 49.3.13 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 2051 49.3.14 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053 49.4 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056 49.5 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057 49.5.1 Control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057 49.5.2 Control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060 49.5.3 Control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2062 49.5.4 Baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2065 49.5.5 Request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2066 49.5.6 Interrupt & status register (LPUART_ISR) . . . . . . . . . . . . . . . . . . . . . 2066 49.5.7 Interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . . . . . . . . . 2070 49.5.8 Receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . . . . . . . . 2071 49.5.9 Transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . . . . . . . . 2072 49.5.10 Prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . . . . . . . . . 2072 49.5.11 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074 50 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2075 50.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2075 50.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2075 50.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076 50.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076 50.4.1 SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076 50.4.2 SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2078 50.4.3 SPI communication general aspects . . . . . . . . . . . . . . . . . . . . . . . . . 2078 50.4.4 Communications between one master and one slave . . . . . . . . . . . . 2078 50.4.5 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 2081 50.4.6 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2084 50.4.7 Slave select (SS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 2084 50.4.8 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088 DocID029587 Rev 3 51/3178 68 Contents RM0433 50.4.9 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2090 50.4.10 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091 50.4.11 SPI data transmission and reception procedures . . . . . . . . . . . . . . . 2091 50.4.12 Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095 50.4.13 Data packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2096 50.4.14 Communication using DMA (direct memory addressing) . . . . . . . . . 2097 50.5 SPI specific modes and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099 50.5.1 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099 50.5.2 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099 50.5.3 CRC computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2101 50.6 Low-power mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103 50.7 SPI wakeup and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105 50.8 I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2106 50.9 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107 50.9.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107 50.9.2 Pin sharing with SPI function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107 50.9.3 Bits and fields usable in I2S/PCM mode . . . . . . . . . . . . . . . . . . . . . . 2108 50.9.4 Slave and master modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109 50.9.5 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109 50.9.6 Additional Serial Interface Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . 2115 50.9.7 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117 50.9.8 Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2118 50.9.9 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2119 50.9.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2121 50.9.11 FIFOs status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2122 50.9.12 Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123 50.9.13 Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124 50.9.14 Frame error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124 50.9.15 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2126 50.9.16 Programing examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127 50.9.17 Slave I2S Philips standard, receive . . . . . . . . . . . . . . . . . . . . . . . . . . 2129 50.10 I2S wakeup and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130 50.11 SPI/I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2131 50.11.1 SPI/I2S control register 1 (SPI2S_CR1) . . . . . . . . . . . . . . . . . . . . . . 2131 50.11.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132 50.11.3 SPI configuration register 1 (SPI_CFG1) . . . . . . . . . . . . . . . . . . . . . . 2133 52/3178 DocID029587 Rev 3 RM0433 Contents 50.11.4 SPI configuration register 2 (SPI_CFG2) . . . . . . . . . . . . . . . . . . . . . . 2136 50.11.5 SPI/I2S Interrupt Enable Register (SPI2S_IER) . . . . . . . . . . . . . . . . 2138 50.11.6 SPI/I2S Status Register (SPI2S_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 2139 50.11.7 SPI/I2S Interrupt/Status Flags Clear Register (SPI2S_IFCR) . . . . . . 2142 50.11.8 SPI/I2S Transmit Data Register (SPI2S_TXDR) . . . . . . . . . . . . . . . . 2143 50.11.9 SPI/I2S Receive Data Register (SPI2S_RXDR) . . . . . . . . . . . . . . . . 2143 50.11.10 SPI Polynomial Register (SPI_CRCPOLY) . . . . . . . . . . . . . . . . . . . . 2144 50.11.11 SPI Transmitter CRC Register (SPI_TXCRC) . . . . . . . . . . . . . . . . . . 2144 50.11.12 SPI Receiver CRC Register (SPI_RXCRC) . . . . . . . . . . . . . . . . . . . . 2145 50.11.13 SPI Underrun Data Register (SPI_UDRDR) . . . . . . . . . . . . . . . . . . . 2145 50.11.14 SPI/I2S configuration register (SPI_I2SCGFR) . . . . . . . . . . . . . . . . . 2146 50.12 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148 51 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150 51.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150 51.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151 51.3 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152 51.3.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152 51.3.2 SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153 51.3.3 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153 51.3.4 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154 51.3.5 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2155 51.3.6 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156 51.3.7 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159 51.3.8 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2161 51.3.9 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163 51.3.10 PDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2165 51.3.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173 51.3.12 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2175 51.3.13 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2177 51.3.14 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2181 51.3.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2184 51.3.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2184 51.4 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2185 51.5 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2186 51.5.1 Global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . . . . 2186 DocID029587 Rev 3 53/3178 68 Contents RM0433 51.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1) . . . . . . . . . . . . . . 2186 51.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2) . . . . . . . . . . . . . . 2189 51.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR) . . . . . . . . 2191 51.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . 2193 51.5.6 Interrupt mask register 2 (SAI_AIM / SAI_BIM) . . . . . . . . . . . . . . . . . 2194 51.5.7 Status register (SAI_ASR / SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . 2195 51.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR) . . . . . . . . . . . . . . 2197 51.5.9 Data register (SAI_ADR / SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . 2198 51.5.10 PDM control register (SAI_PDMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 2199 51.5.11 PDM delay register (SAI_PDMDLY) . . . . . . . . . . . . . . . . . . . . . . . . . 2200 51.5.12 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2202 52 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 2204 52.1 SPDIFRX interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204 52.2 SPDIFRX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204 52.3 SPDIFRX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204 52.3.1 SPDIFRX pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2205 52.3.2 S/PDIF protocol (IEC-60958) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206 52.3.3 SPDIFRX decoder (SPDIFRX_DC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2208 52.3.4 SPDIFRX tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . . . . . 2212 52.3.5 SPDIFRX synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212 52.3.6 SPDIFRX handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214 52.3.7 Data reception management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216 52.3.8 Dedicated control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2218 52.3.9 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219 52.3.10 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2221 52.3.11 Symbol clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2222 52.3.12 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2223 52.3.13 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2224 52.3.14 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225 52.4 52.5 54/3178 Programming procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225 52.4.1 Initialization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226 52.4.2 Handling of interrupts coming from SPDIFRX . . . . . . . . . . . . . . . . . . 2227 52.4.3 Handling of interrupts coming from DMA . . . . . . . . . . . . . . . . . . . . . . 2227 SPDIFRX interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2228 52.5.1 Control register (SPDIFRX_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2228 52.5.2 Interrupt mask register (SPDIFRX_IMR) . . . . . . . . . . . . . . . . . . . . . . 2231 DocID029587 Rev 3 RM0433 Contents 52.5.3 Status register (SPDIFRX_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232 52.5.4 Interrupt flag clear register (SPDIFRX_IFCR) . . . . . . . . . . . . . . . . . . 2233 52.5.5 Data input register (SPDIFRX_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2235 52.5.6 Data input register (SPDIFRX_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2236 52.5.7 Data input register (SPDIFRX_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2237 52.5.8 Channel status register (SPDIFRX_CSR) . . . . . . . . . . . . . . . . . . . . . 2238 52.5.9 Debug Information register (SPDIFRX_DIR) . . . . . . . . . . . . . . . . . . . 2239 52.5.10 SPDIFRX version register (SPDIFRX_VERR) . . . . . . . . . . . . . . . . . . 2240 52.5.11 SPDIFRX identification register (SPDIFRX_IDR) . . . . . . . . . . . . . . . 2240 52.5.12 SPDIFRX size identification register (SPDIFRX_SIDR) . . . . . . . . . . 2241 52.5.13 SPDIFRX interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242 53 Single Wire Protocol Master Interface (SWPMI) . . . . . . . . . . . . . . . . 2243 53.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243 53.2 SWPMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244 53.3 SWPMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245 53.3.1 SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245 53.3.2 SWPMI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245 53.3.3 SWP initialization and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246 53.3.4 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246 53.3.5 SWPMI_IO (internal transceiver) bypass . . . . . . . . . . . . . . . . . . . . . . 2248 53.3.6 SWPMI Bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248 53.3.7 SWPMI frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249 53.3.8 Transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249 53.3.9 Reception procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2254 53.3.10 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258 53.3.11 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260 53.4 SWPMI low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260 53.5 SWPMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261 53.6 SWPMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2262 53.6.1 SWPMI Configuration/Control register (SWPMI_CR) . . . . . . . . . . . . 2262 53.6.2 SWPMI Bitrate register (SWPMI_BRR) . . . . . . . . . . . . . . . . . . . . . . . 2263 53.6.3 SWPMI Interrupt and Status register (SWPMI_ISR) . . . . . . . . . . . . . 2264 53.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . . . . . . . . . . 2265 53.6.5 SWPMI Interrupt Enable register (SMPMI_IER) . . . . . . . . . . . . . . . . 2266 53.6.6 SWPMI Receive Frame Length register (SWPMI_RFL) . . . . . . . . . . 2268 DocID029587 Rev 3 55/3178 68 Contents RM0433 53.6.7 SWPMI Transmit data register (SWPMI_TDR) . . . . . . . . . . . . . . . . . 2268 53.6.8 SWPMI Receive data register (SWPMI_RDR) . . . . . . . . . . . . . . . . . 2268 53.6.9 SWPMI Option register (SWPMI_OR) . . . . . . . . . . . . . . . . . . . . . . . . 2269 53.6.10 SWPMI register map and reset value table . . . . . . . . . . . . . . . . . . . . 2270 54 Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . 2271 54.1 MDIOS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271 54.2 MDIOS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2271 54.3 MDIOS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272 54.3.1 MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272 54.3.2 MDIOS pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272 54.3.3 MDIOS protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273 54.3.4 MDIOS enabling and disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2274 54.3.5 MDIOS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2274 54.3.6 MDIOS APB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2275 54.3.7 Write/read flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2275 54.3.8 MDIOS error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2276 54.3.9 MDIOS in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2277 54.3.10 MDIOS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278 54.4 MDIOS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2279 54.4.1 MDIOS configuration register (MDIOS_CR) . . . . . . . . . . . . . . . . . . . 2279 54.4.2 MDIOS write flag register (MDIOS_WRFR) . . . . . . . . . . . . . . . . . . . . 2280 54.4.3 MDIOS clear write flag register (MDIOS_CWRFR) . . . . . . . . . . . . . . 2280 54.4.4 MDIOS read flag register (MDIOS_RDFR) . . . . . . . . . . . . . . . . . . . . 2281 54.4.5 MDIOS clear read flag register (MDIOS_CRDFR) . . . . . . . . . . . . . . 2281 54.4.6 MDIOS status register (MDIOS_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 2282 54.4.7 MDIOS clear flag register (MDIOS_CLRFR) . . . . . . . . . . . . . . . . . . . 2283 54.4.8 MDIOS input data register (MDIOS_DINR0-MDIOS_DINR31) . . . . . 2284 54.4.9 MDIOS output data register (MDIOS_DOUTR0-MDIOS_DOUTR31) 2284 54.4.10 MDIOS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285 55 56/3178 Secure digital input/output MultiMediaCard interface (SDMMC) . . 2287 55.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2287 55.2 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2287 55.3 SDMMC operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289 55.4 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290 DocID029587 Rev 3 RM0433 Contents 55.5 55.4.1 SDMMC diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291 55.4.2 SDMMC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291 55.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2292 55.4.4 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2294 55.4.5 SDMMC AHB slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315 55.4.6 SDMMC AHB master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2316 55.4.7 MDMA request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2317 55.4.8 AHB and SDMMC_CK clock relation . . . . . . . . . . . . . . . . . . . . . . . . . 2318 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318 55.5.1 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318 55.5.2 CMD12 send timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327 55.5.3 Sleep (CMD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2330 55.5.4 Interrupt mode (Wait-IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2331 55.5.5 Boot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2332 55.5.6 Response R1b handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335 55.5.7 Reset and card cycle power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2336 55.6 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2337 55.7 Ultra-high-speed phase I (UHS-I) voltage switch . . . . . . . . . . . . . . . . . 2338 55.8 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2341 55.8.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 2341 55.8.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 2342 55.8.3 SDMMC argument register (SDMMC_ARGR) . . . . . . . . . . . . . . . . . . 2344 55.8.4 SDMMC command register (SDMMC_CMDR) . . . . . . . . . . . . . . . . . 2346 55.8.5 SDMMC command response register (SDMMC_RESPCMDR) . . . . 2347 55.8.6 SDMMC response 1..4 register (SDMMC_RESPxR) (x = 1..4) . . . . . 2348 55.8.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . . 2348 55.8.8 SDMMC data length register (SDMMC_DLENR) . . . . . . . . . . . . . . . 2349 55.8.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 2350 55.8.10 SDMMC data counter register (SDMMC_DCNTR) . . . . . . . . . . . . . . 2351 55.8.11 SDMMC status register (SDMMC_STAR) . . . . . . . . . . . . . . . . . . . . . 2353 55.8.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 2355 55.8.13 SDMMC mask register (SDMMC_MASKR) . . . . . . . . . . . . . . . . . . . . 2358 55.8.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 2360 55.8.15 SDMMC data FIFO register (SDMMC_FIFOR) . . . . . . . . . . . . . . . . . 2362 55.8.16 SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . . . . . . . 2362 55.8.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . . 2363 DocID029587 Rev 3 57/3178 68 Contents RM0433 55.8.18 SDMMC IDMA buffer 0 base address register (SDMMC_IDMABASE0R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2363 55.8.19 SDMMC IDMA buffer 1 base address register (SDMMC_IDMABASE1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2364 55.8.20 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365 56 FD Controller Area Network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . 2368 56.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2368 56.2 FDCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2371 56.3 FDCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2372 56.3.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2373 56.3.2 Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382 56.3.3 FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2393 56.3.4 Clock calibration on CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2394 56.3.5 TTCAN operations (FDCAN1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 2398 56.3.6 TTCAN configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 56.3.7 Message scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2402 56.3.8 TTCAN gap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409 56.3.9 Stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409 56.3.10 Local time, cycle time, global time, and external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 2410 56.3.11 TTCAN error level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413 56.3.12 TTCAN message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2414 56.3.13 TTCAN interrupt and error handling . . . . . . . . . . . . . . . . . . . . . . . . . 2417 56.3.14 Level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417 56.3.15 Synchronization to external time schedule . . . . . . . . . . . . . . . . . . . . 2420 56.3.16 FDCAN Rx Buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . 2421 56.3.17 FDCAN Tx Buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423 56.3.18 FDCAN Tx Event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425 56.3.19 FDCAN Standard message ID Filter element . . . . . . . . . . . . . . . . . . 2426 56.3.20 FDCAN Extended message ID filter element . . . . . . . . . . . . . . . . . . 2428 56.3.21 FDCAN Trigger memory element . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429 56.4 58/3178 FDCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2431 56.4.1 FDCAN Core Release Register (FDCAN_CREL) . . . . . . . . . . . . . . . 2431 56.4.2 FDCAN Core Release Register (FDCAN_ENDN) . . . . . . . . . . . . . . . 2432 56.4.3 FDCAN Data Bit Timing and Prescaler Register (FDCAN_DBTP) . . 2432 56.4.4 FDCAN Test Register (FDCAN_TEST) . . . . . . . . . . . . . . . . . . . . . . . 2433 56.4.5 FDCAN RAM Watchdog Register (FDCAN_RWD) . . . . . . . . . . . . . . 2434 DocID029587 Rev 3 RM0433 Contents 56.4.6 FDCAN CC Control Register (FDCAN_CCCR) . . . . . . . . . . . . . . . . . 2435 56.4.7 FDCAN Nominal Bit Timing and Prescaler Register (FDCAN_NBTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2436 56.4.8 FDCAN Timestamp Counter Configuration Register (FDCAN_TSCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2437 56.4.9 FDCAN Timestamp Counter Value Register (FDCAN_TSCV) . . . . . 2438 56.4.10 FDCAN Timeout Counter Configuration Register (FDCAN_TOCC) . 2439 56.4.11 FDCAN Timeout Counter Value Register (FDCAN_TOCV) . . . . . . . . 2439 56.4.12 FDCAN Error Counter Register (FDCAN_ECR) . . . . . . . . . . . . . . . . 2440 56.4.13 FDCAN Protocol Status Register (FDCAN_PSR) . . . . . . . . . . . . . . . 2441 56.4.14 FDCAN Transmitter Delay Compensation Register (FDCAN_TDCR) 2443 56.4.15 FDCAN Interrupt Register (FDCAN_IR) . . . . . . . . . . . . . . . . . . . . . . 2443 56.4.16 FDCAN Interrupt Enable Register (FDCAN_IE) . . . . . . . . . . . . . . . . 2446 56.4.17 FDCAN Interrupt Line Select Register (FDCAN_ILS) . . . . . . . . . . . . 2449 56.4.18 FDCAN Interrupt Line Enable Register (FDCAN_ILE) . . . . . . . . . . . 2450 56.4.19 FDCAN Global Filter Configuration Register (FDCAN_GFC) . . . . . . 2451 56.4.20 FDCAN Standard ID Filter Configuration Register (FDCAN_SIDFC) 2452 56.4.21 FDCAN Extended ID Filter Configuration Register (FDCAN_XIDFC) 2452 56.4.22 FDCAN Extended ID and Mask Register (FDCAN_XIDAM) . . . . . . . 2453 56.4.23 FDCAN High Priority Message Status Register (FDCAN_HPMS) . . . 2454 56.4.24 FDCAN New Data 1 Register (FDCAN_NDAT1) . . . . . . . . . . . . . . . . 2454 56.4.25 FDCAN New Data 2 Register (FDCAN_NDAT2) . . . . . . . . . . . . . . . . 2455 56.4.26 FDCAN Rx FIFO 0 Configuration Register (FDCAN_RXF0C) . . . . . 2455 56.4.27 FDCAN Rx FIFO 0 Status Register (FDCAN_RXF0S) . . . . . . . . . . . 2456 56.4.28 FDCAN Rx FIFO 0 Acknowledge Register (FDCAN_RXF0A) . . . . . . 2457 56.4.29 FDCAN Rx Buffer Configuration Register (FDCAN_RXBC) . . . . . . . 2457 56.4.30 FDCAN Rx FIFO 1 Configuration Register (FDCAN_RXF1C) . . . . . 2458 56.4.31 FDCAN Rx FIFO 1 Status Register (FDCAN_RXF1S) . . . . . . . . . . . 2459 56.4.32 FDCAN Rx FIFO 1 Acknowledge Register (FDCAN_RXF1A) . . . . . . 2460 56.4.33 FDCAN Rx Buffer Element Size Configuration Register (FDCAN_RXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460 56.4.34 FDCAN Tx Buffer Configuration Register (FDCAN_TXBC) . . . . . . . . 2461 56.4.35 FDCAN Tx FIFO/Queue Status Register (FDCAN_TXFQS) . . . . . . . 2462 56.4.36 FDCAN Tx Buffer Element Size Configuration Register (FDCAN_TXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463 56.4.37 FDCAN Tx Buffer Request Pending Register (FDCAN_TXBRP) . . . 2464 56.4.38 FDCAN Tx Buffer Add Request Register (FDCAN_TXBAR) . . . . . . . 2465 56.4.39 FDCAN Tx Buffer Cancellation Request Register (FDCAN_TXBCR) 2465 DocID029587 Rev 3 59/3178 68 Contents RM0433 56.4.40 FDCAN Tx Buffer Transmission Occurred Register (FDCAN_TXBTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2466 56.4.41 FDCAN Tx Buffer Cancellation Finished Register (FDCAN_TXBCF) 2466 56.4.42 FDCAN Tx Buffer Transmission Interrupt Enable Register (FDCAN_TXBTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467 56.4.43 FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register (FDCAN_ TXBCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467 56.4.44 FDCAN Tx Event FIFO Configuration Register (FDCAN_TXEFC) . . 2468 56.4.45 FDCAN Tx Event FIFO Status Register (FDCAN_TXEFS) . . . . . . . . 2469 56.4.46 FDCAN Tx Event FIFO Acknowledge Register (FDCAN_TXEFA) . . 2469 56.4.47 FDCAN TT Trigger Memory Configuration Register (FDCAN_TTTMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470 56.4.48 FDCAN TT Reference Message Configuration Register (FDCAN_TTRMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2471 56.4.49 FDCAN TT Operation Configuration Register (FDCAN_TTOCF) . . . 2472 56.4.50 FDCAN TT Matrix Limits Register (FDCAN_TTMLM) . . . . . . . . . . . . 2473 56.4.51 FDCAN TUR Configuration Register (FDCAN_TURCF) . . . . . . . . . . 2474 56.4.52 FDCAN TT Operation Control Register (FDCAN_TTOCN) . . . . . . . . 2476 56.4.53 FDCAN TT Global Time Preset Register (CAN_TTGTP) . . . . . . . . . 2477 56.4.54 FDCAN TT Time Mark Register (FDCAN_TTTMK) . . . . . . . . . . . . . . 2478 56.4.55 FDCAN TT Interrupt Register (FDCAN_TTIR) . . . . . . . . . . . . . . . . . 2479 56.4.56 FDCAN TT Interrupt Enable Register (FDCAN_TTIE) . . . . . . . . . . . 2481 56.4.57 FDCAN TT Interrupt Line Select Register (FDCAN_TTILS) . . . . . . . 2483 56.4.58 FDCAN TT Operation Status Register (FDCAN_TTOST) . . . . . . . . . 2484 56.4.59 FDCAN TUR Numerator Actual Register (FDCAN_TURNA) . . . . . . 2486 56.4.60 FDCAN TT Local and Global Time Register (FDCAN_TTLGT) . . . . . 2487 56.4.61 FDCAN TT Cycle Time and Count Register (FDCAN_TTCTC) . . . . . 2487 56.4.62 FDCAN TT Capture Time Register (FDCAN_TTCPT) . . . . . . . . . . . . 2488 56.4.63 FDCAN TT Cycle Sync Mark Register (FDCAN_TTCSM) . . . . . . . . 2488 56.4.64 FDCAN TT Trigger Select Register (FDCAN_TTTS) . . . . . . . . . . . . . 2489 56.4.65 FDCAN register map and reset value table . . . . . . . . . . . . . . . . . . . . 2490 56.5 60/3178 CCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2496 56.5.1 Clock Calibration Unit Core Release Register (CCU_CREL) . . . . . . 2496 56.5.2 Calibration Configuration Register (CCU_CCFG) . . . . . . . . . . . . . . . 2496 56.5.3 Calibration Status Register (CCU_CSTAT) . . . . . . . . . . . . . . . . . . . . 2498 56.5.4 Calibration Watchdog Register (CCU_CWD) . . . . . . . . . . . . . . . . . . 2499 56.5.5 Clock Calibration Unit Interrupt Register (CCU_IR) . . . . . . . . . . . . . . 2500 56.5.6 Clock Calibration Unit Interrupt Enable Register (CCU_IE) . . . . . . . . 2500 DocID029587 Rev 3 RM0433 Contents 56.5.7 57 CCU register map and reset value table . . . . . . . . . . . . . . . . . . . . . . 2501 USB on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . . . . . . . . . . 2502 57.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502 57.2 OTG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503 57.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2504 57.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2505 57.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2505 57.3 OTG Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506 57.4 OTG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506 57.5 57.6 57.7 57.8 57.9 57.4.1 OTG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506 57.4.2 USB OTG pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2508 57.4.3 OTG core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2508 57.4.4 Embedded full speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2509 57.4.5 High-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2509 57.4.6 External Full-speed OTG PHY using the I2C interface . . . . . . . . . . . 2509 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510 57.5.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510 57.5.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510 57.5.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2511 57.6.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511 57.6.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511 57.6.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2512 USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2514 57.7.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515 57.7.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515 57.7.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2516 57.7.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2518 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519 57.8.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519 57.8.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2520 57.10 Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . . . . . . . . . 2520 57.11 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2521 57.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2522 DocID029587 Rev 3 61/3178 68 Contents RM0433 57.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523 57.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2524 57.12 OTG_HS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2526 57.13 OTG_HS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . 2526 57.13.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2527 57.14 OTG_HS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2532 57.14.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 2532 57.14.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 2534 57.14.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 2535 57.14.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 2537 57.14.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 2540 57.14.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 2542 57.14.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 2547 57.14.8 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP) . . . . . . . . . . . . . . 2550 57.14.9 OTG Receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 2551 57.14.10 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2552 57.14.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2553 57.14.12 OTG I2C access register (OTG_GI2CCTL) . . . . . . . . . . . . . . . . . . . . 2553 57.14.13 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 2555 57.14.14 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2556 57.14.15 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 2556 57.14.16 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2561 57.14.17 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..8, where x is the FIFO_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2561 57.14.18 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2561 57.14.19 OTG Host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 2562 57.14.20 OTG Host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 2562 57.14.21 OTG Host frame number/frame time remaining register (OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2563 57.14.22 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2564 57.14.23 OTG Host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 2564 57.14.24 OTG Host all channels interrupt mask register (OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2565 62/3178 DocID029587 Rev 3 RM0433 Contents 57.14.25 OTG Host port control and status register (OTG_HPRT) . . . . . . . . . 2565 57.14.26 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 2568 57.14.27 OTG Host channel-x split control register (OTG_HCSPLTx) (x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 2569 57.14.28 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 2570 57.14.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 2571 57.14.30 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 2572 57.14.31 OTG Host channel-x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 2574 57.14.32 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2574 57.14.33 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 2574 57.14.34 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 2576 57.14.35 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 2578 57.14.36 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2579 57.14.37 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2580 57.14.38 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 2581 57.14.39 OTG all endpoints interrupt mask register (OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582 57.14.40 OTG device VBUS discharge time register (OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582 57.14.41 OTG device VBUS pulsing time register (OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2583 57.14.42 OTG Device threshold control register (OTG_DTHRCTL) . . . . . . . . 2583 57.14.43 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2584 57.14.44 OTG device each endpoint interrupt register (OTG_DEACHINT) . . . 2585 57.14.45 OTG device each endpoint interrupt register mask (OTG_DEACHINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2585 57.14.46 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 0..8, where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . 2586 57.14.47 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588 57.14.48 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..8, where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . 2590 57.14.49 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..8, where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . 2592 DocID029587 Rev 3 63/3178 68 Contents RM0433 57.14.50 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..8, where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . 2593 57.14.51 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595 57.14.52 OTG Device channel-x DMA address register (OTG_DIEPDMAx) (x = 0..15, where x= Channel_number) . . . . . . . . . . . . . . . . . . . . . . . 2595 57.14.53 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2596 57.14.54 OTG Device channel-x DMA address register (OTG_DOEPDMAx) (x = 0..15, where x= Channel_number) . . . . . . . . . . . . . . . . . . . . . . . 2597 57.14.55 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..8, where x= Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . 2597 57.14.56 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..8, where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2598 57.14.57 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..8, where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599 57.14.58 OTG power and clock gating control register (OTG_PCGCCTL) . . . 2600 57.14.59 OTG_HS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600 57.15 OTG_HS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2610 57.15.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2610 57.15.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2611 57.15.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2611 57.15.4 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2612 57.15.5 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2612 57.15.6 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2644 57.15.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2662 57.15.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2664 58 Ethernet (ETH): media access control (MAC) with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670 58.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670 58.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670 58.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670 58.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2673 58.2.3 Bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2673 58.3 Ethernet pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2674 58.4 Ethernet architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2676 58.4.1 64/3178 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2677 DocID029587 Rev 3 RM0433 Contents 58.5 58.4.2 MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684 58.4.3 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684 Ethernet functional description: MAC . . . . . . . . . . . . . . . . . . . . . . . . . . 2689 58.5.1 Double VLAN processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2689 58.5.2 Source Address and VLAN insertion, replacement, or deletion . . . . . 2690 58.5.3 Packet filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2692 58.5.4 IEEE 1588 timestamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2699 58.5.5 IPv4 ARP offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2711 58.5.6 TCP segmentation offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712 58.5.7 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2716 58.5.8 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2716 58.5.9 Checksum offload engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2718 58.5.10 MAC management counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2723 58.5.11 Interrupts generated by the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2723 58.5.12 MAC and MMC register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 2723 58.6 58.7 58.8 58.9 Ethernet functional description: PHY interfaces . . . . . . . . . . . . . . . . . . 2724 58.6.1 Station management agent (SMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2724 58.6.2 Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2728 58.6.3 Reduced media independent interface (RMII) . . . . . . . . . . . . . . . . . . 2729 Ethernet low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2732 58.7.1 Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2732 58.7.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2733 58.7.3 Power-down and wakeup sequence . . . . . . . . . . . . . . . . . . . . . . . . . 2735 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2736 58.8.1 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2736 58.8.2 MTL interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2737 58.8.3 MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2738 Ethernet programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739 58.9.1 DMA initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739 58.9.2 MTL initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2740 58.9.3 MAC initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2740 58.9.4 Performing normal receive and transmit operation . . . . . . . . . . . . . . 2741 58.9.5 Stopping and starting transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 2741 58.9.6 Programming guidelines for MII link state transitions . . . . . . . . . . . . 2742 58.9.7 Programming guidelines for IEEE 1588 timestamping . . . . . . . . . . . 2743 58.9.8 Programming guidelines for Energy Efficient Ethernet (EEE) . . . . . . 2744 DocID029587 Rev 3 65/3178 68 Contents RM0433 58.9.9 Programming guidelines for flexible pulse-per-second (PPS) output 2745 58.9.10 Programming guidelines for TSO . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746 58.9.11 Programming guidelines to perform VLAN filtering on the receive . . 2747 58.10 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748 58.10.1 Descriptor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748 58.10.2 Descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748 58.10.3 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750 58.10.4 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2762 58.11 Ethernet registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774 58.11.1 Ethernet registers maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774 58.11.2 Ethernet DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774 58.11.3 Ethernet MTL registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2801 58.11.4 Ethernet MAC and MMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2814 59 HDMI-CEC controller (HDMI-CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2915 59.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2915 59.2 HDMI-CEC controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2915 59.3 HDMI-CEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916 59.4 59.3.1 HDMI-CEC pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2916 59.3.2 HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2917 59.3.3 Message description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2918 59.3.4 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2918 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919 59.4.1 59.5 66/3178 SFT option bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921 59.5.1 Bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921 59.5.2 Message error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921 59.5.3 Bit Rising Error (BRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2922 59.5.4 Short Bit Period Error (SBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2922 59.5.5 Long Bit Period Error (LBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2922 59.5.6 Transmission Error Detection (TXERR) . . . . . . . . . . . . . . . . . . . . . . . 2924 59.6 HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2925 59.7 HDMI-CEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926 59.7.1 CEC control register (CEC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926 59.7.2 CEC configuration register (CEC_CFGR) . . . . . . . . . . . . . . . . . . . . . 2927 59.7.3 CEC Tx data register (CEC_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . 2930 DocID029587 Rev 3 RM0433 60 Contents CEC Rx Data Register (CEC_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . 2930 59.7.5 CEC Interrupt and Status Register (CEC_ISR) . . . . . . . . . . . . . . . . . 2930 59.7.6 CEC interrupt enable register (CEC_IER) . . . . . . . . . . . . . . . . . . . . . 2932 59.7.7 HDMI-CEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2934 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2935 60.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2935 60.2 Debug infrastructure features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936 60.3 Debug infrastructure functional description . . . . . . . . . . . . . . . . . . . . . 2936 60.4 60.5 60.6 60.7 61 59.7.4 60.3.1 Debug infrastructure block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2936 60.3.2 Debug infrastructure pins and internal signals . . . . . . . . . . . . . . . . . . 2937 60.3.3 Debug infrastructure powering, clocking and reset . . . . . . . . . . . . . . 2938 Debug access port functional description . . . . . . . . . . . . . . . . . . . . . . . 2940 60.4.1 Serial-wire and JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . 2940 60.4.2 Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2954 Trace and debug subsystem functional description . . . . . . . . . . . . . . . 2960 60.5.1 System ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960 60.5.2 Global timestamp generator (TSG) . . . . . . . . . . . . . . . . . . . . . . . . . . 2968 60.5.3 Cross trigger interfaces (CTI) and matrix (CTM) . . . . . . . . . . . . . . . . 2976 60.5.4 Trace funnel (CSTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2995 60.5.5 Embedded trace FIFO (ETF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3005 60.5.6 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3027 60.5.7 Serial wire output (SWO) and SWO trace funnel (SWTF) . . . . . . . . . 3046 60.5.8 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . 3068 Cortex-M7 debug functional description . . . . . . . . . . . . . . . . . . . . . . . . 3076 60.6.1 Cortex-M7 ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3077 60.6.2 Cortex-M7 data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . 3089 60.6.3 Cortex-M7 instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . 3103 60.6.4 Cortex-M7 breakpoint unit (FPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3111 60.6.5 Cortex-M7 embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . 3119 60.6.6 Cortex-M7 cross trigger interface (CTI) . . . . . . . . . . . . . . . . . . . . . . . 3151 References for debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . 3152 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3153 61.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3153 61.2 Flash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3154 DocID029587 Rev 3 67/3178 68 Contents RM0433 61.3 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3154 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3155 68/3178 DocID029587 Rev 3 RM0433 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Bus-master-to-bus-slave interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 FLASH input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . 113 FLASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Flash module - 1 Mbyte dual bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Number of wait states according to bus frequency (ACLK) and VCORE range . . . . . . . . 118 Parallelism parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Programming speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 List of Flash user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 RDP value vs readout protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Allowed accesses versus Readout protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 AXI interfaces memory mapping SWAP_BANK = ‘0’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 AXI interfaces memory mapping SWAP_BANK = ‘1’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Bank swapping sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 FLASH register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 List of preferred terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Flash protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Secure user software selection use-cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Summary of Flash protected areas access rights. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 ASIB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 AMIB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 AXI interconnect register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 PWR input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 218 PWR internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Supply configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 PDDS_Dn low-power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Low-power exit mode flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 CSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 CStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 DStop mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 DStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 DStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Standby and Stop flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Power control register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 BDMA and DMAMUX2 interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) . . . . . . . . . . . . . . . . . . 278 LPUART1 Initial programming (LPUART1_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 LPUART1 Initial programming (LPUART1_Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 RCC input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 284 RCC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Reset distribution summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Reset source identification (RCC_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Ratio between clock timer and pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 DocID029587 Rev 3 69/3178 80 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. 70/3178 RM0433 STOPWUCK and STOPKERWUCK description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 HSIKERON and CSIKERON behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Kernel clock distribution overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 System states overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Peripheral clock enabling for D1 and D2 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Peripheral clock enabling for D3 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Interrupt sources and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 RCC_RSR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 RCC_AHB3ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 RCC_AHB1ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 RCC_AHB2ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 RCC_AHB4ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 RCC_APB3ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 RCC_APB1ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 RCC_APB1ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 RCC_APB2ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 RCC_APB4ENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 RCC_AHB3LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 RCC_AHB1LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 RCC_AHB2LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 RCC_AHB4LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 RCC_APB3LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 RCC_APB1LLPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 RCC_APB1HLPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 RCC_APB2LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 RCC_APB4LPENR address offset and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 CRS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 HSEM internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Authorized AHB bus master ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 HSEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Peripherals interconnect matrix (D2 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Peripherals interconnect matrix (D3 domain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 Peripherals interconnect matrix details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 EXTI wakeup inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 EXTI pending requests clear inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 MDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 DMAMUX1, DMA1 and DMA2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 DMAMUX2 and BDMA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 MDMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 MDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 MDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Source and destination address registers in double buffer mode (DBM=1) . . . . . . . . . . . 597 Packing/unpacking & endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . . . 598 DocID029587 Rev 3 RM0433 Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. List of tables Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 Programmable data width & endianness (when bits PINC = MINC = 1). . . . . . . . . . . . . . 625 BDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 BDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 DMAMUX1 and DMAMUX2 instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 DMAMUX1: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 637 DMAMUX1: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 DMAMUX1: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . 639 DMAMUX2: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 639 DMAMUX2: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 DMAMUX2: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . 640 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 DMA2D internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 Supported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Alpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Supported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 CLUT data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Supported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 MCU order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 DMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 DMA2D register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 NVIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 EXTI Event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 Configurable Event input Asynchronous Edge detector reset . . . . . . . . . . . . . . . . . . . . . 703 EXTI Event input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 Asynchronous interrupt/event controller register map and reset values . . . . . . . . . . . . . . 728 CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 FMC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 FMC bank mapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 SDRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 SDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 SDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 SDRAM address mapping with 32-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Non-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 DocID029587 Rev 3 71/3178 80 List of tables Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. Table 198. Table 199. Table 200. Table 201. Table 202. Table 203. Table 204. 72/3178 RM0433 16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 NOR Flash/PSRAM: Example of supported memories and transactions . . . . . . . . . . . . . 751 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 Programmable NAND Flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 8-bit NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 16-bit NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 SDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 QUADSPI internal signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 DLYB internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 Delay block control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 DLYB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 879 Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 879 ADC1, ADC2 and ADC3 - External triggers for regular channels . . . . . . . . . . . . . . . . . . . 880 ADC1, ADC2 and ADC3 - External triggers for injected channels . . . . . . . . . . . . . . . . . . 881 TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 16-bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 Numerical examples for 16-bit format (bold indicates saturation). . . . . . . . . . . . . . . . . . . 899 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907 Analog watchdog 1,2,3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908 Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 DocID029587 Rev 3 RM0433 List of tables Table 205. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 Table 206. ADC register map and reset values (master and slave ADC common registers) offset =0x300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 Table 207. DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 Table 208. DAC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 Table 209. DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Table 210. Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 Table 211. Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 Table 212. Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 Table 213. DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 Table 214. DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 Table 215. VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 Table 216. VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 Table 217. COMP input/output internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 Table 218. COMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 Table 219. COMP1_OUT assignment to GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 Table 220. COMP2_OUT assignment to GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 Table 221. Comparator behavior in the low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 Table 222. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 Table 223. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 Table 224. COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 Table 225. Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 Table 226. Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042 Table 227. Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 Table 228. OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 Table 229. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 Table 230. DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 Table 231. DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 Table 232. DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 Table 233. DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 Table 234. Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 Table 235. Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . 1072 Table 236. DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080 Table 237. DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 Table 238. DCMI internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 Table 239. DCMI external signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 Table 240. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . 1112 Table 241. Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . 1112 Table 242. Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . 1113 Table 243. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . 1113 Table 244. Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . 1119 Table 245. Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 Table 246. Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 Table 247. Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . 1121 Table 248. DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 Table 249. DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134 Table 250. LCD-TFT internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 Table 251. LCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137 Table 252. Clock domain for each register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 DocID029587 Rev 3 73/3178 80 List of tables Table 253. Table 254. Table 255. Table 256. Table 257. Table 258. Table 259. Table 260. Table 261. Table 262. Table 263. Table 264. Table 265. Table 266. Table 267. Table 268. Table 269. Table 270. Table 271. Table 272. Table 273. Table 274. Table 275. Table 276. Table 277. Table 278. Table 279. Table 280. Table 281. Table 282. Table 283. Table 284. Table 285. Table 286. Table 287. Table 288. Table 289. Table 290. Table 291. Table 292. Table 293. Table 294. Table 295. Table 296. Table 297. Table 298. Table 299. Table 300. Table 301. 74/3178 RM0433 LTDC register access and update durations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 Pixel Data mapping versus Color Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142 LTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 LTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 JPEG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 JPEG codec interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 JPEG codec register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183 RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 CRYP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202 Counter mode initialization vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 GCM mode IV registers initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 CCM mode IV registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 DES/TDES data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 AES data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 Key registers CRYP_KxR/LR endianness (TDES K1/2/3 and AES 128/192/256-bit keys) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 Initialization vector registers CRYP_IVxR endianness . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248 Cryptographic processor configuration for peripheral to memory DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 CRYP interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 Processing time (in clock cycle) for ECB, CBC and CTR per 128-bit block . . . . . . . . . . 1252 Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . . . . . . . . . . . 1252 CRYP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266 HASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 Hash processor outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 HASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 HASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 HRTIM Input/output summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 Timer resolution and min. PWM frequency for fHRTIM = 400 MHz . . . . . . . . . . . . . . . . . 1298 Period and Compare registers min and max values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 Timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301 Events mapping across Timer A to E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306 Deadtime resolution and max absolute values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314 External events mapping and associated features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321 Output set/reset latency and jitter vs external event operating mode . . . . . . . . . . . . . . . 1322 Filtering signals mapping per time r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325 Windowing signals mapping per timer (EEFLTR[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . 1327 HRTIM preloadable control registers and associated update sources . . . . . . . . . . . . . . 1336 Update enable inputs and sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337 Master timer update event propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 TIMx update event propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 Reset events able to generate an update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340 Update event propagation for a timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341 Output state programming, x= A..E, y = 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 Timer output programming for burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345 Burst mode clock sources from general purpose timer. . . . . . . . . . . . . . . . . . . . . . . . . . 1347 DocID029587 Rev 3 RM0433 Table 302. Table 303. Table 304. Table 305. Table 306. Table 307. Table 308. Table 309. Table 310. Table 311. Table 312. Table 313. Table 314. Table 315. Table 316. Table 317. Table 318. Table 319. Table 320. Table 321. Table 322. Table 323. Table 324. Table 325. Table 326. Table 327. Table 328. Table 329. Table 330. Table 331. Table 332. Table 333. Table 334. Table 335. Table 336. Table 337. Table 338. Table 339. Table 340. Table 341. Table 342. Table 343. Table 344. Table 345. Table 346. Table 347. Table 348. Table 349. Table 350. Table 351. List of tables Fault inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 Sampling rate and filter length vs FLTFxF[3:0] and clock setting . . . . . . . . . . . . . . . . . . 1356 Effect of sync event vs timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361 HRTIM interrupt summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367 HRTIM DMA request summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 RTIM global register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 HRTIM Register map and reset values: Master timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 HRTIM Register map and reset values: TIMx (x= A..E) . . . . . . . . . . . . . . . . . . . . . . . . . 1460 HRTIM Register map and reset values: Common functions. . . . . . . . . . . . . . . . . . . . . . 1464 Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 Output control bits for complementary OCx and OCxN channels with break feature . . . 1546 TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632 TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 1641 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679 TIM12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690 TIM13/TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736 Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745 TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754 Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765 TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776 TIM6/TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790 STM32H7x3 LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791 LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794 LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794 LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794 LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795 LPTIM3 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795 LPTIM4 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795 LPTIM5 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796 LPTIM1 Input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796 LPTIM1 Input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796 LPTIM2 Input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796 LPTIM2 Input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797 LPTIM3 Input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797 Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798 Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805 Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806 LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817 WWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825 IWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827 DocID029587 Rev 3 75/3178 80 List of tables Table 352. Table 353. Table 354. Table 355. Table 356. Table 357. Table 358. Table 359. Table 360. Table 361. Table 362. Table 363. Table 364. Table 365. Table 366. Table 367. Table 368. Table 369. Table 370. Table 371. Table 372. Table 373. Table 374. Table 375. Table 376. Table 377. Table 378. Table 379. Table 380. Table 381. Table 382. Table 383. Table 384. Table 385. Table 387. Table 388. Table 389. Table 390. Table 391. Table 392. Table 393. Table 394. Table 395. Table 396. Table 397. Table 398. Table 399. Table 400. Table 401. Table 402. 76/3178 RM0433 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838 RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839 RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840 RTC functions over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840 Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879 STM32H7x3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882 Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886 I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889 I2C configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893 I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904 Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914 Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914 Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915 SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917 SMBUS with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919 Examples of TIMEOUTA settings for various i2c_ker_ck frequencies (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920 Examples of TIMEOUTB settings for various i2c_ker_ck frequencies . . . . . . . . . . . . . . 1920 Examples of TIMEOUTA settings for various i2c_ker_ck frequencies (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932 I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949 USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953 Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967 Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1970 Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 1971 USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976 USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999 USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028 Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32,768 KHz . . . . 2043 Error calculation for programmed baud rates at fCK = 100 MHz . . . . . . . . . . . . . . . . . . 2044 Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045 LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056 LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074 STM32H7xx SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076 SPI wakeup and interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105 Bit fields usable in PCM/I2S mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108 WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . . . . . . . . . . . . . . . 2116 Serial data line swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116 CLKGEN programming examples for usual I2S frequencies . . . . . . . . . . . . . . . . . . . . . 2121 I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148 SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153 SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153 External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2155 Clock generator programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163 TDM settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2170 Allowed TDM frame configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2172 DocID029587 Rev 3 RM0433 Table 403. Table 404. Table 405. Table 406. Table 407. Table 408. Table 409. Table 410. Table 411. Table 412. Table 413. Table 414. Table 415. Table 416. Table 417. Table 418. Table 419. Table 420. Table 421. Table 422. Table 423. Table 424. Table 425. Table 426. Table 427. Table 428. Table 429. Table 430. Table 431. Table 432. Table 433. Table 434. Table 435. Table 436. Table 437. Table 438. Table 439. Table 440. Table 441. Table 442. Table 443. Table 444. Table 445. Table 446. Table 447. Table 448. Table 449. Table 450. Table 451. Table 452. Table 453. Table 454. List of tables SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176 Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176 Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2177 SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2185 SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2202 SPDIFRX internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205 SPDIFRX pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205 Transition sequence for preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211 Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . . . . . . . . . . . . . . . 2221 Conditions of spdifrx_symb_ck generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2223 Bit field property versus SPDIFRX state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225 SPDIFRX interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242 SWPMI input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . 2245 SWPMI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246 Effect of low-power modes on SWPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261 Buffer modes selection for transmission/reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263 SWPMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2270 MDIOS input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . 2272 MDIOS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278 MDIOS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285 SDMMC operation modes SD & SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289 SDMMC operation modes eMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290 SDMMC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291 SDMMC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291 SDMMC Command and data phase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2293 Command token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299 Short response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300 Short response without CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300 Long response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300 Specific Commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2301 Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2302 Command path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2302 Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310 Data path status flags and clear bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310 Data path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2312 Data FIFO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313 Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2314 Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315 SDMMC connections to MDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318 AHB and SDMMC_CK clock frequency relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318 SDIO special operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2319 4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . . . . . . . . . . . . . . . 2323 CMD12 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327 Response type and SDMMC_RESPxR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2348 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365 CAN subsystem I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2368 CAN subsystem I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369 DLC coding in FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2375 Example of filter configuration for Rx Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2388 Example of filter configuration for Debug messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389 DocID029587 Rev 3 77/3178 80 List of tables Table 455. Table 456. Table 457. Table 458. Table 459. Table 460. Table 461. Table 462. Table 463. Table 464. Table 465. Table 466. Table 467. Table 468. Table 469. Table 470. Table 471. Table 472. Table 473. Table 474. Table 475. Table 476. Table 477. Table 478. Table 479. Table 480. Table 481. Table 482. Table 483. Table 484. Table 485. Table 486. Table 487. Table 488. Table 489. Table 490. Table 491. Table 492. Table 493. Table 494. Table 495. Table 496. Table 497. Table 498. Table 499. Table 500. Table 501. Table 502. Table 503. Table 504. Table 505. Table 506. 78/3178 RM0433 Possible configurations for Frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389 Tx Buffer/FIFO - Queue element size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2390 First byte of Level 1 reference message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2399 First four bytes of Level 2 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2399 First four bytes of Level 0 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 TUR configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2401 System matrix, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2406 Trigger list, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2406 Number of data bytes transmitted with a Reference Message . . . . . . . . . . . . . . . . . . . . 2414 Rx Buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421 Rx Buffer and FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421 Tx Buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423 Tx Buffer element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423 Tx Event FIFO element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425 Tx Event FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425 Standard Message ID Filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426 Standard Message ID Filter element Field description . . . . . . . . . . . . . . . . . . . . . . . . . . 2427 Extended Message ID Filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428 Extended Message ID Filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . 2428 Trigger Memory element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429 Trigger Memory element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2430 FDCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2490 CCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2501 OTG_HS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503 OTG Implementation for STM32H7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506 OTG_FS/OTG_HS input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2508 OTG_FS/OTG_HS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2508 Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2527 Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2528 Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2529 Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2531 Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2531 TRDT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2540 TRDT values (HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2540 Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2578 OTG_HS register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2601 Ethernet peripheral pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2674 Ethernet internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2675 Double VLAN processing features in Tx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2689 Double VLAN processing in Rx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2690 VLAN insertion or replacement based on VLTI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2691 Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2695 Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2696 VLAN match status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697 Ordinary clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2702 End-to-end transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . 2703 Peer-to-peer transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . 2703 PTP message generation criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2710 TSO: TCP and IP header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2714 Pause packet fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2716 Tx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2717 Rx MAC Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2718 DocID029587 Rev 3 RM0433 Table 507. Table 508. Table 509. Table 510. Table 511. Table 512. Table 513. Table 514. Table 515. Table 516. Table 517. Table 518. Table 519. Table 520. Table 521. Table 522. Table 523. Table 524. Table 525. Table 526. Table 527. Table 528. Table 529. Table 530. Table 531. Table 532. Table 533. Table 534. Table 535. Table 536. Table 537. Table 538. Table 539. Table 540. Table 541. Table 542. Table 543. Table 544. Table 545. Table 546. Table 547. Table 548. Table 549. Table 550. Table 551. Table 552. Table 553. Table 554. Table 555. Table 556. Table 557. Table 558. List of tables Transmit checksum offload engine functions for different packet types . . . . . . . . . . . . . 2720 Receive checksum offload engine functions for different packet types . . . . . . . . . . . . . 2721 MCD clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2725 MDIO packet field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2726 RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2729 Transfer complete interrupt behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2737 TDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750 TDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2751 TDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2751 TDES3 normal descriptor (Read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2752 DES0 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755 TDES1 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755 TDES2 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755 TDES3 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2756 TDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759 TDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759 TDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2760 TDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2760 RDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2763 RDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2763 RDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2763 RDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2764 RDES0 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2765 RDES1 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2766 RDES2 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2768 RDES3 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2769 RDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772 RDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2773 RDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2773 RDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2773 ETH_DMA common register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2798 ETH_DMA_CH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2798 ETH_MTL register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2812 Giant Packet Status based on S2KP and JE Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2819 Packet Length based on the CST and ACS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2820 Remote Wakeup packet filter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2843 ETH_MACRWKPFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2845 Remote Wakeup Packet and PMT Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . 2846 Timestamp Snapshot Dependency on Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2886 Ethernet MAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2906 HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916 HDMI-CEC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916 Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2923 TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2924 HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2925 HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2934 JTAG/Serial-wire debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937 Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937 Serial-wire trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937 Trigger pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937 Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2941 ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2941 DocID029587 Rev 3 79/3178 80 List of tables Table 559. Table 560. Table 561. Table 562. Table 563. Table 564. Table 565. Table 566. Table 567. Table 568. Table 569. Table 570. Table 571. Table 572. Table 573. Table 574. Table 575. Table 576. Table 577. Table 578. Table 579. Table 580. Table 581. Table 582. Table 583. Table 584. Table 585. Table 586. Table 587. 80/3178 RM0433 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2941 JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2944 Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2946 MEM-AP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2956 System ROM table 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960 System ROM table 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2961 System ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2967 TSG CoreSight Peripheral identity register 0 (TSG_PIDR0) . . . . . . . . . . . . . . . . . . . . . 2971 TSG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2975 System CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977 System CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977 Cortex-M7 CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977 Cortex-M7 CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2978 CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2993 CSTF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3004 ETF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3025 TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3044 SWO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056 SWTF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3067 DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3076 Cortex-M7 CPU ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3077 Cortex-M7 PPB ROM table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3077 Cortex-M7 CPU ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . 3083 Cortex-M7 PPB ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . 3088 Cortex-M7 DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3101 Cortex-M7 ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110 Cortex-M7 FPB register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3117 Cortex-M7 ETM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3155 DocID029587 Rev 3 RM0433 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. System architecture for STM32H7x3 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Flash memory block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Burst read timing diagram - 4x64bits, latency = 3 ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Burst read timing diagram - 8x64bits, latency = 3 ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Protection transition scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Flash memory areas and services in Standard and Secure access modes . . . . . . . . . . . 189 Secure bootloader state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Root secure service call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Core access to Flash memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 AXI interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Power control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 System supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Device startup with VCORE supplied from voltage regulator . . . . . . . . . . . . . . . . . . . . . . 224 Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 VBAT thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 VCORE voltage scaling versus system power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Power control modes detailed state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Dynamic voltage scaling in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Dynamic voltage scaling behavior with D1, D2 and system in Stop mode . . . . . . . . . . . . 246 Dynamic Voltage Scaling D1, D2, system Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 247 Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and D3 in autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 EXTI, RCC and PWR interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Timing diagram of LPUART1 transmission with D3 domain in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 RCC Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Boot sequences versus system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Top-level clock tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 HSE/LSE clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 PLLs Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Core and bus clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Kernel clock distribution for SAIs and DFSDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Kernel clock distribution for SPIs and SPI/I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Kernel clock distribution for I2Cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Kernel clock distribution for UARTs, USARTs and LPUART1 . . . . . . . . . . . . . . . . . . . . . 316 Kernel clock distribution for LTDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 DocID029587 Rev 3 81/3178 97 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. 82/3178 RM0433 Kernel clock distribution for SDMMC, QUADSPI and FMC . . . . . . . . . . . . . . . . . . . . . . . 317 Kernel clock distribution for USB (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Kernel clock distribution for Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Kernel clock distribution For ADCs, SWPMI, RNG and FDCAN (2) . . . . . . . . . . . . . . . . . 320 Kernel clock distribution for LPTIMs and HDMI-CEC (2) . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Peripheral allocation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Kernel Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Peripheral kernel clock enable logic details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Bus clock enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 RCC mapping overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Interrupt state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Analog inputs connected to ADC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 MDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 BDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 644 Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 644 DMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 Configurable event triggering logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 Configurable event triggering logic Any wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Direct event triggering logic CPU Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 Direct event triggering logic Any Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 D3 domain Pending request clear logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 DocID029587 Rev 3 RM0433 List of figures Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. Figure 141. Figure 142. Figure 143. Figure 144. Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 774 Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 776 NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 790 Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 Burst write SDRAM access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 Burst read SDRAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . . . . . . . . . 803 Read access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 Write access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 Self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 820 QUADSPI block diagram when dual-flash mode is enabled. . . . . . . . . . . . . . . . . . . . . . . 820 An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 834 nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 834 nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 834 DLYB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Updating the ADC offset calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 Triggers are shared between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . 880 Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 886 Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 887 Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 888 Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 888 Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 889 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 889 Figure 145. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 Figure 146. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). DocID029587 Rev 3 83/3178 97 List of figures Figure 147. Figure 148. Figure 149. Figure 150. Figure 151. Figure 152. Figure 153. Figure 154. Figure 155. Figure 156. Figure 157. Figure 158. Figure 159. Figure 160. Figure 161. Figure 162. Figure 163. Figure 164. Figure 165. Figure 166. Figure 167. Figure 168. Figure 169. Figure 170. Figure 171. Figure 172. Figure 173. Figure 174. Figure 175. Figure 176. Figure 177. Figure 178. Figure 179. Figure 180. Figure 181. Figure 182. Figure 183. Figure 184. Figure 185. Figure 186. Figure 187. Figure 188. Figure 189. Figure 190. Figure 191. Figure 192. Figure 193. 84/3178 RM0433 Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 890 Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 891 Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 891 Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 892 Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 894 Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 895 Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 Right alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 904 AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . . (DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 906 AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907 ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 909 ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . . 909 ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 910 ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 910 16-bit result oversampling with 10-bits right shift and rouding . . . . . . . . . . . . . . . . . . . . . 911 Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 913 Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 914 Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 919 Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 921 Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . . 923 Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . . . . . . 923 Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 926 Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 928 Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . . . . . . . . . . . . . 929 DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . . . . . . . . . . . . . . 930 DMA requests in interleaved mode when DAMDF=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . 931 Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 DocID029587 Rev 3 RM0433 Figure 194. Figure 195. Figure 196. Figure 197. Figure 198. Figure 199. Figure 200. Figure 201. Figure 202. Figure 203. Figure 204. Figure 205. Figure 206. Figure 207. Figure 208. Figure 209. Figure 210. Figure 211. Figure 212. Figure 213. Figure 214. Figure 215. Figure 216. Figure 217. Figure 218. Figure 219. Figure 220. Figure 221. Figure 222. Figure 223. Figure 224. Figure 225. Figure 226. Figure 227. Figure 228. Figure 229. Figure 230. Figure 231. Figure 232. Figure 233. Figure 234. Figure 235. Figure 236. Figure 237. Figure 238. Figure 239. Figure 240. Figure 241. Figure 242. List of figures DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 984 DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 987 DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 988 DAC Sample and Hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 Comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 Scaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . 1038 PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain setting (x-1/x-3/x-7/x-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain setting (x-1/x-3/x-7/x-15) with filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062 Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . 1063 First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . 1065 DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . 1069 Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 Top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114 Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116 Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 Data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118 Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 LCD-TFT synchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139 Layer window programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142 Blending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 JPEG codec block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187 Random samples conditioning process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189 RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 DocID029587 Rev 3 85/3178 97 List of figures Figure 243. Figure 244. Figure 245. Figure 246. Figure 247. Figure 248. Figure 249. Figure 250. Figure 251. Figure 252. Figure 253. Figure 254. Figure 255. Figure 256. Figure 257. Figure 258. Figure 259. Figure 260. Figure 261. Figure 262. Figure 263. Figure 264. Figure 265. Figure 266. Figure 267. Figure 268. Figure 269. Figure 270. Figure 271. Figure 272. Figure 273. Figure 274. Figure 275. Figure 276. Figure 277. Figure 278. Figure 279. Figure 280. Figure 281. Figure 282. Figure 283. Figure 284. Figure 285. Figure 286. Figure 287. Figure 288. Figure 289. Figure 290. Figure 291. Figure 292. Figure 293. Figure 294. 86/3178 RM0433 CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 AES-ECB mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204 AES-CBC mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205 AES-CTR mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206 AES-GCM mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207 AES-GMAC mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207 AES-CCM mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 STM32 cryptolib DES/TDES flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209 STM32 cryptolib AES flowchart examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 DES/TDES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216 DES/TDES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 DES/TDES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218 DES/TDES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 AES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 AES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 AES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 AES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 Message construction for the Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 AES-CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 AES-CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 Message construction for the Galois/Counter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230 Message construction for the Galois Message Authentication Code mode . . . . . . . . . . 1235 Message construction for the Counter with CBC-MAC mode. . . . . . . . . . . . . . . . . . . . . 1236 64-bit block construction according to the data type (IN FIFO). . . . . . . . . . . . . . . . . . . . 1243 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 CRYP interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272 HASH save/restore mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277 HASH interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 High-resolution timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295 Timer A..E overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 Continuous timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301 Single-shot timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302 Timer reset resynchronization (prescaling ratio above 32) . . . . . . . . . . . . . . . . . . . . . . . 1303 Repetition rate vs HRTIM_REPxR content in continuous mode. . . . . . . . . . . . . . . . . . . 1304 Repetition counter behavior in single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 Compare events action on outputs: set on compare 1, reset on compare 2 . . . . . . . . . 1306 Timing unit capture circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 Auto-delayed overview (Compare 2 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 Auto-delayed compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Push-pull mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312 Push-pull mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 Complementary outputs with deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 Deadtime insertion vs deadtime sign (1 indicates negative deadtime) . . . . . . . . . . . . . . 1314 Complementary outputs for low pulse width (SDTRx = SDTFx = 0). . . . . . . . . . . . . . . . 1315 Complementary outputs for low pulse width (SDTRx = SDTFx = 1). . . . . . . . . . . . . . . . 1315 Complementary outputs for low pulse width (SDTRx = 0, SDTFx = 1). . . . . . . . . . . . . . 1315 Complementary outputs for low pulse width (SDTRx = 1, SDTFx=0). . . . . . . . . . . . . . . 1316 Master timer overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317 External event conditioning overview (1 channel represented) . . . . . . . . . . . . . . . . . . . 1320 DocID029587 Rev 3 RM0433 Figure 295. Figure 296. Figure 297. Figure 298. Figure 299. Figure 300. Figure 301. Figure 302. Figure 303. Figure 304. Figure 305. Figure 306. Figure 307. Figure 308. Figure 309. Figure 310. Figure 311. Figure 312. Figure 313. Figure 314. Figure 315. Figure 316. Figure 317. Figure 318. Figure 319. Figure 320. Figure 321. Figure 322. Figure 323. Figure 324. Figure 325. Figure 326. Figure 327. Figure 328. Figure 329. Figure 330. Figure 331. Figure 332. Figure 333. Figure 334. Figure 335. Figure 336. Figure 337. Figure 338. Figure 339. Figure 340. Figure 341. Figure 342. Figure 343. Figure 344. Figure 345. Figure 346. List of figures Latency to external events falling edge (counter reset and output set) . . . . . . . . . . . . 1323 Latency to external events (output reset on external event) . . . . . . . . . . . . . . . . . . . . . . 1323 Event blanking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324 Event postpone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324 External trigger blanking with edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 External trigger blanking, level sensitive triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 Event windowing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327 External trigger windowing with edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 1328 External trigger windowing, level sensitive triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328 Delayed Idle mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 Burst mode and delayed protection priorities (DIDL = 0) . . . . . . . . . . . . . . . . . . . . . . . . 1331 Burst mode and delayed protection priorities (DIDL = 1) . . . . . . . . . . . . . . . . . . . . . . . . 1332 Balanced Idle protection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333 Output management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343 HRTIM output states and transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343 Burst mode operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345 Burst mode trigger on external event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 Delayed burst mode entry with deadtime enabled and IDLESx = 1 . . . . . . . . . . . . . . . . 1349 Delayed Burst mode entry during deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350 Burst mode exit when the deadtime generator is enabled . . . . . . . . . . . . . . . . . . . . . . . 1351 Burst mode emulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 Carrier frequency signal insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 HRTIM outputs with Chopper mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 Fault protection circuitry (FAULT1 fully represented, FAULT2..5 partially). . . . . . . . . . . 1355 Fault signal filtering (FLTxF[3:0]= 0010: fSAMPLING = fHRTIM, N = 4) . . . . . . . . . . . . . . 1356 Auxiliary outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358 Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . . . . . . . . . . . . . . . . . . . 1359 Deadtime distortion on auxiliary output when exiting burst mode. . . . . . . . . . . . . . . . . . 1359 Counter behavior in synchronized start mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363 ADC trigger selection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 Combining several updates on a single hrtim_dac_trgx output . . . . . . . . . . . . . . . . . . . 1365 DMA burst overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369 Burst DMA operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 Registers update following DMA burst transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 Buck converter topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 Dual Buck converter management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374 Synchronous rectification depending on output current . . . . . . . . . . . . . . . . . . . . . . . . . 1374 Buck with synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 3-phase interleaved buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376 3-phase interleaved buck converter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377 Transition mode PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377 Transition mode PFC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378 Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1470 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1470 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . 1474 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . 1474 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476 DocID029587 Rev 3 87/3178 97 List of figures Figure 347. Figure 348. Figure 349. Figure 350. Figure 351. Figure 352. Figure 353. Figure 354. Figure 355. Figure 356. Figure 357. Figure 358. Figure 359. Figure 360. Figure 361. Figure 362. Figure 363. Figure 364. Figure 365. Figure 366. Figure 367. Figure 368. Figure 369. Figure 370. Figure 371. Figure 372. Figure 373. Figure 374. Figure 375. Figure 376. Figure 377. Figure 378. Figure 379. Figure 380. Figure 381. Figure 382. Figure 383. Figure 384. Figure 385. Figure 386. Figure 387. Figure 388. Figure 389. Figure 390. Figure 391. Figure 392. Figure 393. Figure 394. Figure 395. Figure 396. Figure 397. Figure 398. 88/3178 RM0433 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1478 Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1479 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1480 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1481 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1482 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1483 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484 TIM1/TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1485 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1489 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490 Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . 1490 Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . 1491 Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 1491 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497 Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1499 Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 1501 Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502 Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 1502 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1503 Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505 Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . 1507 PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . 1508 PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514 Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 1515 Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . 1516 Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517 Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1523 General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1575 DocID029587 Rev 3 RM0433 Figure 399. Figure 400. Figure 401. Figure 402. Figure 403. Figure 404. Figure 405. Figure 406. Figure 407. Figure 408. Figure 409. Figure 410. Figure 411. Figure 412. Figure 413. Figure 414. Figure 415. Figure 416. Figure 417. Figure 418. Figure 419. Figure 420. Figure 421. Figure 422. Figure 423. Figure 424. Figure 425. Figure 426. Figure 427. Figure 428. Figure 429. Figure 430. Figure 431. Figure 432. Figure 433. Figure 434. Figure 435. Figure 436. Figure 437. Figure 438. Figure 439. Figure 440. Figure 441. Figure 442. Figure 443. Figure 444. Figure 445. Figure 446. Figure 447. Figure 448. Figure 449. List of figures Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1575 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578 Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 1578 Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 1579 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581 Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582 Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 1583 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1584 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585 Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . 1585 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1586 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1587 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1590 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1591 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598 Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1599 Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601 Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604 Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 1605 Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . 1606 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1610 Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610 Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611 Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612 Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614 General-purpose timer block diagram (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645 General-purpose timer block diagram (TIM13/TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1648 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1648 DocID029587 Rev 3 89/3178 97 List of figures Figure 450. Figure 451. Figure 452. Figure 453. Figure 454. Figure 455. Figure 456. Figure 457. Figure 458. Figure 459. Figure 460. Figure 461. Figure 462. Figure 463. Figure 464. Figure 465. Figure 466. Figure 467. Figure 468. Figure 469. Figure 470. Figure 471. Figure 472. Figure 473. Figure 474. Figure 475. Figure 476. Figure 477. Figure 478. Figure 479. Figure 480. Figure 481. Figure 482. Figure 483. Figure 484. Figure 485. Figure 486. Figure 487. Figure 488. Figure 489. Figure 490. Figure 491. Figure 492. Figure 493. Figure 494. Figure 495. Figure 496. Figure 497. 90/3178 RM0433 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1653 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 Capture/compare channel (example: channel 1 input stage . . . . . . . . . . . . . . . . . . . . . 1655 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1656 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658 Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661 Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664 Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668 TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697 TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1700 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1700 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1706 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1707 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1709 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1710 Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 1710 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715 Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716 Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717 Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 1718 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1718 Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720 DocID029587 Rev 3 RM0433 Figure 498. Figure 499. Figure 500. Figure 501. Figure 502. Figure 503. Figure 504. Figure 505. Figure 506. Figure 507. Figure 508. Figure 509. Figure 510. Figure 511. Figure 512. Figure 513. Figure 514. Figure 515. Figure 516. Figure 517. Figure 518. Figure 519. Figure 520. Figure 521. Figure 522. Figure 523. Figure 524. Figure 525. Figure 526. Figure 527. Figure 528. Figure 529. Figure 530. Figure 531. Figure 532. Figure 533. Figure 534. Figure 535. Figure 536. Figure 537. Figure 538. Figure 539. Figure 540. Figure 541. Figure 542. Figure 543. Figure 544. Figure 545. Figure 546. List of figures Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725 Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729 Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1780 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1780 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783 Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1785 Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . 1792 Low-power timer block diagram (LPTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1793 Low-power timer block diagram (LPTIM4 and LPTIM5) . . . . . . . . . . . . . . . . . . . . . . . . . 1793 Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798 LPTIM output waveform, Single counting mode configuration . . . . . . . . . . . . . . . . . . . . 1799 LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800 LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1800 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802 Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822 Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826 RTC block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836 Detailed RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885 Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887 I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890 Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1892 Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . 1897 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . 1898 Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899 Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . 1900 Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . 1901 Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901 Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903 Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906 DocID029587 Rev 3 91/3178 97 List of figures Figure 547. Figure 548. Figure 549. Figure 550. Figure 551. Figure 552. Figure 553. Figure 554. Figure 555. Figure 556. Figure 557. Figure 558. Figure 559. Figure 560. Figure 561. Figure 562. Figure 563. Figure 564. Figure 565. Figure 566. Figure 567. Figure 568. Figure 569. Figure 570. Figure 571. Figure 572. Figure 573. Figure 574. Figure 575. Figure 576. Figure 577. Figure 578. Figure 579. Figure 580. Figure 581. Figure 582. Figure 583. Figure 584. Figure 585. Figure 586. Figure 587. Figure 588. Figure 589. Figure 590. Figure 591. Figure 592. Figure 593. Figure 594. 92/3178 RM0433 Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . 1907 Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . 1908 Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909 Transfer sequence flowchart for I2C master receiver for N≤255 bytes. . . . . . . . . . . . . . 1911 Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . 1912 Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913 Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918 Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . 1922 Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . 1922 Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . 1924 Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . 1925 Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926 Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928 I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961 Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962 usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965 Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967 Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975 Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1978 Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1979 USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 1980 USART data clock timing diagram in synchronous master mode (M bits =’00’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980 USART data clock timing diagram in synchronous master mode (M bits = ‘01’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981 USART data clock timing diagram in synchronous slave mode (M bits =’00’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982 ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984 Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1986 IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990 IrDA data modulation (3/16) - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993 Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1995 Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . 1998 Wakeup event not verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1998 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2032 LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2034 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038 lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047 DocID029587 Rev 3 RM0433 Figure 595. Figure 596. Figure 597. Figure 598. Figure 599. Figure 600. Figure 601. Figure 602. Figure 603. Figure 604. Figure 605. Figure 606. Figure 607. Figure 608. Figure 609. Figure 610. Figure 611. Figure 612. Figure 613. Figure 614. Figure 615. Figure 616. Figure 617. Figure 618. Figure 619. Figure 620. Figure 621. Figure 622. Figure 623. Figure 624. Figure 625. Figure 626. Figure 627. Figure 628. Figure 629. Figure 630. Figure 631. Figure 632. Figure 633. Figure 634. Figure 635. Figure 636. Figure 637. Figure 638. Figure 639. Figure 640. Figure 641. Figure 642. Figure 643. List of figures Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2049 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2050 Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2052 Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055 Wakeup event not verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055 SPI2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2077 Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079 Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079 Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2080 Master and three independent slaves at star topology . . . . . . . . . . . . . . . . . . . . . . . . . . 2081 Master and three slaves at circular (daisy chain) topology . . . . . . . . . . . . . . . . . . . . . . . 2083 Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2084 Scheme of SS control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086 Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . . . . . . . . . . . . . . . . . . . . . . 2086 SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). . . . . . . . . . . . . . . . 2087 Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089 Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . . . . . . . . . . . . 2090 Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097 TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099 Low-power mode application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104 Waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110 Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . . . . . . . . . . . . . . . 2111 I2S Philips standard waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111 Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . 2112 Master MSB justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2112 Slave MSB justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113 LSB justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113 Master PCM when the frame length is equal the data length . . . . . . . . . . . . . . . . . . . . . 2114 Master PCM standard waveforms (16 or 24-bit data length) . . . . . . . . . . . . . . . . . . . . . 2114 Slave PCM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2115 Start-up sequence, I2S Philips standard, master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117 Start-up sequence, I2S Philips standard, slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2118 Stop sequence, I2S Philips standard, master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2119 I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2119 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2122 Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123 Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124 Frame error detection, with FIXCH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2125 Frame error detection, with FIXCH=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2125 SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152 Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156 FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 2158 FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159 Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 2160 First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2160 Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2161 PDM typical connection and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2165 DocID029587 Rev 3 93/3178 97 List of figures Figure 644. Figure 645. Figure 646. Figure 647. Figure 648. Figure 649. Figure 650. Figure 651. Figure 652. Figure 653. Figure 654. Figure 655. Figure 656. Figure 657. Figure 658. Figure 659. Figure 660. Figure 661. Figure 662. Figure 663. Figure 664. Figure 665. Figure 666. Figure 667. Figure 668. Figure 669. Figure 670. Figure 671. Figure 672. Figure 673. Figure 674. Figure 675. Figure 676. Figure 677. Figure 678. Figure 679. Figure 680. Figure 681. Figure 682. Figure 683. Figure 684. Figure 685. Figure 686. Figure 687. Figure 688. Figure 689. Figure 690. Figure 691. Figure 692. Figure 693. Figure 694. 94/3178 RM0433 Detailed PDM interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2166 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167 SAI_ADR format in TDM, 32-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168 SAI_ADR format in TDM, 16-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169 SAI_ADR format in TDM, 8-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2170 AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173 Example of typical AC’97 configuration on devices featuring at least 2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2174 SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2175 SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176 Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 2179 Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 2180 Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2181 Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2182 FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2182 SPDIFRX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205 S/PDIF Sub-Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206 S/PDIF block format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206 S/PDIF Preambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2207 Channel coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2208 SPDIFRX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209 Noise filtering and edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209 Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211 Synchronization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213 Synchronization process scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214 SPDIFRX States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2215 SPDIFRX_DR register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217 Channel/user data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2218 S/PDIF overrun error when RXSTEO = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220 S/PDIF overrun error when RXSTEO = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2221 SPDIFRX interface interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2224 S1 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243 S2 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243 SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248 SWP frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2249 SWPMI No software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250 SWPMI No software buffer mode transmission, consecutive frames . . . . . . . . . . . . . . . 2251 SWPMI Multi software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253 SWPMI No software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2255 SWPMI single software buffer mode reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2256 SWPMI Multi software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258 SWPMI single buffer mode reception with CRC error. . . . . . . . . . . . . . . . . . . . . . . . . . . 2259 MDIOS block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272 MDIO protocol write frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273 MDIO protocol read frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2273 SDMMC “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288 SDMMC (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288 SDMMC (multiple) block write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288 SDMMC (sequential) stream read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289 SDMMC (sequential) stream write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291 DocID029587 Rev 3 RM0433 Figure 695. Figure 696. Figure 697. Figure 698. Figure 699. Figure 700. Figure 701. Figure 702. Figure 703. Figure 704. Figure 705. Figure 706. Figure 707. Figure 708. Figure 709. Figure 710. Figure 711. Figure 712. Figure 713. Figure 714. Figure 715. Figure 716. Figure 717. Figure 718. Figure 719. Figure 720. Figure 721. Figure 722. Figure 723. Figure 724. Figure 725. Figure 726. Figure 727. Figure 728. Figure 729. Figure 730. Figure 731. Figure 732. Figure 733. Figure 734. Figure 735. Figure 736. Figure 737. Figure 738. Figure 739. Figure 740. Figure 741. Figure 742. Figure 743. Figure 744. Figure 745. Figure 746. List of figures SDMMC Command and data phase relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2293 Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2295 Command/Response path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2296 Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297 Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303 DDR mode data packet clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2304 DDR mode CRC status / boot acknowledgment clocking. . . . . . . . . . . . . . . . . . . . . . . . 2304 Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305 CLKMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315 Asynchronous interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2320 Synchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2320 Synchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2321 Asynchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322 Asynchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322 Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . . . . . . . . . . . . . . . . . . . . 2325 Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 . . . . . . . . . . . . . . . . . . . . . . 2325 ReadWait with SDMMC_CK < 50 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326 ReadWait with SDMMC_CK > 50 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327 CMD12 stream timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2329 CMD5 Sleep Awake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2331 Normal boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333 Alternative boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2334 Command response R1b busy signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335 SDMMC state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2336 Card cycle power / power up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2337 Hardware flow timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2338 CMD11 signal voltage switch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2338 Voltage switch transceiver typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2340 CAN subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2370 FDCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2372 Transceiver delay measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2377 Pin control in Bus Monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2378 Pin control in Loop Back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2381 Message RAM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2382 Standard Message ID filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2385 Extended Message ID filter path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386 Example of mixed Configuration Dedicated Tx Buffers / Tx FIFO . . . . . . . . . . . . . . . . . 2392 Example of mixed Configuration Dedicated Tx Buffers / Tx Queue . . . . . . . . . . . . . . . . 2392 Bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2394 FSM calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2396 Cycle Time and Global Time synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411 TTCAN Level 0 and Level 2 drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2412 Level 0 schedule synchronization state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2419 Level 0 master to slave relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2420 OTG high-speed block diagram (OTG_HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2507 OTG high-speed block diagram (OTG_HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2507 SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 2519 Updating OTG_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2521 Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 2522 Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 2523 Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2526 Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2614 DocID029587 Rev 3 95/3178 97 List of figures Figure 747. Figure 748. Figure 749. Figure 750. Figure 751. Figure 752. Figure 753. Figure 754. Figure 755. Figure 756. Figure 757. Figure 758. Figure 759. Figure 760. Figure 761. Figure 762. Figure 763. Figure 764. Figure 765. Figure 766. Figure 767. Figure 768. Figure 769. Figure 770. Figure 771. Figure 772. Figure 773. Figure 774. Figure 775. Figure 776. Figure 777. Figure 778. Figure 779. Figure 780. Figure 781. Figure 782. Figure 783. Figure 784. Figure 785. Figure 786. Figure 787. Figure 788. Figure 789. Figure 790. Figure 791. Figure 792. Figure 793. Figure 794. Figure 795. Figure 796. Figure 797. 96/3178 RM0433 Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2615 Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616 Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2620 Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623 Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628 Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2630 Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633 Normal bulk/control OUT/SETUP transactions - DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 2635 Normal bulk/control IN transaction - DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2637 Normal interrupt OUT transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2638 Normal interrupt IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2639 Normal isochronous OUT transaction - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2640 Normal isochronous IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2641 Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2647 Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649 Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2655 TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2663 A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2664 B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2665 A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2666 B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2668 Ethernet high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2676 DMA transmission flow (standard mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2679 DMA transmission flow (OSP mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2681 Receive DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2683 Overview of MAC transmission flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686 MAC reception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2688 Packet filtering sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693 Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2700 Propagation delay calculation in clocks supporting peer-to-peer path correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2701 System time update using Fine method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2706 TCP segmentation offload overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712 Header and payload fields of segmented packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2715 Supported PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2724 SMA Interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2725 MDIO packet structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2725 Write data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2726 Read data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727 Media independent interface (MII) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2728 RMII block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2730 Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2730 Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731 Descriptor ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748 DMA descriptor ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2749 Transmit descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750 Transmit descriptor write-back format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2754 Transmit context descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759 Receive normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2762 Receive normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2765 Receive context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772 Generation of ETH_DMAISR flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2791 DocID029587 Rev 3 RM0433 Figure 798. Figure 799. Figure 800. Figure 801. Figure 802. Figure 803. Figure 804. Figure 805. Figure 806. Figure 807. Figure 808. Figure 809. Figure 810. Figure 811. Figure 812. Figure 813. Figure 814. Figure 815. Figure 816. Figure 817. Figure 818. Figure 819. List of figures HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2917 Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2918 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2918 Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919 Signal free time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919 Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920 SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920 Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2923 TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2924 Block diagram of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936 Power domains of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2938 Clock domains of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2939 SWD successful data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2942 JTAG TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2943 Debug and access port connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2954 APB-D CoreSight component topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2962 Global timestamp distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2968 Embedded cross trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976 Mapping of trigger inputs to outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2978 ETF state transition diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3007 Cortex-M7 CoreSight Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3078 DocID029587 Rev 3 97/3178 97 Documentation conventions RM0433 1 Documentation conventions 1.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit. Reading this bit returns the reset value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value. read/clear by read Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit (rc_r) has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit value. Reserved (Res.) Reserved bit, must be kept at reset value. 1.2 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: 1.3 • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • Double word: data of 64-bit length. • Flash word: data of 256-bit length • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. • ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board. • Option bytes: product configuration bits stored in the Flash memory. • AHB: advanced high-performance bus. • AXI: Advanced extensible Interface protocol • PCROP: proprietary code readout protection. • RDP: readout protection Peripheral availability For peripheral availability and number across all sales types, refer to the particular device datasheet. 98/3178 DocID029587 Rev 3 RM0433 Memory and bus architecture 2 Memory and bus architecture 2.1 System architecture An AXI bus matrix, two AHB bus matrices and bus bridges allow interconnecting bus masters with bus slaves, as illustrated in Table 1 and Figure 1. Table 1. Bus-master-to-bus-slave interconnect SDMMC2 - AHB USBHS1 - AHB USBHS2 - AHB BDMA - AHB - 7 - - - - - - - - - - - - - DTCM - - - D - - 7 - - - - - - - - - - - - - AHB3 peripherals 1 - - - - 1 - - - 21 21 - 21 21 - 21 21 21 21 - APB3 peripherals 14 - - - - 14 - - - 214 214 - 214 214 - 214 214 214 214 - Flash A 1 - - - 1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 - Flash B 1 - - - 1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 - AXI SRAM 1 - - - 1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 - QUADSPI 1 - - - 1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 - FMC 1 - - - 1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 - SRAM 1 12 - - - - 12 - 12 - 2 2 - 2 2 - 2 2 2 2 - SRAM 2 12 - - - - 12 - 12 - 2 2 - 2 2 - 2 2 2 2 - SRAM 3 12 - - - - 12 - 12 - 2 2 - 2 2 - 2 2 2 2 - AHB1 peripherals 12 2 - - - 12 - 12 - 2 2 - 2 2 - - - - - - APB1 peripherals 125 25 - - - 125 - 125 - 25 25 2 25 25 2 - - - - - AHB2 peripherals - 2 - - - - - - - 2 2 - 2 2 - - - - - - APB2 peripherals 125 25 - - - 125 - 125 - 25 25 2 25 25 2 - - - - AHB4 peripherals 13 - - - - 13 - - - 23 23 - 23 23 APB4 peripherals 136 - - - - 136 - - - 236 236 - 236 236 SRAM4 13 - - - - 13 - - - 23 23 - 23 Backup RAM 13 - - - - 13 - - - 23 23 - 23 DMA2 - MEM - DMA1 - MEM - LTDC D Bus slave / type(1) DMA2D - MDMA - AHBS - MDMA - AXI ITCM SDMMC1 Eth. MAC - AHB DMA2 - PERIPH DMA1 - PERIPH Cortex-M7 -DTCM Cortex-M7 - ITCM Cortex-M7 - AHBP Cortex-M7 - AXIM Bus master / type(1) Interconnect path and type(2) - - 213 213 213 213 3 - 213 213 213 213 36 23 - 213 213 213 213 3 23 - 213 213 213 213 3 1. Bold font type denotes 64-bit bus, plain type denotes 32-bit bus. 2. Cells in the table body indicate access possibility, utility, path and type: Access possibility and utility: Any figure = access possible, “-” = access not possible, shading = access useful/usable Access path: D=direct, 1=via AXI bus matrix, 2=via AHB bus matrix in D2, 3=via AHB bus matrix in D3, 4=via AHB/APB bridge in D1, 5=via AHB/APB bridge in D2, 6=via AHB/APB bridge in D3, 7=via AHBS bus of Cortex-M7, Multi-digit numbers = interconnect path goes through more than one matrix or/and bridge, in the order of the digits. Access type: Plain=32-bit, Italic=32-bit on bus master end / 64-bit on bus slave end, Bold=64-bit DocID029587 Rev 3 99/3178 104 $+%6 &38 ,7&0 .E\WH 0'0$ '0$' /7'& 'WR'$+% '0$ '0$B0(0 6'00& '0$B0(0 $+%3 '0$ (WKHUQHW 6'00& 86%+6 0$& 86%+6 '0$B3(5,3+ '7&0 .E\WH '0$B3(5,3+ &RUWH[0 , ' .% .% $;,0 RM0433 Figure 1. System architecture for STM32H7x3 devices 65$0 .E\WH $3% $+% 65$0 .E\WH 65$0 .E\WH DocID029587 Rev 3 )ODVK$ 0E\WH $+% )ODVK% 0E\WH $+% $;,65$0 .E\WH $3% 463, $3% )0& ELW$;,EXVPDWUL[ 'GRPDLQ 'WR'$+% 'WR'$+% %'0$ 'WR'$+% /HJHQG ELWEXV 7&0 $+% $;, $3% 100/3178 ELWEXV 0DVWHULQWHUIDFH %XVPXOWLSOH[HU 6ODYHLQWHUIDFH $+% $3% 65$0 .E\WH ELW$+%EXVPDWUL[ 'GRPDLQ %DFNXS 65$0 .E\WH 06Y 9 Memory and bus architecture ELW$+%EXVPDWUL[ 'GRPDLQ RM0433 2.1.1 Memory and bus architecture Bus matrices AXI bus matrix in D1 domain The D1 domain multi AXI bus matrix ensures and arbitrates concurrent accesses from multiple masters to multiple slaves. This allows efficient simultaneous operation of highspeed peripherals. The arbitration uses a round-robin algorithm with QoS capability. The DTCM and ITCM (data and instruction tightly coupled RAMs) are connected through dedicated TCM buses directly to the Cortex-M7 core. The MDMA controller can access the DTCM and ITCM through AHBS, a specific CPU slave AHB. The ITCM is accessed by Cortex-M7 at CPU clock speed, with zero wait states. Refer to Section 5: AXI interconnect for more information on AXI interconnect. AHB bus matrices in D2 and D3 domains The AHB bus matrices in D2 and D3 domains ensure and arbitrate concurrent accesses from multiple masters to multiple slaves. This allows efficient simultaneous operation of high-speed peripherals. The arbitration uses a round-robin algorithm. 2.1.2 Bus-to-bus bridges To allow peripherals with different types of buses to communicate together, there is a number of bus-to-bus bridges in the system. The AHB/APB bridges in D1 and D3 domains allow connecting peripherals on APB3 and APB4 to AHB3 and AHB4, respectively. The AHB/APB bridges in D2 domain allow peripherals on APB1 and APB2 to connect to AHB1. These AHB/APB bridges provide full synchronous interfacing, which allows the APB peripherals to operate with clocks independent of AHB that they connect to. The AHB/APB bridges also allow APB1 and APB2 peripherals to connect to DMA1 and DMA2 peripheral buses, respectively, without transiting through AHB1. The AHB/APB bridges convert 8-bit / 16-bit APB data to 32-bit AHB data, by replicating it to the three upper bytes / the upper half-word of the 32-bit word. The AXI bus matrix incorporates AHB/AXI bus bridge functionality on its slave bus interfaces. The AXI/AHB bus bridges on its master interfaces marked as 32-bit in Figure 1 are outside the matrix. The Cortex-M7 CPU provides AHB/TCM-bus (ITCM and DTCM buses) translation from its AHBS slave AHB, allowing the MDMA controller to access the ITCM and DTCM. 2.1.3 Inter-domain buses D2-to-D1 AHB This 32-bit bus connects the D2 domain to the AXI bus matrix in the D1 domain. It allows bus masters in the D2 domain to access resources (bus slaves) in the D1 domain and indirectly, via the D1-to-D3 AHB, in the D3 domain. DocID029587 Rev 3 101/3178 104 Memory and bus architecture RM0433 D1-to-D2 AHB This 32-bit bus connects the D1 domain to the D2 domain AHB bus matrix. It allows bus masters in the D1 domain to access resources (bus slaves) in the D2 domain. D1-to-D3 AHB This 32-bit bus connects the D1 domain to the D3 domain AHB bus matrix. It allows bus masters in the D1 domain to access resources (bus slaves) in the D3 domain. D2-to-D3 AHB This 32-bit bus connects the D2 domain to the D3 domain AHB bus matrix. It allows bus masters in the D2 domain to access resources (bus slaves) in the D3 domain. 2.1.4 CPU buses Cortex®-M7 AXIM bus The Cortex®-M7 CPU uses the 64-bit AXIM bus for accesses with all memories and peripherals excluding the ITCM, DTCM, AHB2 peripherals, and, due to addressing incompatibility, excluding also the AHB1, APB1 and APB2 peripherals. The AXIM bus connects the CPU to the AXI bus matrix in the D1 domain. Cortex®-M7 ITCM bus The Cortex®-M7 CPU uses the 64-bit ITCM bus for fetching instructions from and accessing data in the ITCM. Cortex®-M7 DTCM bus The Cortex®-M7 CPU uses the 64-bit DTCM bus for accessing data in the DTCM. It can also fetch instructions. Cortex®-M7 AHBS bus The Cortex®-M7 CPU uses the 32-bit AHBS slave bus to allow the MDMA controller to access the ITCM and the DTCM. Cortex®-M7 AHBP bus The Cortex®-M7 CPU uses the 32-bit AHBP bus for accessing AHB1, AHB2, APB1 and APB2 peripherals via the AHB bus matrix in the D2 domain. 2.1.5 Bus master peripherals SDMMC1 The SDMMC1 uses a 32-bit bus, connected to the AXI bus matrix, through which it can access internal AXI SRAM and Flash memories, and external memories through the QuadSPI controller and the FMC. 102/3178 DocID029587 Rev 3 RM0433 Memory and bus architecture SDMMC2 The SDMMC2 uses a 32-bit bus, connected to the AHB bus matrix in D2 domain. Through the system bus matrices, it can access the internal AXI SRAM, SRAM1, SRAM2, SRAM3 and Flash memories, and external memories through the Quad-SPI controller and the FMC. MDMA controller The MDMA controller uses a 64-bit bus, connected to the AXI bus matrix, for DMA data transfers between memories and with peripherals. Through the system bus matrices and the Cortex-M7 AHBS slave bus, it can access all internal memories and AHB1 peripherals. It can also access external memories through the Quad-SPI controller and the FMC. DMA1 and DMA2 controllers The DMA1 and DMA2 controllers have two 32-bit buses - memory bus and peripheral bus, connected to the AHB bus matrix in D2 domain. The memory bus allows DMA data transfers between memories. Through the system bus matrices, the memory bus can access all internal memories except ITCM and DTCM, and external memories through the Quad-SPI controller and the FMC. The peripheral bus allows DMA data transfers between two peripherals, between two memories or between a peripheral and a memory. Through the system bus matrices, the peripheral bus can access all internal memories except ITCM and DTCM, external memories through the Quad-SPI controller and the FMC, and all AHB and APB peripherals. A direct access to APB1 and APB2 is available, without passing through AHB1. BDMA controller The BDMA controller uses a 32-bit bus, connected to the AHB bus matrix in D3 domain, for DMA data transfers between two peripherals, between two memories or between a peripheral and a memory. Through the AHB bus matrix in the D3 domain, it can access the internal SRAM4, backup RAM, and AHB4 and APB4 peripherals. Chrom-Art Accelerator™ (DMA2D) The DMA2D graphics accelerator uses a 64-bit bus, connected to the AXI bus matrix. Through the system bus matrices, internal AXI SRAM, SRAM1, SRAM2, SRAM3 and Flash memories, and external memories through the Quad-SPI controller and the FMC. LCD-TFT controller (LTDC) The LCD-TFT display controller, LTDC, uses a 64-bit bus, connected to the AXI bus matrix, through which it can access internal AXI SRAM and Flash memories, and external memories through the Quad-SPI controller and the FMC. Ethernet MAC The Ethernet MAC uses a 32-bit bus, connected to the AHB bus matrix in the D2 domain. Through the system bus matrices, it can access all internal memories except ITCM and DTCM, and external memories through the Quad-SPI controller and the FMC. DocID029587 Rev 3 103/3178 104 Memory and bus architecture RM0433 USBHS1 and USBHS2 peripherals The USBHS1 and USBHS2 peripherals use 32-bit buses, connected to the AHB bus matrix in the D2 domain. Through the system bus matrices, they can access all internal memories except ITCM and DTCM, and external memories through the Quad-SPI controller and the FMC. 2.1.6 Clocks to functional blocks Upon reset, clocks to blocks such as peripherals and some memories are disabled (except for the SRAM, DTCM, ITCM and Flash memory). To operate a block with no clock upon reset, the software must first enable its clock through RCC_AHBxENR or RCC_APBxENR register, respectively. 104/3178 DocID029587 Rev 3 RM0433 2.2 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. The addressable memory space is divided into 8 main blocks, of 512 Mbytes each. All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to Memory map and register boundary addresses and peripheral sections. 2.2.2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map. The following table gives the boundary addresses of the peripherals available in the devices. Table 2. Register boundary addresses Boundary address Peripheral Bus Register map 0x58026400 - 0x580267FF HSEM Section 10.4: HSEM registers 0x58026000 - 0x580263FF ADC3 Section 25.6: ADC common registers 0x58025800 - 0x58025BFF DMAMUX2 0x58025400 - 0x580257FF BDMA 0x58024C00 - 0x58024FFF CRC Section 21.4: CRC registers 0x58024800 - 0x58024BFF PWR Section 6.8: PWR register description 0x58024400 - 0x580247FF RCC Section 8.7: RCC register description 0x58022800 - 0x58022BFF GPIOK 0x58022400 - 0x580227FF GPIOJ 0x58022000 - 0x580223FF GPIOI 0x58021C00 - 0x58021FFF GPIOH Section 11.4: .GPIO registers 0x58021800 - 0x58021BFF GPIOG Section 11.4: .GPIO registers 0x58021400 - 0x580217FF GPIOF Section 11.4: .GPIO registers 0x58021000 - 0x580213FF GPIOE Section 11.4: .GPIO registers 0x58020C00 - 0x58020FFF GPIOD Section 11.4: .GPIO registers 0x58020800 - 0x58020BFF GPIOC Section 11.4: .GPIO registers 0x58020400 - 0x580207FF GPIOB Section 11.4: .GPIO registers 0x58020000 - 0x580203FF GPIOA Section 11.4: .GPIO registers Section 17.6: DMAMUX registers Section 16.4: BDMA registers Section 11.4: .GPIO registers AHB4 (D3) Section 11.4: .GPIO registers Section 11.4: .GPIO registers DocID029587 Rev 3 105/3178 111 RM0433 Table 2. Register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x58006400 - 0x58006BFF Reserved 0x58005400 - 0x580057FF SAI4 0x58004C00 - 0x58004FFF Reserved 0x58004800 - 0x58004BFF IWDG1 0x58004000 - 0x580043FF RTC & BKP registers 0x58003C00 - 0x58003FFF VREF 0x58003800 - 0x58003BFF COMP1 - COMP2 0x58003000 - 0x580033FF LPTIM5 0x58002C00 - 0x58002FFF LPTIM4 0x58002800 - 0x58002BFF LPTIM3 Section 43.6: LPTIM registers 0x58002400 - 0x580027FF LPTIM2 Section 43.6: LPTIM registers 0x58001C00 - 0x58001FFF I2C4 Section 47.7: I2C registers 0x58001400 - 0x580017FF SPI6 Section 50.11: SPI/I2S registers 0x58000C00 - 0x58000FFF LPUART1 Section 49.5: LPUART registers 0x58000400 - 0x580007FF SYSCFG Section 12.3: SYSCFG register description 0x58000000 - 0x580003FF EXTI 0x52008000 - 0x52008FFF Delay Block SDMMC1 0x52007000 - 0x52007FFF SDMMC1 0x52006000 - 0x52006FFF Delay Block QUADSPI 0x52005000 - 0x52005FFF QUADSPI control registers 0x52004000 - 0x52004FFF FMC control registers 0x52003000 - 0x52003FFF JPEG 0x52002000 - 0x52002FFF Flash interface registers Section 3.5: FLASH registers 0x52001000 - 0x52001FFF Chrom-Art (DMA2D) Section 18.6: DMA2D registers 0x52000000 - 0x52000FFF MDMA Section 14.5: MDMA registers 0x51000000 - 0x510FFFFF GPV 0x50003000 - 0x50003FFF WWDG1 Reserved Section 51.5: SAI registers Reserved Section 45.4: IWDG registers Section 27.3: VREFBUF registers Section 28.7: COMP registers APB4 (D3) Section 43.6: LPTIM registers Section 43.6: LPTIM registers Section 20.6: EXTI register description Section 24.4: DLYB registers Section 55.8: SDMMC registers Section 24.4: DLYB registers Section 23.5: QUADSPI registers AHB3 (D1) Section 22.7.6: NOR/PSRAM controller registers, Section 22.8.7: NAND Flash controller registers, Section 22.9.5: SDRAM controller registers Section 33.5: JPEG codec registers Section 5.4: AXI interconnect registers Section 44.4: .WWDG registers 0x50001000 - 0x50001FFF LTDC 0x50000000 - 0x50000FFF Reserved 0x48022800 - 0x48022BFF Delay Block SDMMC2 106/3178 Section 46.6: RTC registers APB3 (D1) Section 32.7: LTDC registers AHB2 (D2) Section 24.4: DLYB registers DocID029587 Rev 3 RM0433 Table 2. Register boundary addresses (continued) Boundary address Peripheral 0x48022400 - 0x480227FF SDMMC2 0x48021800 - 0x48021BFF RNG Bus Register map Section 55.8: SDMMC registers Section 34.8: RNG registers AHB2 (D2) 0x48021400 - 0x480217FF HASH Section 36.6: HASH registers 0x48021000 - 0x480213FF CRYPTO 0x48020000 - 0x480203FF DCMI 0x40080000 - 0x400BFFFF USB2 OTG FS Section 57.14: OTG_HS registers 0x40040000 - 0x4007FFFF USB1 OTG HS/FS Section 57.14: OTG_HS registers 0x40028000 - 0x400293FF ETHERNET MAC Section 58.11: Ethernet registers 0x40024400 - 0x400247FF Reserved 0x40022000 - 0x400223FF ADC1 - ADC2 0x40020800 - 0x40020BFF DMAMUX1 0x40020400 - 0x400207FF DMA2 Section 15.5: DMA registers 0x40020000 - 0x400203FF DMA1 Section 15.5: DMA registers 0x40017400 - 0x400177FF HRTIM Section 37.5: HRTIM registers 0x40017000 - 0x400173FF DFSDM1 0x40016000 - 0x400163FF SAI3 Section 51.5: SAI registers 0x40015C00 - 0x40015FFF SAI2 Section 51.5: SAI registers 0x40015800 - 0x40015BFF SAI1 Section 51.5: SAI registers 0x40015000 - 0x400153FF SPI5 Section 50.11: SPI/I2S registers 0x40014800 - 0x40014BFF TIM17 0x40014400 - 0x400147FF TIM16 0x40014000 - 0x400143FF TIM15 0x40013400 - 0x400137FF SPI4 Section 50.11: SPI/I2S registers 0x40013000 - 0x400133FF SPI1 / I2S1 Section 50.11: SPI/I2S registers 0x40011400 - 0x400117FF USART6 Section 48.7: USART registers 0x40011000 - 0x400113FF USART1 Section 48.7: USART registers 0x40010400 - 0x400107FF TIM8 Section 38.4: TIM1/TIM8 registers 0x40010000 - 0x400103FF TIM1 Section 38.4: TIM1/TIM8 registers Section 35.6: CRYP registers Section 31.7: DCMI register description AHB1 (D2) Reserved Section 25.6: ADC common registers Section 17.6: DMAMUX registers Section 30.7: DFSDM channel y registers (y=0..7), Section 30.8: DFSDM filter x module registers (x=0..3) APB2 (D2) Section 41.6: TIM16/TIM17 registers Section 41.6: TIM16/TIM17 registers Section 41.5: TIM15 registers DocID029587 Rev 3 107/3178 111 RM0433 Table 2. Register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x4000AC00 - 0x4000D3FF CAN Message RAM Section 56.4: FDCAN registers 0x4000A800 - 0x4000ABFF CAN CCU Section 56.4: FDCAN registers 0x4000A400 - 0x4000A7FF FDCAN2 Section 56.4: FDCAN registers 0x4000A000 - 0x4000A3FF FDCAN1 Section 56.4: FDCAN registers 0x40009400 - 0x400097FF MDIOS Section 54.4: MDIOS registers 0x40009000 - 0x400093FF OPAMP Section 29.6: OPAMP registers 0x40008800 - 0x40008BFF SWPMI Section 53.6: SWPMI registers 0x40008400 - 0x400087FF CRS 0x40007C00 - 0x40007FFF UART8 Section 48.7: USART registers 0x40007800 - 0x40007BFF UART7 Section 48.7: USART registers 0x40007400 - 0x400077FF DAC1 Section 26.6: DAC registers 0x40006C00 - 0x40006FFF HDMI-CEC 0x40005C00 - 0x40005FFF I2C3 Section 47.7: I2C registers 0x40005800 - 0x40005BFF I2C2 Section 47.7: I2C registers 0x40005400 - 0x400057FF I2C1 Section 47.7: I2C registers 0x40005000 - 0x400053FF UART5 Section 9.7: CRS registers Section 59.7: HDMI-CEC registers Section 48.7: USART registers APB1 (D2) 0x40004C00 - 0x40004FFF UART4 0x40004800 - 0x40004BFF USART3 Section 48.7: USART registers 0x40004400 - 0x400047FF USART2 Section 48.7: USART registers 0x40004000 - 0x400043FF SPDIFRX Section 52.5: SPDIFRX interface registers 0x40003C00 - 0x40003FFF SPI3 / I2S3 Section 50.11: SPI/I2S registers 0x40003800 - 0x40003BFF SPI2 / I2S2 Section 50.11: SPI/I2S registers 0x40002C00 - 0x40002FFF Reserved 0x40002400 - 0x400027FF LPTIM1 0x40002000 - 0x400023FF TIM14 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 0x40001C00 - 0x40001FFF TIM13 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 0x40001800 - 0x40001BFF TIM12 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 0x40001400 - 0x400017FF TIM7 Section 42.4: TIM6/TIM7 registers 0x40001000 - 0x400013FF TIM6 Section 42.4: TIM6/TIM7 registers 0x40000C00 - 0x40000FFF TIM5 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 0x40000800 - 0x40000BFF TIM4 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 0x40000400 - 0x400007FF TIM3 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 0x40000000 - 0x400003FF TIM2 Section 39.4: TIM2/TIM3/TIM4/TIM5 registers 108/3178 Section 48.7: USART registers Reserved Section 43.6: LPTIM registers DocID029587 Rev 3 RM0433 2.3 Embedded SRAM The STM32H7x3 devices feature: • Up to 864 Kbytes of System SRAM • 128 Kbytes of data TCM RAM • 64 Kbytes of instruction TCM RAM • 4 Kbytes of backup SRAM The embedded system SRAM is divided into up to five blocks: • AXI SRAM (D1 domain): – • • AXI SRAM mapped at address 0x2400 0000 and accessible by all system masters except BDMA through D1 domain AXI bus matrix AHB SRAM (D2 domain): – AHB SRAM1 mapped at address 0x3000 0000 and accessible by all system masters except BDMA through D2 domain AHB matrix – AHB SRAM2 mapped at address 0x3002 0000 and accessible by all system masters except BDMA through D2 domain AHB matrix – AHB SRAM3 mapped at address 0x3004 0000 and accessible by all system masters except BDMA through D2 domain AHB matrix AHB SRAM (D3 domain): – AHB SRAM4 mapped at address 0x3800 0000 and accessible by most of system masters through D3 domain AHB matrix The system AHB SRAM can be accessed as bytes, half-words (16-bit units) or full-words (32-bit units), while the system AXI SRAM can be accessed as bytes, half-words, full-words or double-words (64-bit units). These memories can be addressed at maximum system clock frequency without wait state. The AHB masters can read/write-access an SRAM section concurrently with the Ethernet MAC or the USB OTG HS peripheral accessing another SRAM section. For example, the Ethernet MAC accesses the SRAM2 while the CPU accesses the SRAM1, concurrently. The TCM SRAMs are dedicated to the Cortex®-M7: • DTCM-RAM on TCM interface is mapped at the address 0x2000 0000 and accessible by Cortex®-M7, and by MDMA through AHBS slave bus of the Cortex®-M7 CPU. • ITCM-RAM on TCM interface mapped at the address 0x0000 0000 and accessible by Cortex®-M7 and by MDMA through AHBS slave bus of the Cortex®-M7 CPU. The backup RAM is mapped at the address 0x3880 0000 and is accessible by most of the system masters through D3 domain’s AHB matrix. Error code correction (ECC) SRAM data are protected by ECC: • 7 ECC bits are added per 32-bit word. • 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single- and doubleerror correction. DocID029587 Rev 3 109/3178 111 RM0433 2.4 Flash memory overview The Flash memory interface manages CPU AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory is organized as follows: • Two main memory block divided into sectors. • An information block: – System memory from which the device boots in System memory boot mode – Option bytes to configure read and write protection, BOR level, watchdog software/hardware and reset when the device is in Standby or Stop mode. Refer to Section 3: Embedded Flash memory (FLASH) for more details. 2.5 Boot configuration In the STM32H7x3, two different boot areas can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes as shown in the Table 3. Table 3. Boot modes Boot mode selection Boot area BOOT Boot address option bytes 0 BOOT_ADD0[15:0] Boot address defined by user option byte BOOT_ADD0[15:0] ST programmed value: Flash memory at 0x0800 0000 1 BOOT_ADD1[15:0] Boot address defined by user option byte BOOT_ADD1[15:0] ST programmed value: System bootloader at 0x1FF0 0000 The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset. The BOOT pin is also re-sampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode. After startup delay, the selection of the boot area is done before releasing the processor reset. The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot memory address from 0x0000 0000 to 0x3FFF 0000 which includes: • All Flash address space • All RAM address space: ITCM, DTCM RAMs and SRAMs • The TCM-RAM The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot from any other boot address after next reset. 110/3178 DocID029587 Rev 3 RM0433 If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is programmed as follows: – Boot address 0: FLASH at 0x0800 0000 – Boot address 1: ITCM-RAM at 0x0000 0000 When the Flash level 2 protection is enabled, only boot from Flash memory is available. If the boot address already programmed in the BOOT_ADD0 / BOOT_ADD1 option bytes is out of the memory range or belongs to the RAM address range, the default fetch will be forced from Flash memory at address 0x0800 0000 . Embedded bootloader The embedded bootloader code is located in system memory. It is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces: • USART1 on pins PA9/PA10 and PB14/PB15, USART2 on pins PA3/PA2 and USART3 on pins PB10/PB11. • I2C1 on pins PB6/PB9, I2C2 on pins PF0/PF1 and I2C3 on pins PA8/PC9 • USB OTG FS in Device mode (DFU) on pins PA11/PA12 • SPI1 on pins PA7/PA6/PA5/PA4, SPI2 on pins PI3/PI2/PI1/PI0, SPI3 on pins PC12/PC11/PC10/PA15 and SPI4 on pins PE14/PE13/PE12/PE11. For additional information, refer to the application note AN2606. DocID029587 Rev 3 111/3178 111 Embedded Flash memory (FLASH) RM0433 3 Embedded Flash memory (FLASH) 3.1 Introduction The Flash memory interface manages AXI accesses of any master to the Flash memory. It implements the read, program and erase Flash memory operations as well as the read and program/erase protection mechanisms. The Flash interface also manages the option byte loading at reset and the dynamic option byte change. 3.2 FLASH main features • Memory density up to 2 Mbytes • Error Code Correction (ECC): 10 ECC bits by 256-bit Flash word • Double-word, word, half-word and byte read operations • Flash programming by 256 bits • Double-word, word, half-word and byte write operations • Sector erase, Bank erase and Mass erase • Dual-bank organization supporting simultaneous operations: two read/program/erase operations can be executed in parallel on the two banks • Bank swapping: the address mapping of the user Flash memory of each bank can be swapped. • Enhanced security features • 112/3178 – Readout protection (RDP) – Sector write protection – 2 PCROP protection area (1 per bank) (execute-only memory) 2 secure area in user Flash memory (1 per bank) DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.3 FLASH functional description 3.3.1 Block diagram Figure 2. Flash memory block diagram 0DVWHU 0DVWHU $+% V\VBFN 0DVWHUQ $;, ,QWHUFRQQHFW )ODVK &RQILJXUDWLRQ 5HJLVWHUV )ODVKPHPRU\ ,QWHUIDFH IODVKBLW 1567 )ODVK %DQN )ODVK %DQN 06Y 9 3.3.2 Pins and internal signals Table 4 lists the FLASH inputs and output signals connected to package pins or balls, while Table 5 shows the internal FLASH signals. Table 4. FLASH input/output signals connected to package pins or balls Signal name Signal type NRST Digital input Description External reset signal. Table 5. FLASH internal input/output signals Signal name Signal type sys_ck Digital input System clock flash_it Digital output Embedded Flash memory interrupt Description DocID029587 Rev 3 113/3178 185 Embedded Flash memory (FLASH) 3.3.3 RM0433 Flash memory architecture The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: • One Flash word (8 words, 32 bytes or 256 bits) • 10 ECC bits. The Flash memory is divided into two independent banks. Each bank is organized as follows: • A 1 Mbyte user Flash memory block containing eight user sectors of 128 Kbytes(4 K Flash words) • 128 Kbytes of System Flash memory from which the device can boot: This area contains root secure services (RSS) and the bootloader, which are used respectively for secure or non-secure Flash memory programming through one of the following interfaces: USART, USB (DFU), I2C, SPI or Ethernet. The System Flash memory is reserved for use by STMicroelectronics. It is programmed by STMicroelectronics when the device is manufactured, and then protected against spurious program/erase operations. For further details, please refer to application note AN2606 “STM32 microcontroller System Flash memory boot mode” available from http://www.st.com. • 2 Kbytes (64 Flash words) of user option bytes for user configuration: This area is available only in bank 1. Unlike user Flash memory and System Flash memory, it is not mapped to any memory address and can be accessed only through the Flash register interface. Figure 2 shows the Flash memory high-level block diagram while Table 6 describes the Flash memory organization. Figure 3 gives an overview of the Flash memory mapping as well as of the protection mechanisms. A PCROP and a secure area can be defined for each bank. The properties of these protected areas are detailed in Section 3.3.12: Protection mechanisms, while the secure services stored in System Flash memory are described in Section 4: Security memory management. Table 6. Flash module - 1 Mbyte dual bank organization Flash area Start address User Flash memory Bank 1 System Flash memory 114/3178 End address Size (bytes) Region Na me 0x0800 0000 0x0801 FFFF 128 K Sector 0 0x0802 0000 0x0803 FFFF 128 K Sector 1 ... ... ... ... 0x080E 0000 0x080F FFFF 128 K Sector 7 0x1FF0 0000 0x1FF1 FFFF 128 K System Flash memory DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Table 6. Flash module - 1 Mbyte dual bank organization (continued) Flash area Start address User Flash memory Bank 2 System Flash memory End address Region Na Size (bytes) me 0x0810 0000 0x0811 FFFF 128 K Sector 0 0x0812 0000 0x0813 FFFF 128 K Sector 1 ... ... ... ... 0x081E 0000 0x081F FFFF 128 K Sector 7 0x1FF4 0000 0x1FF5 FFFF 128 K System Flash memory Figure 3. Flash memory overview 0DLQXVHUPHPRU\%DQN [[.E\WHV 2SWLRQE\WHV 6HFW 6(&B$5($B(1' 6HFXUH$UHD 6HFW 8VHUVHFXUHDUHD 6HFXUHDFFHVVRQO\ 6(&B$5($B67$57 3527B$5($B(1' 3527B$5($B67$57 ([HFXWHRQO\UHJLRQ QRUHDGDFFHVV 3&523$UHD 6HFW 6HFW 6\VWHP)ODVK%DQN %RRWORDGHU 1RQ6HFXUH 566BERRW 6HFXUH 566URRWVHFXULW\VHUYLFHV 6HFXUHDFFHVVRQO\ 2SWLRQ%\WHVHFWRU 06Y 9 DocID029587 Rev 3 115/3178 185 Embedded Flash memory (FLASH) 3.3.4 RM0433 Flash read operations Read protocol The Flash interface support the following access types: • Double-word (64 bits) • Single-word (32 bits) • Half-word (16 bits) • Byte (8 bits) The Flash interface clock must be enabled and running when reading data from Flash memory. To ensure correct Flash interface read operation, the number of wait states (LATENCY) must be correctly configured in the FLASH_ACR register according to the Flash memory interface frequency (see Section : Read access latency). A wrong number of wait states may results in incorrect read values (e.g.when not enough wait states have been programmed) or to a long access time (e.g.when too many wait states have been programmed). The operations are executed in the order in which they have been received by the Flash interface. The Flash interface is built in such a way that only one read, program or erase operation can be executed at a time on a given bank. As an example, let us consider the case where the user Flash memories are swapped. The first AXI interface requests a read operation on bank 1 System Flash memory (ICP) while the second AXI interface requests a read or fetch operation on the user Flash memory of the same bank. In this case, a hardware arbitration occurs and both read requests are accepted, but they are served sequentially. Simultaneous read/program/erase operations are supported if they target different banks. When a read operation is requested while a program/erase operation is ongoing on the same bank, the read command is buffered and is executed after the program/erase operation has completed. The system is not stalled unless the read command FIFO is full (3 read operations are already pending). Read sequence The Flash interface implements a dual AXI bus interface for code/data accesses and an AHB interface for Flash interface configuration. The AXI interfaces can request a read/program operation at the same time. The read mechanism is the following: 116/3178 • The read command buffer depth is fixed to 3 requests. When it is full (3 read requests queued in the buffer), any new read request will stall the bus interface and consequently the master. • The Flash interface will free a request in the read command queue buffer as soon as the last data of current read transaction are transferred from the Flash memory to the read data buffer inside the Flash memory interface. • Any system read request which data are not available in the read buffer will trigger a Flash read operation. This latter will be buffered inside the read data buffer. • If several consecutive read accesses request data that belong to the same Flash data word (256 bits), data are read directly from the current data read buffer and do not trigger additional Flash read operations. DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Figure 4 and Figure 5 show the timing diagrams of a burst read transaction of four and eight double-word data, respectively. The latency is configured to three wait states: 1. The first data are available after a first latency (three wait states). 2. Once the data are available in the read current buffer, the Flash interface is ready to execute the next command from the read command queue. 3. The second latency, corresponding to next Flash word read access, is masked by the current buffer read operation which can serve four double-word read consecutively. This is equivalent to a 0 wait-state execution sequence. Figure 4. Burst read timing diagram - 4x64bits, latency = 3 ws $&/. $ $5$''5 $59$/,' ' 5'$7$ ' ' ' 59$/,' 5/$67 )ODVK5HDG )G )ODVK'DWD /$7(1&< :6 06Y 9 1. ACLK, ARADDR, ARVALID, RDATA, RVALID and RLAST are AXI bus signals. Flash Read and Flash Data are Flash interface signals. Figure 5. Burst read timing diagram - 8x64bits, latency = 3 ws $&/. $5$''5 $ $59$/,' ' 5'$7$ ' ' ' ' ' ' ' 59$/,' 5/$67 )ODVK5HDG )G )ODVK'DWD )G /$7(1&< :6 06Y 9 1. ACLK, ARADDR, ARVALID, RDATA, RVALID and RLAST are AXI bus signals. Flash Read and Flash Data are Flash interface signals. DocID029587 Rev 3 117/3178 185 Embedded Flash memory (FLASH) RM0433 Read access latency To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the bus clock (aclk) and the internal voltage range of the device VCORE. Table 7 shows the correspondence between the number of wait states, the bus clock frequency and VCORE range. Table 7. Number of wait states according to bus frequency (ACLK) and VCORE range VCORE range VOS1 level VOS2 level VOS3 level Number of wait states Maximum frequency 0 70 MHz 1 140 MHz 2 210 MHz 0 55 MHz 1 110 MHz 2 165 MHz 3 220 MHz 0 45 MHz 1 90 MHz 2 135 MHz 3 180 MHz 4 225 MHz 1.15 V - 1.26 V 1.05 V - 1.15 V 0.95 V - 1.05 V After power-on, the clock used is the HSI (64 MHz) and 0x7 wait-states are configured by default in the FLASH_ACR register. To change the bus frequency, the software sequences described in Section : Adjusting the bus frequency must be applied in order to tune the number of wait states required to access the Flash memory. 118/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Adjusting the bus frequency • • 3.3.5 Increasing the bus frequency a) If necessary, program the right number (see Table 7) of wait states to the LATENCY bits in the FLASH_ACR register. b) Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register. c) Modify the Flash interface clock source and/or the bus clock prescaler in the RCC_CFGR register. d) Check that the new Flash interface clock source and/or the new Flash interface clock prescaler value has been taken in account, by reading the clock source status and/or the bus prescaler value, in the RCC_CFRG register. Decreasing the bus frequency a) Modify the Flash interface clock source and/or the bus clock prescaler in the RCC_CFGR register. b) Check that the new Flash interface clock source and/or the new bus clock prescaler value are taken into account by reading the Flash interface clock source status and/or the bus prescaler value in the RCC_CFGR register. c) If necessary, program the right number of wait states (see Table 7) to the LATENCY bits in FLASH_ACR register. d) Check that the new number of wait states has been taken into account by reading the FLASH_ACR register. Error code correction (ECC) Data in Flash memory are 266-bit words: 10 ECC bits are added per Flash word of 256 bits. The ECC mechanism is based on the SECDED algorithm. It supports: • Single error correction • Double errors detection When an error is detected and corrected, the SNECCERR1/2 flag is set in FLASH_SR1/2 register. An interrupt is generated if SNECCERRIE bit is set in FLASH_CR1/2 register. When two errors are detected, the DBECCERR1/2 flag is set in FLASH_SR1/2 register and a bus error is generated. In this case the received data are not corrected. An interrupt is generated if DBECCERRIE1/2 bit is set in FLASH_CR1/2 register. When an ECC error is detected, the address of the failing Flash word is saved in the FLASH_ECC_FA1/2R register. In case of successive error detections, only the address corresponding to the first error will be stored. This register is automatically cleared when the associated flag that generated the error has been reset. DocID029587 Rev 3 119/3178 185 Embedded Flash memory (FLASH) 3.3.6 RM0433 Cyclic redundancy check module The Flash interface embeds a cyclic redundancy check hardware module. This module allows checking the integrity of a Flash area content. This area can be defined either by sectors or by start/end addresses. Only one CRC check operation on bank 1 or 2 can be launched at a time. The CRC operation is concurrent with option byte change operations. This means that if a CRC operation is requested while an option byte change is ongoing, the option byte change operation must be complete before serving the CRC operation, and vice-versa. When enabled, the CRC hardware module processes Flash data by chunks of 4, 16, 64 or 256 Flash words. CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7 X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1 The Flash interface internally issues 4, 16, 64 or 256 consecutive Flash-word read accesses. These transactions are queued into the read command queue together with other AXI read requests, thus avoiding to deny AXI read commands. The queue command buffer can contain only one CRC command. The sequence recommended to configure a CRC operation in the bank 1/2 is the following: 1. Enable the CRC feature by setting the CRC_EN bit in FLASH_CR1/2. 2. Program the desired data size in the CRC_BURST field of FLASH_CRCCR1/2. 3. Define the Flash area on which the CRC has to be computed.Two solutions are possible: – Define the area start and end addresses by programing FLASH_CRCSADD1/2R and FLASH_CRCEADD1/2R, respectively – or select the targeted sectors by setting the CRC_BY_SECT bit in FLASH_CRCCR1/2 and by programming consecutively the target sector numbers in the CRC_SECT field of the FLASH_CRCCR1/2 register. Set ADD_SECT bit after each CRC_SECT programming. 4. Start the CRC operation by setting the START_CRC bit. 5. Wait until the CRC_BUSY flag is reset. 6. Retrieve the CRC result in the FLASH_CRCDATAR register. The CRC can be computed for a whole bank by setting the ALL_BANK bit in the FLASH_CRCCR1/2 register. Note: 120/3178 Running a CRC on PCROP- or secure-protected user Flash area may alter the expected CRC value. DocID029587 Rev 3 RM0433 3.3.7 Embedded Flash memory (FLASH) Flash program and erase operations Overview of program/erase operations The Flash interface implements single error correction and double error detection (see Section 3.3.5: Error code correction (ECC). The ECC algorithm is built so that a full “zero” data generates a full “zero” ECC code, and a full “ones” data generates full “ones” ECC codes. Since a 10-bit ECC code is associated to each 256-bit data Flash word, only write operations by 256 bits are supported. To restore the virgin state, an erase of the entire sector is required. The Flash memory interface supports multiple program operations: • Write to user sectors • Erase user sectors • Erase bank 1, bank 2 or both banks • Change user option bytes The write accesses issued through the AXI interface can be considered as bufferable and not cacheable except that it is not possible to read back the write buffer inside the Flash interface. The embedded Flash memory can be programmed using in-circuit programming or inapplication programming. Write buffer structure and hints The Flash interface write queue buffer can contain 2 requests. As a result, when several write accesses are requested to the Flash interface, they are accepted until the write queue buffer becomes full. When it is full, the Flash interface stalls the AXI bus. The operations are executed in the order in which they have been received by the Flash interface. The system is not stalled unless the write command queue and the write buffer are full (2 write operations are already ongoing). During a normal write operation, the PG1/2 bit must be set to ‘1’ (see Section : Enabling write operation). Write accesses must then fill in the 256-bit write buffer. When it is full, its content is automatically transferred to the write queue buffer. The effective write operation is executed as soon as the Flash is ready and the previously requested operations have been served. When the write buffer is partially filled, a write operation can be forced before filling entirely the write buffer. This is done by setting the FW1/2 bits in FLASH_CR1/2. In this particular case, the unwritten bits are automatically set to “high” value. If no bit in the write buffer is set to “low”, the FW1/2 bit has no effect. It is not recommended to overwrite a not virgin Flash word. The result may result in an inconsistent ECC code. The Flash interface can report systematically ECC errors. A valid scenario that can be supported is to overwrite with all zero data. In this case the corresponding ECC code will also be all zero. Consequently, no ECC errors will be detected during the read. The write buffer also supports incremental write burst accesses. It allows wrap burst write accesses only when they do not cross 32-byte aligned addresses (Flash word = 256 bits). DocID029587 Rev 3 121/3178 185 Embedded Flash memory (FLASH) RM0433 Configuring the programming parameters The user application must configure the programming parameters prior to performing a program/erase operation: 1. Unlock and program the Flash configuration registers (FLASH_CR1/2): The Flash interface implements two Flash control registers: FLASH_CR1 for bank 1 and FLASH_CR2 for bank 2. After reset, these registers are write-protected to avoid unwanted operations on the Flash memory (e.g. due to electric disturbances). The following sequence is used to unlock FLASH_CR1/2 registers: a) Write KEY1 = 0x45670123 in the FLASH_KEYR1/2 register. b) Write KEY2 = 0xCDEF89AB in the FLASH_KEYR1/2 register. The LOCK1/2 bit in FLASH_CR1/2 register are automatically cleared. Any wrong sequence locks up FLASH_CR1/2 until the next system reset. In this case, a bus error is generated. In addition, the FLASH_CR1/2 remains locked and a bus error is generated when the following operations are executed: – programming a third key value, – writing to a different register belonging to the same bank than FLASH_KEYR1/2 before FLASH_CR1/2 has been completely unlocked (KEY1 programmed but KEY2 not yet programmed). – writing less than one Flash word to KEY1 or KEY2. To lock again the FLASH_CR1/2 registers, set the corresponding LOCK1/2 bit to ‘1’ by software. Note: The FLASH_KEYR1/2 are only accessible at word level. 2. Unlock the Flash option configuration register (FLASH_OPTCR): To modify the option bytes, unlock the FLASH_OPTCR register. Since option bytes are common to both banks, only one FLASH_OPTCR register exists in the Flash interface and FLASH_OPTCR is not impacted by bank swapping. The register is aliased and therefore accessible at two different addresses: – 0x018 – 0x118 After reset, the OPTLOCK bit is set to ‘1’ and FLASH_OPTCR is locked. The following sequence is required to unlock the FLASH_OPTCR register: a) Write 0x08192A3B to OPTKEY1 in the FLASH_OPTKEYR register. b) Write 0x4C5D6E7F to OPTKEY2 in the FLASH_OPTKEYR register After executing this sequence, the OPTLOCK bit is cleared and FLASH_OPTCR is unlocked. Any wrong key sequence locks up FLASH_OPTCR until the next system reset and generates a bus error. In addition, the FLASH_OPTCR remains locked and a bus error is generated when the following operations are executed: – programming a third key value, – writing to a different register before FLASH_OPTCR has been completely unlocked (OPTKEY1 programmed but OPTKEY2 not yet programmed) – writing less than one Flash word to OPTKEY1 or OPTKEY2. To lock again the FLASH_OPTCR register, set the OPTLOCK bit to ‘1’ by software. Note: 122/3178 The FLASH_OPTCR is only accessible at word level. DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3. Set the programming parallelism: The parallelism is the maximum number of bits that can be written to ‘0’ in one shot during a write operation. The programming parallelism is also used during sector and bank erase. There is no hardware limitation on programming parallelism. The user can select different parallelisms depending on the application requirements: the lower the parallelism, the lower the peak consumption during a programming operation, but the longer the execution time. The parallelism is configured through the PSIZE1/2 bits in FLASH_CR1/2. Two distinct values can be defined for bank 1 and 2 (refer to Table 8). Table 8. Parallelism parameter PSIZE1/2 Parallelism 00 byte (8 bits) 01 half-word (16 bits) 10 word (32 bits) 11 double-word (64 bits) 4. Set the programming delay: Programming operation timing constraints depend of the Flash interface frequency, which directly impacts the performance. If timing constraints are too tight, the Flash memory will not operate correctly, if they are too lax, programming speed will not be optimal. The user must therefore trim the optimal programming delay through the WRHIGHFREQ parameter in the FLASH_ACR register. This configuration register is common to both banks. Refer to Table 9 for the recommended programming delay depending on the Flash interface frequency. Table 9. Programming speed Recommended WRHIGHFREQ value Flash interface frequency (MHz) 00 85 01 185 After modifying WRHIGHFREQ, check that the new value has been correctly taken in account by reading it back. Note: When the programming speed is modified while a program/erase operation is ongoing, the new value will be taken into account only after the current operation is complete. Enabling write operation Prior to programming, the PG1/2 bit must be set in FLASH_CR1/2. FLASH_CR1/2 must be previously unlocked. Any write access requested while the PG1/2 bit is set to ‘0’ will be rejected. In this case, no error is generated on the bus, but the PGSERR1/2 flag is raised. DocID029587 Rev 3 123/3178 185 Embedded Flash memory (FLASH) RM0433 Checking write protections The protection properties of the write transaction target are checked at the output of the write queue buffer, just before the effective write to the Flash memory. No check is performed when the Flash interface accepts AXI write requests. If a write protection violation is detected, the write operation is canceled and a flag corresponding to the protection violation raised in the FLASH_SR1/2 register. If the write operation is valid, the 10-bit ECC code is concatenated to the 256-bits of data and the write to the Flash memory is effectively executed. The write protection flag must be cleared before performing a new program/erase operation. Write status busy flags Three different status flags located in FLASH_SR1/2 are available for each bank. They indicate the ongoing write operation status: Note: • BSY1/2: This bit indicates that an effective write, erase or option byte change operation is ongoing to the Flash memory. • QW1/2: This bit indicates that a program, erase or option byte change operation is pending. This bit remains high until the write operation is complete. It supersedes the BSY1/2 status bit. • WBNE1/2: This bit indicates that the write buffer is not empty. It is reset as soon as the write command is queued. Since the write buffer corresponds to 256-bit Flash words aligned on 32-byte addresses, it is not possible to start writing a new Flash word if another write operation is ongoing. Simple write sequence (recommended) 1. Set PG1/2 bit in the FLASH_CR1/2 register of the targeted bank (bank1/2) (see Section : Enabling write operation). 2. Check the protection of the target memory area (see Section : Checking write protections). 3. Write one Flash word corresponding to 32-byte data starting at 32-byte aligned address. 4. Check that BSY1/2 has been raised and wait until it is reset (see Section : Write status busy flags). Optimal block write sequence This sequence can be used to program a block to Flash memory: 124/3178 1. Set PG1/2 bit in the FLASH_CR1/2 register of the corresponding bank (bank1/2) (see Section : Enabling write operation). 2. Check the protection of the target memory area (see Section : Checking write protections). 3. Write successively 32 data bytes (Flash words) until the whole block is transferred. Each Flash word must start at an 32-byte aligned address. DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Release the Flash interface to allow the system switching to Stop or Standby mode If one of the busy flags is active, the microcontroller cannot switch the D1 domain to Stop or Standby mode (see Section 6: Power control (PWR)). There are two ways to release the Flash interface: • • Reset the WBNE1/2 busy flag by any of the following actions: a) Complete the write buffer with missing data. b) Force the write operation without filling the missing data by activating the FW1/2 bit in FLASH_CR1/2. This will force all missing data “high”. c) Reset the PG1/2 bit in FLASH_CR1/2. This will disable the write buffer and consequently lead to the loss of its content. Poll BSY1/2 and QW1/2 busy bits until they are cleared. This will indicate that all recorded write, erase and option change operations are complete. The microcontroller can then switch to Stop or Standby mode. Flash sector erase To erase a 128-Kbytes user sector proceed as follows: Note: 1. Check and clear (optional) all the error flags due to previous programming/erase operation (refer to Section 3.3.9: Flash interface error flags for details). 2. Unlock the FLASH_CR1/2 register, as described in Section : Configuring the programming parameters. 3. Set the SER1/2 bit and SNB1/2 bitfield in the corresponding FLASH_CR1/2 register. SER1/2 indicates a sector erase operation, while SNB1/2 contains the target sector number. 4. Set the START1/2 bit in the FLASH_CR1/2 register. 5. Wait for the BSY1/2 bit to be cleared in the corresponding FLASH_SR1/2 register. If a bank erase is requested simultaneously to the sector erase (BER1/2 bit set), the bank erase operation supersedes the sector erase operation. Standard Flash bank erase To erase all bank sectors excepted for those containing secure and protected data, proceed as follows: 1. Check and clear (optional) all the error flags due to previous programming/erase operation (refer to Section 3.3.9: Flash interface error flags for details). 2. Unlock the FLASH_CR1/2 register, as described in Section : Configuring the programming parameters. 3. If a PCROP-protected area exists, DMEP1/2 bits both in FLASH_PRAR_CUR1/2 and FLASH_PRAR_PRG1/2 registers shall be set to 0. 4. If a secure-only area exists, DMES1/2 bits both in FLASH_SCAR_CUR1/2 and FLASH_SCAR_PRG1/2 registers shall be set to 0. 5. Set the BER1/2 bit in the FLASH_CR1/2 register corresponding to the target bank. 6. Set the START1/2 bit in the FLASH_CR1/2 register to start the bank erase operation. Then wait until the BSY1/2 bit is cleared in the corresponding FLASH_SR1/2 register. DocID029587 Rev 3 125/3178 185 Embedded Flash memory (FLASH) Note: RM0433 BER1/2 and START1/2 bits can be set together and steps 8 and 9 merged. If a sector erase is requested simultaneously to the bank erase (SER1/2 bit set), the bank erase operation supersedes the sector erase operation. Flash bank erase with automatic protection removal To erase all bank sectors including those containing secure and protected data, without performing an RDP regression, proceed as follows: 1. Check that no Flash memory operation is ongoing by monitoring the BSY1/2 bits in FLASH_SR1/2 register. 2. Check and clear (optional) all the error flags due to previous programming/erase operation (refer to Section 3.3.9: Flash interface error flags for details). 3. Unlock FLASH_OPTCR register, as described in Section : Configuring the programming parameters. 4. If a PCROP-protected area exists, set DMEP1/2 bit either in FLASH_PRAR_CUR1/2 or FLASH_PRAR_PRG1/2 register. In addition, program the PCROP area end and start addresses so that the difference is negative, that is: 5. If a secure-only area exists, set DMES1/2 bit either in FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2 register. In addition, program the secure area end and start addresses so that the difference is negative, that is: PROT_AREA_END1/2 < PROT_AREA_START1/2 SEC_AREA_END1/2 < SEC_AREA_START1/2 Note: Note: Step 5 can only be performed by ST secure library or by an application running in Secure mode. However it is only mandatory when a secure-only area exists. 6. Set all WRPSn1/2 bits in FLASH_WPSN_PRG1/2R to 1 to disable all sector write protection. 7. Unlock FLASH_CR1/2 register. 8. Set the BER1/2 bit in the FLASH_CR1/2 register corresponding to the target bank. 9. Set the START1/2 bit in the FLASH_CR1/2 register to start the bank erase with protection removal operation. Then wait until the BSY1/2 bit is cleared in the corresponding FLASH_SR1/2 register. At that point a bank erase operation erases the whole bank including the sectors containing PCROP-protected and/or secured data, and an option byte change is automatically performed so that all the protections are disabled. BER1/2 and START1/2 bits can be set together and steps 8 and 9 merged. Warning: 126/3178 Please note the following warnings, with regard to above sequence: - It is not possible to execute the above sequence on one bank while also modifying the protection parameters of the other bank. - No other option bytes than those indicated above must be changed, and no protection change must be performed in the bank that is not targeted by the bank erase with protection removal request. - When one or both of the events above occur(s), a simple DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) bank erase takes place, no option byte change occurs and no option change error is set. Flash mass erase To erase all sectors of both banks simultaneously, excepted for those containing secure and protected data, the user application can set the MER bit to 1 in FLASH_OPTCR register, as described below: 1. Check that no Flash memory operation is ongoing by monitoring the BSY1/2 bits in FLASH_SR1/2. 2. Check and clear (optional) all the error flags due to previous programming/erase operation (refer to Section 3.3.9: Flash interface error flags for details). 3. Unlock the two FLASH_CR1/2 registers plus FLASH_OPTCR register, as described in Section : Configuring the programming parameters. 4. If a PCROP-protected area exists, DMEP1/2 bits both in FLASH_PRAR_CUR1/2 and FLASH_PRAR_PRG1/2 registers shall be set to 0. 5. If a secure-only area exists, DMES1/2 bits both in FLASH_SCAR_CUR1/2 and FLASH_SCAR_PRG1/2 registers shall be set to 0. 6. Set the MER bit to 1 in FLASH_OPTCR register. It automatically sets BER1, BER2, START1 and START2 to 1, thus launching a bank erase operation on both banks. Then wait until the BSY1/2 bit is cleared in the corresponding FLASH_SR1/2 register. Flash mass erase with automatic protection removal To erase all sectors of both banks simultaneously, including those containing secure and protected data, and without performing an RDP regression, proceed as follows: Note: 1. Check that no Flash memory operation is ongoing by monitoring the BSY1/2 bits in FLASH_SR1/2. 2. Check and clear (optional) all the error flags due to previous programming/erase operation. 3. Unlock the two FLASH_CR1/2 registers plus FLASH_OPTCR register. 4. If a PCROP-protected area exists, set DMEP1/2 bit either in FLASH_PRAR_CUR1/2 or FLASH_PRAR_PRG1/2 register. In addition program the PCROP area end and start addresses so that the difference is negative. 5. If a secure-only area exists set DMES1/2 bit either in FLASH_SCAR_CUR1/2 or FLASH_SCAR_PRG1/2 register. In addition program the secure area end and start addresses so that the difference is negative. Step 5 can only be performed by ST secure library or by an application running in Secure mode. it is however only mandatory when a secure-only area exists. 6. Set all WRPSn1/2 bits in FLASH_WPSN_PRG1/2R to 1 to disable all sector write protection. 7. Set the MER bit to 1 in FLASH_OPTCR register, then wait until the BSY1/2 bit is cleared in the corresponding FLASH_SR1/2 register. At that point a Flash bank erase with automatic protection removal is executed on both banks. DocID029587 Rev 3 127/3178 185 Embedded Flash memory (FLASH) 3.3.8 RM0433 Changing user option bytes The user option byte change operation can be used to modify the configuration and the protection settings saved as the Flash memory option byte area (see Table 10: List of Flash user option bytes for a detailed list). The Flash interface features two sets of option byte registers: • The first register set contains the current values of the option bytes.Their names has the _CUR extension. All “_CUR” registers are read-only. Their values are automatically loaded after power-on or after an option byte change operation. • The second register set allows modifying the option bytes. Their names contains the _PRG extension. All “_PRG” registers can be accessed in read/write mode. When the OPTLOCK bit in FLASH_OPTCR register is set, modifying the FLASH_OPTXX_PRG registers is forbidden. When OPTSTART bit is set to ‘1’, the Flash interface checks if at least one option byte needs to be programmed by comparing the current values (_CUR) with the new ones (_PRG). An option byte change operation is granted only if the following condition are met: • Current RDP is not level 2 (except for SWAP bit which can be changed whatever the level). • If a PCROP-protected area exists, then the new programmed area must be greater or equal to the current one (except during a regression level). • If a secure-protected area exists, then this area can be modified when the secure mode is set (see Section 4: Security memory management). • In case of level regression (change from level 1 to level 0), DMEP1/2 option bit can be set without limitations, otherwise it can only be set to ’1’. • DMES1/2 option bit can be modified in FLASH_SCAR_PRG1/2 only by simultaneously performing a level regression (change from level 1 to level 0), otherwise it can only be set to ’1’. • When the SECURITY option bit is set and a PCROP or secure area exists, the protection can be reset (SECURITY bit reset) by performing a level regression and programming the PCROP or secure area end and start addresses so that the difference is negative. If one of these conditions is not respected, the Flash interface sets the OPTCHANGEERR flag to ‘1’ in the FLASH_OPTSR_CUR register and aborts the option byte change operation. Option byte modification sequence To modify user option bytes, follow the procedure below: Note: 128/3178 1. Unlock OPTLOCK bit according to the specific sequence described inSection : Configuring the programming parameters. 2. Write the desired option byte value in the corresponding option registers: FLASH_XXX_PRG1/2. 3. Set the Options Start OPTSTART bit in the FLASH_OPTCR register. 4. Wait until OPT_BUSY bit is cleared. If a reset or a power-down occurs while the option byte modification is ongoing, the old option byte values are kept. A new option byte modification sequence is required to program the new values. DocID029587 Rev 3 RM0433 3.3.9 Embedded Flash memory (FLASH) Flash interface error flags The Flash interface reports when an error occurred during a program/erase operation. The user application can individually enable the interrupt for each error. Some errors need to be cleared before a new write starts. Each bank has a dedicated set of error flags in order to identify which bank generated the error: they are available in Flash Status register 1 or 2 (FLASH_SR1/2). Each error flag is associated to an interrupt enable bit in FLASH_CR1/2. When the interrupt enable bit is set to ‘1’, an interrupt is generated when the corresponding error flag is raised to ‘1’.To clear an error flag, set the corresponding bit in the FLASH_CCR1/2 register. Write protection error (WRPERR1/2) The WRPERR1/2 flag is a sticky bit which is set by hardware when the user application attempts to program/erase a protected area. When this flag is raised, the operation is aborted and nothing is changed. This flag is cleared by setting CLR_WRPERR1/2 bit in FLASH_CCR1/2 register to ‘1’. If WRPERRIE1/2 bit in FLASH_CR1/2 register is set to ‘1’, an interrupt is generated when WRPERR1/2 flag is raised. WRPERR1/2 must be cleared before starting a new write operation, otherwise a sequence error (PGSERR1/2 bit) is generated and the next program operation is aborted. Programming sequence error (PGSERR1/2) The PGSERR1/2 flag is a sticky bit which is set by hardware when the programming sequence is incorrect. This bit is set to ‘1’ when one of the following condition is met: • A write operation is requested by the AXI bus but PG1/2 bit has not yet been set. • The write protection error flag (WRPERR1/2) has not been reset and a new write operation is requested. • The inconsistency error (INCERR1/2) has not been reset and a new write operation is requested. • The Flash operation error (OPERR1/2) has not been reset and a new write operation is requested. When PGSERR1/2 flag is raised, the program operation is aborted. To clear this flag, set CLR_PGSERR1/2 bit in FLASH_CCR1/2 register to ‘1’. If PGSERRIE1/2 bit is set in FLASH_CR1/2, an interrupt is generated when PGSERR1/2 flag is raised. PGSERR1/2 must be cleared before starting a new write operation. Strobe error (STRBERR1/2) The STRBERR1/2 flag is a sticky bit which is set by hardware when the user application writes several times the same byte in the write buffer. The write operation is not aborted and the application can ignore the error, proceed with the current write operation and request new write operations. This flag is cleared by setting the CLR_STRBERR1/2 bit in FLASH_CCR1/2. If STRBERRIE1/2 bit is et in FLASH_CR1/2, an interrupt is generated when STRBERR1/2 flag is raised. It is not mandatory to clear STRBERR1/2 flag before starting a new write operation. DocID029587 Rev 3 129/3178 185 Embedded Flash memory (FLASH) RM0433 Inconsistency error (INCERR1/2) The INCERR1/2 flag is a sticky bit which is set by hardware in the following cases: • when the user application starts a write operation to a Flash word (with a first burst) and sends a new burst write to a different Flash word address before the ongoing write operation is complete. In this case, the write buffer is emptied, the new data are rejected and INCERR1/2 flag is raised. • when a master starts a write operation to a Flash word (with a first burst) and another master sends a new write burst to the same or a new Flash word address before the operation initiated by the first master is complete. In this case, the write buffer is emptied, the new data is rejected and INCERR1/2 flag is raised. • when a wrap burst issued by a master overlaps two or more Flash-word address (the maximum size of a wrap burst being limited to the Flash-word size, that is 256 bits). When the INCERR1/2 flag is raised, the operation is aborted and no write operation is executed. To clear this flag, set the CLR_INCERR1/2 bit in FLASH_CCR1/2 register. If INCERRIE1/2 bit in FLASH_CR register is set, an interrupt is generated when INCERR1/2 flag is raised. INCERR1/2 flag must be cleared before starting a new program or erase operation, otherwise a sequence error (PGSERR1/2 bit) is generated and the next program operation is aborted. Operation error (OPERR1/2) The OPERR1/2 flag is a sticky bit which is set by hardware when the Flash memory detects an error during a write or erase operation. This error may be caused by an incorrect Flash memory behavior due to cycling issues. To clear this flag, set to ‘1’ the CLR _OPERR1/2 bit in FLASH_CCR1/2 register. If OPERRIE1/2 bit in FLASH_CR1/2 register is ‘1’, an interrupt is generated when OPERR1/2 flag is raised. OPERR1/2 must be cleared before starting a new program operation, otherwise a sequence error (PGSERR1/2 bit) is generated and the new programming is aborted. 3.3.10 Simultaneous read/program/erase on bank1 and bank2 The Flash memory is divided into two independent banks. The Flash interface can drive different operations at the same time on each bank. A read, program or erase operation can be executed on bank 1 while another read, program or erase operation is executed on bank 2. An exception exists for option byte change when a level regression is required: in this case, the availability of both banks is needed. 130/3178 DocID029587 Rev 3 RM0433 3.3.11 Embedded Flash memory (FLASH) FLASH option bytes Option byte description The option bytes are configured by the end user depending on the application requirements.The user option bytes are accessible through the Flash interface registers interface. The programming sequence of option byte is described in Section : Option byte modification sequence. To increase the robustness of option byte storage in the Flash interface, each option byte data is associated to an error code correction (ECC) inside the Flash memory. Table 10 describes the list of all user option bytes available in the Flash interface registers. Table 10. List of Flash user option bytes User option Register(1) Size (bits) Default factory programmed value(2) SWAP_BANK FLASH_OPTSR_CUR 1 0x0 RDP FLASH_OPTSR_CUR 8 0xAA BOR_LEV FLASH_OPTSR_CUR 2 0x1 BOOT_ADD0 FLASH_BOOT_CURR 16 0x0800 BOOT_ADD1 FLASH_BOOT_CURR 16 0x1FF0 DMEP1 FLASH_PRAR_CUR1 1 0x0 DMES1 FLASH_SCAR_CUR1 1 0x0 WRPSn1 FLASH_WRP_CUR1R 8 0xFF PROT_AREA_START1 FLASH_PRAR_CUR1 12 0xFF PROT_AREA_END1 FLASH_PRAR_CUR1 12 0x00 SEC_AREA_START1 FLASH_SCAR_CUR1 12 0xFF SEC_AREA_END1 FLASH_SCAR_CUR1 12 0x00 DMEP2 FLASH_PRAR_CUR2 1 0x0 DMES2 FLASH_SCAR_CUR2 1 0x0 WRPSn2 FLASH_WPSN_CUR1R 8 0xFF PROT_AREA_START2 FLASH_PRAR_CUR2 12 0xFF PROT_AREA_END2 FLASH_PRAR_CUR2 12 0x00 SEC_AREA_START2 FLASH_SCAR_CUR2 12 0xFF SEC_AREA_END2 FLASH_SCAR_CUR2 12 0x00 IWDG1_HW FLASH_OPTSR_CUR 1 0x1 SECURITY FLASH_OPTSR_CUR 1 0x0 ST_RAM_SIZE FLASH_OPTSR_CUR 2 0x10 nRST_STBY_D1 FLASH_OPTSR_CUR 1 0x1 nRST_STOP_D1 FLASH_OPTSR_CUR 1 0x1 FZ_IWDG_SDBY FLASH_OPTSR_CUR 1 0x1 DocID029587 Rev 3 131/3178 185 Embedded Flash memory (FLASH) RM0433 Table 10. List of Flash user option bytes (continued) User option Register(1) Size (bits) Default factory programmed value(2) FZ_IWDG_STOP FLASH_OPTSR_CUR 1 0x1 PERSO_OK FLASH_OPTSR_CUR 1 0x1 IO_HSLV FLASH_OPTSR_CUR 1 0x0 1. Bit mapping and detailed bit description are available in Section 3.5: FLASH registers. 2. The default factory option bytes values are the default values before first option byte change. Option byte loading There are three ways to load Flash user option bytes: 1. At Power-on: The Flash interface automatically loads user option bytes from the Flash memory. During the loading sequence, the device remains under reset and the Flash interface is not accessible. 2. When D1 power domain, which contains the Flash interface, is switched from Standby mode to Run mode: In this case the Flash interface behaves as during a power-on sequence except that the device does not remain under reset. 3. When the user application modifies the option byte content through the Flash interface registers: In this case, after the Flash interface has reprogrammed the option byte sectors, an option byte reloading is done to update the Flash interface option registers. Rules for changing specific option bits Some of the option byte field must respect specific rules before being updated with new values. These fields, as well as the associated constraints, are described below: • Secure area size The secure area size is controlled by SEC_AREA_START1/2, SEC_AREA_END1/2 and DMES1/2 located in the FLASH_SCAR_CUR1/2 and FLASH_SCAR_PRG1/2 registers. These option bytes can be modified in secure mode. When the SEC_AREA_END1/2 field is lower than SEC_AREA_START1/2, the secure area size is null. If SEC_AREA_START1/2 = SEC_AREA_END1/2, all banks are secure protected. For more details refer to Section 4: Security memory management. • DMES1/2 When this option bit is set, the secure area is erased during a level regression (level 1 to level 0) or a bank erase with all protections removed, otherwise it is preserved. Resetting this bit can be done only when a level regression or a bank erase with all protections removed is requested at the same time. For more details refer to Section 4: Security memory management. • PCROP area size (execute-only) The PCROP area size is controlled by PROT_AREA_START1/2, PROT_AREA_END1/2 and DMEP1/2 in the FLASH_PRAR_CUR1/2 and FLASH_PRAR_PRG1/2 registers. Increasing the PCROP area can be done without any restriction. To reduce or remove the PCROP area, a level regression must be 132/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) requested at the same time. PCROP areas can be deleted by performing a bank erase with all protections removed. When the PROT_AREA_END1/2 field is lower than the PROT_AREA_START1/2 one, the PCROP area size is null. If PROT_AREA_START1/2 = PROT_AREA_END1/2, all banks are PCROP protected. For more details refer to Section 4: Security memory management. • DMEP1/2 When this bit is set, the PCROP area is erased during a level regression or a bank erase with all protections removed. When it is not set, the PCROP area is preserved during a level regression (level 1 to level 0). There are no restriction in setting this bit. However, resetting this bit can only be done when a level regression or a bank erase is requested at the same time. • • Readout protection (RDP) – When RDP is set to level 2, there is no way to return to a lower level. If the user application attempts to perform such an operation, an error is raised and the required change is ignored. – When the RDP is set to level 1, RDP option byte modification is allowed without any restriction if the user application requests to switch to RDP level 2. – However switching from level1 to level 0 leads to a Flash mass erase if DMES1/2 in FLASH_SCAR_CUR1/2 and DMEP1/2 bit in FLASH_PRAR_CUR1/2 are set to 1’ for the corresponding bank. – If the user application wants to keep the PCROP area or the secure area during a level regression, DMEP1/2 or DMES1/2 bit must have been set to ‘0’ prior to performing the level regression. – When RDP is set to level 0, switching to level 1 or level 2 is possible without any restriction. Sector Write Protection (WRPSn1/2) No specific rules. • Security mode (SECURITY) Setting this option bit activates the device security mode. This bit can be cleared when no Secure or PCROP areas exist, otherwise a level regression or a Security boot service must be executed to reset this bit. For more details please refer to Section 4: Security memory management. • ST_RAM_SIZE The value of this option byte can be increased without any restriction. Decreasing this value is only authorized through root secure services. This option is effective only when the SECURITY option byte is set. For more details please refer to Section 4: Security memory management. 3.3.12 Protection mechanisms The Flash interface implements different protection mechanisms: • Readout protection (RDP) • PCROP (Proprietary code readout protection): execute-only area • Secure protection • Sector write protection. DocID029587 Rev 3 133/3178 185 Embedded Flash memory (FLASH) RM0433 RDP (Readout protection) A Flash user area can be protected against read operations by an untrusted code. Three read protection levels exist (refer to Table 11: RDP value vs readout protection level, Table 12: Allowed accesses versus Readout protection level and Figure 6: Protection transition scheme): • Level 0: no read protection When the read protection level is set to level 0 by writing 0xAA into the read protection option byte (RDP), all read/program operations (if no others protections are set) from/to the Flash memory or the backup SRAM are possible whatever the boot configuration (Flash user boot, debug or boot from RAM). • Level 1 The read protection level 1 is activated by writing any value (except for 0xAA and 0xCC used to set level 0 and level 2, respectively) into the RDP option byte. When the read protection level 1 is set: • – No access (read, erase, program) to Flash memory or backup SRAM can be performed when the debugger is connected or when the boot configuration is different from user Flash. A bus error is generated when a read access to the Flash memory is requested. – When booting from Flash memory (no debugger connected), read, erase and program accesses from/to Flash memory and backup SRAM from user code are allowed. – When level 1 is active, programming the protection option byte to level 0 (RDP level regression) causes the Flash memory and the backup SRAM to be masserased. As a result the user Flash memory area and backup SRAM are cleared before the RDP level is set to level 0. The mass erase will delete the content of both banks and backup SRAM as well as preserve the Flash PCROP and Secure areas if the DMEP1/2 and DMES1/2 bits are to ‘0’. Level 2: debug disabled and RDP enabled The read protection level 2 is activated by writing 0xCC to the RDP option byte. When the read protection level 2 is set: Note: 134/3178 – All protections provided by level 1 are active. – Booting from RAM is no more allowed. – When security is enabled, the boot is forced in the secure System Flash memory (see Section 4: Security memory management). – Booting from System Flash memory is no more allowed, excepted when the security is enabled. The boot is forced in the secure System Flash (see Section 4: Security memory management). – All Debug features are disabled. – User option bytes can no longer be changed except for the SWAP bit (see Section 3.3.13: Flash bank swapping). – When booting from Flash memory, read, erase and program accesses to Flash memory and backup SRAM from user code are allowed. Memory read protection level 2 is an irreversible operation. When level 2 is activated, the level of protection cannot be decreased to level 0 nor level 1. The JTAG port is permanently disabled when level 2 is active (acting as a JTAG fuse). As a consequence, STMicroelectronics is not able to perform analysis on the defective parts on which the level 2 protection has been set. DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Table 11. RDP value vs readout protection level RDP option byte value Readout protection level 0xAA level 0 0xCC level 2 Any other value level 1 Table 12. Allowed accesses versus Readout protection level Area Protection level (RDP) Boot = user Flash memory (1) Boot /= user Flash memory or Debug connected 1 R/W/E No Access 2 R/W/E -(2) 1 R R 2 R -(2) 1 R/W/E R/W/E 2 R -(2) 1 R/W No Access 2 R/W -(2) User Flash memory System Flash memory Option bytes Backup SRAM 1. W: Write, R: Read, E: Erase. 2. When RDP = Level 2, no Debug feature is available, no other Boot than User Flash is possible, modification of option bytes is not allowed excepted for the SWAP bit field. Figure 6. Protection transition scheme :ULWH 5'3 ;$$DQG 5'3 [&& :ULWH 5'3 [&& /HYHO 5'3 [&& /HYHO 5'3[$$ 5'3[&& GHIDXOW :ULWH 5'3 [&& :ULWH 5'3 [$$ 0DVVHUDVH /HYHO 5'3 [$$ :ULWH 5'3 [$$ 5'3,QFUHDVH 5'35HJUHVVLRQ 5'38QFKDQJHG 06Y 9 DocID029587 Rev 3 135/3178 185 Embedded Flash memory (FLASH) RM0433 PCROP area (proprietary code readout protection, execute-only area) The Flash interface allows defining an “executable-only” area in each Flash bank. This area permits only instruction fetch transactions. No data access (data or literal pool) is allowed. The native code must be compiled accordingly with “execute-only” option. The execute-only area helps protecting software intellectual property. Two different PCROP regions can be defined (one per Flash bank) by setting the PROT_AREA_END1/2 and PROT_AREA_START1/2 option bytes so that the resulting difference is positive and not null (END address higher than START address). The minimum PCROP area that can be set is 16 Flash words, that is 512 bytes. The maximum execute-only area that can be set is the whole Flash bank area. This is done by setting PROT_AREA_END1/2 and PROT_AREA_START1/2 fields to the same value. The PCROP area can be defined with a granularity of eight Flash words. In others words, the difference between END and START addresses incremented by one and multiplied by eight represents the number of Flash words that are PCROP configured, assuming PROT_AREA_END1/2 is strictly higher than PROT_AREA_START1/2. To disable any of the two PCROP areas, the PROT_AREA_END1/2 address field must be set to a lower value than PROT_AREA_START1/2, meaning that the resulting difference is negative (END address lower than START address). For example, to set a PCROP area from address 0x08000000 (included) to address 0x08000FFF (included), corresponding to 4 Kbytes starting from the bank 1 base address of the first bank, PROT_AREA_START1 and PROT_AREA_END1 registers must be respectively programmed to: • PROT_AREA_START1 = 0x000 • PROT_AREA_END1 = 0x00F The protected area size is equal to: [(PROT_AREA_END - PROT_AREA_START) + 1] x 256 = 16 x 256 bytes = 4 Kbytes. PCROP area properties • Read (not fetch) transaction performed from a PCROP area will raise the RDPERR flag in the FLASH_SR1/2 register. • Write transaction performed to a PCROP area will raise the WRPERR flag in the FLASH_SR1/2 register. • When a PCROP area is already defined, the area size can still be increased either by reducing the START address, or by increasing the END address field. Two sequences can be used to disable the PCROP area: – Perform an RDP level regression (level 1 to level 0), enable the DMEP1/2 bit and set the PROT_AREA_START1/2 to a value higher than PROT_AREA_END1/2 in the FLASH_PRAR_PRG1/2 registers. PCROP protection is independent from the RDP protection. However, in this case, prior to removing PCROP, RDP should be first set to level 1 to enable a RDP level regression. – 136/3178 Request a bank erase operation while enabling at the same time DMEP1/2, DMES1/2 and all WRPSn1/2 bits to ‘1’, set the PROT_AREA_START1/2 higher than PROT_AREA_END1/2 in the FLASH_PRAR_PRG1/2 and SEC_AREA_START1/2 higher than SEC_AREA_END1/2 in FLASH_SCAR_PRG1/2. DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Secure area The Flash interface allows setting a “secure” area in each Flash bank. The data and program stored in this area cannot be accessed unless the secure mode is set. The secure area helps isolating secure user code from application non-secure code. For example, the secure area can be used to protect a secure firmware upgrade code, a secure boot code. Two different secure regions can be defined (one per Flash bank) by setting the SEC_AREA_END1/2 and SEC_AREA_START1/2 option bytes so that the resulting difference is positive and not null (END address higher than START address). Please note that these option bytes can be modified only in secure mode (see Section 4: Security memory management). The size of the smaller secure area that can be set is 512 bytes. The maximum secure area size is the whole Flash bank. This can be done by setting SEC_AREA_END1/2 and SEC_AREA_START1/2 fields to the same value. The secure area can be defined with a granularity of eight Flash words. In others words, the difference between the END and START addresses incremented by one and multiplied by eight represents the number of Flash words that are secure protected, assuming SEC_AREA_END1/2 is strictly higher than SEC_AREA_START1/2. To disable any of the two secure areas, the SEC_AREA_END1/2 address field must be set to a value lower than SEC_AREA_START1/2, meaning that the resulting difference is negative (END address lower than START address). For example, to set a Secure area from the address 0x08100000 (included) to address 0x08101FFF (included), corresponding to 8 Kbytes starting from the second bank base address, SEC_AREA_START2 and SEC_AREA_END2 registers must be respectively programmed to: • SEC_AREA_START2 = 0x000 • SEC_AREA_END2 = 0x01F The secure area size is equal to: [(SEC_AREA_END2 - SEC_AREA_START2) + 1] x 256 = 32 x 256 bytes = 8 Kbytes. Secure area properties • The secure area size can be modified when security is enabled and under specific conditions (see Section 4: Security memory management). Two solutions are possible to delete a secure area: – Perform an RDP level regression (level 1 to level 0), enable the DMES1/2 bit and set the SEC_AREA_START1/2 address to a value higher than SEC_AREA_END1/2 in the FLASH_SCAR_PRG1/2 registers. RDP protection is independent from the secure protection. However, in this case, prior to removing RDP, RDP should be first set to level 1 to enable a RDP level regression. – Request a bank erase operation, set at the same time DMEP1/2, DMES1/2 and all WRPSn1/2 bits to ‘1’. and configure the SEC_AREA_START1/2 address to a value higher than SEC_AREA_END1/2 in the FLASH_SCAR_PRG1/2 and PROT_AREA_START1/2 higher than PROT_AREA_END1/2 in FLASH_PRAR_PRG1/2. For more details on how to use the security aspects of the device and how to enable/disable user secure mode, refer to Section 4: Security memory management. DocID029587 Rev 3 137/3178 185 Embedded Flash memory (FLASH) RM0433 Sector write protection The purpose of the sector write protection is to protect Flash memory against unwanted modifications of the non-volatile code and/or data. Any Flash sector can be independently write-protected or unprotected by clearing/setting the corresponding WRPSn1/2 bit in the FLASH_WPSN_PRG1/2R register. A write-protected sector can neither be erased nor programmed. As a result, a bank erase cannot be performed if one bank sector is write-protected, unless the bank erase is done in the scope of a level regression. In this case, the bank erase is transformed into a sequence of sector erase operations since only unprotected sectors are erased. Sector write protection bits (user options) can be modified without restrictions when RDP level is set to level 0 or level 1. When level 2 is set, it is no more possible to change the write protection bitfield in the option bytes. Note: By default, a PCROP area is also write-protected. As a result, a sector that partly or entirely belongs to a PCROP area cannot be erased nor programmable. 3.3.13 Flash bank swapping The Flash interface allows swapping bank 1 and bank 2 memory mapping. This feature can be used after a firmware upgrade to restart the device on the new firmware after a system reset. Bank swapping is controlled by the SWAP_BANK bit located in the FLASH_OPTCR register. Table 13 gives the accessible memory map from both AXI slave Flash interfaces depending on SWAP_BANK option bit configuration. Table 13. AXI interfaces memory mapping SWAP_BANK = ‘0’ Area AXI 1 AXI 2 User Sector Bank 1 Yes(1) No User Sector Bank 2 No Yes(1) System Flash Bank 1 Yes(2) No System Flash Bank 2 No Yes(2) 1. User Bank 1 and 2 are mapped from 0x0800 0000 to 0x080F FFFF and from 0x0810 0000 to 0x081F FFFF, respectively. 2. System Flash Bank 1 and 2 are mapped from 0x1FF0 0000 to 0x1FF1 FFFF and from 0x1FF4 0000 to 0x1FF5 FFFF, respectively. Table 14. AXI interfaces memory mapping SWAP_BANK = ‘1’ Area AXI 1 AXI 2 Yes(1) User Sector Bank 1 No User Sector Bank 2 Yes(1) No (2) System Flash Bank 1 Yes No System Flash Bank 2 No Yes(2) 1. User Bank 1 and 2 are mapped from 0x0810 0000 to 0x081F FFFF and from 0x0800 0000 to 0x080F FFFF, respectively. 2. System Flash Bank 1 and 2 are mapped from 0x1FF0 0000 to 0x1FF1 FFFF and from 0x1FF4 0000 to 0x1FF5 FFFF, respectively. 138/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) When modifying the SWAP_BANK_OPT bit in the FLASH_OPTSR_PRG register, the new value is taken into account only when the option bytes have been reloaded from the option byte sector into the FLASH_OPTSR_CUR register and its value copied to the SWAP_BANK bit of the FLASH_OPTCR register after system reset. Table 15. Bank swapping sequence 8SGDWHQHZ):LQ )ODVK%DQN 2SWLRQE\WH SURJUDPLQJ 6HW8QVHW 6:$3B%$1.B237RSWLRQ ELW,Q)/$6+B23765B35* :ULWH67$57ELWLQ )/$6+B237&57RVWDUW RSWLRQE\WHFKDQJH VHTXHQFH )/$6+B23765B35* 6:$3 %$1. 237 )/$6+B23765B&85 6:$3 %$1. 237 6\VWHPUHVHW 0DNHV\VWHPUHVHW !6:$3B%$1.RI )/$6+B23765B&85LV FRSLHGWR 6:$3B%$1.B237ELWLQ )/$6+B237&5 )/$6+ 190 2SWLRQE\WH UHORDG )/$6+B237&5 6:$3 %$1. 67$57 /2&. 6:$3ORJLF )/$6+ ,17(5)$&( 6:$3LVHIIHFWLYH !([HFXWLRQRI QHZ): %DQN %DQN 06Y 9 Below the recommended sequence to swap bank 1 and bank 2 memory mapping after a firmware update: 1. Update bank 2 or bank 1 with the new firmware. 2. Modify SWAP_BANK_OPT bit accordingly in the FLASH_OPTSR_PRG register. 3. Start the Option byte change sequence by setting the OPTSTART bit in the FLASH_OPTCR register. Make sure that the register has been unlocked prior to programming it. 4. Perform a system reset. After the option byte loading sequence, the bank swap is effective and the new firmware shall be executed. DocID029587 Rev 3 139/3178 185 Embedded Flash memory (FLASH) RM0433 Note: The SWAP_BANK_OPT option bit in FLASH_OPTSR_PRG can be modified whatever the RDP level, even in level 2, thus allowing advanced firmware upgrade in any level of readout protection. 3.4 FLASH interrupts As explained in Section 3.3.9: Flash interface error flags, each flag error can generate an interrupt if the corresponding interrupt enable bit has been set in the FLASH_CR1/2 register. The End of Operation (EOP1/2) bit in the FLASH_SR1/2 register is set when an erase, program or option change operation has successfully completed. Setting the End of Operation Interrupt Enable bit (EOPIE1/2) in the FLASH_CR1/2 register enables the generation of an interrupt when the erase, program or option change operation has completed. The EOP1/2 flag can be cleared by writing the corresponding bit in the FLASH_FCCR1/2 register. 3.5 FLASH registers 3.5.1 FLASH access control register (FLASH_ACR) Address offset: 0x000 or 0x100 Reset value: 0x0000 0037 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRHIGH FREQ rw 140/3178 DocID029587 Rev 3 rw Res. LATENCY rw rw rw RM0433 Embedded Flash memory (FLASH) Bits 31:6 Reserved, must be kept at reset value. Bits 5:4 WRHIGHFREQ: Flash signal delay These bits are used to control the delay between Flash signals during programming operations. The user has to write the correct value depending on the Flash interface frequency (see Table 7). No check is performed to verify that the configuration is correct. 00: ≤ 85 MHz 01: ≤ 185 MHz 10: ≤ 285 MHz 11: ≤ 385 MHz Bit 3 Reserved, must be kept at reset value. Bits 2:0 LATENCY: Read latency The value of these bits specifies the number of wait states that will be used during read operations on both Flash memory banks. The user has to write the correct value depending on the Flash memory interface frequency and power operating mode as explained in Table 7. No check is performed to verify that the configuration is correct. 000: zero wait states used to read a word from Flash memory 001: one wait state used to read a word from Flash memory ... 111: 7 wait states used to read from Flash memory 3.5.2 FLASH key register for bank 1 (FLASH_KEYR1) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR1 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w KEYR1 w w w w w w w w Bits 31:0 KEYR1: Bank 1 access configuration unlock key FLASH_KEYR1 is a write-only register. The following values must be programmed consecutively to unlock FLASH_CR1 register and allow programming/erasing it: a) 1st key = 0x4567 0123 b) 2ndkey = 0xCDEF 89AB For more details, refer to Section : Configuring the programming parameters. DocID029587 Rev 3 141/3178 185 Embedded Flash memory (FLASH) 3.5.3 RM0433 FLASH option key register (FLASH_OPTKEYR) Address offset: 0x008 or 0x108 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OPTKEYR w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w OPTKEYR w w w w w w w w w Bits 31:0 OPTKEYR: Unlock key option bytes FLASH_OPTKEYR is a write-only register. The following values must be programmed consecutively to unlock FLASH_OPTCR register and allow programming/erasing it as well as all _PRG registers: a) 1st key = 0x0819 2A3B b) 2nd key= 0x4C5D 6E7F For more details, see Section : Configuring the programming parameters. 3.5.4 FLASH control register for bank 1 (FLASH_CR1) Address offset: 0x00C Reset value: 0x0000 0031 Res. Res. Res. Res. rw rw rw rw rw 10 9 8 7 6 5 rw rw 15 14 13 12 11 Res. Res. Res. Res. rw 142/3178 SNB1 rw rw rw DocID029587 Rev 3 4 PSIZE1 rw CRC_EN rw rw rw EOPIE1 Res. rw rw rw rw 3 2 1 0 LOCK1 16 WRPERRIE1 17 PG1 18 PGSERRIE1 19 SER1 20 STRBERRIE1 21 BER1 22 INCERRIE1 23 OPERRIE1 24 FW1 25 RDPERRIE1 26 START1 27 RDSERRIE1 28 SNECCERRIE1 29 DBECCERRIE1 30 CRCENDIE1 31 rw rw rw rs RM0433 Embedded Flash memory (FLASH) Bits 31:28 Reserved, must be kept at reset value. Bit 27 CRCENDIE1: Bank 1 end of CRC calculation interrupt enable bit When CRCENDIE1 bit is set to ’1’, an interrupt is generated when the CRC computation has completed on bank 1. CRCENDIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when CRC computation complete on bank 1 1: interrupt generated when CRC computation complete on bank 1 Bit 26 DBECCERRIE1: Bank 1 ECC double detection error interrupt enable bit When DBECCERRIE1 bit is set to ‘1’, an interrupt is generated when an ECC double detection error occurs during a read operation from bank 1. DBECCERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when an ECC double detection error occurs on bank 1 1: interrupt generated if an ECC double detection error occurs on bank 1 Bit 25 SNECCERRIE1: Bank 1 ECC single correction error interrupt enable bit When SNECCERRIE1 bit is set to ‘1’, an interrupt is generated when an ECC single correction error occurs during a read operation from bank 1. SNECCERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when an ECC single correction error occurs on bank 1 1: interrupt generated when an ECC single correction error occurs on bank 1 Bit 24 RDSERRIE1: Bank 1 secure error interrupt enable bit When RDSERRIE1 bit is set to ‘1’, an interrupt is generated when a secure error (access to a secure protected address without the appropriate rights) occurs during a read operation from bank 1. RDSERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a secure error occurs on bank 1 1: an interrupt is generated when a secure error occurs on bank 1 Bit 23 RDPERRIE1: Bank 1 read protection error interrupt enable bit When RDPERRIE1 bit is set to ‘1’, an interrupt is generated when a read protection error occurs (access to an address protected by PCROP) during a read operation from bank 1. RDPERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a read protection error occurs on bank 1 1: an interrupt is generated when a read protection error occurs on bank 1 Bit 22 OPERRIE1: Bank 1 write/erase error interrupt enable bit When OPERRIE1 bit is set to ‘1’, an interrupt is generated when an error is detected during a write/erase operation to bank 1. OPERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a write/erase error occurs on bank 1 1: interrupt generated when a write/erase error occurs on bank 1 Bit 21 INCERRIE1: Bank 1 inconsistency error interrupt enable bit When INCERRIE1 bit is set to ‘1’, an interrupt is generated when an inconsistency error occurs during a write operation to bank 1. INCERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a inconsistency error occurs on bank 1 1: interrupt generated when a inconsistency error occurs on bank 1. Bit 20 Reserved, must be kept at reset value. DocID029587 Rev 3 143/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 19 STRBERRIE1: Bank 1 strobe error interrupt enable bit When STRBERRIE1 bit is set to ‘1’, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation to bank 1. STRBERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a strobe error occurs on bank 1 1: interrupt generated when strobe error occurs on bank 1. Bit 18 PGSERRIE1: Bank 1 programming sequence error interrupt enable bit When PGSERRIE1 bit is set to ‘1’, an interrupt is generated when a sequence error occurs during a program operation to bank 1. PGSERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a sequence error occurs on bank 1 1: interrupt generated when sequence error occurs on bank 1. Bit 17 WRPERRIE1: Bank 1 write protection error interrupt enable bit When WRPERRIE1 bit is set to ‘1’, an interrupt is generated when a protection error occurs during a program operation to bank 1. WRPERRIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated when a protection error occurs on bank 1 1: interrupt generated when a protection error occurs on bank 1. Bit 16 EOPIE1: Bank 1 end-of-program interrupt control bit Setting EOPIE1 bit to ‘1’ enables the generation of an interrupt at the end of a program operation to bank 1. EOPIE1 can be programmed only when LOCK1 is set to ‘0’. 0: no interrupt generated at the end of a program operation to bank 1. 1: interrupt enabled when at the end of a program operation to bank 1. Bit 15 CRC_EN: Bank 1 CRC control bit Setting CRC_EN bit to ‘1’ enables the CRC calculation on bank 1. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR1 register. When CRC calculation is performed on bank 1, it can only be disabled by setting CRC_EN bit to ‘0’. Resetting CRC_EN resets the content of FLASH_CRCDATAR register. CRC_EN can be programmed only when LOCK1 is set to ‘0’. Bits 14:11 Reserved, must be kept at reset value. Bits 10:8 SNB1: Bank 1 sector erase selection number These bits are used to select the target sector for a sector erase operation. SNB1 can be programmed only when LOCK1 is set to ‘0’. 000: sector 0 of bank 1 001: sector 1 of bank 1 ... 111: sector 7 of bank 1 Bit 7 START1: Bank 1 bank or sector erase start control bit START1 bit is used to start a sector erase or a bank erase operation. START1 can be programmed only when LOCK1 is set to ‘0’. The Flash memory interface resets START1 when the corresponding operation has been acknowledged. The user application cannot access any Flash register until the operation has been acknowledged. 144/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 6 FW1: Bank 1 write forcing control bit FW1 forces a write operation even if the write buffer is not full. FW1 can be programmed only when LOCK1 is set to ‘0’. The Flash memory interface resets FW1 when the corresponding operation has been acknowledged. The user application cannot access any Flash register until the operation has been acknowledged. Write forcing is effective only if the write buffer is not empty (in particular, FW1 will not start several write operations when the write operations are performed consecutively). Bits 5:4 PSIZE1: Bank 1 program size PSIZE1 selects the parallelism used by the Flash memory during write and erase operations to bank 1 (refer to Section : Configuring the programming parameters for details). PSIZE1 can be programmed only when LOCK1 is set to ‘0’. 00: programming executed with byte parallelism 01: programming executed with half-word parallelism 10: programming executed with word parallelism 11: programming executed with double word parallelism Bit 3 BER1: Bank 1 erase request Setting BER1 bit to ‘1’ requests a bank erase operation on bank 1. BER1 can be programmed only when LOCK1 is set to ‘0’. BER1 has a higher priority than SER1: if both are set, the Flash memory interface executes a bank erase (for more details, see Section : Standard Flash bank erase). 0: bank erase not requested on bank 1 1: bank erase requested on bank 1 Bit 2 SER1: Bank 1 sector erase request Setting SER1 bit to ‘1’ requests a sector erase on bank 1. SER1 can be programmed only when LOCK1 is set to ‘0’. BER1 has a higher priority than SER1: if both are set, the Flash memory interface executes a bank erase (for more details, see Section : Flash sector erase). 0: sector erase not requested on bank 1 1: sector erase requested on bank 1 Bit 1 PG1: Bank 1 program enable bit Setting PG1 bit to ‘1’ enables write operations to bank 1. This allows preparing program operations even if a sector or bank erase is ongoing. PG1 can be programmed only when LOCK1 is set to ‘0’. When PG1 is reset, the internal buffer is disabled for write operations to bank 1, and all the data stored in the buffer but not yet programmed are lost. Bit 0 LOCK1: Bank 1 configuration lock bit This bit locks the FLASH_CR1 register. When the FLASH_CR1 register is unlocked, LOCK1 bit is automatically reset (see Section : Configuring the programming parameters). If a wrong sequence is executed, this bit remains locked until next system reset. LOCK1 can be set by programming it to ‘1’. When set to ‘1’, a new unlock sequence is mandatory to unlock it. When LOCK1 changes from ‘0’ to ‘1’, the other bits of FLASH_CR1 register do not change. 0: FLASH_CR1 register unlocked 1: FLASH_CR1 register locked DocID029587 Rev 3 145/3178 185 Embedded Flash memory (FLASH) 3.5.5 RM0433 FLASH status register for bank 1 (FLASH_SR1) Address offset: 0x010 Reset value: 0x0000 0000 20 19 18 17 16 Res. Res. Res. Res. Res. r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BSY1 r WBNE1 r QW1 r CRC_BUSY1 r EOP1 21 WRPERR1 22 PGSERR1 23 STRBERR1 24 INCERR1 25 OPERR1 26 RDPERR1 27 RDSERR1 28 SNECCERR1 29 DBECCERR1 30 CRCEND1 31 r r r r Bits 31:28 Reserved, must be kept at reset value. Bit 27 CRCEND1: Bank 1 CRC-complete flag CRCEND1 bit is raised when the CRC computation has completed on bank 1. An interrupt is generated if CRCENDIE1 is set to ‘1’. It is not necessary to reset CRCEND1 before restarting CRC computation. Writing ‘1’ to CLR_CRCEND1 bit in FLASH_CCR1 register clears CRCEND1. 0: CRC computation not complete on bank 1 1: CRC computation complete on bank 1 Bit 26 DBECCERR1: Bank 1 ECC double detection error flag DBECCERR1 flag is raised when an ECC double detection error occurs during a read operation from bank 1. An interrupt is generated if DBECCERRIE1 is set to ‘1’. Writing ‘1’ to CLR_DBECCERR1 bit in FLASH_CCR1 register clears DBECCERR1. 0: no ECC double detection error occurs on bank 1 1: ECC double detection error occurs on bank 1 Bit 25 SNECCERR11: Bank 1 single correction error flag SNECCERR1 flag is raised when an ECC single correction error occurs during a read operation from bank 1. An interrupt is generated if SNECCERRIE1 is set to ‘1’. Writing ‘1’ to CLR_SNECCERR1 bit in FLASH_CCR1 register clears SNECCERR1. 0: no ECC single correction error occurs on bank 1 1: ECC single correction error occurs on bank 1 Bit 24 RDSERR1: Bank 1 secure error flag RDSERR1 flag is raised when a secure error (access to a secure protected word without the appropriate rights) occurs on bank 1. An interrupt is generated if RDSERRIE1 is set to ‘1’. Writing ‘1’ to CLR_RDSERR1 bit in FLASH_CCR1 register clears RDSERR1. 0: no secure error occurs on bank 1 1: a secure error occurs on bank 1 146/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 23 RDPERR1: Bank 1 read protection error flag RDPERR1 flag is raised when an read protection error (access to a PCROP-protected word) occurs on bank 1. An interrupt is generated if RDPERRIE1 is set to ‘1’. Writing ‘1’ to CLR_RDPERR1 bit in FLASH_CCR1 register clears RDPERR1. 0: no read protection error occurs on bank 1 1: a read protection error occurs on bank 1 Bit 22 OPERR1: Bank 1 write/erase error flag OPERR1 flag is raised when an error occurs during a write/erase to/from bank 1. An interrupt is generated if OPERRIE1 is 1 set to ‘1’. Writing ‘1’ to CLR_OPERR1 bit in FLASH_CCR1 register clears OPERR1. 0: no write/erase error occurs on bank 1 1: a write/erase error occurs on bank 1 Bit 21 INCERR1: Bank 1 inconsistency error flag INCERR1 flag is raised when a inconsistency error occurs on bank 1. An interrupt is generated if INCERRIE1 is set to ‘1’. Writing ‘1’ to CLR_INCERR1 bit in the FLASH_CCR1 register clears INCERR1. (refer to Section 3.3.9: Flash interface error flags). 0: no inconsistency error occurs on bank 1 1: a inconsistency error occurs on bank 1 Bit 20 Reserved, must be kept at reset value. Bit 19 STRBERR1: Bank 1 strobe error flag STRBERR1 flag is raised when a strobe error occurs on bank 1 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE1 bit is set to ‘1’. Writing ‘1’ to CLR_STRBERR1 bit in FLASH_CCR1 register clears STRBERR1. 0: no strobe error occurs on bank 1 1: a strobe error occurs on bank 1 Bit 18 PGSERR1: Bank 1 programming sequence error flag PGSERR1 flag is raised when a sequence error occurs on bank 1. An interrupt is generated if the PGSERRIE1 bit is set to ‘1’. Writing ‘1’ to CLR_PGSERR1 bit in FLASH_CCR1 register clears PGSERR1. 0: no sequence error occurs on bank 1 1: a sequence error occurs on bank 1 Bit 17 WRPERR1: Bank 1 write protection error flag WRPERR1 flag is raised when a protection error occurs during a program operation to bank 1. An interrupt is also generated if the EOPIE1 is set to ‘1’. Writing ‘1’ to CLR_EOP1 bit in FLASH_CCR1 register clears WRPERR1. 0: no protection error occurs on bank 1 1: a protection error occurs on bank 1 Bit 16 EOP1: Bank 1 end-of-program flag EOP1 flag is set when a programming operation to bank 1 completes. An interrupt is generated if the EOPIE1 is set to ‘1’. It is not necessary to reset EOP1 before starting a new operation. EOP1 bit is cleared by writing ‘1’ to CLR_EOP1 bit in FLASH_CCR1 register. 0: no programming operation completed on bank 1 1: a programming operation completed on bank 1 Bits 15:4 Reserved, must be kept at reset value. DocID029587 Rev 3 147/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 3 CRC_BUSY1: Bank 1 CRC busy flag CRC_BUSY1 flag is set when a CRC calculation is ongoing on bank 1. This bit cannot be forced to ‘0’. The user must wait until the CRC calculation has completed or disable CRC computation on bank 1. 0: no CRC calculation ongoing on bank 1 1: CRC calculation ongoing on bank 1 Bit 2 QW1: Bank 1 wait queue flag QW1 flag is set when a program operation to bank 1 is in the waiting queue. It is not possible to know what type of programming operation is in the queue. When all program operations have been executed and thus removed from the waiting queue, this flag is reset by hardware. This bit cannot be forced to ‘0’. It is reset after a deterministic time if no other operations are requested. 0: no program operations waiting in the operation queue of bank 1 1: at least one programming operation is waiting in the operation queue of bank 1 Bit 1 WBNE1: Bank 1 write buffer not empty flag WBNE1 flag is set when bank 1 write buffer is not empty and the Flash memory interface is waiting for new data to complete it. WBNE1 is reset by hardware each time the write buffer is emptied. This happens when one of the following event occurs: – the write buffer is full – the user forces the write operation – an error that involves data loss – the write operation has been disabled. This bit cannot be forced to ‘0’. To reset it, clear the write buffer by performing any of the above listed actions. 0: write buffer of bank 1 empty 1: write buffer of bank 1 waiting data to complete Bit 0 BSY1: Bank 1 ongoing program flag BSY1 flag is set when a program operation to bank 1 is ongoing. It is not possible to know what type of program operation is ongoing. BSY1 cannot be forced to ‘0’. It is reset by hardware when the operation completes, provided no other program operation starts. 0: no programming operation executing on bank 1 1: programming operation executing on bank 1. 148/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.6 FLASH clear control register for bank 1 (FLASH_CCR1) Address offset: 0x014 Reset value: 0x0000 0000 20 19 18 17 16 Res. Res. Res. Res. Res. w w w w w w w CLR_EOP1 21 CLR_WRPERR1 22 CLR_PGSERR1 23 CLR_STRBERR1 24 CLR_INCERR1 25 CLR_OPERR1 26 CLR_RDPERR1 27 CLR_RDSERR1 28 CLR_SNECCERR1 29 CLR_DBECCERR1 30 CLR_CRCEND1 31 w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Bits 31:28 Reserved, must be kept at reset value. Bit 27 CLR_CRCEND1: Bank 1 CRCEND1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ CRCEND1 flag of FLASH_SR1 register. Bit 26 CLR_DBECCERR1: Bank 1 DBECCERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ DBECCERR1 flag of FLASH_SR1 register. If the SNECCERR1 flag of FLASH_SR1 register is set to ‘0’, FLASH_ECC_FA1R register are reset to ‘0’ as well. Bit 25 CLR_SNECCERR1: Bank 1 SNECCERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ SNECCERR1 flag of FLASH_SR1 register. If the DBECCERR1 flag of FLASH_SR1 register is set to ‘0’, FLASH_ECC_FA1R register are reset to ‘0’ as well. Bit 24 CLR_RDSERR1: Bank 1 RDSERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ RDSERR1 flag of FLASH_SR1 register. Bit 23 CLR_RDPERR1: Bank 1 RDPERR1 flag clear bit Setting this bit to 1’ resets to ‘0’ RDPERR1 flag of FLASH_SR1 register. Bit 22 CLR_OPERR1: Bank 1 OPERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ OPERR1 flag of FLASH_SR1 register. Bit 21 CLR_INCERR1: Bank 1 INCERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ INCERR1 flag of FLASH_SR1 register. Bit 20 Reserved, must be kept at reset value. Bit 19 CLR_STRBERR1: Bank 1 STRBERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ STRBERR1 flag of FLASH_SR1 register. Bit 18 CLR_PGSERR1: Bank 1 PGSERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ PGSERR1 flag of FLASH_SR1 register. DocID029587 Rev 3 149/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 17 CLR_WRPERR1: Bank 1 WRPERR1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ WRPERR1 flag of FLASH_SR1 register. Bit 16 CLR_EOP1: Bank 1 EOP1 flag clear bit Setting this bit to ‘1’ resets to ‘0’ EOP1 flag of FLASH_SR1 register. Bits 15:0 Reserved, must be kept at reset value. 3.5.7 FLASH option control register (FLASH_OPTCR) Address offset: 0x018 or 0x118 Reset value: 0x0000 0001 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OPTLOCK 27 OPTSTART 28 MER 29 OPTCHANGEERRIE 30 SWAP_BANK 31 rw rs w Bit 31 SWAP_BANK: Bank swapping configuration bit SWAP_BANK controls whether the bank 1 and bank 2 are swapped or not. After option byte loading, this bit is loaded with the SWAP_BANK_OPT bit of FLASH_OPTSR_CUR register. When the FLASH_OPTCR register is unlocked (OPTLOCK = ‘0’), the master can modify SWAP_BANK to swap/unswap user Flash memory banks (see Section 3.3.13: Flash bank swapping). 0: bank 1 and bank 2 not swapped 1: bank 1 and bank 2 swapped. Bit 30 OPTCHANGEERRIE: Option byte change error interrupt enable bit OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. 0: no interrupt is generated when an error occurs during an option byte change 1: an interrupt is generated when an error occurs during an option byte change. Bits 29:5 Reserved, must be kept at reset value. Bit 4 MER: Flash mass erase enable bit To program MER bit, FLASH_CR1, FLASH_CR2 and FLASH_OPTCR registers must have been previously unlocked. Programming MER bit to ‘1’ automatically sets BER1, BER2, START1 and START2 to ‘1’. This allows to mass erase both banks simultaneously. 150/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bits 3:2 Reserved, must be kept at reset value. Bit 1 OPTSTART: Option byte start change option configuration bit OPTSTART triggers an option byte change operation. The user can set OPTSTART only when the OPTLOCK bit is set t ‘0’. The Flash memory interface resets OPTSTART when the option byte change operation has been acknowledged. The user application cannot access any Flash register until the operation has been acknowledged. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers will be locked until the option byte change operation has been executed in Flash memory. It is not possible to start an option byte change operation if a CRC calculation is ongoing on bank 1 or bank 2: trying to set OPTSTART when CRC_BUSY1/2 of FLASH_SR1/2 register is set has not effect; the option byte change does not start and no error is generated. Bit 0 OPTLOCK: FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register. When FLASH_OPTCR is unlocked OPTLOCK is automatically reset (see Section : Configuring the programming parameters). If a wrong sequence is executed, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to ‘1’. When set to ‘1’, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from ‘0’ to ‘1’, the others bits of FLASH_OPTCR register do not change. 0: FLASH_OPTCR register unlocked 1: FLASH_OPTCR register locked. 3.5.8 FLASH option status register (current value) (FLASH_OPTSR_CUR) Address offset: 0x01C or 0x11C Reset value: 0xXXXX XXXX r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. OPT_BUSY r r r r r r r r r r r r DocID029587 Rev 3 BOR_LEV RDP ST_RAM_SIZE FZ_IWDG_STOP Res. FZ_IWDG_SDBY 16 IWDG1_HW 17 SECURITY 18 Res. 19 Res. 20 nRST_STOP_D1 21 Res. 22 nRST_STBY_D1 23 Res. 24 Res. 25 RSS1 26 RSS2 27 PERSO_OK 28 IO_HSLV 29 OPTCHANGEERR 30 SWAP_BANK_OPT 31 r r r 151/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 31 SWAP_BANK_OPT: Bank swapping option status bit SWAP_BANK_OPT reflects the value of the corresponding option bit that configures the default value for bank 1/2 swapping. 0: after boot loading, no swap for user sectors 1: after boot loading, user sectors swapped. Bit 30 OPTCHANGEERR: Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to ‘1’, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised If the OPTCHANGEERRIE bit of FLASH_OPTCR register is set to ‘1’. Writing ‘1’ to CLR_OPTCHANGEERR of register FLASH_OPTCCR clears OPTCHANGEERR. 0: no option byte change errors occurred 1: one or more errors occurred during an option byte change operation. Bit 29 IO_HSLV: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_27V) This bit indicates that the product operates below 2.7 V. 0: Product working in the full voltage range, I/O speed optimization at low-voltage disabled 1: Product operating below 2.7 V, I/O speed optimization at low-voltage feature allowed Bit 28 PERSO_OK: Device personalization status bit PERSO_OK indicates that the device has been personalized. Bit 27 RSS2: User option status bit 2 RSS2 is used for ST development code (RSS / bootloader). Bit 26 RSS1: User option status bit 1 RSS1 is used for ST development code (RSS / bootloader). Bits 25: 22 Reserved, must be kept at reset value. Bit 21 SECURITY: Security enable option status bit 0: Security feature disabled 1: Security feature enabled. Bits 20:19 ST_RAM_SIZE: DTCM RAM size option status 00: 2 Kbytes 01: 4 Kbytes 10: 8 Kbytes 11: 16 Kbytes Note: This bitfield is effective only when the security is enabled (SECURITY = ‘1’). Bit 18 FZ_IWDG_SDBY: IWDG Standby mode freeze option status bit This bit reflects the freeze status of the IWDG_FZ_STOP option bit.. 0: Independent watchdog frozen in Standby mode 1: Independent watchdog running in Standby mode. Bit 17 FZ_IWDG_STOP: IWDG Stop mode freeze option status bit This bit reflects the freeze status of the IWDG_FZ_STANDBY option bit. 0: Independent watchdog frozen in Stop mode 1: Independent watchdog running in Stop mode. Bit 16 Reserved, must be kept at reset value. 152/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bits 15:8 RDP: Readout protection level option status byte For more information about the readout protection level (refer to Section : RDP (Readout protection)). Three different levels are available: 0xAA: protection level 0 0xCC: protection level 2 others values: protection level 1. Bit 7 nRST_STBY_D1: D1 DStandby entry reset option status bit 0: a reset is generated when entering DStandby mode on D1 domain 1: no reset generated Bit 6 nRST_STOP_D1: D1 DStop entry reset option status bit 0: a reset is generated when entering DStop mode on D1 domain 1: no reset generated Bit 5 Reserved, must be kept at reset value. Bit 4 IWDG1_HW: IWDG1 control option status bit 0: IWDG1 is controlled by software 1: IWDG1 watchdog is controller by hardware. Bits 3:2 BOR_LEV: Brownout level option status bit These option bits are used to define the power level that generate a system reset. 00: the reset level is set to 2.1 V 01: the reset is set to 2.4 V 10: the reset is set to 2.7 V 11: the reset level is set to 2.1 V (as 00 configuration). Bit 1 Reserved, must be kept at reset value. Bit 0 OPT_BUSY: Option byte change ongoing flag OPT_BUSY indicates if an option byte change is ongoing. When this bit is set to ‘1’, the Flash memory interface is performing an option change and it is not possible to modify any Flash register. 0: no option byte change ongoing 1: an option byte change ongoing and all write accesses to Flash registers are blocked until the option byte change completes. DocID029587 Rev 3 153/3178 185 Embedded Flash memory (FLASH) 3.5.9 RM0433 FLASH option status register (value to program) (FLASH_OPTSR_PRG) Address offset: 0x020 or 0x120 rw 15 14 13 12 rw rw rw 16 Res. rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. rw rw rw rw rw rw rw rw ST_RAM_SIZE rw RDP rw 17 BOR_LEV rw 18 FZ_IWDG_STOP IO_HSLV Res. 19 FZ_IWDG_SDBY Res. 20 IWDG1_HW 21 SECURITY 22 Res. 23 Res. 24 nRST_STOP_D1 25 Res. 26 nRST_STBY_D1 27 Res. 28 Res. 29 RSS1 30 RSS2 31 SWAP_BANK_OPT Reset value: 0xXXXX XXXX rw rw Bit 31 SWAP_BANK_OPT: Bank swapping option configuration bit SWAP_BANK_OPT option bit is used to configure the default value for bank 1/2 swapping. 0: after boot loading, no swap for user sectors 1: after boot loading, user sectors swapped. Bit 30 Reserved, must be kept at reset value. Bit 29 IO_HSLV: I/O high-speed at low-voltage (PRODUCT_BELOW_27V) This bit indicates that the product operates below 2.7 V. It must be set only if the product supply voltage is below 2.7 V. 0: Product working in the full voltage range, I/O speed optimization at low-voltage disabled 1: Product operating below 2.7 V, I/O speed optimization at low-voltage feature allowed Bit 28 Reserved, must be kept at reset value. Bit 27 RSS2: User option configuration bit 2 RSS2 is used for ST development code (RSS / bootloader). Modifying this bit has no effect. Bit 26 RSS1: User option configuration bit 1 RSS1 is used for ST development code (RSS / bootloader). Modifying this bit has no effect. Bits 25: 22 Reserved, must be kept at reset value. 154/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 21 SECURITY: Security option configuration bit The SECURITY bit enables the security feature at device level during an option byte change. The change will be taken into account at next power-on reset. Once it is enabled, the security feature can be disabled if no areas are protected by PCROP or secure mode. If there are secure or PCROP protected areas, perform a level regression (from level 1 to 0) and set all the bits to unprotect secure areas and PCROP areas (see Section 3.3.12: Protection mechanisms). 0: Security feature disabled 1: Security feature enabled. Bits 20:19 ST_RAM_SIZE: DTCM size select option configuration bits ST_RAM_SIZE bits are used during an option byte change to set the size of DTCM RAM to be protected. 00: 2 Kbytes 01: 4 Kbytes 10: 8 Kbytes 11: 16 Kbytes Note: This bitfield is effective only when the security is enabled (SECURITY = ‘1’). Bit 18 FZ_IWDG_SDBY: IWDG Standby mode freeze option configuration bit FZ_IWDG_SDBY is used during option byte change to select if the independent watchdog is frozen in Standby mode. 0: Independent watchdog frozen in Standby mode 1: Independent watchdog running in Standby mode. Bit 17 FZ_IWDG_STOP: IWDG Stop mode freeze option configuration bit FZ_IWDG_STOP is used during option change to select if the independent watchdog is frozen in Stop mode. 0: Independent watchdog frozen in Stop mode 1: Independent watchdog running in Stop mode. Bit 16 Reserved, must be kept at reset value. Bits 15:8 RDP: Readout protection level option configuration byte RDP bits are used to change the readout protection level. This change is possible only when the current protection level is different from level 2 (see Section : RDP (Readout protection)). The possible configurations are: 0xAA: to set the protection level 0 0xCC: to set the protection level 2 all others values: to set the protection level 1. Bit 7 nRST_STBY_D1: Option byte erase after D1 DStandby option configuration bit nRST_STBY_D1 is used during option byte change.When it is set to ‘1’, option bytes are erased when entering DStandby mode on D1 domain. 0: Option bytes erased when entering DStandby mode on D1 domain 1: Option bytes Option bytes not erased when entering DStandby mode on D1 domain Bit 6 nRST_STOP_D1: Option byte erase after D1 DStop option configuration bit nRST_STOP_D1 is used during option byte change.When it is set to ‘1’, the options bytes are erased when entering DStop mode on D1 domain. 0: Option bytes erased when entering DStop mode on D1 domain 1: Option bytes Option bytes not erased when entering DStop mode on D1 domain Bit 5 Reserved, must be kept at reset value. DocID029587 Rev 3 155/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 4 IWDG1_HW: IWDG1 option configuration bit IWDG1_HW option bit is used to select if IWDG1 independent watchdog has to be controlled by hardware or by software. 0: IWDG1 controlled by software 1: IWDG1 controlled by hardware. Bits 3:2 BOR_LEV: BOR reset level option configuration bits FLASH_OPTSR_PRG are used to change the BOR_LEV option byte. To modify this option, the user must program BOR_LEV to the required configuration before starting an option byte change. The possible configurations are: 00 and 11: the reset level is set to 2.1 V 01: the reset is set to 2.4 V 10: the reset is set to 2.7 V Bits 1:0 Reserved, must be kept at reset value. 3.5.10 FLASH option clear control register (FLASH_OPTCCR) Address offset: 0x024 or 0x124 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. CLR_OPTCHANGEERR Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bit 31 Reserved, must be kept at reset value. Bit 30 CLR_OPTCHANGEERR: OPTCHANGEERR reset bit FLASH_OPTCCR is used to reset the OPTCHANGEERR flag of FLASH_OPTSR_CUR register. FLASH_OPTCCR is write-only. It is reset by programming it to ‘1’. Bits 29:0 Reserved, must be kept at reset value. 156/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.11 FLASH protection address for bank 1 (current value) (FLASH_PRAR_CUR1) Address offset: 0x028 31 30 29 28 DMEP1 Reset value: 0xXXXX XXXX Res. Res. Res. r 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 PROT_AREA_END1 r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r PROT_AREA_START1 r r r r r r r Bit 31 DMEP1: Bank 1 PCROP protected erase enable option status bit If DMEP1 is set to ‘1’, the PCROP protected areas are erased when a protection level regression (change from level 1 to 0) occurs (Section : PCROP area (proprietary code readout protection, execute-only area) and Section : Standard Flash bank erase). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 PROT_AREA_END1: Bank 1 highest PCROP protected address These bits contain the last address protected by PCROP in bank 1. If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected. If this address is lower than PROT_AREA_START1, no protection is set on bank 1. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 PROT_AREA_START1: Bank 1 lowest PCROP protected address These bits contain the first address protected by PCROP in bank 1. If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected. If this address is higher than PROT_AREA_END1, no protection is set on bank 1. DocID029587 Rev 3 157/3178 185 Embedded Flash memory (FLASH) 3.5.12 RM0433 FLASH protection address for bank 1 (value to program) (FLASH_PRAR_PRG1) Address offset: 0x02C 31 30 29 28 DMEP1 Reset value: 0xXXXX XXXX Res. Res. Res. rw 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 PROT_AREA_END1 rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw PROT_AREA_START1 rw rw rw rw rw rw rw Bit 31 DMEP1: Bank 1 PCROP protected erase enable option configuration bit If DMEP1 is set to ‘1’, the PCROP protected areas are erased when a protection level regression (change from level 1 to 0) or a bank 1 erase occurs (Section : PCROP area (proprietary code readout protection, execute-only area)). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 PROT_AREA_END1: Bank 1 highest PCROP protected address configuration These bits allow configuring the last PCROP protected address in bank 1. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 PROT_AREA_START1: Bank 1 lowest PCROP protected address configuration These bits allow configuring the first PCROP protected address in bank 1. 3.5.13 FLASH secure address for bank 1 (current value) (FLASH_SCAR_CUR1) Address offset: 0x030 31 30 29 28 DMES1 Reset value: 0xXXXX XXXX Res. Res. Res. r 15 14 13 12 Res. Res. Res. Res. 27 25 24 23 22 21 20 19 18 17 16 SEC_AREA_END1 r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r SEC_AREA_START1 r 158/3178 26 r r r r DocID029587 Rev 3 r r RM0433 Embedded Flash memory (FLASH) Bit 31 DMES1: Bank 1 secure protected erase enable option status bit If DMES1 is set to ‘1’, the secure protected areas are erased when a protection level regression (change from level 1 to 0) occurs (Section : Secure area and Section : Standard Flash bank erase). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 SEC_AREA_END1: Bank 1 highest secure protected address These bits contain the last secure protected address in bank 1. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected. If this address is lower than SEC_AREA_START1, no protection is set on bank 1. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 SEC_AREA_START1: Bank 1 lowest secure protected address These bits contain the first secure protected address in bank 1. If this address is equal to SEC_AREA_END1, the whole bank 1 is secure protected. If this address is higher than SEC_AREA_END1, no protection is set on bank 1. 3.5.14 FLASH secure address for bank 1 (value to program) (FLASH_SCAR_PRG1) Address offset: 0x034 31 30 29 28 DMES1 Reset value: 0xXXXX XXXX Res. Res. Res. rw 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 SEC_AREA_END1 rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw SEC_AREA_START1 rw rw rw rw rw rw rw Bit 31 DMES1: Bank 1 secure protected erase enable option configuration bit If DMES1 is set to ‘1’, the secure protected areas are erased when a protection level regression (change from level 1 to 0) or a bank 1 erase occurs (Section : Secure area). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 SEC_AREA_END1: Bank 1 highest secure protected address configuration These bit allow configuring the last secure protected address in bank 1. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 SEC_AREA_START1: Bank 1 lowest secure protected address configuration These bit allow configuring the first secure protected address in bank 1. DocID029587 Rev 3 159/3178 185 Embedded Flash memory (FLASH) 3.5.15 RM0433 FLASH write sector protection for bank 1 (current value) (FLASH_WPSN_CUR1R) Address offset: 0x038 Reset value: 0x0000 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. r r r WRPSn1 r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 WRPSn1: Bank 1 sector write protection option status byte Each FLASH_WPSN_CUR1R bit reflects the write protection status of the corresponding bank 1 sector (see Section : Sector write protection). 3.5.16 FLASH write sector protection for bank 1 (value to program) (FLASH_WPSN_PRG1R) Address offset: 0x03C Reset value: 0x0000 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw WRPSn1 rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 WRPSn1: Bank 1 sector write protection configuration byte Setting WRPSn1 bit to ‘0’ allows write protecting the corresponding bank 1 sector (see Section : Sector write protection). 160/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.17 FLASH register with boot address (current value) (FLASH_BOOT_CURR) Address offset: 0x040 Reset value: 0xXXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BOOT_ADD1 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r BOOT_ADD0 r r r r r r r r r Bits 31:16 BOOT_ADD1: Boot address 1 These bits reflect the MSB of the boot address when BOOT pin is high. Bits 15:0 BOOT_ADD0: Boot address 0 These bits reflect the MSB of the boot address when BOOT pin is low. 3.5.18 FLASH register with boot address (value to program) (FLASH_BOOT_PRGR) Address offset: 0x044 Reset value: 0xXXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BOOT_ADD1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BOOT_ADD0 rw rw rw rw rw rw rw rw rw Bits 31:16 BOOT_ADD1: Boot address 1 configuration These bits allow configuring the MSB of the boot address when BOOT pin is high. Bits 15:0 BOOT_ADD1: Boot address 0 configuration These bits allow configuring the MSB of the boot address when BOOT pin is low. DocID029587 Rev 3 161/3178 185 Embedded Flash memory (FLASH) 3.5.19 RM0433 FLASH CRC control register for bank 1 (FLASH_CRCCR1) Address offset: 0x050 Reset value: 0x001C 0000 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 rw rw 19 18 17 16 Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. w w rw w 2 START_CRC 24 CLEAN_CRC 25 w rw 1 0 CRC_SECT 26 CRC_BURST 27 ALL_BANK 28 CRC_BY_SECT 29 ADD_SECT 30 CLEAN_SECT 31 rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 CRC_BURST: Bank 1 CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. 00: every burst has a size of 4 Flash words 01: every burst has a size of 16 Flash words 10: every burst has a size of 64 Flash words 11: every burst has a size of 256 Flash words Bits 19:18 Reserved, must be kept at reset value. Bit 17 CLEAN_CRC: Bank 1 CRC clear bit Setting CLEAN_CRC to ‘1’ clears the current CRC result stored in the FLASH_CRCDATAR register. Bit 16 START_CRC: Bank 1 CRC start bit START_CRC bit triggers a CRC calculation on bank 1 using the current configuration. It is not possible to start a CRC calculation when an option byte change operation is ongoing because all write accesses to Flash registers are put on hold until the option byte change operation has completed. Bits 15:13 Reserved, must be kept at reset value. Bits 12:11 Reserved, must be kept at reset value. Bit 10 CLEAN_SECT: Bank 1 CRC sector list clear bit Setting CLEAN_SECT to ‘1’ clears the list of sectors on which the CRC is calculated. Bit 9 ADD_SECT: Bank 1 CRC sector select bit Setting ADD_SECT to ‘1’ adds the sector whose number is CRC_SECT to the list of sectors on which the CRC is calculated. 162/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 8 CRC_BY_SECT: Bank 1 CRC sector mode select bit When CRC_BY_SECT is set to ‘1’, the CRC calculation is performed at sector level, on the sectors selected by CRC_SECT or on all banks if ALL_BANK bit is set. When CRC_BY_SECT is reset to ‘0’, the CRC calculation is performed on all addresses between CRC_START_ADDR and CRC_END_ADDR. Bit 7 ALL_BANK: Bank 1 CRC select bit When ALL_BANK is set to ‘1’, all bank 1 user sectors are added to list of sectors on which the CRC is calculated. Bits 6:3 Reserved, must be kept at reset value. Bits 2:0 CRC_SECT: Bank 1 CRC sector number CRC_SECT is used to select one or more sectors to be added to CRC calculation. The CRC can be computed either between two addresses (start address and end address) or on a list of sectors. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting to ‘1’ ADD_SECT. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. To know the number of each sector, refer to the description of SNB1 bits in FLASH_CR register (see Section 3.5.4: FLASH control register for bank 1 (FLASH_CR1)). CRC_SECT can be set only when CRC_EN of FLASH_CR register is set to ‘1’. 3.5.20 FLASH CRC start address register for bank 1 (FLASH_CRCSADD1R) Address offset: 0x054 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRC_START_ADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRC_START_ADDR rw rw rw rw rw rw rw rw rw Bits 31:0 CRC_START_ADDR: CRC start address on bank 1 CRC_START_ADDR is used when CRC_BY_SECT is ‘0’. It must be programmed to the start address of the bank 1 memory area on which the CRC calculation is performed. DocID029587 Rev 3 163/3178 185 Embedded Flash memory (FLASH) 3.5.21 RM0433 FLASH CRC end address register for bank 1 (FLASH_CRCEADD1R) Address offset: 0x058 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRC_END_ADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRC_END_ADDR rw rw rw rw rw rw rw rw rw Bits 31:0 CRC_END_ADDR: CRC end address on bank 1 CRC_END_ADDR is used when CRC_BY_SECT is ‘0’. It must be programmed to the end address of the bank 1 memory area on which the CRC calculation is performed 3.5.22 FLASH CRC data register (FLASH_CRCDATAR) Address offset: 0x05C or 0x15C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRC_DATA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRC_DATA rw rw rw rw rw rw rw rw rw Bits 31:0 CRC_DATA: CRC result CRC_DATA contain the result of the CRC calculation. 164/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.23 FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) Address offset: 0x060 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r Res. FAIL_ECC_ADDR1 r r r r r r r r r Bits 31:15 Reserved, must be kept at reset value. Bits 14:0 FAIL_ECC_ADDR1: Bank 1 ECC error address When an ECC error occurs (both for single correction or double detection) during a read operation from bank 1, the FAIL_ECC_ADDR1 bitfield contains the address that generated the error. FAIL_ECC_ADDR1 is reset when the flag error in the FLASH_SR1 register (CLR_SNECCERR1 or CLR_DBECCERR1) is reset. The Flash memory interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. DocID029587 Rev 3 165/3178 185 Embedded Flash memory (FLASH) 3.5.24 RM0433 FLASH key register for bank 2 (FLASH_KEYR2) Address offset: 0x104 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR2 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w KEYR2 w w w w w w w w Bits 31:0 KEYR2: Bank 2 access configuration unlock key FLASH_KEYR2 is a write-only register. The following values must be programmed consecutively to unlock FLASH_CR2 register and allow programming/erasing it: a) 1stkey = 0x4567 0123 b) 2ndkey = 0xCDEF 89AB For more details, see Section : Configuring the programming parameters. 3.5.25 FLASH control register for bank 2 (FLASH_CR2) Address offset: 0x10C Reset value: 0x0000 0031 Res. Res. Res. Res. rw rw rw rw rw 10 9 8 7 6 5 rw rw 15 14 13 12 11 Res. Res. Res. Res. rw 166/3178 SNB2 rw rw rw DocID029587 Rev 3 4 PSIZE2 rw CRC_EN rw rw rw EOPIE2 Res. rw rw rw rw 3 2 1 0 LOCK2 16 WRPERRIE2 17 PG2 18 PGSERRIE2 19 SER2 20 STRBERRIE2 21 BER2 22 INCERRIE2 23 OPERRIE2 24 FW2 25 RDPERRIE2 26 START2 27 RDSERRIE2 28 SNECCERRIE2 29 DBECCERRIE2 30 CRCENDIE2 31 rw rw rw rs RM0433 Embedded Flash memory (FLASH) Bits 31:28 Reserved, must be kept at reset value. Bit 27 CRCENDIE2: Bank 2 end of CRC calculation interrupt enable bit When CRCENDIE2 bit is set to ’1’, an interrupt is generated when the CRC computation has completed on bank 2. CRCENDIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when CRC computation complete on bank 2 1: interrupt generated when CRC computation complete on bank 2 Bit 26 DBECCERRIE2: Bank 2 ECC double detection error interrupt enable bit When DBECCERRIE2 bit is set to ‘1’, an interrupt is generated when an ECC double detection error occurs during a read operation from bank 2. DBECCERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when an ECC double detection error occurs on bank 2 1: interrupt generated if an ECC double detection error occurs on bank 2 Bit 25 SNECCERRIE2: Bank 2ECC single correction error interrupt enable bit When SNECCERRIE2 bit is set to ‘1’, an interrupt is generated when an ECC single correction error occurs during a read operation from bank 2. SNECCERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when an ECC single correction error occurs on bank 2 1: interrupt generated when an ECC single correction error occurs on bank 2 Bit 24 RDSERRIE2: Bank 2 secure error interrupt enable bit When RDSERRIE2 bit is set to ‘1’, an interrupt is generated when a secure error (access to a secure protected address without the appropriate rights) occurs during a read operation from bank 2. RDSERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a secure error occurs on bank 2 1: an interrupt is generated when a secure error occurs on bank 2 Bit 23 RDPERRIE2: Bank 2 read protection error interrupt enable bit When RDPERRIE2 bit is set to ‘1’, an interrupt is generated when a read protection error occurs (access to an address protected by PCROP) during a read operation from bank 2. RDPERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a read protection error occurs on bank 2 1: an interrupt is generated when a read protection error occurs on bank 2 Bit 22 OPERRIE2: Bank 2 write/erase error interrupt enable bit When OPERRIE2 bit is set to ‘1’, an interrupt is generated when an error is detected during a write/erase operation to bank 2. OPERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a write/erase error occurs on bank 2 1: interrupt generated when a write/erase error occurs on bank 2 Bit 21 INCERRIE2: Bank 2 inconsistency error interrupt enable bit When INCERRIE2 bit is set to ‘1’, an interrupt is generated when an inconsistency error occurs during a write operation to bank 2. INCERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a inconsistency error occurs on bank 2 1: interrupt generated when a inconsistency error occurs on bank 2 Bit 20 Reserved, must be kept at reset value. DocID029587 Rev 3 167/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 19 STRBERRIE2: Bank 2 strobe error interrupt enable bit When STRBERRIE2 bit is set to ‘1’, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation to bank 2. STRBERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a strobe error occurs on bank 2 1: interrupt generated when strobe error occurs on bank 2 Bit 18 PGSERRIE2: Bank 2 programming sequence error interrupt enable bit When PGSERRIE2 bit is set to ‘1’, an interrupt is generated when a sequence error occurs during a program operation to bank 2. PGSERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a sequence error occurs on bank 2 1: interrupt generated when sequence error occurs on bank 2 Bit 17 WRPERRIE2: Bank 2 write protection error interrupt enable bit When WRPERRIE2 bit is set to ‘1’, an interrupt is generated when a protection error occurs during a program operation to bank 2. WRPERRIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated when a protection error occurs on bank 2 1: interrupt generated when a protection error occurs on bank 2 Bit 16 EOPIE2: Bank 2end-of-program interrupt control bit Setting EOPIE2 bit to ‘1’ enables the generation of an interrupt at the end of a program operation to bank 2. EOPIE2 can be programmed only when LOCK2 is set to ‘0’. 0: no interrupt generated at the end of a program operation to bank 2. 1: interrupt enabled when at the end of a program operation to bank 2 Bit 15 CRC_EN: Bank 2 CRC control bit Setting CRC_EN bit to ‘1’ enables the CRC calculation on bank 2. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR2 register. When CRC calculation is performed on bank 2, it can only be disabled by setting CRC_EN bit to ‘0’. Resetting CRC_EN resets the content of FLASH_CRCDATAR register. CRC_EN can be programmed only when LOCK2 is set to ‘0’. Bits 14:11 Reserved, must be kept at reset value. Bits 10:8 SNB2: Bank 2 sector erase selection number These bits are used to select the target sector for a sector erase operation. SNB2 can be programmed only when LOCK2 is set to ‘0’. When the most significant bit is set to ‘1’, the third bit is used to select between ICP sectors and Option sectors. 000 0000: sector 0 of bank 2 000 0001: sector 1 of bank 2 ... 000 0111: sector 7 of bank 2 000 1000 to 011 1111: reserved (it's not possible to set this configuration) ... 011 1111: reserved (it's not possible to set this configuration) 100 0000: ICP sector of bank 2 other configurations: reserved Bit 7 START2: Bank 2 bank or sector erase start control bit START2 bit is used to start a sector erase or a bank erase operation. START2 can be programmed only when LOCK2 is set to ‘0’. The Flash memory interface resets START2 when the corresponding operation has been acknowledged. The user application cannot access any Flash register until the operation has been acknowledged. 168/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 6 FW2: Bank 2 write forcing control bit FW2 forces a write operation even if the write buffer is not full. FW2 can be programmed only when LOCK2 is set to ‘0’. The Flash memory interface resets FW2 when the corresponding operation has been acknowledged, The user application cannot access any Flash register until the operation has been acknowledged. Write forcing is effective only if the write buffer is not empty (in particular, FW2 will not start several write operations when the write operations are performed consecutively). Bits 5:4 PSIZE2: Bank 2 program size PSIZE2 selects the parallelism used by the Flash memory during write and erase operations to bank 2(refer to Section : Configuring the programming parameters for details). PSIZE2 can be programmed only when LOCK2 is set to ‘0’. 00: programming executed with byte parallelism 01: programming executed with half-word parallelism 10: programming executed with word parallelism 11: programming executed with double word parallelism. Bit 3 BER2: Bank 2 erase request Setting BER2 bit to ‘1’ requests a bank erase operation on bank 2. BER2 can be programmed only when LOCK2 is set to ‘0’. BER2 has a higher priority than SER2: if both are set, the Flash memory interface executes a bank erase (for more details, see Section : Standard Flash bank erase). 0: bank erase not requested on bank 2 1: bank erase requested on bank 2. Bit 2 SER2: Bank 2 sector erase request Setting SER2 bit to ‘1’ requests a sector erase on bank 2. SER2 can be programmed only when LOCK2 is set to ‘0’. BER2 has a higher priority than SER2: if both are set, the Flash memory interface executes a bank erase (for more details, see Section : Flash sector erase). 0: sector erase not requested on bank 2 1: sector erase requested on bank 2. Bit 1 PG2: Bank 2 program enable bit Setting PG2 bit to ‘1’ enables write operations to bank 2. This allows preparing program operations even if a sector or bank erase is ongoing. PG2 can be programmed only when LOCK2 is set to ‘0’. When PG2 is reset, the internal buffer is disabled for write operations to bank 2, and all the data stored in the buffer but not yet programmed are lost. Bit 0 LOCK2: Bank 2 configuration lock bit This bit locks the FLASH_CR2 register. When the FLASH_CR2 register is unlocked, LOCK2 bit is automatically reset (see Section : Configuring the programming parameters). If a wrong sequence is executed, this bit remains locked until next system reset. LOCK2 can be set by programming it to ‘1’. When set to ‘1’, a new unlock sequence is mandatory to unlock it. When LOCK2 changes from ‘0’ to ‘1’, the other bits of FLASH_CR2 register do not change. DocID029587 Rev 3 169/3178 185 Embedded Flash memory (FLASH) 3.5.26 RM0433 FLASH status register for bank 2 (FLASH_SR2) Address offset: 0x110 Reset value: 0x0000 0000 20 19 18 17 16 Res. Res. Res. Res. Res. r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BSY2 r WBNE2 r QW2 r CRC_BUSY2 r EOP2 21 WRPERR2 22 PGSERR2 23 STRBERR2 24 INCERR2 25 OPERR2 26 RDPERR2 27 RDSERR2 28 SNECCERR2 29 DBECCERR2 30 CRCEND2 31 r r r r Bits 31:28 Reserved, must be kept at reset value. Bit 27 CRCEND2: Bank 2 CRC-complete flag CRCEND2 bit is raised when the CRC computation has completed on bank 2. An interrupt is generated if CRCENDIE2 is set to ‘1’. It is not necessary to reset CRCEND2 before restarting CRC computation. Writing ‘1’ to CLR_CRCEND2 bit in FLASH_CCR2 register clears CRCEND2. 0: CRC computation not complete on bank 2 1: CRC computation complete on bank 2 Bit 26 DBECCERR2: Bank 2 ECC double detection error flag DBECCERR2 flag is raised when an ECC double detection error occurs during a read operation from bank 2. An interrupt is generated if DBECCERRIE2 is set to ‘1’. Writing ‘1’ to CLR_DBECCERR2 bit in FLASH_CCR2 register clears DBECCERR2. 0: no ECC double detection error occurs on bank 2 1: ECC double detection error occurs on bank 2 Bit 25 SNECCERR2: Bank 2 single correction error flag SNECCERR2 flag is raised when an ECC single correction error occurs during a read operation from bank 2. An interrupt is generated if SNECCERRIE2 is set to ‘1’. Writing ‘1’ to CLR_SNECCERR2 bit in FLASH_CCR2 register clears SNECCERR2. 0: no ECC single correction error occurs on bank 2 1: ECC single correction error occurs on bank 2 Bit 24 RDSERR2: Bank 2 secure error flag RDSERR2 flag is raised when an secure error (access to a secure protected word without the appropriate rights) occurs on bank 2. An interrupt is generated if RDSERRIE2 is set to ‘1’. Writing ‘1’ to CLR_RDSERR2 bit in FLASH_CCR2 register clears RDSERR2. 0: no secure error occurs on bank 2 1: a secure error occurs on bank 2 170/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 23 RDPERR2: Bank 2 read protection error flag RDPERR2 flag is raised when an read protection error (access to a PCROP-protected word) occurs on bank 2. An interrupt is generated if RDPERRIE2 is set to ‘1’. Writing ‘1’ to CLR_RDPERR2 bit in FLASH_CCR2 register clears RDPERR2. 0: no read protection error occurs on bank 2 1: a read protection error occurs on bank 2 Bit 22 OPERR2: Bank 2 write/erase error flag OPERR2 flag is raised when an error occurs during a write/erase to/from bank 2. An interrupt is generated if OPERRIE2 is 1 set to ‘1’. Writing ‘1’ to CLR_OPERR2 bit in FLASH_CCR2 register clears OPERR2. 0: no write/erase error occurs on bank 2 1: a write/erase error occurs on bank 2 Bit 21 INCERR2: Bank 2 inconsistency error flag INCERR2 flag is raised when a inconsistency error occurs on bank 2. An interrupt is generated if INCERRIE2 is set to ‘1’. Writing ‘1’ to CLR_INCERR2 bit in the FLASH_CCR2 register clears INCERR2. 0: no inconsistency error occurs on bank 2 1: a inconsistency error occurs on bank 2. Bit 20 Reserved, must be kept at reset value. Bit 19 STRBERR2: Bank 2 strobe error flag STRBERR2 flag is raised when a strobe error occurs on bank 2 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE2 bit is set to ‘1’. Writing ‘1’ to CLR_STRBERR2 bit in FLASH_CCR2 register clears STRBERR2. 0: no strobe error occurs on bank 2 1: a strobe error occurs on bank 2. Bit 18 PGSERR2: Bank 2 programming sequence error flag PGSERR2 flag is raised when a sequence error occurs on bank 2. An interrupt is generated if the PGSERRIE2 bit is set to ‘1’. Writing ‘1’ to CLR_PGSERR2 bit in FLASH_CCR2 register clears PGSERR2. 0: no sequence error occurs on bank 2 1: a sequence error occurs on bank 2. Bit 17 WRPERR2: Bank 2 write protection error flag WRPERR2 flag is raised when a protection error occurs during a program operation to bank 2. An interrupt is also generated if the EOPIE2 is set to ‘1’. Writing ‘1’ to CLR_EOP2 bit in FLASH_CCR2 register clears WRPERR2. 0: no protection error occurs on bank 2 1: a protection error occurs on bank 2 Bit 16 EOP2: Bank 2 end-of-program flag EOP2 flag is set when a programming operation to bank 2 completes. An interrupt is generated if the EOPIE2 is set to ‘1’. It is not necessary to reset EOP2 before starting a new operation. EOP2 bit is cleared by writing ‘1’ to CLR_EOP2 bit in FLASH_CCR2 register. 0: no programming operation completed on bank 2 1: a programming operation completed on bank 2 Bits 15:4 Reserved, must be kept at reset value. DocID029587 Rev 3 171/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 3 CRC_BUSY2: Bank 2CRC busy flag CRC_BUSY2 flag is set when a CRC calculation is ongoing on bank 2. This bit cannot be forced to ‘0’. The user must wait until the CRC calculation has completed or disable CRC computation on bank 2. 0: no CRC calculation ongoing on bank 2 1: CRC calculation ongoing on bank 2. Bit 2 QW2: Bank 2 wait queue flag QW2 flag is set when a program operation to bank 2 is in the waiting queue. It is not possible to know what type of programming operation is in the queue. When all program operations have been executed and thus removed from the waiting queue, this flag is reset by hardware. This bit cannot be forced to ‘0’. It is reset after a deterministic time if no other operations are requested. 0: no program operations waiting in the operation queue of bank 2 1: at least one programming operation is waiting in the operation queue of bank 2 Bit 1 WBNE2: Bank 2 write buffer not empty flag WBNE2 flag is set when bank 2 write buffer is not empty and the Flash memory interface is waiting for new data to complete it. WBNE2 is reset by hardware each time the write buffer is emptied. This happens when one of the following event occurs: – the write buffer is full – the user forces the write operation – an error that involves data loss occurs – the write operation has been disabled. This bit cannot be forced to ‘0’. To reset it, clear the write buffer by performing any of the above listed actions. 0: write buffer of bank 2 empty 1: write buffer of bank 2 waiting data to complete. Bit 0 BSY2: Bank 2 ongoing program flag BSY2 flag is set when a program operation to bank 1 is ongoing. It is not possible to know what type of program operation is ongoing. BSY2 cannot be forced to ‘0’. It is reset by hardware when the operation completes, provided no other program operation starts. 0: no programming operation executing on bank 2 1: programming operation executing on bank 2. 172/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.27 FLASH clear control register for bank 2 (FLASH_CCR2) Address offset: 0x114 Reset value: 0x0000 0000 20 19 18 17 16 Res. Res. Res. Res. Res. w w w w w w w CLR_EOP2 21 CLR_WRPERR2 22 CLR_PGSERR2 23 CLR_STRBERR2 24 CLR_INCERR2 25 CLR_OPERR2 26 CLR_RDPERR2 27 CLR_RDSERR2 28 CLR_SNECCERR2 29 CLR_DBECCERR2 30 CLR_CRCEND2 31 w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:28 Reserved, must be kept at reset value. Bit 27 CLR_CRCEND2: Bank 2 CRCEND2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ CRCEND2 flag of FLASH_SR2 register. Bit 26 CLR_DBECCERR2: Bank 2 DBECCERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ DBECCERR2 flag of FLASH_SR2 register. If the SNECCERR2 flag of FLASH_SR2 register is set to ‘0’, FLASH_ECC_FA2R register are reset to ‘0’ as well. Bit 25 CLR_SNECCERR2: Bank 2 SNECCERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ SNECCERR2 flag of FLASH_SR2 register. If the DBECCERR2 flag of FLASH_SR2 register is set to ‘0’, FLASH_ECC_FA2R register are reset to ‘0’ as well. Bit 24 CLR_RDSERR2: Bank 2 RDSERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ RDSERR2 flag of FLASH_SR2 register. Bit 23 CLR_RDPERR2: Bank 2 RDPERR2 flag clear bit Setting this bit to 1’ resets to ‘0’ RDPERR2 flag of FLASH_SR2 register. Bit 22 CLR_OPERR2: Bank 2 OPERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ OPERR2 flag of FLASH_SR2 register. Bit 21 CLR_INCERR2: Bank 2 INCERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ INCERR2 flag of FLASH_SR2 register. Bit 20 Reserved, must be kept at reset value. Bit 19 CLR_STRBERR2: Bank 2 STRBERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ STRBERR2 flag of FLASH_SR2 register. Bit 18 CLR_PGSERR2: Bank 2 PGSERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ PGSERR2 flag of FLASH_SR2 register. DocID029587 Rev 3 173/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 17 CLR_WRPERR2: Bank 2 WRPERR2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ WRPERR2 flag of FLASH_SR2 register. Bit 16 CLR_EOP2: Bank 2 EOP2 flag clear bit Setting this bit to ‘1’ resets to ‘0’ EOP2 flag of FLASH_SR2 register. Bits 15:0 Reserved, must be kept at reset value. 3.5.28 FLASH protection address for bank 2 (current value) (FLASH_PRAR_CUR2) Address offset: 0x128 31 30 29 28 DMEP2 Reset value: 0xXXXX XXXX Res. Res. Res. r 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 PROT_AREA_END2 r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r PROT_AREA_START2 r r r r r r r Bit 31 DMEP2: Bank 2 PCROP protected erase enable option status bit If DMEP2 is set to ‘1’, the PCROP protected areas are erased when a protection level regression (change from level 1 to 0) occurs (see Section : PCROP area (proprietary code readout protection, execute-only area) and Section : Standard Flash bank erase). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 PROT_AREA_END2: Bank 2 highest PCROP protected address These bits contain the last address protected by PCROP in bank 2. If this address is equal to PROT_AREA_START2, the whole bank 2 is PCROP protected. If this address is lower than PROT_AREA_START2, no protection is set on bank 2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 PROT_AREA_START2: Bank 2 lowest PCROP protected address These bits contain the first address protected by PCROP in bank 2. If this address is equal to PROT_AREA_END2, the whole bank 2 is PCROP protected. If this address is higher than PROT_AREA_END2, no protection is set on bank 1. 174/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.29 FLASH protection address for bank 2 (value to program) (FLASH_PRAR_PRG2) Address offset: 0x12C 31 30 29 28 DMEP2 Reset value: 0xXXXX XXXX Res. Res. Res. rw 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 PROT_AREA_END2 rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw PROT_AREA_START2 rw rw rw rw rw rw rw Bit 31 DMEP2: Bank 2 PCROP protected erase enable option configuration bit If DMEP2 is set to ‘1’, the PCROP protected areas are erased when a protection level regression (change from level 1 to 0) or a bank 2 erase occurs (see Section : PCROP area (proprietary code readout protection, execute-only area)). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 PROT_AREA_END2: Bank 2 highest PCROP protected address configuration These bits allow configuring the last PCROP protected address in bank 2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 PROT_AREA_START2: Bank 2 lowest PCROP protected address configuration These bits allow configuring the first PCROP protected address in bank 2. 3.5.30 FLASH secure address for bank 2 (current value) (FLASH_SCAR_CUR2) Address offset: 0x130 31 30 29 28 DMES2 Reset value: 0xXXXX XXXX Res. Res. Res. r 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 SEC_AREA_END2 r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r SEC_AREA_START2 r r r r r DocID029587 Rev 3 r r 175/3178 185 Embedded Flash memory (FLASH) RM0433 Bit 31 DMES2: Bank 2 secure protected erase enable option status bit If DMES2 is set to ‘1’, the secure protected areas are erased when a protection level regression (change from level 1 to 0) occurs (see Section : Secure area and Section : Standard Flash bank erase). Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 SEC_AREA_END2: Bank 2 highest secure protected address These bits contain the last secure protected address in bank 2. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected. If this address is lower than SEC_AREA_START2, no protection is set on bank 2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 SEC_AREA_START2: Bank 2 lowest secure protected address These bits contain the first secure protected address in bank 2. If this address is equal to SEC_AREA_END2, the whole bank 2 secure protected. If this address is higher than SEC_AREA_END2, no protection is set on bank 2. 3.5.31 FLASH secure address for bank 2 (value to program) (FLASH_SCAR_PRG2) Address offset: 0x134 31 30 29 28 DMES2 Reset value: 0xXXXX XXXX Res. Res. Res. rw 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 SEC_AREA_END2 rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw SEC_AREA_START2 rw rw rw rw rw rw rw Bit 31 DMES2: Bank 2 secure protected erase enable option configuration bit If DMES2 is set to ‘1’, the secure protected areas are erased when a protection level regression (change from level 1 to 0) or a bank 2 erase occurs (see Section : Secure area), Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 SEC_AREA_END2: Bank 2 highest secure protected address configuration These bit allow configuring the last secure protected address in bank 2. This bit can be programmed only in secure mode. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 SEC_AREA_START2: Bank 2lowest secure protected address configuration These bit allow configuring the first secure protected address in bank 2. This bit can be programmed only in secure mode. 176/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) 3.5.32 FLASH write sector protection for bank 2 (current value) (FLASH_WPSN_CUR2R) Address offset: 0x138 Reset value: 0x0000 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. r r r WRPSn2 r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 WRPSn2: Bank 2 sector write protection status byte Each FLASH_WPSN_CUR2R bit reflects the write protection status of the corresponding bank 2 sector. 3.5.33 FLASH write sector protection for bank 2 (value to program) (FLASH_WPSN_PRG2R) Address offset: 0x13C Reset value: 0x0000 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw WRPSn2 rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 WRPSn2: Bank 2 sector write protection configuration byte Setting WRPSn2 bit to ‘0’ allows write protecting the corresponding bank 2 sector. DocID029587 Rev 3 177/3178 185 Embedded Flash memory (FLASH) 3.5.34 RM0433 FLASH CRC control register for bank 2 (FLASH_CRCCR2) Address offset: 0x150 Reset value: 0x001C 0000 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 rw rw 19 18 17 16 Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. w w rw w 2 START_CRC 24 CLEAN_CRC 25 w rw 1 0 CRC_SECT 26 CRC_BURST 27 ALL_BANK 28 CRC_BY_SECT 29 ADD_SECT 30 CLEAN_SECT 31 rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 CRC_BURST: Bank 2 CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. 00: every burst has a size of 4 words 01: every burst has a size of 16 words 10: every burst has a size of 64 words 11: every burst has a size of 256 words Bits 19:18 Reserved, must be kept at reset value. Bit 17 CLEAN_CRC: Bank 2 CRC clear bit Setting CLEAN_CRC to ‘1’ clears the current CRC result stored in the FLASH_CRCDATAR register. Bit 16 START_CRC: Bank 2 CRC start bit START_CRC bit triggers a CRC calculation on bank 2 using the current configuration. It is not possible to start a CRC calculation when an option byte change operation is ongoing because all write accesses to Flash registers are put on hold until the option byte change operation has completed. Bits 15:13 Reserved, must be kept at reset value. Bits 12:11 Reserved, must be kept at reset value. Bit 10 CLEAN_SECT: Bank 2 CRC sector list clear bit Setting CLEAN_SECT to ‘1’ clears the list of sectors on which the CRC is calculated. Bit 9 ADD_SECT: Bank 2 CRC sector select bit Setting ADD_SECT to ‘1’ adds the sector whose number is CRC_SECT to the list of sectors on which the CRC is calculated. 178/3178 DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) Bit 8 CRC_BY_SECT: Bank 2 CRC sector mode select bit When CRC_BY_SECT is set to ‘1’, the CRC calculation is performed at sector level, on the sectors selected by CRC_SECT. When CRC_BY_SECT is reset to ‘0’, the CRC calculation is performed on all addresses between CRC_START_ADDR and CRC_END_ADDR. Bit 7 ALL_BANK: Bank 2 CRC select bit When ALL_BANK is set to ‘1’, all bank 2 user sectors are added to list of sectors on which the CRC is calculated. Bits 6:3 Reserved, must be kept at reset value. Bits 2:0 CRC_SECT: Bank 2 CRC sector number CRC_SECT is used to select one or more sectors to be added to CRC calculation. The CRC can be computed either between two addresses (start address and end address) or on a list of sectors. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting to ‘1’ ADD_SECT. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. To know the number of each sector, refer to the description of SNB2 bits in FLASH_CR register (see Section 3.5.25: FLASH control register for bank 2 (FLASH_CR2)). CRC_SECT can be set only when CRC_EN of FLASH_CR register is set to ‘1’. 3.5.35 FLASH CRC start address register for bank 2 (FLASH_CRCSADD2R) Address offset: 0x154 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRC_START_ADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRC_START_ADDR rw rw rw rw rw rw rw rw rw Bits 31:0 CRC_START_ADDR: CRC start address on bank 2 CRC_START_ADDR is used when CRC_BY_SECT is ‘0’. It must be programmed to the start address of the bank 2 memory area on which the CRC calculation is performed. DocID029587 Rev 3 179/3178 185 Embedded Flash memory (FLASH) 3.5.36 RM0433 FLASH CRC end address register for bank 2 (FLASH_CRCEADD2R) Address offset: 0x158 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRC_END_ADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRC_END_ADDR rw rw rw rw rw rw rw rw rw Bits 31:0 CRC_END_ADDR: CRC end address on bank 2 CRC_END_ADDR is used when CRC_BY_SECT is ‘0’. It must be programmed to the end address of the bank 2 memory area on which the CRC calculation is performed. 3.5.37 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) Address offset: 0x160 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r Res. FAIL_ECC_ADDR2 r r r r r r r r r Bits 31:15 Reserved, must be kept at reset value. Bits 14:0 FAIL_ECC_ADDR2: Bank 2 ECC error address When an ECC error occurs (both for single error correction or double detection) during a read operation from bank 2, the FAIL_ECC_ADDR2 bitfield contains the address that generated the error. FAIL_ECC_ADDR2 is reset when the flag error in the FLASH_SR2 register (CLR_SNECCERR2 or CLR_DBECCERR2) is reset. The Flash memory interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. 180/3178 DocID029587 Rev 3 0x018 FLASH_CCR1 FLASH_OPTCR 0x00000001 0 0 CLR_RDSERR1 CLR_RDPERR1 CLR_OPERR1 CLR_INCERR1 0 0 0 0 0 0 Res. Res. Res. Res. DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MER Res. Res. OPTSTART OPTLOCK 1 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 0 SER1 PG1 LOCK1 1 0 0 0 1 WBNE1 BSY1 Res. BER1 Res. 1 QW1 0 Res. 0 Res. SNB1 [2:0] CRC_BUSY1 FW1 0 Res. 0x00000037 PSIZE1 [1:0] START1 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. CRC_EN 0 Res. 0 EOPIE1 EOP1 0 WRPERRIE1 0 Res. 0 Res. 0 0 Res. 0 0 PGSERRIE1 FLASH_ OPTKEYR 0 Res. 0 0 Res. 0 0 Res. 0 0 STRBERRIE1 FLASH_KEYR1 Res. 0 CLR_EOP1 0 Res. 0 WRPERR1 0 CLR_WRPERR1 0 Res. 0 PGSERR1 0 0 Res. 0 0 STRBERR1 0 INCERRIE1 0 CLR_PGSERR1 INCERR1 0 OPERRIE1 0 Res. OPERR1 0 RDPERRIE1 0 CLR_STRBERR1 RDPERR1 0 RDSERRIE1 0 Res. RDSERR1 0 SNECCERRIE1 0 Res. SNECCERR1 0 DBECCERRIE1 0 Res. CLR_SNECCERR1 0 Res. DBECCERR1 0 CRCENDIE1 0 Res. CLR_DBECCERR1 0x00000000 Res. 0x00000000 CRCEND1 0x00000031 CLR_CRCEND1 Res.. 0 Res. FLASH_CR1 0 Res. 0 Res. Res. 0 Res. Res. 0 Res.. 0 Res. 0x014 FLASH_SR1 0 Res. 0x010 0x00000000 Res.. 0x00C 0 Res. 0x008 0x00000000 Res. 0x004 1 1 LATENCY [3:0] Res. WRHIGHFREQ [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ACR Res. 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name and reset value Res. Offset SWAP_BANK 3.6 OPTCHANGEERRIE RM0433 Embedded Flash memory (FLASH) FLASH register map and reset values Table 16. FLASH register map and reset value 1 1 1 KEYR1 OPTKEYR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 181/3178 185 Embedded Flash memory (FLASH) RM0433 Res. Res. Res. Res. Res. BOR_LEV [1:0] OPT_BUSY BOR_LEV[1:0] IWDG1_HW Res. Res. IWDG1_HW Res. Res. Res. Res. nRST_STBY_D1 nRST_STBY_D1 nRST_STOP_D1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X Res. Res. Res. Res. Res. Res. Res. Res. SEC_AREA_START1[11:0] Res. Res. Res. Res. SEC_AREA_START1[11:0] Res. Res. Res. Res. Res. Res. Res. X X X X X X X X X X X X Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PROT_AREA_START1[11:0] X X X X X X X X X X X X X X X X X X X X X X X X Res. FLASH_WPSN_ CUR1R SEC_AREA_END1[11:0] PROT_AREA_START1[11:0] X X X X X X X X X X X X X X X X X X X X X X X X Res. X SEC_AREA_END1[11:0] Res. 0xXXXX XXXX Res. FLASH_SCAR_ PRG1 Res. X Res. 0xXXXX XXXX PROT_AREA_END1[11:0] WRPSn1[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X X X X X X 0x000000FF 182/3178 X X X X X X X X X X X X X X X X X X X X X X X X X Res. FLASH_SCAR_ CUR1 PROT_AREA_END1[11:0] Res. X Res. 0xXXXX XXXX Res. FLASH_PRAR_ PRG1 FLASH_WPSN_ PRG1R X X X X X X X X X X X X X 0x000000FF 0x03C nRST_STOP_D1 Res. Res. FZ_IWDG_SDBY FZ_IWDG_STOP Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X X X RDP[7:0] Res. FZ_IWDG_STOP FZ_IWDG_SDBY Res. ST_RAM_SIZE [1:0] ST_RAM_SIZE [1:0] SECURITY Res Res. Res. Res. RSS2. RSS1. Res. Res. Res. Res. SECURITY Res. Res. Res. RSS1. RSS2. IO_HSLV OPTCHANGEERR SWAP_BANK_OPT PERSO_OK Res. IO_HSLV Res. Res. X X X X X X X X X X X X X X X X X X X X X X X X Res. 0x038 DMEP1 0x034 X DMEP1 0x030 0xXXXX XXXX DMES1 0x02C FLASH_PRAR_ CUR1 DMES1 0x028 X X X X X X RDP[7:0] 0 Res. 0x00000000 Res. SWAP_BANK_OPT FLASH_OPTCCR Res. X CLR_OPTCHANGEERR 0xXXXX XXXX Res. 0x024 FLASH_OPTSR_ PRG Res. 0x020 X X X X X X Res. 0xXXXX XXXX Res. FLASH_OPTSR_ CUR 0x01C Res. Register name and reset value Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 16. FLASH register map and reset value (continued) WRPSn1[7:0] X X X X X X X X DocID029587 Rev 3 RM0433 Embedded Flash memory (FLASH) FLASH_BOOT_ CURR FLASH_BOOT_ PRGR FLASH_ CRCSADD1R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ CRCDATAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ECC_ FA1R Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAIL_ECC_ADDR1[14:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 0 0 0 0 0 0 0 0 0 WRHIGHFREQ [1:0] 0 Res. 0 Res. 0 Res. 0 LATENCY [3:0] 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK2 0 PG2 0 SER2 0 BER2 0 PSIZE2 [1:0] 0 FW2 KEYR2 0 FLASH_ OPTKEYR 0 0 1 0 0 0 1 OPERRIE2 INCERRIE2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 SNB2 [2:0] Res. RDPERRIE2 0 0 Res. RDSERRIE2 0 0 Res. 0 Res. 0 EOPIE2 0 CRC_EN 0 WRPERRIE2 0 PGSERRIE2 0 Res. 0 STRBERRIE2 0 SNECCERRIE2 0 DBECCERRIE2 0 Res. 0 CRCENDIE2 OPTKEYR Res. 0x00000031 0 START2 FLASH_KEYR2 FLASH_CR2 CRC_SECT [2:0] 0 Res. 0 Res. 0x10C Res. 0 Res. 0 0x00000000 0 0 Res. 0 Res. 0x108 0 0 Res. 0 0x00000000 0 0 0x00000037 0x104 Res. 0 Res. ALL_BANK 0 Res. ADD_SECT CRC_BY_SECT Res. CLEAN_SECT Res. Res. 0 CRC_DATA[31:0] 0x00000000 FLASH_ACR 0 CRC_END_ADDR[31:0] 0x00000000 0x100 Res. START_CRC Res. CLEAN_CRC Res. 0 Res. 0x060 0 Res. 0x05C 0 CRC_START_ADDR[31:0] FLASH_ CRCEADD1R 0x00000000 0 Res. 0x00000000 0x058 1 Res. 0x054 0 Res. Res. 0x001C0000 CRC_BURST [1:0] Res. Res. Res. FLASH_CRCCR1 Res. 0x050 BOOT_ADD0[15:0] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Res. 0xXXXX XXXX BOOT_ADD1[15:0] Res. 0x044 BOOT_ADD0[15:0] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Res. 0xXXXX XXXX BOOT_ADD1[15:0] Res. 0x040 Register name and reset value Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 16. FLASH register map and reset value (continued) 0 0 0 1 183/3178 185 0x124 0x128 184/3178 FLASH_OPTCCR 0x00000000 FLASH_PRAR_ CUR2 0x80000000 X 0 FLASH_OPTSR_ PRG 0x13C600F0 0 1 1 FZ_IWDG_SDBY FZ_IWDG_STOP 0 1 1 Res. Res. Res. 0 X X X X X X X X X X X X DocID029587 Rev 3 0 0 0 0 0 0 0 1 Res. Res. OPT_BUSY 0 Res. 0 Res. BOR_LEV [1:0] 1 Res. BOR_LEV [1:0] 0 Res. IWDG1_HW Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OBL_LAUNCH OPTSTART OPTLOCK EOP2 QW2 WBNE2 BSY2 CRC_BUSY2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. IWDG1_HW 1 Res. Res 1 Res. 1 Res. nRST_STOP_D1 0 1 nRST_STOP_D1 0 nRST_STBY_D1 RDP[7:0] nRST_STBY_D1 0 Res. 0 0 Res. RDP[7:0] 0 Res. 0 Res. 0 Res. PROT_AREA_END2[11:0] 0 Res. 1 Res. 1 0 Res. 0 Res. PGSERR2 WRPERR2 0 Res. CLR_EOP2 0 Res. 0 Res. CLR_PGSERR2 CLR_WRPERR2 0 Res. 0 Res. STRBERR2 0 Res. CLR_STRBERR2 0 Res. OPERR2 INCERR2 0 Res. Res. RDPERR2 0 Res. Res. RDSERR2 0 Res. Res. SNECCERR2 0 Res. Res. DBECCERR2 0 Res. 0 Res. Res. 0 Res. CLR_INCERR2 Res. CRCEND2 Res. Res. Res. Res. 0 Res. 0 FZ_IWDG_STOP CLR_OPERR2 0 FZ_IWDG_SDBY CLR_RDPERR2 0 Res. CLR_RDSERR2 0 Res. CLR_SNECCERR2 0 ST_RAM_SIZE [1:0] CLR_DBECCERR2 0 Res. ST_RAM_SIZE [1:0] 0 Res. SECURITY Res Res Res. CLR_CRCEND2 0 Res. Res. Res. 0 Res. SECURITY Res 0 Res. Res. Res 0 Res. nRST_STOP_D2 0 Res. Res. RSS1 RSS1 nRST_STBY_D2 0 Res. 0 Res. RSS2 0x00000000 RSS2 Res. 0x00000000 Res. PERSO_OK 1 Res. Res. 0 IO_HSLV 0x13C600F0 IO_HSLV FLASH_OPTSR_ CUR Res. 0 Res. 0 Res. Res. Res. FLASH_CCR2 Res. SWAP_BANK OPTCHANGEERRIE 0x120 0x00000001 OPTCHANGEERR 0x11C FLASH_OPTCR SWAP_BANK_OPT 0x118 Res. 0x114 SWAP_BANK_OPT FLASH_SR2 Res. 0x110 CLR_OPTCHANGEERR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name and reset value Res. Offset DMEP2 Embedded Flash memory (FLASH) RM0433 Table 16. FLASH register map and reset value (continued) 0 0 0 0 0 1 0 0 PROT_AREA_START2[11:0] X X X X X X X X X X X X RM0433 Embedded Flash memory (FLASH) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X X X X X X X X X X Res. Res. Res. Res. Res. Res. X X X X X X X X X X X X Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X X X X X X X X X X SEC_AREA_START2[11:0] Res. SEC_AREA_END2[11:0] SEC_AREA_START2[11:0] Res. Res. Res. Res. Res. FLASH_WPSN_ CUR2R Res. X Res. 0x80000000 Res. FLASH_SCAR_ PRG2 SEC_AREA_END2[11:0] PROT_AREA_START2[11:0] X X X X X X X X X X X X X X X X X X X X X X X X Res. X Res. DMEP2 0x80000000 PROT_AREA_END2[11:0] X X X X X X X X X X X X Res. FLASH_SCAR_ CUR2 DMES2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x154 ALL_BANK 0 0 CRC_SECT [2:0] CRC_BY_SECT 0 Res. ADD_SECT 0 Res. CLEAN_SECT Res. Res. Res. Res. Res. START_CRC Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_END_ADDR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ CRCDATAR 0 0 0 0 0 0 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ECC_ FA2R Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_DATA[31:0] Res. 0x160 0 CRC_START_ADDR[31:0] FLASH_ CRCEADD2R 0x00000000 0x15C x FLASH_ CRCSADD2R 0x00000000 0x158 0 CLEAN_CRC 0x001C0000 CRC_BURST [1:0] Res. Res. Res. Res. Res. Res. Res. Res. FLASH_CRCCR2 Res. 0x150 X X X X X X X X Res. 0x000000FF WRPSn2[7:0] Res. FLASH_WPSN_ PRG2R Res. 0x13C X X X X X X X X Res. 0x000000FF WRPSn2[7:0] Res. 0x138 X Res. 0x134 0x80000000 DMES2 0x130 FLASH_PRAR_ PRG2 Res. 0x12C Register name and reset value Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 16. FLASH register map and reset value (continued) 0x00000000 0 FAIL_ECC_ADDR2[14:0] 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 185/3178 185 Security memory management RM0433 4 Security memory management 4.1 Introduction STM32H7x3 microcontrollers offer a first set of protection mechanisms, which are similar to the latest STM32 Series (STM32F4/F7 and STM32L0/L4): • Global readout device protection • Write protection • Proprietary code readout protection (PCROP) A summary of these protection mechanisms is given in Section 4.3: Flash protections. STM32H7x3 also offer a new enhanced protection mode, the Secure access mode, that makes possible the development of user-defined secure services (e.g. secure firmware update) and guarantees of a safe execution and protection of both code and data. This new mechanism is described in details in Section 4.4: Secure access mode, Section 4.5: Root secure services (RSS) and Section 4.6: Secure user software. The security memory management unit is contained inside the D1 domain. 4.2 Glossary The following terms will be used in herein: Table 17. List of preferred terms Term Description Device Security Level Standard mode Device state which allows accessing the user Flash memory, the option bytes and the bootloader area Secure access mode Device state which allows to access all the memory areas of the device Memory areas System memory User Flash memory Secure user memory/area 186/3178 ST reserved memory area used to store ST ROM code Flash memory area used to store user code and data This area can be configured to be accessed once after reset and be hidden for the firmware stored in the user Flash memory after the code stored in this area is executed. DocID029587 Rev 3 RM0433 Security memory management Table 17. List of preferred terms (continued) Term Description SW services Bootloader Root secure services (RSS) 4.3 STMicroelectronics software executed at reset which allows downloading firmware from regular communication port STMicroelectronics software which allows encrypted firmware/module decryption and installation into secure and non-secure user memory Secure bootloader Complementary services composed by an STMicroelectronics bootloader plus ST root secure services. Secure user software User software executed once after reset, which can be used to store SFU and firmware initialization. Secure User SW is located in Secure User Memory Secure Firmware Update (SFU) User software used to download and update installed firmware from user Flash memory Flash protections Three protection mechanisms can be used in the end-user application or during development involving proprietary code (such as third-party libraries): • Readout device protection (RDP) This is a global protection mechanism, which is suitable for end products. It prevents the device from being accessed externally through the debug port or boot from RAM or bootloader. • Proprietary code readout protection (PCROP) This mechanism can be set on specific Flash memory areas that must be execute-only. PCROP is used to avoid sensitive software dumping. • Write protection This protection can be set at Flash sector level. It prevents code or data from being accidentally erased. Table 18 summarizes the protection mechanisms that are available on STM32H7x3 as well as most STM32 devices. On STM32H7x3, they are available both in Standard and Secure access modes. For further details, refer to Section 3: Embedded Flash memory (FLASH). DocID029587 Rev 3 187/3178 195 Security memory management RM0433 Table 18. Flash protection mechanisms Flash Protection Description Protection Level 1: – No access (read, erase and program) to Flash memory or backup SRAM can be performed when the debugger is connected or when the boot configuration is different from user Flash memory. Global (All sectors of all banks + – Protection can be removed by performing Flash mass erase Protection level 2: backup SRAM) – Debug access (SW or JTAG) disabled – No System bootloader access(1) – No RAM boot allowed – Protection level2 is permanent RDP 1. Scope Write protection At sector level (128 Kbytes) PCROP/executeonly area At area level (256-byte granularity) Protection against unwanted write/modification of user Flash memory sectors Only execute accesses are allowed. This protection is set on sensitive code to prevent debug accesses and code copy by other software. Access to root secure services in Secure access mode is allowed. Refer to Section 4.4: Secure access mode. 4.4 Secure access mode Some sensitive functions require safe execution from potential malicious software attacks. Secure firmware update (SFU) software is a good example of code that requires a high level of protection since it handles secret data (such as encrypted firmware or cryptographic keys) that shall not be retrieved by other processes. STM32H7x3 microcontrollers feature secure memory areas with restricted access. They allow building secure services that will be executed prior to any user application. These secure areas, together with the software they contain, are only accessible when configuring a new device in Secure access mode. Figure 7 gives an overview of Flash memory areas and services in Standard and Secure access modes. 188/3178 DocID029587 Rev 3 RM0433 Security memory management Figure 7. Flash memory areas and services in Standard and Secure access modes 2SWLRQE\WHV %DQNRQO\ 2SWLRQE\WHV %DQNRQO\ %RRWORDGHU %RRWORDGHU 6\VWHP PHPRU\ 6HFXUHERRWORDGHU 566 8VHU PHPRU\ 6HFXUHXVHU VRIWZDUH 6HFXUHXVHU PHPRU\ 8VHUVRIWZDUH 8VHUVRIWZDUH 6WDQGDUG PRGH 6HFXUHDFFHVV PRGH 06Y9 1. The protected areas that can only be accessed in Secure access mode are shown in blue. 4.4.1 Associated features The Secure access mode can be configured through option bytes. When it is set, it enables access to: • the secure bootloader, which embeds the bootloader plus some secure services provided by STMicroelectronics (see Section 4.5: Root secure services (RSS)) • Secure user memory which embeds secure user code and data. For a summary of access rights for each core, refer to Section 4.7: Summary of Flash protection mechanisms. 4.4.2 Boot state machine In Secure access mode, the secure bootloader replaces the standard bootloader. Booting in the RSS is forced independently from boot configuration (boot pins and boot addresses). Root secure services and Secure user software will hence preempt all other codes in the device (including classical bootloader). Execution priority 1. Root secure services have the highest priority after a system reset. The service called will be executed and a new system reset will be triggered immediately afterwards. The available secure services are detailed in Section 4.5: Root secure services (RSS). 2. If no service is requested, the Secure user software will be executed provided it has been defined and the boot address has been set accordingly. Refer to Section 4.6: Secure user software for Secure user software settings. 3. Otherwise, the classical boot state-machine will be followed: bootloader or boot from Flash memory. DocID029587 Rev 3 189/3178 195 Security memory management RM0433 Figure 8 shows STM32H7x3 boot state machine. Figure 8. Secure bootloader state machine 6HFXUH$FFHVVPRGH 6HFXUH 6HUYLFH UHTXHVWHG" ([HFXWH VHUYLFHDQG UHVHW \HV 6\VWHP5HVHW 6WDQGDUGPRGH 1R %227# 6HFBXVHUBVWDUW EDQNRU #" \HV 1R %227# 2U %RRW/RDGHU 566 6HFXUH%RRWORDGHU 6HFXUH8VHU6RIWZDUH %DQNRU ([LWVHUYLFHFDOO 566BH[LW6HFXUH$UHD 8VHUDSSOLFDWLRQ# 8VHUDSSOLFDWLRQ 06Y9 4.4.3 Secure access mode configuration Enabling Secure access mode There is no restriction on how to activate Secure access mode on the device. It is configured through the SECURITY option bit in FLASH_OPTSR_CUR register (see Section 3.5.8: FLASH option status register (current value) (FLASH_OPTSR_CUR)). The Secure access mode becomes active after a system reset. Disabling Secure access mode Disabling Secure access mode is a more sensitive task as it can only be done if no more protected code exists on the device. As a result, to come back to Standard mode, Secure user memories and PCROP/execute-only areas shall be removed before clearing the SECURITY option bit in the FLASH_OPTSR_CUR register. Protected areas can be removed either by performing a Flash mass erase, a bank erase or by calling a dedicated secure service (for PCROP areas only): 190/3178 • Refer to Section : PCROP area (proprietary code readout protection, execute-only area) and to RSS_resetAndDestroyPCROPArea secure service for removing PCROP protection. • Refer to Section 3.3.12: Protection mechanisms for an explanation on how to remove secure areas. DocID029587 Rev 3 RM0433 4.5 Security memory management Root secure services (RSS) STMicroelectronics provides services to configure secure areas. These root secure services are executed after a system reset in Secure access mode and prior to any other software stored in the device. RSS software cannot be accessed (read, write, execute and debug) when the STM32H7x3 operates in Standard mode. When the STM32H7x3 is configured in Secure access mode, the RSS software is executed only once at reset. When RSS software execution is complete, it cannot be accessed anymore (no other code can jump directly to RSS). Any RSS routine is called by performing a reset. 4.5.1 Calling root secure services A secure service is called through a public API that triggers a software reset (see Figure 9, step 1) so that the secure bootloader is executed with RSS code available (see Figure 9, step 2). Once executed, most services trigger a system reset (see Figure 9, step 3) and as no more service is required, the secure bootloader jumps to the user software (see Figure 9, step 4). Figure 9. Root secure service call 6\VWHP5HVHW 6HFXUH%RRWORDGHU 5RRW6HFXUHVHUYLFH FDOO 8VHUFRGH 06Y9 DocID029587 Rev 3 191/3178 195 Security memory management 4.5.2 RM0433 Root secure services description The following secure services are available for managing PCROP, secure user memory and secure mode settings. RSS_resetAndInitializeSecureAreas Prototype void RSS_resetAndInitializeSecureAreas(RSS_SecureArea_t area) Arguments Secure user areas start and end addresses. One or two Secure user areas can be set. This service sets Secure user area boundaries, following the values stored in the option byte registers: – SEC_AREA_START1 and SEC_AREA_END1 for bank 1 Description – SEC_AREA_START2 and SEC_AREA_END2 for bank 12 This service can be used only when a secure area is set for the first time. A system reset is triggered after service completion. RSS_exitSecureArea Prototype void RSS_exitSecureArea(unsigned int vectors) Arguments Address of application vectors where to jump after exit This service is used to exit from secure user software and jump to user main Description application. There is no system reset triggered by this service RSS_resetAndDestroyPCROPArea Prototype RSS_resetAndDestroyPCROPArea(RSS_FlashBank_et bank) Arguments Targeted bank number This service overwrites PCROP area and removes the PCROP protection. Description Avoid a Flash/bank mass erase. A system reset is triggered after service completion 4.6 Secure user software A Secure user software is a trusted piece of code that is executed after device power-on or after a system reset. It allows building secure applications such as: 192/3178 • code signature or integrity checking (user secure boot). • software license checking • secure firmware update DocID029587 Rev 3 RM0433 4.6.1 Security memory management Access rules Only accessible in Secure access mode, the Secure user software is stored in the secure user memory, a configurable protected area which is part of the user main memory. Only one user secure area per bank can be configured. Only root secure services have higher priority and can preempt secure user software execution (see Section 4.4.2: Boot state machine). After secure user software execution, the code shall jump to the main user application and prevent access to the secure user area. This is done by calling RSS_exitSecureAreas secure service with the application code address given as parameter. Once in the application code, any access to the secure user area triggers a Flash error. 4.6.2 Setting secure user memory areas One secure area of configurable size can be set in each bank. The size of each area can be set from 512 bytes to full bank with a granularity of 256 bytes: • Secure area in bank 1 Boundaries are configured through SEC_AREA_START1 and SEC_AREA_END1 option bits in FLASH_SCAR_CUR1 (see Section 3.5.13: FLASH secure address for bank 1 (current value) (FLASH_SCAR_CUR1)). • Secure area in bank 2 Boundaries are configured through SEC_AREA_START2 and SEC_AREA_END2 option bits in FLASH_SCAR_CUR2 (see Section 3.5.30: FLASH secure address for bank 2 (current value) (FLASH_SCAR_CUR2)). Note: If the secure area start address is equal to the secure area end address, the full bank is considered as secure protected. Active setting then differs depending on whether a secure user area is defined or not in the device: • No secure user area exists (first time setting): A dedicated root secure service, RSS_resetAndInitializeSecureAreas, shall be called to initialize the empty address in the ST boot state machine. Both secure areas (one per bank) can be set in the same operation. • A secure user area already exists: In this case, the secure user area code can update its own secure user area size or create a new one in the other bank. Note that RSS_resetAndInitializeSecureAreas function cannot be used to create a second user secure area. 4.6.3 Removing secure user memory areas Secure user areas can only be erased by performing a Flash mass erase or a bank erase operation. • A Flash mass erase is triggered by a level regression from RDP level 1 to RDP level 0. • A bank erase is triggered by setting BER1/2 bit of FLASH_CR1/2 register (see Section 3.5.4: FLASH control register for bank 1 (FLASH_CR1) and Section 3.5.25: FLASH control register for bank 2 (FLASH_CR2)). DocID029587 Rev 3 193/3178 195 Security memory management RM0433 In both cases, the DMES1/2 bit that defines the erase policy in the FLASH_PRAR_CUR1/2 register (see Section 3.5.11: FLASH protection address for bank 1 (current value) (FLASH_PRAR_CUR1) and Section 3.5.28: FLASH protection address for bank 2 (current value) (FLASH_PRAR_CUR2) shall be set to 1 and the area start address shall be superior to its end address. 4.6.4 Selecting secure user software The current boot address selects one of the two secure user software (one per bank). As two boot addresses can be defined, several use-cases have to be considered. The selection of the boot address between BOOT_ADD0 and BOOT_ADD1 in FLASH_BOOT_CURR register is done by the BOOT pin (see Section 2.5: Boot configuration) or by the swap bank mechanism (see Section 3.3.13: Flash bank swapping). Table 19 shows different boot address register setting and the potential associated scenarios. Table 19. Secure user software selection use-cases(1) BOOT_ADD0 (boot pin=0) BOOT_ADD1 (boot pin=1) SEC_AREA_START1 SEC_AREA_START2 SEC_AREA_START1 Use the bank swapping feature to switch between two secure SEC_AREA_START1 user software starting at same offset in each bank (previous secure boot to current) SEC_AREA_START1 Recovery firmware SEC_AREA_START1 Bootloader Use case Use the BOOT pin to switch between two secure user software (current and recovery or current and previous) Use the BOOT pin to switch between secure user software and non-secure recovery boot Use BOOT pin for bootloader based recovery (in non-secure mode) 1. Bank number and boot address register number are not related. BOOT_ADDx or can be set either to bank 1 or to bank 2. If the boot address is different from the two secure user areas, the system jump directly to the selected address, bypassing the secure user software. 194/3178 DocID029587 Rev 3 RM0433 4.7 Security memory management Summary of Flash protection mechanisms Figure 10 and Table 20 summarize the access rights of the different Flash memory areas, both in Secure access and Standard modes. Figure 10. Core access to Flash memory areas Z^^ %RRWORDGHU ^ĞĐƵƌĞƵƐĞƌ ŵĞŵŽƌLJϭ ^ĞĐƵƌĞƵƐĞƌ ŵĞŵŽƌLJϮ 3&523 3&523 8VHU0HPRU\ 8VHU0HPRU\ %DQN %DQN 6HFXUHDFFHVVPRGHRQO\ 06Y9 Table 20. Summary of Flash protected areas access rights Access type Execution Read access Debug access SW Area Security Mode Access PCROP Any ✓ Secure user software Secure access ✓ (1) Root secure services Secure access ✓ (1) PCROP Any No Secure User software Secure access ✓(1) Root secure services Secure access ✓ (1) PCROP Any No Secure User software Secure access No Root secure services Secure access No 1. Access rights granted after reset until code completion only. DocID029587 Rev 3 195/3178 195 AXI interconnect 5 AXI interconnect 5.1 AXI introduction RM0433 The AXI (advanced extensible interface) interconnect is based on the ARM® CoreLink™ NIC-400 Network Interconnect. The interconnect has six initiator ports, or ASIBs (AMBA slave interface blocks), and seven target ports, or AMIBs (AMBA master interface blocks). The ASIBs are connected to the AMIBs via an AXI switch matrix. Each ASIB is a slave on an AXI bus or AHB (advanced high-performance bus). Similarly, each AMIB is a master on an AXI or AHB bus. Where an ASIB or AMIB is connected to an AHB, it converts between the AHB and the AXI protocol. The AXI interconnect includes a GPV (global programmer view) which contains registers for configuring certain parameters, such as the QoS (quality of service) level at each ASIB. Any accesses to unallocated address space are handled by the default slave, which generates the return signals. This ensures that such transactions complete and do not block the issuing master and ASIB. 5.2 196/3178 AXI interconnect main features • 64-bit AXI bus switch matrix with six ASIBs and seven AMIBs, in D1 domain • AHB/AXI bridge function built into the ASIBs • concurrent connectivity of multiple ASIBs to multiple AMIBs • programmable traffic priority management (QoS - quality of service) • software-configurable via GPV DocID029587 Rev 3 RM0433 AXI interconnect 5.3 AXI interconnect functional description 5.3.1 Block diagram The AXI interconnect is shown in Figure 11. Figure 11. AXI interconnect 0DVWHUV &0 '$+% $+% $6,%V 6'00& $;, ,1, $+% ,1, 0'0$ $;, ,1, *39 /7'& $;, ,1, $;, ,1, ,1, GHIDXOW VODYH $;,VZLWFKPDWUL[ $0,%V 6ODYHV 7$5* 7$5* 7$5* 7$5* 7$5* 7$5* 7$5* $;, $;, $;, $;, $;, $;, $;, $;,$+% EULGJH $;,$+% EULGJH )ODVK$ )ODVK% $+% )0& 463, $;, LQWHUFRQQHFW $;, 65$0 $+% ELWEXV $+%SHULSKV 'GRPDLQ 'GRPDLQ 5.3.2 '0$' ELWEXV 06Y 9 ASIB configuration Table 21 summarizes the characteristics of the ASIBs. Table 21. ASIB configuration ASIB Connected master Protocol Bus width R/W issuing INI 1 AHB from D2 domain AHB-lite 32 1/4 INI 2 Cortex-M7 AXI4 64 7/32 INI 3 SDMMC1 AHB-lite 32 1/4 INI 4 MDMA AXI4 64 4/1 INI 5 DMA2D AXI4 64 2/1 INI 6 LTDC AXI4 64 1/1 DocID029587 Rev 3 197/3178 215 AXI interconnect 5.3.3 RM0433 AMIB configuration Table 22 summarizes the characteristics of the AMIBs. Table 22. AMIB configuration AMIB Connected slave Protocol Bus width R/W/Total acceptance TARG 1 Peripheral 3 and D3 AHB AXI4(1) 32 1/1/1 TARG 2 D2 AHB AXI4(1) 32 1/1/1 TARG 3 Flash A AXI4 64 3/2/5 TARG 4 Flash B AXI4 64 3/2/5 TARG 5 FMC AXI4 64 3/3/6 TARG 6 QUADSPI AXI4 64 2/1/3 TARG 7 AXI SRAM AXI3 64 2/2/2 1. Conversion to AHB protocol is done via an AXI/AHB bridge sitting between AXI interconnect and the connected slave. 5.3.4 Quality of service (QoS) The AXI switch matrix uses a priority-based arbitration when two ASIB simultaneously attempt to access the same AMIB. Each ASIB has programmable read channel and write channel priorities, known as QoS, from 0 to 15, such that the higher the value, the higher the priority. The read channel QoS value is programmed in the AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS), and the write channel in the AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS). The default QoS value for all channels is 0 (lowest priority). If two coincident transactions arrive at the same AMIB, the higher priority transaction passes before the lower priority. If the two transactions have the same QoS value, then a leastrecently-used (LRU) priority scheme is adopted. The QoS values should be programmed according to the latency requirements for the application. Setting a higher priority for an ASIB ensures a lower latency for transactions initiated by the associated bus master. This can be useful for real-time-constrained tasks, such as graphics processing (LTDC, DMA2D). Assigning a high priority to masters that can make many and frequent accesses to the same slave (such as the Cortex-M7 CPU) can block access to that slave by other lower-priority masters. 5.3.5 Global programmer view (GPV) The GPV contains configuration registers for the AXI interconnect (see Section 5.4). These registers are only accessible by the Cortex-M7 CPU. 198/3178 DocID029587 Rev 3 RM0433 AXI interconnect 5.4 AXI interconnect registers 5.4.1 AXI interconnect - peripheral ID4 register (AXI_PERIPH_ID_4) Address offset: 0x1FD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: N/A Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® 5.4.2 AXI interconnect - peripheral ID0 register (AXI_PERIPH_ID_0) Address offset: 0x1FE0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Peripheral part number bits 0 to 7 0x00: Part number = 0x400 DocID029587 Rev 3 199/3178 215 AXI interconnect 5.4.3 RM0433 AXI interconnect - peripheral ID1 register (AXI_PERIPH_ID_1) Address offset: 0x1FE4 Reset value: 0x0000 00B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity bits 0 to 3 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Peripheral part number bits 8 to 11 0x4: Part number = 0x400 5.4.4 AXI interconnect - peripheral ID2 register (AXI_PERIPH_ID_2) Address offset: 0x1FE8 Reset value: 0x0000 002B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bits 7:4 REVISION[3:0]: Peripheral revision number 0x2: r0p2 Bit 3 JEDEC: JEP106 code flag 0x1: JEDEC allocated code Bits 2:0 JEP106ID[6:4]: JEP106 Identity bits 4 to 6 0x3: ARM® JEDEC code 200/3178 DocID029587 Rev 3 RM0433 AXI interconnect 5.4.5 AXI interconnect - peripheral ID3 register (AXI_PERIPH_ID_3) Address offset: 0x1FEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REV_AND[3:0] CUST_MOD_NUM[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 REV_AND[3:0]: Customer version 0: None Bits 3:0 CUST_MOD_NUM[3:0]: Customer modification 0: None 5.4.6 AXI interconnect - component ID0 register (AXI_COMP_ID_0) Address offset: 0x1FF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE7:0]: Preamble bits 0 to 7 0xD: Common ID value DocID029587 Rev 3 201/3178 215 AXI interconnect 5.4.7 RM0433 AXI interconnect - component ID1 register (AXI_COMP_ID_1) Address offset: 0x1FF4 Reset value: 0x0000 00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component class 0xF: Generic IP component class Bits 3:0 PREAMBLE[11:8]: Preamble bits 8 to 11 0x0: Common ID value 5.4.8 AXI interconnect - component ID2 register (AXI_COMP_ID_2) Address offset: 0x1FF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Preamble bits 12 to 19 0x05: Common ID value 202/3178 DocID029587 Rev 3 RM0433 AXI interconnect 5.4.9 AXI interconnect - component ID3 register (AXI_COMP_ID_3) Address offset: 0x1FFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Preamble bits 20 to 27 0xB1: Common ID value 5.4.10 AXI interconnect - TARG x bus matrix issuing functionality register (AXI_TARGx_FN_MOD_ISS_BM) Address offset: 0x1008 + 0x1000 * x, where x = 1 to 7 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRITE READ _ISS_ _ISS_ OVERR OVERR IDE IDE rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 WRITE_ISS_OVERRIDE: Switch matrix write issuing override for target 0: Normal issuing capability 1: Set switch matrix write issuing capability to 1 Bit 0 READ_ISS_OVERRIDE: Switch matrix read issuing override for target 0: Normal issuing capability 1: Set switch matrix read issuing capability to 1 DocID029587 Rev 3 203/3178 215 AXI interconnect 5.4.11 RM0433 AXI interconnect - TARG x bus matrix functionality 2 register (AXI_TARGx_FN_MOD2) Address offset: 0x1024 + 0x1000 * x, where x = 1, 2 and 7 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BYPAS S_MER GE rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 BYPASS_MERGE: Disable packing of beats to match the output data width. Unaligned transactions are not realigned to the input data word boundary. 0: Normal operation 1: Disable packing 5.4.12 AXI interconnect - TARG x long burst functionality modification register (AXI_TARGx_FN_MOD_LB) Address offset: 0x102C + 0x1000 * x, where x = 1 and 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. FN_MO D_LB Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 FN_MOD_LB: Controls burst breaking of long bursts 0: Long bursts can not be generated at the output of the ASIB 1: Long bursts can be generated at the output of the ASIB 204/3178 DocID029587 Rev 3 RM0433 AXI interconnect 5.4.13 AXI interconnect - TARG x issuing functionality modification register (AXI_TARGx_FN_MOD) Address offset: 0x1108 + 0x1000 * x, where x = 1, 2 and 7 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRITE READ _ISS_ _ISS_ OVERR OVERR IDE IDE rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 WRITE_ISS_OVERRIDE: Override AMIB write issuing capability 0: Normal issuing capability 1: Force issuing capability to 1 Bit 0 READ_ISS_OVERRIDE: Override AMIB read issuing capability 0: Normal issuing capability 1: Force issuing capability to 1 5.4.14 AXI interconnect - INI x functionality modification 2 register (AXI_INIx_FN_MOD2) Address offset: 0x41024 + 0x1000 * x, where x = 1 and 3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. BYPAS S_MER GE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 BYPASS_MERGE: Disables alteration of transactions by the up-sizer unless required by the protocol 0: Normal operation 1: Transactions pass through unaltered where allowed DocID029587 Rev 3 205/3178 215 AXI interconnect 5.4.15 RM0433 AXI interconnect - INI x AHB functionality modification register (AXI_INIx_FN_MOD_AHB) Address offset: 0x41028 + 0x1000 * x, where x = 1 and 3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WR_IN RD_IN C_OVE C_OVE RRIDE RRIDE rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI transactions. 0: Override disabled 1: Override enabled Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. 0: Override disabled 1: Override enabled 5.4.16 AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS) Address offset: 0x41100 + 0x1000 * x, where x = 1 to 6 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AR_QOS[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 AR_QOS[3:0]: Read channel QoS setting 0x0: Lowest priority 0xF: Highest priority 206/3178 DocID029587 Rev 3 RM0433 AXI interconnect 5.4.17 AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS) Address offset: 0x41104 + 0x1000 * x, where x = 1 to 6 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AW_QOS[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 AW_QOS[3:0]: Write channel QoS setting 0x0: Lowest priority 0xF: Highest priority 5.4.18 AXI interconnect - INI x issuing functionality modification register (AXI_INIx_FN_MOD) Address offset: 0x41108 + 0x1000 * x, where x = 1 to 6 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRITE READ _ISS_ _ISS_ OVERR OVERR IDE IDE rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 WRITE_ISS_OVERRIDE: Override ASIB write issuing capability 0: Normal issuing capability 1: Force issuing capability to 1 Bit 0 READ_ISS_OVERRIDE: Override ASIB read issuing capability 0: Normal issuing capability 1: Force issuing capability to 1 DocID029587 Rev 3 207/3178 215 0x1FF4 208/3178 AXI_COMP_ ID_1 Reset value DocID029587 Rev 3 Reset value JEP106ID [6:4] JEDEC Reset value CUST_MOD_NUM [3:0] PARTNUM [11:8] Reset value PREAMBLE [11:8] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value JEP106ID [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value REVISION [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value REV_AND[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CLASS[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x1FF0 AXI_PERIPH_ ID_3 Res. 0x1FEC AXI_PERIPH_ ID_2 Res. 0x1FE8 AXI_PERIPH_ ID_1 Res. 0x1FE4 AXI_PERIPH_ ID_0 Res. 0x1FE0 AXI_PERIPH_ ID_7 Res. 0x1FDC AXI_PERIPH_ ID_6 Res. 0x1FD8 AXI_PERIPH_ ID_5 Res. 0x1FD4 Res. JEP106CON [3:0] 4KCOUNT [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AXI_PERIPH _ID_4 Res. 0x1FD0 Res. Register name Res. Offset Res. 5.5 Res. AXI interconnect RM0433 AXI interconnect register map Table 23. AXI interconnect register map and reset values 0 0 0 0 0 1 0 0 Reserved 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 PARTNUM[7:0] 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 1 Reset value 0 0 0 0 0 0 0 0 AXI_COMP_ ID_0 PREAMBLE[7:0] Reset value 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 0 0x210C 0x3004 Reserved DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value READ_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FN_MOD_LB Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BYPASS_MERGE Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. READ_ISS_OVERRIDE Res. Res. Res. Res. WRITE_ISS_OVERRIDE Res. AXI_TARG1_ FN_MOD_ ISS_BM WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. AXI_TARG1_ FN_MOD_LB Res. Res. AXI_TARG1_ FN_MOD2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_TARG1_ FN_MOD Res. Res. 0x202C Res. Reserved Res. AXI_COMP_ ID_3 Res. Res. 0x2108 Reserved Res. 0x2030 0x2104 Res. Res. 0x2024 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AXI_COMP_ ID_2 Res. Reserved Res. 0x1FF8 Res. 0x2028 Res. 0x200C 0x2020 Res. 0x2008 Res. 0x2000 0x2004 Res. 0x1FFC Res. Register name Res. Offset Res. RM0433 AXI interconnect Table 23. AXI interconnect register map and reset values (continued) PREAMBLE[19:12] 0 0 0 0 0 1 0 1 PREAMBLE[27:20] 1 0 1 1 0 0 0 1 0 0 0 0 0 0 209/3178 215 0x400C 0x5004 210/3178 Reserved DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FN_MOD_LB Res. Res. AXI_TARG2_ FN_MOD_LB Res. Res. 0x302C READ_ISS_OVERRIDE Reserved Res. Reset value Res. Res. Res. 0x3028 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BYPASS_MERGE Res. Res. AXI_TARG2_ FN_MOD2 READ_ISS_OVERRIDE Res. Res. Res. Res. Res. WRITE_ISS_OVERRIDE Res. Reserved Res. Reset value Res. Res. AXI_TARG3_ FN_MOD_ ISS_BM Res. Reset value WRITE_ISS_OVERRIDE Reserved Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x4008 AXI_TARG2_ FN_MOD Res. READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x3008 AXI_TARG2_ FN_MOD_ ISS_BM Res. 0x310C 0x4004 Reserved Res. 0x3108 Res. 0x3030 0x3104 Res. 0x3024 Res. 0x300C 0x3020 Res. Register name Res. Offset Res. AXI interconnect RM0433 Table 23. AXI interconnect register map and reset values (continued) 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value DocID029587 Rev 3 READ_ISS_OVERRIDE Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. READ_ISS_OVERRIDE Res. Res. Res. Res. WRITE_ISS_OVERRIDE Res. AXI_TARG5_ FN_MOD_ ISS_BM READ_ISS_OVERRIDE Res. Res. Reserved Res. Res. Reset value WRITE_ISS_OVERRIDE Res. AXI_TARG6_ FN_MOD_ ISS_BM Res. READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x5008 AXI_TARG4_ FN_MOD_ ISS_BM Res. Res. AXI_TARG7_ FN_MOD_ ISS_BM Res. Reserved Res. Register name WRITE_ISS_OVERRIDE Res. Offset BYPASS_MERGE Res. Res. AXI_TARG7_ FN_MOD2 Res. 0x8024 Reserved Res. 0x800C 0x8020 Res. 0x8008 Reserved Res. 0x700C 0x8004 Res. 0x7008 Res. 0x600C 0x7004 Res. 0x6008 Res. 0x500C 0x6004 Res. RM0433 AXI interconnect Table 23. AXI interconnect register map and reset values (continued) 0 0 0 0 0 0 0 0 0 211/3178 215 0x4210C0x430FC 212/3178 Reserved DocID029587 Rev 3 AW_QOS [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BYPASS_MERGE Res. Res. Reset value WR_INC_OVERRIDE RD_INC_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_INI1_ FN_MOD2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. READ_ISS_OVERRIDE Res. Res. Res. Res. WRITE_ISS_OVERRIDE Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. AXI_TARG7_ FN_MOD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reserved Res. Reserved READ_ISS_OVERRIDE AXI_INI1_ WRITE_QOS Res. Res. Res. Res. Res. 0x8028 0x8104 Res. 0 0 0 0 Res. Res. Res. Register name WRITE_ISS_OVERRIDE Res. Reset value Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x42108 AXI_INI1_ FN_MOD Res. 0x42104 AXI_INI1_ READ_QOS Res. 0x42100 Reserved Res. 0x4202C0x420FC AXI_INI1_FN_ MOD_AHB Res. 0x42028 Res. 0x42024 Res. 0x810C0x42020 Res. 0x8108 Res. AXI interconnect RM0433 Table 23. AXI interconnect register map and reset values (continued) 0 0 0 0 0 AR_QOS [3:0] 0 0 0 0 0 0 0x44104 Reset value 0 0 0 0 AXI_INI3_ WRITE_QOS AW_QOS [3:0] Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_INI3_ READ_QOS Res. 0x44100 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reserved Res. 0x4402C0x440FC Res. Reset value Res. Reset value WR_INC_OVERRIDE RD_INC_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BYPASS_MERGE Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_INI3_ FN_MOD2 Res. READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_INI3_ FN_MOD_AHB Res. 0x44028 Reserved Res. 0x44024 Res. 0x4310C - 0x44020 AXI_INI2_ FN_MOD Res. 0x43108 Res. 0x43104 Res. Reset value 0 0 0 0 AXI_INI2_ WRITE_QOS AW_QOS [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AXI_INI2_ READ_QOS Res. 0x43100 Res. Register name Res. Offset Res. RM0433 AXI interconnect Table 23. AXI interconnect register map and reset values (continued) AR_QOS [3:0] 0 0 0 0 0 0 0 0 0 AR_QOS [3:0] 0 0 0 0 213/3178 215 0x47100 214/3178 AXI_INI6_ READ_QOS Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reserved Res. 0x4610C0x470FC Reset value Res. READ_ISS_OVERRIDE 0 0 0 0 AXI_INI5_ WRITE_QOS AW_QOS [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value WRITE_ISS_OVERRIDE Res. Reset value Res. READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 AXI_INI4_ WRITE_QOS AW_QOS [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_INI5_ FN_MOD Res. 0x46108 Res. 0x46104 AXI_INI5_ READ_QOS Res. 0x46100 Reserved Res. 0x4510C0x460FC AXI_INI4_ FN_MOD Res. 0x45108 Res. 0x45104 AXI_INI4_ READ_QOS Res. 0x45100 Reserved Res. 0x4410C0x450FC Res. READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AXI_INI3_ FN_MOD Res. 0x44108 Res. Register name Res. Offset Res. AXI interconnect RM0433 Table 23. AXI interconnect register map and reset values (continued) 0 0 AR_QOS [3:0] 0 0 0 0 0 0 AR_QOS [3:0] 0 0 0 0 0 0 AR_QOS [3:0] 0 0 0 0 0x47108 AXI_INI6_ FN_MOD DocID029587 Rev 3 Reset value Res. READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AXI_INI6_ WRITE_QOS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x47104 Res. Register name Res. Offset Res. RM0433 AXI interconnect Table 23. AXI interconnect register map and reset values (continued) AW_QOS [3:0] 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 215/3178 215 Power control (PWR) RM0433 6 Power control (PWR) 6.1 Introduction The Power control section (PWR) provides an overview of the supply architecture for the different power domains and of the supply configuration controller. It also describes the features of the power supply supervisors and explains how the VCORE supply domain is configured depending on the operating modes, the selected performance (clock frequency) and the voltage scaling. 6.2 PWR main features • • Power supplies and supply domains – Core domains (VCORE) – VDD domain – Backup domain (VSW, VBKP) – Analog domain (VDDA) System supply voltage regulation – • Peripheral supply regulation – • • 216/3178 Voltage regulator (LDO) USB regulator Power supply supervision – POR/PDR monitor – BOR monitor – PVD monitor – AVD monitor – VBAT thresholds – Temperature thresholds Power management – VBAT battery charging – Operating modes – Voltage scaling control – Low-power modes DocID029587 Rev 3 RM0433 6.3 Power control (PWR) PWR block diagram Figure 12. Power control block diagram 5&& ELW $+% EXV 3'5B21 9'' 5HJLVWHU LQWHUIDFH 3253'5 SZUBSRUBUVW %25 %DFNXSGRPDLQ 9%$7 6\VWHP6XSSO\ 9&$3 3RZHU PDQDJHPHQW 7(03 WKUHVKROGV 9%$7FKDUJLQJ 9''/'2 SZUBERUBUVW 9ROWDJH 5HJXODWRU SZUBGBZNXS SZUBGBZNXS SZUBGBZNXS 9%$7 WKUHVKROGV 9ROWDJH 6FDOLQJ 9''$ 966$ 95() H[WLBFBZNXS $QDORJGRPDLQ H[WLBGBZNXS 95() SZUBZNXS[BZNXS (;7, 9''86% 9''86% 966 86%5HJXODWRU SZUBSYGBZNXS 39' $9' SZUBDYGBZNXS 06Y 9 DocID029587 Rev 3 217/3178 270 Power control (PWR) 6.3.1 RM0433 PWR pins and internal signals Table 24 lists the PWR inputs and output signals connected to package pins or balls, while Table 25 shows the internal PWR signals. Table 24. PWR input/output signals connected to package pins or balls Signal type Pin name Description VDD Supply Main I/O and VDD domain supply input input VDDA Supply External analog power supply for analog peripherals input Supply Input/ External reference voltage for ADCs and DAC Outputs VREF+,VREF- Supply Backup battery supply input input VBAT Supply Voltage regulator supply input input VDDLDO VCAP Supply Input/ Digital core domain supply Output VDD50USB Supply USB regulator supply input input VDD33USB Supply Input/ USB regulator supply output Output VSS Supply Main ground input AHB Digital inputs/ AHB register interface outputs Digital input PDR_ON Power Down Reset enable Table 25. PWR internal input/output signals 218/3178 Signal name Signal type pwr_pvd_wkup Digital output Programmable voltage detector output pwr_avd_wkup Digital output Analog voltage detector output pwr_wkupx_wkup Digital output CPU wakeup signals (x=1 to 6) Description DocID029587 Rev 3 RM0433 Power control (PWR) Table 25. PWR internal input/output signals (continued) Signal name Signal type pwr_por_rst Digital output Power-on reset pwr_bor_rst Digital output Brownout reset exti_c_wkup Digital input CPU wakeup request exti_d3_wkup Digital input D3 domain wakeup request pwr_d1_wkup Digital output D1 domain bus matrix clock wakeup request pwr_d2_wkup Digital output D2 domain bus matrix clock wakeup request pwr_d3_wkup Digital output D3 domain bus matrix clock wakeup request Description DocID029587 Rev 3 219/3178 270 Power control (PWR) 6.4 RM0433 Power supplies The device requires VDD power supply as well as independent supplies for VDDLDO, VDDA, VDDUSB, and VCAP. It also provides regulated supplies for specific functions (voltage regulator, USB regulator). • VDD external power supply for I/Os and system analog blocks such as reset, power management and oscillators • VBAT optional external power supply for backup domain when VDD is not present (VBAT mode) This power supply shall be connected to VDD when no battery is used. • VDDLDO external power supply for voltage regulator • VCAP digital core domain supply This power supply is independent from all the other power supplies: • – When the voltage regulator is enabled, VCORE is delivered by the internal voltage regulator. – When the voltage regulator is disabled, VCORE is delivered by an external power supply through VCAP pin. VDDA external analog power supply for ADCs, DACs, OPAMPs, comparators and voltage reference buffers This power supply is independent from all the other power supplies. • 220/3178 – When the voltage reference buffer is enabled, VREF+ and VREF- are delivered by the internal voltage reference buffer. – When the voltage reference buffer is disabled, VREF+ is delivered by an independent external reference supply. • VSSA separate analog and reference voltage ground. • VDD50USB external power supply for USB regulator. • VDD33USB USB regulator supply output for USB interface. • Note: VREF+ external reference voltage for ADC and DAC. – When the USB regulator is enabled, VDD33USB is delivered by the internal USB regulator. – When he USB regulator is disabled, VDD33USB is delivered by an independent external supply input. VSS common ground for all supplies and analog regulator. Depending on the operating power supply range, some peripherals might be used with limited features and performance. For more details, refer to section “General operating conditions” of the device datasheets. DocID029587 Rev 3 RM0433 Power control (PWR) 966 9''86% 9''86% Figure 13. Power supply overview 86% ,2V 86% UHJXODWRU 966 9&$3 /HYHOVKLIWHU ,2V 'GRPDLQ 6\VWHP ORJLF (;7, ,2 ORJLF 3HULSKHUDOV 5$0 3RZHU VZLWFK 966 3RZHU VZLWFK &RUHGRPDLQ 9&25( 9ROWDJH UHJXODWRU 9''/'2 'GRPDLQ SHULSKHUDOV 5$0 'GRPDLQ &38SHULSKHUDOV 5$0 )ODVK 966 9''GRPDLQ +6,&6, 5& +6(3//V 9'' 9%$7 FKDUJLQJ %DFNXSGRPDLQ %DFNXS 9%.3 UHJXODWRU 96: 9%$7 3RZHU VZLWFK 3RZHUVZLWFK /6,/6(57& :DNHXSORJLF EDFNXS ,2 ORJLF UHJLVWHUV5HVHW %.83 ,2V 9''$ 966 $QDORJGRPDLQ 5()B%8) 95() $'&'$& 95() 95() 95() %DFNXS 5$0 966 23$03 &RPSDUDWRU 966$ 06Y 9 DocID029587 Rev 3 221/3178 270 Power control (PWR) RM0433 By configuring the voltage regulator the supply configurations shown in Figure 14 are supported for the VCORE core domain and an external supply. Figure 14. System supply configurations ([WHUQDOVXSSO\ 9&$3 9'' 9''/'2 966 9&25( 9'' 9UHJ RQ 9&$3 9&25( 9''/'2 966 9UHJ RII %\SDVV /'26XSSO\ 06Y 9 The different supply configurations are controlled through the LDOEN and BYPASS bits in PWR control register 3 (PWR_CR3) register according to Table 26. Default configuration Description 1 0 – VCORE Power Domains are supplied from the LDO according to VOS. LDO supply 1 0 – VCORE Power Domains are supplied from the LDO according to VOS. – LDO power mode (Main, LP, Off) will follow system low-power modes. LDO Bypass 0 1 – VCORE supplied from external source – LDO bypassed, voltage monitoring still active. 0 0 1 1 Illegal 222/3178 BYPASS Supply configuration LDOEN Table 26. Supply configuration control – Illegal combination, the default configuration is kept. (write data will be ignored). DocID029587 Rev 3 RM0433 6.4.1 Power control (PWR) System supply startup The system startup sequence from power-on in different supply configurations is the following (see Figure 15 for LDO supply): 1. When the system is powered on, the POR monitors VDD supply. Once VDD is above the POR threshold level, the voltage regulator is enabled in the default supply configuration: – The Voltage converter output level is set at 1.0 V in accordance with the VOS3 level configured in PWR D3 domain control register (PWR_D3CR). 2. The system is kept in reset mode as long as VCORE is not correct. 3. Once VCORE is correct, the system is taken out of reset and the HSI oscillator is enabled. 4. Once the oscillator is stable, the system is initialized: Flash memory and option bytes are loaded and the CPU starts in limited run mode (Run*). 5. The software shall then initialize the system including supply configuration programming in PWR control register 3 (PWR_CR3). Once the supply configuration has been configured, the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) shall be checked to guarantee valid voltage levels: a) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in Run* mode, write accesses to the RAMs are not permitted and VOS shall not be changed. b) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal Run mode, write accesses to RAMs are allowed and VOS can be changed. The software has to program the supply configuration in PWR control register 3 (PWR_CR3). DocID029587 Rev 3 223/3178 270 Power control (PWR) RM0433 Figure 15. Device startup with VCORE supplied from voltage regulator 325WKUHVKROG 9'' SZUBSRUBUVW 9 9''/'2 9 926 9&25( $&79265'< 9265'< 2SHUDWLQJPRGH 3RZHU GRZQ :DLW 2VFLOODWRU 5HVHW +:V\VWHP,QLW 5XQ :DLW $&7926 5'< 5XQ FNBV\V 6XSSO\FRQILJXUDWLRQ 6XSSO\FRQILJXUDWLRQ SURJUDPPHG 'HIDXOWFRQILJXUDWLRQ %<3$66 /'2(1 D E 06Y 9 1. In Run* mode, write operations to RAM are not allowed. 2. Write operations to RAM are allowed and VOS can be changed only when ACTVOSRDY is valid. When exiting from Standby mode, the supply configuration is known by the system since the PWR control register 3 (PWR_CR3) register content is retained. However the software shall still wait for the ACTVOSRDY bit to be set in PWR control status register 1 (PWR_CSR1) to indicate VCORE voltage levels are valid, before performing write accesses to RAM or changing VOS. 6.4.2 Core domain The VCORE core domain supply can be provided by the voltage regulator or by an external supply (VCAP). VCORE supplies all the digital circuitries except for the backup domain and the Standby circuitry. The VCORE domain is split into 3 sections: 224/3178 • D1 domain containing the CPU (Cortex®-M7), Flash memory and peripherals. • D2 domain containing peripherals. • D3 domain containing the system control, I/O logic and low-power peripherals. DocID029587 Rev 3 RM0433 Power control (PWR) When a system reset occurs, the voltage regulator is enabled and supplies VCORE. This allows the system to start up in any supply configurations (see Figure 14). After a system reset, the software shall configure the used supply configuration in PWR control register 3 (PWR_CR3) register before changing VOS in PWR D3 domain control register (PWR_D3CR) or the RCC ck_sys frequency. The different system supply configurations are controlled as shown in Table 26. Voltage regulator The embedded voltage regulator (LDO) requires external capacitors to be connected to VCAP pins. The voltage regulator provides three different operating modes: Main (MR), Low-power (LP) or Off. These modes will be used depending on the system operating modes (Run, Stop and Standby). • Run mode The LDO regulator is in Main mode and provides full power to the VCORE domain (core, memories and digital peripherals). The regulator output voltage can be scaled by software to different voltage levels (VOS1, VOS2, and VOS3) that are configured through VOS bits in PWR D3 domain control register (PWR_D3CR). The VOS voltage scaling allows optimizing the power consumption when the system is clocked below the maximum frequency. By default VOS3 is selected after system reset. VOS can be changed on-the-fly to adapt to the required system performance. • Stop mode The voltage regulator supplies the VCORE domain to retain the content of registers and internal memories. The regulator can be kept in Main mode to allow fast exit from Stop mode, or can be set in LP mode to obtain a lower VCORE supply level and extend the exit-from-Stop latency. The regulator mode is selected through the SVOS and LPDS bits in PWR control register 1 (PWR_CR1). Main mode and LP mode are allowed if SVOS3 voltage scaling is selected, while only LP mode is possible for SVOS4 and SVOS5 scaling. Due to a lower voltage level for SVOS4 and SVOS5 scaling, the Stop mode consumption can be further reduced. • Standby mode The voltage regulator is OFF and the VCORE domains are powered down. The content of the registers and memories is lost except for the Standby circuitry and the backup domain. Note: For more details, refer to the voltage regulator section in the datasheets. 6.4.3 PWR external supply When VCORE is supplied from an external source, different operating modes can be used depending on the system operating modes (Run, Stop or Standby): • In Run mode The external source supplies full power to the VCORE domain (core, memories and digital peripherals). The external source output voltage is scalable through different voltage levels (VOS1, VOS2 and VOS3). The externally applied voltage level shall be DocID029587 Rev 3 225/3178 270 Power control (PWR) RM0433 reflected in the VOS bits of PWR_D3CR register. The RAMs shall only be accessed for write operations when the external applied voltage level matches VOS settings. • In Stop mode The external source supplies VCORE domain to retain the content of registers and internal memories. The regulator can select a lower VCORE supply level to reduce the consumption in Stop mode. • In Standby mode The external source shall be switched OFF and the VCORE domains powered down. The content of registers and memories is lost except for the Standby circuitry and the backup domain. The external source shall be switched ON when exiting Standby mode. 6.4.4 Backup domain To retain the content of the backup domain (RTC, backup registers and backup RAM) when VDD is turned off, VBAT pin can be connected to an optional standby voltage which is supplied from a battery or from an another source. The switching to VBAT is controlled by the power-down reset embedded in the Reset block that monitors the VDD supply. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR is detected, the power switch between VBAT and VDD remains connected to VBAT. During the a startup phase, if VDD is established in less than tRSTTEMPO (see the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. When the VDD supply is present, the backup domain is supplied from VDD. This allows saving VBAT power supply battery life time. If no external battery is used in the application, it is recommended to connect VBAT externally to VDD through a 100 nF external ceramic capacitor. When the VDD supply is present and higher than the PDR threshold, the backup domain is supplied by VDD and the following functions are available: 226/3178 • PC14 and PC15 can be used either as GPIO or as LSE pins. • PC13 can be used either as GPIO or as RTC_AF1 or RTC_TAMP1 pin assuming they have been configured by the RTC. • PI8/RTC_TAMP2 and PC1/RTC_TAMP3 when they are configured by the RTC as tamper pins. DocID029587 Rev 3 RM0433 Note: Power control (PWR) Since the switch only sinks a limited amount of current, the use of PC1, PC13 to PC15 and PI8 GPIOs is restricted: only one I/O can be used as an output at a time, at a speed limited to 2 MHz with a maximum load of 30 pF. These I/Os must not be used as current sources (e.g. to drive an LED). In VBAT mode, when the VDD supply is absent and a supply is present on VBAT, the backup domain is supplied by VBAT and the following functions are available: • PC14 and PC15 can be used as LSE pins only. • PC13 can be used as RTC_AF1 or RTC_TAMP1 pin assuming they have been configured by the RTC. • PI8/RTC_TAMP2 and PC1/RTC_TAMP3 when they are configured by the RTC as tamper pins. Accessing the backup domain After reset, the backup domain (RTC registers and RTC backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, set the DBP bit in the PWR control register 1 (PWR_CR1). For more detail on RTC and backup RAM access, refer to Section 8: Reset and Clock Control (RCC). Backup RAM The backup domain includes 4 Kbytes of backup RAM accessible in 32-bit, 16-bit or 8-bit data mode. The backup RAM is supplied from the Backup regulator in the backup domain. When the Backup regulator is enabled through BREN bit in PWR control register 2 (PWR_CR2), the backup RAM content is retained even in Standby and/or VBAT mode (it can be considered as an internal EEPROM if VBAT is always present.) The Backup regulator can be ON or OFF depending whether the application needs the backup RAM function in Standby or VBAT modes. The backup RAM is not mass erased by an tamper event, instead it is read protected to prevent confidential data, such as cryptographic private key, from being accessed. To regain access to the backup RAM after a tamper event, the memory area needs to be first erased. The backup RAM can be erased: • through the Flash interface when a protection level change from level 1 to level 0 is requested (refer to the description of Read protection (RDP) in the Flash programming manual). • After a tamper event, by performing a dummy write with zero as data to the backup RAM. DocID029587 Rev 3 227/3178 270 Power control (PWR) RM0433 Figure 16. Backup domain 9%$7 96: 9'' %DFNXSGRPDLQ 9ROWDJH UHJXODWRU %DFNXS 5HJXODWRU %DFNXS,2¶V 9''/'2 9&$3 9&25(GRPDLQ %DFNXS ,QWHUIDFH %DFNXS 5$0 57& /6( 06Y9 6.4.5 VBAT battery charging When VDD is present, the external battery connected to VBAT can be charged through an internal resistance. VBAT charging can be performed either through a 5 k Ω resistor or through a 1.5 k Ω resistor, depending on the VBRS bit value in PWR control register 3 (PWR_CR3). The battery charging is enabled by setting the VBE bit in PWR control register 3 (PWR_CR3). It is automatically disabled in VBAT mode. 6.4.6 Analog supply Separate VDDA analog supply The analog supply domain is powered by dedicated VDDA and VSSA pads that allow the supply to be filtered and shielded from noise on the PCB, thus improving ADC and DAC conversion accuracy: • The analog supply voltage input is available on a separate VDDA pin. • An isolated supply ground connection is provided on VSSA pin. Analog reference voltage VREF+/VREFTo achieve better accuracy low-voltage signals, the ADC and DAC also have a separate reference voltage, available on VREF+ pin. The user can connect a separate external reference voltage on VREF+. The VREF+ controls the highest voltage, represented by the full scale value, the lower voltage reference (VREF-) being connected to VSSA. 228/3178 DocID029587 Rev 3 RM0433 Power control (PWR) When enabled by ENVR bit in the VREFBUF control and status register (see Section 27: Voltage reference buffer (VREFBUF)), VREF+ is provided from the internal voltage reference buffer. The internal voltage reference buffer can also deliver a reference voltage to external components through VREF+/VREF- pins. When the internal voltage reference buffer is disabled by ENVR, VREF+ s delivered by an independent external reference supply voltage. 6.4.7 USB regulator The USB transceivers are supplied from a dedicated VDD33USB supply that can be provided either by the integrated USB regulator, or by an external USB supply. When enabled by USBREGEN bit in PWR control register 3 (PWR_CR3), the VDD33USB is provided from the USB regulator. Before using VDD33USB, check that it is available by monitoring USB33RDY bit in PWR control register 3 (PWR_CR3). The VDD33USB supply level detector shall be enabled through USB33DEN bit in PWR_CR3 register. When the USB regulator is disabled through USBREGEN bit, VDD33USB can be provided from an external supply. In this case VDD33USB and VDD50USB shall be connected together. The VDD33USB supply level detector must be enabled through USB33DEN bit in PWR_CR3 register before using the USB transceivers. For more information on the USB regulator (see Section 57: USB on-the-go high-speed (OTG_HS)). Figure 17. USB supply configurations 9''86% 9'' 9'' 9''86% 966 9''86% 9''86% 86% UHJXODWRU 21 86%UHJXODWRU6XSSO\ 966 86% UHJXODWRU %\SDVV ([WHUQDO86%6XSSO\ 06Y 9 6.5 Power supply supervision Power supply level monitoring is available on the following supplies: • VDD via POR/PDR (see Section 6.5.1), BOR (see Section 6.5.2) and PVD monitor (see Section 6.5.3) • VDDA via AVD monitor (see Section 6.5.4) • VBAT via VBAT threshold (see Section 6.5.5) • VSW via rst_vsw, which keeps VSW domain in Reset mode as long as the level is not OK. • VBKP via a BRRDY bit in PWR control register 2 (PWR_CR2). • VDD33USB via USBRDY bit in PWR control register 3 (PWR_CR3). DocID029587 Rev 3 229/3178 270 Power control (PWR) 6.5.1 RM0433 Power-on reset (POR)/power-down reset (PDR) The system has an integrated POR/PDR circuitry that ensures proper startup operation. The system remains in Reset mode when VDD is below a specified VPOR threshold, without the need for an external reset circuit. Once the VDD supply level is above the VPOR threshold, the system is taken out of reset (see Figure 18). For more details concerning the power-on/power-down reset threshold, refer to the electrical characteristics section of the datasheets. The PDR can be enabled/disabled by the device PDR_ON input pin. Figure 18. Power-on reset/power-down reset waveform 9'' 325 K\VWHUHVLV 3'5 7 7HPSRULVDWLRQ75677(032 SZUBSRUBUVW 06Y9 1. For thresholds and hysteresis values, please refer to the datasheets. 6.5.2 Brownout reset (BOR) During power-on, the Brownout reset (BOR) keeps the system under reset until the VDD supply voltage reaches the specified VBOR threshold. The VBOR threshold is configured through system option bytes. By default, BOR is OFF. The following programmable VBOR thresholds can be selected: • BOR OFF (VBOR0) • BOR Level 1 (VBOR1) • BOR Level 2 (VBOR2) • BOR Level 3 (VBOR3) For more details on the brown-out reset thresholds, refer to the section “Electrical characteristics” of the product datasheets. A system reset is generated when the BOR is enabled and VDD supply voltage drops below the selected VBOR threshold. 230/3178 DocID029587 Rev 3 RM0433 Power control (PWR) BOR can be disabled by programming the system option bytes. To disable the BOR function, VDD must have been higher than VBOR0 to start the system option byte programming sequence. The power-down is then monitored by the PDR (see Section 6.5.1). Figure 19. BOR thresholds 9'' %25ULVH K\VWHUHVLV %25IDOO 7 SZUBERUBUVW 06Y9 1. For thresholds and hysteresis values, please refer to the datasheets. 6.5.3 Programmable voltage detector (PVD) The PVD can be used to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR control register 1 (PWR_CR1). The PVD can also be used to monitor a voltage level on the PVD_IN pin. In this case PVD_IN voltage is compared to the internal VREFINT level. The PVD is enabled by setting the PVDE bit in PWR control register 1 (PWR_CR1). A PVDO flag is available in the PWR control status register 1 (PWR_CSR1) to indicate whether VDD or PVD_IN voltage is higher or lower than the PVD threshold. This event is internally connected to the EXTI and can generate an interrupt, assuming it has been enabled through the EXTI registers. The pwr_pvd_wkup output interrupt can be generated when VDD or PVD_IN voltage drops below the PVD threshold and/or when VDD or PVD_IN voltage rises above the PVD threshold depending on EXTI rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. DocID029587 Rev 3 231/3178 270 Power control (PWR) RM0433 Figure 20. PVD thresholds 9''RU39'B,1 39'ULVH K\VWHUHVLV 39'IDOO 7 39'2 39'(1 6:HQDEOH 3'5UHVHW 06Y9 1. For thresholds and hysteresis values, please refer to the datasheets. 232/3178 DocID029587 Rev 3 RM0433 6.5.4 Power control (PWR) Analog voltage detector (AVD) The AVD can be used to monitor the VDDA supply by comparing it to a threshold selected by the ALS[1:0] bits in the PWR control register 1 (PWR_CR1). The AVD is enabled by setting the AVDEN bit in PWR control register 1 (PWR_CR1). An AVDO flag is available in the PWR control status register 1 (PWR_CSR1) to indicate whether VDDA is higher or lower than the AVD threshold. This event is internally connected to the EXTI and can generate an interrupt if enabled through the EXTI registers. The pwr_avd_wkup interrupt can be generated when VDDA drops below the AVD threshold and/or when VDDA rises above the AVD threshold depending on EXTI rising/falling edge configuration. As an example the service routine could indicate when the VDDA supply drops below a minimum level. Figure 21. AVD thresholds 9''$ $9'ULVH K\VWHUHVLV $9'IDOO 7 $9'2 $9'(1 6:HQDEOH 6:GLVDEOH 06Y9 1. For thresholds and hysteresis values, please refer to the datasheets. DocID029587 Rev 3 233/3178 270 Power control (PWR) 6.5.5 RM0433 Battery voltage thresholds The VBAT battery voltage supply can be monitored by comparing it with two threshold levels: VBAThigh and VBATlow. VBATH and VBATL flags in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or lower than the threshold. The VBAT supply monitoring can be enabled/disabled via MONEN bit in PWR control register 2 (PWR_CR2). When it is enabled, the battery voltage thresholds increase power consumption. As an example the levels could be used to trigger a routine to perform emergency saving tasks. VBATH and VBATL wakeup interrupts are available on the RTC tamper signals (see Section 46: Real-time clock (RTC)) Figure 22. VBAT thresholds 9%$7 9%$7KLJK 9%$7ORZ 7 9%$7+ 9%$7/ 06Y9 1. For thresholds and hysteresis values, please refer to the datasheets. 234/3178 DocID029587 Rev 3 RM0433 6.5.6 Power control (PWR) Temperature thresholds The junction temperature can be monitored by comparing it with two threshold levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2), indicate whether the device temperature is higher or lower than the threshold. The temperature monitoring can be enabled/disabled via MONEN bit in PWR control register 2 (PWR_CR2). When enabled, the temperature thresholds increase power consumption. As an example the levels could be used to trigger a routine to perform temperature control tasks. TEMPH and TEMPL wakeup interrupts are available on the RTC tamper signals (see Section 46: Real-time clock (RTC)). Figure 23. Temperature thresholds 7HPSHUDWXUH 7(03KLJK 7(03ORZ 7 7(03+ 7(03/ 06Y9 1. For thresholds and hysteresis values, please refer to the datasheets. DocID029587 Rev 3 235/3178 270 Power control (PWR) 6.6 RM0433 Power management The power management block controls the VCORE supply in accordance with the system operation modes (see Section 6.6.1). The VCORE domain is split into the following power domains. • D1 domain containing some peripherals and the Cortex®-M7 Core (CPU). • D2 domain containing a large part of the peripherals. • D3 domain containing some peripherals and the system control. The D1, D2 and system D3 power domains can operate in one of the following operating modes: • DRun/Run/Run* (power ON, clock ON) • DStop/Stop (power ON, clock OFF) • DStandby/Standby (Power OFF, clock OFF). The operating modes for D1 domain and D2 domain are independent. However system D3 domain power modes depend on D1 and D2 domain modes: • For system D3 domain to operate in Stop mode, both D1 and D2 domains must be in DStop or DStandby mode. • For system D3 domain to operate in Standby mode, both D1 and D2 domains must be in DStandby too. D1, D2 and system D3 domains are supplied from a single regulator at a common VCORE level. The VCORE supply level follows the system operating mode (Run, Stop, Standby). The D1 domain and/or D2 domain supply can be powered down individually when the domains are in DStandby mode. The following voltage scaling features allow controlling the power with respect to the required system performance (see Section 6.6.2: Voltage scaling): 236/3178 • To obtain a given system performance, the corresponding voltage scaling shall be set in accordance with the system clock frequency. To do this, configure the VOS bits to the Run mode voltage scaling. • To obtain the best trade-off between power consumption and exit-from-Stop mode latency, configure the SVOS bits to Stop mode voltage scaling. DocID029587 Rev 3 RM0433 6.6.1 Power control (PWR) Operating modes Several system operating modes are available to tune the system according to the performance required, i.e. when the CPU does not need to execute code and is waiting for an external event. It is up to the user to select the operating mode that gives the best compromise between low power consumption, short startup time and available wakeup sources. The operating modes allow controlling the clock distribution to the different system blocks and powering them. The system operating mode is driven by the CPU subsystem, D2 domain and system D3 autonomous wakeup. The CPU subsystem can include multiple domains depending on its peripheral allocation (see Section 8.5.11: Peripheral clock gating control). The following operating modes are available for the different system blocks (see Table 27): • CPU subsystem modes: – CRun CPU and CPU subsystem peripheral(s) allocated via RCC PERxEN bits are clocked. – CSleep: The CPU clocks is stalled and the CPU subsystem allocated peripheral(s) clock operate according to RCC PERxLPEN. – CStop: CPU and CPU subsystem peripheral(s) clocks are stalled. • D1 domain mode: – DRun The domain bus matrix is clocked. The CPU subsystem operates in CRun or CSleep mode. – DStop The domain bus matrix clock is stalled. The CPU subsystem operates in CStop mode and the PDDS_D1(1) bit selects DStop mode. – DStandby The domain is powered down. The CPU subsystem operates in CStop mode and the PDDS_D1 bit selects DStandby mode. • D2 domain mode: – DRun The domain bus matrix is clocked. The CPU subsystem has an allocated peripheral in the D2 domain and the CPU subsystem operates in CRun or CSleep mode. 1. The PDDS_Dn bits belong to PWR CPU control register (PWR_CPUCR). DocID029587 Rev 3 237/3178 270 Power control (PWR) – RM0433 DStop The domain bus matrix clock is stalled. The CPU subsystem has no peripherals allocated in the D2 domain and PDDS_D2(1) bit selects DStop mode, or the CPU subsystem has an allocated peripheral in D2 domain, the CPU subsystem operates in CStop mode and PDDS_D2 bit selects DStop mode. – DStandby The domain is powered down. The CPU subsystem has no peripherals allocated in the D2 domain and PDDS_D2 bit selects DStandby mode, or the CPU subsystem has an allocated peripheral in the D2 domain, the CPU subsystem operates in CStop mode and PDDS_D2 bit selects DStandby mode. • System /D3 domain modes – Run/Run* The system clock and D3 domain bus matrix clock are running: - The CPU subsystem is in CRun or CSleep mode or - A wakeup signal is active. (i.e. System D3 autonomous mode) The Run* mode is entered after a POR reset and a wakeup from Standby. In Run* mode, the performance is limited and the system supply configuration shall be programmed in PWR control register 3 (PWR_CR3). The system enters Run mode only when the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) is set to 1. – Stop The system clock and D3 domain bus matrix clock is stalled: - The CPU subsystem is in CStop mode. and - all wakeup signals are inactive. and - At least one PDDS_Dn(1) bit for any domain select Stop mode. – Standby The system is powered down: - The CPU subsystem is in CStop mode and - all wakeup signals are inactive. and - All PDDS_Dn(1) bits for all domains select Standby mode. In Run mode, power consumption can be reduced by one of the following means: 238/3178 • Lowering the system performance by slowing down the system clocks and reducing the VCORE supply level through VOS voltage scaling bits. • Gating the clocks to the APBx and AHBx peripherals when they are not used, through PERxEN bits. DocID029587 Rev 3 RM0433 Power control (PWR) CStop Standby(8) DStandby(3) All PDDS_Dn bit WKUP pins rising or + SLEEPDEEP falling edge, RTC alarm bit + WFI or (Alarm A or Alarm B), return from ISR RTC Wakeup event, RTC or WFE tamper events, RTC time stamp event, external or Wakeup reset in NRST pin, IWDG source reset cleared(6) Domain supply ON OFF ON ON OFF DStandby(3) Any EXTI interrupt or event OFF Stop(5) SLEEPDEEP bit + WFI or return from ISR or WFE or Wakeup source cleared(6) OFF DStop(3) ON/OFF DStandby(3) OFF SLEEPDEEP bit + WFI or return from ISR or WFE OFF DStop(3) OFF Run Voltage regulator Any interrupt or event ON CPU clk WFI or return from ISR or WFE ON/OFF(2) ON Peripheral clk CSleep DRun(1) Domain bus matrix clk ON - (4) CRun System clk Wakeup ON Entry Sys-oscillator CPU ON/OFF(7) Domain OFF System ON Table 27. Low-power mode summary 1. The CPU subsystem has an allocated peripheral in the D2 domain and operates in CRun or CSleep mode. 2. The CPU subsystem peripherals that have a PERxLPEN bit will operate accordingly. 3. If the CPU subsystem has an allocated peripheral in the D2 domain, it must operate in CStop mode. 4. The CPU subsystem peripherals that have a PERxAMEN bit will operate accordingly. 5. All domains need to be in DStop Or DStandby. 6. When the CPU is in CStop and D3 domain in autonomous mode, the last EXTI Wakeup source is cleared. 7. When the system oscillator HSI or CSI is used, the state is controlled by HSIKERON and CSIKERON, otherwise the system oscillator is OFF. 8. All domains are in DStandby mode. DocID029587 Rev 3 239/3178 270 Power control (PWR) 6.6.2 RM0433 Voltage scaling The D1, D2, and D3 domains are supplied from a single voltage regulator supporting voltage scaling with the following features: • • Run mode voltage scaling – VOS1: Scale 1 – VOS2: Scale 2 – VOS3: Scale 3 Stop mode voltage scaling – SVOS3: Scale 3 – LP-SVOS4: Scale 4 – LP-SVOS5: Scale 5 For more details on voltage scaling values, refer to the product datasheets. After reset, the system starts on the lowest Run mode voltage scaling (VOS3). The voltage scaling can then be changed on-the-fly by software by programming VOS bits in PWR D3 domain control register (PWR_D3CR) according to the required system performance. When exiting from Stop mode or Standby mode, the Run mode voltage scaling is reset to the default VOS3 value. Before entering Stop mode, the software can preselect the SVOS level in PWR control register 1 (PWR_CR1). The Stop mode voltage scaling for SVOS4 and SVOS5 also sets the voltage regulator in Low-power (LP) mode to further reduce power consumption. When preselecting SVOS3, the use of the voltage regulator low-power mode (LP) can be selected by LPDS register bit. Figure 24. VCORE voltage scaling versus system power modes 67$1'%< 32:(5'2:1 581 0$,1926 UHVHW 0$,1926 0$,1926 0$,1RU/36926 6:5XQPRGH /36926 6WRSPRGH /36926 6WDQGE\PRGH 6723 :DNHXS 06Y9 240/3178 DocID029587 Rev 3 RM0433 Power control modes The power control block handles the VCORE supply for system Run, Stop and Standby modes. The system operating mode depends on the CPU subsystem modes (CRun, CSleep, CStop), on the domain modes (DRun, DStop, DStandby), and on the system D3 autonomous wakeup: • In Run mode, VCORE is defined by the VOS voltage scaling. The CPU subsystem is in CRun or CSleep or an EXTI wakeup is active. • In Stop mode, VCORE is defined by the SVOS voltage scaling. The CPU subsystem is in CStop mode and all EXTI wakeups are inactive. The D1 domain and D2 domain are either in DStop or DStandby mode. • In Standby mode, VCORE supply is switched off. The CPU subsystem is in CStop mode and all EXTI wakeups are inactive. The D1 domain and D2 domain are both in DStandby mode. The domain operating mode can depend on the CPU subsystem when peripherals are allocated in the corresponding domain. The domain mode selection between DStop and DStandby is configured via domain dedicated PDDS_Dn bits in PWR CPU control register (PWR_CPUCR). The CPU can choose to keep a domain in DStop, or allow a domain to enter DStandby mode. If a domain is in DStandby mode, the corresponding power is switched off. All the domains can be configured for the system mode (Stop or Standby) through PDDS_Dn bits in PWR CPU control register (PWR_CPUCR). The system enters Standby only when all PDDS_Dn bits for all domains have allowed it. Table 28. PDDS_Dn low-power mode control 0 1 x PDDS_D3 PDDS_D2 PWR_CPUCR PDDS_D1 6.6.3 Power control (PWR) x 0 x 1 at least one = 0 1 1 1 D1 mode D2 mode D3 mode DStop any Run or Stop DStandby any any any DStop Run or Stop any DStandby any DStop or DStandby DStop or DStandby Stop DStandby DStandby Standby DocID029587 Rev 3 241/3178 270 Power control (PWR) RM0433 Figure 25. Power control modes detailed state diagram 581 :DNHXSIURP67$1'%< UHVHW 3''6B' &38VXEV\VWHPKDYLQJDQ DOORFDWHGSHULSKHUDOLQ' GRPDLQ &38&581RU&6/((3 'GRPDLQ'581 'GRPDLQ'6723 &BZDNHXS ' SHULSKHUDO DOORFDWLRQ ' SHULSKHUDO GHORFDWLRQ &6723 &38&581RU&6/((3 'GRPDLQ'581 ' SHULSKHUDO DOORFDWLRQ 'GRPDLQ'581 ' SHULSKHUDO GHORFDWLRQ &BZDNHXS &6723 &38&581RU&6/((3 'GRPDLQ'581 'GRPDLQ'67$1'%< &BZDNHXS &6723 &6723 &38&6723 (;7,ZDNHXSDFWLYH V\VWHP'GRPDLQDXWRQRPRXVPRGH 'GRPDLQ'6723 'GRPDLQ'67$1'%< 'GRPDLQ'6723 'GRPDLQ'67$1'%< 'GRPDLQ'6723 'GRPDLQ'6723 'GRPDLQ'67$1'%< 'GRPDLQ'67$1'%< :DNHXS IURP 6723 :DNHXS IURP 6723 6723 :DNHXS IURP 6723 (QWHUWR6723 (QWHUWR6723 :DNHXS IURP 6723 (QWHUWR6723 (QWHUWR6723 &38&6723 (;7,ZDNHXSVLQDFWLYH 'GRPDLQ'6723 'GRPDLQ'67$1'%< 'GRPDLQ'6723 'GRPDLQ'67$1'%< 'GRPDLQ'6723 'GRPDLQ'6723 'GRPDLQ'67$1'%< 'GRPDLQ'67$1'%< 67$1'%< (QWHUWR 67$1'%< 'GRPDLQ'67$1'%< &38VXEV\VWHPPRGHV 'RPDLQPRGHV 6\VWHP'GRPDLQPRGHV 'GRPDLQ'67$1'%< 6:5XQPRGH 6WRSPRGH 6WDQGE\PRGH :DNHXS 06Y 9 242/3178 DocID029587 Rev 3 RM0433 Power control (PWR) After a system reset, the CPU is in CRun mode. Power control state transitions are initiated by the following events: • • • CPU going to CStop mode (state transitions in Run mode are marked in green and red) – Green transitions: CPU wakes up as from CSleep. – Red transitions: CPU wakes up with domain reset. The SBF_Dn is set. Allocating or de-locating a peripheral in a domain (state transitions in Run mode are marked in orange and red) – Orange transitions: the domain wakes up from DStop – Red transitions: the domain wakes up from DStandby. The SBF_Dn is set. The system enters or exits from Stop mode (state transitions marked in blue) – • Blue transitions the system wakes up from Stop mode. The STOPF is set. The system enters or exits from Standby mode (state transitions in Stop and Standby mode are marked in red). – When exiting from Standby mode, the SBF is set. When a domain exits from DStandby, the domain peripherals are reset, while the domain SBF_Dn bit is set (state transitions causing a domain reset are marked in red). Table 29 shows the flags that indicate from which mode the domain/system exits. The CPU features a set of flags which can be read from PWR CPU control register (PWR_CPUCR). System mode D1 domain mode D2 domain mode SBF_D1 SBF_D2 SBF STOPF Table 29. Low-power exit mode flags Run DRun or DStop DRun or DStop 0 0 0 0 D1, D2 and system contents retained Run DStandby DStop 1 0 0 0 D1 contents lost, D2 and system contents retained Run DRun or DStop DStandby 0 1 0 0 D2 contents lost, D1 and system contents retained Run DStandby DStandby 1 1 0 0 D1 and D2 contents lost, system contents retained Stop DStop DStop 0 0 0 1 D1, D2 and system contents retained, clock system reset. Stop DStandby DStop 1 0 0 1 D1 contents lost, D2 and system contents retained, clock system reset Stop DStop DStandby 0 1 0 1 D2 contents lost, D1 and system contents retained, clock system reset Stop DStandby DStandby 1 1 0 1 D1 and D2 contents lost, system contents retained, clock system reset Standby DStandby DStandby 1 0 D1, D2 and system contents lost 0(1) 0(1) Comment 1. When returning from Standby, the SBF_D1 and SBF_D2 reflect the reset value. DocID029587 Rev 3 243/3178 270 Power control (PWR) 6.6.4 RM0433 Power management examples • Figure 26 shows VCORE voltage scaling behavior in Run mode. • Figure 27 shows VCORE voltage scaling behavior in Stop mode. • Figure 28 shows VCORE voltage regulator and voltage scaling behavior in Standby mode. • Figure 29 shows VCORE voltage scaling behavior in Run mode with D1 and D2 domains are in DStandby mode Example of VCORE voltage scaling behavior in Run mode Figure 26 illustrates the following system operation sequence example: 1. After reset, the system starts from HSI with VOS3. 2. The system performance is first increased to a medium-speed clock from the PLL with voltage scaling VOS2. To do this: 3. 4. 5. 6. a) Program the voltage scaling to VOS2. b) Once the VCORE supply has reached the required level indicated by VOSRDY, increase the clock frequency by enabling the PLL. c) Once the PLL is locked, switch the system clock. The system performance is then increased to high-speed clock from the PLL with voltage scaling VOS1. To do this: a) Program the voltage scaling to VOS1. b) Once the VCORE supply has reached the required level indicated by VOSRDY, increase the clock frequency. The system performance is then reduced to a medium-speed clock with voltage scaling VOS2. To do this: a) First decrease the system frequency. b) Then decrease the voltage scaling to VOS2. The next step is to reduce the system performance to HSI clock with voltage scaling VOS3. To do this: a) Switch the clock to HSI. b) Disable the PLL. c) Decrease the voltage scaling to VOS3. The system performance can then be increased to high-speed clock from the PLL. To do this: a) Program the voltage scaling to VOS1. b) Once the VCORE supply has reached the required level indicated by VOSRDY, increase the clock frequency by enabling the PLL. c) Once the PLL is locked, switch the system clock. When the system performance (clock frequency) is changed, VOS shall be set accordingly. otherwise the system might be unreliable. 244/3178 DocID029587 Rev 3 RM0433 Power control (PWR) Figure 26. Dynamic voltage scaling in Run mode 926 926 9&25( 926 926 9265'< 3//[21 FNBV\V FNBKFONBG FNBKFONBG FNBKFONBG 581 :DLW :DLW 9265'< 3// 581IURP+6, 581 :DLW 9265'< 581 :DLW :DLW :DLW 581 9265'< 9265'< 3// 5XQIURP3// 581IURP+6, 581 5XQIURP3// 06Y9 1. The status of the register bits at each step is shown in blue. Example of VCORE voltage scaling behavior in Stop mode Figure 27 illustrates the following system operation sequence example: 1. The system is running from the PLL in high-performance mode (VOS1 voltage scaling). 2. The CPU subsystem deallocates all the peripheral in the D2 domain that will first enter DStop mode. D2 system clock is stopped. The system still provides the highperformance system clock, hence the voltage scaling shall stay at VOS1 level. 3. In a second step, the CPU subsystem enters CStop mode, D1 domain enters DStop mode and the system enters Stop mode. The system clock is stopped and the hardware lowers the voltage scaling to the software preselected SVOS4 level. 4. The CPU subsystem is then woken up. The system exits from Stop mode, the D1 domain exits from DStop mode and the CPU subsystem exits from CStop mode. The hardware then sets the voltage scaling to VOS3 level and waits for the requested supply level to be reached before enabling the HSI clock. Once the HSI clock is stable, the system clock and the D1 system clock are enabled. 5. The CPU subsystem allocates a peripheral in the D2 domain. The D2 system clock is enabled. 6. The system performance is then increased. To do this: a) The software first sets the voltage scaling to VOS1. b) Once the VCORE supply has reached the required level indicated by VOSRDY, the clock frequency can be increased by enabling the PLL. c) Once the PLL is locked, the system clock can be switched. DocID029587 Rev 3 245/3178 270 Power control (PWR) RM0433 Figure 27. Dynamic voltage scaling behavior with D1, D2 and system in Stop mode 926 926 9&25( 6 926 6926 926 6926 9265'< H[WLBFBZNXS SZUBGBZNXS 3//Q21 FNBV\V FNBKFONBG FNBKFONBG FNBKFONBG 581 '581 '6723 '581 5XQIURP3// 6723 :DLW 9&25( &ORFN6WRSSHG :DLW +6, '581 '6723 '581 581 :DLW 9265'< 581IURP+6, 581 5XQIURP3// 06Y 9 1. The status of the register bits at each step is shown in blue. Example of VCORE voltage regulator and voltage scaling behavior in Standby mode Figure 28 illustrates the following system operation sequence example: 246/3178 1. The system is running from the PLL in high-performance mode (VOS1 voltage scaling). 2. The CPU subsystem deallocates all the peripherals in the D2 domain that will first enter DStandby mode.The D2 domain bus matrix clock is stopped and the power is switched off. The system performance is unchanged hence the voltage scaling does not change. 3. The CPU subsystem then enters to CStop mode, D1 domain enters DStandby mode and the system enters Standby mode. The system clock is stopped and the voltage regulator switched off. 4. The system is then woken up by a wakeup source. The system exits from Standby mode. The hardware sets the voltage scaling to the default VOS3 level and waits for the requested supply level to be reached before enabling the default HSI oscillator. Once the HSI clock is stable, the system clock and D1 subsystem clock are enabled. Since there are no allocated peripherals in the D2 domain, this domain remains in DocID029587 Rev 3 RM0433 Power control (PWR) DStop mode. The software shall then check the ACTVOSRDY is valid before changing the system performance. 5. 6. In a next step, increase the system performance. To do this: a) The software first increases the voltage scaling to VOS1 level b) Before enabling the PLL, it waits for the requested supply level to be reached by monitoring VOSRDY bit. c) Once the PLL is locked, the system clock can be switched. The CPU subsystem puts the D2 domain in DStandby mode. Figure 28. Dynamic Voltage Scaling D1, D2, system Standby mode 926 9&25( 926 9GGB' 6 926 6926 2II 9GGB' 926 2)) 6926 2)) 9265'< $&79265'< H[WLBFBZNXS SZUBGBZNXS 3//[21 FNBV\V FNBKFONBG FNBKFONBG FNBKFONBG '581 '581 '581 '581 '67$1'%< '581 5XQIURP3// '67$1'%< '67$1'%< '67$1'%< 3RZHUGRZQ 5(6(7 :DLW 9&25( :DLW +6, :DLW '581 :DLW :DLW $&7926 '6723 9265'< 3// 5'< '581 581IURP+6, '581 '6723 '581 '581 '67$1'%< '581 5XQIURP3// 06Y 9 1. The status of the register bits at each step is shown in blue. DocID029587 Rev 3 247/3178 270 Power control (PWR) RM0433 Example of VCORE voltage scaling behavior in Run mode with D1 and D2 domains in DStandby mode Figure 29 illustrates the following system operation sequence example: 248/3178 1. The system is running from the PLL with system in high performance mode (VOS1 voltage scaling). 2. The CPU subsystem deallocates all the peripherals in the D2 domain that will first enter DStandby mode. The D2 domain bus matrix clock is stopped and its power switched off. The system performance is unchanged hence the voltage scaling does not change. 3. The CPU subsystem then enters CStop mode and the D1 domain enters DStandby mode. The D1 domain bus matrix clock is stopped and its power switched off. At the same time the system enters Stop mode. The system clock is stopped and the hardware lowers the voltage scaling to the software preselected SVOS4 level. 4. The system is then woken up by a D3 autonomous mode wakeup event. The system exits from Stop mode. The hardware sets the voltage scaling to the default VOS3 level and waits for the requested supply level to be reached before enabling the HSI clock. Once the HSI clock is stable, the system clock is enabled. The system is running in D3 autonomous mode. 5. The D3 autonomous mode wakeup source is then cleared, causing the system to enter Stop mode. The system clock is stopped and the voltage scaling is lowered to the software preselected SVOS4 level. 6. The CPU subsystem is then woken up. The system exits from Stop mode, the D1 domain exits from DStandby mode and the CPU subsystem exits from CStop mode. The hardware sets the voltage scaling to the default VOS3 level and waits for the requested supply level to be reached before enabling the default HSI oscillator. Once the HSI clock is stable, the system clock and the D1 subsystem clock are enabled. The D2 domain remains in DStandby mode. DocID029587 Rev 3 RM0433 Power control (PWR) Figure 29. Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and D3 in autonomous mode 926 9&25( 926 6 926 6926 2II 926 9GGB' 9GGB' 9GGB' 9GGB' 6926 9265'< H[WLBFBZNXS SZUBGBZNXS H[WLBGBZNXS SZUBGBZNXS 3//[21 FNBV\V FNBKFONBG FNBKFONBG FNBKFONBG 581 '581 '67$1'%< '581 581IURP3// '67$1'%< '67$1'%< '6723 :DLW 9&25( :DLW +6, &ORFNVWRSSHG '67$1'%< '67$1'%< '581 581IURP +6, '67$1'%< '67$1'%< '6723 :DLW 9&25( &ORFNVWRSSHG :DLW +6, '581 '67$1'%< '581 581IURP +6, 06Y 9 1. The status of the register bits at each step is shown in blue. DocID029587 Rev 3 249/3178 270 Power control (PWR) 6.7 RM0433 Low-power modes Several low-power modes are available to save power when the CPU does not need to execute code (i.e. when waiting for an external event). It is up to the user application to select the mode that gives the best compromise between low power consumption, short startup time and available wakeup sources: 6.7.1 • Slowing down system clocks (see Section 8.5.6: System clock (sys_ck)) • Controlling individual peripheral clocks (see Section 8.5.11: Peripheral clock gating control) • Low-power modes – CSleep (CPU clock stopped) – CStop (CPU subsystem clock stopped) – DStop (Domain bus matrix clock stopped) – Stop (System clock stopped) – DStandby (Domain powered down) – Standby (System powered down) Slowing down system clocks In Run mode, the speed of the system clock ck_sys can be reduced. For more details refer to Section 8.5.6: System clock (sys_ck). 6.7.2 Controlling peripheral clocks In Run mode, the HCLKx and PCLKx for individual peripherals can be stopped by configuring at any time PERxEN bit in RCC_C1_xxxxENR or RCC_DnxxxxENR to reduce power consumption. To reduce power consumption in CSleep mode, the individual peripheral clocks can be disabled by configuring PERxLPEN bit in RCC_C1_xxxxLPENR or RCC_DnxxxxLPENR. For the peripherals still receiving a clock in CSleep mode, their clock can be slowed down before entering CSleep mode. 6.7.3 Entering low-power modes CPU subsystem CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M System Control register is set on Return from ISR. A domain can enter DStop or DStandby low-power mode when the CPU subsystem has an allocated peripheral in the domain and enters CStop mode, or when all D2 domain peripherals are deallocated. The system can enter Stop or Standby low-power mode when all EXTI wakeup sources are cleared and the other domains are in DStop or DStandby mode. 250/3178 DocID029587 Rev 3 RM0433 6.7.4 Power control (PWR) Exiting from low-power modes The CPU subsystem exits from CSleep mode through any interrupt or event depending on how the low-power mode was entered: • If the WFI instruction or Return from ISR was used to enter to low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the system. • If the WFE instruction is used to enter to low-power mode, the CPU exits from lowpower mode as soon as an event occurs. The wakeup event can be generated either by: – An NVIC IRQ interrupt. When SEVONPEND = 0 in the Cortex®-M7 System Control register, the interrupt must be enabled in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit in the NVIC interrupt clear pending register have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. When SEVONPEND = 1 in the Cortex®-M7 System Control register, the interrupt must be enabled in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and, when enabled, the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. – An event An EXTI line must be configured in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It might be necessary to clear the interrupt flag in the peripheral. The CPU subsystem exits from CStop, DStop and Stop modes by enabling an EXTI interrupt or event depending on how the low-power mode was entered (see above). The system can wakeup from Stop mode by enabling an EXTI wakeup, without waking up a CPU subsystem. In this case the system will operate in D3 autonomous mode. The CPU subsystem exits from DStandby mode by enabling an EXTI interrupt or event, regardless on how DStandby mode was entered. Program execution restarts from CPU local reset (such as a reset vector fetched from System configuration block (SYSCFG). The D2 domain can exit from DStop or DStandby mode when the CPU allocates a first peripheral in the domain. The CPU subsystem exits from Standby mode by enabling an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event. Program execution restarts in the same way as after a system reset (such as boot pin sampling, option bytes loading or reset vector fetched). DocID029587 Rev 3 251/3178 270 Power control (PWR) 6.7.5 RM0433 CSleep mode The CSleep mode applies only to the CPU subsystem. In CSleep mode, the CPU clock is stopped. The CPU subsystem peripheral clocks operate according to the values of PERxLPEN bits in RCC_C1_xxxxENR or RCC_DnxxxxENR. Entering CSleep mode The CSleep mode is entered according to Section 6.7.3: Entering low-power modes, when the SLEEPDEEP bit in the Cortex®-M System Control register is cleared. Refer to Table 30 for details on how to enter to CSleep mode. Exiting from CSleep mode The CSleep mode is exited according to Section 6.7.4: Exiting from low-power modes. Refer to Table 30 for more details on how to exit from CSleep mode. Table 30. CSleep mode CSleep mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 (Refer to the Cortex®-M System Control register.) – CPU NVIC interrupts and events cleared. Mode entry 252/3178 On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 (refer to the Cortex®-M System Control register.) – CPU NVIC interrupts and events cleared. Mode exit If WFI or return from ISR was used for entry: – Any Interrupt enabled in NVIC: Refer to Table 130: NVIC If WFE was used for entry and SEVONPEND = 0: – Any event: Refer to Section 20.5.3: EXTI CPU wakeup procedure If WFE was used for entry and SEVONPEND = 1: – Any Interrupt even when disabled in NVIC: refer to Table 130: NVIC or any event: refer to Section 20.5.3: EXTI CPU wakeup procedure Wakeup latency None DocID029587 Rev 3 RM0433 6.7.6 Power control (PWR) CStop mode The CStop mode applies only to the CPU subsystem. In CStop mode, the CPU clock is stopped. Most CPU subsystem peripheral clocks are stopped too and only the CPU subsystem peripherals having a PERxAMEN bit operate accordingly. In CStop mode, the CPU subsystem peripherals that have a kernel clock request can still request their kernel clock. For the peripheral that have a PERxAMEN bit, this bit shall be set to be able to request the kernel clock. Entering CStop mode The CStop mode is entered according to Section 6.7.3: Entering low-power modes, when the SLEEPDEEP bit in the Cortex®-M System Control register is set. Refer to Table 31 for details on how to enter to CStop mode. Exiting from CStop mode The CStop mode is exited according to Section 6.7.4: Exiting from low-power modes. Refer to Table 31 for more details on how to exit from CStop mode. Table 31. CStop mode CStop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 1 (Refer to the Cortex®-M System Control register.) – CPU NVIC interrupts and events cleared. – All CPU EXTI Wakeup sources are cleared. Mode entry On return from ISR while: – SLEEPDEEP = 1 and – SLEEPONEXIT = 1 (Refer to the Cortex®-M System Control register.) – CPU NVIC interrupts and events cleared. – All CPU EXTI Wakeup sources are cleared. Mode exit If WFI or return from ISR was used for entry: – EXTI Interrupt enabled in NVIC: Refer to Table 130: NVIC, for peripheral which are not stopped or powered down. If WFE was used for entry and SEVONPEND = 0: – EXTI event: Refer to Section 20.5.3: EXTI CPU wakeup procedure, for peripheral which are not stopped or powered down. If WFE was used for entry and SEVONPEND = 1: – EXTI Interrupt even when disabled in NVIC: refer to Table 130: NVIC or EXTI event: refer to Section 20.5.3: EXTI CPU wakeup procedure, for peripheral which are not stopped or powered down. Wakeup latency EXTI and RCC wakeup synchronization (see Section 8.4.7: Power-on and wakeup sequences) DocID029587 Rev 3 253/3178 270 Power control (PWR) 6.7.7 RM0433 DStop mode D1 domain and/or D2 domain enters DStop mode only when the CPU subsystem is in CStop mode and has allocated peripheral in the domain (see Table 32). In DStop mode the domain bus matrix clock is stopped. The Flash memory can enter low-power Stop mode when it is enabled through FLPS in PWR_CR1 register. This allows a trade-off between domain DStop restart time and low power consumption. Table 32. DStop mode overview Peripheral allocation CPU D1 domain D2 domain No peripheral allocated in D2 domain CRun or CSleep DRun DStop CStop DStop DStop CRun or CSleep DRun DRun CStop DStop DStop Peripheral allocated in D2 domain Comment CPU subsystem, keep D2 domain active. In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a kernel clock request are still able to operate. Entering DStop mode The DStop mode is entered according to Section 6.7.3: Entering low-power modes, when at least one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for the domain select Stop. Refer to Table 33 for details on how to enter DStop mode. If Flash memory programming is ongoing, the DStop mode entry is delayed until the memory access is finished. If an access to the domain bus matrix is ongoing, the DStop mode entry is delayed until the domain bus matrix access is complete. Exiting from DStop mode The DStop mode is exited according to Section 6.7.4: Exiting from low-power modes. Refer to Table 33 for more details on how to exit from DStop mode. When exiting from DStop mode, the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling depend on the system mode. 254/3178 • When the system did not enter Stop mode, the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling values are the same as when entering DStop mode. • When the system has entered Stop mode, the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling are reset. DocID029587 Rev 3 RM0433 Power control (PWR) Table 33. DStop mode DStop mode 6.7.8 Description Mode entry – The domain CPU subsystem enters CStop. – The CPU subsystem has an allocated peripheral in the D2 domain and enters CStop. – The CPU subsystem deallocated its last peripheral in the D2 domain. – The PDDS_Dn bit for the domain selects Stop mode. Mode exit – The domain CPU subsystem exits from CStop mode (see Table 31) – The CPU subsystem has an allocated peripheral in the D2 domain and exits from CStop mode (see Table 31) – The CPU subsystem allocates a first peripheral in the D2 domain. Wakeup latency EXTI and RCC wakeup synchronization (see Section 8.4.7: Power-on and wakeup sequences). Stop mode The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode, the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for any domain request Stop. In Stop mode, the system clock including a PLL and the D3 domain bus matrix clocks are stopped. When HSI or CSI is selected, the system oscillator operates according to the HSIKERON and CSIKERON bits in RCC_CR register. Other system oscillator sources are stopped. In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or DStandby mode. In Stop mode, the domain peripherals that use the LSI or LSE clock, and the peripherals that have a kernel clock request to select HSI or CSI as source, are still able to operate. In system Stop mode, the following features can be selected to remain active by programming individual control bits: • Independent watchdog (IWDG) The IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset (see Section 45.3 in Section 45: Independent watchdog (IWDG). • Real-time clock (RTC) This is configured via the RTCEN bit in the RCC Backup Domain Control Register (RCC_BDCR). • Internal RC oscillator (LSI RC) This is configured via the LSION bit in the RCC Clock Control and Status Register (RCC_CSR). • External 32.768 kHz oscillator (LSE OSC) This is configured via the LSEON bit in the RCC Backup Domain Control Register (RCC_BDCR). DocID029587 Rev 3 255/3178 270 Power control (PWR) RM0433 • Peripherals capable of running on the LSI or LSE clock. • Peripherals having a kernel clock request. • Internal RC oscillators (HSI and CSI) • This is configured via the HSIKERON and CSIKERON bits in the RCC Clock Control and Status Register (RCC_CSR). • The ADC or DAC can also consume power during Stop mode, unless they are disabled before entering this mode. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0. The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from system Stop mode (see Table 34). Table 34. Stop mode operation SVOS SVOS3 SVOS4 or SVOS5 Stop mode LPDS Voltage regulator operation Wake-up Latency 0 Main No additional wakeup time. 1 LP Voltage Regulator wakeup time from LP mode. x LP Voltage Regulator wakeup time from LP mode + voltage level wakeup time for SVOS4 or SVOS5 level to VOS3 level Entering Stop mode The Stop mode is entered according to Section 6.7.3: Entering low-power modes, when at least one PDDS_Dn bit n PWR CPU control register (PWR_CPUCR) for any domain request Stop. Refer to Table 35 for details on how to enter Stop mode. If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished. If an access to a bus matrix (AXI, AHB or APB) is ongoing, the Stop mode entry is delayed until the bus matrix access is finished. Note: Use a DSB instruction to ensure that outstanding memory transactions complete before entering stop mode. To allow peripherals having a kernel clock request to operate in Stop mode, the system must use SVOS3 level. Exiting from Stop mode The Stop mode is exited according to Section 6.7.4: Exiting from low-power modes. Refer to Table 35 for more details on how to exit from Stop mode. When exiting from Stop mode, the system clock, D3 domain bus matrix clocks and voltage scaling are reset. STOPF status flag in PWR CPU control register (PWR_CPUCR) indicates that the system has exited from Stop mode (see Table 29). 256/3178 DocID029587 Rev 3 RM0433 Power control (PWR) Table 35. Stop mode Stop mode Description Mode entry – When the CPU is in CStop mode and there is no active EXTI Wakeup source and Run_D3 = 0. – At least one PDDS_Dn bit for any domain select Stop. Mode exit – On a EXTI Wakeup. Wakeup latency System oscillator startup (when disabled). + EXTI and RCC wakeup synchronization. + Voltage Scaling refer to Table 34 (see Section 6.6.2: Voltage scaling) I/O states in Stop mode I/O pin configuration remain unchanged in Stop mode. 6.7.9 DStandby mode Like DStop mode, DStandby mode is based on the CPU subsystem CStop mode. However the domain VCORE supply is powered off. A domain enters DStandby mode only when the CPU subsystem is in CStop mode if peripherals are allocated in the domain A domain enters DStandby mode only when the CPU subsystem is in CStop mode if peripherals are allocated in the domain and the PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for the domain is configured accordingly. In DStandby mode, the domain is powered down and the domain RAM and register contents are lost. Entering DStandby mode The DStandby mode is entered according to Section 6.7.3: Entering low-power modes, when the PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for the Dn domain selects Standby mode. Refer to Table 36 for details on how to enter DStandby mode. If Flash memory programming is ongoing, the DStandby mode entry is delayed until the memory access is finished. If an access to the domain bus matrix is ongoing, the DStandby mode entry is delayed until the domain bus matrix access is finished. Note: When the CPU sets the PDDS_D2 bit to select Standby mode, the D2 domain enters DStandby mode (the CPU has no allocated peripherals in the D2 domain). Exiting from DStandby mode The DStandby mode is exited according to Section 6.7.4: Exiting from low-power modes. Refer to Table 36 for more details on how to exit from DStandby mode. Note: When the D2 domain is in DStandby mode and the CPU sets the domain PDDS_D2 bit to select Stop mode, the D2 domain remains in DStandby mode. The D2 domain will only exit DStandby when the CPU allocates a peripheral in the D2 domain. DocID029587 Rev 3 257/3178 270 Power control (PWR) RM0433 When exiting from DStandby mode, the domain CPU and peripherals are reset. However the state of the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling depends on the system mode: • When the system did not enter Stop mode, the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling are the same as when entering DStandby mode. • When the system has entered Stop or Standby mode, the CPU subsystem clocks, domain(s) bus matrix clocks and voltage scaling are reset. When the D2 domain exits from DStandby mode due to the CPU subsystem (i.e when allocating a first peripheral or when peripherals are allocated in the D2 domain and the CPU subsystem exits from CStop mode), the CPU shall verify that the domain has exited from DStandby mode. To ensure correct operation, it is recommended to follow the sequence below: 1. 2. First check that the domain bus matrix clock is available. The domain bus matrix clock state can be checked in RCC_CR register: – When RCC DnCKRDY = 0, the domain bus matrix clock is stalled. – If RCC DnCKRDY = 1, the domain bus matrix clock is enabled. Then wait for the domain has exited from DStandby mode. To do this, check the SBF_Dn flag in PWR CPU control register (PWR_CPUCR). The domain is powered and can be accessed only when SBF_Dn is cleared. Below an example of code: Loop write PWR SBF_Dn = 0 ; try to clear bit. read PWR SBF_Dn While 1 ==> loop Table 36. DStandby mode DStandby mode 258/3178 Description Mode entry – The domain CPU subsystem enters CStop. – The CPU subsystem has an allocated peripheral in D2 domain and enters CStop. – The CPU subsystem deallocated its last peripheral in the D2 domain. – The PDDS_Dn bits for the domain select Standby mode. – All WKUPF bits in Power Control/Status register (PWR_WKUPFR) are cleared. Mode exit – The CPU subsystem exits from CStop mode (see Table 31) – The CPU subsystem has an allocated peripheral in the D2 domain and exits from CStop mode (see Table 31) – The CPU subsystem allocates a first peripheral in the D2 domain. Wakeup latency EXTI and RCC wakeup synchronization. + Domain power up and reset. (see Section 8.4.7: Power-on and wakeup sequences) DocID029587 Rev 3 RM0433 6.7.10 Power control (PWR) Standby mode The Standby mode allows achieving the lowest power consumption. Like Stop mode, it is based on CPU subsystem CStop mode. However the VCORE supply regulator is powered off. The system D3 domain enters Standby mode only when the D1 and D2 domain are in DStandby. When the system D3 domain enters Standby mode, the voltage regulator is disabled. The complete VCORE domain is consequently powered off. The PLLs, HSI oscillator, CSI oscillator, HSI48 and the HSE oscillator are also switched off. SRAM and register contents are lost except for backup domain registers (RTC registers, RTC backup register and backup RAM), and Standby circuitry (see Section 6.4.4: Backup domain). In system Standby mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG) The IWDG is started by programming its Key register or by hardware option. Once started, it cannot be stopped except by a reset (see Section 45.3 in Section 45: Independent watchdog (IWDG). • Real-time clock (RTC) This is configured via the RTCEN bit in the backup domain control register (RCC_BDCR). • Internal RC oscillator (LSI RC) This is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE OSC) This is configured by the LSEON bit in the backup domain control register (RCC_BDCR). Entering Standby mode The Standby mode is entered according to Section 6.7.3: Entering low-power modes, when all PDDS_Dn bits in PWR CPU control register (PWR_CPUCR) for all domains request Standby. Refer to Table 38 for more details on how to enter to Standby mode. Exiting from Standby mode The Standby mode is exited according to Section 6.7.4: Exiting from low-power modes. Refer to Table 38 for more details on how to exit from Standby mode. The system exits from Standby mode when an external Reset (NRST pin), an IWDG Reset, a WKUP pin event, a RTC alarm, a tamper event, or a time stamp event is detected. All registers are reset after waking up from Standby except for power control and status registers (PWR control register 2 (PWR_CR2), PWR control register 3 (PWR_CR3)), SBF bit in PWR CPU control register (PWR_CPUCR), PWR wakeup flag register (PWR_WKUPFR), and PWR wakeup enable and polarity register (PWR_WKUPEPR). After waking up from Standby mode, the program execution restarts in the same way as after a system reset (boot option sampling, boot vector reset fetched, etc.). The SBF status flags in PWR CPU control register (PWR_CPUCR) registers indicate from which mode the system has exited (see Table 37). DocID029587 Rev 3 259/3178 270 Power control (PWR) RM0433 SBF_D2 SBF_D1 SBF STOPF Table 37. Standby and Stop flags 0 1 0 0 D1 domain exits from DStandby while system stayed in Run 0 1 0 1 D1 domain exits from DStandby, while system has been in or exits from Stop 1 0 0 0 D2 domain exits from DStandby while system stayed in Run 1 0 0 1 D2 domain exits from DStandby while system has been in or exits from Stop 1 1 0 0 D1 and D2 domain exit from DStandby while the system remains in Run mode 1 1 0 1 D1 and D2 domain exit from DStandby while the system is in Stop mode or is exiting this mode. 0 0 0 1 System has been in or exits from Stop 0(1) 1 0 System exits from Standby (1) 0 Description 1. When exiting from Standby the SBF_D1 and SBF_D2 reflect the reset value Table 38. Standby mode Standby mode Description Mode entry – The CPU subsystem is in CStop mode, and there is no active EXTI Wakeup source and RUN_D3 = 0. – All PDDS_Dn bits for all domains select Standby. – All WKUPF bits in Power Control/Status register (PWR_WKUPFR) are cleared. Mode exit – WKUP pins rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. Wakeup latency System reset phase (see Section 8.4.2: System reset) I/O states in Standby mode In Standby mode, all I/O pins are high impedance without pull, except for: 260/3178 • Reset pad (still available) • RTC_AF1 pin if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out • WKUP pins (if enabled). The WKUP pin pull configuration can be defined through WKUPPUPD register bits in PWR wakeup enable and polarity register (PWR_WKUPEPR). DocID029587 Rev 3 RM0433 Power control (PWR) 6.8 PWR register description The PWR registers can be accessed in word, half-word and byte format, unless otherwise specified. 6.8.1 PWR control register 1 (PWR_CR1) Address offset: 0x000 Reset value: 0xF000 C000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 SVOS rw 13 12 11 10 9 8 Res. Res. Res. Res. FLPS DBP rw rw rw Bits 31:19 7 6 5 PLS rw rw rw 18 17 ALS 16 AVDEN rw rw rw 4 3 2 1 0 PVDE Res. Res. Res. LPDS rw rw Reserved, must be kept at reset value. Bits 18:17 ALS: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. 00: 1.7 V 01: 2.1 V 10: 2.5 V 11: 2.8 V Bit 16 AVDEN: Peripheral voltage monitor on VDDA enable 0: Peripheral voltage monitor on VDDA disabled. 1: Peripheral voltage monitor on VDDA enabled Bits 15:14 SVOS: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. 00: Reserved 01: SVOS5 Scale 5 10: SVOS4 Scale 4 11: SVOS3 Scale 3 (default) Bits 13:10 Reserved, must be kept at reset value. Bit 9 FLPS: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. 0: Flash memory remains in normal mode when D1 domain enters DStop (quick restart time). 1: Flash memory enters low-power mode when D1 domain enters DStop mode (low-power consumption). DocID029587 Rev 3 261/3178 270 Power control (PWR) RM0433 Bit 8 DBP: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC, RTC Backup registers and backup SRAM disabled 1: Access to RTC, RTC Backup registers and backup SRAM enabled Bits 7:5 PLS: Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. 000: 1.95 V 001: 2.1 V 010: 2.25 V 011: 2.4 V 100: 2.55 V 101: 2.7 V 110: 2.85 V 111: External voltage level on PVD_IN pin, compared to internal VREFINT level. Note: Refer to Section “Electrical characteristics” of the product datasheet for more details. Bit 4 PVDE: Programmable voltage detector enable 0: Programmable voltage detector disabled. 1: Programmable voltage detector enabled Bits 3:1 Reserved, must be kept at reset value. Bit 0 LPDS: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) 0: Voltage regulator in Main mode (MR) when SVOS3 is selected for Stop mode 1: Voltage regulator in Low-power mode (LPR) when SVOS3 is selected for Stop mode 6.8.2 PWR control status register 1 (PWR_CSR1) Address offset: 0x004 Reset value: 0x0000 4000. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AVDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTVOS ACTVOSR DY Res. Res. Res. Res. Res. Res. Res. Res. PVDO Res. Res. Res. Res. r r r 262/3178 r DocID029587 Rev 3 RM0433 Power control (PWR) Bits 31:17 Reserved, must be kept at reset value. Bit 16 AVDO: Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. 0: VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits. 1: VDDA is lower than the AVD threshold selected with the ALS[2:0] bits Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set. Bits 15:14 ACTVOS: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the voltage regulator. Bit 13 ACTVOSRDY: Voltage levels ready bit for currently used VOS This bit is set to 1 by hardware when the voltage regulator is disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). 0: Voltage level invalid, above or below current VOS selected level. 1: Voltage level valid, at current VOS selected level. Bits 12:5 Reserved, must be kept at reset value. Bit 4 PVDO: Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. 0: VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the PLS[2:0] bits. 1: VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0] bits. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set. Bits 3:0 6.8.3 Reserved, must be kept at reset value. PWR control register 2 (PWR_CR2) Address offset: 0x008 Reset value: 0x0000 0000 This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain. After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. TEMPH TEMPL VBATH VBATL Res. Res. Res. BRRDY r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MONEN Res. Res. Res. BREN rw DocID029587 Rev 3 r rw 263/3178 270 Power control (PWR) Bits 31:24 RM0433 Reserved, must be kept at reset value. Bit 23 TEMPH: Temperature level monitoring versus high threshold 0: Temperature below high threshold level. 1: Temperature equal or above high threshold level. Bit 22 TEMPL: Temperature level monitoring versus low threshold 0: Temperature above low threshold level. 1: Temperature equal or below low threshold level. Bit 21 VBATH: VBAT level monitoring versus high threshold 0: VBAT level below high threshold level. 1: VBAT level equal or above high threshold level. Bit 20 VBATL: VBAT level monitoring versus low threshold 0: VBAT level above low threshold level. 1: VBAT level equal or below low threshold level. Bits 19:17 Reserved, must be kept at reset value. Bit 16 BRRDY: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. 0: Backup regulator not ready. 1: Backup regulator ready. Bits 15:5 Reserved, must be kept at reset value. Bit 4 MONEN: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. 0: VBAT and temperature monitoring disabled. 1: VBAT and temperature monitoring enabled. Bits 3:1 Reserved, must be kept at reset value. Bit 0 BREN: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. 0: Backup regulator disabled. 1: Backup regulator enabled. 6.8.4 PWR control register 3 (PWR_CR3) Address offset: 0x00C Reset value: 0x0000 0006 (reset only by POR only, not reset by wakeup from Standby mode and RESET pad). The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes. Programming data corresponding to an invalid combination of LDOEN and BYPASS bits (see Table 26) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration 264/3178 DocID029587 Rev 3 RM0433 Power control (PWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. USB33RDY USBREGEN USB33DEN Res. Res. Res. Res. Res. Res. Res. Res. r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. VBRS VBE Res. Res. Res. Res. Res. SCUEN LDOEN BYPASS will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value. rw rw rw rw rw Bits 31:27 Reserved, must be kept at reset value. Bit 26 USB33RDY: USB supply ready. 0: USB33 supply not ready. 1: USB33 supply ready. Bit 25 USBREGEN: USB regulator enable. 0: USB regulator disabled. 1: USB regulator enabled. Bit 24 USB33DEN: VDD33USB voltage level detector enable. 0: VDD33USB voltage level detector disabled. 1: VDD33USB voltage level detector enabled. Bits 23:10 Reserved, must be kept at reset value. Bit 9 VBRS: VBAT charging resistor selection 0: Charge VBAT through a 5 kΩ resistor. 1: Charge VBAT through a 1.5 kΩ resistor. Bit 8 VBE: VBAT charging enable 0: VBAT battery charging disabled. 1: VBAT battery charging enabled. Bits 7:3 Reserved, must be kept at reset value. Bit 2 SCUEN: Supply configuration update enable This bit is read-only: 0: Supply configuration update locked. 1: Single write enabled to Supply configuration (LDOEN and BYPASS) Bit 1 LDOEN: Low drop-out regulator enable 0: Low drop-out regulator disabled. 1: Low drop-out regulator enabled (default) Bit 0 BYPASS: Power management unit bypass 0: Power management unit normal operation. 1: Power management unit bypassed, voltage monitoring still active. DocID029587 Rev 3 265/3178 270 Power control (PWR) 6.8.5 RM0433 PWR CPU control register (PWR_CPUCR) This register allows controlling CPU power. Address offset: 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. RUN_D3 Res. CSSF SBF_D2 SBF_D1 SBF SOPFF Res. Res. PDDS_D3 PDDS_D2 PDDS_D1 Reset value: 0x0000 0000 rw r r r r rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 RUN_D3: Keep system D3 domain in Run mode regardless of the CPU subsystem modes 0: D3 domain follows CPU subsystem modes. 1: D3 domain remains in Run mode regardless of CPU subsystem modes. Bit 10 Reserved, must be kept at reset value. Bit 9 CSSF: Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. 0: No effect. 1: STOPF, SBF, SBF_D1, and SBF_D2 flags are cleared. Bit 8 SBF_D2: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. 0: D2 domain has not been in DStandby mode 1: D2 domain has been in DStandby mode. Bit 7 SBF_D1: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode. 0: D1 domain has not been in DStandby mode 1: D1 domain has been in DStandby mode. Bit 6 SBF: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CSSF bit 0: System has not been in Standby mode 1: System has been in Standby mode Bit 5 STOPF: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. 0: System has not been in Stop mode 1: System has been in Stop mode Bits 4:3 266/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Power control (PWR) Bit 2 PDDS_D3: System D3 domain Power Down Deepsleep. This bit allows defining the Deepsleep mode for System D3 domain. 0: Keep Stop mode when D3 domain enters Deepsleep. 1: Allow Standby mode when D3 domain enters Deepsleep. Bit 1 PDDS_D2: D2 domain Power Down Deepsleep. This bit allows defining the Deepsleep mode for D2 domain. 0: Keep DStop mode when D2 domain enters Deepsleep. 1: Allow DStandby mode when D2 domain enters Deepsleep. Bit 0 PDDS_D1: D1 domain Power Down Deepsleep selection. This bit allows defining the Deepsleep mode for D1 domain. 0: Keep DStop mode when D1 domain enters Deepsleep. 1: Allow DStandby mode when D1 domain enters Deepsleep. 6.8.6 PWR D3 domain control register (PWR_D3CR) This register allows controlling D3 domain power. Address offset: 0x018 Reset value: 0x0000 4000 (Following reset VOSRDY will be read 1 by software). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VOS VOSRDY Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw r Bits 31:16 Reserved, must be kept at reset value. Bits 15:14 VOS: Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: – When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. – When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling. 00: Reserved (Scale 3 selected). 01: Scale 3 (default) 10: Scale 2 11: Scale 1 Bit 13 VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). 0: Not ready, voltage level below VOS selected level. 1: Ready, voltage level at or above VOS selected level. Bits 12:0 Reserved, must be kept at reset value. DocID029587 Rev 3 267/3178 270 Power control (PWR) 6.8.7 RM0433 PWR wakeup clear register (PWR_WKUPCR) Address offset: 0x020 Reset value: 0x0000 0000 (reset only by system reset, not reset by wakeup from Standby mode) 5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared). 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:6 WKUPC1 26 Res. WKUPC2 27 Res. WKUPC3 28 Res. WKUPC4 29 Res. WKUPC5 30 Res. WKUPC6 31 Res. rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Reserved, always read as 0. Bits 5:0 WKUPCn+1: Clear Wakeup pin flag for WKUPn+1. These bits are always read as 0. 0: No effect 1: Writing 1 clears the WKUPFn+1 Wakeup pin flag (bit is cleared to 0 by hardware) 6.8.8 PWR wakeup flag register (PWR_WKUPFR) Address offset: 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WKUPF6 WKUPF5 WKUPF4 WKUPF3 WKUPF2 WKUPF1 Reset value: 0x0000 0000 (reset only by system reset, not reset by wakeup from Standby mode) r r r r r r Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 WKUPn+1: Wakeup pin WKUPn+1 flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). 0: No wakeup event occurred 1: A wakeup event was received from WKUPn+1 pin 268/3178 DocID029587 Rev 3 RM0433 Power control (PWR) 6.8.9 PWR wakeup enable and polarity register (PWR_WKUPEPR) Address offset: 0x028 Res. rw rw 9 8 rw rw rw rw 7 6 rw rw rw rw rw 5 4 Res. Res. rw 16 rw rw rw rw 3 2 1 0 rw rw rw rw rw WKUPPUPD1 Res. rw WKUPEN1 10 WKUPEN2 rw 11 WKUPEN3 rw 19 WKUPPUPD2 12 17 WKUPEN4 13 18 WKUPEN5 14 21 WKUPPUPD3 15 20 WKUPEN6 Res. 22 WKUPPUPD4 Res. 23 WKUPP1 Res. 24 WKUPPUPD5 Res. 27 WKUPP2 28 WKUPPUPD6 29 WKUPP3 25 WKUPP4 30 Bits 31:28 26 WKUPP5 31 WKUPP6 Reset value: 0x0000 0000 (reset only by system reset, not reset by wakeup from Standby mode) Reserved, must be kept at reset value. Bits 27:16 WKUPPUPD[truncate(n/2)-7): Wakeup pin pull configuration for WKUP(truncate(n/2)-7) These bits define the I/O pad pull configuration used when WKUPEN(truncate(n/2)-7) = 1. The associated GPIO port pull configuration shall be set to the same value or to ‘00’. The Wakeup pin pull configuration is kept in Standby mode. 00: No pull-up 01: Pull-up 10: Pull-down 11: Reserved Bits 15:14 Reserved, must be kept at reset value. Bits 13:8 WKUPPn-7: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bits 7:6 Reserved, must be kept at reset value. Bits 5:0 WKUPENn+1: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. 0: An event on WKUPn+1 pin does not wakeup the system from Standby mode. 1: A rising or falling edge on WKUPn+1 pin wakes-up the system from Standby mode. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge. DocID029587 Rev 3 269/3178 270 0x028 PWR_WKUPEPR 0x030 Reset value 270/3178 0 0 0 0 0 0 0 0 0 0 0 Reserved DocID029587 Rev 3 WKUPP3 WKUPP2 WKUPP1 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. WKUPF4 WKUPF3 WKUPF2 WKUPF1 0 0 0 0 0 0 WKUPEN4 WKUPEN3 WKUPEN2 WKUPEN1 Reset value WKUPF5 Res. Res. Res. Res. Res. Res. Res. Res. WKUPC5 WKUPC4 WKUPC3 WKUPC2 WKUPC1 Reset value WKUPC6 SBF STOPF 0 0 0 0 0 PDDS_D3 PDDS_D2 PDDS_D1 SCUEN LDOEN BYPASS 0 Res. Res. BREN Res. Res. Res. Res. Res. PVDO Res. Res. 0 Res. MONEN Res. Res. DBP Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. VBE Res. LPDS Res. Res. Res. PVDE PLS Res. SBF_D1 FLPS Res. Res. 0 Res. Res. Res. Res. 0 WKUPEN5 Res. SBF_D2 Res. Res. Res. Res. ACTVOSRDY AVDEN 0 WKUPF6 Res. Res. VBRS 0 Res. Res. Res. CSSF Res. Res. Res. Res. ACTVOS Res. 0 WKUPEN6 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Reset value Res. Res. RUN_D3 Res. Res. 1 Res. WKUPP4 0 Res. VOSRDY Res. 0 Res. 1 Res. Res. 1 Res. VOS Res. 0 Res. 0 Res. 1 WKUPP5 Res. Res. Res. AVDO Res. Res. Res. Res. Res. SVOS WKUPP6 0 Res. Reset value Res. 0 Res. BRRDY Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Reset value Res. Res. Res. Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALS Res. Res. VBATL Res. Res. VBATH Res. Res. TEMPL Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value WKUPPUPD1 WKUPPUPD2 WKUPPUPD3 WKUPPUPD4 Res. TEMPH USB33DEN Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. USBREGEN Res. Res. USB33RDY 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Reset value WKUPPUPD5 PWR_WKUPFR WKUPPUPD6 PWR_WKUPCR Res. PWR_D3CR Res. 0x018 Res. 0x014 Res. PWR_CPUCR Res. 0x010 Res. PWR_CR3 Res. 0x00C Res. PWR_CR2 Res. 0x008 Res. 0x024 PWR_CSR1 Res. 0x004 Res. 0x020 PWR_CR1 Res. 0x000 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 6.8.10 Res. Power control (PWR) RM0433 PWR register map Table 39. Power control register map and reset values 0 0 1 1 0 0 0 0 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 7 Low-power D3 domain Low-power D3 domain This section describes, through an example, how to use the D3 domain to implement lowpower applications. 7.1 Introduction The first part of the description explains how the EXTI, RCC and PWR blocks interact with each other and with the other system blocks. A detailed explanation on how the DMAMUX2 can be used to free the CPU is also provided. The second part explains how to use the Autonomous mode to perform simple data transfers through an example of LINUART1 transmission. Register programming is detailed only for the blocks related to the Autonomous mode. 7.2 EXTI, RCC and PWR interconnections Figure 30 shows the main EXTI, RCC and PWR interconnections. DocID029587 Rev 3 271/3178 282 Low-power D3 domain RM0433 Figure 30. EXTI, RCC and PWR interconnections )/$6+BEXV\ $KE%ULGJHBG[BEXV\ $SE%ULGJHBG[BEXV\ 5&& ' &38 19,& ' 3HULSKHUDO LQWHUUXSWV ,UT ,UT FSXBGHHSVOHHS 3HULSKHUDOV ,3V LQWHUUXSW UFFBIFONBFSX (;7, ZDNHXS FSXBLWBH[WLBSHU ZDNHXS 96: ,3V 3HULSKHUDOV 6LJQDO 6LJQDO 57& &RQILJXUDEOH (YHQWLQSXWV ' 3HULSKHUDOV ,3V LQWHUUXSW 'LUHFW(YHQWLQSXWV FSXBLWBH[WLBSHU [ GBLWBH[WLBSHU GBLWBH[WLBSHU Q '3HQG&OHDU> @ ,UT ,UT ' UFFBIFONBG GPDPX[BHYW[ OSWLP> @BRXW 3:5 H[WLBFSXBZNXS H[WLBGBZNXS 6LJQDO :.83 FSXBSHUBDOORFBG FSXBSHUBDOORFBG SZUBG> @BZNXS 'B'((36/((3 GBGHHSVOHHS 06Y 9 272/3178 DocID029587 Rev 3 RM0433 7.2.1 Low-power D3 domain Interrupts and wakeup Three kinds of signals are exchanged between the peripherals. They can be used to wake up the system from Stop mode: • Wakeup events (or asynchronous interrupts) Some peripherals can generate interrupt events, even if their bus interface clock is not present. These interrupt events are called wakeup events (or asynchronous interrupts). Example: i2c1_wkup, usart1_wkup and lptim1_wkup. • Signals Some peripherals generate a pulse instead of an interrupt signal. These pulses are called signals. Examples: lptim2_out and lptim3_out. • Interrupts Contrary to signals, the interrupts should be cleared by a CPU or any other bus master, either by clearing the corresponding event bit in the peripheral register or by updating the FIFO interrupt level. All the interrupts associated to system peripherals are directly connected to the NVIC, except for the peripherals which are able to wake up the system from Stop mode or the CPU from CStop. In this latter case, the interrupts, signals or wakeup events are connected to the NVIC via the EXTI. Example: spi1_it, tim1_brk_it and tim1_upd_it. The interrupt and wakeup sources that require to be cleared in the peripheral itself are connected to EXTI Direct Event inputs. The EXTI does not manage any CPU status pending bit. The peripherals signals are connected to EXTI Configurable Event inputs. These EXTI inputs provide a CPU status pending bit which needs to be cleared by the application. 7.2.2 Block interactions Interaction between EXTI and PWR blocks The EXTI delivers wakeup requests signals (exti_c_wkup, exti_d3_wkup) to the PWR controller. These signals are activated according to the state of the interrupts, signals or wakeup events connected to the EXTI. These wakeup requests are used by the PWR controller to supply the domain who needs to handle the activated wakeup event generated by the peripherals. Interaction between PWR and RCC blocks The PWR block controls the VCORE supply according to the system operating mode (CRun, CSleep or CStop). The PWR block also controls the power switches (ePODs) that delivers VCORE supply to D1 and D2 domains. The RCC block controls the clock generation in accordance with the system operating mode. It is also responsible for reset generation. DocID029587 Rev 3 273/3178 282 Low-power D3 domain RM0433 To synchronize the system mode transitions, the RCC block is tightly coupled with the PWR controller: • The RCC informs the PWR controller when peripherals located in Dx domain are allocated by the CPU (c_per_alloc_d2, c_per_alloc_d1). • The RCC also warns the PWR block when a domain clock is activated/deactivated. These signals are used in case of domain transition from DRun to DStop or DStandby. In this case, the PWR controller waits until the domain clock has been gated, before switching down this domain. • Similarly, the PWR controller informs the RCC about the VCORE supply status of each domain (pwr_d[1:3]_wkup). This information is used by the RCC when a domain transition from DStop or DStandby to DRun occurs. Interaction between EXTI and D3 domain All the wakeup event inputs received by the EXTI from the peripherals located in D3 domain are forwarded back to the D3 domain after system clock re-synchronization. These events are used by the D3 domain to perform autonomous operations without activating the CPU. The EXTI D3_PenClear[3:0] inputs received from the D3 domain are used to acknowledge the ongoing wakeup requests generated by peripherals located in the D3 domain. The D3_PenClear[3:0] inputs allow switching the system D3 domain from Run to Stop mode. 7.2.3 Role of D3 domain DMAMUX2 The DMAMUX2 implemented in the D3 domain allows chaining BDMA transfers. BDMA requests are synchronized thanks to trigger events (dmamux2_evtx) which can be generated when the expected amount of data has been transferred. These events can also trigger DMAMUX2 request generators (REQ_GEN[3:0]), and thus chain several BDMA transfers. In fact REQ_GEN[3:0] can be triggered indirectly by all the wakeup events generated by all D3 domain peripherals. Like LPTIM5 and LPTIM4 outputs, dmamux2_evt7 and dmamux2_evt6 events are connected to the EXTI. They can be used to switch the D3 domain from DRun to DStop mode when the task requested by the wakeup event is complete. 274/3178 DocID029587 Rev 3 RM0433 7.3 Low-power D3 domain Low-power application example based on LPUART1 transmission This section illustrates, through an example, the benefit of the D3 domain usage on power consumption. To help the user program the device, only the key register settings are given herein. Refer to Section 8: Reset and Clock Control (RCC) and Section 6: Power control (PWR)for additional details. 7.3.1 Memory retention The D3 domain features 64 Kbytes of SRAM (SRAM4), which can be used to retain data while the D1 and D2 domains enter DStandby mode. This feature can be used in several use-cases: Note: • to retain the application code in order to recover properly from DStandby • to retain the data from/to a sensor when the CPU enters CStop with D1 or D2 domain in DStandby) between two consecutive operations. SRAM4 remains available as long as the system is not in Standby mode. If the system is in Standby mode, it is still possible to use the BKUP_SRAM. However, its size is limited to 4 Kbytes. 7.3.2 Memory-to-peripheral transfer using LPUART1 interface Example description Figure 31 shows the proposed implementation. At a regular time interval given by LPTIM4, the CPU wakes up from CStop mode (which domain is in DStandby). When the CPU is in Run mode, it prepares the data to be transmitted via LPUART1, transfers them to SRAM4, and goes back to CStop. The D3 domain is configured to perform data transfers via LPUART1 and go back to Stop mode when the transfer is complete. The LPTIM4 interface is used to wake up the system from Standby at regular time intervals. the CPU must then perform the following operations: 1. Recover the application from the system Standby mode (RECO). 2. Process the new data to be sent via LPUART1 (PROC). 3. Transfer the data into SRAM4 (XFER). 4. Configure the DMAMUX2, the BDMA, the LPUART1, and the RCC (CFG). 5. Configure the EXTI (CFG). 6. Configure the PWR block to allow D1 domain to go to DStandby (STP). 7. Set the CPU to Stop mode. The D3 domain executes the following tasks in Autonomous mode: 1. Transfer the data from SRAM4 to LPUART1, using BDMA. 2. When the LPUART1 interface indicates that the last byte has been transferred, the D3 domain is switched to Stop mode. DocID029587 Rev 3 275/3178 282 Low-power D3 domain RM0433 Figure 31. Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain in Autonomous mode '6WDWH 2)) '5XQ 'SURFHVVLQJ 6\VWHP' 6WDWH '6WDQGE\ 5XQ 673 '5XQ 0(0WR/38$577UDQVIHU 2)) ;)(5 5(&2 352& 673 &38SURFHVVLQJ ;)(5 6757 &)* 352& OSWLPBZNXS '6WDQGE\ 0(0WR/38$57 6WRS 5XQ 6757 3RZHURQUHVHWVWDUWXS &)* 3HULSKHUDOVLQLWLDOL]DWLRQ %'0$'0$08;3:5/38$57(;7, 5(&2 5HFRYHUIURPWKH&6WDQGE\ ;)(5 7UDQVIHURISURFHVVHGGDWDWR65$0 352& 'DWDSURFHVVLQJ 673 &RQWURORI(;7,%'0$DQG/38$57SULRUWRJRWR&6723 06Y 9 Note: In the example described in this section, the D3 domain cannot be kept in Run mode when D1 and D2 domains are in DStop/DStandby by using the RUN_D3 bit of PWR_CPUCR register. RUN_D3 will force the D3 domain to Run mode, but it will not be able to go back to Stop on its own. If the application needs to toggle the D3 domain between Stop and Run modes, then the Run mode must be triggered by a wakeup event so that the D3 domain can clear this event is needed. RCC programming In this example, the CPU sub-system also includes the peripherals of D3 domain that are used for the data transfer, that is BDMA, DMAMUX2, LPUART1 and LPTIM4. These peripherals must be programmed in Autonomous mode, in order to operate even when the CPU is in CSTOP mode. LPUART1 can use its own APB clock as kernel clock. Since the system will not enter Stop mode before LPUART1 has completed data transfer, PLLx can be used to provide clocks to the peripherals. PWR programming In this example, the PWR block must be programmed in order to: Note: 276/3178 • Prevent system D3 domain to enter Standby mode when the data transfer is complete. • Allow the D1 domain to enter DStandby. • Define the working voltage according to system modes. D3 domain could enter Standby as well, but in this case the LPTIM4 could not be used to wake up the system and the AWU should be used instead. In addition, everything must be reprogrammed when the system wakes up. DocID029587 Rev 3 RM0433 Low-power D3 domain EXTI programming The EXTI block must be configured to provide the following services: • Keep D3 domain running when D1 domain is in DStandby. This will be done by a software event. • Set the device to Stop mode when the data transfer via LPUART1 is complete. • Wake up the product from Stop when LPTIM4 time interval has elapsed. The EXTI block is configured once before performing the first data transfer. For incoming data transfers, the programmed configuration remains unchanged; only some events need to be triggered or acknowledged. Note: The CPU uses the event input number 0 to generate a software event. LPTIM4 wakeup signal is connected to event input number 52 (direct event input). All other event inputs must be disabled: EXTI_RTSRx_TRy = ‘0’ and EXTI_FTSRx_TRy = ‘0’. To generate a wakeup event for D3 domain, the CPU must write SWIER0 bit of EXTI_SWIER1 to ‘1’. The GPIO connected to this event input must not toggle in order to avoid spurious wakeup. To prevent the GPIO to disturb, the following sequence can be done: BDMA and DMAMUX2 programming Two BDMA channels are required to execute data transfers via LPUART1. • A BDMA channel, such as channel 0, is used to transfer data from SRAM4 to LPUART1, using the TXE flag. • The second BDMA channel role is to switch the D3 domain to Stop mode. For that purpose, DMAMUX2 request generator channel 0 (REQ_GEN0) and DMAMUX2 channel 7 synchronization block (SYNC7) are used in conjunction with BDMA channel 7. BDMA channel 0 does not use DMAMUX2 trigger capabilities. Refer to Table 41 for initialization details. BDMA channel 7 uses REQ_GEN0 to generate BDMA requests. The generation of BDMA requests is triggered by the LPUART1 transmit interrupt (lpuart1_tx_it). The LPUART1 interface generates lpuart1_tx_it interrupt when the transmit complete event is detected. The BDMA then clears the pending interrupt by performing a write operation to the LPUART1. The SYNC7 block is programmed in Free-running mode. It generates a pulse on its dmamux2_evt7 output when the BDMA request generated by the REQ_GEN0 is complete. dmamux2_evt7 signal is used by the EXTI to switch back the D3 domain to Stop mode. Figure 40 shows the active signal paths via DMAMUX2. The grayed blocks represent the unused paths. DocID029587 Rev 3 277/3178 282 Low-power D3 domain RM0433 Table 40. BDMA and DMAMUX2 interconnection /38$57 '0$08; GPDPX[BUHT> @ GPDPX[BUHT OSXDUWBW[BGPD 6<1& GPDPX[BUHTBRXW &+ 7&B5HT&QWBFK GPDPX[BUHT> @ %'0$ GPDPX[BUHT> @ GPDPX[BUHT 5(4B*(1 GPDPX[BUHTBRXW 6<1& ,7B7 (;7, &+ GPDPX[BHYW 'B3HQG&OHDU>@ GPDPX[BWUJ> @ GPDPX[BV\QF> @ OSXDUWBW[BLW 0VY9 Table 41 explain how to program BDMA and DMAMUX2 key functions. The way errors are handled is not described. Table 41. BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) Peripherals Register content Related actions DMAREQ_ID of DMAMUX2_C0CR = ‘7’ SE of DMAMUX2_C0CR = ‘0’ DMAMUX2 EGE of DMAMUX2_C0CR = ‘0’ SYNC0 NBREQ of DMAMUX2_C0CR = ‘0’ Selects LPUART_TX BDMA request. Disables block synchronization. No event generation. Generates an event every BDMA transfer (free running mode). DMAREQ_ID of DMAMUX2_C7CR = ‘0’ SE of DMAMUX2_C7CR = ‘0’ DMAMUX2 EGE of DMAMUX2_C7CR = ‘1’ SYNC7 NBREQ of DMAMUX2_C7CR = ‘0’ Selects of REQ_GEN0 as BDMA request. Disables block synchronization. Enables event generation. Generates an event every BDMA transfer (free running mode). SIG_ID of DMAMUX2_RG0CR = ‘0d24’ DMAMUX2 GPOL of DMAMUX2_RG0CR = ‘0b01’ REQ_GEN0 GNBREQ of DMAMUX2_RG0CR = ‘0’ GE of DMAMUX2_RG0CR = ‘1’ Selects LPUART TX interrupt as trigger. Trigger on rising edge of the event. Generates only one BDMA request. Enables generator. 278/3178 DocID029587 Rev 3 RM0433 Low-power D3 domain Table 41. BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) (continued) Peripherals Register content BDMA CH0 NDT bits of BDMA_CNDTR0 = DatNber PA of BDMA_CPAR0 = &LPUART1_TDR MA of BDMA_CMAR0 = &DatBuff DIR of BDMA_CCR0 = ‘1’ CIRC of BDMA_CCR0 = ‘0’ PINC of BDMA_CCR0 = ‘0’ MINC of BDMA_CCR0 = ‘1’ PSIZE of BDMA_CCR0 = ‘0’ MSIZE of BDMA_CCR0 = ‘1’ MEM2MEM of BDMA_CCR0 = ‘0’ Number of data to transfer. Address of LPUART1_TDR. Address of memory buffer of SRAM4. Read from memory. Circular mode disabled. Peripheral increment disabled. Memory increment enabled. Peripheral size = 8 bits. Memory size = 8 bits. Memory to memory disabled. NDT bits of BDMA_CNDTR7 = ‘1’ PA of BDMA_CPAR7 = &LPUART1_ICR MA of BDMA_CMAR7 = &DatClrTC Only one data transferred. Address of LPUART1_ICR (Interrupt Flag Clear Reg.). Address of a variable located into SRAM4. This variable must contain 0x0040 in order to clear the TC flag. Read from memory. Circular mode disabled. Peripheral increment disabled. Memory increment disabled. Peripheral size = 32 bits. Memory size = 32 bits. Memory to memory disabled. BDMA CH7 Related actions DIR of BDMA_CCR7 = ‘1’ CIRC of BDMA_CCR7 = ‘0’ PINC of BDMA_CCR7 = ‘0’ MINC of BDMA_CCR7 = ‘1’ PSIZE of BDMA_CCR7 = 2 MSIZE of BDMA_CCR7 = 2 MEM2MEM of BDMA_CCR7 = ‘0’ LPTIM4 programming When LPTIM4 wakeup event occurs, the CPU reboots and D3 domain mode is also set to Run mode. An interrupt issued by LPTIM4 is pending on the CPU NVIC. LPTIM4 interrupt handler must acknowledge this LPTIM4 interrupt by writing ARRMCF bit in LPTIM4_ICR register to ‘1’ (LPTIM4_Ack). LPUART programming In the use-case described herein, the capability of the LPUART1 to request the kernel clock according to some events is not used. LPUART1 is programmed so that is generates a BDMA request when its TX-FIFO is not full. LPUART1 also generates an interrupt when the TX-FIFO and its transmit shift register are empty. This interrupt is used to switch the D3 domain to Stop mode. Table 42 gives the key settings concerning the handling of Stop mode for LPUART1. DocID029587 Rev 3 279/3178 282 Low-power D3 domain RM0433 Table 42. LPUART1 Initial programming (LPUART1_INIT) Register content FIFOEN of LPUART1_CR1 = ‘1’ TCIE of LPUART1_CR1 = ‘0’ UE of LPUART1_CR1 = ‘1’ TE of LPUART1_CR1 = ‘1’ TXE of LPUART1_CR1 = ‘1’ DMAT of LPUART1_CR3 = ‘1’ Related actions Enables FIFO. BDMA will then use TXFNF (TXFIFO Not Full) flag for generating the BDMA requests. Disables interrupt when the transmit buffer is empty. Enables BDMA. Enables the LPUART1. Enables transmission. Enables the BDMA mode for transmission. Respect the sequence described in Table 43 to enable LPUART1. Table 43. LPUART1 Initial programming (LPUART1_Start) Register content TCCF of LPUART1_ICR = ‘1’ TCIE of LPUART1_CR1 = ‘1’ 7.3.3 Related actions Clears the TC flag, to avoid immediate interrupt generation, which would clear the D3_PendClear[1] in EXTI. Enables interrupt when the transmit buffer is empty. Overall description of the low-power application example based on LPUART1 transmission After a Power-on reset, the CPU perform the following operations: 1. Boot sequence (not described here). 2. Full initialization of RCC, PWR, EXTI, LPUART1, GPIOs, LPTIM4, DMAMUX2, BDMA and NVIC. Only the relevant steps of RCC, EXTI, PWR, LPUART1, BDMA and DMAMUX2 initialization related to the Autonomous mode are described herein. Refer to the previous sections for additional details. 3. the CPU processes the data to be transferred and copies them to SRAM4. 4. the CPU generates a wakeup event (EXTI_Event) to maintain D3 in Run mode when D1 enters DStandby. 5. the CPU enables the BDMA to start LPUART transmission and goes to Stop mode. As it is allowed to do so, D1 domain enters DStandby while D3 remains in Run mode. The data stored in SRAM4 are retained while the D1 domain is in DStandby mode. 6. As soon as the BDMA is enabled, it serves the request from LPUART1 in order to fill its TX-FIFO. In parallel, serial data transmission can start. 7. When the expected amount of data has been transmitted (NDT bits of BDMA_CNDTR0 set to 0), the BDMA no longer provides data to the LPUART1. The LPUART1 generates an interrupt when the TX-FIFO and the transmit buffer are empty. 8. This interrupt triggers DMAMUX2 REQ_GEN0, thus activating a data transfer via BDMA channel 7 (BDMA_Ch7). This transfer clears LPUART1 TC flag, and the lpuart1_tx_it is reset to ‘0’. 9. The end of this transfer triggers a dmamux2_evt7 signal which is used to clear the wakeup request generated by the CPU. 10. As a consequence, the D3 domain (i.e. the system) enters Stop mode and the system clock is gated. LPTIM4 still operates since it uses ck_lsi clock. 280/3178 DocID029587 Rev 3 RM0433 Low-power D3 domain 11. LPTIM4 lptim4_wkup interrupt wakes up the system. The device exits from Stop mode with the HSI clock. the CPU must restore the proper clock configuration during the warm re-boot sequence and perform the following tasks: Note: d) Acknowledge LPTIM4 wakeup interrupt, e) Process the next data block and transfers them to SRAM4, f) Generate again a wakeup event for D3 domain, g) Start the BDMA. h) Go back to CStop mode. The CPU does not need to initialize BDMA, DMAMUX2 and LPUART1 again. &38SURFHVVLQJ /38$57B6WDUW %'0$B6WDUW *RWR&6WRS (;7,B(YHQW 'DWD3URF :DUP%RRW 19,&LQLW /37,0B$FN %'0$B6WDUW *RWR&6WRS /38$57B6WDUW (;7,B(YHQW /37,0B6WDUW /38$57B,1,7 '0$08;B,1,7 'DWD3URF %RRW 5&&B,1,7 3:5B,1,7 (;7,B,1,7 /37,0B,1,7 Figure 32. Timing diagram of LPUART1 transmission with D3 domain in Autonomous mode OSWLPBZNXS '6WDWH 2)) 6\VWHP'6WDWH 2)) /38$57B7;' '5XQ '6WDQGE\ '5XQ 5XQ 6WRS ' ' ' '1 '6WDQGE\ 5XQ ' ' ' 6WRS '1 EGPDBFK OSXDUWBW[BLW EGPDBFK 5(4B*(1 GPDPX[BHYW 6\VWHP&ORFN 06Y9 7.3.4 Alternate implementations More power efficient implementations are also possible. As an example the system clock can be stopped once the data have been transferred to LPUART1 TX-FIFO, instead of remaining activated during the whole transmission as in the example presented above. In this case, the LPUART1 must use ck_hsi or ck_csi as kernel clock when the system switches from Run to Stop mode. LPUART1 must be programmed to wake up D3 domain when its TX-FIFO in almost empty. This asynchronous interrupt can be used as trigger by the REQ_GENx of the DMAMUX2, which will perform a given number (e.g. 14) of data transfers to LPUART1_TDR and then switch back the D3 domain to Stop mode. This implementation is possible because the LPUART1 can request the kernel clock as long as the TX-FIFO and transmit buffer are not empty. DocID029587 Rev 3 281/3178 282 Low-power D3 domain 7.4 RM0433 Other low-power applications Other peripherals located in D3 domain, such as I2C4, SPI6, SAI4 or ADC3, can be used to implement low-power applications. 282/3178 DocID029587 Rev 3 RM0433 8 Reset and Clock Control (RCC) Reset and Clock Control (RCC) The RCC block manages the clock and reset generation for the whole microcontroller. The RCC block is located in the D3 domain (refer to Section 6: Power control (PWR) for a detailed description). The operating modes this section refers to are defined in Section 6.6.1: Operating modes of the PWR block. 8.1 RCC main features Reset block • Generation of local and system reset • Bidirectional pin reset allowing to reset the microcontroller or external devices • Hold Boot function • WWDG reset supported Clock generation block • Generation and dispatching of clocks for the complete device • 3 separate PLLs using integer or fractional ratios • Possibility to change the PLL fractional ratios on-the-fly • Smart clock gating to reduce power dissipation • 2 external oscillators: • – High-speed external oscillator (HSE) supporting a wide range of crystals from 4 to 48 MHz frequency – Low-speed external oscillator (LSE) for the 32 kHz crystals 4 internal oscillators – High-speed internal oscillator (HSI) – 48 MHz RC oscillator (HSI48) – Low-power Internal oscillator (CSI) – Low-speed internal oscillator (LSI) • Buffered clock outputs for external devices • Generation of two types of interrupts lines: – Dedicated interrupt lines for clock security management – One general interrupt line for other events • Clock generation handling in Stop and Standby mode • D3 domain Autonomous mode DocID029587 Rev 3 283/3178 457 Reset and Clock Control (RCC) 8.2 RM0433 RCC block diagram Figure 33 shows the RCC block diagram. Figure 33. RCC Block diagram 5&& ' WRDOOFLUFXLW EORFNV QUHVHW V\VWHPUHVHW 1567 SHU[BUVW UFFBVIWBUVW SZUBERUBUVW SZUBSRUBUVW 6\VWHP 5HVHW &RQWURO LZGJBRXWBUVW ,:'* SZUBG[BZNXS 3:5 UFFBSZGBG[BUHT ZZGJBRXWBUVW ::'* SZUBKROGBFWUO &RUH 5HVHW &RQWURO &ORFN0DQDJHU &08 UFFBFBUVW FBVOHHS &38 FBGHHSVOHHS SHUBNHUBFNUHT KVHBFN KVLBFN FVLBFN 26&B,1 26&B287 &56 +6( &66 KVHBFN +6, KVLBFN OVLBFN /6, $+%%XV +6, &6, KVHBFN 0 KVLBFN 8 FVLBFN ; ',9,'(56 9'' 3// 3// 3// 6\VWHP &ORFN *HQHUDWLRQ 6&*8 3HULSKHUDO .HUQHO FORFN 6HOHFWLRQ 3.68 KVLBFN FVLBFN (;7, 5HJLVWHU,QWHUIDFHDQG&RQWURO UFFBOVHFVVBLW 0 8 ; ( 6 ',9,'(56 UFFBLW UFFBKVHFVVBLW 6\VWHP&ORFN (QDEOLQJ 6&(8 ',9 UFFBFNIDLOBHYW 7,0 3(5 SHU[BNHUBFNUHT 7R57& $:8 3HULSKHUDO &ORFN (QDEOLQJ 3.(8 /6(&66 OVHBFN 0 8 ; (Q 26&B,1 26&B287 OVHBFN OVLBFN KVHBFN ',9,'(56 96: 3(5[ 7RFRUHVDQGEXVVHV UFFBEXVBFN UFFBFBFN UFFBIFONBF 7RSHULSKHUDOV UFFBSHU[BNHUBFN UFFBSHU[BEXVBFN (7+B0,,B7;B&/. (7+B0,,B5;B&/. (7+B50,,B5()B&/. 86%B3+< 86%B3+< ,6B&.,1 0&2 0&2 06Y 9 8.3 RCC pins and internal signals Table 44 lists the RCC inputs and output signals connected to package pins or balls. Table 44. RCC input/output signals connected to package pins or balls Signal name Signal type NRST I/O OSC32_IN I 32 kHz oscillator input OSC32_OUT O 32 kHz oscillator output OSC_IN I System oscillator input 284/3178 Description System reset, can be used to provide reset to external devices DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Table 44. RCC input/output signals connected to package pins or balls (continued) Signal name Signal type OSC_OUT O System oscillator output MCO1 O Output clock 1 for external devices MCO2 O Output clock 2 for external devices I2S_CKIN I External kernel clock input for digital audio interfaces: SPI/I2S, SAI, and DFSDM ETH_MII_TX_CLK I External TX clock provided by the Ethernet MII interface ETH_MII_RX_CLK I External RX clock provided by the Ethernet MII interface ETH_RMII_REF_CLK I External reference clock provided by the Ethernet RMII interface USB_PHY1 I USB clock input provided by the external USB PHY USB_PHY2 I USB clock input provided by the external USB PHY Description The RCC exchanges a lot of internal signals with all components of the product, for that reason, the Table 44 only shows the most significant internal signals. Table 45. RCC internal input/output signals New Signal name Signal type rcc_it O General interrupt request line rcc_hsecss_it O HSE clock security failure interrupt rcc_lsecss_it O LSE clock security failure interrupt rcc_ckfail_evt O Event indicating that a HSE clock security failure is detected. This signal is connected to TIMERS nreset I/O System reset iwdg1_out_rst I Reset line driven by the IWDG1, indicating that a timeout occurred. wwdg1_out_rst I Reset line driven by the WWDG1, indicating that a timeout occurred. pwr_bor_rst I Brownout reset generated by the PWR block pwr_por_rst I Power-on reset generated by the PWR block pwr_vsw_rst I Power-on reset of the VSW domain generated by the PWR block rcc_perx_rst O Reset generated by the RCC for the peripherals. pwr_d[3:1]_wkup I Wake-up domain request generated by the PWR. Generally used to restore the clocks a domain when this domain exits from DStop rcc_pwd_d[3:1]_req O Low-Power request generated by the RCC. Generally used to ask to the PWR to set a domain into low-power mode, when a domain is in DStop. pwr_hold_ctrl I Signals generated by the PWR, in order to set the processor into CStop when exiting from system Stop mode. c_sleep I c_deepsleep I Description Signal generated by the CPU, indicating if the CPU is in CRun, CSleep or CStop. DocID029587 Rev 3 285/3178 457 Reset and Clock Control (RCC) RM0433 Table 45. RCC internal input/output signals (continued) New Signal name Signal type Description perx_ker_ckreq I Signal generated by some peripherals in order to request the activation of their kernel clock. rcc_perx_ker_ck O Kernel clock signals generated by the RCC, for some peripherals. rcc_perx_bus_ck O Bus interface clock signals generated by the RCC for peripherals. rcc_bus_ck O Clocks for APB (rcc_apb_ck), AHB (rcc_ahb_ck) and AXI (rcc_axi_ck) bridges generated by the RCC. rcc_c_ck O rcc_fclk_c O 8.4 Clock for the CPU, generated by the RCC. RCC reset block functional description Several sources can generate a reset: • An external device via NRST pin • A failure on the supply voltage applied to VDD • A watchdog timeout • A software command The reset scope depends on the source that generates the reset. Three reset categories exist: 8.4.1 • Power-on/off reset • System reset • Local resets Power-on/off reset The power-on/off reset (pwr_por_rst) is generated by the power controller block (PWR). It is activated when the input voltage (VDD) is below a threshold level. This is the most complete reset since it resets the whole circuit, except the backup domain. The power-on/off reset function can be disabled through PDR_ON pin (see Section 6.5: Power supply supervision). Refer to Table 46: Reset distribution summary for details. 286/3178 DocID029587 Rev 3 RM0433 8.4.2 Reset and Clock Control (RCC) System reset A system reset (nreset) resets all registers to their default values except for the reset status flags in the RCC_RSR (or RCC_C1_RSR) register, the debug features, the Flash memory and the Backup domain registers. A system reset can be generated from one of the following sources: • A reset from NRST pin (external reset) • A reset from the power-on/off reset block (pwr_por_rst) • A reset from the brownout reset block (pwr_bor_rst) Refer to Section 6.5.2: Brownout reset (BOR) for a detailed description of the BOR function. • A reset from the independent watchdogs (iwdg1_out_rst) • A software reset from the Cortex®-M7 core It is generated via the SYSRESETREQ signal issued by the Cortex®-M7 core. This signal is also named SFTRESET in this document. Note: • A reset from the window watchdogs depending on WWDG configuration (wwdg1_out_rst) • A reset from the low-power mode security reset, depending on option byte configuration (lpwr[2:1]_rst) The SYSRESETREQ bit in Cortex®-M7 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex®-M7 with FPU technical reference manual for more details (see http://infocenter.arm.com). As shown in Figure 34, some internal sources (such as pwr_por_rst, pwr_bor_rst, iwdg1_out_rst) perform a system reset of the circuit, which is also propagated to the NRST pin to reset the connected external devices. The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted Low. Note: It is not recommended to let the NRST pin unconnected. When it is not used, connect this pin to ground via a 10 to 100 nFcapacitor (CR in Figure 34). Figure 34. System reset circuit 5&& 9'' )LOWHU QUHVHW 6\VWHP5HVHW 538 SZUBERUBUVW 1567 ([WHUQDOUHVHW SZUBSRUBUVW &5 3XOVHJHQHUDWRU VPLQ 25 LZGJBRXWBUVW ZZGJBRXWBUVW OSZUBUVW 6)75(6(7 06Y 9 DocID029587 Rev 3 287/3178 457 Reset and Clock Control (RCC) 8.4.3 RM0433 Local resets CPU reset The CPU can reset itself by means of the CPURST bit in RCC AHB3 Reset Register (RCC_AHB3RSTR). Domain reset Some resets also dependent on the domain status. For example, when D1 domain exits from DStandby, it is reset (d1_rst). The same mechanism applies to D2. When the system exits from Standby mode, a stby_rst reset is applied. The stby_rst signal generates a reset of the complete VCORE domain as long the VCORE voltage provided by the internal regulator is not valid. Table 46 gives a detailed overview of reset sources and scopes. Reset source Pin Reset name D1 CPU D1 Interconnect D1 Peripherals D1 Debug WWDG1 D2 Interconnect D2 Peripherals D3 Peripherals IWDG1 FLASH RTC domain Backup RAM System Supply NRST pin Table 46. Reset distribution summary NRST x x x - x x x x x - - - - x pwr_bor_rst x x x - x x x x x - - - - x pwr_por_rst x x x x x x x x x x - - x x lpwr_rst x x x - x x x x x - - - - x PWR 288/3178 DocID029587 Rev 3 Comments – Resets D1 and D2 domains, and all their peripherals – Resets D3 domain peripherals – Resets VDD domain: IWDG1, LDO... – Debug features, Flash memory, RTC and backup RAM are not reset – Same as pin reset. The pin is asserted as well. – Same as pwr_bor_rst reset, plus: Reset of the Flash memory digital block (including the option byte loading). Reset of the debug block – The low-power mode security reset has the same scope than pwr_por_rst. Refer to Section 8.4.5: Low-power mode security reset (lpwr_rst) for additional information. RM0433 Reset and Clock Control (RCC) Reset source Reset name D1 CPU D1 Interconnect D1 Peripherals D1 Debug WWDG1 D2 Interconnect D2 Peripherals D3 Peripherals IWDG1 FLASH RTC domain Backup RAM System Supply NRST pin Table 46. Reset distribution summary (continued) BDRST - - - - - - - - - - x - - - d1_rst x x x x x - - - - - - - - - d2_rst - - - - - x x - - - - - - - stby_rst x x x x x x x x - - - - - - CPURST x - - - x - - - - - - - - - CPU SFTRESET x x x - x x x x x - - - - x Backup domain pwr_vsw_rst - - - - - - - - - - x - - - IWDG1 WWDG1 iwdg1_out_rst x x x - x x x x x - - - - x wwdg1_out_rst x x x - x x x x x - - - - x RCC 8.4.4 Comments – The backup domain reset can be triggered by software. Refer to Section 8.4.6: Backup domain reset for additional information – Resets D1 domain, and all its peripherals, when the domain exits DStandby mode. – Resets D2 domain, and all its peripherals, when the domain exits DStandby mode. – When the device exits Standby mode, a reset of the complete VCORE domain is performed as long the VCORE voltage is not valid. The VCORE is supplied by the internal regulator. NRST signal is not asserted. – This reset is generated by software through the bit located into RCC AHB3 Reset Register (RCC_AHB3RSTR). – Resets the CPU, and the WWDG1 block – This reset is generated by software when writing SYSRESETREQ bit located into AIRCR register of the Cortex®-M7 core. – Same scope as pwr_bor_rst reset. – This reset is generated by the backup domain when the VSW supply voltage is outside the operating range. – Same as pwr_bor_rst reset. – Same as pwr_bor_rst reset. Reset source identification The CPU can identify the reset source by checking the reset flags in the RCC_RSR (or RCC_C1_RSR) register. The CPU can reset the flags by setting RMVF bit. Table 47 shows how the status bits of RCC_RSR (or RCC_C1_RSR) register behaves, according to the situation that generated the reset. For example when an IWDG1 timeout occurs (line #10), if the CPU is reading the RCC_RSR (or RCC_C1_RSR) register during DocID029587 Rev 3 289/3178 457 Reset and Clock Control (RCC) RM0433 the boot phase, both PINRSTF and IWDG1RSTF bits are set, indicating that the IWDG1 also generated a pin reset. IWDG1RSTF SFTRSTF PORRSTF PINRSTF BORRSTF Power-on reset (pwr_por_rst) 0 0 0 0 1 1 1 1 1 1 2 Pin reset (NRST) 0 0 0 0 0 1 0 0 0 1 3 Brownout reset (pwr_bor_rst) 0 0 0 0 0 1 1 0 0 1 4 System reset generated by CPU (SFTRESET) 0 0 0 1 0 1 0 0 0 1 5 CPU reset (CPURST) 0 0 0 0 0 0 0 0 0 1 6 WWDG1 reset (wwdg1_out_rst) 0 1 0 0 0 1 0 0 0 1 8 IWDG1 reset (iwdg1_out_rst) 0 0 1 0 0 1 0 0 0 1 10 D1 exits DStandby mode 0 0 0 0 0 0 0 0 1 0 11 D2 exits DStandby mode 0 0 0 0 0 0 0 1 0 0 12 D1 erroneously enters DStandby mode or CPU erroneously enters CStop mode 1 0 0 0 0 1 0 0 0 1 D1RSTF Situations Generating a Reset CPURSTF WWDG1RSTF 1 # D2RSTF LPWRRSTF Table 47. Reset source identification (RCC_RSR)(1) 1. Grayed cells highlight the register bits that are set. 8.4.5 Low-power mode security reset (lpwr_rst) To prevent critical applications from mistakenly enter a low-power mode, two low-power mode security resets are available. When enabled through nRST_STOP_D1 option bytes, a system reset is generated if the following conditions are met: • CPU accidentally enters CStop mode This type of reset is enabled by resetting nRST_STOP_D1 user option byte. In this case, whenever the CPU CStop mode entry sequence is successfully executed, a system reset is generated. • D1 domain accidentally enters DStandby mode This type of reset is enabled by resetting nRST_STDBY_D1 user option byte. In this case, whenever a D1 domain DStandby mode entry sequence is successfully executed, a system reset is generated. LPWRRSTF bits in RCC Reset Status Register (RCC_RSR) indicates that a low-power mode security reset occurred (see line #12 in Table 47). lpwr_rst is activated when a low-power mode security reset due to D1 or CPU occurred. Refer to Section 3.3.11: FLASH option bytes for additional information. 290/3178 DocID029587 Rev 3 RM0433 8.4.6 Reset and Clock Control (RCC) Backup domain reset A backup domain reset is generated when one of the following events occurs: • A software reset, triggered by setting BDRST bit in the RCC Backup Domain Control Register (RCC_BDCR). All RTC registers and the RCC_BDCR register are reset to their default values. The backup RAM is not affected. • VSW voltage is outside the operating range. All RTC registers and the RCC_BDCR register are reset to their default values. In this case the content of the backup RAM is no longer valid. There are two ways to reset the backup RAM: • through the Flash memory interface by requesting a protection level change from 1 to 0 • when a tamper event occurs. Refer to Section 6.4.4: Backup domain section of PWR block for additional information. 8.4.7 Power-on and wakeup sequences For detailed diagrams refer to Section 6.4.1: System supply startup in the PWR section. The time interval between the event which exits the product from a low-power and the moment where the CPU is able to execute code, depends on the system state and on its configuration. Figure 35 shows the most usual examples. Power-on wakeup sequence The power-on wakeup sequence shown in Figure 35 gives the most significant phases of the power-on sequence. It is the longest sequence since the circuit was not powered. Note that this sequence remains unchanged, whatever VBAT was present or not. Boot from pin reset When a pin reset occurs, VDD is still present. As a results: Note: • The regulator settling time is faster since the reference voltage is already stable. • The HSI restart delay may be needed if the HSI was not enabled when the NRST occurred, otherwise this restart delay phase is skipped. • The Flash memory power recovery delay can also be skipped if the Flash memory was enabled when the NRST occurred. The boot sequence is similar for pwr_bor_rst, lpwr_rst, STFxRESET, iwdg1_out_rst and wwdg1_out_rst (if WW1RSC = ‘1’). Boot from system Standby When waking up from system Standby, the reference voltage is stable since VDD has not been removed. As a result, the regulator settling time is fast. Since VCORE was not present, the restart delay for the HSI, the Flash memory power recovery and the option byte reloading cannot be skipped. DocID029587 Rev 3 291/3178 457 Reset and Clock Control (RCC) RM0433 Restart from system Stop When restarting from system Stop, VDD is still present. As a result, the sequence is mainly composed of two steps: 1. Regulator settling time to reach VOS3 (default voltage) 2. HSI/CSI restart delay. This step can be skipped if HSIKERON or CSIKERON bit, in RCC Source Control Register (RCC_CR) is set to ‘1’. Boot from domain DStandby The boot sequence of a domain from domain DStandby is mainly composed of two steps: 1. The power switch settling time (the regulator is already activated). 2. The Flash memory power recovery. Restart from domain DStop The restart sequence of a domain from domain DStop is mainly composed of the handshake between the RCC, EXTI and PWR blocks. 292/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Figure 35. Boot sequences versus system states 3RZHURQZDNHXS ZLWKRUZLWKRXW9%$7 9''!325 5(*%DQG*DS 1567JRHV +,*+ +6, )/B3:5 :DNHXS HYHQW )/B237% 581 +6, )/B3:5 :DNHXS HYHQW 581 7LPH )/B237% 581 7LPH 5HVWDUWIURPV\VWHP6WRS 5(*B926 +6,&6, 581 :DNHXS HYHQW 7LPH :DNHXSIURP'RPDLQ'6WDQGE\ H32' )/B3:5 581 :DNHXS HYHQW 7LPH 5HVWDUWIURP'RPDLQ'6WRS 581 5(*%DQG*DS %DQGJDSDQGUHJXODWRUVHWWOLQJWLPH 5(*B926 7LPH :DNHXSIURPV\VWHP6WDQGE\ 5(* 5(* )/B3:5 3$'5HVHW RUSZUBERUBUVW6)75(6(7LZGJBRXWBUVW« 5(* ' +6, 5(*VHWWOLQJWLPHWRUHDFKWKH926 5(*VHWWOLQJWLPH 7LPH )/B3:5 )ODVKSRZHUUHFRYHU\GHOD\ 581 )/B237% 2SWLRQE\WHVORDGLQJGHOD\ ' H32' 3RZHUVZLWFKGHOD\GHOD\ +6,&6, &38)HWFK 'HOD\GXHWRKDQGVKDNH5&&3:5DQG (;7, +6,RU&6,5HVWDUWGHOD\ 06Y 9 DocID029587 Rev 3 293/3178 457 Reset and Clock Control (RCC) 8.5 RM0433 RCC clock block functional description The RCC provides a wide choice of clock generators: • HSI (High-speed internal oscillator) clock: ~ 8, 16, 32 or 64 MHz • HSE (High-speed external oscillator) clock: 4 to 48 MHz • LSE (Low-speed external oscillator) clock: 32 kHz • LSI (Low-speed internal oscillator) clock: ~ 32 kHz • CSI (Low-power internal oscillator) clock: ~4 MHz • HSI48 (High-speed 48 MHz internal oscillator) clock: ~48 MHz It offers a high flexibility for the application to select the appropriate clock for CPU and peripherals, in particular for peripherals that require a specific clock such as Ethernet, USB OTG-FS and HS, SPI/I2S, SAI and SDMMC. To optimize the power consumption, each clock source can be switched ON or OFF independently. The RCC provides up to 3 PLLs; each of them can be configured with integer or fractional ratios. As shown in the Figure 36, the RCC offers 2 clock outputs (MCO1 and MCO2), with a great flexibility on the clock selection and frequency adjustment. The SCGU block (System Clock Generation Unit) contains several prescalers used to configure the CPU and bus matrix clock frequencies. The PKSU block (Peripheral Kernel clock Selection Unit) provides several dynamic switches allowing a large choice of kernel clock distribution to peripherals. The PKEU (Peripheral Kernel clock Enable Unit) and SCEU (System Clock Enable Unit) blocks perform the peripheral kernel clock gating, and the bus interface/cores/bus matrix clock gating, respectively. 294/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Figure 36. Top-level clock tree 5&& 9'''RPDLQ /6,21RU,:'*DFWLYDWHG OVLBFN /6, WHPSR 7R ,:'* 57&65& 96: %DFNXS OVHBFN &66 9'''RPDLQ 26&B,1 26&B287 +6(21 +6, WHPSR +6,',9 KVLBNHUBFN &6,.(521 &6,21 &6, FVLBNHUBFN KVLBFN 0&2 ·WR 0&2 V\VBFN SOOBSBFN KVHBFN SOOBSBFN FVLBFN OVLBFN 0&235( 7R73,8 ·WR KVLBFN FVLBFN KVHBFN SOOBUBFN WUDFHFONLQ ' KVLBFN FVLBFN ' KVHBFN SOOBSBFN &.3(565& KVLBNHUBFN FVLBNHUBFN KVHBFN 3//65& KVLBFN FVLBFN KVHBFN 0&235( 6: WHPSR +6, 7R 57&$:8 FVLBFN +6,21 &56 &ORFN UHFRYHU\ V\VWHP KVLBFN · UFFBUWFBFN 0&26(/ &66 +6,.(521 +6,21 KVLBFN OVHBFN KVHBFN SOOBTBFN KVLBFN KVHBFN WHPSR +6( 57&(1 0&26(/ 57&35( ·WR ' V\VBFN WR 0+] 3// UHIBFN 9&2 ',93 ',91 ',94 )5$&1 ·',90 UHIBFN WR 0+] UHIBFN WR 0+] SOOBSBFN SOOBTBFN SOOBUBFN SOO> @BSBFN 9&2 ',93 ',91 ',94 ',95 V\VBFN SHUBFN KVHBFN KVLBNHUBFN FVLBNHUBFN OVLBFN OVHBFN KVLBFN 3// )5$&1 ·',90 ',95 SOOBSBFN SOOBTBFN SOOBUBFN 9&2 ',93 ',94 )5$&1 ',95 ' 7KHVHOHFWHGLQSXWFDQEHFKDQJHGRQWKHIO\ZLWKRXWVSXUVRQWKHRXWSXWVLJQDO 7R SHULSKHUDOV ,6B&.,1 3// ',91 7R&38 EXVVHVDQG SHULSKHUDOV SOO> @BTBFN SHUBFN SOO> @BUBFN ·',90 6&(8 6\VWHP&ORFN (QDEOLQJ WHPSR 3.(8 3HULSKHUDO&ORFN(QDEOLQJ /6( 6&*8 6\VWHP&ORFN *HQHUDWLRQ 26&B,1 26&B287 OVHBFN OVLBFN KVHB0BFN 3.68 3HULSKHUDO.HUQHOFORFN6HOHFWLRQ /6(21 (7+B0,,B7;B&/. (7+B0,,B5;B&/. (7+B50,,B5()B&/. SOOBSBFN SOOBTBFN SOOBUBFN XOSLBSK\BFN XOSLBSK\BFN 86%B3+< 86%B3+< [5HSUHVHQWVWKHVHOHFWHGPX[LQSXWDIWHUDV\VWHPUHVHW 06Y 9 DocID029587 Rev 3 295/3178 457 Reset and Clock Control (RCC) 8.5.1 RM0433 Clock naming convention The RCC provides clocks to the complete circuit. To avoid misunderstanding, the following terms are used in this document: • Peripheral clocks The peripheral clocks are the clocks provided by the RCC to the peripherals. Two kinds of clock are available: – The bus interface clocks – The kernel clocks A peripheral receives from the RCC a bus interface clock in order to access its registers, and thus control the peripheral operation. This clock is generally the AHB, APB or AXI clock depending on which bus the peripheral is connected to. Some peripherals only need a bus interface clock (e.g. RNG, TIMx). Some peripherals also require a dedicated clock to handle the interface function. This clock is named “kernel clock”. As an example, peripherals such as SAI have to generate specific and accurate master clock frequencies, which require dedicated kernel clock frequencies. Another advantage of decoupling the bus interface clock from the specific interface needs, is that the bus clock can be changed without reprogramming the peripheral. • CPU clocks The CPU clock is the clock provided to the CPU. It is derived from the system clock (sys_ck). • Bus matrix clocks The bus matrix clocks are the clocks provided to the different bridges (APB, AHB or AXI). These clocks are derived from the system clock (sys_ck). 8.5.2 Oscillators description HSE oscillator The HSE block can generate a clock from two possible sources: • External crystal/ceramic resonator • External clock source Figure 37. HSE/LSE clock source ([WHUQDO&ORFNFRQILJXUDWLRQ &U\VWDOFHUDPLFUHVRQDWRUVFRQILJXUDWLRQ 26&B,1 26&B287 26&B,1 26&B287 26&B,1 26&B287 26&B,1 26&B287 +L= ([WHUQDOFORFN VRXUFH &/ /RDG FDSDFLWRUV &/ 06Y 9 296/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) External clock source (HSE bypass) In this mode, an external clock source must be provided to OSC_IN pin. This mode is selected by setting the HSEBYP and HSEON bits of the RCC Source Control Register (RCC_CR) to ‘1’. The external clock source (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left HI-Z (see Figure 37). External crystal/ceramic resonator The oscillator is enabled by setting the HSEBYP bit to ‘0’ and HSEON bit to ‘1’. The HSE can be used when the product requires a very accurate high-speed clock. The associated hardware configuration is shown in Figure 37: the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag of the RCC Source Control Register (RCC_CR), indicates whether the HSE oscillator is stable or not. At startup, the hse_ck clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC Clock Source Interrupt Enable Register (RCC_CIER). The HSE can be switched ON and OFF through the HSEON bit. Note that the HSE cannot be switched OFF if one of the two conditions is met: • The HSE is used directly (via software mux) as system clock • The HSE is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux). In that case the hardware does not allow programming the HSEON bit to ‘0’. The HSE is automatically disabled by hardware, when the system enters Stop or Standby mode (refer to Section 8.5.7: Handling clock generators in Stop and Standby mode for additional information). In addition, the HSE clock can be driven to the MCO1 and MCO2 outputs and used as clock source for other application components. LSE oscillator The LSE block can generate a clock from two possible sources: • External crystal/ceramic resonator • External user clock External clock source (LSE bypass) In this mode, an external clock source must be provided to OSC32_IN pin. The input clock can have a frequency up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits of RCC Backup Domain Control Register (RCC_BDCR) to ‘1’. The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left HI-Z (see Figure 37). DocID029587 Rev 3 297/3178 457 Reset and Clock Control (RCC) RM0433 External crystal/ceramic resonator (LSE crystal) The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It has the advantage to provide a low-power highly accurate clock source to the real-time clock (RTC) for clock/calendar or other timing functions. The LSERDY flag of the RCC Backup Domain Control Register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC Clock Source Interrupt Enable Register (RCC_CIER). The LSE oscillator is switched ON and OFF using the LSEON bit. The LSE remains enabled when the system enters Stop or Standby mode. In addition, the LSE clock can be driven to the MCO1 output and used as clock source for other application components. The LSE also offers a programmable driving capability (LSEDRV[1:0]) that can be used to modulate the amplifier driving capability. The driving capability can be changed dynamically from high drive to medium high drive, and then to medium low drive. HSI oscillator The HSI block provides the default clock to the product. The HSI is a high-speed internal RC oscillator which can be used directly as system clock, peripheral clock, or as PLL input. A predivider allows the application to select an HSI output frequency of 8, 16, 32 or 64 MHz. This predivider is controlled by the HSIDIV. The HSI advantages are the following: • Low-cost clock source since no external crystal is required • Faster startup time than HSE (a few microseconds) The HSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator. The HSI can be switched ON and OFF using the HSION bit. Note that the HSI cannot be switched OFF if one of the two conditions is met: • The HSI is used directly (via software mux) as system clock • The HSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux). In that case the hardware does not allow programming the HSION bit to ‘0’. Note that the HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to ‘1’). In that case the hardware does not update the HSIDIV with the new value. However it is possible to change the HSIDIV if the HSI is used directly as system clock. The HSIRDY flag indicates if the HSI is stable or not. At startup, the HSI output clock is not released until this bit is set by hardware. The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails (refer to Section : CSS on HSE). The HSI can be disabled or not when the system enters Stop mode, please refer to Section 8.5.7: Handling clock generators in Stop and Standby mode for additional information. In addition, the HSI clock can be driven to the MCO1 output and used as clock source for other application components. 298/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Care must be taken when the HSI is used as kernel clock for communication peripherals, the application must take into account the following parameters: Note: • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available, • the frequency accuracy. The HSI can remain enabled when the system is in Stop mode (see Section 8.5.7 for additional information). HSION, HSIRDY and HSIDIV bits are located in the RCC Source Control Register (RCC_CR). HSI calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to achieve an accuracy of ACCHSI (refer to the product datasheet for more information). After a power-on reset, the factory calibration value is loaded in the HSICAL[11:0] bits. If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the HSI frequency using the HSITRIM[5:0] bits. Note: HSICAL[11:0] and HSITRIM[5:0] bits are located in the RCC Internal Clock Source Calibration Register (RCC_ICSCR). CSI oscillator The CSI is a low-power RC oscillator which can be used directly as system clock, peripheral clock, or PLL input. The CSI advantages are the following: • Low-cost clock source since no external crystal is required • Faster startup time than HSE (a few microseconds) • Very low-power consumption, The CSI provides a clock frequency of about 4 MHz, while the HSI is able to provide a clock up to 64 MHz. CSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator. The CSI can be switched ON and OFF through the CSION bit. The CSIRDY flag indicates whether the CSI is stable or not. At startup, the CSI output clock is not released until this bit is set by hardware. The CSI cannot be switched OFF if one of the two conditions is met: • The CSI is used directly (via software mux) as system clock • The CSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux). In that case the hardware does not allow programming the CSION bit to ‘0’. The CSI can be disabled or not when the system enters Stop mode (refer to Section 8.5.7: Handling clock generators in Stop and Standby mode for additional information). In addition, the CSI clock can be driven to the MCO2 output and used as clock source for other application components. DocID029587 Rev 3 299/3178 457 Reset and Clock Control (RCC) RM0433 Even if the CSI settling time is faster than the HSI, care must be taken when the CSI is used as kernel clock for communication peripherals: the application has to take into account the following parameters: Note: • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available, • the frequency precision. CSION and CSIRDY bits are located in the RCC Source Control Register (RCC_CR). CSI calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by STMicroelectronics to achieve accuracy of ACCCSI(refer to the product datasheet for more information). After reset, the factory calibration value is loaded in the CSICAL[7:0] bits. If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the CSI frequency using the CSITRIM[4:0] bits. Note: Bits CSICAL[7:0] and CSITRIM[4:0] are located into the RCC Internal Clock Source Calibration Register (RCC_ICSCR) HSI48 oscillator The HSI48 is an RC oscillator that delivers a 48 MHz clock that can be used directly as kernel clock for some peripherals. The HSI48 oscillator mainly aims at providing a high precision clock to the USB peripheral by means of a special Clock Recovery System (CRS) circuitry, which could use the USB SOF signal, the LSE, or an external signal, to automatically adjust the oscillator frequency on-the-fly, in very small granularity. The HSI48 oscillator is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, this oscillator is free running and thus subject to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to achieve an accuracy of ACCHSI48 (refer to the product datasheet of the for more information). For more details on how to configure and use the CRS, please refer to Section 9: Clock recovery system (CRS). The HSI48RDY flag indicates whether the HSI48 oscillator is stable or not. At startup, the HSI48 output clock is not released until this bit is set by hardware. The HSI48 can be switched ON and OFF using the HSI48ON bit. The HSI48 clock can also be driven to the MCO1 multiplexer and used as clock source for other application components. Note: 300/3178 HSI48ON and HSI48RDY bits are located in the RCC Source Control Register (RCC_CR). DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) LSI oscillator The LSI acts as a low-power clock source that can be kept running when the system is in Stop or Standby mode for the independent watchdog (IWDG) and Auto-Wakeup Unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheet. The LSI can be switched ON and OFF using the LSION bit. The LSIRDY flag indicates whether the LSI oscillator is stable or not. If an independent watchdog is started either by hardware or software, the LSI is forced ON and cannot be disabled. The LSI remains enabled when the system enters Stop or Standby mode (refer to Section 8.5.7: Handling clock generators in Stop and Standby mode for additional information). At LSI startup, the clock is not provided until the hardware sets the LSIRDY bit. An interrupt can be generated if enabled in the RCC Clock Source Interrupt Enable Register (RCC_CIER). In addition, the LSI clock can be driven to the MCO2 output and used as a clock source for other application components. Note: Bits LSION and LSIRDY are located into the RCC Clock Control and Status Register (RCC_CSR). 8.5.3 Clock Security System (CSS) CSS on HSE The clock security system can be enabled by software via the HSECSSON bit. The HSECSSON bit can be enabled even when the HSEON is set to ‘0’. The CSS on HSE is enabled by the hardware when the HSE is enabled and ready, and HSECSSON set to ‘1’. The CSS on HSE is disabled when the HSE is disabled. As a result, this function does not work when the system is in Stop mode. It is not possible to clear directly the HSECSSON bit by software. The HSECSSON bit is cleared by hardware when a system reset occurs or when the system enters Standby mode (see Section 8.4.2: System reset). If a failure is detected on the HSE clock, the system automatically switches to the HSI in order to provide a safe clock. The HSE is then automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers (TIM1, TIM8, TIM15, TIM16, and TIM17), and an interrupt is generated to inform the software about the failure (CSS interrupt: rcc_hsecss_it), thus allowing the MCU to perform rescue operations. If the HSE output was used as clock source for PLLs when the failure occurred, the PLLs are also disabled. If an HSE clock failure occurs when the CSS is enabled, the CSS generates an interrupt which causes the automatic generation of an NMI. The HSECSSF flag in RCC Clock Source Interrupt Flag Register (RCC_CIFR) is set to ‘1’ to allow the application to identify the failure source. The NMI routine is executed indefinitely until the HSECSSF bit is cleared. As a consequence, the application has to clear the HSECSSF flag in the NMI ISR by setting the HSECSSC bit in the RCC Clock Source Interrupt Clear Register (RCC_CICR). DocID029587 Rev 3 301/3178 457 Reset and Clock Control (RCC) RM0433 CSS on LSE A clock security system on the LSE oscillator can be enabled by software by programming the LSECSSON bit in the RCC Backup Domain Control Register (RCC_BDCR). This bit can be disabled only by hardware when the following conditions are met: • after a pwr_vsw_rst (VSW software reset) • or after a failure detection on LSE. LSECSSON bit must be written after the LSE is enabled (LSEON bit set by software) and ready (LSERDY set by hardware), and after the RTC clock has been selected through the RTCSEL bit. The CSS on LSE works in all modes (Run, Stop and Standby) except VBAT. If an LSE failure is detected, the LSE clock is no more delivered to the RTC but the value of RTCSEL, LSECSSON and LSEON bits are not changed by the hardware. A wakeup is generated in Standby mode. In other modes an interrupt (rcc_lsecss_it) can be sent to wake up the software. The software must then disable the LSECSSON bit, stop the defective LSE (clear LSEON bit), and can change the RTC clock source (no clock or LSI or HSE) through RTCSEL bits, or take any required action to secure the application. 8.5.4 Clock output generation (MCO1/MCO2) Two micro-controller clock output (MCO) pins, MCO1 and MCO2, are available. A clock source can be selected for each output.The selected clock can be divided thanks to configurable prescaler (refer to Figure 36 for additional information on signal selection). MCO1 and MCO2 outputs are controlled via MCO1PRE[3:0], MCO1[2:0], MCO2PRE[3:0] and MCO2[2:0] located in the RCC Clock Configuration Register (RCC_CFGR). The GPIO port corresponding to each MCO pin, has to be programmed in alternate function mode. The clock provided to the MCOs outputs must not exceed the maximum pin speed (refer to the product datasheet for information on the supported pin speed). 302/3178 DocID029587 Rev 3 RM0433 8.5.5 Reset and Clock Control (RCC) PLL description The RCC features three PLLs: • A main PLL, PLL1, which is generally used to provide clocks to the CPU and to some peripherals. • Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals. The PLLs integrated into the RCC are completely independent. They offer the following features: • Two embedded VCOs: • – A wide-range VCO (VCOH) – A low-frequency VCO (VCOL) Input frequency range: – 1 to 2 MHz when VCOL is used – 2 to 16 MHz when VCOH is used • Capability to work either in integer or Fractional mode • 13-bit Sigma-Delta modulator, allowing to fine-tune the VCO frequency by steps of 11 to 0.3 ppm. • The Sigma-Delta modulator can be updated on-the-fly, without generating frequency overshoots on PLLs outputs. • Each PLL offer 3 outputs with post-dividers Figure 38. PLL block diagram 3//[5*( 3//[ WR0+] WR0+] 3)'&3 UHI[BFN 9&2+ /3) YFR[BFN ·',93[ ',93[(1 WR0+] SOO[BSBFN WR0+] 3//[9&26(/ 3)'&3 9&2/ /3) 3//[9&26(/ ',91[ ',94[ · ',94[(1 SOO[BTBFN ',95[ ·«« · ',95[(1 SOO[BUBFN Ȉǻ0RGXODWRU 3//[)5$&(1 /'2 6+B5(* 9 )5$&1[ ',93[ ZKHQ[ DQG',93[ IRU[ RU 9''$ 06Y 9 DocID029587 Rev 3 303/3178 457 Reset and Clock Control (RCC) RM0433 The PLLs are controlled via RCC_PLLxDIVR, RCC_PLLxFRACR, RCC_PLLCFGR and RCC_CR registers. The frequency of the reference clock provided to the PLLs (refx_ck) must range from 1 to 16 MHz. The user application has to program properly the DIVMx dividers of the RCC PLLs Clock Source Selection Register (RCC_PLLCKSELR) in order to match this condition. In addition, the PLLxRGE of the RCC PLLs Configuration Register (RCC_PLLCFGR) field must be set according to the reference input frequency to guarantee an optimal performance of the PLL. The user application can then configure the proper VCO: if the frequency of the reference clock is lower or equal to 2 MHz, then VCOL must be selected, otherwise VCOH must be chosen. To reduce the power consumption, it is recommended to configure the VCO output to the lowest frequency. DIVNx loop divider has to be programmed to achieve the expected frequency at VCO output. In addition, the VCO output range must be respected. The PLLs operate in integer mode when the value of SH_REG (FRACNx shadow register) is set to ‘0’. The SH_REG is updated with the FRACNx value when PLLxFRACEN bit goes from ‘0’ to ‘1’. The Sigma-Delta modulator is designed in order to minimize the jitter impact while allowing very small frequency steps. The PLLs can be enabled by setting PLLxON to ‘1’. The bits PLLxRDY indicate that the PLL is ready (i.e. locked). Note: Before enabling the PLLs, make sure that the reference frequency (refx_ck) provided to the PLL is stable, so the hardware does not allow changing DIVMx when the PLLx is ON and it is also not possible to change PLLSRC when one of the PLL is ON. The hardware prevents writing PLL1ON to ‘0’ if the PLL1 is currently used to deliver the system clock. There are other hardware protections on the clock generators (refer to sections HSE oscillator, HSI oscillator and CSI oscillator). The following PLL parameters cannot be changed once the PLL is enabled: DIVNx, PLLxRGE, PLLxVCOSEL, DIVPx, DIVQx, DIVRx, DIVPxEN, DIVQxEN and DIVRxEN. To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, the application shall set the enable bit (DIVyEN) as well as the corresponding post-divider bits (DIVP, DIVQ or DIVR) to ‘0’. If the above rules are not respected, the PLL output frequency is not guaranteed. Output frequency computation When the PLL is configured in integer mode (SH_REG = ‘0’), the VCO frequency (FVCO) is given by the following expression: F VCO = F REF_CK × DIVN F PLL_y_CK = ( F VCO ⁄ ( DIVy + 1 ) ) with y = P, Q or R When the PLL is configured in fractional mode (SH_REG different from ‘0’), the DIVN divider must be initialized before enabling the PLLs. However, it is possible to change the value of FRACNx on-the-fly without disturbing the PLL output. 304/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) This feature can be used either to generate a specific frequency from any crystal value with a good accuracy, or to fine-tune the frequency on-the-fly. For each PLL, the VCO frequency is given by the following formula: ⎛ FRACN⎞ F VCO = F ref_ck × ⎜ DIVN + ----------------------⎟ ( 13 ) ⎠ ⎝ 2 Note: For PLL1, DIVP can only take odd values. The PLLs are disabled by hardware when: • The system enters Stop or Standby mode. • An HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. PLL initialization phase Figure 39 shows the recommended PLL initialization sequence in integer and fractional mode. The PLLx are supposed to be disabled at the start of the initialization sequence: 1. Initialize the PLLs registers according to the required frequency. – Set PLLxFRACEN of RCC PLLs Configuration Register (RCC_PLLCFGR) to ‘0’ for integer mode. – For fractional mode, set FRACN to the required initial value (FracInitValue) and then set PLLxFRACEN to ‘1’. 2. Once the PLLxON bit is set to ‘1’, the user application has to wait until PLLxRDY bit is set to ‘1’. If the PLLx is in fractional mode, the PLLxFRACEN bit must not be set back to ‘0’ as long as PLLxRDY = ‘0’. 3. Once the PLLxRDY bit is set to ‘1’, the PLLx is ready to be used. 4. If the application intends to tune the PLLx frequency on-the-fly (possible only in fractional mode), then: a) Note: PLLxFRACEN must be set to ‘0’, When PLLxFRACEN = ‘0’, the Sigma-Delta modulator is still operating with the value latched into SH_REG. b) A new value must be uploaded into PLLxFRACR (FracValue(n)). c) PLLxFRACEN must be set to ‘1’, in order to latch the content of PLLxFRACR into its shadow register. When the PLLxRDY goes to ‘1’, it means that the difference between the PLLx output frequency and the target value is lower than ±2%. DocID029587 Rev 3 305/3178 457 Reset and Clock Control (RCC) RM0433 Figure 39. PLLs Initialization Flowchart 3//(QDEOH6HTXHQFH ,QWHJHUPRGH 3//(QDEOH6HTXHQFH )UDFWLRQDOPRGH 6HOHFWFORFNVRXUFH5&&B&.6(/5 3//65& 6HOHFWFORFNVRXUFH 5&&B&.6(/5 3//65& ,QLW3UH'LYLGHU 5&&B&.6(/5 ',90[ ,QLW3UH'LYLGHU 5&&B&.6(/5 ',90[ 3//[&RQILJ 5&&B3//&)*5 3//[9&26(/3//[5*( 3//[)5$&(1 ',93[(1',94[(1',95[(1 ,QLW3//[GLYLGHUV 5&&B3//[',95 ',91[',93[',94[',95[ ,QLW)UDFWLRQDOYDOXH 5&&B3//[)5$&5 )5$&1 )UDF,QLW9DOXH 3//[&RQILJ 5&&B3//&)*5 3//[9&26(/3//[5*( 3//[)5$&(1 ',93[(1',94[(1',95[(1 ,QLW3//[GLYLGHUV 5&&B3//[',95 ',91[',93[',94[',95[ (QDEOH3//[ 5&&B&5 3//[21 1R &DQEHUHSHDWHG IRUHDFK3// (QDEOH3//[ 5&&B&5 3//[21 3//[5'< " 1R 3//[5'< "@ '335( UFFBSFON · UFFBWLP[BNHUBFN $3%SHULSKHUDOFORFNV 6&(8 6\VWHP&ORFN(QDEOLQJ * ''20$,1 $+% SHULSKHUDOFORFNV $3%SHULSKHUDOFORFNV 7LPHUVSUHVFDOHUFORFN '335( UFFBSFON · UFFBWLP\BNHUBFN V\VBGFSUHBFN $3%SHULSKHUDOFORFNV 7LPHUVSUHVFDOHUFORFN +57,0SUHVFDOHUFORFN +57,06(/ UFFBKFON UFFBIFONBG $+%SHULSKHUDOFORFNV '335( · UFFBSFON $3%SHULSKHUDOFORFNV ''20$,1 [5HSUHVHQWVWKHVHOHFWHGPX[LQSXWDIWHUDV\VWHPUHVHW &DQEHFKDQJHGRQWKHIO\ 06Y 9 This block also provides the clock for the timers (rcc_timx_ker_ck and rcc_timy_ker_ck). The frequency of the timers clock depends on the APB prescaler corresponding to the bus to which the timer is connected, and on TIMPRE bit. Table 48 shows how to select the timer clock frequency. Table 48. Ratio between clock timer and pclk D2PPRE1 (1) TIMPRE Frcc_timx_ker_ck Frcc_pclk1 Frcc_timy_ker_ck Frcc_pclk2 D2PPRE2 (2) 0xx 0 → Frcc_hclk1 Frcc_hclk1 100 0 → Frcc_hclk1 Frcc_hclk1 / 2 101 0 → Frcc_hclk1 / 2 Frcc_hclk1 / 4 110 0 → Frcc_hclk1 / 4 Frcc_hclk1 / 8 111 0 → Frcc_hclk1 / 8 Frcc_hclk1 / 16 308/3178 DocID029587 Rev 3 Comments The timer clock is equal to the bus clock. The timer clock is twice as fast as the bus clock. RM0433 Reset and Clock Control (RCC) Table 48. Ratio between clock timer and pclk (continued) D2PPRE1 (1) TIMPRE (2) D2PPRE2 Frcc_timx_ker_ck Frcc_pclk1 Frcc_timy_ker_ck Frcc_pclk2 Comments 0xx 1 → Frcc_hclk1 Frcc_hclk1 The timer clock is equal to the bus clock. 100 1 → Frcc_hclk1 Frcc_hclk1 / 2 The timer clock is twice as fast as the bus clock. 101 1 → Frcc_hclk1 Frcc_hclk1 / 4 110 1 → Frcc_hclk1 / 2 Frcc_hclk1 / 8 111 1 → Frcc_hclk1 / 4 Frcc_hclk1 / 16 The timer clock is 4 times faster than the bus clock. 1. D2PPRE1 and D2PPRE2 belong to RCC Domain 2 Clock Configuration Register (RCC_D2CFGR). 2. TIMPRE belongs to RCC Clock Configuration Register (RCC_CFGR). 8.5.7 Handling clock generators in Stop and Standby mode When the whole system enters Stop mode, all the clocks (system and kernel clocks) are stopped as well as the following clock sources: • CSI, HSI (depending on HSIKERON, and CSIKERON bits) • HSE • PLL1, PLL2 and PLL3 • HSI48 The content of the RCC registers is not altered except for PLL1ON, PLL2ON, PLL3ON HSEON and HSI48ON which are set to ‘0’. Exiting Stop mode When the microcontroller exits system Stop mode via a wake-up event, the application can select which oscillator (HSI and/or CSI) will be used to restart. The STOPWUCK bit selects the oscillator used as system clock. The STOPKERWUCK bit selects the oscillator used as kernel clock for peripherals. The STOPKERWUCK bit is useful if after a system Stop a peripheral needs a kernel clock generated by an oscillator different from the one used for the system clock. All these bits belong to the RCC Clock Configuration Register (RCC_CFGR). Table 49 gives a detailed description of their behavior. Table 49. STOPWUCK and STOPKERWUCK description Activated oscillator when the system exits Stop mode STOPWUCK STOPKERWUCK 0 1 0 → 1 → 0 → 1 → HSI Distributed clocks when System exits Stop mode System Clock HSI HSI and CSI CSI DocID029587 Rev 3 Kernel Clock HSI HSI and/or CSI CSI CSI 309/3178 457 Reset and Clock Control (RCC) RM0433 During Stop mode There are two specific cases where the HSI or CSI can be enabled during system Stop mode: • When a dedicated peripheral requests the kernel clock: In this case the peripheral will receive the HSI or CSI according to the kernel clock source selected for this peripheral (via PERxSRC). • When the bits HSIKERON or CSIKERON are set: In this case the HSI and CSI are kept running during Stop mode but the outputs are gated. In that way, the clock will be available immediately when the system exits Stop mode or when a peripheral requests the kernel clock (see Table 50 for details). HSIKERON and CSIKERON bits belong to RCC Source Control Register (RCC_CR). Table 50 gives a detailed description of their behavior. Table 50. HSIKERON and CSIKERON behavior HSIKERON (CSIKERON) HSI (CSI) state during Stop mode HSI (CSI) Setting time 0 → OFF tsu(HSI) (tsu(CSI)) (1) 1 → Running and Gated Immediate 1. tsu(HSI) and tsu(CSI) are the startup times of the HSI and CSI oscillators (see refer to the product datasheet for the values of these parameters). When the microcontroller exists system Standby mode, the HSI is selected as system and kernel clock, the RCC registers are reset to their initial values except for the RCC_RSR (or RCC_C1_RSR) and RCC_BDCR registers. Note as well that the HSI and CSI outputs provide two clock paths (see Figure 36): • one path for the system clock (hsi_ck or csi_ck) • one path for the peripheral kernel clock (hsi_ker_ck or csi_ker_ck). When a peripheral requests the kernel clock in system Stop mode, only the path providing the hsi_ker_ck or csi_ker_ck is activated. Caution: 310/3178 It is not guaranteed that the CPU will get automatically the same clock frequencies when leaving CStop mode: this mainly depends on the System state. For example If the CPU goes to CStop, while the D3 domain is kept in CRun, when the CPU exits from CStop, the clock settings remain unchanged. If the D3 domain goes to CStop while the CPU is also in CStop, then when the CPU exits from CStop, the CPU will operate with HSI or CSI when it left the CStop mode. DocID029587 Rev 3 RM0433 8.5.8 Reset and Clock Control (RCC) Kernel clock selection Some peripherals are designed to work with two different clock domains that operate asynchronously: • a clock domain synchronous with the register and bus interface (ckg_bus_perx clock) • and a clock domain generally synchronous with the peripheral (kernel clock). The benefit of having peripherals supporting these two clock domains is that the user application has more freedom to choose optimized clock frequency for the CPU, bus matrix and for the kernel part of the peripheral. As a consequence, the user application can change the bus frequency without reprogramming the peripherals. As an example an on-going transfer with UART will not be disturbed if its APB clock is changed on-the-fly. Table 51 shows the kernel clock that the RCC can deliver to the peripherals. Each row of Table 51 represents a MUX and the peripherals connected to its output. The columns starting from number 4 represents the clock sources. Column 3 gives the maximum allowed frequency at each MUX output. It is up to the user to respect these requirements. DocID029587 Rev 3 311/3178 457 Reset and Clock Control (RCC) RM0433 Table 51. Kernel clock distribution overview SDMMC1 SDMMC2 SDMMCSEL 200 D1 1 2 0 3 1 2 0 3 0 1 (4) 200 SAI1SEL 133 DFSDM1 clk DFSDM1SEL 133 FDCAN FDCANSEL 100 HDMI-CEC CECSEL 66 I2C1,2,3 I2C123SEL 100 LPTIM1 LPTIM1SEL 100 TIM[8:1], TIM[17:12] - 200 x HRTIM - 400 x RNG RNGSEL 66 1 SAI1 SAI1SEL 133 0 1 2 4 3 0 1 2 4 3 4 3 SAI3 SAI23SEL 133 0 1 2 4 1 1 0 2 0 2 (3) 1 D2 133 3 1 0 2 0 2 0 1 3 4 2 3 3 0 5 SPDIFRX SPDIFSEL 200 0 SPI(I2S)1,2,3 SPI123SEL 200 0 SPI4,5 SPI45SEL 100 SWPMI SWPSEL 100 USART1,6 USART16SEL 100 1 USART2,3 UART4,5,7,8 USART234578 SEL 100 1 USB1OTG USB2OTG USBSEL 66 USB1ULPI - 100 x USB2ULPI - 100 x ADCSEL 36 (4) ADC1,2 ADC3 312/3178 Disabled x DFSDM1 Aclk SAI2 USB_PHY1/2 I2S_CKIN per_ck (2) lsi_ck lse_ck hsi48_ck csi_ker_ck hsi_ker_ck 200 hse_ck QSPISEL sys_ck QUADSPI bus clocks (1) 200 pll3_r_ck FMCSEL pll3_q_ck FMC pll2_r_ck 66 pll3_p_ck - pll2_q_ck LTDC pll2_p_ck Clock mux control bits pll1_q_ck Peripherals Domain Clock Sources Max. allowed freq. [MHz] 1 1 D3 3 2 1 1 2 2 0 5 3 4 0 1 2 0 3 4 5 2 0 3 4 5 2 0 DocID029587 Rev 3 3 1 0 2 RM0433 Reset and Clock Control (RCC) Table 51. Kernel clock distribution overview (continued) LPUART1 LPUART1SEL 100 SAI4_A SAI4ASEL 133 0 1 2 4 3 SAI4_B SAI4BSEL 133 0 1 2 4 3 SPI6 SPI6SEL 100 RTC/AWU RTCSEL 1 lsi_ck per_ck (2) 4 5 1 2 0 3 4 5 D3 1 1 2 2 VS W 0 0 3 5 3 4 hsi48_ck 3 hse_ck 0 sys_ck 2 pll3_r_ck 1 pll2_r_ck lse_ck 3 0 Disabled 100 2 1 I2S_CKIN LPTIM345SEL csi_ker_ck LPTIM3,4,5 hsi_ker_ck 100 bus clocks (1) LPTIM2SEL pll3_q_ck LPTIM2 pll3_p_ck 100 pll2_q_ck I2C4SEL pll2_p_ck I2C4 pll1_q_ck Max. allowed freq. [MHz] Domain Peripherals Clock mux control bits USB_PHY1/2 Clock Sources 5 4 3 (5) 1 2 0 1. The bus clocks are the bus interface clocks to which the peripherals are connected, it can be APB, AHB or AXI clocks. 2. The per_ck clock could be hse_ck, hsi_ker_ck or csi_ker_ck according to CKPERSEL selection. 3. Clock CSI divided by 122. 4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR. 5. Clock HSE divided by RTCPRE. Figure 41 to Figure 50 provide a more detailed description of kernel clock distribution. To simplify the drawings, the bus interface clocks (pclk, hclk) are not represented, even if they are gated with enable signals. Refer to Section 8.5.11: Peripheral clock gating control for more details. To reduce the amount of switches, some peripherals share the same kernel clock source. Nevertheless, all peripherals have their dedicated enable signal. Peripherals dedicated to audio applications The audio peripherals generally need specific accurate frequencies, except for SPDIFRX. As shown in Figure 41, the kernel clock of the SAIs or SPI(I2S)s can be generated by: Note: • The PLL1 when the amount of active PLLs has to be reduced • The PLL2 or 3 for optimal flexibility in frequency generation • HSE, HSI or CSI for use-cases where the current consumption is critical • I2S_CKIN when an external clock reference need to be used. The SPDIFRX does not require a specific frequency, but only a kernel clock frequency high enough to make the peripheral work properly. Refer to the SPDIFRX description for more details. DFSDM1 can use the same clock as SAI1A. This is useful when DFSDM1 is used for audio applications. To improve the flexibility, SAI4 can use different clock for each sub-block. The SPI/I2S1, 2, and 3 share the same kernel clock source (see Figure 42). DocID029587 Rev 3 313/3178 457 Reset and Clock Control (RCC) RM0433 Figure 41. Kernel clock distribution for SAIs and DFSDM 6$,$6(/ SOOBTBFN SOOBSBFN SOOBSBFN ,6B&.,1 SHUBFN ' 6$,$0(1 6$,(1 6$,/3(1 SOOBTBFN SOOBSBFN SOOBSBFN ,6B&.,1 SHUBFN VDLBDBNHUBFN /RJLF ' 6$, VDLBEBNHUBFN 6$,%6(/ 6$,6(/ 5&& SOOBTBFN SOOBSBFN SOOBSBFN ,6B&.,1 SHUBFN ' 6$,> @(1 6$,> @/3(1 /RJLF VDLB$BNHUBFN 6$, VDLBEBNHUBFN ')6'06(/ UFFBSFON V\VBFN ' ')6'0(1 ')6'0/3(1 6$,6(/ SOOBTBFN SOOBSBFN SOOBSBFN ,6B&.,1 SHUBFN FON ' ')6'0 /RJLF $FON 6$,(1 6$,/3(1 /RJLF VDLB$BNHUBFN 6$, 3.68 ' 3.(8 VDLBEBNHUBFN 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripherals. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. Peripherals dedicated to control and data transfer Peripherals such as SPIs, I2Cs, UARTs do not need a specific kernel clock frequency but a clock fast enough to generate the correct baud rate, or the required bit clock on the serial interface. For that purpose the source can be selected among: 314/3178 • PLL1 when the amount of active PLLs has to be reduced • PLL2 or PLL3 if better flexibility is required. As an example, this solution allows changing the frequency bus via PLL1 without affecting the speed of some serial interfaces. • HSI or CSI for low-power use-cases or when the peripheral has to quickly wake up from Stop mode (i.e. UART, I2C...). DocID029587 Rev 3 RM0433 Note: Reset and Clock Control (RCC) UARTs also need the LSE clock when high baud rates are not required. Figure 42. Kernel clock distribution for SPIs and SPI/I2S 63',)6(/ SOOBTBFN SOOBUBFN SOOBUBFN KVLBNHUBFN ' 63',)5;(1 /RJLF 63',)5;/3(1 63',)5; VSGLIU[BNHUBFN ,66(/ SOOBTBFN SOOBSBFN SOOBSBFN ,6B&.,1 SHUBFN ' 63,> @(1 63,> @/3(1 /RJLF 63,,6> @ VSLBNHUBFN 63,6(/ 5&& UFFBSFON SOOBTBFN SOOBTBFN KVLBNHUBFN FVLBNHUBFN KVHBFN ' 63,> @(1 63,> @/3(1 /RJLF 63,> @ VSLBNHUBFN 63,6(/ UFFBSFON SOOBTBFN SOOBTBFN KVLBNHUBFN FVLBNHUBFN KVHBFN ' 63,$0(1 63,(1 63,/3(1 63, VSLBNHUBFN 3.68 ' /RJLF 3.(8 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. DocID029587 Rev 3 315/3178 457 Reset and Clock Control (RCC) RM0433 Figure 43. Kernel clock distribution for I2Cs ,&6(/ UFFBSFON 5&& ' SOOBUBFN KVLBNHUBFN FVLBNHUBFN ,&$0(1 ,&(1 ,&/3(1 ,& /RJLF LFBNHUBFN ,&> @ ,&6(/ UFFBSFON ' SOOBUBFN KVLBNHUBFN FVLBNHUBFN ,&> @(1 ,&> @/3(1 /RJLF LFBNHUBFNBUHT LFBNHUBFN 3.68 ' LFBNHUBFNBUHT 3.(8 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset 2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. Figure 44. Kernel clock distribution for UARTs, USARTs and LPUART1 86$576(/ UFFBSFON SOOBTBFN SOOBTBFN KVLBNHUBFN FVLBNHUBFN OVHBFN ' 86$57 86$57(1 /RJLF 86$57/3(1 86$57(1 86$57/3(1 86$57 /RJLF XVDUWBNHUBFNBUHT XVDUWBNHUBFN 86$576(/ UFFBSFON SOOBTBFN SOOBTBFN KVLBNHUBFN FVLBNHUBFN OVHBFN ' XVDUWBNHUBFNBUHT XVDUWBNHUBFN 86$57> @ 86$57> @(1 86$57> @/3(1 /RJLF 8$57> @(1 8$57> @/3(1 /RJLF XVDUWBNHUBFNBUHT XVDUWBNHUBFN 8$57> @ XDUWBNHUBFNBUHT XDUWBNHUBFN 5&& 3.68 8$57> @(1 8$57> @ /RJLF 8$57> @/3(1 XDUWBNHUBFN /38$576(/ /38$57$0(1 UFFBSFON SOOBTBFN SOOBTBFN KVLBNHUBFN FVLBNHUBFN OVHBFN ' XDUWBNHUBFNBUHT ' /38$57(1 /38$573/(1 /38$57 /RJLF OSXDUWBNHUBFNBUHT OSXDUWBNHUBFN 3.(8 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. 316/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Figure 45. Kernel clock distribution for LTDC 5&& 3.68 3.(8 /7'&(1 /7'&/3(1 /RJLF OWGFBNHUBFN /7'& SOOBUBFN 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. The FMC, QUADSPI and SDMMC1/2 can also use a clock different from the bus interface clock for more flexibility. Figure 46. Kernel clock distribution for SDMMC, QUADSPI and FMC 6'00&6(/ SOOBTBFN SOOBUBFN 5&& 6'00&> @(1 ' 6'00&> @/3(1 6'00& /RJLF VGPPFBNHUBFN 463,6(/ 463,(1 UFFBKFON SOOBTBFN SOOBUBFN SHUBFN ' 463,/3(1 ' )0&/3(1 48$'63, /RJLF TXDGVSLBNHUBFN )0&6(/ )0&(1 UFFBKFON SOOBTBFN SOOBUBFN SHUBFN )0& IPFBNHUBFN 3.68 ' /RJLF 3.(8 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. DocID029587 Rev 3 317/3178 457 Reset and Clock Control (RCC) RM0433 Figure 47 shows the clock distribution for the USB blocks. The USBxULPI blocks receive their clock from the external PHY. The USBxOTG blocks receive the clock for USB communications which can be selected among different sources thanks to the MUX controlled by USBSEL. Figure 47. Kernel clock distribution for USB (2) 86%6(/ SOOBTBFN SOOBTBFN KVLBFN 5&& ' 86%27*(1 86%27*/3(1 /RJLF 86%27* 86%27*(1 86%27*/3(1 /RJLF 86%27* 3.68 3.(8 86%8/3, 86%8/3,(1 86%8/3,/3(1 /RJLF 86%8/3,(1 86%8/3,/3(1 /RJLF FNBXOSL 86%B3+< FNBXOSL 86%B3+< ' 86%8/3, 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. 318/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) The Ethernet transmit and receive clocks shall be provided from an external Ethernet PHY. The clock selection for the RX and TX path is controlled via the SYSCFG block. Figure 48. Kernel clock distribution for Ethernet 5&& 3.(8 (7+ (7+7;(1 (7+7;/3(1 3.68 (7+B0,,B7;B&/. /RJLF HWKBPLLBW[BFON ' )(6 (3,6>@ (7+B0,,B5;B&/. (7+B50,,B5()B&/. · (7+5;(1 (7+5;/3(1 /RJLF (7+7;(1RU(7+5;(1 (7+7;/3(1RU(7+5;/3(1 /RJLF (7+0$&(1 (7+0$&/3(1 /RJLF UFFBKFON ' HWKBPLLBU[BFON ' HWKBUPLLBUHIBFON KFONBL 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. DocID029587 Rev 3 319/3178 457 Reset and Clock Control (RCC) RM0433 Figure 49. Kernel clock distribution For ADCs, SWPMI, RNG and FDCAN (2) $'&$0(1 $'&6(/ SOOBSBFN SOOBUBFN SHUBFN ' $'&(1 $'&/3(1 /RJLF $'&(1 $'&/3(1 /RJLF $'& DGFBNHUBFN 5&& 6:36(/ UFFBSFON KVLBNHUBFN KVLBFN SOOBTBFN OVHBFN OVLBFN ' )'&$16(/ KVHBFN 6:3(1 6:3/3(1 /RJLF 51*(1 51*/3(1 /RJLF SOOBTBFN ' SOOBTBFN 6:30, VZSPLBNHUBFN ' 51*6(/ 51* UQJBNHUBFN )'&$1(1 )'&$1/3(1 /RJLF )'&$1 IGFDQBNHUBFN 3.68 ' $'& DGFBNHUBFN 3.(8 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. 320/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Figure 50. Kernel clock distribution for LPTIMs and HDMI-CEC (2) 5&& &(&6(/ &(&(1 OVHBFN OVLBFN FVLBNHUBFN ' &(&/3(1 +'0,&(& /RJLF FHFBNHUBFN LP · /37,06(/ UFFBSFON SOOBSBFN SOOBUBFN OVHBFN OVLBFN SHUBFN ' /37,0(1 /37,0/3(1 /37,0 /RJLF &/.08; /37,06(/ UFFBSFON SOOBSBFN SOOBUBFN OVHBFN OVLBFN SHUBFN /37,0$0(1 /37,0(1 /37,0/3(1 ' /37,0 /RJLF &/.08; /37,06(/ /37,0> @$0(1 UFFBSFON SOOBSBFN SOOBUBFN OVHBFN OVLBFN SHUBFN /37,0> @(1 /37,0> @/3(1 ' &/.08; 3.68 ' /37,0> @ /RJLF 3.(8 7KHVZLWFKLVG\QDPLF WKHWUDQVLWLRQEHWZHHQWZRLQSXWVLVJOLWFKIUHH 06Y 9 1. X represents the selected MUX input after a system reset 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 8.5.11: Peripheral clock gating control. RTC/AWU clock The rtc_ck clock source can be: • the hse_1M_ck (hse_ck divided by a programmable prescaler) • the lse_ck • or the lsi_ck clock The source clock is selected by programming the RTCSEL[1:0] bits in the RCC Backup Domain Control Register (RCC_BDCR) and the RTCPRE[5:0] bits in the RCC Clock Configuration Register (RCC_CFGR). This selection cannot be modified without resetting the Backup domain. If the LSE is selected as RTC clock, the RTC will work normally even if the backup or the VDD supply disappears. DocID029587 Rev 3 321/3178 457 Reset and Clock Control (RCC) RM0433 The LSE clock is in the Backup domain, whereas the other oscillators are not. As a consequence: • If LSE is selected as RTC clock, the RTC continues working even if the VDD supply is switched OFF, provided the VBAT supply is maintained. • If LSI is selected as the RTC clock, the AWU state is not guaranteed if the VDD supply is powered off. • If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the VDD supply is powered off or if the VCORE supply is powered off. The rtc_ck clock is enabled through RTCEN bit located in the RCC Backup Domain Control Register (RCC_BDCR). The RTC bus interface clock (APB clock) is enabled through RTCAPBEN and RTCAPBLPEN bits located in RCC_APB4ENR/LPENR registers. Note: To read the RTC calendar register when the APB clock frequency is less than seven times the RTC clock frequency (FAPB < 7 x FRTCLCK), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed. Watchdog clocks The RCC provides the clock for the four watchdog blocks available on the circuit. The independent watchdog (IWDG1) is connected to the LSI. The window watchdog (WWDG1) are connected to the APB clock. If an independent watchdog is started by either hardware option or software access, the LSI is forced ON and cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDGs. Caution: Before enabling the WWDG1, the application must set the WW1RSC bit to ‘1’. If the WW1RSC remains to ‘0’, when the WWDG1 is enabled, its the behavior is not guaranteed. The WW1RSC bit is located in RCC Global Control Register (RCC_GCR). Clock frequency measurement using TIMx Most of the clock source generator frequencies can be measured by means of the input capture of TIMx. • Calibrating the HSI or CSI with the LSE The primary purpose of having the LSE connected to a TIMx input capture is to be able to accurately measure the HSI or CSI. This requires to use the HSI or CSI as system clock source either directly or via PLL1. The number of system clock counts between consecutive edges of the LSE signal gives a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltagerelated frequency deviations. The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio is, the more accurate the measurement is. The HSI and CSI oscillators have dedicated user-accessible calibration bits for this purpose (see RCC Internal Clock Source Calibration Register (RCC_ICSCR)). When 322/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) the HSI or CSI are used via the PLLx, the system clock can also be fine-tuned by using the fractional divider of the PLLs. • Calibrating the LSI with the HSI The LSI frequency can also be measured: this is useful for applications that do not have a crystal. The ultralow power LSI oscillator has a large manufacturing process deviation. By measuring it versus the HSI clock source, it is possible to determine its frequency with the precision of the HSI. The measured value can be used to have more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an IWDG timeout with an acceptable accuracy. 8.5.9 General clock concept overview The RCC handles the distribution of the CPU, bus interface and peripheral clocks for the system (D1, D2 and D3 domains), according to the operating mode of each function (refer to Section 8.5.1: Clock naming convention for details on clock definitions). For each peripheral, the application can control the activation/deactivation of its kernel and bus interface clock. Prior to use a peripheral, the CPU has to enable it (by setting PERxEN to ‘1’), and define if this peripheral remains active in CSleep mode (by setting PERxLPEN to ‘1’). This is called ‘allocation’ of a peripheral to the CPU (refer to Section 8.5.10: Peripheral allocation for more details). The peripheral allocation is used by the RCC to automatically control the clock gating according to the CPU and domain modes, and by the PWR to control the supply voltages of D1, D2 and D3 domains. Figure 51 gives an example of peripheral allocation: • Note: The CPU enabled SDMMC1, SPI5 and SRAM1, AXISRAM, ITCM, DTCM1, DTCM2 and SRAM4 are implicitly allocated to the CPU. The group composed of the CPU, bus matrix 1/2/3 and allocated peripherals makes up a sub-system (CPU_SS). The FLASH, AXISRAM, ITCM, DTCM1, DTCM2, SRAM4, IWGD1, IWGD2, PWR, EXTI and RCC are common resources and are implicitly allocated to the CPU. DocID029587 Rev 3 323/3178 457 Reset and Clock Control (RCC) RM0433 Figure 51. Peripheral allocation example ' ' '7&0 3(5 6$, 3(5 ,& ,7&0 63, 3(5 3(5 %XV0DWUL[ $;,65$0 &38B66 6'00& %XV0DWUL[ )/$6+ )/,7) &38 65$0 65$0 '7&0 ' 65$0 %XV0DWUL[ 3(5 6$, ,& '0$08; %'0$ 65$0 (;7, 3:5 5&& ,:'* 3HULSKHUDOVLPSOLFLWO\DOORFDWHGWRWKH&38 06Y 9 When the CPU enters CStop mode, the RCC automatically disables the bus interface and kernel clocks of all the peripherals of the CPU_SS as well as the CPU clock. The PLLs, if enabled, are not disabled by the RCC since D3 is still running. The D3 domain can be kept in DRun mode while the CPU is in CStop mode and D1 and D2 domains are in DStop or DStandby mode. This is done by setting RUN_D3 bit in PWR_CPUCR registers. • If RUN_D3 is set to ‘1’, then D3 is maintained in DRun mode, independently from the CPU modes (see PWR CPU control register (PWR_CPUCR). • If RUN_D3 is set to ‘0’, then D3 domain enters DStop or DStandby mode when the CPU enters CStop mode (see Table 52). Note that the CPU can control if D1, D2 or D3 domains are allowed to enter in DStandby when conditions are met, via bits PDDS_D1, PDDS_D2 and PDDS_D3 of PWR CPU control register (PWR_CPUCR). A wakeup event will be able to exit D1, D2 and D3 domains from DStandby or DStop mode. In addition, more autonomy can be given to some peripherals located into D3 domain (refer to Section : D3 domain Autonomous mode for details). 324/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) D3 domain Autonomous mode The Autonomous mode allows to deliver the peripheral clocks to peripherals located in D3, even if the CPU is in CStop mode. When a peripheral has its autonomous bit enabled, it receives its peripheral clocks according to D3 domain state, if the CPU is in CStop mode: • If the D3 domain is in DRun mode, peripherals with Autonomous mode activated receive their peripheral clocks, • If the D3 domain is in DStop mode, no peripheral clock is provided. The Autonomous mode does not prevent the D3 domain to enter DStop or DStandby mode. The autonomous bits are located in RCC D3 Autonomous mode Register (RCC_D3AMR). For example, the CPU can enter CStop mode, while the SAI4 is filling the SRAM4 with data received from an external device via BDMA. When the amount of received data is reached, the CPU can be activated by a wakeup event. This can be done by setting the SAI4, the BDMA, and SRAM4 in Autonomous mode, while keeping D3 in DRun mode (RUN_D3 set to ‘1’). In this example, the RCC does not switch off the PLLs as the D3 domain is always in DRun mode. It is possible to go a step further with power consumption reduction by combining the Autonomous mode with the capability of some peripherals (UARTs, I2Cs) to request the kernel clock on their own, without waking-up the CPU. For example, if the system is expecting messages via I2C4, the whole system can be put in Stop mode. When the I2C4 peripheral detects a START bit, it will generate a “kernel clock request”. This request enables the HSI or CSI, and a kernel clock is provided only to the requester (in our example the I2C4). The I2C4 then decodes the incoming message. Several cases are then possible: • If the device address of the message does not match, then I2C4 releases its “kernel clock request” until a new START condition is detected. • If the device address of the incoming message matches, it has to be stored into D3 local memory. I2C4 is able to generate a wakeup event on address match to switch the D3 domain to DRun mode. The message is then transferred into memory via BDMA, and the D3 domain go back to DStop mode without any CPU activation. Note that if the amount of data transferred into memory reached the transfer count, the BDMA can also generate an interrupt to wake-up the CPU. • If the device address of the incoming message matches and the peripheral is setup to wake up the CPU, then I2C4 generates a wakeup event to activate the CPU. Please refer to the description of EXTI block in order see which peripheral is able to perform a wake-up event to which domain. Memory handling The CPU can access all the memory areas available in the product: • AXISRAM, ITCM, DTCM1, DTCM2 and FLASH, • SRAM1, SRAM2 and SRAM3, • SRAM4 and BKPRAM. As shown in Figure 51, FLASH, AXISRAM, SRAM4, ITCM, DTCM1 and DTCM2 are implicitly allocated to the CPU. As a result, there is no enable bit allowing the CPU to allocate these memories. If the CPU wants to use memories located into D2 domain (SRAM1, SRAM2 and SRAM3), it has to enable them. DocID029587 Rev 3 325/3178 457 Reset and Clock Control (RCC) RM0433 The BKPRAM has a dedicated enable in order to gate the bus interface clock. The CPU needs to enable the BKPRAM prior to use it. Note: The memory interface clocks (Flash and RAM interfaces) can be stopped by software during CSleep mode (via DxSRAMyLPEN bits). Refer to Peripheral clock gating control and CPU and bus matrix clock gating control sections for details on clock enabling. System states overview Table 52 gives an overview of the system states with respect to the D1, D2 and D3 domain modes. • The system remains in Run mode as long as D3 is in DRun mode. Several sub-states of system Run exist that are not detailed here (refer Power control (PWR) for more information). • When the D1 domain is in DRun, the D2 domain can be in DRun, DStop or DStandby. When the D1 domain is in DStop or DStandby, the D2 domain can no longer remain in DRun it will switch to DStop or DStandby according to PDDS_D2 bit. • D3 can run while D1 and D2 are in DStop/DStandby mode thanks to RUN_D3 bits of PWR_CPUCR registers or when D3 is in Autonomous mode. • The system remains in Stop mode as long as D3 is in DStop mode. This means implicitly that D1 and D2 are in DStop or DStandby. As soon as D1 or D2 exits DStop or DStandby, D3 switches to DRun mode. • The system remains in Standby mode as long as D1, D2 and D3 are in DStandby. • Domain states versus CPU states: – When the D1 domain is in DRun mode, it means that its bus matrix is clocked, and the CPU is in CRun mode. – When the D2 domain is in DRun mode, it means that its bus matrix is clocked, and the CPU is in CRun mode with at least a peripheral of D2 domain allocated. – When the D1 domain is in DStop mode it means that its bus matrix is no longer clocked, and the CPU is in CStop mode. – When the D2 domain is in DStop mode it means that its bus matrix is no longer clocked. This situation happens when: - the CPU did not allocate peripherals of D2 domain, - the CPU allocated peripherals of D2 domain, but the CPU is in CStop or CStandby, – When a domain is in DStandby mode, it means that the domain including its CPU are powered down. Table 52. System states overview System State D1 State D2 State DRun DRun/DStop/DStandby DStop/DStandby DStop/DStandby Stop DStop/DStandby DStop/ DStandby DStop Standby DStandby DStandby DStandby Run 326/3178 DocID029587 Rev 3 D3 State DRun RM0433 8.5.10 Reset and Clock Control (RCC) Peripheral allocation The CPU can allocate a peripheral and hence control its kernel and bus interface clock. The CPU can allocate a peripheral by setting the dedicated PERxEN bit located into: • RCC_xxxxENR registers or • RCC_C1_xxxxENR registers. The CPU can control the peripheral clocks gating when it is in CSleep mode via the PERxLPEN bits located into: • RCC_xxxxLPENR registers or • RCC_C1_xxxxLPENR registers. Refer to Section 8.7.1: Register mapping overview for additional information. The peripheral allocation bits (PERxEN bits) are used by the hardware to provide the kernel and bus interface clocks to the peripherals. However they are also used to link peripherals to the CPU (CPU sub-system). In this way, the hardware is able to safely gate the peripheral clocks and bus matrix clocks according to CPU states. The PWR block also uses this information to control properly the domain states. Clock switches and gating • Clock switching delays The input selected by the kernel clock switches can be changed dynamically without generating spurs or timing violation. As a consequence, switching from the original to the new input can only be performed if a clock is present on both inputs. If it not the case, no clock will be provided to the peripheral. To recover from this situation, the user has to provide a valid clock to both inputs. During the transition from one input to another, the kernel clock provided to the peripheral will be gated, in the worst case, during 2 clock cycles of the previously selected clock and 2 clock cycles of the new selected clock. As shown in Figure 52, both input clocks shall be present during transition time. Figure 52. Kernel Clock switching 7UDQVLWLRQ WLPH 3(5[65& LQBFN LQBFN UFFBSHU[BNHUBFN .HUQHOFORFN SURYLGHGWR 3(5[ 3(5[65& LQBFN LQBFN ' ,QWKLVDUHDFNBLQFORFNFDQEH GLVDEOHG UFFBSHU[BNHUBFN 06Y 9 DocID029587 Rev 3 327/3178 457 Reset and Clock Control (RCC) • RM0433 Clock enabling delays In the same way, the clock gating logic synchronizes the enable command (coming generally from a kernel clock request or PERxEN bits) with the selected clock, in order to avoid generation of spurs. Note: – A maximum delay of two periods of the enabled clock may occur between the enable command and the first rising edge of the clock. The enable command can be the rising edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel clock request asserted by a peripheral. – A maximum delay of 1.5 periods of the disabled clock may occur between the disable command and the last falling edge of the clock. The disable command can be the falling edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel clock request released by a peripheral. Both the kernel clock and the bus interface clock are affected by this re-synchronization delay. In addition, the clock enabling delay may strongly increase if the application is enabling for the first time a peripheral which is not located into the same domain. This is due to the fact that the domain where the peripheral is located could be in DStop or DStandby mode. The domain must be switched to DRun mode before the application can use this peripheral. As an example, if the CPU enables a peripheral located in the D2 domain while the D2 domain is in DStop/DStandby mode, then the power controller (PWR) has first to provide a supply voltage to D2, then the RCC has to wait for an acknowledge from the PWR before enabling the clocks of the D2 domain. To handle properly this situation the RCC and the PWR blocks feature four flags: – D1CKRDY/D2CKRDY located in RCC Source Control Register (RCC_CR) – SBF_D1 and SBF_D2 located in PWR CPU control register (PWR_CPUCR). The following sequence can be followed to avoid this issue: a) Enable the peripheral clocks (i.e. allocate the peripheral) by writing the corresponding PERxEN bit to ‘1’ in the RCC_xxxxENR register, b) Read back the RCC_xxxxENR register to make sure that the previous write operation is not pending into a write buffer. c) If the peripheral is located in a different domain, perform the two next steps: Read DxCKRDY until it is set to ‘1’. Write SBF_Dx to zero and read-back the value, in order to check if the domain where the peripheral is located is still in DStandby. If the corresponding bit is read at ‘1’, it means that the domain is still in DStandby. Repeat this operation until SBF_Dx is equal to ‘0’, then continue the other steps. Note: 328/3178 d) Perform a dummy read operation into a register of the enabled peripheral. This operation will take at least 2 clock cycles, which is equal to the max delay of the enable command. e) The peripheral can then be used. When the bus interface clock is not active, read or write accesses to the peripheral registers are not supported. A read access will return invalid data. A write access will be ignored and will not create any bus errors. DocID029587 Rev 3 RM0433 8.5.11 Reset and Clock Control (RCC) Peripheral clock gating control As mentioned previously, each peripheral requires a bus interface clock, named rcc_perx_bus_ck (for peripheral ‘x’). This clock can be an APB, AHB or AXI clock, according to which bus the peripheral is connected. The clocks used as bus interface for peripherals located in D1 domain, could be rcc_aclk, rcc_hclk3 or rcc_pclk3, depending on the bus connected to each peripheral. For simplicity sake, these clocks are named rcc_bus_d1_ck. In the same way, the signal named rcc_bus_d2_ck represents rcc_hclk1, rcc_hclk2, rcc_pclk1 or rcc_pclk2, depending on the bus connected to each peripheral of D2 domain. Similarly, the signal rcc_bus_d3_ck represents rcc_hclk4 or rcc_pclk4 for peripherals located in D3. Some peripherals (SAI, UART...) also require a dedicated clock for their communication interface. This clock is generally asynchronous with respect to the bus interface clock. It is named kernel clock (perx_ker_ckreq). Both clocks can be gated according to several conditions detailed hereafter. As shown in Figure 53, enabling the kernel and bus interface clocks of each peripheral depends on several input signals: • PERxEN and PERxLPEN bits PERxEN represents the peripheral enable (allocation) bit for the CPU. The CPU can write these bits to ‘1’ via RCC_C1_xxxxENR or RCC_xxxxENR registers. • PERxAMEN bits The PERxAMEN bits are belong to RCC D3 Autonomous mode Register (RCC_D3AMR). • CPU state (c_sleep and c_deepsleep signals) • D3 domain state (d3_deepsleep signal) • The kernel clock request (perx_ker_ckreq) of the peripheral itself, when the feature is available. Refer to Section 8.5.10: Peripheral allocation for more details. DocID029587 Rev 3 329/3178 457 Reset and Clock Control (RCC) RM0433 Figure 53. Peripheral kernel clock enable logic details 6&(8 6\VWHP&ORFN(QDEOLQJ8QLW UFFBEXVBGBFN UFFBEXVBGBFN UFFBEXVBGBFN UFFBSHU[BEXVBFN V\QF 3(5[(1 3(5[/3(1 &38BVWDWH 3(5[$0(1 'BVWDWH 5&& 3(5[65& EXVLI &RQWURO /RJLF UFFBSHU[BEXVBGBHQ UFFBSHU[BEXVBGBHQ UFFBSHU[BEXVBHQ 6&*8 6\VWHP FORFNJHQHUDWLRQ « UFFBSHU[BNHUBFN 3(5[$0(1 'BVWDWH .HUQHO &RQWURO /RJLF UFFBSHU[BNHUBFSXBHQ UFFBSHU[BNHUBGBHQ V\QF UFFBSHU[BNHUBHQ 3(5[(1 3(5[/3(1 &38BVWDWH 3.68 3HULSKHUDONHUQHO FORFN6HOHFWLRQ 3(5[ 3.(8 3HULSKHUDO.HUQHO&ORFN(QDEOLQJ SHU[BNHUBFNUHT :KHQWKHSHULSKHUDORIIHUVWKHIHDWXUH 06Y 9 330/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Table 53 gives a detailed description of the enabling logic of the peripheral clocks for peripherals located in D1 or D2 domain and allocated by the CPU. PERxEN PERxLPEN PERxSRC perx_ker_ckreq CPU State rcc_perx_ker_c_en rcc_perx_bus_d1_en Table 53. Peripheral clock enabling for D1 and D2 peripherals 0 X X X X 0 0 No clock provided to the peripheral, because PERxEN=‘0’ 1 X X X CRun 1 1 Kernel and bus interface clocks are provided to the peripheral, because the CPU is in CRun, and PERxEN=‘1’ 1 0 X X 0 0 No clock provided to the peripheral, because the CPU is in CSleep, and PERxLPEN=‘0’ CSleep Comments 1 1 X X 1 1 Kernel and bus interface clocks are provided to the peripheral, because CPU is in CSleep, and PERxLPEN=‘1’ 1 0 X X 0 0 No clock provided to the peripheral because the PERxLPEN bit is set to ‘0’. 1 no lsi_ck and no lse_ck and no hsi_ker_ck and no csi_ker_ck X 0 0 No clock provided to the peripheral because CPU is in CStop and lse_ck or lsi_ck or hsi_ker_ck or csi_ker_ck are not selected. 1 lsi_ck or lse_ck 0 Kernel clock is provided to the peripheral because PERxEN = PERxLPEN=‘1’ and lsi_ck or lse_ck are selected. The bus interface clock is no provided as the CPU is in CStop 1 1 hsi_ker_ck or csi_ker_ck 1 1 0 Kernel clock is provided to the peripheral because req_ker_perx = ‘1’, and PERxEN = PERxLPEN=‘1’ and hsi_ker_ck or csi_ker_ck are selected. The bus interface clock is no provided as the CPU is in CStop 1 1 hsi_ker_ck or csi_ker_ck 0 0 0 No clock provided to the peripheral because CPU is in CStop, and no kernel clock request pending 1 CStop 1 X 1 (1) 1. For RNG block, the kernel clock is not delivered if the CPU to which it is allocated is in CStop mode, even if the clock selected is lsi_ck or lse_ck. DocID029587 Rev 3 331/3178 457 Reset and Clock Control (RCC) RM0433 As a summary, we can state that the kernel clock is provided to the peripherals located on domains D1 and D2 when the following conditions are met: 1. The CPU is in CRun mode, and the peripheral is allocated. 2. The CPU is in CSleep mode, and the peripheral is allocated with PERxLPEN = ‘1’. 3. The CPU is in CStop mode, and the peripheral is allocated with PERxLPEN = ‘1’, and the peripheral generates a kernel clock request, and the selected clock is hsi_ker_ck or csi_ker_ck. 4. The CPU is in CStop mode, and the peripheral is allocated with PERxLPEN = ‘1’, and the kernel source clock of the peripheral is lse_ck or lsi_ck. The bus interface clock will be provided to the peripherals only when conditions 1 or 2 are met. Table 54 gives a detailed description of the enabling logic of the kernel clock for all peripherals located in D3. PERxSRC perx_ker_ckreq CPU State X X X Any 1 X X X X CRun 1 0 X X X rcc_perx_bus_d3_en PERxAMEN X rcc_perx_ker_d3_en PERxLPEN 0 D3 State PERxEN Table 54. Peripheral clock enabling for D3 peripherals Any 0 0 No clock provided to the peripheral, as PERxEN=‘0’ 1 1 Kernel and bus interface clocks are provided to the peripheral, because the CPU is in CRun, and PERxEN=‘1’ 0 0 No clock provided to the peripheral, because the CPU is in CSleep, and PERxLPEN=‘0’ 1 1 Kernel and bus interface clocks are provided to the peripheral, because the CPU is in CSleep, and PERxLPEN=‘1’ 0 As the CPU is in CStop, and PERxEN=‘1’, then the kernel clock gating depends on D3 state and PERxAMEN bits. No clock provided to the peripheral because PERxAMEN = ‘0’. 1 1 The kernel and bus interface clocks are provided because even if the CPU is in CStop mode, D3 is in DRun mode, with PERxEN and PERxAMEN bits set to ‘1’. 0 0 No clock provided to the peripheral, because D3 is in DStop, req_ker_perx = ‘0’, and lse_ck or lsi_ck are not selected. CSleep 1 1 X X X DRun 1 X 0 X X 1 X 1 X X 1 X 1 not lse_ck and not lsi_ck 0 332/3178 0 CStop DStop Comments DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) X hsi_ker_ck or csi_ker_ck 1 lse_ck or lsi_ck CStop 1 X D3 State perx_ker_ckreq 1 CPU State PERxSRC 1 rcc_perx_bus_d3_en 1 X 1 not hsi_ker_ck and not csi_ker_ck and not lse_ck and not lsi_ck rcc_perx_ker_d3_en 1 X PERxAMEN 1 PERxLPEN PERxEN Table 54. Peripheral clock enabling for D3 peripherals (continued) Comments 0 0 No clock provided to the peripheral, because even if req_ker_perx = ‘0’, lse_ck or lsi_ck or hsi_ker_ck or csi_ker_ck are not selected. 0 Kernel clock is provided to the peripheral because req_ker_perx = ‘1’, and PERxEN = PERxAMEN=‘1’, and the selected clock is hsi_ker_ck or csi_ker_ck. The bus interface clock is not provided as D3 is in DStop. 0 Kernel clock is provided to the peripheral because PERxEN = PERxAMEN=‘1’ and lse_ck or lsi_ck are selected, while D3 is in STOP. The bus interface clock is not provided as D3 is in DSTOP. DStop 1 1 As a summary, we can state that the kernel clock is provided to the peripherals of D3 if the following conditions are met: 1. The CPU is in CRun mode, and the peripheral is allocated. 2. The CPU is in CSleep mode, and the peripheral is allocated with PERxLPEN = ‘1’. 3. The CPU is in CStop mode, and the peripheral is allocated and D3 domain is in DRun mode with PERxAMEN = ‘1’. 4. The CPU is in CStop mode, and the peripheral is allocated, and D3 domain is in DStop mode with PERxAMEN = ‘1’, and the peripheral is generating a kernel clock request and the kernel clock source is hsi_ker_ck or csi_ker_ck. 5. The CPU is in CStop mode, and the peripheral is allocated, and D3 domain is in DStop mode with PERxAMEN = ‘1’, and the kernel clock source of the peripheral is lse_ck or lsi_ck. The bus interface clock will be provided to the peripherals only when condition 1, 2 or 3 is met. DocID029587 Rev 3 333/3178 457 Reset and Clock Control (RCC) Note: RM0433 When they are set to ‘1’, the autonomous bits indicate that the associated peripheral will receive a kernel clock according to D3 state, and not according to the mode of the CPU. Only I2C, U(S)ART and LPUART peripherals are able to request the kernel clock. This feature gives to the peripheral the capability to transfer data with an optimal power consumption. The autonomous bits dedicated to some peripherals located in D3 domain allow the data transfer with external devices without activating the CPU. In order for the LPTIMER to operate with lse_ck or lsi_ck when the circuit is in Stop mode, the user application has to select the lsi_ck or lse_ck input via LPTIMxSEL fields, and set bit LPTIMxAMEN and LPTIMxLPEN to ‘1’. 8.5.12 CPU and bus matrix clock gating control For each domain it is possible to control the activation/deactivation of the CPU clock and bus matrix clock. For information about convention naming, refer to Section 8.5.11: Peripheral clock gating control. The clocks of the CPU, AHB and AXI bridges and APB busses are enabled according to the rules hereafter: • The CPU clock rcc_c_ck is enabled when the CPU is in CRun mode. • The AXI bridge clock is enabled when the CPU is in CRun mode. • The D2 domain AHB bridges clocks are enabled when: • • • – The CPU is in CRun or, – If the CPU is in CSleep with at least a peripheral (master) connected to this bus having both its PERxEN and PERxLPEN set to ‘1’ or, – If the CPU is in CSleep with at least an APB bus having its clock enabled. The D3 domain AHB bridge clock is enabled when: – The CPU is in CRun or CSleep mode or, – When the RUN_D3 bit is set to ‘1’, independently of CPU modes or, – When the d3_deepsleep signal is inactive (‘0’), independently of CPU modes. The APB1,2,3 busses are enabled when: – The CPU is in CRun or, – If the CPU is in CSleep with at least a peripheral connected to this bus having both its PERxEN and PERxLPEN set to ‘1’. The APB4 bus is enabled when: the D3 domain is in DRun. As shown in the Figure 54, the enabling of the core and bus clock of each domain depends on several input signals: 334/3178 • c_sleep and c_deepsleep signals from the CPU, • d3_sleepdeep signal, • RCC_xxxxENR.PERxEN bits of peripherals located on D2 domain DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Figure 54. Bus clock enable logic 5&& 6&(8 UFFBFBFN UXQBF V\VBFN 6&*8 6\VWHP FORFNJHQHUDWLRQ UFFBEXVBGBFN UFFBEXVBGBFN UFFBEXVBGBFN FBGHHSVOHHS /RJLF IXQFWLRQ GBGHHSVOHHS 581B'RI3:5B&38&5 /RJLF IXQFWLRQ ' &380RGH FBVOHHSFBGHHSVOHHS /RJLF IXQFWLRQ ' FBSHUBDOORFBG UXQBFLVDFRPELQDWLRQRI127FBGHHSVOHHSDQG127FBVOHHS UFFBEXVBG[UHSUHVHQWVWKHFORFNVIRUWKHEXVPDWUL[DQGWKHSHULSKHUDOEXVLQWHUIDFHIRUGRPDLQ[ 06Y 9 DocID029587 Rev 3 335/3178 457 Reset and Clock Control (RCC) 8.6 RM0433 RCC Interrupts The RCC provides 3 interrupt lines: • rcc_it: a general interrupt line, providing events when the PLLs are ready, or when the oscillators are ready. • rcc_hsecss_it: an interrupt line dedicated to the failure detection of the HSE Clock Security System. • rcc_lsecss_it: an interrupt line dedicated to the failure detection of the LSE Clock Security System. The interrupt enable is controlled via RCC Clock Source Interrupt Enable Register (RCC_CIER), except for the HSE CSS failure. When the HSE CSS feature is enabled, it not possible to mask the interrupt generation. The interrupt flags can be checked via RCC Clock Source Interrupt Flag Register (RCC_CIFR), and those flags can be cleared via RCC Clock Source Interrupt Clear Register (RCC_CICR). Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set. Table 55 gives a summary of the interrupt sources, and the way to control them. Table 55. Interrupt sources and control Interrupt Source Interrupt enable Description Action to clear interrupt LSIRDYF LSI ready LSIRDYIE Set LSIRDYC to ‘1’ LSERDYF LSE ready LSERDYIE Set LSERDYC to ‘1’ HSIDRYF HSI ready HSIDRYIE Set HSIRDYC to ‘1’ HSERDYF HSE ready HSERDYIE Set HSERDYC to ‘1’ CSIRDYF CSI ready CSIRDYIE Set CSIRDYC to ‘1’ HSI48RDYF HSI48 ready HSI48RDYIE Set HSI48RDYC to ‘1’ PLL1RDYF PLL1 ready PLL1RDYIE Set PLL1RDYC to ‘1’ PLL2RDYF PLL2 ready PLL2RDYIE Set PLL2RDYC to ‘1’ PLL3RDYF PLL3 ready PLL3RDYIE LSECSSF HSECSSF LSE Clock security system failure HSE Clock security system failure LSECSSFIE (2) - Set LSECSSC to ‘1’ rcc_lsecss_it Set HSECSSC to ‘1’ rcc_hsecss_it 2. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = ‘1’). DocID029587 Rev 3 rcc_it Set PLL3RDYC to ‘1’ (1) 1. The security system feature must also be enabled (LSECSSON = ‘1’), in order to generate interrupts. 336/3178 Interrupt Line RM0433 Reset and Clock Control (RCC) 8.7 RCC register description 8.7.1 Register mapping overview Note that the control of PERxEN and PERxLPEN bits can be performed at two different address offset:0x0D0 and 0x130. So the application can use the registers named: • RCC_xxxxENR or RCC_C1_xxxxENR to control the PERxEN bits • RCC_xxxxLPENR or RCC_C1_xxxxLPENR to control the PERxLPEN bits • RCC_RSR or RCC_C1_RSR to control the reset flag status bits. This feature is provided to insure the compatibility with other products of this family. Figure 55 shows the RCC mapping overview. Figure 55. RCC mapping overview 3K\VLFDOUHJLVWHU PDSSLQJ /RJLFDOUHJLVWHU PDSSLQJ [)) 5&&B&B$3%/3(15 « EDQN [ 5&&B565 « 5&&B$3%/3(15 « 5&&B$3%/3(15 [' EDQN 5&&B565 « 5&&B$3%5675 « 5&&B$3%5675 5&&B&5 5&&B&B565 [ EDQN 5&&B&5 06Y 9 DocID029587 Rev 3 337/3178 457 Reset and Clock Control (RCC) 8.7.2 RM0433 RCC Source Control Register (RCC_CR) Address offset: 0x000 24 23 22 21 20 19 18 17 16 Res. Res. PLL3RDY PLL3ON PLL2RDY PLL2ON PLL1RDY PLL1ON Res. Res. Res. Res. r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 D1CKRDY HSI48RDY HSI48ON Res. Res. CSIKERON CSIRDY CSION Res. HSIDIVF r r r rw rw r rw r rs rw r rw 3 2 1 0 r rw rw HSIDIV[1:0] HSEON 25 HSION 26 HSERDY 27 HSIKERON 28 HSEBYP 29 HSIRDY 30 HSECSSON 31 D2CKRDY Reset value: 0x0000 0001 rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 PLL3RDY: PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked. 0: PLL3 unlocked (default after reset) 1: PLL3 locked Bit 28 PLL3ON: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 0: PLL3 OFF (default after reset) 1: PLL3 ON Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 0: PLL2 unlocked (default after reset) 1: PLL2 locked Bit 26 PLL2ON: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. 0: PLL2 OFF (default after reset) 1: PLL2 ON Bit 25 PLL1RDY: PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. 0: PLL1 unlocked (default after reset) 1: PLL1 locked Bit 24 PLL1ON: PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to ‘0’, if the PLL1 output is used as the system clock. 0: PLL1 OFF (default after reset) 1: PLL1 ON Bits 23:20 Reserved, must be kept at reset value. 338/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 19 HSECSSON: HSE Clock Security System enable Set by software to enable Clock Security System on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. 0: Clock Security System on HSE OFF (Clock detector OFF) (default after reset) 1: Clock Security System on HSE ON (Clock detector ON if the HSE oscillator is stable, OFF if not). Bit 18 HSEBYP: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: HSE oscillator not bypassed (default after reset) 1: HSE oscillator bypassed with an external clock Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. 0: HSE clock is not ready (default after reset) 1: HSE clock is ready Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’). 0: HSE is OFF (default after reset) 1: HSE is ON Bit 15 D2CKRDY: D2 domain clocks ready flag Set by hardware to indicate that the D2 domain clocks are available. 0: D2 domain clocks are not available (default after reset) 1: D2 domain clocks are available Bit 14 D1CKRDY: D1 domain clocks ready flag Set by hardware to indicate that the D1 domain clocks (CPU, bus and peripheral) are available. 0: D1 domain clocks are not available (default after reset) 1: D1 domain clocks are available Bit 13 HSI48RDY: HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. 0: HSI48 clock is not ready (default after reset) 1: HSI48 clock is ready Bit 12 HSI48ON: HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. 0: HSI48 is OFF (default after reset) 1: HSI48 is ON Bits 11:10 Reserved, must be kept at reset value. DocID029587 Rev 3 339/3178 457 Reset and Clock Control (RCC) RM0433 Bit 9 CSIKERON: CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. 0: no effect on CSI (default after reset) 1: CSI is forced to ON even in Stop mode Bit 8 CSIRDY: CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). 0: CSI clock is not ready (default after reset) 1: CSI clock is ready Bit 7 CSION: CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = ‘1’ or STOPKERWUCK = ‘1’. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’). 0: CSI is OFF (default after reset) 1: CSI is ON Bit 6 Reserved, must be kept at reset value. Bit 5 HSIDIVF: HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF will go immediately to ‘0’ when HSIDIV value is changed, and will be set back to ‘1’ when the output frequency matches the value programmed into HSIDIV. 0: new division ratio not yet propagated to hsi(_ker)_ck (default after reset) 1: hsi(_ker)_ck clock frequency reflects the new HSIDIV value Bits 4:3 HSIDIV[1:0]: HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to ‘1’). In that case, the new HSIDIV value is ignored. 00: Division by 1, hsi(_ker)_ck = 64 MHz (default after reset) 01: Division by 2, hsi(_ker)_ck = 32 MHz 10: Division by 4, hsi(_ker)_ck = 16 MHz 11: Division by 8, hsi(_ker)_ck = 8 MHz 340/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 2 HSIRDY: HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. 0: HSI clock is not ready (default after reset) 1: HSI clock is ready Bit 1 HSIKERON: High Speed Internal clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. 0: no effect on HSI (default after reset) 1: HSI is forced to ON even in Stop mode Bit 0 HSION: High Speed Internal clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = ‘0’ or STOPKERWUCK = ‘0’. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’). 0: HSI is OFF 1: HSI is ON (default after reset) DocID029587 Rev 3 341/3178 457 Reset and Clock Control (RCC) 8.7.3 RM0433 RCC Internal Clock Source Calibration Register (RCC_ICSCR) Address offset: 0x004 Reset value: 0x4xxx 0xxx 31 30 29 Res. 28 27 26 25 24 23 CSITRIM[4:0] 22 rw 15 14 13 12 21 20 19 18 CSICAL[7:0] 17 r 11 10 9 8 7 6 16 HSITRIM[5:4] rw 5 HSITRIM[3:0] HSICAL[11:0] rw r 4 3 2 1 0 Bit 31 Reserved, must be kept at reset value. Bits 30:26 CSITRIM[4:0]: CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering Option Bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x10. Bits 25:18 CSICAL[7:0]: CSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering Option Byte calibration value and CSITRIM bits value Bits 17:12 HSITRIM[5:0]: HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering Option Bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x20. Bits 11:0 HSICAL[11:0]: HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering Option Byte calibration value and HSITRIM bits value. 342/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.4 RCC Clock Recovery RC Register (RCC_CRRCR) Address offset: 0x008 Reset value: 0x0000 0xxx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. HSI48CAL[9:0] r Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 HSI48CAL[9:0]: Internal RC 48 MHz clock calibration Set by hardware by option byte loading during system reset nreset. Read-only. DocID029587 Rev 3 343/3178 457 Reset and Clock Control (RCC) 8.7.5 RM0433 RCC Clock Configuration Register (RCC_CFGR) Address offset: 0x010 Reset value: 0x0000 0000 30 29 28 MCO2[2:0] 27 24 rw 13 12 11 23 22 21 MCO1[2:0] 20 rw 10 9 8 19 18 MCO11PRE[3:0] 17 16 Res. Res. 1 0 rw 7 6 RTCPRE[5:0] STOPKERWUCK rw 25 HRTIMSEL 14 TIMPRE rw 15 26 MCO2PRE[3:0] rw rw rw 5 4 3 2 STOPWUCK 31 SWS[2:0] SW[2:0] rw r rw Bits 31:29 MCO2[2:0]: Micro-controller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. 000: System clock selected (sys_ck) (default after reset) 001: PLL2 oscillator clock selected (pll2_p_ck) 010: HSE clock selected (hse_ck) 011: PLL1 clock selected (pll1_p_ck) 100: CSI clock selected (csi_ck) 101:LSI clock selected (lsi_ck) others: reserved Bits 28:25 MCO2PRE[3:0]: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. 0000: prescaler disabled (default after reset) 0001: division by 1 (bypass) 0010: division by 2 0011: division by 3 0100: division by 4 ... 1111: division by 15 Bits 24:22 MCO1[2:0]: Micro-controller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. 000: HSI clock selected (hsi_ck) (default after reset) 001: LSE oscillator clock selected (lse_ck) 010: HSE clock selected (hse_ck) 011: PLL1 clock selected (pll1_q_ck) 100: HSI48 clock selected (hsi48_ck) others: reserved 344/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bits 21:18 MCO1PRE[3:0]: MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. 0000: prescaler disabled (default after reset) 0001: division by 1 (bypass) 0010: division by 2 0011: division by 3 0100: division by 4 ... 1111: division by 15 Bits 17:16 Reserved, must be kept at reset value. Bit 15 TIMPRE: Timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. 0: The Timers kernel clock is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset) 1: The Timers kernel clock is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2 Please refer to Table 48: Ratio between clock timer and pclk Bit 14 HRTIMSEL: High Resolution Timer clock prescaler selection This bit is set and reset by software to control the clock frequency of high resolution the timer (HRTIM). 0: The HRTIM prescaler clock source is the same as other timers. (default after reset) 1: The HRTIM prescaler clock source is the CPU clock (rcc_c_ck). Bits 13:8 RTCPRE[5:0]: HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. 000000: no clock (default after reset) 000001: no clock 000010: HSE/2 000011: HSE/3 000100: HSE/4 ... 111110: HSE/62 111111: HSE/63 Bit 7 STOPKERWUCK: Kernel clock selection after a wake up from system Stop Set and reset by software to select the Kernel wakeup clock from system Stop. 0: The HSI is selected as wake up clock from system Stop (default after reset) 1: The CSI is selected as wake up clock from system Stop See Section 8.5.7: Handling clock generators in Stop and Standby mode for details. DocID029587 Rev 3 345/3178 457 Reset and Clock Control (RCC) RM0433 Bit 6 STOPWUCK: System clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the Clock Security System on HSE. 0: The HSI is selected as wake up clock from system Stop (default after reset) 1: The CSI is selected as wake up clock from system Stop See Section 8.5.7: Handling clock generators in Stop and Standby mode for details. Caution: STOPWUCK must not be modified when the Clock Security System is enabled (by HSECSSON bit) and the system clock is HSE (SWS=”10”) or a switch on HSE is requested (SW=”10”). Bits 5:3 SWS[2:0]: System clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset) 001: CSI used as system clock (csi_ck) 010: HSE used as system clock (hse_ck) 011: PLL1 used as system clock (pll1_p_ck) others: Reserved Bits 2:0 SW[2:0]: System clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to: – force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode – force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock. 000: HSI selected as system clock (hsi_ck) (default after reset) 001: CSI selected as system clock (csi_ck) 010: HSE selected as system clock (hse_ck) 011: PLL1 selected as system clock (pll1_p_ck) others: Reserved 346/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.6 RCC Domain 1 Clock Configuration Register (RCC_D1CFGR) Address offset: 0x018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. D1CPRE[3:0] Res. rw D1PPRE[2:0] HPRE[3:0] rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:8 D1CPRE[3:0]: D1 domain Core prescaler Set and reset by software to control D1 domain CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock, and all bus matrix clocks. The clocks are divided by the new prescaler factor. This factor ranges from 1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after D1CPRE update. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset) 1000: sys_ck divided by 2 1001: sys_ck divided by 4 1010: sys_ck divided by 8 1011: sys_ck divided by 16 1100: sys_ck divided by 64 1101: sys_ck divided by 128 1110: sys_ck divided by 256 1111: sys_ck divided by 512 DocID029587 Rev 3 347/3178 457 Reset and Clock Control (RCC) RM0433 Bit 7 Reserved, must be kept at reset value. Bits 6:4 D1PPRE[2:0]: D1 domain APB3 prescaler Set and reset by software to control the division factor of rcc_pclk3. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk3 after D1PPRE write. 0xx: rcc_pclk3 = rcc_hclk3 (default after reset) 100: rcc_pclk3 = rcc_hclk3 / 2 101: rcc_pclk3 = rcc_hclk3 / 4 110: rcc_pclk3 = rcc_hclk3 / 8 111: rcc_pclk3 = rcc_hclk3 / 16 Bits 3:0 HPRE[3:0]: D1 domain AHB prescaler Set and reset by software to control the division factor of rcc_hclk3 and rcc_aclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: rcc_hclk3 = sys_d1cpre_ck (default after reset) 1000: rcc_hclk3 = sys_d1cpre_ck / 2 1001: rcc_hclk3 = sys_d1cpre_ck / 4 1010: rcc_hclk3 = sys_d1cpre_ck / 8 1011: rcc_hclk3 = sys_d1cpre_ck / 16 1100: rcc_hclk3 = sys_d1cpre_ck / 64 1101: rcc_hclk3 = sys_d1cpre_ck / 128 1110: rcc_hclk3 = sys_d1cpre_ck / 256 1111: rcc_hclk3 = sys_d1cpre_ck / 512 Note: The clocks are divided by the new prescaler factor from1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after HPRE update. Note: Note also that rcc_hclk3 = rcc_aclk. Caution: Care must be taken when using the voltage scaling. Due to the propagation delay of the new division factor, after a prescaler factor change and before lowering the VCORE voltage, this register must be read in order to check that the new prescaler value has been taken into account. Depending on the clock source frequency and the voltage range, the software application has to program a correct value in HPRE to make sure that the system frequency does not exceed the maximum frequency. 348/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.7 RCC Domain 2 Clock Configuration Register (RCC_D2CFGR) Address offset: 0x01C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. D2PPRE2[2:0] Res. rw D2PPRE1[2:0] rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:8 D2PPRE2[2:0]: D2 domain APB2 prescaler Set and reset by software to control D2 domain APB2 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after D2PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 (default after reset) 100: rcc_pclk2 = rcc_hclk1 / 2 101: rcc_pclk2 = rcc_hclk1 / 4 110: rcc_pclk2 = rcc_hclk1 / 8 111: rcc_pclk2 = rcc_hclk1 / 16 Bit 7 Reserved, must be kept at reset value. Bits 6:4 D2PPRE1[2:0]: D2 domain APB1 prescaler Set and reset by software to control D2 domain APB1 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after D2PPRE1 write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset) 100: rcc_pclk1 = rcc_hclk1 / 2 101: rcc_pclk1 = rcc_hclk1 / 4 110: rcc_pclk1 = rcc_hclk1 / 8 111: rcc_pclk1 = rcc_hclk1 / 16 Bits 3:0 Reserved, must be kept at reset value. DocID029587 Rev 3 349/3178 457 Reset and Clock Control (RCC) 8.7.8 RM0433 RCC Domain 3 Clock Configuration Register (RCC_D3CFGR) Address offset: 0x020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. D3PPRE[2:0] Res. rw Bits 31:7 Reserved, must be kept at reset value. Bits 6:4 D3PPRE[2:0]: D3 domain APB4 prescaler Set and reset by software to control D3 domain APB4 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk4 after D3PPRE write. 0xx: rcc_pclk4 = rcc_hclk4 (default after reset) 100: rcc_pclk4 = rcc_hclk4 / 2 101: rcc_pclk4 = rcc_hclk4 / 4 110: rcc_pclk4 = rcc_hclk4 / 8 111: rcc_pclk4 = rcc_hclk4 / 16 Bits 3:0 Reserved, must be kept at reset value. 350/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.9 RCC PLLs Clock Source Selection Register (RCC_PLLCKSELR) Address offset: 0x028 Reset value: 0x0202 0200 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 Res. Res. 25 24 23 22 21 20 DIVM3[5:0] 19 18 Res. Res. 3 2 Res. Res. 17 rw DIVM2[3:0] 9 8 7 rw 6 DIVM1[5:0] rw rw 16 DIVM2[5:4] 5 4 1 0 PLLSRC[1:0] rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:20 DIVM3[5:0]: Prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = ‘1’). In order to save power when PLL3 is not used, the value of DIVM3 must be set to ‘0’. 000000: prescaler disabled (default after reset) 000001: division by 1 (bypass) 000010: division by 2 000011: division by 3 ... 100000: division by 32 (default after reset) ... 111111: division by 63 Bits 19:18 Reserved, must be kept at reset value. Bits 17:12 DIVM2[5:0]: Prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = ‘1’). In order to save power when PLL2 is not used, the value of DIVM2 must be set to ‘0’. 000000: prescaler disabled 000001: division by 1 (bypass) 000010: division by 2 000011: division by 3 ... 100000: division by 32 (default after reset) ... 111111: division by 63 Bits 11:10 Reserved, must be kept at reset value. DocID029587 Rev 3 351/3178 457 Reset and Clock Control (RCC) RM0433 Bits 9:4 DIVM1[5:0]: Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = ‘1’). In order to save power when PLL1 is not used, the value of DIVM1 must be set to ‘0’. 000000: prescaler disabled 000001: division by 1 (bypass) 000010: division by 2 000011: division by 3 ... 100000: division by 32 (default after reset) ... 111111: division by 63 Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 PLLSRC[1:0]: DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLLSRC must be set to ‘11’. 00: HSI selected as PLL clock (hsi_ck) (default after reset) 01: CSI selected as PLL clock (csi_ck) 10: HSE selected as PLL clock (hse_ck) 11: No clock send to DIVMx divider and PLLs 352/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.10 RCC PLLs Configuration Register (RCC_PLLCFGR) Address offset: 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. DIVR3EN DIVQ3EN DIVP3EN DIVR2EN DIVQ2EN DIVP2EN DIVR1EN DIVQ1EN DIVP1EN rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. PLL3RGE[[1:0] PLL3VCOSEL PLL3FRACEN PLL2RGE[[1:0] PLL2VCOSEL PLL2FRACEN PLL1RGE[[1:0] PLL1VCOSEL PLL1FRACEN Reset value: 0x01FF 0000 rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 DIVR3EN: PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). 0: pll3_r_ck output is disabled 1: pll3_r_ck output is enabled (default after reset) Bit 23 DIVQ3EN: PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). 0: pll3_q_ck output is disabled 1: pll3_q_ck output is enabled (default after reset) Bit 22 DIVP3EN: PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. This bit can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. 0: pll3_p_ck output is disabled 1: pll3_p_ck output is enabled (default after reset) Bit 21 DIVR2EN: PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). 0: pll2_r_ck output is disabled 1: pll2_r_ck output is enabled (default after reset) Bit 20 DIVQ2EN: PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). 0: pll2_q_ck output is disabled 1: pll2_q_ck output is enabled (default after reset) DocID029587 Rev 3 353/3178 457 Reset and Clock Control (RCC) RM0433 Bit 19 DIVP2EN: PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. This bit can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. 0: pll2_p_ck output is disabled 1: pll2_p_ck output is enabled (default after reset) Bit 18 DIVR1EN: PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR3EN and DIVR3 bits must be set to ‘0’ when the pll3_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). 0: pll1_r_ck output is disabled 1: pll1_r_ck output is enabled (default after reset) Bit 17 DIVQ1EN: PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). 0: pll1_q_ck output is disabled 1: pll1_q_ck output is enabled (default after reset) Bit 16 DIVP1EN: PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. 0: pll1_p_ck output is disabled 1: pll1_p_ck output is enabled (default after reset) Bits 15:12 Reserved, must be kept at reset value. Bits 11:10 PLL3RGE[1:0]: PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. These bits must be written before enabling the PLL3. 00: The PLL3 input (ref3_ck) clock range frequency is between 1 and 2 MHz (default after reset) 01: The PLL3 input (ref3_ck) clock range frequency is between 2 and 4 MHz 10: The PLL3 input (ref3_ck) clock range frequency is between 4 and 8 MHz 11: The PLL3 input (ref3_ck) clock range frequency is between 8 and 16 MHz Bit 9 PLL3VCOSEL: PLL3 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL3. This bit must be written before enabling the PLL3. 0: Wide VCO range:192 to 836 MHz (default after reset) 1: Medium VCO range:150 to 420 MHz Bit 8 PLL3FRACEN: PLL3 fractional latch enable Set and reset by software to latch the content of FRACN3 into the Sigma-Delta modulator. In order to latch the FRACN3 value into the Sigma-Delta modulator, PLL3FRACEN must be set to ‘0’, then set to ‘1’: the transition 0 to 1 transfers the content of FRACN3 into the modulator. Please refer to Section : PLL initialization phase for additional information. 354/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bits 7:6 PLL2RGE[1:0]: PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2. 00: The PLL2 input (ref2_ck) clock range frequency is between 1 and 2 MHz (default after reset) 01: The PLL2 input (ref2_ck) clock range frequency is between 2 and 4 MHz 10: The PLL2 input (ref2_ck) clock range frequency is between 4 and 8 MHz 11: The PLL2 input (ref2_ck) clock range frequency is between 8 and 16 MHz Bit 5 PLL2VCOSEL: PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2. 0: Wide VCO range:192 to 836 MHz (default after reset) 1: Medium VCO range:150 to 420 MHz Bit 4 PLL2FRACEN: PLL2 fractional latch enable Set and reset by software to latch the content of FRACN2 into the Sigma-Delta modulator. In order to latch the FRACN2 value into the Sigma-Delta modulator, PLL2FRACEN must be set to ‘0’, then set to ‘1’: the transition 0 to 1 transfers the content of FRACN2 into the modulator. Please refer to Section : PLL initialization phase for additional information. Bits 3:2 PLL1RGE[1:0]: PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00: The PLL1 input (ref1_ck) clock range frequency is between 1 and 2 MHz (default after reset) 01: The PLL1 input (ref1_ck) clock range frequency is between 2 and 4 MHz 10: The PLL1 input (ref1_ck) clock range frequency is between 4 and 8 MHz 11: The PLL1 input (ref1_ck) clock range frequency is between 8 and 16 MHz Bit 1 PLL1VCOSEL: PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. These bits must be written before enabling the PLL1. 0: Wide VCO range: 192 to 836 MHz (default after reset) 1: Medium VCO range: 150 to 420 MHz Bit 0 PLL1FRACEN: PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the Sigma-Delta modulator. In order to latch the FRACN1 value into the Sigma-Delta modulator, PLL1FRACEN must be set to ‘0’, then set to ‘1’: the transition 0 to 1 transfers the content of FRACN1 into the modulator. Please refer to Section : PLL initialization phase for additional information. DocID029587 Rev 3 355/3178 457 Reset and Clock Control (RCC) 8.7.11 RM0433 RCC PLL1 Dividers Configuration Register (RCC_PLL1DIVR) Address offset: 0x030 Reset value: 0x0101 0280 31 30 29 28 Res. 27 26 25 24 DIVR1[6:0] 23 22 21 20 Res. 19 rw 15 14 13 12 11 18 17 16 2 1 0 DIVQ1[6:0] rw 10 9 8 7 6 5 4 DIVP1[6:0] DIVN1[8:0] rw rw 3 Bit 31 Reserved, must be kept at reset value. Bits 30:24 DIVR1[6:0]: PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). 0000000: pll1_r_ck = vco1_ck 0000001: pll1_r_ck = vco1_ck / 2 (default after reset) 0000010: pll1_r_ck = vco1_ck / 3 0000011: pll1_r_ck = vco1_ck / 4 ... 1111111: pll1_r_ck = vco1_ck / 128 Bit 23 Reserved, must be kept at reset value. 356/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bits 22:16 DIVQ1[6:0]: PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). 0000000: pll1_q_ck = vco1_ck 0000001: pll1_q_ck = vco1_ck / 2 (default after reset) 0000010: pll1_q_ck = vco1_ck / 3 0000011: pll1_q_ck = vco1_ck / 4 ... 1111111: pll1_q_ck = vco1_ck / 128 Bits 15:9 DIVP1[6:0]: PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). Note that odd division factors are not allowed. 0000000: Not allowed 0000001: pll1_p_ck = vco1_ck / 2 (default after reset) 0000010: Not allowed 0000011: pll1_p_ck = vco1_ck / 4 ... 1111111: pll1_p_ck = vco1_ck / 128 Bits 8:0 DIVN1[8:0]: Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = ‘0’ and PLL1RDY = ‘0’). 0x003: DIVN1 = 4 0x004: DIVN1 = 5 0x005: DIVN1 = 6 ... 0x080: DIVN1 = 129 (default after reset) ... 0x1FF: DIVN1 = 512 Others: wrong configurations Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: – 192 to 836 MHz if PLL1VCOSEL = ‘0’ – 150 to 420 MHz if PLL1VCOSEL = ‘1’ – VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN1, with: – DIVN1 between 4 and 512 – The input frequency Fref1_ck between 1MHz and 16 MHz DocID029587 Rev 3 357/3178 457 Reset and Clock Control (RCC) 8.7.12 RM0433 RCC PLL1 Fractional Divider Register (RCC_PLL1FRACR) Address offset: 0x034 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. FRACN1[12:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:3 FRACN1[12:0]: Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: – 192 to 836 MHz if PLL1VCOSEL = ‘0’ – 150 to 420 MHz if PLL1VCOSEL = ‘1’ VCO output frequency = Fref1_ck x (DIVN1 + (FRACN1 / 213)), with – DIVN1 shall be between 4 and 512 – FRACN1 can be between 0 and 213- 1 – The input frequency Fref1_ck shall be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as follow: – set the bit PLL1FRACEN to ‘0’, – write the new fractional value into FRACN1, – set the bit PLL1FRACEN to ‘1’. Bits 2:0 Reserved, must be kept at reset value. 358/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.13 RCC PLL2 Dividers Configuration Register (RCC_PLL2DIVR) Address offset: 0x038 Reset value: 0x0101 0280 31 30 29 28 Res. 27 26 25 24 DIVR2[6:0] 23 22 21 20 19 Res. rw 15 14 13 12 11 18 17 16 2 1 0 DIVQ2[6:0] rw 10 9 8 7 6 5 4 DIVP2[6:0] DIVN2[8:0] rw rw 3 Bit 31 Reserved, must be kept at reset value. Bits 30:24 DIVR2[6:0]: PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). 0000000: pll2_r_ck = vco2_ck 0000001: pll2_r_ck = vco2_ck / 2 (default after reset) 0000010: pll2_r_ck = vco2_ck / 3 0000011: pll2_r_ck = vco2_ck / 4 ... 1111111: pll2_r_ck = vco2_ck / 128 Bit 23 Reserved, must be kept at reset value. DocID029587 Rev 3 359/3178 457 Reset and Clock Control (RCC) RM0433 Bits 22:16 DIVQ2[6:0]: PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). 0000000: pll2_q_ck = vco2_ck 0000001: pll2_q_ck = vco2_ck / 2 (default after reset) 0000010: pll2_q_ck = vco2_ck / 3 0000011: pll2_q_ck = vco2_ck / 4 ... 1111111: pll2_q_ck = vco2_ck / 128 Bits 15:9 DIVP2[6:0]: PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). 0000000: pll2_p_ck = vco2_ck 0000001: pll2_p_ck = vco2_ck / 2 (default after reset) 0000010: pll2_p_ck = vco2_ck / 3 0000011: pll2_p_ck = vco2_ck / 4 ... 1111111: pll2_p_ck = vco2_ck / 128 Bits 8:0 DIVN2[8:0]: Multiplication factor for PLL2 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = ‘0’ and PLL2RDY = ‘0’). Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: – 192 to 836 MHz if PLL2VCOSEL = ‘0’ – 150 to 420 MHz if PLL2VCOSEL = ‘1’ VCO output frequency = Fref2_ck x DIVN2, when fractional value 0 has been loaded into FRACN2, with – DIVN2 between 4 and 512 – The input frequency Fref2_ck between 1MHz and 16MHz 0x003: DIVN2 = 4 0x004: DIVN2 = 5 0x005: DIVN2 = 6 ... 0x080: DIVN2 = 129 (default after reset) ... 0x1FF: DIVN2 = 512 Others: wrong configurations 360/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.14 RCC PLL2 Fractional Divider Register (RCC_PLL2FRACR) Address offset: 0x03C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. FRACN2[12:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:3 FRACN2[12:0]: Fractional part of the multiplication factor for PLL2 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: – 192 to 836 MHz if PLL2VCOSEL = ‘0’ – 150 to 420 MHz if PLL2VCOSEL = ‘1’ VCO output frequency = Fref2_ck x (DIVN2 + (FRACN2 / 213)), with – DIVN2 shall be between 4 and 512 – FRACN2 can be between 0 and 213 - 1 – The input frequency Fref2_ck shall be between 1 and 16 MHz In order to change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as follow: – set the bit PLL2FRACEN to ‘0’, – write the new fractional value into FRACN2, – set the bit PLL2FRACEN to ‘1’. Bits 2:0 Reserved, must be kept at reset value. DocID029587 Rev 3 361/3178 457 Reset and Clock Control (RCC) 8.7.15 RM0433 RCC PLL3 Dividers Configuration Register (RCC_PLL3DIVR) Address offset: 0x040 Reset value: 0x0101 0280 31 30 29 28 Res. 27 26 25 24 DIVR3[6:0] 23 22 21 20 Res. 19 rw 15 14 13 12 11 18 17 16 2 1 0 DIVQ3[6:0] rw 10 9 8 7 6 5 4 DIVP3[6:0] DIVN3[8:0] rw rw 3 Bit 31 Reserved, must be kept at reset value. Bits 30:24 DIVR3[6:0]: PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). 0000000: pll3_r_ck = vco3_ck 0000001: pll3_r_ck = vco3_ck / 2 (default after reset) 0000010: pll3_r_ck = vco3_ck / 3 0000011: pll3_r_ck = vco3_ck / 4 ... 1111111: pll3_r_ck = vco3_ck / 128 Bit 23 Reserved, must be kept at reset value. 362/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bits 22:16 DIVQ3[6:0]: PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). 0000000: pll3_q_ck = vco3_ck 0000001: pll3_q_ck = vco3_ck / 2 (default after reset) 0000010: pll3_q_ck = vco3_ck / 3 0000011: pll3_q_ck = vco3_ck / 4 ... 1111111: pll3_q_ck = vco3_ck / 128 Bits 15:9 DIVP3[6:0]: PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). 0000000: pll3_p_ck = vco3_ck 0000001: pll3_p_ck = vco3_ck / 2 (default after reset) 0000010: pll3_p_ck = vco3_ck / 3 0000011: pll3_p_ck = vco3_ck / 4 ... 1111111: pll3_p_ck = vco3_ck / 128 Bits 8:0 DIVN3[7:0]: Multiplication factor for PLL3 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = ‘0’ and PLL3RDY = ‘0’). Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: – 192 to 836 MHz if PLL3VCOSEL = ‘0’ – 150 to 420 MHz if PLL3VCOSEL = ‘1’ VCO output frequency = Fref3_ck x DIVN3, when fractional value 0 has been loaded into FRACN3, with – DIVN3 between 4 and 512 – The input frequency Fref3_ck between 1MHz and 16MHz 0x003: DIVN3 = 4 0x004: DIVN3 = 5 0x005: DIVN3 = 6 ... 0x080: DIVN3 = 129 (default after reset) ... 0x1FF: DIVN3 = 512 Others: wrong configurations DocID029587 Rev 3 363/3178 457 Reset and Clock Control (RCC) 8.7.16 RM0433 RCC PLL3 Fractional Divider Register (RCC_PLL3FRACR) Address offset: 0x044 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. FRACN3[12:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:3 FRACN3[12:0]: Fractional part of the multiplication factor for PLL3 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: – 192 to 836 MHz if PLL3VCOSEL = ‘0’ – 150 to 420 MHz if PLL3VCOSEL = ‘1’ VCO output frequency = Fref3_ck x (DIVN3 + (FRACN3 / 213)), with – DIVN3 shall be between 4 and 512 – FRACN3 can be between 0 and 213 - 1 – The input frequency Fref3_ck shall be between 1 and 16 MHz In order to change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as follow: – set the bit PLL1FRACEN to ‘0’, – write the new fractional value into FRACN1, – set the bit PLL1FRACEN to ‘1’. Bits 2:0 Reserved, must be kept at reset value. 364/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.17 RCC Domain 1 Kernel Clock Configuration Register (RCC_D1CCIPR) Address offset: 0x04C 31 30 Res. Res. 29 28 CKPERSEL[1:0] (1) 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMCSEL (1) Reset value: 0x0000 0000 rw rw 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5 4 QSPISEL[1:0] (1) 3 2 Res. Res. rw 1 0 FMCSEL[1:0] (1) rw 1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make use that both the previous and the new clock sources are present during the switching, and during the whole transition time. Please refer to Section : Clock switches and gating. Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 CKPERSEL[1:0]: per_ck clock source selection 00: hsi_ker_ck clock selected as per_ck clock (default after reset) 01: csi_ker_ck clock selected as per_ck clock 10: hse_ck clock selected as per_ck clock 11: reserved, the per_ck clock is disabled Bits 27:17 Reserved, must be kept at reset value. Bit 16 SDMMCSEL: SDMMC kernel clock source selection 0: pll1_q_ck clock is selected as kernel peripheral clock (default after reset) 1: pll2_r_ck clock is selected as kernel peripheral clock Bits 15:6 Reserved, must be kept at reset value. Bits 5:4 QSPISEL[1:0]: QUADSPI kernel clock source selection 00: rcc_hclk3 clock selected as kernel peripheral clock (default after reset) 01: pll1_q_ck clock selected as kernel peripheral clock 10: pll2_r_ck clock selected as kernel peripheral clock 11: per_ck clock selected as kernel peripheral clock Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 FMCSEL[1:0]: FMC kernel clock source selection 00: rcc_hclk3 clock selected as kernel peripheral clock (default after reset) 01: pll1_q_ck clock selected as kernel peripheral clock 10: pll2_r_ck clock selected as kernel peripheral clock 11: per_ck clock selected as kernel peripheral clock DocID029587 Rev 3 365/3178 457 Reset and Clock Control (RCC) 8.7.18 RM0433 RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP1R) Address offset: 0x050 Res. 29 28 rw 27 26 25 24 23 22 Res. Res. Res. DFSDM1SEL (1) 30 FDCANSEL[1:0] (1) 31 SWPSEL (1) Reset value: 0x0000 0000 Res. Res. rw 15 14 13 12 11 10 9 Res. Res. Res. 8 rw 20 SPDIFSEL[1:0] (1) rw SPI123SEL[2:0] (1) Res. 21 19 Res. 18 7 6 rw 5 4 3 Res. Res. Res. rw 2 1 SAI1SEL[2:0] (1) rw 1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make sure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section : Clock switches and gating. Bit 31 SWPSEL: SWPMI kernel clock source selection Set and reset by software. 0: pclk is selected as SWPMI kernel clock (default after reset) 1: hsi_ker_ck clock is selected as SWPMI kernel clock Bit 30 Reserved, must be kept at reset value. Bits 29:28 FDCANSEL: FDCAN kernel clock source selection Set and reset by software. 00: hse_ck clock is selected as FDCAN kernel clock (default after reset) 01: pll1_q_ck clock is selected as FDCAN kernel clock 10: pll2_q_ck clock is selected as FDCAN kernel clock 11: reserved, the kernel clock is disabled Bits 27:25 Reserved, must be kept at reset value. Bit 24 DFSDM1SEL: DFSDM1 kernel Clk clock source selection Set and reset by software. Note: the DFSDM1 Aclk Clock Source Selection is done by SAI1SEL. 0: rcc_pclk2 is selected as DFSDM1 Clk kernel clock (default after reset) 1: sys_ck clock is selected as DFSDM1 Clk kernel clock Bits 23:22 Reserved, must be kept at reset value. Bits 21:20 SPDIFSEL[1:0]: SPDIFRX kernel clock source selection 00: pll1_q_ck clock selected as SPDIFRX kernel clock (default after reset) 01: pll2_r_ck clock selected as SPDIFRX kernel clock 10: pll3_r_ck clock selected as SPDIFRX kernel clock 11: hsi_ker_ck clock selected as SPDIFRX kernel clock Bit 19 Reserved, must be kept at reset value. 366/3178 DocID029587 Rev 3 16 SPI45SEL[2:0] (1) rw SAI23SEL[2:0] (1) 17 0 RM0433 Reset and Clock Control (RCC) Bits 18:16 SPI45SEL[2:0]: SPI4 and 5 kernel clock source selection Set and reset by software. 000: APB clock is selected as kernel clock (default after reset) 001: pll2_q_ck clock is selected as kernel clock 010: pll3_q_ck clock is selected as kernel clock 011: hsi_ker_ck clock is selected as kernel clock 100: csi_ker_ck clock is selected as kernel clock 101: hse_ck clock is selected as kernel clock others: reserved, the kernel clock is disabled Bit 15 Reserved, must be kept at reset value. Bits 14:12 SPI123SEL[2:0]: SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information. 000: pll1_q_ck clock selected as SPI/I2S1,2 and 3 kernel clock (default after reset) 001: pll2_p_ck clock selected as SPI/I2S1,2 and 3 kernel clock 010: pll3_p_ck clock selected as SPI/I2S1,2 and 3 kernel clock 011: I2S_CKIN clock selected as SPI/I2S1,2 and 3 kernel clock 100: per_ck clock selected as SPI/I2S1,2 and 3 kernel clock others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. Bits 11:9 Reserved, must be kept at reset value. DocID029587 Rev 3 367/3178 457 Reset and Clock Control (RCC) RM0433 Bits 8:6 SAI23SEL[2:0]: SAI2 and SAI3 kernel clock source selection Set and reset by software. Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information. 000: pll1_q_ck clock selected as SAI2 and SAI3 kernel clock (default after reset) 001: pll2_p_ck clock selected as SAI2 and SAI3 kernel clock 010: pll3_p_ck clock selected as SAI2 and SAI3 kernel clock 011: I2S_CKIN clock selected as SAI2 and SAI3 kernel clock 100: per_ck clock selected as SAI2 and SAI3 kernel clock others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. Bits 5:3 Reserved, must be kept at reset value. Bits 2:0 SAI1SEL[2:0]: SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information. Note: DFSDM1 Clock Source Selection is done by DFSDM1SEL. 000: pll1_q_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock (default after reset) 001: pll2_p_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock 010: pll3_p_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock 011: I2S_CKIN clock selected as SAI1 and DFSDM1 Aclk kernel clock 100: per_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 368/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.19 RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP2R) Address offset: 0x054 Reset value: 0x0000 0000 31 Res. 30 29 28 LPTIM1SEL[2:0] (1) 27 Res. 26 Res. 25 24 Res. Res. 23 CECSEL[1:0] rw 15 14 Res. Res. 22 21 (1) USBSEL[1:0] rw 13 12 I2C123SEL[1:0] (1) rw 11 10 Res. Res. 9 8 RNGSEL[1:0] (1) 20 (1) 19 18 17 16 Res. Res. Res. Res. 3 2 1 0 rw 7 6 Res. Res. 5 4 USART16SEL[2:0] (1) USART234578SEL[2:0] (1) rw rw rw 1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make sure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section : Clock switches and gating. Bit 31 Reserved, must be kept at reset value. Bits 30:28 LPTIM1SEL[2:0]: LPTIM1 kernel clock source selection Set and reset by software. 000: rcc_pclk1 clock selected as kernel peripheral clock (default after reset) 001: pll2_p_ck clock selected as kernel peripheral clock 010: pll3_r_ck clock selected as kernel peripheral clock 011: lse_ck clock selected as kernel peripheral clock 100: lsi_ck clock selected as kernel peripheral clock 101: per_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled Bits 27:24 Reserved, must be kept at reset value. Bits 23:22 CECSEL[1:0]: HDMI-CEC kernel clock source selection Set and reset by software. 00: lse_ck clock is selected as kernel clock (default after reset) 01: lsi_ck clock is selected as kernel clock 10: csi_ker_ck divided by 122 is selected as kernel clock 11: reserved, the kernel clock is disabled Bits 21:20 USBSEL[1:0]: USBOTG 1 and 2 kernel clock source selection Set and reset by software. 00: Disable the kernel clock (default after reset) 01: pll1_q_ck clock is selected as kernel clock 10: pll3_q_ck clock is selected as kernel clock 11: hsi48_ck clock is selected as kernel clock Bits 19:14 Reserved, must be kept at reset value. Bits 13:12 I2C123SEL[1:0]: I2C1,2,3 kernel clock source selection Set and reset by software. 00: rcc_pclk1 clock is selected as kernel clock (default after reset) 01: pll3_r_ck clock is selected as kernel clock 10: hsi_ker_ck clock is selected as kernel clock 11: csi_ker_ck clock is selected as kernel clock DocID029587 Rev 3 369/3178 457 Reset and Clock Control (RCC) RM0433 Bits 11:10 Reserved, must be kept at reset value. Bits 9:8 RNGSEL[1:0]: RNG kernel clock source selection Set and reset by software. 00: hsi8_ck clock is selected as kernel clock (default after reset) 01: pll1_q_ck clock is selected as kernel clock 10: lse_ck clock is selected as kernel clock 11: lsi_ck clock is selected as kernel clock Bits 7:6 Reserved, must be kept at reset value. Bits 5:3 USART16SEL[2:0]: USART1 and 6 kernel clock source selection Set and reset by software. 000: rcc_pclk2 clock is selected as kernel clock (default after reset) 001: pll2_q_ck clock is selected as kernel clock 010: pll3_q_ck clock is selected as kernel clock 011: hsi_ker_ck clock is selected as kernel clock 100: csi_ker_ck clock is selected as kernel clock 101: lse_ck clock is selected as kernel clock others: reserved, the kernel clock is disabled Bits 2:0 USART234578SEL[2:0]: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection Set and reset by software. 000: rcc_pclk1 clock is selected as kernel clock (default after reset) 001: pll2_q_ck clock is selected as kernel clock 010: pll3_q_ck clock is selected as kernel clock 011: hsi_ker_ck clock is selected as kernel clock 100: csi_ker_ck clock is selected as kernel clock 101: lse_ck clock is selected as kernel clock others: reserved, the kernel clock is disabled 370/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.20 RCC Domain 3 Kernel Clock Configuration Register (RCC_D3CCIPR) Address offset: 0x058 Reset value: 0x0000 0000 31 Res. 30 29 SPI6SEL[2:0] 28 (1) 27 Res. 26 14 13 24 SAI4BSEL[2:0] rw 15 25 (1) 23 SAI4ASEL[2:0] rw 12 11 10 22 21 (1) 20 19 18 Res. Res. Res. 2 17 ADCSEL[1:0] (1) rw 9 8 LPTIM345SEL[2:0] (1) LPTIM2SEL[2:0] (1) I2C4SEL[1:0] (1) rw rw rw 16 rw 7 6 5 4 3 Res. Res. Res. Res. Res. 1 0 LPUART1SEL[2:0] (1) rw 1. Changing the clock source on-the-fly is allowed, and will not generate any timing violation. However the user has to make sure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section : Clock switches and gating. Bit 31 Bits 30:28 Bit 27 Bits 26:24 Reserved, must be kept at reset value. SPI6SEL[2:0]: SPI6 kernel clock source selection Set and reset by software. 000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset) 001: pll2_q_ck clock selected as kernel peripheral clock 010: pll3_q_ck clock selected as kernel peripheral clock 011: hsi_ker_ck clock selected as kernel peripheral clock 100: csi_ker_ck clock selected as kernel peripheral clock 101: hse_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled Reserved, must be kept at reset value. SAI4BSEL[2:0]: Sub-Block B of SAI4 kernel clock source selection Set and reset by software. Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information. 000: pll1_q_ck clock selected as kernel peripheral clock (default after reset) 001: pll2_p_ck clock selected as kernel peripheral clock 010: pll3_p_ck clock selected as kernel peripheral clock 011: I2S_CKIN clock selected as kernel peripheral clock 100: per_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. DocID029587 Rev 3 371/3178 457 Reset and Clock Control (RCC) Bits 23:21 RM0433 SAI4ASEL[2:0]: Sub-Block A of SAI4 kernel clock source selection Set and reset by software. Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information. 000: pll1_q_ck clock selected as kernel peripheral clock (default after reset) 001: pll2_p_ck clock selected as kernel peripheral clock 010: pll3_p_ck clock selected as kernel peripheral clock 011: I2S_CKIN clock selected as kernel peripheral clock 100: per_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. Bits 20:18 Reserved, must be kept at reset value. Bits 17:16 ADCSEL[1:0]: SAR ADC kernel clock source selection Set and reset by software. 00: pll2_p_ck clock selected as kernel peripheral clock (default after reset) 01: pll3_r_ck clock selected as kernel peripheral clock 10: per_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled Bits 15:13 LPTIM345SEL[2:0]: LPTIM3,4,5 kernel clock source selection Set and reset by software. 000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset) 001: pll2_p_ck clock selected as kernel peripheral clock 010: pll3_r_ck clock selected as kernel peripheral clock 011: lse_ck clock selected as kernel peripheral clock 100: lsi_ck clock selected as kernel peripheral clock 101: per_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled Bits 12:10 LPTIM2SEL[2:0]: LPTIM2 kernel clock source selection Set and reset by software. 000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset) 001: pll2_p_ck clock selected as kernel peripheral clock 010: pll3_r_ck clock selected as kernel peripheral clock 011: lse_ck clock selected as kernel peripheral clock 100: lsi_ck clock selected as kernel peripheral clock 101: per_ck clock selected as kernel peripheral clock others: reserved, the kernel clock is disabled 372/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bits 9:8 I2C4SEL[1:0]: I2C4 kernel clock source selection Set and reset by software. 00: rcc_pclk4 clock selected as kernel peripheral clock (default after reset) 01: pll3_r_ck clock selected as kernel peripheral clock 10: hsi_ker_ck clock selected as kernel peripheral clock 11: csi_ker_ck clock selected as kernel peripheral clock Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LPUART1SEL[2:0]: LPUART1 kernel clock source selection Set and reset by software. 000: rcc_pclk_d3 clock is selected as kernel peripheral clock (default after reset) 001: pll2_q_ck clock is selected as kernel peripheral clock 010: pll3_q_ck clock is selected as kernel peripheral clock 011: hsi_ker_ck clock is selected as kernel peripheral clock 100: csi_ker_ck clock is selected as kernel peripheral clock 101: lse_ck clock is selected as kernel peripheral clock others: reserved, the kernel clock is disabled DocID029587 Rev 3 373/3178 457 Reset and Clock Control (RCC) 8.7.21 RM0433 RCC Clock Source Interrupt Enable Register (RCC_CIER) Address offset: 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. LSECSSIE PLL3RDYIE PLL2RDYIE PLL1RDYIE HSI48RDYIE CSIRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE Reset value: 0x0000 0000 rw rw rw rw rw rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSIE: LSE clock security system Interrupt Enable Set and reset by software to enable/disable interrupt caused by the Clock Security System on external 32 kHz oscillator. 0: LSE CSS interrupt disabled (default after reset) 1: LSE CSS interrupt enabled Bit 8 PLL3RDYIE: PLL3 ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by PLL3 lock. 0: PLL3 lock interrupt disabled (default after reset) 1: PLL3 lock interrupt enabled Bit 7 PLL2RDYIE: PLL2 ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by PLL2 lock. 0: PLL2 lock interrupt disabled (default after reset) 1: PLL2 lock interrupt enabled Bit 6 PLL1RDYIE: PLL1 ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. 0: PLL1 lock interrupt disabled (default after reset) 1: PLL1 lock interrupt enabled Bit 5 HSI48RDYIE: HSI48 ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. 0: HSI48 ready interrupt disabled (default after reset) 1: HSI48 ready interrupt enabled Bit 4 CSIRDYIE: CSI ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. 0: CSI ready interrupt disabled (default after reset) 1: CSI ready interrupt enabled Bit 3 HSERDYIE: HSE ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. 0: HSE ready interrupt disabled (default after reset) 1: HSE ready interrupt enabled 374/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 2 HSIRDYIE: HSI ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. 0: HSI ready interrupt disabled (default after reset) 1: HSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled (default after reset) 1: LSE ready interrupt enabled Bit 0 LSIRDYIE: LSI ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0: LSI ready interrupt disabled (default after reset) 1: LSI ready interrupt enabled DocID029587 Rev 3 375/3178 457 Reset and Clock Control (RCC) 8.7.22 RM0433 RCC Clock Source Interrupt Flag Register (RCC_CIFR) Address offset: 0x64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. HSECSSF LSECSSF PLL3RDYF PLL2RDYF PLL1RDYF HSI48RDYF CSIRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF Reset value: 0x0000 0000 r r r r r r r r r r r Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSECSSF: HSE clock security system Interrupt Flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. 0: No clock security interrupt caused by HSE clock failure (default after reset) 1: Clock security interrupt caused by HSE clock failure Bit 9 LSECSSF: LSE clock security system Interrupt Flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. 0: No failure detected on the external 32 kHz oscillator (default after reset) 1: A failure is detected on the external 32 kHz oscillator Bit 8 PLL3RDYF: PLL3 ready Interrupt Flag Reset by software by writing PLL3RDYC bit. Set by hardware when the PLL3 locks and PLL3RDYIE is set. 0: No clock ready interrupt caused by PLL3 lock (default after reset) 1: Clock ready interrupt caused by PLL3 lock Bit 7 PLL2RDYF: PLL2 ready Interrupt Flag Reset by software by writing PLL2RDYC bit. Set by hardware when the PLL2 locks and PLL2RDYIE is set. 0: No clock ready interrupt caused by PLL2 lock (default after reset) 1: Clock ready interrupt caused by PLL2 lock Bit 6 PLL1RDYF: PLL1 ready Interrupt Flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. 0: No clock ready interrupt caused by PLL1 lock (default after reset) 1: Clock ready interrupt caused by PLL1 lock Bit 5 HSI48RDYF: HSI48 ready Interrupt Flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. 0: No clock ready interrupt caused by the HSI48 oscillator (default after reset) 1: Clock ready interrupt caused by the HSI48 oscillator 376/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 4 CSIRDYF: CSI ready Interrupt Flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. 0: No clock ready interrupt caused by the CSI (default after reset) 1: Clock ready interrupt caused by the CSI Bit 3 HSERDYF: HSE ready Interrupt Flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. 0: No clock ready interrupt caused by the HSE (default after reset) 1: Clock ready interrupt caused by the HSE Bit 2 HSIRDYF: HSI ready Interrupt Flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. 0: No clock ready interrupt caused by the HSI (default after reset) 1: Clock ready interrupt caused by the HSI Bit 1 LSERDYF: LSE ready Interrupt Flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. 0: No clock ready interrupt caused by the LSE (default after reset) 1: Clock ready interrupt caused by the LSE Bit 0 LSIRDYF: LSI ready Interrupt Flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. 0: No clock ready interrupt caused by the LSI (default after reset) 1: Clock ready interrupt caused by the LSI DocID029587 Rev 3 377/3178 457 Reset and Clock Control (RCC) 8.7.23 RM0433 RCC Clock Source Interrupt Clear Register (RCC_CICR) Address offset: 0x68 Reset value: 0x0000 0000 20 19 18 17 16 Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. LSIRDYC 21 Res. LSERDYC 22 Res. HSIRDYC 23 Res. HSERDYC 24 Res. CSIRDYC 25 Res. HSI48RDYC 26 Res. PLL1RDYC 27 Res. PLL2RDYC 28 Res. PLL3RDYC 29 Res. LSECSSC 30 Res. HSECSSC 31 Res. rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSECSSC: HSE clock security system Interrupt Clear Set by software to clear HSECSSF. Reset by hardware when clear done. 0: HSECSSF no effect (default after reset) 1: HSECSSF cleared Bit 9 LSECSSC: LSE clock security system Interrupt Clear Set by software to clear LSECSSF. Reset by hardware when clear done. 0: LSECSSF no effect (default after reset) 1: LSECSSF cleared Bit 8 PLL3RDYC: PLL3 ready Interrupt Clear Set by software to clear PLL3RDYF. Reset by hardware when clear done. 0: PLL3RDYF no effect (default after reset) 1: PLL3RDYF cleared Bit 7 PLL2RDYC: PLL2 ready Interrupt Clear Set by software to clear PLL2RDYF. Reset by hardware when clear done. 0: PLL2RDYF no effect (default after reset) 1: PLL2RDYF cleared Bit 6 PLL1RDYC: PLL1 ready Interrupt Clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. 0: PLL1RDYF no effect (default after reset) 1: PLL1RDYF cleared Bit 5 HSI48RDYC: HSI48 ready Interrupt Clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. 0: HSI48RDYF no effect (default after reset) 1: HSI48RDYF cleared 378/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 4 CSIRDYC: CSI ready Interrupt Clear Set by software to clear CSIRDYF. Reset by hardware when clear done. 0: CSIRDYF no effect (default after reset) 1: CSIRDYF cleared Bit 3 HSERDYC: HSE ready Interrupt Clear Set by software to clear HSERDYF. Reset by hardware when clear done. 0: HSERDYF no effect (default after reset) 1: HSERDYF cleared Bit 2 HSIRDYC: HSI ready Interrupt Clear Set by software to clear HSIRDYF. Reset by hardware when clear done. 0: HSIRDYF no effect (default after reset) 1: HSIRDYF cleared Bit 1 LSERDYC: LSE ready Interrupt Clear Set by software to clear LSERDYF. Reset by hardware when clear done. 0: LSERDYF no effect (default after reset) 1: LSERDYF cleared Bit 0 LSIRDYC: LSI ready Interrupt Clear Set by software to clear LSIRDYF. Reset by hardware when clear done. 0: LSIRDYF no effect (default after reset) 1: LSIRDYF cleared DocID029587 Rev 3 379/3178 457 Reset and Clock Control (RCC) 8.7.24 RM0433 RCC Backup Domain Control Register (RCC_BDCR) Address offset: 0x070 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 ≤ wait state ≤ 7, word, half-word and byte access. Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST After a system reset, the RCC_BDCR register is write-protected. To modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to ‘1’. RCC_BDCR bits are only reset after a backup domain reset (see Section 8.4.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits. 10 Res. Res. Res. Res. Res. rw 9 8 RTCSEL[1:0] 7 6 5 Res. r rwo 2 1 0 LSEDRV[1:0] LSEON 11 LSERDY 12 LSEBYP 13 LSECSSON 14 LSECSSD 15 RTCEN rw 4 3 rs rw rw r rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and reset by software. 0: Reset not activated (default after backup domain reset) 1: Resets the entire VSW domain Bit 15 RTCEN: RTC clock enable Set and reset by software. 0: rtc_ck clock is disabled (default after backup domain reset) 1: rtc_ck clock enabled Bits 14:10 Reserved, must be kept at reset value. Bits 9:8 RTCSEL[1:0]:RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The BDRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock: this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). 00: No clock (default after backup domain reset) 01: LSE clock used as RTC clock 10: LSI clock used as RTC clock 11: HSE clock divided by RTCPRE value is used as RTC clock Bit 7 Reserved, must be kept at reset value. 380/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 6 LSECSSD: LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator. 0: No failure detected on 32 kHz oscillator (default after backup domain reset) 1: Failure detected on 32 kHz oscillator Bit 5 LSECSSON: LSE clock security system enable Set by software to enable the Clock Security System on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware), and after RTCSEL is selected. Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD = ‘1’). In that case the software must disable LSECSSON. 0: Clock Security System on 32 kHz oscillator OFF (default after backup domain reset) 1: Clock Security System on 32 kHz oscillator ON Bits 4:3 LSEDRV[1:0]: LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. 00: Lowest drive (default after backup domain reset) 01: Medium low drive 10: Medium high drive 11: Highest drive Bit 2 LSEBYP: LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = ‘1’) 0: LSE oscillator not bypassed (default after backup domain reset) 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to ‘0’. 0: LSE oscillator not ready (default after backup domain reset) 1: LSE oscillator ready Bit 0 LSEON: LSE oscillator enabled Set and reset by software. 0: LSE oscillator OFF (default after backup domain reset) 1: LSE oscillator ON DocID029587 Rev 3 381/3178 457 Reset and Clock Control (RCC) 8.7.25 RM0433 RCC Clock Control and Status Register (RCC_CSR) Address offset: 0x074 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 7, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSIRDY LSION Wait states are inserted in case of successive accesses to this register. r rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: LSI oscillator ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to ‘0’. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the Clock Security System on LSE or by the Low Speed Watchdog or by the RTC. 0: LSI clock is not ready (default after reset) 1: LSI clock is ready Bit 0 LSION: LSI oscillator enable Set and reset by software. 0: LSI is OFF (default after reset) 1: LSI is ON 382/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.26 RCC AHB3 Reset Register (RCC_AHB3RSTR) Address offset: 0x07C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CPURST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC1RST Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. FMCRST Res. Res. Res. Res. Res. Res. JPGDECRST DMA2DRST Res. Res. Res. MDMARST rw QSPIRST rs rw rw rw rw rw Bit 31 CPURST: CPU reset Set by software, Reset by hardware 0: does not reset the CPU (default after reset) 1: resets the CPU, bit auto cleared to ‘0’. Bits 30:17 Reserved, must be kept at reset value. Bit 16 SDMMC1RST: SDMMC1 and SDMMC1 delay block reset Set and reset by software. 0: does not reset SDMMC1 and SDMMC1 Delay block (default after reset) 1: resets SDMMC1 and SDMMC1 Delay block Bit 15 Reserved, must be kept at reset value. Bit 14 QSPIRST: QUADSPI and QUADSPI delay block reset Set and reset by software. 0: does not reset QUADSPI and QUADSPI Delay block (default after reset) 1: resets QUADSPI and QUADSPI Delay block Bit 13 Reserved, must be kept at reset value. Bit 12 FMCRST: FMC block reset Set and reset by software. 0: does not reset FMC block (default after reset) 1: resets FMC block Bits 11:6 Reserved, must be kept at reset value. Bit 5 JPGDECRST: JPGDEC block reset Set and reset by software. 0: does not reset JPGDEC block (default after reset) 1: resets JPGDEC block DocID029587 Rev 3 383/3178 457 Reset and Clock Control (RCC) RM0433 Bit 4 DMA2DRST: DMA2D block reset Set and reset by software. 0: does not reset DMA2D block (default after reset) 1: resets DMA2D block Bits 3:1 Reserved, must be kept at reset value. Bit 0 MDMARST: MDMA block reset Set and reset by software. 0: does not reset MDMA block (default after reset) 1: resets MDMA block 384/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.27 RCC AHB1 Peripheral Reset Register(RCC_AHB1RSTR) Address offset: 0x080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. USB2OTGRST Res. USB1OTGRST Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETH1MACRST Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12RST Res. Res. Res. DMA2RST DMA1RST Reset value: 0x0000 0000 rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bit 27 USB2OTGRST: USB2OTG block reset Set and reset by software. 0: does not reset USB2OTG block (default after reset) 1: resets USB2OTG block Bit 26 Reserved, must be kept at reset value. Bit 25 USB1OTGRST: USB1OTG block reset Set and reset by software. 0: does not reset USB1OTG block (default after reset) 1: resets USB1OTG block Bits 24:16 Reserved, must be kept at reset value. Bit 15 ETH1MACRST: ETH1MAC block reset Set and reset by software. 0: does not reset ETH1MAC block (default after reset) 1: resets ETH1MAC block Bits 14:6 Reserved, must be kept at reset value. Bit 5 ADC12RST: ADC1 and 2 block reset Set and reset by software. 0: does not reset ADC1 and 2 block (default after reset) 1: resets ADC1 and 2 block DocID029587 Rev 3 385/3178 457 Reset and Clock Control (RCC) RM0433 Bits 4:2 Reserved, must be kept at reset value. Bit 1 DMA2RST: DMA2 block reset Set and reset by software. 0: does not reset DMA2 block (default after reset) 1: resets DMA2 block Bit 0 DMA1RST: DMA1 block reset Set and reset by software. 0: does not reset DMA1 block (default after reset) 1: resets DMA1 block 386/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.28 RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR) Address offset: 0x084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. SDMMC2RST Res. Res. RNGRST HASHRST CRYPTRST Res. Res. Res. CAMITFRST Reset value: 0x0000 0000 rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 SDMMC2RST: SDMMC2 and SDMMC2 Delay block reset Set and reset by software. 0: does not reset SDMMC2 and SDMMC2 Delay block (default after reset) 1: resets SDMMC2 and SDMMC2 Delay block Bits 8:7 Reserved, must be kept at reset value. Bit 6 RNGRST: Random Number Generator block reset Set and reset by software. 0: does not reset RNG block (default after reset) 1: resets RNG block Bit 5 HASHRST: Hash block reset Set and reset by software. 0: does not reset hash block (default after reset) 1: resets hash block Bit 4 CRYPTRST: Cryptography block reset Set and reset by software. 0: does not reset cryptography block (default after reset) 1: resets cryptography block Bits 3:1 Reserved, must be kept at reset value. Bit 0 CAMITFRST: CAMITF block reset Set and reset by software. 0: does not reset the CAMITF block (default after reset) 1: resets the CAMITF block DocID029587 Rev 3 387/3178 457 Reset and Clock Control (RCC) 8.7.29 RM0433 RCC AHB4 Peripheral Reset Register (RCC_AHB4RSTR) Address offset: 0x088 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. HSEMRST ADC3RST Res. Res. BDMARST Res. CRCRST Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. GPIOKRST GPIOJRST GPIOIRST GPIOHRST GPIOGRST GPIOFRST GPIOERST GPIODRST GPIOCRST GPIOBRST GPIOARST Reset value: 0x0000 0000 rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 HSEMRST: HSEM block reset Set and reset by software. 0: does not reset the HSEM block (default after reset) 1: resets the HSEM block Bit 24 ADC3RST: ADC3 block reset Set and reset by software. 0: does not reset the ADC3 block (default after reset) 1: resets the ADC3 block Bits 23:22 Reserved, must be kept at reset value. Bit 21 BDMARST: BDMA block reset Set and reset by software. 0: does not reset the BDMA block (default after reset) 1: resets the BDMA block Bit 20 Reserved, must be kept at reset value. Bit 19 CRCRST: CRC block reset Set and reset by software. 0: does not reset the CRC block (default after reset) 1: resets the CRC block Bits 18:11 Reserved, must be kept at reset value. Bit 10 GPIOKRST: GPIOK block reset Set and reset by software. 0: does not reset the GPIOK block (default after reset) 1: resets the GPIOK block Bit 9 GPIOJRST: GPIOJ block reset Set and reset by software. 0: does not reset the GPIOJ block (default after reset) 1: resets the GPIOJ block 388/3178 DocID029587 Rev 3 rw RM0433 Reset and Clock Control (RCC) Bit 8 GPIOIRST: GPIOI block reset Set and reset by software. 0: does not reset the GPIOI block (default after reset) 1: resets the GPIOI block Bit 7 GPIOHRST: GPIOH block reset Set and reset by software. 0: does not reset the GPIOH block (default after reset) 1: resets the GPIOH block Bit 6 GPIOGRST: GPIOG block reset Set and reset by software. 0: does not reset the GPIOG block (default after reset) 1: resets the GPIOG block Bit 5 GPIOFRST: GPIOF block reset Set and reset by software. 0: does not reset the GPIOF block (default after reset) 1: resets the GPIOF block Bit 4 GPIOERST: GPIOE block reset Set and reset by software. 0: does not reset the GPIOE block (default after reset) 1: resets the GPIOE block Bit 3 GPIODRST: GPIOD block reset Set and reset by software. 0: does not reset the GPIOD block (default after reset) 1: resets the GPIOD block Bit 2 GPIOCRST: GPIOC block reset Set and reset by software. 0: does not reset the GPIOC block (default after reset) 1: resets the GPIOC block Bit 1 GPIOBRST: GPIOB block reset Set and reset by software. 0: does not reset the GPIOB block (default after reset) 1: resets the GPIOB block Bit 0 GPIOARST: GPIOA block reset Set and reset by software. 0: does not reset the GPIOA block (default after reset) 1: resets the GPIOA block DocID029587 Rev 3 389/3178 457 Reset and Clock Control (RCC) 8.7.30 RM0433 RCC APB3 Peripheral Reset Register (RCC_APB3RSTR) Address offset: 0x08C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDCRST Reset value: 0x0000 0000 Res. Res. Res. rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 LTDCRST: LTDC block reset Set and reset by software. 0: does not reset the LTDC block (default after reset) 1: resets the LTDC block Bits 2:0 Reserved, must be kept at reset value. 390/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.31 RCC APB1 Peripheral Reset Register (RCC_APB1LRSTR) Address offset: 0x090 SPDIFRXRST Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. TIM2RST HDMICECRST Res. USART2RST DAC12RST Res. TIM3RST UART7RST Res. USART3RST 16 TIM4RST 17 UART4RST 18 TIM5RST 19 UART5RST 20 TIM6RST 21 I2C1RST 22 TIM7RST 23 I2C2RST 24 TIM12RST 25 I2C3RST 26 TIM13RST 27 TIM14RST 28 LPTIM1RST 29 SPI2RST 30 SPI3RST 31 UART8RST Reset value: 0x0000 0000 rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 UART8RST: UART8 block reset Set and reset by software. 0: does not reset the UART8 block (default after reset) 1: resets the UART8 block Bit 30 UART7RST: UART7 block reset Set and reset by software. 0: does not reset the UART7 block (default after reset) 1: resets the UART7 block Bit 29 DAC12RST: DAC1 and 2 Blocks Reset Set and reset by software. 0: does not reset the DAC1 and 2 blocks (default after reset) 1: resets the DAC1 and 2 blocks Bit 28 Reserved, must be kept at reset value. Bit 27 HDMICECRST: HDMI-CEC block reset Set and reset by software. 0: does not reset the HDMI-CEC block (default after reset) 1: resets the HDMI-CEC block Bits 26:24 Reserved, must be kept at reset value. Bit 23 I2C3RST: I2C3 block reset Set and reset by software. 0: does not reset the I2C3 block (default after reset) 1: resets the I2C3 block Bit 22 I2C2RST: I2C2 block reset Set and reset by software. 0: does not reset the I2C2 block (default after reset) 1: resets the I2C2 block DocID029587 Rev 3 391/3178 457 Reset and Clock Control (RCC) RM0433 Bit 21 I2C1RST: I2C1 block reset Set and reset by software. 0: does not reset the I2C1 block (default after reset) 1: resets the I2C1 block Bit 20 UART5RST: UART5 block reset Set and reset by software. 0: does not reset the UART5 block (default after reset) 1: resets the UART5 block Bit 19 UART4RST: UART4 block reset Set and reset by software. 0: does not reset the UART4 block (default after reset) 1: resets the UART4 block Bit 18 USART3RST: USART3 block reset Set and reset by software. 0: does not reset the USART3 block (default after reset) 1: resets the USART3 block Bit 17 USART2RST: USART2 block reset Set and reset by software. 0: does not reset the USART2 block (default after reset) 1: resets the USART2 block Bit 16 SPDIFRXRST: SPDIFRX block reset Set and reset by software. 0: does not reset the SPDIFRX block (default after reset) 1: resets the SPDIFRX block Bit 15 SPI3RST: SPI3 block reset Set and reset by software. 0: does not reset the SPI3 block (default after reset) 1: resets the SPI3 block Bit 14 SPI2RST: SPI2 block reset Set and reset by software. 0: does not reset the SPI2 block (default after reset) 1: resets the SPI2 block Bits 13:10 Reserved, must be kept at reset value. Bit 9 LPTIM1RST: LPTIM1 block reset Set and reset by software. 0: does not reset the LPTIM1 block (default after reset) 1: resets the LPTIM1 block Bit 8 TIM14RST: TIM14 block reset Set and reset by software. 0: does not reset the TIM14 block (default after reset) 1: resets the TIM14 block Bit 7 TIM13RST: TIM13 block reset Set and reset by software. 0: does not reset the TIM13 block (default after reset) 1: resets the TIM13 block 392/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 6 TIM12RST: TIM12 block reset Set and reset by software. 0: does not reset the TIM12 block (default after reset) 1: resets the TIM12 block Bit 5 TIM7RST: TIM7 block reset Set and reset by software. 0: does not reset the TIM7 block (default after reset) 1: resets the TIM7 block Bit 4 TIM6RST: TIM6 block reset Set and reset by software. 0: does not reset the TIM6 block (default after reset) 1: resets the TIM6 block Bit 3 TIM5RST: TIM5 block reset Set and reset by software. 0: does not reset the TIM5 block (default after reset) 1: resets the TIM5 block Bit 2 TIM4RST: TIM4 block reset Set and reset by software. 0: does not reset the TIM4 block (default after reset) 1: resets the TIM4 block Bit 1 TIM3RST: TIM3 block reset Set and reset by software. 0: does not reset the TIM3 block (default after reset) 1: resets the TIM3 block Bit 0 TIM2RST: TIM2 block reset Set and reset by software. 0: does not reset the TIM2 block (default after reset) 1: resets the TIM2 block DocID029587 Rev 3 393/3178 457 Reset and Clock Control (RCC) 8.7.32 RM0433 RCC APB1 Peripheral Reset Register (RCC_APB1HRSTR) Address offset: 0x094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. FDCANRST Res. Res. MDIOSRST OPAMPRST Res. SWPRST CRSRST Reset value: 0x0000 0000 Res. rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 FDCANRST: FDCAN block reset Set and reset by software. 0: does not reset the FDCAN block (default after reset) 1: resets the FDCAN block Bits 7:6 Reserved, must be kept at reset value. Bit 5 MDIOSRST: MDIOS block reset Set and reset by software. 0: does not reset the MDIOS block (default after reset) 1: resets the MDIOS block Bit 4 OPAMPRST: OPAMP block reset Set and reset by software. 0: does not reset the OPAMP block (default after reset) 1: resets the OPAMP block Bit 3 Reserved, must be kept at reset value. Bit 2 SWPRST: SWPMI block reset Set and reset by software. 0: does not reset the SWPMI block (default after reset) 1: resets the SWPMI block Bit 1 CRSRST: Clock Recovery System reset Set and reset by software. 0: does not reset CRS (default after reset) 1: resets CRS Bit 0 Reserved, must be kept at reset value. 394/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.33 RCC APB2 Peripheral Reset Register (RCC_APB2RSTR) Address offset: 0x098 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. HRTIMRST DFSDM1RST Res. Res. Res. SAI3RST SAI2RST SAI1RST Res. SPI5RST Res. TIM17RST TIM16RST TIM15RST rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. SPI4RST SPI1RST Res. Res. Res. Res. Res. Res. USART6RST USART1RST Res. Res. TIM8RST TIM1RST Reset value: 0x0000 0000 rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 HRTIMRST: HRTIM block reset Set and reset by software. 0: does not reset the HRTIM block (default after reset) 1: resets the HRTIM block Bit 28 DFSDM1RST: DFSDM1 block reset Set and reset by software. 0: does not reset DFSDM1 block (default after reset) 1: resets DFSDM1 block Bits 27:25 Reserved, must be kept at reset value. Bit 24 SAI3RST: SAI3 block reset Set and reset by software. 0: does not reset the SAI3 block (default after reset) 1: resets the SAI3 block Bit 23 SAI2RST: SAI2 block reset Set and reset by software. 0: does not reset the SAI2 block (default after reset) 1: resets the SAI2 block Bit 22 SAI1RST: SAI1 block reset Set and reset by software. 0: does not reset the SAI1 (default after reset) 1: resets the SAI1 Bit 21 Reserved, must be kept at reset value. Bit 20 SPI5RST: SPI5 block reset Set and reset by software. 0: does not reset the SPI5 block (default after reset) 1: resets the SPI5 block Bit 19 Reserved, must be kept at reset value. DocID029587 Rev 3 395/3178 457 Reset and Clock Control (RCC) RM0433 Bit 18 TIM17RST: TIM17 block reset Set and reset by software. 0: does not reset the TIM17 block (default after reset) 1: resets the TIM17 block Bit 17 TIM16RST: TIM16 block reset Set and reset by software. 0: does not reset the TIM16 block (default after reset) 1: resets the TIM16 block Bit 16 TIM15RST: TIM15 block reset Set and reset by software. 0: does not reset the TIM15 block (default after reset) 1: resets the TIM15 block Bits 15:14 Reserved, must be kept at reset value. Bit 13 SPI4RST: SPI4 block reset Set and reset by software. 0: does not reset the SPI4 block (default after reset) 1: resets the SPI4 block Bit 12 SPI1RST: SPI1 block reset Set and reset by software. 0: does not reset the SPI1 block (default after reset) 1: resets the SPI1 block Bits 11:6 Reserved, must be kept at reset value. Bit 5 USART6RST: USART6 block reset Set and reset by software. 0: does not reset the USART6 block (default after reset) 1: resets the USART6 block Bit 4 USART1RST: USART1 block reset Set and reset by software. 0: does not reset the USART1 block (default after reset) 1: resets the USART1 block Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8RST: TIM8 block reset Set and reset by software. 0: does not reset the TIM8 block (default after reset) 1: resets the TIM8 block Bit 0 TIM1RST: TIM1 block reset Set and reset by software. 0: does not reset the TIM1 block (default after reset) 1: resets the TIM1 block 396/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.34 RCC APB4 Peripheral Reset Register (RCC_APB4RSTR) Address offset: 0x09C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4RST Reset value: 0x0000 0000 Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VREFRST COMP12RST Res. LPTIM5RST LPTIM4RST LPTIM3RST LPTIM2RST Res. I2C4RST Res. SPI6RST Res. LPUART1RST Res. SYSCFGRST rw Res. rw rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:22 Reserved, must be kept at reset value. Bit 21 SAI4RST: SAI4 block reset Set and reset by software. 0: does not reset the SAI4 block (default after reset) 1: resets the SAI4 block Bits 20:16 Reserved, must be kept at reset value. Bit 15 VREFRST: VREF block reset Set and reset by software. 0: does not reset the VREF block (default after reset) 1: resets the VREF block Bit 14 COMP12RST: COMP12 Blocks Reset Set and reset by software. 0: does not reset the COMP1 and 2 blocks (default after reset) 1: resets the COMP1 and 2 blocks Bit 13 Reserved, must be kept at reset value. Bit 12 LPTIM5RST: LPTIM5 block reset Set and reset by software. 0: does not reset the LPTIM5 block (default after reset) 1: resets the LPTIM5 block Bit 11 LPTIM4RST: LPTIM4 block reset Set and reset by software. 0: does not reset the LPTIM4 block (default after reset) 1: resets the LPTIM4 block Bit 10 LPTIM3RST: LPTIM3 block reset Set and reset by software. 0: does not reset the LPTIM3 block (default after reset) 1: resets the LPTIM3 block DocID029587 Rev 3 397/3178 457 Reset and Clock Control (RCC) RM0433 Bit 9 LPTIM2RST: LPTIM2 block reset Set and reset by software. 0: does not reset the LPTIM2 block (default after reset) 1: resets the LPTIM2 block Bit 8 Reserved, must be kept at reset value. Bit 7 I2C4RST: I2C4 block reset Set and reset by software. 0: does not reset the I2C4 block (default after reset) 1: resets the I2C4 block Bit 6 Reserved, must be kept at reset value. Bit 5 SPI6RST: SPI6 block reset Set and reset by software. 0: does not reset the SPI6 block (default after reset) 1: resets the SPI6 block Bit 4 Reserved, must be kept at reset value. Bit 3 LPUART1RST: LPUART1 block reset Set and reset by software. 0: does not reset the LPUART1 block (default after reset) 1: resets the LPUART1 block Bit 2 Reserved, must be kept at reset value. Bit 1 SYSCFGRST: SYSCFG block reset Set and reset by software. 0: does not reset the SYSCFG block (default after reset) 1: resets the SYSCFG block Bit 0 Reserved, must be kept at reset value. 398/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.35 RCC Global Control Register (RCC_GCR) Address offset: 0x0A0 Reset value: 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WW1RSC 31 Res. rw1 Bits 31:1 Reserved, must be kept at reset value. Bit 0 WW1RSC: WWDG1 reset scope control This bit can be set by software but is cleared by hardware during a system reset In order to work properly, before enabling the WWDG1, this bit must be set to ‘1’. DocID029587 Rev 3 399/3178 457 Reset and Clock Control (RCC) 8.7.36 RM0433 RCC D3 Autonomous mode Register (RCC_D3AMR) The Autonomous mode allows providing the peripheral clocks to peripherals located in D3, even if the CPU is in CStop mode. When a peripheral is enabled, and has its autonomous bit enabled, it receives its peripheral clocks according to D3 domain state, if the CPU is in CStop mode. Address offset: 0x0A8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. SRAM4AMEN BKPRAMAMEN Res. Res. Res. ADC3AMEN Res. Res. SAI4AMEN Res. CRCAMEN Res. Res. RTCAMEN rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VREFAMEN COMP12AMEN Res. LPTIM5AMEN LPTIM4AMEN LPTIM3AMEN LPTIM2AMEN Res. I2C4AMEN Res. SPI6AMEN Res. LPUART1AMEN Res. Res. BDMAAMEN Reset value: 0x0000 0000 rw rw rw rw rw rw Bits 31:30 rw rw rw rw rw rw rw Reserved, must be kept at reset value. Bit 29 SRAM4AMEN: SRAM4 Autonomous mode enable Set and reset by software. 0: SRAM4 clock is disabled when the CPU is in CStop (default after reset) 1: SRAM4 peripheral bus clock enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 28 BKPSRAMAMEN: Backup RAM Autonomous mode enable Set and reset by software. 0: Backup RAM clock is disabled when the CPU is in CStop (default after reset) 1: Backup RAM clock enabling is controlled by D3 domain state. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 27 Reserved, must be kept at reset value. Bits 26:25 Reserved, must be kept at reset value. Bit 24 Bits 23:22 ADC3AMEN: ADC3 Autonomous mode enable Set and reset by software. 0: ADC3 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: ADC3 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Reserved, must be kept at reset value. Bit 21 SAI4AMEN: SAI4 Autonomous mode enable Set and reset by software. 0: SAI4 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: SAI4 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 20 Reserved, must be kept at reset value. 400/3178 DocID029587 Rev 3 rw RM0433 Bit 19 Bits 18:17 Reset and Clock Control (RCC) CRCAMEN: CRC Autonomous mode enable Set and reset by software. 0: CRC peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: CRC peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Reserved, must be kept at reset value. Bit 16 RTCAMEN: RTC Autonomous mode enable Set and reset by software. 0: RTC peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: RTC peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 15 VREFAMEN: VREF Autonomous mode enable Set and reset by software. 0: VREF peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: VREF peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 14 COMP12AMEN: COMP12 Autonomous mode enable Set and reset by software. 0: COMP12 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: COMP12 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 13 Reserved, must be kept at reset value. Bit 12 LPTIM5AMEN: LPTIM5 Autonomous mode enable Set and reset by software. 0: LPTIM5 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: LPTIM5 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 11 LPTIM4AMEN: LPTIM4 Autonomous mode enable Set and reset by software. 0: LPTIM4 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: LPTIM4 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 10 LPTIM3AMEN: LPTIM3 Autonomous mode enable Set and reset by software. 0: LPTIM3 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: LPTIM3 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 9 LPTIM2AMEN: LPTIM2 Autonomous mode enable Set and reset by software. 0: LPTIM2 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: LPTIM2 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 8 Reserved, must be kept at reset value. Bit 7 I2C4AMEN: I2C4 Autonomous mode enable Set and reset by software. 0: I2C4 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: I2C4 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information DocID029587 Rev 3 401/3178 457 Reset and Clock Control (RCC) RM0433 Bit 6 Reserved, must be kept at reset value. Bit 5 SPI6AMEN: SPI6 Autonomous mode enable Set and reset by software. 0: SPI6 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: SPI6 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bit 4 Reserved, must be kept at reset value. Bit 3 LPUART1AMEN: LPUART1 Autonomous mode enable Set and reset by software. 0: LPUART1 peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: LPUART1 peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information Bits 2:1 Bit 0 402/3178 Reserved, must be kept at reset value. BDMAAMEN: BDMA and DMAMUX Autonomous mode enable Set and reset by software. 0: BDMA and DMAMUX peripheral clocks are disabled when the CPU is in CStop (default after reset) 1: BDMA and DMAMUX peripheral clocks enabled when D3 domain is in DRun. Refer to Section 8.5.11: Peripheral clock gating control for additional information DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.37 RCC Reset Status Register (RCC_RSR) This register can be accessed via two different offset address. Table 56. RCC_RSR address offset and reset value Register Name Address Offset RCC_RSR 0x0D0 RCC_C1_RSR 0x130 Reset Value 0x00FE 0000 (1) 1. Reset by power-on reset only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. LPWRRSTF Res. WWDG1RSTF Res. IWDG1RSTF Res. SFTRSTF PORRSTF PINRSTF BORRSTF D2RSTF D1RSTF Res. CPURSTF RMVF Access: 0 ≤ wait state ≤ 7, word, half-word and byte access. Wait states are inserted in case of successive accesses to this register. r r r r r r r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r r Bit 31 Reserved, must be kept at reset value. Bit 30 LPWRRSTF: Reset due to illegal D1 DStandby or CPU CStop flag (1) Reset by software by writing the RMVF bit. Set by hardware when D1 domain goes erroneously in DStandby or when CPU goes erroneously in CStop. 0: No illegal reset occurred (default after power-on reset) 1: Illegal D1 DStandby or CPU CStop reset occurred Bit 29 Reserved, must be kept at reset value. Bit 28 WWDG1RSTF: Window Watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. 0: No window watchdog reset occurred from WWDG1 (default after power-on reset) 1: window watchdog reset occurred from WWDG1 Bit 27 Reserved, must be kept at reset value. Bit 26 IWDG1RSTF: Independent Watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. 0: No independent watchdog reset occurred (default after power-on reset) 1: Independent watchdog reset occurred Bit 25 Reserved, must be kept at reset value. DocID029587 Rev 3 403/3178 457 Reset and Clock Control (RCC) RM0433 Bit 24 SFTRSTF: System reset from CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the CM7. 0: No CPU software reset occurred (default after power-on reset) 1: A system reset has been generated by the CPU Bit 23 PORRSTF: POR/PDR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred (default after power-on reset) Bit 22 PINRSTF: Pin reset flag (NRST) (1) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. 0: No reset from pin occurred 1: Reset from pin occurred (default after power-on reset) Bit 21 BORRSTF: BOR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). 0: No BOR reset occurred 1: BOR reset occurred (default after power-on reset) Bit 20 D2RSTF: D2 domain power switch reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a D2 domain exits from DStandby or after of power-on reset. Refer to Table 47 for details. 0: No D2 domain power switch reset occurred 1: A D2 domain power switch (ePOD2) reset occurred (default after power-on reset) Bit 19 D1RSTF: D1 domain power switch reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a D1 domain exits from DStandby or after of power-on reset. Refer to Table 47 for details. 0: No D1 domain power switch reset occurred 1: A D1 domain power switch (ePOD1) reset occurred (default after power-on reset) Bit 18 Reserved, must be kept at reset value. Bit 17 CPURSTF: CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware every time a CPU reset occurs. 0: No CPU reset occurred 1: A CPU reset occurred (default after power-on reset) Bit 16 RMVF: Remove reset flag Set and reset by software to reset the value of the reset flags. 0: Reset of the reset flags not activated (default after power-on reset) 1: Reset the value of the reset flags Bits 15:0 Reserved, must be kept at reset value. 1. Refer to Table 47: Reset source identification (RCC_RSR) for details on flag behavior. 404/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.38 RCC AHB3 Clock Register (RCC_AHB3ENR) This register can be accessed via two different offset address. Table 57. RCC_AHB3ENR address offset and reset value Register Name Address Offset RCC_AHB3ENR 0x0D4 RCC_C1_AHB3ENR 0x134 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC1EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. QSPIEN Res. FMCEN Res. Res. Res. Res. Res. Res. JPGDECEN DMA2DEN Res. Res. Res. MDMAEN 0x0000 0000 rw rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 SDMMC1EN: SDMMC1 and SDMMC1 Delay Clock Enable Set and reset by software. 0: SDMMC1 and SDMMC1 Delay clock disabled (default after reset) 1: SDMMC1 and SDMMC1 Delay clock enabled Bit 15 Reserved, must be kept at reset value. Bit 14 QSPIEN: QUADSPI and QUADSPI Delay Clock Enable Set and reset by software. 0: QUADSPI and QUADSPI Delay clock disabled (default after reset) 1: QUADSPI and QUADSPI Delay clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 FMCEN: FMC Peripheral Clocks Enable Set and reset by software. 0: FMC peripheral clocks disabled (default after reset) 1: FMC peripheral clocks enabled The peripheral clocks of the FMC are: the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock. Bits 11:6 Reserved, must be kept at reset value. Bit 5 JPGDECEN: JPGDEC Peripheral Clock Enable Set and reset by software. 0: JPGDEC peripheral clock disabled (default after reset) 1: JPGDEC peripheral clock enabled DocID029587 Rev 3 405/3178 457 Reset and Clock Control (RCC) RM0433 Bit 4 DMA2DEN: DMA2D Peripheral Clock Enable Set and reset by software. 0: DMA2D peripheral clock disabled (default after reset) 1: DMA2D peripheral clock enabled Bits 3:1 Reserved, must be kept at reset value. Bit 0 MDMAEN: MDMA Peripheral Clock Enable Set and reset by software. 0: MDMA peripheral clock disabled (default after reset) 1: MDMA peripheral clock enabled 406/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.39 RCC AHB1 Clock Register (RCC_AHB1ENR) This register can be accessed via two different offset address. Table 58. RCC_AHB1ENR address offset and reset value Register Name Address Offset RCC_AHB1ENR 0x0D8 RCC_C1_AHB1ENR 0x138 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. USB2ULPIEN USB2OTGEN USB1ULPIEN USB1OTGEN Res. Res. Res. Res. Res. Res. Res. ETH1RXEN ETH1TXEN rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETH1MACEN Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12EN Res. Res. Res. DMA2EN DMA1EN 0x0000 0000 rw rw rw rw Bits 31:29 Reserved, must be kept at reset value. Bit 28 USB2ULPIEN: USB_PHY2 Clocks Enable Set and reset by software. 0: USB_PHY2 clocks disabled (default after reset) 1: USB_PHY2 clocks enabled Bit 27 USB2OTGEN: USB2OTG Peripheral Clocks Enable Set and reset by software. 0: USB2OTG peripheral clocks disabled (default after reset) 1: USB2OTG peripheral clocks enabled The peripheral clocks of the USB2OTG are: the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock. Bit 26 USB1ULPIEN: USB_PHY1 Clocks Enable Set and reset by software. 0: USB1ULPI PHY clocks disabled (default after reset) 1: USB1ULPI PHY clocks enabled Bit 25 USB1OTGEN: USB1OTG Peripheral Clocks Enable Set and reset by software. 0: USB1OTG peripheral clocks disabled (default after reset) 1: USB1OTG peripheral clocks enabled The peripheral clocks of the USB1OTG are: the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock. Bits 24:18 Reserved, must be kept at reset value. DocID029587 Rev 3 407/3178 457 Reset and Clock Control (RCC) RM0433 Bit 17 ETH1RXEN: Ethernet Reception Clock Enable Set and reset by software. 0: Ethernet Reception clock disabled (default after reset) 1: Ethernet Reception clock enabled Bit 16 ETH1TXEN: Ethernet Transmission Clock Enable Set and reset by software. 0: Ethernet Transmission clock disabled (default after reset) 1: Ethernet Transmission clock enabled Bit 15 ETH1MACEN: Ethernet MAC bus interface Clock Enable Set and reset by software. 0: Ethernet MAC bus interface clock disabled (default after reset) 1: Ethernet MAC bus interface clock enabled Bits 14:6 Reserved, must be kept at reset value. Bit 5 ADC12EN: ADC1/2 Peripheral Clocks Enable Set and reset by software. 0: ADC1 and 2 peripheral clocks disabled (default after reset) 1: ADC1 and 2 peripheral clocks enabled The peripheral clocks of the ADC1 and 2 are: the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock. Bits 4:2 Reserved, must be kept at reset value. Bit 1 DMA2EN: DMA2 Clock Enable Set and reset by software. 0: DMA2 clock disabled (default after reset) 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 Clock Enable Set and reset by software. 0: DMA1 clock disabled (default after reset) 1: DMA1 clock enabled 408/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.40 RCC AHB2 Clock Register (RCC_AHB2ENR) This register can be accessed via two different offset address. Table 59. RCC_AHB2ENR address offset and reset value Register Name Address Offset RCC_AHB2ENR 0x0DC RCC_C1_AHB2ENR 0x13C Reset Value 26 25 24 23 22 21 20 19 18 17 16 SRAM2EN SRAM1EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCMIEN 27 CRYPTEN 28 HASHEN 29 RNGEN 30 SDMMC2EN 31 SRAM3EN 0x0000 0000 rw rw rw rw rw Bit 31 SRAM3EN: SRAM3 block enable Set and reset by software. When set, this bit indicates that the SRAM3 is allocated by the CPU. It causes the D2 domain to take into account also the CPU operation modes, i.e. keeping D2 domain in DRun when the CPU is in CRun. 0: SRAM3 interface clock is disabled. (default after reset) 1: SRAM3 interface clock is enabled. Bit 30 SRAM2EN: SRAM2 block enable Set and reset by software. When set, this bit indicates that the SRAM2 is allocated by the CPU. It causes the D2 domain to take into account also the CPU operation modes, i.e. keeping D2 domain in DRun when the CPU is in CRun. 0: SRAM2 interface clock is disabled. (default after reset) 1: SRAM2 interface clock is enabled. Bit 29 SRAM1EN: SRAM1 block enable Set and reset by software. When set, this bit indicates that the SRAM1 is allocated by the CPU. It causes the D2 domain to take into account also the CPU operation modes, i.e. keeping D2 domain in DRun when the CPU is in CRun. 0: SRAM1 interface clock is disabled. (default after reset) 1: SRAM1 interface clock is enabled. Bits 28:10 Reserved, must be kept at reset value. Bit 9 SDMMC2EN: SDMMC2 and SDMMC2 delay clock enable Set and reset by software. 0: SDMMC2 and SDMMC2 Delay clock disabled (default after reset) 1: SDMMC2 and SDMMC2 Delay clock enabled Bits 8:7 Reserved, must be kept at reset value. DocID029587 Rev 3 409/3178 457 Reset and Clock Control (RCC) RM0433 Bit 6 RNGEN: RNG peripheral clocks enable Set and reset by software. 0: RNG peripheral clocks disabled (default after reset) 1: RNG peripheral clocks enabled: The peripheral clocks of the RNG are: the kernel clock selected by RNGSEL and provided to rng_ker_ck input, and the rcc_hclk2 bus interface clock. Bit 5 HASHEN: HASH peripheral clock enable Set and reset by software. 0: HASH peripheral clock disabled (default after reset) 1: HASH peripheral clock enabled Bit 4 CRYPTEN: CRYPT peripheral clock enable Set and reset by software. 0: CRYPT peripheral clock disabled (default after reset) 1: CRYPT peripheral clock enabled Bits 3:1 Reserved, must be kept at reset value. Bit 0 DCMIEN: DCMI peripheral clock enable Set and reset by software. 0: DCMI peripheral clock disabled (default after reset) 1: DCMI peripheral clock enabled 410/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.41 RCC AHB4 Clock Register (RCC_AHB4ENR) This register can be accessed via two different offset address. Table 60. RCC_AHB4ENR address offset and reset value Register Name Address Offset RCC_AHB4ENR 0x0E0 RCC_C1_AHB4ENR 0x140 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. BKPRAMEN Res. Res. HSEMEN ADC3EN Res. Res. BDMAEN Res. CRCEN Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. GPIOKEN GPIOJEN GPIOIEN GPIOHEN GPIOGEN GPIOFEN GPIOEEN GPIODEN GPIOCEN GPIOBEN GPIOAEN 0x0000 0000 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:29 Reserved, must be kept at reset value. Bit 28 BKPRAMEN: Backup RAM Clock Enable Set and reset by software. 0: Backup RAM clock disabled (default after reset) 1: Backup RAM clock enabled Bits 27:26 Reserved, must be kept at reset value. Bit 25 HSEMEN: HSEM peripheral clock enable Set and reset by software. 0: HSEM peripheral clock disabled (default after reset) 1: HSEM peripheral clock enabled Bit 24 ADC3EN: ADC3 Peripheral Clocks Enable Set and reset by software. 0: ADC3 peripheral clocks disabled (default after reset) 1: ADC3 peripheral clocks enabled The peripheral clocks of the ADC3 are: the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk4 bus interface clock. Bits 23:22 Reserved, must be kept at reset value. Bit 21 BDMAEN: BDMA and DMAMUX2 Clock Enable Set and reset by software. 0: BDMA and DMAMUX2 clock disabled (default after reset) 1: BDMA and DMAMUX2 clock enabled Bit 20 Reserved, must be kept at reset value. DocID029587 Rev 3 411/3178 457 Reset and Clock Control (RCC) RM0433 Bit 19 CRCEN: CRC peripheral clock enable Set and reset by software. 0: CRC peripheral clock disabled (default after reset) 1: CRC peripheral clock enabled Bits 18:11 Reserved, must be kept at reset value. Bit 10 GPIOKEN: GPIOK peripheral clock enable Set and reset by software. 0: GPIOK peripheral clock disabled (default after reset) 1: GPIOK peripheral clock enabled Bit 9 GPIOJEN: GPIOJ peripheral clock enable Set and reset by software. 0: GPIOJ peripheral clock disabled (default after reset) 1: GPIOJ peripheral clock enabled Bit 8 GPIOIEN: GPIOI peripheral clock enable Set and reset by software. 0: GPIOI peripheral clock disabled (default after reset) 1: GPIOI peripheral clock enabled Bit 7 GPIOHEN: GPIOH peripheral clock enable Set and reset by software. 0: GPIOH peripheral clock disabled (default after reset) 1: GPIOH peripheral clock enabled Bit 6 GPIOGEN: GPIOG peripheral clock enable Set and reset by software. 0: GPIOG peripheral clock disabled (default after reset) 1: GPIOG peripheral clock enabled Bit 5 GPIOFEN: GPIOF peripheral clock enable Set and reset by software. 0: GPIOF peripheral clock disabled (default after reset) 1: GPIOF peripheral clock enabled Bit 4 GPIOEEN: GPIOE peripheral clock enable Set and reset by software. 0: GPIOE peripheral clock disabled (default after reset) 1: GPIOE peripheral clock enabled Bit 3 GPIODEN: GPIOD peripheral clock enable Set and reset by software. 0: GPIOD peripheral clock disabled (default after reset) 1: GPIOD peripheral clock enabled 412/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 2 GPIOCEN: GPIOC peripheral clock enable Set and reset by software. 0: GPIOC peripheral clock disabled (default after reset) 1: GPIOC peripheral clock enabled Bit 1 GPIOBEN: GPIOB peripheral clock enable Set and reset by software. 0: GPIOB peripheral clock disabled (default after reset) 1: GPIOB peripheral clock enabled Bit 0 GPIOAEN: GPIOA peripheral clock enable Set and reset by software. 0: GPIOA peripheral clock disabled (default after reset) 1: GPIOA peripheral clock enabled DocID029587 Rev 3 413/3178 457 Reset and Clock Control (RCC) 8.7.42 RM0433 RCC APB3 Clock Register (RCC_APB3ENR) This register can be accessed via two different offset address. Table 61. RCC_APB3ENR address offset and reset value Register Name Address Offset RCC_APB3ENR 0x0E4 RCC_C1_APB3ENR 0x144 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG1EN Res. Res. LTDCEN 0x0000 0000 Res. Res. Res. rs rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 WWDG1EN: WWDG1 Clock Enable Set by software, and reset by hardware when a system reset occurs. Note that in order to work properly, before enabling the WWDG1, the bit WW1RSC must be set to ‘1’. 0: WWDG1 peripheral clock disable (default after reset) 1: WWDG1 peripheral clock enabled Bits 5:4 Reserved, must be kept at reset value. Bit 3 LTDCEN: LTDC peripheral clock enable Provides the pixel clock (ltdc_ker_ck) to the LTDC block. Set and reset by software. 0: LTDC peripheral clock disabled (default after reset) 1: LTDC peripheral clock provided to the LTDC block Bits 2:0 Reserved, must be kept at reset value. 414/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.43 RCC APB1 Clock Register (RCC_APB1LENR) This register can be accessed via two different offset address. Table 62. RCC_APB1ENR address offset and reset value Register Name Address Offset RCC_APB1LENR 0x0E8 RCC_C1_APB1LENR 0x148 Reset Value SPDIFRXEN Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. TIM2EN HDMICECEN Res. USART2EN DAC12EN Res. TIM3EN UART7EN Res. USART3EN 16 TIM4EN 17 UART4EN 18 TIM5EN 19 UART5EN 20 TIM6EN 21 I2C1EN 22 TIM7EN 23 I2C2EN 24 TIM12EN 25 I2C3EN 26 TIM13EN 27 TIM14EN 28 LPTIM1EN 29 SPI2EN 30 SPI3EN 31 UART8EN 0x0000 0000 rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 UART8EN: UART8 Peripheral Clocks Enable Set and reset by software. 0: UART8 peripheral clocks disable (default after reset) 1: UART8 peripheral clocks enabled The peripheral clocks of the UART8 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 30 UART7EN: UART7 Peripheral Clocks Enable Set and reset by software. 0: UART7 peripheral clocks disable (default after reset) 1: UART7 peripheral clocks enabled The peripheral clocks of the UART7 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 29 DAC12EN: DAC1 and 2 peripheral clock enable Set and reset by software. 0: DAC1 and 2 peripheral clock disable (default after reset) 1: DAC1 and 2 peripheral clock enabled Bit 28 Reserved, must be kept at reset value. Bit 27 HDMICECEN: HDMI-CEC peripheral clock enable Set and reset by software. 0: HDMI-CEC peripheral clock disable (default after reset) 1: HDMI-CEC peripheral clock enabled The peripheral clocks of the HDMI-CEC are: the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock. Bits 26:24 Reserved, must be kept at reset value. DocID029587 Rev 3 415/3178 457 Reset and Clock Control (RCC) RM0433 Bit 23 I2C3EN: I2C3 Peripheral Clocks Enable Set and reset by software. 0: I2C3 peripheral clocks disable (default after reset) 1: I2C3 peripheral clocks enabled The peripheral clocks of the I2C3 are: the kernel clock selected by I2C123SEL and provided to i2c_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 22 I2C2EN: I2C2 Peripheral Clocks Enable Set and reset by software. 0: I2C2 peripheral clocks disable (default after reset) 1: I2C2 peripheral clocks enabled The peripheral clocks of the I2C2 are: the kernel clock selected by I2C123SEL and provided to i2c_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 21 I2C1EN: I2C1 Peripheral Clocks Enable Set and reset by software. 0: I2C1 peripheral clocks disable (default after reset) 1: I2C1 peripheral clocks enabled The peripheral clocks of the I2C1 are: the kernel clock selected by I2C123SEL and provided to i2c_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 20 UART5EN: UART5 Peripheral Clocks Enable Set and reset by software. 0: UART5 peripheral clocks disable (default after reset) 1: UART5 peripheral clocks enabled The peripheral clocks of the UART5 are: the kernel clock selected by USART234578SEL and provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 19 UART4EN: UART4 Peripheral Clocks Enable Set and reset by software. 0: UART4 peripheral clocks disable (default after reset) 1: UART4 peripheral clocks enabled The peripheral clocks of the UART4 are: the kernel clock selected by USART234578SEL and provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 18 USART3EN: USART3 Peripheral Clocks Enable Set and reset by software. 0: USART3 peripheral clocks disable (default after reset) 1: USART3 peripheral clocks enabled The peripheral clocks of the USART3 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 17 USART2EN: USART2 Peripheral Clocks Enable Set and reset by software. 0: USART2 peripheral clocks disable (default after reset) 1: USART2 peripheral clocks enabled The peripheral clocks of the USART2 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 16 SPDIFRXEN: SPDIFRX Peripheral Clocks Enable Set and reset by software. 0: SPDIFRX peripheral clocks disable (default after reset) 1: SPDIFRX peripheral clocks enabled The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock. 416/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 15 SPI3EN: SPI3 Peripheral Clocks Enable Set and reset by software. 0: SPI3 peripheral clocks disable (default after reset) 1: SPI3 peripheral clocks enabled The peripheral clocks of the SPI3 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 14 SPI2EN: SPI2 Peripheral Clocks Enable Set and reset by software. 0: SPI2 peripheral clocks disable (default after reset) 1: SPI2 peripheral clocks enabled The peripheral clocks of the SPI2 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock. Bits 13:10 Reserved, must be kept at reset value. Bit 9 LPTIM1EN: LPTIM1 Peripheral Clocks Enable Set and reset by software. 0: LPTIM1 peripheral clocks disable (default after reset) 1: LPTIM1 peripheral clocks enabled The peripheral clocks of the LPTIM1 are: the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 8 TIM14EN: TIM14 peripheral clock enable Set and reset by software. 0: TIM14 peripheral clock disable (default after reset) 1: TIM14 peripheral clock enabled Bit 7 TIM13EN: TIM13 peripheral clock enable Set and reset by software. 0: TIM13 peripheral clock disable (default after reset) 1: TIM13 peripheral clock enabled Bit 6 TIM12EN: TIM12 peripheral clock enable Set and reset by software. 0: TIM12 peripheral clock disable (default after reset) 1: TIM12 peripheral clock enabled Bit 5 TIM7EN: TIM7 peripheral clock enable Set and reset by software. 0: TIM7 peripheral clock disable (default after reset) 1: TIM7 peripheral clock enabled Bit 4 TIM6EN: TIM6 peripheral clock enable Set and reset by software. 0: TIM6 peripheral clock disable (default after reset) 1: TIM6 peripheral clock enabled Bit 3 TIM5EN: TIM5 peripheral clock enable Set and reset by software. 0: TIM5 peripheral clock disable (default after reset) 1: TIM5 peripheral clock enabled DocID029587 Rev 3 417/3178 457 Reset and Clock Control (RCC) RM0433 Bit 2 TIM4EN: TIM4 peripheral clock enable Set and reset by software. 0: TIM4 peripheral clock disable (default after reset) 1: TIM4 peripheral clock enabled Bit 1 TIM3EN: TIM3 peripheral clock enable Set and reset by software. 0: TIM3 peripheral clock disable (default after reset) 1: TIM3 peripheral clock enabled Bit 0 TIM2EN: TIM2 peripheral clock enable Set and reset by software. 0: TIM2 peripheral clock disable (default after reset) 1: TIM2 peripheral clock enabled 418/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.44 RCC APB1 Clock Register (RCC_APB1HENR) This register can be accessed via two different offset address. Table 63. RCC_APB1ENR address offset and reset value Register Name Address Offset RCC_APB1HENR 0x0EC RCC_C1_APB1HENR 0x14C Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. FDCANEN Res. Res. MDIOSEN OPAMPEN Res. SWPEN CRSEN 0x0000 0000 Res. rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 FDCANEN: FDCAN Peripheral Clocks Enable Set and reset by software. 0: FDCAN peripheral clocks disable (default after reset) 1: FDCAN peripheral clocks enabled: The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to fdcan_ker_ck input, and the rcc_pclk1 bus interface clock. Bits 7:6 Reserved, must be kept at reset value. Bit 5 MDIOSEN: MDIOS peripheral clock enable Set and reset by software. 0: MDIOS peripheral clock disable (default after reset) 1: MDIOS peripheral clock enabled Bit 4 OPAMPEN: OPAMP peripheral clock enable Set and reset by software. 0: OPAMP peripheral clock disable (default after reset) 1: OPAMP peripheral clock enabled Bit 3 Reserved, must be kept at reset value. DocID029587 Rev 3 419/3178 457 Reset and Clock Control (RCC) RM0433 Bit 2 SWPEN: SWPMI Peripheral Clocks Enable Set and reset by software. 0: SWPMI peripheral clocks disable (default after reset) 1: SWPMI peripheral clocks enabled: The peripheral clocks of the SWPMI are: the kernel clock selected by SWPSEL and provided to swpmi_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 1 CRSEN: Clock Recovery System peripheral clock enable Set and reset by software. 0: CRS peripheral clock disable (default after reset) 1: CRS peripheral clock enabled Bit 0 Reserved, must be kept at reset value. 420/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.45 RCC APB2 Clock Register (RCC_APB2ENR) This register can be accessed via two different offset address. Table 64. RCC_APB2ENR address offset and reset value Register Name Address Offset RCC_APB2ENR 0x0F0 RCC_C1_APB2ENR 0x150 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. HRTIMEN DFSDM1EN Res. Res. Res. SAI3EN SAI2EN SAI1EN Res. SPI5EN Res. TIM17EN TIM16EN TIM15EN rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. SPI4EN SPI1EN Res. Res. Res. Res. Res. Res. USART6EN USART1EN Res. Res. TIM8EN TIM1EN 0x0000 0000 rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 HRTIMEN: HRTIM peripheral clock enable Set and reset by software. 0: HRTIM peripheral clock disabled (default after reset) 1: HRTIM peripheral clock enabled Bit 28 DFSDM1EN: DFSDM1 Peripheral Clocks Enable Set and reset by software. 0: DFSDM1 peripheral clocks disabled (default after reset) 1: DFSDM1 peripheral clocks enabled DFSDM1 peripheral clocks are: the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock. Bits 27:25 Reserved, must be kept at reset value. Bit 24 SAI3EN: SAI3 Peripheral Clocks Enable Set and reset by software. 0: SAI3 peripheral clocks disabled (default after reset) 1: SAI3 peripheral clocks enabled The peripheral clocks of the SAI3 are: the kernel clock selected by SAI23SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. Bit 23 SAI2EN: SAI2 Peripheral Clocks Enable Set and reset by software. 0: SAI2 peripheral clocks disabled (default after reset) 1: SAI2 peripheral clocks enabled The peripheral clocks of the SAI2 are: the kernel clock selected by SAI23SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. DocID029587 Rev 3 421/3178 457 Reset and Clock Control (RCC) RM0433 Bit 22 SAI1EN: SAI1 Peripheral Clocks Enable Set and reset by software. 0: SAI1 peripheral clocks disabled (default after reset) 1: SAI1 peripheral clocks enabled: The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. Bit 21 Reserved, must be kept at reset value. Bit 20 SPI5EN: SPI5 Peripheral Clocks Enable Set and reset by software. 0: SPI5 peripheral clocks disabled (default after reset) 1: SPI5 peripheral clocks enabled: The peripheral clocks of the SPI5 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. Bit 19 Reserved, must be kept at reset value. Bit 18 TIM17EN: TIM17 peripheral clock enable Set and reset by software. 0: TIM17 peripheral clock disabled (default after reset) 1: TIM17 peripheral clock enabled Bit 17 TIM16EN: TIM16 peripheral clock enable Set and reset by software. 0: TIM16 peripheral clock disabled (default after reset) 1: TIM16 peripheral clock enabled Bit 16 TIM15EN: TIM15 peripheral clock enable Set and reset by software. 0: TIM15 peripheral clock disabled (default after reset) 1: TIM15 peripheral clock enabled Bits 15:14 Reserved, must be kept at reset value. Bit 13 SPI4EN: SPI4 Peripheral Clocks Enable Set and reset by software. 0: SPI4 peripheral clocks disabled (default after reset) 1: SPI4 peripheral clocks enabled: The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. Bit 12 SPI1EN: SPI1 Peripheral Clocks Enable Set and reset by software. 0: SPI1 peripheral clocks disabled (default after reset) 1: SPI1 peripheral clocks enabled: The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. Bits 11:6 Reserved, must be kept at reset value. Bit 5 USART6EN: USART6 Peripheral Clocks Enable Set and reset by software. 0: USART6 peripheral clocks disabled (default after reset) 1: USART6 peripheral clocks enabled: The peripheral clocks of the USART6 are: the kernel clock selected by USART16SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock. 422/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 4 USART1EN: USART1 Peripheral Clocks Enable Set and reset by software. 0: USART1 peripheral clocks disabled (default after reset) 1: USART1 peripheral clocks enabled: The peripheral clocks of the USART1 are: the kernel clock selected by USART16SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock. Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8EN: TIM8 peripheral clock enable Set and reset by software. 0: TIM8 peripheral clock disabled (default after reset) 1: TIM8 peripheral clock enabled Bit 0 TIM1EN: TIM1 peripheral clock enable Set and reset by software. 0: TIM1 peripheral clock disabled (default after reset) 1: TIM1 peripheral clock enabled DocID029587 Rev 3 423/3178 457 Reset and Clock Control (RCC) 8.7.46 RM0433 RCC APB4 Clock Register (RCC_APB4ENR) This register can be accessed via two different offset address. Table 65. RCC_APB4ENR address offset and reset value Register Name Address Offset RCC_APB4ENR 0x0F4 RCC_C1_APB4ENR 0x154 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4EN Res. Res. Res. Res. RTCAPBEN 0x0001 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP12EN Res. LPTIM5EN LPTIM4EN LPTIM3EN LPTIM2EN Res. I2C4EN Res. SPI6EN Res. LPUART1EN Res. SYSCFGEN rw VREFEN rw Res. rw rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:22 Reserved, must be kept at reset value. Bit 21 SAI4EN: SAI4 Peripheral Clocks Enable Set and reset by software. 0: SAI4 peripheral clocks disabled (default after reset) 1: SAI4 peripheral clocks enabled The peripheral clocks of the SAI4 are: the kernel clocks selected by SAI4ASEL and SAI4BSEL, and provided to sai_a_ker_ck and sai_b_ker_ck inputs respectively, and the rcc_pclk4 bus interface clock. Bits 20:17 Reserved, must be kept at reset value. Bit 16 RTCAPBEN: RTC APB Clock Enable Set and reset by software. 0: The register clock interface of the RTC (APB) is disabled 1: The register clock interface of the RTC (APB) is enabled (default after reset) Bit 15 VREFEN: VREF peripheral clock enable Set and reset by software. 0: VREF peripheral clock disabled (default after reset) 1: VREF peripheral clock enabled Bit 14 COMP12EN: COMP1/2 peripheral clock enable Set and reset by software. 0: COMP1/2 peripheral clock disabled (default after reset) 1: COMP1/2 peripheral clock enabled Bit 13 Reserved, must be kept at reset value. 424/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 12 LPTIM5EN: LPTIM5 Peripheral Clocks Enable Set and reset by software. 0: LPTIM5 peripheral clocks disabled (default after reset) 1: LPTIM5 peripheral clocks enabled The peripheral clocks of the LPTIM5 are: the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 11 LPTIM4EN: LPTIM4 Peripheral Clocks Enable Set and reset by software. 0: LPTIM4 peripheral clocks disabled (default after reset) 1: LPTIM4 peripheral clocks enabled The peripheral clocks of the LPTIM4 are: the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 10 LPTIM3EN: LPTIM3 Peripheral Clocks Enable Set and reset by software. 0: LPTIM3 peripheral clocks disabled (default after reset) 1: LPTIM3 peripheral clocks enabled The peripheral clocks of the LPTIM3 are: the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 9 LPTIM2EN: LPTIM2 Peripheral Clocks Enable Set and reset by software. 0: LPTIM2 peripheral clocks disabled (default after reset) 1: LPTIM2 peripheral clocks enabled The peripheral clocks of the LPTIM2 are: the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 8 Reserved, must be kept at reset value. Bit 7 I2C4EN: I2C4 Peripheral Clocks Enable Set and reset by software. 0: I2C4 peripheral clocks disabled (default after reset) 1: I2C4 peripheral clocks enabled The peripheral clocks of the I2C4 are: the kernel clock selected by I2C4SEL and provided to i2c_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 6 Reserved, must be kept at reset value. Bit 5 SPI6EN: SPI6 Peripheral Clocks Enable Set and reset by software. 0: SPI6 peripheral clocks disabled (default after reset) 1: SPI6 peripheral clocks enabled The peripheral clocks of the SPI6 are: the kernel clock selected by SPI6SEL and provided to spi_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 4 Reserved, must be kept at reset value. Bit 3 LPUART1EN: LPUART1 Peripheral Clocks Enable Set and reset by software. 0: LPUART1 peripheral clocks disabled (default after reset) 1: LPUART1 peripheral clocks enabled The peripheral clocks of the LPUART1 are: the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock. DocID029587 Rev 3 425/3178 457 Reset and Clock Control (RCC) RM0433 Bit 2 Reserved, must be kept at reset value. Bit 1 SYSCFGEN: SYSCFG peripheral clock enable Set and reset by software. 0: SYSCFG peripheral clock disabled (default after reset) 1: SYSCFG peripheral clock enabled Bit 0 Reserved, must be kept at reset value. 426/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.47 RCC AHB3 Sleep Clock Register (RCC_AHB3LPENR) This register can be accessed via two different offset address. Table 66. RCC_AHB3LPENR address offset and reset value Register Name Address Offset RCC_AHB3LPENR 0x0FC RCC_C1_AHB3LPENR 0x15C Reset Value 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MDMALPEN 22 DMA2DLPEN 23 JPGDECLPEN 24 FLASHLPEN 25 DTCM1LPEN 26 FMCLPEN 27 DTCM2LPEN 28 ITCMLPEN 29 QSPILPEN 30 AXISRAMLPEN 31 SDMMC1LPEN 0xF001 5131 rw rw rw rw rw rw rw Bit 31 AXISRAMLPEN: AXISRAM Block Clock Enable During CSleep mode Set and reset by software. 0: AXISRAM interface clock disabled during CSleep mode 1: AXISRAM interface clock enabled during CSleep mode (default after reset) Bit 30 ITCMLPEN: D1ITCM Block Clock Enable During CSleep mode Set and reset by software. 0: D1 ITCM interface clock disabled during CSleep mode 1: D1 ITCM interface clock enabled during CSleep mode (default after reset) Bit 29 DTCM2LPEN: D1 DTCM2 Block Clock Enable During CSleep mode Set and reset by software. 0: D1 DTCM2 interface clock disabled during CSleep mode 1: D1 DTCM2 interface clock enabled during CSleep mode (default after reset) Bit 28 D1DTCM1LPEN: D1DTCM1 Block Clock Enable During CSleep mode Set and reset by software. 0: D1DTCM1 interface clock disabled during CSleep mode 1: D1DTCM1 interface clock enabled during CSleep mode (default after reset) Bits 27:17 Reserved, must be kept at reset value. Bit 16 SDMMC1LPEN: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode Set and reset by software. 0: SDMMC1 and SDMMC1 Delay clock disabled during CSleep mode 1: SDMMC1 and SDMMC1 Delay clock enabled during CSleep mode (default after reset) Bit 15 Reserved, must be kept at reset value. DocID029587 Rev 3 427/3178 457 Reset and Clock Control (RCC) RM0433 Bit 14 QSPILPEN: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode Set and reset by software. 0: QUADSPI and QUADSPI Delay clock disabled during CSleep mode 1: QUADSPI and QUADSPI Delay clock enabled during CSleep mode (default after reset) Bit 13 Reserved, must be kept at reset value. Bit 12 FMCLPEN: FMC Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: FMC peripheral clocks disabled during CSleep mode 1: FMC peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the FMC are: the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock. Bits 11:9 Reserved, must be kept at reset value. Bit 8 FLASHLPEN: Flash interface Clock Enable During CSleep Mode Set and reset by software. 0: Flash interface clock disabled during CSleep mode 1: Flash interface clock enabled during CSleep mode (default after reset) Bits 7:6 Reserved, must be kept at reset value. Bit 5 JPGDECLPEN: JPGDEC Clock Enable During CSleep Mode Set and reset by software. 0: JPGDEC peripheral clock disabled during CSleep mode 1: JPGDEC peripheral clock enabled during CSleep mode (default after reset) Bit 4 DMA2DLPEN: DMA2D Clock Enable During CSleep Mode Set and reset by software. 0: DMA2D peripheral clock disabled during CSleep mode 1: DMA2D peripheral clock enabled during CSleep mode (default after reset) Bits 3:1 Reserved, must be kept at reset value. Bit 0 MDMALPEN: MDMA Clock Enable During CSleep Mode Set and reset by software. 0: MDMA peripheral clock disabled during CSleep mode 1: MDMA peripheral clock enabled during CSleep mode (default after reset) 428/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.48 RCC AHB1 Sleep Clock Register (RCC_AHB1LPENR) This register can be accessed via two different offset address. Table 67. RCC_AHB1LPENR address offset and reset value Register Name Address Offset RCC_AHB1LPENR 0x100 RCC_C1_AHB1LPENR 0x160 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. USB2ULPILPEN USB2OTGLPEN USB1ULPILPEN USB1OTGLPEN Res. Res. Res. Res. Res. Res. Res. ETH1RXLPEN ETH1TXLPEN rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETH1MACLPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12LPEN Res. Res. Res. DMA2LPEN DMA1LPEN 0x1E03 C023 rw rw rw rw Bits 31:29 Reserved, must be kept at reset value. Bit 28 USB2ULPILPEN: USB_PHY2 clocks enable during CSleep mode Set and reset by software. 0: USB_PHY2 clocks disabled during CSleep mode 1: USB_PHY2 clocks enabled during CSleep mode (default after reset) Bit 27 USB2OTGLPEN: USB2OTG peripheral clock enable during CSleep mode Set and reset by software. 0: USB2OTG peripheral clocks disabled during CSleep mode 1: USB2OTG peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the USB2OTG are: the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock. Bit 26 USB1ULPILPEN: USB_PHY1 clock enable during CSleep mode Set and reset by software. 0: USB_PHY1 peripheral clock disabled during CSleep mode 1: USB_PHY1 peripheral clock enabled during CSleep mode (default after reset) Bit 25 USB1OTGLPEN: USB1OTG peripheral clock enable during CSleep mode Set and reset by software. 0: USB1OTG peripheral clock disabled during CSleep mode 1: USB1OTG peripheral clock enabled during CSleep mode (default after reset) The peripheral clocks of the USB1OTG are: the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock. Bits 24:18 Reserved, must be kept at reset value. DocID029587 Rev 3 429/3178 457 Reset and Clock Control (RCC) RM0433 Bit 17 ETH1RXLPEN: Ethernet Reception Clock Enable During CSleep Mode Set and reset by software. 0: Ethernet Reception clock disabled during CSleep mode 1: Ethernet Reception clock enabled during CSleep mode (default after reset) Bit 16 ETH1TXLPEN: Ethernet Transmission Clock Enable During CSleep Mode Set and reset by software. 0: Ethernet Transmission clock disabled during CSleep mode 1: Ethernet Transmission clock enabled during CSleep mode (default after reset) Bit 15 ETH1MACLPEN: Ethernet MAC bus interface Clock Enable During CSleep Mode Set and reset by software. 0: Ethernet MAC bus interface clock disabled during CSleep mode 1: Ethernet MAC bus interface clock enabled during CSleep mode (default after reset) Bits 14:6 Reserved, must be kept at reset value. Bit 5 ADC12LPEN: ADC1/2 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: ADC1/2 peripheral clocks disabled during CSleep mode 1: ADC1/2 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the ADC1 and 2 are: the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock. Bits 4:2 Reserved, must be kept at reset value. Bit 1 DMA2LPEN: DMA2 Clock Enable During CSleep Mode Set and reset by software. 0: DMA2 clock disabled during CSleep mode 1: DMA2 clock enabled during CSleep mode (default after reset) Bit 0 DMA1LPEN: DMA1 Clock Enable During CSleep Mode Set and reset by software. 0: DMA1 clock disabled during CSleep mode 1: DMA1 clock enabled during CSleep mode (default after reset) 430/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.49 RCC AHB2 Sleep Clock Register (RCC_AHB2LPENR) This register can be accessed via two different offset address. Table 68. RCC_AHB2LPENR address offset and reset value Register Name Address Offset RCC_AHB2LPENR 0x104 RCC_C1_AHB2LPENR 0x164 Reset Value 26 25 24 23 22 21 20 19 18 17 16 SRAM2LPEN SRAM1LPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CAMITFLPEN 27 CRYPTLPEN 28 HASHLPEN 29 RNGLPEN 30 SDMMC2LPEN 31 SRAM3LPEN 0xE000 0271 rw rw rw rw rw Bit 31 SRAM3LPEN: SRAM3 Clock Enable During CSleep Mode Set and reset by software. 0: SRAM3 clock disabled during CSleep mode 1: SRAM3 clock enabled during CSleep mode (default after reset) Bit 30 SRAM2LPEN: SRAM2 Clock Enable During CSleep Mode Set and reset by software. 0: SRAM2 clock disabled during CSleep mode 1: SRAM2 clock enabled during CSleep mode (default after reset) Bit 29 SRAM1LPEN: SRAM1 Clock Enable During CSleep Mode Set and reset by software. 0: SRAM1 clock disabled during CSleep mode 1: SRAM1 clock enabled during CSleep mode (default after reset) Bits 28:10 Reserved, must be kept at reset value. Bit 9 SDMMC2LPEN: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode Set and reset by software. 0: SDMMC2 and SDMMC2 Delay clock disabled during CSleep mode 1: SDMMC2 and SDMMC2 Delay clock enabled during CSleep mode (default after reset) Bits 8:7 Reserved, must be kept at reset value. Bit 6 RNGLPEN: RNG peripheral clock enable during CSleep mode Set and reset by software. 0: RNG peripheral clocks disabled during CSleep mode 1: RNG peripheral clock enabled during CSleep mode (default after reset) The peripheral clocks of the RNG are: the kernel clock selected by RNGSEL and provided to rng_ker_ck input, and the rcc_hclk2 bus interface clock. DocID029587 Rev 3 431/3178 457 Reset and Clock Control (RCC) RM0433 Bit 5 HASHLPEN: HASH peripheral clock enable during CSleep mode Set and reset by software. 0: HASH peripheral clock disabled during CSleep mode 1: HASH peripheral clock enabled during CSleep mode (default after reset) Bit 4 CRYPTLPEN: CRYPT peripheral clock enable during CSleep mode Set and reset by software. 0: CRYPT peripheral clock disabled during CSleep mode 1: CRYPT peripheral clock enabled during CSleep mode (default after reset) Bits 3:1 Reserved, must be kept at reset value. Bit 0 DCMILPEN: DCMI peripheral clock enable during CSleep mode Set and reset by software. 0: DCMI peripheral clock disabled during CSleep mode 1: DCMI peripheral clock enabled during CSleep mode (default after reset) 432/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.50 RCC AHB4 Sleep Clock Register (RCC_AHB4LPENR) This register can be accessed via two different offset address. Table 69. RCC_AHB4LPENR address offset and reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. BDMALPEN Res. CRCLPEN Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. GPIOGLPEN GPIOFLPEN GPIOELPEN GPIODLPEN GPIOCLPEN GPIOBLPEN GPIOALPEN 0x168 GPIOHLPEN RCC_C1_AHB4LPENR ADC3LPEN 0x3128 07FF GPIOILPEN 0x108 GPIOJLPEN RCC_AHB4LPENR GPIOKLPEN Reset Value BKPRAMLPEN Address Offset SRAM4LPEN Register Name rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 SRAM4LPEN: SRAM4 Clock Enable During CSleep Mode Set and reset by software. 0: SRAM4 clock disabled during CSleep mode 1: SRAM4 clock enabled during CSleep mode (default after reset) Bit 28 BKPRAMLPEN: Backup RAM Clock Enable During CSleep Mode Set and reset by software. 0: Backup RAM clock disabled during CSleep mode 1: Backup RAM clock enabled during CSleep mode (default after reset) Bits 27:25 Reserved, must be kept at reset value. Bit 24 ADC3LPEN: ADC3 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: ADC3 peripheral clocks disabled during CSleep mode 1: ADC3 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the ADC3 are: the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk4 bus interface clock. Bits 23:22 Reserved, must be kept at reset value. Bit 21 BDMALPEN: BDMA Clock Enable During CSleep Mode Set and reset by software. 0: BDMA clock disabled during CSleep mode 1: BDMA clock enabled during CSleep mode (default after reset) Bit 20 Reserved, must be kept at reset value. DocID029587 Rev 3 433/3178 457 Reset and Clock Control (RCC) RM0433 Bit 19 CRCLPEN: CRC peripheral clock enable during CSleep mode Set and reset by software. 0: CRC peripheral clock disabled during CSleep mode 1: CRC peripheral clock enabled during CSleep mode (default after reset) Bits 18:11 Reserved, must be kept at reset value. Bit 10 GPIOKLPEN: GPIOK peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOK peripheral clock disabled during CSleep mode 1: GPIOK peripheral clock enabled during CSleep mode (default after reset) Bit 9 GPIOJLPEN: GPIOJ peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOJ peripheral clock disabled during CSleep mode 1: GPIOJ peripheral clock enabled during CSleep mode (default after reset) Bit 8 GPIOILPEN: GPIOI peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOI peripheral clock disabled during CSleep mode 1: GPIOI peripheral clock enabled during CSleep mode (default after reset) Bit 7 GPIOHLPEN: GPIOH peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOH peripheral clock disabled during CSleep mode 1: GPIOH peripheral clock enabled during CSleep mode (default after reset) Bit 6 GPIOGLPEN: GPIOG peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOG peripheral clock disabled during CSleep mode 1: GPIOG peripheral clock enabled during CSleep mode (default after reset) Bit 5 GPIOFLPEN: GPIOF peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOF peripheral clock disabled during CSleep mode 1: GPIOF peripheral clock enabled during CSleep mode (default after reset) Bit 4 GPIOELPEN: GPIOE peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOE peripheral clock disabled during CSleep mode 1: GPIOE peripheral clock enabled during CSleep mode (default after reset) Bit 3 GPIODLPEN: GPIOD peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOD peripheral clock disabled during CSleep mode 1: GPIOD peripheral clock enabled during CSleep mode (default after reset) 434/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 2 GPIOCLPEN: GPIOC peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOC peripheral clock disabled during CSleep mode 1: GPIOC peripheral clock enabled during CSleep mode (default after reset) Bit 1 GPIOBLPEN: GPIOB peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOB peripheral clock disabled during CSleep mode 1: GPIOB peripheral clock enabled during CSleep mode (default after reset) Bit 0 GPIOALPEN: GPIOA peripheral clock enable during CSleep mode Set and reset by software. 0: GPIOA peripheral clock disabled during CSleep mode 1: GPIOA peripheral clock enabled during CSleep mode (default after reset) DocID029587 Rev 3 435/3178 457 Reset and Clock Control (RCC) 8.7.51 RM0433 RCC APB3 Sleep Clock Register (RCC_APB3LPENR) This register can be accessed via two different offset address. Table 70. RCC_APB3LPENR address offset and reset value Register Name Address Offset RCC_APB3LPENR 0x10C RCC_C1_APB3LPENR 0x16C Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG1LPEN Res. Res. LTDCLPEN 0x0000 0058 Res. Res. Res. rw rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 WWDG1LPEN: WWDG1 Clock Enable During CSleep Mode Set and reset by software. 0: WWDG1 clock disable during CSleep mode 1: WWDG1 clock enabled during CSleep mode (default after reset) Bits 5:4 Reserved, must be kept at reset value. Bit 3 LTDCLPEN: LTDC peripheral clock enable during CSleep mode Provides the pixel clock (ltdc_ker_ck) to the LTDC block. Set and reset by software. 0: LTDC clock disabled during CSleep mode 1: LTDC clock provided to the LTDC during CSleep mode (default after reset) Bits 2:0 Reserved, must be kept at reset value. 436/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.52 RCC APB1 Low Sleep Clock Register (RCC_APB1LLPENR) This register can be accessed via two different offset address. Table 71. RCC_APB1LLPENR address offset and reset value Register Name Address Offset RCC_APB1LLPENR 0x110 RCC_C1_APB1LLPENR 0x170 Reset Value SPDIFRXLPEN Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. TIM2LPEN CECLPEN Res. USART2LPEN DAC12LPEN Res. TIM3LPEN UART7LPEN Res. USART3LPEN 16 TIM4LPEN 17 UART4LPEN 18 TIM5LPEN 19 UART5LPEN 20 TIM6LPEN 21 I2C1LPEN 22 TIM7LPEN 23 I2C2LPEN 24 TIM12LPEN 25 I2C3LPEN 26 TIM13LPEN 27 TIM14LPEN 28 LPTIM1LPEN 29 SPI2LPEN 30 SPI3LPEN 31 UART8LPEN 0xE8FF CBFF rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 UART8LPEN: UART8 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: UART8 peripheral clocks disabled during CSleep mode 1: UART8 peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the UART8 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 30 UART7LPEN: UART7 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: UART7 peripheral clocks disabled during CSleep mode 1: UART7 peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the UART7 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 29 DAC12LPEN: DAC1/2 peripheral clock enable during CSleep mode Set and reset by software. 0: DAC1/2 peripheral clock disabled during CSleep mode 1: DAC1/2 peripheral clock enabled during CSleep mode (default after reset) Bit 28 Reserved, must be kept at reset value. Bit 27 CECLPEN: HDMI-CEC Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: HDMI-CEC peripheral clocks disabled during CSleep mode 1: HDMI-CEC peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the HDMI-CEC are: the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock. Bits 26:24 Reserved, must be kept at reset value. DocID029587 Rev 3 437/3178 457 Reset and Clock Control (RCC) RM0433 Bit 23 I2C3LPEN: I2C3 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: I2C3 peripheral clocks disabled during CSleep mode 1: I2C3 peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the I2C3 are: the kernel clock selected by I2C123SEL and provided to i2c_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 22 I2C2LPEN: I2C2 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: I2C2 peripheral clocks disabled during CSleep mode 1: I2C2 peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the I2C2 are: the kernel clock selected by I2C123SEL and provided to i2c_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 21 I2C1LPEN: I2C1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: I2C1 peripheral clocks disabled during CSleep mode 1: I2C1 peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the I2C1 are: the kernel clock selected by I2C123SEL and provided to i2c_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 20 UART5LPEN: UART5 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: UART5 peripheral clocks disabled during CSleep mode 1: UART5 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the UART5 are: the kernel clock selected by USART234578SEL and provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 19 UART4LPEN: UART4 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: UART4 peripheral clocks disabled during CSleep mode 1: UART4 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the UART4 are: the kernel clock selected by USART234578SEL and provided to uart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 18 USART3LPEN: USART3 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: USART3 peripheral clocks disabled during CSleep mode 1: USART3 peripheral clocks enabled during CSleep mode (default after reset): The peripheral clocks of the USART3 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 17 USART2LPEN: USART2 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: USART2 peripheral clocks disabled during CSleep mode 1: USART2 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the USART2 are: the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 16 SPDIFRXLPEN: SPDIFRX Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPDIFRX peripheral clocks disabled during CSleep mode 1: SPDIFRX peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock. 438/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 15 SPI3LPEN: SPI3 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPI3 peripheral clocks disabled during CSleep mode 1: SPI3 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPI3 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 14 SPI2LPEN: SPI2 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPI2 peripheral clocks disabled during CSleep mode 1: SPI2 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPI2 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock. Bits 13:10 Reserved, must be kept at reset value. Bit 9 LPTIM1LPEN: LPTIM1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: LPTIM1 peripheral clocks disabled during CSleep mode 1: LPTIM1 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the LPTIM1 are: the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 8 TIM14LPEN: TIM14 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM14 peripheral clock disabled during CSleep mode 1: TIM14 peripheral clock enabled during CSleep mode (default after reset) Bit 7 TIM13LPEN: TIM13 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM13 peripheral clock disabled during CSleep mode 1: TIM13 peripheral clock enabled during CSleep mode (default after reset) Bit 6 TIM12LPEN: TIM12 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM12 peripheral clock disabled during CSleep mode 1: TIM12 peripheral clock enabled during CSleep mode (default after reset) Bit 5 TIM7LPEN: TIM7 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM7 peripheral clock disabled during CSleep mode 1: TIM7 peripheral clock enabled during CSleep mode (default after reset) Bit 4 TIM6LPEN: TIM6 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM6 peripheral clock disabled during CSleep mode 1: TIM6 peripheral clock enabled during CSleep mode (default after reset) Bit 3 TIM5LPEN: TIM5 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM5 peripheral clock disabled during CSleep mode 1: TIM5 peripheral clock enabled during CSleep mode (default after reset) DocID029587 Rev 3 439/3178 457 Reset and Clock Control (RCC) RM0433 Bit 2 TIM4LPEN: TIM4 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM4 peripheral clock disabled during CSleep mode 1: TIM4 peripheral clock enabled during CSleep mode (default after reset) Bit 1 TIM3LPEN: TIM3 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM3 peripheral clock disabled during CSleep mode 1: TIM3 peripheral clock enabled during CSleep mode (default after reset) Bit 0 TIM2LPEN: TIM2 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM2 peripheral clock disabled during CSleep mode 1: TIM2 peripheral clock enabled during CSleep mode (default after reset) 440/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.53 RCC APB1 High Sleep Clock Register (RCC_APB1HLPENR) This register can be accessed via two different offset address. Table 72. RCC_APB1HLPENR address offset and reset value Register Name Address Offset RCC_APB1HLPENR 0x114 RCC_C1_APB1HLPENR 0x174 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. FDCANLPEN Res. Res. MDIOSLPEN OPAMPLPEN Res. SWPLPEN CRSLPEN 0x0000 0136 Res. rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 FDCANLPEN: FDCAN Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: FDCAN peripheral clocks disabled during CSleep mode 1: FDCAN peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to fdcan_ker_ck input, and the rcc_pclk1 bus interface clock. Bits 7:6 Reserved, must be kept at reset value. Bit 5 MDIOSLPEN: MDIOS peripheral clock enable during CSleep mode Set and reset by software. 0: MDIOS peripheral clock disabled during CSleep mode 1: MDIOS peripheral clock enabled during CSleep mode (default after reset) Bit 4 OPAMPLPEN: OPAMP peripheral clock enable during CSleep mode Set and reset by software. 0: OPAMP peripheral clock disabled during CSleep mode 1: OPAMP peripheral clock enabled during CSleep mode (default after reset) Bit 3 Reserved, must be kept at reset value. DocID029587 Rev 3 441/3178 457 Reset and Clock Control (RCC) RM0433 Bit 2 SWPLPEN: SWPMI Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SWPMI peripheral clocks disabled during CSleep mode 1: SWPMI peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SWPMI are: the kernel clock selected by SWPSEL and provided to swpmi_ker_ck input, and the rcc_pclk1 bus interface clock. Bit 1 CRSLPEN: Clock Recovery System peripheral clock enable during CSleep mode Set and reset by software. 0: CRS peripheral clock disabled during CSleep mode 1: CRS peripheral clock enabled during CSleep mode (default after reset) Bit 0 Reserved, must be kept at reset value. 442/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) 8.7.54 RCC APB2 Sleep Clock Register (RCC_APB2LPENR) This register can be accessed via two different offset address. Table 73. RCC_APB2LPENR address offset and reset value Register Name Address Offset RCC_APB2LPENR 0x118 RCC_C1_APB2LPENR 0x178 Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. HRTIMLPEN DFSDM1LPEN Res. Res. Res. SAI3LPEN SAI2LPEN SAI1LPEN Res. SPI5LPEN Res. TIM17LPEN TIM16LPEN TIM15LPEN rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. SPI4LPEN SPI1LPEN Res. Res. Res. Res. Res. Res. USART6LPEN USART1LPEN Res. Res. TIM8LPEN TIM1LPEN 0x31D7 3033 rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 HRTIMLPEN: HRTIM peripheral clock enable during CSleep mode Set and reset by software. 0: HRTIM peripheral clock disabled during CSleep mode 1: HRTIM peripheral clock enabled during CSleep mode (default after reset) Bit 28 DFSDM1LPEN: DFSDM1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: DFSDM1 peripheral clocks disabled during CSleep mode 1: DFSDM1 peripheral clocks enabled during CSleep mode (default after reset) DFSDM1 peripheral clocks are: the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock. Bits 27:25 Reserved, must be kept at reset value. Bit 24 SAI3LPEN: SAI3 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SAI3 peripheral clocks disabled during CSleep mode 1: SAI3 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SAI3 are: the kernel clock selected by SAI23SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. Bit 23 SAI2LPEN: SAI2 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SAI2 peripheral clocks disabled during CSleep mode 1: SAI2 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SAI2 are: the kernel clock selected by SAI23SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. DocID029587 Rev 3 443/3178 457 Reset and Clock Control (RCC) RM0433 Bit 22 SAI1LPEN: SAI1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SAI1 peripheral clocks disabled during CSleep mode 1: SAI1 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. Bit 21 Reserved, must be kept at reset value. Bit 20 SPI5LPEN: SPI5 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPI5 peripheral clocks disabled during CSleep mode 1: SPI5 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPI5 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. Bit 19 Reserved, must be kept at reset value. Bit 18 TIM17LPEN: TIM17 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM17 peripheral clock disabled during CSleep mode 1: TIM17 peripheral clock enabled during CSleep mode (default after reset) Bit 17 TIM16LPEN: TIM16 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM16 peripheral clock disabled during CSleep mode 1: TIM16 peripheral clock enabled during CSleep mode (default after reset) Bit 16 TIM15LPEN: TIM15 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM15 peripheral clock disabled during CSleep mode 1: TIM15 peripheral clock enabled during CSleep mode (default after reset) Bits 15:14 Reserved, must be kept at reset value. Bit 13 SPI4LPEN: SPI4 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPI4 peripheral clocks disabled during CSleep mode 1: SPI4 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. Bit 12 SPI1LPEN: SPI1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPI1 peripheral clocks disabled during CSleep mode 1: SPI1 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. Bits 11:6 Reserved, must be kept at reset value. Bit 5 USART6LPEN: USART6 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: USART6 peripheral clocks disabled during CSleep mode 1: USART6 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the USART6 are: the kernel clock selected by USART16SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock. 444/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 4 USART1LPEN: USART1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: USART1 peripheral clocks disabled during CSleep mode 1: USART1 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the USART1 are: the kernel clock selected by USART16SEL and provided to usart_ker_ck inputs, and the rcc_pclk2 bus interface clock. Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8LPEN: TIM8 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM8 peripheral clock disabled during CSleep mode 1: TIM8 peripheral clock enabled during CSleep mode (default after reset) Bit 0 TIM1LPEN: TIM1 peripheral clock enable during CSleep mode Set and reset by software. 0: TIM1 peripheral clock disabled during CSleep mode 1: TIM1 peripheral clock enabled during CSleep mode (default after reset) DocID029587 Rev 3 445/3178 457 Reset and Clock Control (RCC) 8.7.55 RM0433 RCC APB4 Sleep Clock Register (RCC_APB4LPENR) This register can be accessed via two different offset address. Table 74. RCC_APB4LPENR address offset and reset value Register Name Address Offset RCC_APB4LPENR 0x11C RCC_C1_APB4LPENR 0x17C Reset Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4LPEN Res. Res. Res. Res. RTCAPBLPEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VREFLPEN COMP12LPEN Res. LPTIM5LPEN LPTIM4LPEN LPTIM3LPEN LPTIM2LPEN Res. I2C4LPEN Res. SPI6LPEN Res. LPUART1LPEN Res. SYSCFGLPEN 0x0421 DEAA Res. rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:22 Reserved, must be kept at reset value. Bit 21 SAI4LPEN: SAI4 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SAI4 peripheral clocks disabled during CSleep mode 1: SAI4 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SAI4 are: the kernel clocks selected by SAI4ASEL and SAI4BSEL, and provided to sai_a_ker_ck and sai_b_ker_ck inputs respectively, and the rcc_pclk4 bus interface clock. Bits 20:17 Reserved, must be kept at reset value. Bit 16 RTCAPBLPEN: RTC APB Clock Enable During CSleep Mode Set and reset by software. 0: The register clock interface of the RTC (APB) is disabled during CSleep mode 1: The register clock interface of the RTC (APB) is enabled during CSleep mode (default after reset) Bit 15 VREFLPEN: VREF peripheral clock enable during CSleep mode Set and reset by software. 0: VREF peripheral clock disabled during CSleep mode 1: VREF peripheral clock enabled during CSleep mode (default after reset) Bit 14 COMP12LPEN: COMP1/2 peripheral clock enable during CSleep mode Set and reset by software. 0: COMP1/2 peripheral clock disabled during CSleep mode 1: COMP1/2 peripheral clock enabled during CSleep mode (default after reset) Bit 13 Reserved, must be kept at reset value. 446/3178 DocID029587 Rev 3 RM0433 Reset and Clock Control (RCC) Bit 12 LPTIM5LPEN: LPTIM5 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: LPTIM5 peripheral clocks disabled during CSleep mode 1: LPTIM5 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the LPTIM5 are: the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 11 LPTIM4LPEN: LPTIM4 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: LPTIM4 peripheral clocks disabled during CSleep mode 1: LPTIM4 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the LPTIM4 are: the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 10 LPTIM3LPEN: LPTIM3 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: LPTIM3 peripheral clocks disabled during CSleep mode 1: LPTIM3 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the LPTIM3 are: the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 9 LPTIM2LPEN: LPTIM2 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: LPTIM2 peripheral clocks disabled during CSleep mode 1: LPTIM2 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the LPTIM5 are: the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 8 Reserved, must be kept at reset value. Bit 7 I2C4LPEN: I2C4 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: I2C4 peripheral clocks disabled during CSleep mode 1: I2C4 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the I2C4 are: the kernel clock selected by I2C4SEL and provided to i2c_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 6 Reserved, must be kept at reset value. Bit 5 SPI6LPEN: SPI6 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: SPI6 peripheral clocks disabled during CSleep mode 1: SPI6 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the SPI6 are: the kernel clock selected by SPI6SEL and provided to spi_ker_ck input, and the rcc_pclk4 bus interface clock. Bit 4 Reserved, must be kept at reset value. Bit 3 LPUART1LPEN: LPUART1 Peripheral Clocks Enable During CSleep Mode Set and reset by software. 0: LPUART1 peripheral clocks disabled during CSleep mode 1: LPUART1 peripheral clocks enabled during CSleep mode (default after reset) The peripheral clocks of the LPUART1 are: the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock. DocID029587 Rev 3 447/3178 457 Reset and Clock Control (RCC) RM0433 Bit 2 Reserved, must be kept at reset value. Bit 1 SYSCFGLPEN: SYSCFG peripheral clock enable during CSleep mode Set and reset by software. 0: SYSCFG peripheral clock disabled during CSleep mode 1: SYSCFG peripheral clock enabled during CSleep mode (default after reset) Bit 0 Reserved, must be kept at reset value. 448/3178 DocID029587 Rev 3 0x024 Reset value reserved 0x028 RCC_ PLLCKSELR Reset value 1 0 0 0 0 0 1 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 - - - 1 0 0 0 0 0 SW[2:0] - - HPRE[3:0] - SWS[2:0] - - Res. Res. Res. Res. - D1PPRE[2:0] - D2PPRE1[2:0] STOPKERWUCK STOPWUCK - Res. Res. Res. Res. Reset value HSI48CAL[9:0] - D3PPRE[2:0] Reset value - Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 - Res. - D2PPRE2[2:0] - RTCPRE[5:0] - D1CPRE[3:0] - Res. Res. TIMPRE HRTIMSEL - Res. HSITRIM[5:0] - - PLLSRC[1:0] RCC_D3CFGR - 0 0 0 Res. Res. 0x020 RCC_D2CFGR - 0 0 0 0 0 0 0 0 DIVM1[5:0] 0x01C RCC_D1CFGR CSICAL[7:0] Res. Res. 0x018 Reset value reserved 0 0 0 0 0 0 DIVM2[5:0] 0x014 RCC_CFGR 1 0 0 0 0 - MCO1PRE[3:0] 0x00C Reset value reserved CSITRIM[4:0] Res. Res. RCC_CRRCR MCO1[2:0] 0x008 MCO2PRE[3:0] Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value DIVM3[5:0] 0x010 RCC_ICSCR MCO2[2:0] 0x004 HSIRDY HSIKERON HSION HSIDIV[1:0] Res. Res.ì PLL3RDY PLL3ON PLL2RDY PLL2ON PLL1RDY PLL1ON Res. Res. Res. Res. HSECSSON HSEBYP HSERDY HSEON D2CKRDY D1CKRDY HSI48RDY HSI48ON Res. Res. CSIKERON CSIRDY CSION Res. HSIDIVF RCC_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8.8 Res. Res. Res. Res. Res. Res. RM0433 Reset and Clock Control (RCC) RCC register map Table 75. RCC register map and reset values 0 0 0 0 0 1 HSICAL[11:0] - Reserved - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 449/3178 457 0x054 450/3178 Reset value Reset value 0 RCC_D2CCIP2R 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 FMCSEL[1:0] FRACN3[12:0] Res. Res. Res. Res. Res. Res. FRACN2[12:0] SAI1SEL[2:0] 0 Res. Res. DIVP3[6:0] QSPISEL[1:0] DIVP2[6:0] Res. Res. Res. Res. Res. Res. FRACN1[12:0] USART234578SEL[2:0] 0 0 Res. Res. DIVP1[6:0] USART16SEL[2:0] 0 0 SAI23SEL[2:0] Reset value reserved Res. Res. Res. DIVQ3[6:0] SPI123SEL[2:0] Reset value Res. Res. 0 DIVQ2[6:0] RNGSEL[1:0] 0 0 Res. Reset value Res. 0 0 0 0 0 0 1 SPI45SEL[2:0] Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 1 1 1 1 1 1 Res. Res. RCC_D2CCIP1R DIVR3[6:0] DIVQ1[6:0] I2C123SEL[1:0] 0x050 RCC_D1CCIPR 0 0 0 0 0 0 1 Res. 0x04C DIVR2[6:0] Res. Res. Res. Res. Res. Res. 0x048 0 0 0 0 0 0 1 SPDIFSEL[1:0] Reset value DIVR1[6:0] USBSEL[1:0] RCC_PLL3FRACR Res. Reset value CECSEL[1:0] RCC_PLL3DIVR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMCSEL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x040 Res. Res. Res. DFSDM1SEL Res. Res. RCC_PLL2FRACR Res. Res. Res. Res. Reset value CKPERSEL[1:0] 0x044 RCC_PLL2DIVR FDCANSEL[1:0] 0x038 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value LPTIM1SEL[2:0] 0x03C RCC_PLL1FRACR Res. 0x034 RCC_PLL1DIVR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x030 Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC_PLLCFGR PLL1VCOSEL PLL1FRACEN PLL1RGE[1:0] PLL2VCOSEL PLL2FRACEN PLL2RGE[1:0] PLL3VCOSEL PLL3FRACEN PLL3RGE[1:0] Register name Res. Res. Res. Res. Res. Res. Res. DIVR3EN DIVQ3EN DIVP3EN DIVR2EN DIVQ2EN DIVP2EN DIVR1EN DIVQ1EN DIVP1EN Res. Res. Res. Res. 0x02C SWPSEL Res. Offset Res. Reset and Clock Control (RCC) RM0433 Table 75. RCC register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 DIVN1[8:0] 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVN2[8:0] 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVN3[8:0] 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0x070 0x074 0x080 RCC_BDCR 0x078 Reset value reserved 0x07C RCC_ AHB3RSTR Reset value RCC_ AHB1RSTR Reset value Reset value reserved 0 0 0 0 0 0 0 0 0 0 0 Reserved Reset value 0 0 RCC_CSR 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 LSEBYP LSERDY LSEON 0 0 0 0 0 0 LSEDRV[1:0] 0 0 0 Res. LSECSSD LSECSSON Reset value reserved RTCSEL[1:0] 0x06C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSECSSIE PLL3RDYIE PLL2RDYIE PLL1RDYIE HSI48RDYIE CSIRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE 0x068 Reset value 0 0 0 0 0 0 0 0 0 0 RCC_CIFR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSECSSF LSECSSF PLL3RDYF PLL2RDYF PLL1RDYF HSI48RDYF CSIRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF 0x064 RCC_CIER Reset value 0 0 0 0 0 0 0 0 0 0 0 RCC_CICR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSECSSC LSECSSC PLL3RDYC PLL2RDYC PLL1RDYC HSI48RDYC CSIRDYC HSERDYC HSIRDYC LSERDYC LSIRDYC 0x060 LPUART1SEL[2:0] Res. Res. Res. Res. Res. I2C4SEL[1:0] LPTIM2SEL[2:0] LPTIM345SEL[2:0] ADCSEL[1;0] Res. Res. Res. SAI4ASEL[2:0] SAI4BSEL[2:0] Res. SPI6SEL[2:0] Res. RCC_D3CCIPR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST RTCEN Res. Res. Res. Res. Res. 0x05C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSIRDY LSION 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name CPURST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC1RST Res. QSPIRST Res. FMCRST Res. Res. Res. Res. Res. Res. JPGDECRST DMA2DRST Res. Res. Res. MDMARST Offset Res. Res. Res. Res. USB2OTGRST Res. USB1OTGRST Res. Res. Res. Res. Res. Res. Res. Res. Res. ETH1MACRST Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12RST Res. Res. Res. DMA2RST DMA1RST RM0433 Reset and Clock Control (RCC) Table 75. RCC register map and reset values (continued) 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 451/3178 457 0x094 0x098 0x09C 452/3178 Reset value RCC_ APB1HRSTR RCC_ APB2RSTR Reset value RCC_ APB4RSTR Reset value 0x0A0 RCC_GCR 0x0A4 Reset value reserved UART8RST UART7RST DAC12RST Res. HDMICECRST Res. Res. Res. I2C3RST I2C2RST I2C1RST UART5RST UART4RST USART3RST USART2RST SPDIFRXRST SPI3RST SPI2RST Res. Res. Res. Res. LPTIM1RST TIM14RST TIM13RST TIM12RST TIM7RST TIM6RST TIM5RST TIM4RST TIM3RST TIM2RST RCC_ APB1LRSTR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FDCANRST Res. Res. MDIOSRST OPAMPRST Res. RST CRSRST Res. 0x090 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDCRST Res. Res. Res. RCC_ APB3RSTR Res. Res. HRTIMRST DFSDM1RST Res. Res. Res. SAI3RST SAI2RST SAI1RST Res. SPI5RST Res. TIM17RST TIM16RST TIM15RST Res. Res. SPI4RST SPI1RST Res. Res. Res. Res. Res. Res. USART6RST USART1RST Res. Res. TIM8RST TIM1RST 0x08C Res. Res. Res. Res. Res. Res. HSEMRST ADC3RST Res. Res. BDMARST Res. CRCRST Res. Res. Res. Res. Res. Res. Res. Res. GPIOKRST GPIOJRST GPIOIRST GPIOHRST GPIOGRST GPIOFRST GPIOERST GPIODRST GPIOCRST GPIOBRST GPIOARST RCC_ AHB4RSTR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4RST Res. Res. Res. Res. Res. VREFRST COMP12RST Res. LPTIM5RST LPTIM4RST LPTIM3RST LPTIM2RST Res. I2C4RST Res. SPI6RST Res. LPUART1RST Res. SYSCFGRST Res. 0x088 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WW1RSC Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x084 RCC_ AHB2RSTR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC2RST Res. Res. RNGRST HASHRST CRYPTRST Res. Res. Res. CAMITFRST Reset and Clock Control (RCC) 0 0 0 0 0 RM0433 Table 75. RCC register map and reset values (continued) Reset value 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 Reserved DocID029587 Rev 3 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0D4 0x0D8 0x0DC 0x0E0 0x0E4 0x0E8 RCC_ AHB3ENR RCC_ AHB1ENR RCC_ AHB2ENR Reset value RCC_ AHB4ENR RCC_ APB3ENR RCC_ APB1LENR Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC1EN Res. QSPIEN Res. FMCEN Res. Res. Res. Res. Res. Res. JPGDECEN DMA2DEN Res. Res. Res. MDMAEN Reset value Res. Res. Res. USB2ULPIEN USB2OTGEN USB1ULPIEN USB1OTGEN Res. Res. Res. Res. Res. Res. Res. ETH1RXEN ETH1TXEN ETH1MACEN Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12EN Res. Res. Res. DMA2EN DMA1EN reserved Reserved RCC_RSR Res. LPWRRSTF Res. WWDG1RSTF Res. IWDG1RSTF Res. SFTRSTF PORRSTF PINRSTF BORRSTF D2RSTF D1RSTF Res. CPURSTF RMVF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0D0 SRAM3EN SRAM2EN SRAM1EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC2EN Res. Res. RNGEN HASHEN CRYPTEN Res. Res. Res. DCMIEN 0x0AC to 0x0CC SRAM4AMEN BKPRAMAMEN Res. Res. Res. ADC3AMEN Res. Res. SAI4AMEN Res. CRCAMEN Res. Res. RTCAMEN VREFAMEN COMP12AMEN Res. LPTIM5AMEN LPTIM4AMEN LPTIM3AMEN LPTIM2AMEN Res. I2C4AMEN Res. SPI6AMEN Res. LPUART1AMEN Res. Res. BDMAAMEN Res. RCC_D3AMR Res. Res. Res. BKPRAMEN Res. Res. HSEMEN ADC3EN Res. Res. BDMAEN Res. CRCEN Res. Res. Res. Res. Res. Res. Res. Res. GPIOKEN GPIOJEN GPIOIEN GPIOHEN GPIOGEN GPIOFEN GPIOEEN GPIODEN GPIOCEN GPIOBEN GPIOAEN 0x0A8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG1EN Res. Res. LTDCEN Res. Res. Res. Offset UART8EN UART7EN DAC12EN Res. HDMICECEN Res. Res. Res. I2C3EN I2C2EN I2C1EN UART5EN UART4EN USART3EN USART2EN SPDIFRXEN SPI3EN SPI2EN Res. Res. Res. Res. LPTIM1EN TIM14EN TIM13EN TIM12EN TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN RM0433 Reset and Clock Control (RCC) Table 75. RCC register map and reset values (continued) Reset value 0 0 0 Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 Reset value 0 DocID029587 Rev 3 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 453/3178 457 0x0F8 Reset value reserved 0x0FC RCC_ AHB3LPENR Reset value 0x104 0x108 0x10C 454/3178 RCC_ AHB1LPENR RCC_ AHB2LPENR Reset value RCC_ AHB4LPENR Reset value RCC_ APB3LPENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4EN Res. Res. Res. Res. RTCAPBEN VREFEN COMP12EN Res. LPTIM5EN LPTIM4EN LPTIM3EN LPTIM2EN Res. I2C4EN Reserved SPI6EN Res. LPUART1EN Res. SYSCFGEN Res. RCC_ APB4ENR AXISRAMLPEN ITCMLPEN DTCM2LPEN DTCM1LPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC1LPEN Res. QSPILPEN Res. FMCLPEN Res. Res. Res. FLASHLPEN Res. Res. JPGDECLPEN DMA2DLPEN Res. Res. Res. MDMALPEN 0x0F4 Res. Res. Res. USB2ULPILPEN USB2OTGLPEN USB1ULPILPEN USB1OTGLPEN Res. Res. Res. Res. Res. Res. Res. ETH1RXLPEN ETH1TXLPEN ETH1MACLPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12LPEN Res. Res. Res. DMA2LPEN DMA1LPEN Reset value SRAM3LPEN SRAM2LPEN SRAM1LPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC2LPEN Res. Res. RNGLPEN HASHLPEN CRYPTLPEN Res. Res. Res. CAMITFLPEN 0x100 Res. Res. HRTIMEN DFSDM1EN Res. Res. Res. SAI3EN SAI2EN SAI1EN Res. SPI5EN Res. TIM17EN TIM16EN TIM15EN Res. Res. SPI4EN SPI1EN Res. Res. Res. Res. Res. Res. USART6EN USART1EN Res. Res. TIM8EN TIM1EN RCC_ APB2ENR Res. Res. SRAM4LPEN BKPRAMLPEN Res. Res. Res. ADC3LPEN Res. Res. BDMALPEN Res. CRCLPEN Res. Res. Res. Res. Res. Res. Res. Res. GPIOKLPEN GPIOJLPEN GPIOILPEN GPIOHLPEN GPIOGLPEN GPIOFLPEN GPIOELPEN GPIODLPEN GPIOCLPEN GPIOBLPEN GPIOALPEN 0x0F0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG1LPEN Res. Res. LTDCLPEN Res. Res. Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0EC RCC_ APB1HENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FDCANEN Res. Res. MDIOSEN OPAMPEN Res. SWPEN CRSEN Res. Reset and Clock Control (RCC) 0 0 Reset value 1 1 RM0433 Table 75. RCC register map and reset values (continued) Reset value 0 0 0 0 1 0 1 0 0 0 0 1 0 0 Reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset value DocID029587 Rev 3 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x13C 0x140 RCC_C1_ AHB2ENR Reset value RCC_C1_ AHB4ENR Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 1 0 0 0 0 0 1 SYSCFGLPEN Res. LPUART1LPEN Res. 1 1 0 0 MDMAEN 1 SPI6LPEN Res. TIM8LPEN TIM1LPEN USART6LPEN USART1LPEN Res. Res. 1 1 DMA2EN DMA1EN Reset value 1 1 JPGDECEN DMA2DEN Res. Res. Res. reserved 1 1 1 1 I2C4LPEN Res. TIM17LPEN TIM16LPEN TIM15LPEN Res. Res. SPI4LPEN SPI1LPEN Res. Res. Res. Res. Res. Res. SPI5LPEN Res. 1 ADC12EN Res. Res. Res. 1 1 1 LPTIM5LPEN LPTIM4LPEN LPTIM3LPEN LPTIM2LPEN Res. 1 1 1 FMCEN Res. Res. Res. Res. Res. Res. 1 QSPIEN Res. 1 RTCAPBLPEN VREFLPEN COMP12LPEN Res. 1 1 1 SDMMC1EN Res. Reset value SAI4LPEN Res. Res. Res. Res. 1 1 SAI3LPEN SAI2LPEN SAI1LPEN Res. HRTIMLPEN DFSDM1LPEN Res. Res. Res. Res. Res. Reset value DCMIEN RCC_C1_ AHB1ENR SWPLPEN CRSLPEN Res. MDIOSLPEN OPAMPLPEN Res. FDCANLPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 1 1 1 1 1 1 1 RNGEN HASHEN CRYPTEN Res. Res. Res. 0x138 RCC_C1_ AHB3ENR 1 SDMMC2EN Res. Res. 0x134 1 1 1 ETH1RXEN ETH1TXEN ETH1MACEN Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x120 to 0x130 RCC_ APB4LPENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value USB2ULPIEN USB2OTGEN USB1ULPIEN USB1OTGEN Res. Res. Res. Res. Res. Res. Res. 0x11C RCC_ APB2LPENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x118 RCC_ APB1HLPENR Res. Res. Res. 0x114 SRAM3EN SRAM2EN SRAM1EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. BKPRAMEN Res. Res. HSEMEN ADC3EN Res. Res. DMA1EN Res. CRCEN Res. Res. Res. Res. Res. Res. Res. Res. GPIOKEN GPIOJEN GPIOIEN GPIOHEN GPIOGEN GPIOFEN GPIOEEN GPIODEN GPIOCEN GPIOBEN GPIOAEN Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x110 RCC_ APB1LLPENR UART8LPEN UART7LPEN DAC12LPEN Res. CECLPEN Res. Res. Res. I2C3LPEN I2C2LPEN I2C1LPEN UART5LPEN UART4LPEN USART3LPEN USART2LPEN SPDIFRXLPEN SPI3LPEN SPI2LPEN Res. Res. Res. Res. LPTIM1LPEN TIM14LPEN TIM13LPEN TIM12LPEN TIM7LPEN TIM6LPEN TIM5LPEN TIM4LPEN TIM3LPEN TIM2LPEN RM0433 Reset and Clock Control (RCC) Table 75. RCC register map and reset values (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 455/3178 457 0x150 0x160 0x164 456/3178 RCC_C1_ APB2ENR Reset value 0x154 RCC_C1_ APB4ENR 0x158 Reset value reserved 0x15C RCC_C1_ AHB3LPENR Reset value RCC_C1_ AHB1LPENR RCC_C1_ AHB2LPENR Reset value Res. Res. HRTIMEN DFSDM1EN Res. Res. Res. SAI3EN SAI2EN SAI1EN Res. SPI5EN Res. TIM17EN TIM16EN TIM15EN Res. Res. SPI4EN SPI1EN Res. Res. Res. Res. Res. Res. USART6EN USART1EN Res. Res. TIM8EN TIM1EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FDCANEN Res. Res. MDIOSEN OPAMPEN Res. SWPEN CRSEN Res. RCC_C1_ APB1HENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4EN Res. Res. Res. Res. RTCAPBEN VREFEN COMP12EN Res. LPTIM5EN LPTIM4EN LPTIM3EN LPTIM2EN Res. I2C4EN Res. SPI6EN Res. LPUART1EN Res. SYSCFGEN Res. Reset value AXISRAMLPEN ITCMLPEN DTCM2LPEN DTCM1LPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC1LPEN Res. QSPILPEN Res. FMCLPEN Res. Res. Res. FLASHLPEN Res. Res. JPGDECLPEN DMA2DLPEN Res. Res. Res. MDMALPEN 0x14C UART8EN UART7EN DAC12EN Res. HDMICECEN Res. Res. Res. I2C3EN I2C2EN I2C1EN UART5EN UART4EN USART3EN USART2EN SPDIFRXEN SPI3EN SPI2EN Res. Res. Res. Res. LPTIM1EN TIM14EN TIM13EN TIM12EN TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN RCC_C1_ APB1LENR Res. Res. Res. USB2ULPILPEN USB2OTGLPEN USB1ULPILPEN USB1OTGLPEN Res. Res. Res. Res. Res. Res. Res. ETH1RXLPEN ETH1TXLPEN ETH1MACLPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC12LPEN Res. Res. Res. DMA2LPEN DMA1LPEN 0x148 SRAM3LPEN SRAM2LPEN SRAM1LPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC2LPEN Res. Res. RNGLPEN HASHLPEN CRYPTLPEN Res. Res. Res. CAMITFLPEN Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x144 RCC_C1_ APB3ENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG1EN Res. Res. LTDCEN Res. Res. Res. Reset and Clock Control (RCC) 0 0 0 Reset value RM0433 Table 75. RCC register map and reset values (continued) Reset value 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DocID029587 Rev 3 0 0 1 0 0 Reserved 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0x170 0x174 0x178 0x17C 0x180 to 0x1FC RCC_C1_ APB1LLPENR Reset value RCC_C1_ APB1HLPENR RCC_C1_ APB2LPENR Reset value RCC_C1_ APB4LPENR Reset value reserved UART8LPEN UART7LPEN DAC12LPEN Res. CECLPEN Res. Res. Res. I2C3LPEN I2C2LPEN I2C1LPEN UART5LPEN UART4LPEN USART3LPEN USART2LPEN SPDIFRXLPEN SPI3LPEN SPI2LPEN Res. Res. Res. Res. LPTIM1LPEN TIM14LPEN TIM13LPEN TIM12LPEN TIM7LPEN TIM6LPEN TIM5LPEN TIM4LPEN TIM3LPEN TIM2LPEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG1LPEN Res. Res. LTDCLPEN Res. Res. Res. RCC_C1_ APB3LPENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FDCANLPEN Res. Res. MDIOSLPEN OPAMPLPEN Res. SWPLPEN CRSLPEN Res. 0x16C Res. Res. HRTIMLPEN DFSDM1LPEN Res. Res. Res. SA3LPEN SAI2LPEN SAI1LPEN Res. SPI5LPEN Res. TIM17LPEN TIM16LPEN TIM15LPEN Res. Res. SPI4LPEN SPI1LPEN Res. Res. Res. Res. Res. Res. USART6LPEN USART1LPEN Res. Res. TIM8LPEN TIM1LPEN Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI4LPEN Res. Res. Res. Res. RTCAPBLPEN VREFLPEN COMP12LPEN Res. LPTIM5LPEN LPTIM4LPEN LPTIM3LPEN LPTIM2LPEN Res. I2C4LPEN Res. SPI6LPEN Res. LPUART1LPEN Res. SYSCFGLPEN Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x168 RCC_C1_ AHB4LPENR Res. Res. SRAM4LPEN BKPRAMLPEN Res. Res. Res. ADC3LPEN Res. Res. DMA1LPEN Res. CRCLPEN Res. Res. Res. Res. Res. Res. Res. Res. GPIOKLPEN GPIOJLPEN GPIOILPEN GPIOHLPEN GPIOGLPEN GPIOFLPEN GPIOELPEN GPIODLPEN GPIOCLPEN GPIOBLPEN GPIOALPEN RM0433 Reset and Clock Control (RCC) Table 75. RCC register map and reset values (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset value 1 1 1 1 1 1 1 1 1 1 1 Reset value 1 1 1 1 1 1 1 1 DocID029587 Rev 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reserved Refer to Section 2.2.2 on page 105 for the register boundary addresses. 457/3178 457 Clock recovery system (CRS) RM0433 9 Clock recovery system (CRS) 9.1 Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides a powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal. It is capable of doing automatic adjustment of oscillator trimming based on the measured frequency error value, while keeping the possibility of a manual trimming. The CRS is ideally suited to provide a precise clock to the USB peripheral. In such case, the synchronization signal can be derived from the start-of-frame (SOF) packet signalization on the USB bus, which is sent by a USB host at precise 1-ms intervals. The synchronization signal can also be derived from the LSE oscillator output or it can be generated by user software. 9.2 CRS main features • 458/3178 Selectable synchronization source with programmable prescaler and polarity: – USB2 SOF packet reception – LSE oscillator output – USB1 SOF packet reception • Possibility to generate synchronization pulses by software • Automatic oscillator trimming capability with no need of CPU action • Manual control option for faster start-up convergence • 16-bit frequency error counter with automatic error value capture and reload • Programmable limit for automatic frequency error value evaluation and status reporting • Maskable interrupts/events: – Expected synchronization (ESYNC) – Synchronization OK (SYNCOK) – Synchronization warning (SYNCWARN) – Synchronization or trimming error (ERR) DocID029587 Rev 3 RM0433 Clock recovery system (CRS) 9.3 CRS functional description 9.3.1 CRS block diagram Figure 56. CRS block diagram &56 27*B+6B'3 FUVBV\QF 27*B+6 27*B+6B'0 26&B,1 6<1&65& FUVBV\QF /6( 26&B287 6:6<1& 6<1&GLYLGHU « 6<1& 27*B)6B'3 27*B+6 FUVBV\QF )(/,0 27*B)6B'0 FUVBLW 75,0 ELW $+%EXV )(',5 )(&$3 FUVBSFON FUVBWULP> @ 5&& +6, KVLBFN ELWFRXQWHU 5(/2$' 7R27*B+6 7R27*B+6 06Y9 DocID029587 Rev 3 459/3178 469 Clock recovery system (CRS) 9.4 RM0433 CRS internal signals Table 76 gives the list of CRS internal signals. Table 76. CRS internal input/output signals 9.4.1 Signal name Signal type crs_it Digital output CRS interrupt crs_pclk Digital input AHB bus clock hsi48_ck Digital input HSI48 oscillator clock crs_trim[0:5] Digital output HSI48 oscillator smooth trimming value crs_sync0, crs_sync1, crs_sync2 Digital input SYNC signal source selection (USB2, LSE, or USB1) Description Synchronization input The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can be the signal from the LSE clock, the USB1 SOF signal, or the USB2 SOF signal. This source signal also has a configurable polarity and can then be divided by a programmable binary prescaler to obtain a synchronization signal in a suitable frequency range (usually around 1 kHz). For more information on the CRS synchronization source configuration, refer to Section 9.7.2: CRS configuration register (CRS_CFGR). It is also possible to generate a synchronization event by software, by setting the SWSYNC bit in the CRS_CR register. 9.4.2 Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected synchronization) event is generated. Then it starts counting up to the OUTRANGE limit where it eventually stops (if no SYNC event is received) and generates a SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field of the CRS_CFGR register) multiplied by 128. When the SYNC event is detected, the actual value of the frequency error counter and its counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR (frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected during the downcounting phase (before reaching the zero value), it means that the actual frequency is lower than the target (and so, that the TRIM value should be incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). 460/3178 DocID029587 Rev 3 RM0433 Clock recovery system (CRS) Figure 57. CRS counter behavior &56FRXQWHUYDOXH 5(/2$' (6<1& 'RZQ 8S )UHTXHQF\ HUURUFRXQWHU VWRSSHG 2875$1*( [)(/,0 :$51,1*/,0,7 [)(/,0 72/(5$1&(/,0,7 )(/,0 7ULPPLQJDFWLRQ &56HYHQW 6<1&(55 6<1&:$51 6<1&2. 6<1&:$51 6<1&0,66 06Y9 DocID029587 Rev 3 461/3178 469 Clock recovery system (CRS) 9.4.3 RM0433 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register – WARNING LIMIT, defined as 3 * FELIM value – OUTRANGE (error limit), defined as 128 * FELIM value The result of this comparison is used to generate the status indication and also to control the automatic trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR register: • • • • Note: When the frequency error is below the tolerance limit, it means that the actual trimming value in the TRIM field is the optimal one and that then, no trimming action is necessary. – SYNCOK status indicated – TRIM value not changed in AUTOTRIM mode When the frequency error is below the warning limit but above or equal to the tolerance limit, it means that some trimming action is necessary but that adjustment by one trimming step is enough to reach the optimal TRIM value. – SYNCOK status indicated – TRIM value adjusted by one trimming step in AUTOTRIM mode When the frequency error is above or equal to the warning limit but below the error limit, it means that a stronger trimming action is necessary, and there is a risk that the optimal TRIM value will not be reached for the next period. – SYNCWARN status indicated – TRIM value adjusted by two trimming steps in AUTOTRIM mode When the frequency error is above or equal to the error limit, it means that the frequency is out of the trimming range. This can also happen when the SYNC input is not clean or when some SYNC pulse is missing (for example when one USB SOF is corrupted). – SYNCERR or SYNCMISS status indicated – TRIM value not changed in AUTOTRIM mode If the actual value of the TRIM field is so close to its limits that the automatic trimming would force it to overflow or underflow, then the TRIM value is set just to the limit and the TRIMOVF status is indicated. In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of CRS_CR is adjusted by hardware and is read-only. 9.4.4 CRS initialization and configuration RELOAD value The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1 The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). 462/3178 DocID029587 Rev 3 RM0433 Clock recovery system (CRS) FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be used: FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2 The result should be always rounded up to the nearest integer value in order to obtain the best trimming response. If frequent trimming actions are not wanted in the application, the trimming hysteresis can be increased by increasing slightly the FELIM value. The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000 and to a typical trimming step size of 0.14%. Caution: There is no hardware protection from a wrong configuration of the RELOAD and FELIM fields which can lead to an erratic trimming response. The expected operational mode requires proper setup of the RELOAD value (according to the synchronization source frequency), which is also greater than 128 * FELIM value (OUTRANGE limit). 9.5 CRS low-power modes Table 77. Effect of low-power modes on CRS Mode Sleep Description No effect. CRS interrupts cause the device to exit the Sleep mode. Stop CRS registers are frozen. The CRS stops operating until the Stop or Standby mode is exited and the HSI48 oscillator Standby restarted. 9.6 CRS interrupts Table 78. Interrupt control bits Interrupt event Event flag Enable control bit Clear flag bit Expected synchronization ESYNCF ESYNCIE ESYNCC Synchronization OK SYNCOKF SYNCOKIE SYNCOKC Synchronization warning SYNCWARNF SYNCWARNIE SYNCWARNC Synchronization or trimming error (TRIMOVF, SYNCMISS, SYNCERR) ERRF ERRIE ERRC DocID029587 Rev 3 463/3178 469 Clock recovery system (CRS) 9.7 RM0433 CRS registers Refer to Section 1.1 on page 98 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 9.7.1 CRS control register (CRS_CR) Address offset: 0x00 Reset value: 0x0000 2000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. SWSY AUTOT NC RIMEN TRIM[5:0] rw rw rw rw rw rw rt_w rw CEN rw Res. SYNC ESYNC SYNCO ERRIE WARNI IE KIE E rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 TRIM[5:0]: HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. Bit 7 SWSYNC: Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 0: No action 1: A software SYNC event is generated. Bit 6 AUTOTRIMEN: Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section 9.4.3: Frequency error evaluation and automatic trimming for more details. 0: Automatic trimming disabled, TRIM bits can be adjusted by the user. 1: Automatic trimming enabled, TRIM bits are read-only and under hardware control. Bit 5 CEN: Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. 0: Frequency error counter disabled 1: Frequency error counter enabled When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. Bit 4 Reserved, must be kept at reset value. 464/3178 DocID029587 Rev 3 RM0433 Clock recovery system (CRS) Bit 3 ESYNCIE: Expected SYNC interrupt enable 0: Expected SYNC (ESYNCF) interrupt disabled 1: Expected SYNC (ESYNCF) interrupt enabled Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable 0: SYNC warning (SYNCWARNF) interrupt disabled 1: SYNC warning (SYNCWARNF) interrupt enabled Bit 0 SYNCOKIE: SYNC event OK interrupt enable 0: SYNC event OK (SYNCOKF) interrupt disabled 1: SYNC event OK (SYNCOKF) interrupt enabled 9.7.2 CRS configuration register (CRS_CFGR) This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. Address offset: 0x04 Reset value: 0x2022 BB7F 31 30 SYNCP OL Res. rw 29 28 SYNCSRC[1:0] 27 26 Res. 25 24 23 22 21 SYNCDIV[2:0] 20 19 18 17 16 FELIM[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw RELOAD[15:0] rw rw Bit 31 SYNCPOL: SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 0: SYNC active on rising edge (default) 1: SYNC active on falling edge Bit 30 Reserved, must be kept at reset value. Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. 00: USB2 SOF selected as SYNC signal source 01: LSE selected as SYNC signal source 10: USB1 SOF selected as SYNC signal source (default) 11: Reserved Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE should be used as SYNC signal. Bit 27 Reserved, must be kept at reset value. DocID029587 Rev 3 465/3178 469 Clock recovery system (CRS) RM0433 Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16 101: SYNC divided by 32 110: SYNC divided by 64 111: SYNC divided by 128 Bits 23:16 FELIM[7:0]: Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 9.4.3: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. Bits 15:0 RELOAD[15:0]: Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section 9.4.2: Frequency error measurement for more details about counter behavior. 9.7.3 CRS interrupt and status register (CRS_ISR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r FECAP[15:0] r 15 r 14 r 13 12 r r 11 10 r r 9 r 8 r 7 6 5 4 3 2 1 0 FEDIR Res. Res. Res. Res. TRIMOVF SYNCMISS SYNCERR Res. Res. Res. Res. ESYNCF ERRF SYNCWARNF SYNCOKF r r r r r r r r Bits 31:16 FECAP[15:0]: Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section 9.4.3: Frequency error evaluation and automatic trimming for more details about FECAP usage. Bit 15 FEDIR: Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 0: Upcounting direction, the actual frequency is above the target. 1: Downcounting direction, the actual frequency is below the target. Bits 14:11 Reserved, must be kept at reset value. Bit 10 TRIMOVF: Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0: No trimming error signalized 1: Trimming error signalized 466/3178 DocID029587 Rev 3 RM0433 Clock recovery system (CRS) Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0: No SYNC missed error signalized 1: SYNC missed error signalized Bit 8 SYNCERR: SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0: No SYNC error signalized 1: SYNC error signalized Bits 7:4 Reserved, must be kept at reset value. Bit 3 ESYNCF: Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 0: No expected SYNC signalized 1: Expected SYNC signalized Bit 2 ERRF: Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 0: No synchronization or trimming error signalized 1: Synchronization or trimming error signalized Bit 1 SYNCWARNF: SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 0: No SYNC warning signalized 1: SYNC warning signalized Bit 0 SYNCOKF: SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0: No SYNC event OK signalized 1: SYNC event OK signalized DocID029587 Rev 3 467/3178 469 Clock recovery system (CRS) 9.7.4 RM0433 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ESYNCC ERRC SYNCWARNC SYNCOKC rw rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 ESYNCC: Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. Bit 2 ERRC: Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. Bit 1 SYNCWARNC: SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. Bit 0 SYNCOKC: SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 468/3178 DocID029587 Rev 3 RM0433 9.7.5 Clock recovery system (CRS) CRS register map SWSYNC CEN Res. ESYNCIE ERRIE SYNCWARNIE SYNCOKIE 0 0 0 0 0 0 0 0 0 0 0 CRS_ICR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Reset value SYNCOKF 0 0 0 0 0 SYNCOKC 0 ERRF 0 1 SYNCWARNF 0 1 ERRC 0 1 SYNCWARNC 0 1 ESYNCF 0 1 ESYNCC 0 1 Res. 0 1 Res. 0 0 Res. 0 1 SYNCERR 0 1 Res. 0 0 SYNCMISS 0 1 Res. 0 Res. 1 Res. 1 Res. 0 Res. FECAP[15:0] 1 Res. 0 Res. 1 TRIMOVF 0 Reset value 0x0C 0 Res. 0 Res. 0 Res. 1 Res. 0 Res. 0 Res. 0 Res. CRS_ISR 0 0 RELOAD[15:0] Res. 0 0 FELIM[7:0] Res. 0 0 FEDIR 1 SYNC DIV [2:0] Res. 0 Res. Reset value SYNC SRC [1:0] Res. 0x08 CRS_CFGR Res. 0x04 1 SYNCPOL Reset value TRIM[5:0] AUTOTRIMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRS_CR Res. 0x00 Res. Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 79. CRS register map and reset values 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 469/3178 469 Hardware semaphore (HSEM) RM0433 10 Hardware semaphore (HSEM) 10.1 Hardware semaphore introduction The hardware semaphore block provides 32 (32-bit) register based semaphores. The semaphores can be used to ensure synchronization between different processes running on the core. The HSEM provides a non blocking mechanism to lock semaphores in an atomic way. The following functions are provided: • • Locking a semaphore can be done in two ways: – 2-step lock: by writing MasterID and ProcessID to the semaphore, followed by a Read check – 1-step lock: by reading the MasterID from the semaphore Interrupt generation when a semaphore is freed – • Semaphore clear protection – • 10.2 Each semaphore may generate an interrupt A semaphore will only be cleared when MasterID and ProcessID match Global semaphore clear per MasterID Hardware semaphore main features The HSEM includes the following features: • • • • • 470/3178 32 (32-bit) semaphores 8-bit ProcessID 4-bit MasterID 1 interrupt line Lock indication DocID029587 Rev 3 RM0433 Hardware semaphore (HSEM) 10.3 HSEM functional description 10.3.1 HSEM block diagram As shown in Figure 58, the HSEM is based on three sub-blocks: • The Semaphore block containing the semaphore status and IDs • The Semaphore Interface block providing AHB access to the Semaphore via the HSEM_R and HSEM_RLR registers • The Interrupt interface block providing control for the interrupts via the HSEM_CnISR, HSEM_CnIER, HSEM_CnMISR, and HSEM_CnICR registers Figure 58. HSEM block diagram ELW$+%EXV +6(0 %XV0DVWHU,' ,QWHUUXSWLQWHUIDFH 6HPDSKRUHLQWHUIDFH 6HPDSKRUHEORFN 6HPB,QWV +6(0B5 +6(0B0,65 +6(0B5 6HPDSKRUH +6(0B,(5 KVHPBKFON +6(0B5/5 6HPB,QWV +6(0B,65 6HPDSKRUH KVHPBLQWBLW +6(0B5/5 6HPB,QWV +6(0B5 6HPDSKRUH +6(0B5/5 +6(0B,&5 06Y 9 10.3.2 HSEM internal signals Table 80. HSEM internal input/output signals Signal name Signal type hsem_hclk Digital input hsem_int_it Digital output DocID029587 Rev 3 Description AHB clock Interrupt line 471/3178 483 Hardware semaphore (HSEM) 10.3.3 RM0433 HSEM lock procedures There are two lock procedures: • 2-step (Write) lock • 1-step (Read) lock The semaphore is free when its lock bit is ‘0’, in this case the MasterID and ProcessID are also ‘0. When the lock bit is ‘1’ the semaphore is locked and the MasterID indicates which AHB bus master has locked it. The ProcessID indicates which process of that AHB bus master has locked the semaphore. When Write locking a semaphore, the MasterID is taken from the bus master ID and the ProcessID is taken from the Write data. When Read locking the semaphore, the MasterID is taken from the master ID, and the ProcessID will be zero. There are no ProcessID available with the 1-step (Read) lock. The MasterID is taken from the AHB bus master ID. The ProcessID is written by the firmware of that AHB bus master. Each AHB bus master process must have a unique ProcessID. ProcessID is only available in the 2-step lock procedure. The two procedures (1-step and 2-step) can be used concurrently. Figure 59. Procedure state diagram :5,7( /2&. :5,7( 0DVWHU,' 3URFHVV,' /2&. RU 5($'/2&. :5,7( /2&. RU :5,7( 0DVWHU,'RU3URFHVV,' /RFN )UHH 5($' /RFNHG &OHDU :5,7( 0DVWHU,' 3URFHVV,' /2&. 5($' RU 5($'/2&. 06Y 9 2-step (Write) lock procedure The 2-step lock procedure consists in a Write to lock the semaphore, followed by a Read to check if the lock has been successful, carried out from the HSEM_Rn register • Write semaphore with ProcessID and MasterID, and LOCK bit = 1 (Lock will be put in place when semaphore is free at Write time) • Read-back the semaphore (FW checks lock status, if ProcessID and MasterID match, then lock is confirmed). • Else retry (the semaphore has been locked by another AHB bus master or process) A semaphore can only be locked when it is free. A semaphore can be locked when the ProcessID is ‘0’. Consecutive write attempts with the lock bit = 1 to a locked semaphore are ignored. 472/3178 DocID029587 Rev 3 RM0433 Hardware semaphore (HSEM) 1-step (Read) lock procedure The 1-step procedure consists in a Read to lock and check the semaphore in a single step from the HSEM_RLRn register. • Read Lock semaphore with MasterID. • If Read MasterID matches and ProcessID = 0, then lock is put in place. (if MasterID matches and ProcessID is not ‘0’, this means that another process from the same MasterID has locked the semaphore with a 2-step (Write) procedure. • Else retry (the semaphore has been locked by another AHB bus master or process) A semaphore can only be locked when it is free. When Read locking a free semaphore the ProcessID will be ‘0’. Read locking a locked semaphore will return the MasterID and ProcessID that locked it. All Read locks, including the first one which locks the semaphore, will return the MasterID that locks or has locked the semaphore. If multiple processes of the same AHB bus master use the 1-step procedure, all processes using the same semaphore will read the same status. When only one process locks the semaphore, each process of that AHB bus master will read the semaphore as locked by itself with the MasterID. 10.3.4 HSEM Write/Read/ReadLock register address For each semaphore, two AHB register addresses are provided, separated in two banks of 0x80. In the first register address bank the semaphore can be written (locked/cleared) and read through the HSEM_R registers. In the second register address bank the semaphore can be read (locked) through the HSEM_RLR registers. 10.3.5 HSEM Clear procedures Clearing a semaphore is a protected process, to prevent accidental clearing by a AHB bus master or by a process that does not have the semaphore lock right. The semaphore Clear procedure consists in writing to the semaphore with the corresponding MasterID and ProcessID and the lock bit = 0. When cleared, the semaphore lock bit, the MasterID, and the ProcessID are all ‘0’. When cleared, an interrupt may be generated to signal the event. To this end, the semaphore interrupt shall be enabled. The Clear procedure consists in a Write to the semaphore HSEM_R register • Write semaphore with ProcessID and MasterID, lock bit = 0 • If ProcessID and MasterID match, semaphore is freed, and an interrupt may be generated when enabled • Else Write is ignored, semaphore remains locked and no interrupts are generated (the semaphore is locked by another AHB bus master or process) If multiple processes of the same AHB bus master use the 1-step lock procedure (ProcessID = 0), all processes using the same semaphore will clear the semaphore also for the other processes of that AHB bus master. DocID029587 Rev 3 473/3178 483 Hardware semaphore (HSEM) 10.3.6 RM0433 HSEM MasterID semaphore clear All semaphores locked by a AHB bus master can be cleared all at once by using the HSEM_CR register. The procedure to clear all semaphores locked by a AHB bus master is the following: • Write MasterID and correct KEY value. All locked semaphore with a matching MasterID are cleared (set to free), and may generate an interrupt when enabled. This procedure may be used in case of an incorrect functioning AHB bus master, where the AHB bus master can free the locked semaphores by writing the MasterID into the HSEM_CR register with the correct KEY value. This will clear all locked semaphores with a matching MasterID. An interrupt may be generated for the semaphore(s) that become free. To this end, the semaphore interrupt shall be enabled in the HSEM_CnIER registers. 10.3.7 HSEM interrupts hsem_int_it interrupt line allows each of the 32 semaphores to generate an interrupt. This interrupt line provides the following features: • Interrupt enable per semaphore • Interrupt clear per semaphore • Interrupt status per semaphore • Masked interrupt status per semaphore With the Interrupt enable (HSEM_CnIER) the semaphores affecting the interrupt line can be enabled. Disabled (masked) semaphore interrupts will not set the masked interrupt status for that semaphore, and will not generate an interrupt on the interrupt line. The Interrupt clear (HSEM_CnICR) will clear the Interrupt status and Masked interrupt status of the associated semaphore for the interrupt line. The Interrupt status (HSEM_CnISR) mirrors the semaphore Interrupt status of the interrupt line before the Enable. The Masked interrupt status (HSEM_CnMISR) only mirrors the semaphore Interrupt status of the enabled semaphore interrupts on the interrupt line. All Masked interrupt status of the enabled semaphore need to be cleared in order to clear the interrupt line. 474/3178 DocID029587 Rev 3 RM0433 Hardware semaphore (HSEM) Figure 60. Interrupt state diagram 6HPDSKRUH1 ORFNHG :5,7( 0DVWHU,' 3URFHVV,' /2&. ,QWHUUXSW 6HPDSKRUH1 6WDWXV 1R ,QWHUUXSW 6HPDSKRUH1 (QDEOHG @LQ *3,2[B02'(5 UHVHWVWDWH RSHQ 3&B& 3&B& 7R$'& 3$B& 3$B& Figure 67. Analog inputs connected to ADC inputs 3[\62ELWLQ 6<6&)*B30&5 UHVHWVWDWH FORVHG 7R$'& $OWHUQDWH)XQFWLRQ,QSXW 5HDG:ULWH )URPRQFKLSSHULSKHUDOV )URPDQDORJSHULSKHUDOV 2XWSXWGDWDUHJLVWHU :ULWH %LW6HW5HVHW UHJLVWHU 9'' 2QRII 287387 &21752/ $OWHUQDWH)XQFWLRQ2XWSXW 3& 3& 3$ 2QRII 3$ *3,2 6FKPLWW 7ULJJHU ,QSXW'ULYHU 3XOOXS 5HDG 9''RU 9'' 9''B)7 2QRII 3XOOGRZQ ,QSXWGDWDUHJLVWHU 7RRQFKLSSHULSKHUDOV 966 966 966 2XWSXW'ULYHU 3XVK 3XOO 2SHQ'UDLQ 'LVDEOHG $QDORJ 06Y 9 1. VDD_FT is a potential specific to 5V tolerant I/Os. It is distinct from VDD. 11.3.14 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect. When the oscillator is configured in a user external clock mode, only the OSC_IN or OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO. 11.3.15 Using the GPIO pins in the backup supply domain The PC13/PC14/PC15/PI8 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode. DocID029587 Rev 3 493/3178 501 General-purpose I/Os (GPIO) 11.4 .GPIO RM0433 registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table 84. The peripheral registers can be written in word, half word or byte mode. 11.4.1 GPIO port mode register (GPIOx_MODER) (x =A..K) Address offset:0x00 Reset values: 31 30 • 0xABFF FFFF for port A • 0xFFFF FEBF for port B • 0xFFFF FFFF for other ports 29 MODER15[1:0] 28 MODER14[1:0] 27 26 MODER13[1:0] 25 24 MODER12[1:0] 23 22 MODER11[1:0] 21 20 MODER10[1:0] 19 18 MODER9[1:0] 17 16 MODER8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODER7[1:0] rw rw MODER6[1:0] rw rw MODER5[1:0] rw rw MODER4[1:0] rw rw MODER3[1:0] rw rw MODER2[1:0] rw rw MODER1[1:0] rw rw MODER0[1:0] rw rw Bits 2y+1:2y MODERy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode. 00: Input mode (reset state) 01: General purpose output mode 10: Alternate function mode 11: Analog mode 11.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..K) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OTy: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 494/3178 DocID029587 Rev 3 RM0433 General-purpose I/Os (GPIO) 11.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..K) Address offset: 0x08 Reset value: 31 • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports 30 29 OSPEEDR15 [1:0] 28 27 OSPEEDR14 [1:0] 26 25 OSPEEDR13 [1:0] 24 OSPEEDR12 [1:0] 23 22 OSPEEDR11 [1:0] 21 20 OSPEEDR10 [1:0] 19 18 17 16 OSPEEDR9 [1:0] OSPEEDR8 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSPEEDR7 [1:0] OSPEEDR6 [1:0] OSPEEDR5 [1:0] OSPEEDR4 [1:0] OSPEEDR3 [1:0] OSPEEDR2 [1:0] OSPEEDR1 [1:0] OSPEEDR0 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y OSPEEDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. 00: Low speed 01: Medium speed 10: High speed 11: Very high speed Note: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD range and external load. 11.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..K) Address offset: 0x0C Reset values: 31 30 PUPDR15[1:0] • 0x6400 0000 for port A • 0x0000 0100 for port B • 0x0000 0000 for other ports 29 28 PUPDR14[1:0] 27 26 PUPDR13[1:0] 25 24 PUPDR12[1:0] 23 22 PUPDR11[1:0] 21 20 PUPDR10[1:0] 19 18 PUPDR9[1:0] 17 16 PUPDR8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUPDR7[1:0] rw rw PUPDR6[1:0] rw rw PUPDR5[1:0] rw rw PUPDR4[1:0] rw rw PUPDR3[1:0] rw rw DocID029587 Rev 3 PUPDR2[1:0] rw rw PUPDR1[1:0] rw rw PUPDR0[1:0] rw rw 495/3178 501 General-purpose I/Os (GPIO) RM0433 Bits 2y+1:2y PUPDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved 11.4.5 GPIO port input data register (GPIOx_IDR) (x = A..K) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 IDRy: Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port. 11.4.6 GPIO port output data register (GPIOx_ODR) (x = A..K) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ODRy: Port output data bit (y = 0..15) These bits can be read and written by software. Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F). 11.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..K) Address offset: 0x18 Reset value: 0x0000 0000 496/3178 DocID029587 Rev 3 RM0433 General-purpose I/Os (GPIO) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Sets the corresponding ODRx bit 11.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..K) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 497/3178 501 General-purpose I/Os (GPIO) RM0433 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next MCU reset or peripheral reset. Bits 15:0 LCKy: Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is ‘0. 0: Port configuration not locked 1: Port configuration locked 11.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..K) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 AFR7[3:0] 26 25 24 23 22 AFR6[3:0] 21 20 19 AFR5[3:0] 18 17 16 AFR4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AFR3[3:0] rw rw rw AFR2[3:0] rw rw rw rw AFR1[3:0] rw rw rw rw AFR0[3:0] rw rw Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 498/3178 1000: AF8 1001: AF9 1010: AF10 1011: AF11 1100: AF12 1101: AF13 1110: AF14 1111: AF15 DocID029587 Rev 3 rw rw rw RM0433 General-purpose I/Os (GPIO) 11.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..J) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 AFR15[3:0] 26 25 24 23 22 AFR14[3:0] 21 20 19 AFR13[3:0] 18 17 16 AFR12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AFR11[3:0] rw rw rw AFR10[3:0] rw rw rw rw AFR9[3:0] rw rw rw rw AFR8[3:0] rw rw rw rw rw Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 1000: AF8 1001: AF9 1010: AF10 1011: AF11 1100: AF12 1101: AF13 1110: AF14 1111: AF15 DocID029587 Rev 3 499/3178 501 0x08 Reset value GPIOB_OSPEEDR Reset value GPIOx_OSPEEDR (where x = C..K) Reset value 0x0C 0x0C 500/3178 GPIOA_PUPDR Reset value GPIOB_PUPDR Reset value 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIOx_OTYPER (where x = A..K) Reset value 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OT1 OT0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSPEEDR0[1:0] MODER0[1:0] MODER0[1:0] 1 OSPEEDR0[1:0] MODER1[1:0] 1 OSPEEDR0[1:0] MODEv1[1:0] 1 PUPDR0[1:0] OT2 1 PUPDR0[1:0] OT3 OSPEEDR1[1:0] 1 OSPEEDR1[1:0] MODER2[1:0] 0 OSPEEDR1[1:0] MODER2[1:0] 1 PUPDR1[1:0] OT4 1 PUPDR1[1:0] OT5 OSPEEDR2[1:0] 1 OSPEEDR2[1:0] MODER3[1:0] 0 OSPEEDR2[1:0] MODER3[1:0] 1 PUPDR2[1:0] OT6 1 PUPDR2[1:0] OT7 OSPEEDR3[1:0] 1 OSPEEDR3[1:0] MODER4[1:0] 1 OSPEEDR3[1:0] MODER4[1:0] 1 PUPDR3[1:0] OT8 1 PUPDR3[1:0] OT9 OSPEEDR4[1:0] 1 OSPEEDR4[1:0] 1 OSPEEDR4[1:0] MODER5[1:0] 1 PUPDR4[1:0] MODER5[1:0] 1 PUPDR4[1:0] OT11 OT10 OSPEEDR5[1:0] 1 OSPEEDR5[1:0] MODER6[1:0] 1 OSPEEDR5[1:0] MODER6[1:0] 1 PUPDR5[1:0] OT12 1 PUPDR5[1:0] OT13 OSPEEDR6[1:0] 1 OSPEEDR6[1:0] 1 OSPEEDR6[1:0] MODER7[1:0] 1 PUPDR6[1:0] MODER7[1:0] 1 PUPDR6[1:0] OT14 1 OT15 OSPEEDR7[1:0] MODER8[1:0] 1 OSPEEDR7[1:0] MODER8[1:0] 1 OSPEEDR7[1:0] 1 Res. 1 PUPDR7[1:0] 1 Res. 1 PUPDR7[1:0] OSPEEDR8[1:0] MODER9[1:0] 1 OSPEEDR8[1:0] MODER9[1:0] 1 OSPEEDR8[1:0] 1 Res. 1 PUPDR8[1:0] 1 Res. 1 PUPDR8[1:0] OSPEEDR9[1:0] MODER10[1:0] 1 OSPEEDR9[1:0] MODER10[1:0] 1 OSPEEDR9[1:0] 1 Res. 1 PUPDR9[1:0] 1 Res. 1 PUPDR9[1:0] OSPEEDR10[1:0] MODER11[1:0] 1 OSPEEDR10[1:0] MODER11[1:0] 1 OSPEEDR10[1:0] 1 Res. 1 PUPDR10[1:0] 1 Res. 1 PUPDR10[1:0] OSPEEDR11[1:0] MODER12[1:0] 1 OSPEEDR11[1:0] MODER12[1:0] 1 OSPEEDR11[1:0] 1 Res. 1 PUPDR11[1:0] 1 Res. 0 PUPDR11[1:0] OSPEEDR12[1:0] MODER13[1:0] 1 OSPEEDR12[1:0] MODER13[1:0] 1 OSPEEDR12[1:0] 1 Res. 1 PUPDR12[1:0] 1 Res. MODER14[1:0] 0 PUPDR12[1:0] OSPEEDR13[1:0] MODER14[1:0] 1 OSPEEDR13[1:0] 1 Res. 1 OSPEEDR13[1:0] 1 Res. 1 PUPDR13[1:0] OSPEEDR14[1:0] MODER15[1:0] 0 PUPDR13[1:0] GPIOA_OSPEEDR OSPEEDR14[1:0] GPIOx_MODER (where x = C..K) 1 OSPEEDR14[1:0] 0x00 MODER15[1:0] Reset value PUPDR14[1:0] 0x08 GPIOB_MODER 1 PUPDR14[1:0] 0x08 1 Res. 0x04 Reset value Res. Reset value OSPEEDR15[1:0] 0x00 MODE0[1:0] MODE1[1:0] MODE2[1:0] MODE3[1:0] MODE4[1:0] MODE5[1:0] MODE6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] MODE15[1:0] GPIOA_MODER OSPEEDR15[1:0] 0x00 OSPEEDR15[1:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name PUPDR15[1:0] 11.4.11 PUPDR15[1:0] General-purpose I/Os (GPIO) RM0433 GPIO register map The following table gives the GPIO register map and reset values. Table 84. GPIO register map and reset values 1 1 1 1 1 1 0 0 0 0 0 RM0433 General-purpose I/Os (GPIO) 0 0 0 0 0 0x10 Res. Res. PUPDR0[1:0] 0 0 0 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 ODR0 BS11 BS10 0 LCK11 0 LCK10 0 BS12 0 BS13 0 LCK12 0 LCK13 0 BS14 0 BS15 0 LCK14 0 LCK15 0 BR0 0 BR1 0 Res. 0 LCKK 0 BR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFR4[3:0] 0 x ODR1 Res. 0 x ODR2 Res. 0 x ODR3 Res. 0 x ODR4 Res. 0 x ODR5 Res. 0 x ODR6 Res. 0 x ODR7 Res. 0 x ODR8 Res. 0 x ODR9 Res. 0 x ODR11 Res. Reset value 0 x ODR10 Res. Reset value AFR5[3:0] x ODR12 Res. 0x24 GPIOx_AFRH (where x = A..K) AFR6[3:0] x 0 Reset value AFR7[3:0] x ODR13 Res. 0x20 GPIOx_AFRL (where x = A..K) x ODR14 0x1C Reset value x ODR15 0 Res. 0 Res. BR3 0 Res. BR4 0 Res. BR5 0 Res. BR6 0 Res. BR7 0 Res. BR8 0 Res. BR9 0 Res. BR11 BR10 0 Res. BR12 0 Res. BR13 0 Res. BR14 0 Res. BR15 Reset value GPIOx_LCKR (where x = A..K) Res. 0x18 GPIOx_BSRR (where x = A..I/J/K) Res. GPIOx_ODR (where x = A..K) Res. 0x14 Res. Reset value IDR0 0 IDR1 0 Res. PUPDR1[1:0] 0 IDR2 0 IDR3 0 Res. PUPDR2[1:0] 0 IDR4 0 IDR5 0 Res. PUPDR3[1:0] 0 IDR6 0 IDR7 0 Res. PUPDR4[1:0] 0 IDR8 0 IDR9 0 Res. PUPDR5[1:0] 0 IDR11 0 IDR10 0 Res. PUPDR6[1:0] 0 IDR12 0 IDR13 0 Res. PUPDR7[1:0] 0 IDR14 0 IDR15 0 Res. PUPDR8[1:0] 0 Res. PUPDR9[1:0] PUPDR10[1:0] 0 Res. PUPDR11[1:0] PUPDR12[1:0] 0 Res. PUPDR13[1:0] Reset value GPIOx_IDR (where x = A..I/J/K) Res. PUPDR14[1:0] GPIOx_PUPDR (where x = C..K) Res. PUPDR15[1:0] 0x0C Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 84. GPIO register map and reset values (continued) 0 0 0 AFR3[3:0] 0 0 0 0 AFR2[3:0] 0 0 0 0 AFR15[3:0] AFR14[3:0] AFR13[3:0] AFR12[3:0] AFR11[3:0] AFR10[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFR1[3:0] 0 0 0 0 AFR9[3:0] 0 0 0 0 AFR0[3:0] 0 0 0 0 AFR8[3:0] 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 501/3178 501 System configuration controller (SYSCFG) RM0433 12 System configuration controller (SYSCFG) 12.1 Introduction The devices feature a set of configuration registers. The objectives of this section is to describe in details the system configuration controller. 12.2 SYSCFG main features The system configuration controller main functions are the following: • Analog switch configuration management • I2C Fm+ configuration • Selection of the Ethernet PHY interface. • Management of the external interrupt line connection to the GPIOs • Management of the I/O compensation cell • Getting readout protection and Flash memory bank swap informations • Management of boot sequences and boot addresses • Management BOR reset level • Management of Flash memory secured and protected sector status • Management Flash memory write protections status • Management of DTCM secured section status • Management of independent watchdog behavior (hardware or software / freeze) • Reset generation in Stop and Standby mode • Secure mode enabling/disabling. 12.3 SYSCFG register description 12.3.1 SYSCFG peripheral mode configuration register (SYSCFG_PMCR) Address offset: 0x04 Reset value: 0x0X00 0000 ) 31 30 29 28 Res. Res. Res. Res. 15 Res. 14 Res. 502/3178 13 Res. 12 Res. 27 26 25 24 PC3SO PC2SO PA1SO 23 PA0SO 22 21 EPIS[2:0] 18 17 16 Res. Res. Res. rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 BOOSTE PB9 FMP PB8 FMP PB7 FMP PB6 FMP I2C4 FMP I2C3 FMP I2C2 FMP I2C1 FMP rw rw rw rw rw rw rw rw rw Res. Res. rw 19 Res. rw Res. rw 20 Res. DocID029587 Rev 3 rw RM0433 System configuration controller (SYSCFG) Bits 31:28 Reserved, must be kept at reset value. Bit 27 PC3SO: PC3 Switch Open This bits controls the analog switch between PC3 and PC3_C (dual pad) 0: Analog switch closed (pads are connected through the analog switch) 1: Analog switch open (2 separated pads) Bit 26 PC2SO: PC2 Switch Open This bits controls the analog switch between PC2 and PC2_C (dual pad) 0: Analog switch closed (pads are connected through the analog switch) 1: Analog switch open (2 separated pads) Bit 25 PA1SO: PA1 Switch Open This bits controls the analog switch between PA1 and PA1_C (dual pad) 0: Analog switch closed (pads are connected through the analog switch) 1: Analog switch open (2 separated pads) Bit 24 PA0SO: PA0 Switch Open This bits controls the analog switch between PA0 and PA0_C (dual pad) 0: Analog switch closed (pads are connected through the analog switch) 1: Analog switch open (2 separated pads) Bits 23:21 EPIS[2:0]: Ethernet PHY Interface Selection These bits select the Ethernet PHY interface. 000: MII 001: Reserved 010: Reserved 011: Reserved 100: RMII 101: Reserved 110: Reserved 111: Reserved Bits 20:9 Reserved, must be kept at reset value. Bit 8 BOOSTE: Booster Enable This bit enables the booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V. Activating the booster allows to guaranty the analog switch AC performance when the supply voltage is below 2.7 V: in this case, the analog switch performance is the same on the full voltage range. 0: Booster disabled 1: Booster enabled Bit 7 PB9FMP: PB(9) Fm+ This bit enables I2C Fm+ on PB(9). 0: Fm+ disabled 1: Fm+ enabled Bit 6 PB8FMP: PB(8) Fast Mode Plus This bit enables I2C Fm+ on PB(8). 0: Fm+ disabled 1: Fm+ enabled DocID029587 Rev 3 503/3178 523 System configuration controller (SYSCFG) RM0433 Bit 5 PB7FMP: PB(7) Fast Mode Plus this bit enables I2C Fm+ on PB(7). 0: Fm+ disabled 1: Fm+ enabled Bit 4 PB6FMP: PB(6) Fm+ This bit enables I2C Fm+ on PB(6). 0: Fm+ disabled 1: Fm+ enabled Bit 3 I2C4FMP: I2C4 Fm+ This bit enables Fm+ on I2C4. 0: Fm+ disabled 1: Fm+ enabled Bit 2 I2C3FMP: I2C3 Fm+ This bit enables Fm+ on I2C3. 0: Fm+ disabled 1: Fm+ enabled Bit 1 I2C2FMP: I2C2 Fm+ This bit enables Fm+ on I2C2. 0: Fm+ disabled 1: Fm+ enabled Bit 0 I2C1FMP: I2C1 Fm+ This bit enables Fm+ on I2C1. 0: Fm+ disabled 1: Fm+ enabled 12.3.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI3[3:0] rw 504/3178 rw rw EXTI2[3:0] rw rw rw EXTI1[3:0] rw rw rw rw DocID029587 Rev 3 rw EXTI0[3:0] rw rw rw rw rw RM0433 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3) These bits are written by software to select the source input for the EXTI input for external interrupt / event detection. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 0111: PH[x] pin 1000: PI[x] pin 1001: PJ[x] pin 1010: PK[x] pin Other configurations: reserved 12.3.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7[3:0] rw rw rw EXTI6[3:0] rw rw rw EXTI5[3:0] rw rw rw rw rw EXTI4[3:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTI input for external interrupt / event detection. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 0111: PH[x] pin 1000: PI[x] pin 1001: PJ[x] pin 1010: PK[x] pin Other configurations: reserved DocID029587 Rev 3 505/3178 523 System configuration controller (SYSCFG) 12.3.4 RM0433 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11[3:0] rw rw rw EXTI10[3:0] rw rw rw rw EXTI9[3:0] rw rw rw rw EXTI8[3:0] rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11) These bits are written by software to select the source input for the EXTI input for external interrupt / event detection. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 0111: PH[x] pin 1000: PI[x] pin 1001: PJ[x] pin 1010: PK[x] pin Other configurations: reserved Note: PK[11:8] are not used 506/3178 DocID029587 Rev 3 rw RM0433 System configuration controller (SYSCFG) 12.3.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 EXTI15[3:0] rw rw rw EXTI14[3:0] rw rw rw rw EXTI13[3:0] rw rw rw rw EXTI12[3:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15) These bits are written by software to select the source input for the EXTI input for external interrupt / event detection. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 0111: PH[x] pin 1001: PJ[x] pin 1010: PK[x] pin Other configurations: reserved Note: PK[15:12] are not used. DocID029587 Rev 3 507/3178 523 System configuration controller (SYSCFG) 12.3.6 RM0433 SYSCFG compensation cell control/status register (SYSCFG_CCCSR) Address offset: 0x20 Reset value: 0x0000 0000 Refer to Section 11.3.11: I/O compensation cell for a detailed description of I/O compensation mechanism. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSLV rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. READY Res. Res. Res. Res. Res. Res. CS EN rw rw r Bits 31:17 Reserved, must be kept at reset value. Bit 16 HSLV: High-speed at low-voltage This bit is written by software to optimize the I/O speed when the product voltage is low. This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V might be destructive. 0: No I/O speed optimization 1: I/O speed optimization Bits 15:9 Reserved, must be kept at reset value. Bit 8 READY: Compensation cell ready flag This bit provides the status of the compensation cell. 0: I/O compensation cell not ready 1: I/O compensation cell ready Bits 7:2 Reserved, must be kept at reset value. Bit 1 CS: Code selection This bit selects the code to be applied for the I/O compensation cell. 0: Code from the cell (available in the SYSCFG_CCVR) 1: Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) Bit 0 EN: Enable This bit enables the I/O compensation cell. 0: I/O compensation cell disabled 1: I/O compensation cell enabled 508/3178 DocID029587 Rev 3 RM0433 System configuration controller (SYSCFG) 12.3.7 SYSCFG compensation cell value register (SYSCFG_CCVR) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PCV[3:0] r NCV[3:0] r r r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 PCV[3:0]: PMOS compensation value This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is reset. Bits 3:0 NCV[3:0]: NMOS compensation value This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is reset. 12.3.8 SYSCFG compensation cell code register (SYSCFG_CCCR) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PCC[3:0] rw rw rw NCC[3:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 PCC[3:0]: PMOS compensation code This bits are written by software to define an I/O compensation cell code for PMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CMPCR is set. Bits 3:0 NCC[3:0]: NMOS compensation code This bits are written by software to define an I/O compensation cell code for NMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CCCSR is set. DocID029587 Rev 3 509/3178 523 System configuration controller (SYSCFG) 12.3.9 RM0433 SYSCFG package register (SYSCFG_PKGR) Address offset: 0x124 Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKG[3:0 r Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 PKG[3:0]: Package This bits indicate the device package. 0000: LQFP100 (STM32H7x3) 0010: TQFP144 (STM32H7x3) 0101: TQFP176/UFBGA176 (STM32H7x3) 1000: LQFP208/TFBGA240 (STM32H7x3) Other configurations: all pads enabled 510/3178 DocID029587 Rev 3 r r r RM0433 System configuration controller (SYSCFG) 12.3.10 SYSCFG user register 0 (SYSCFG_UR0) Address offset: 0x300 Reset value: 0x00XX 000X 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 RDP[7:0] r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKS r Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 RDP[7:0]: Readout protection This bits indicate the readout protection level. 0xAA: Level 0 (no protection) 0xCC: Level 2 (Flash memory readout protected, full debug features, boot from SRAM and boundary scan disabled) Other configurations: Level 1 (Flash memory readout protected, limited debug features and boundary scan enabled) Bits 15:1 Reserved, must be kept at reset value. Bit 0 BKS: Bank Swap This bit indicates Flash memory bank mapping. 0: Flash memory bank addresses are inverted 1: Flash memory banks are mapped to their original addresses 12.3.11 SYSCFG user register 2 (SYSCFG_UR2) Address offset: 0x308 Reset value: 0xXXXX 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BOOT_ADD0[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BORH[1:0] r DocID029587 Rev 3 r 511/3178 523 System configuration controller (SYSCFG) RM0433 Bits 31:16 BOOT_ADD0[15:0]: Boot Address 0 These bits define the MSB of the core boot address when BOOT pin is low. Bits 15:2 Reserved, must be kept at reset value. Bits 1:0 BORH[1:0]: BOR_LVL Brownout Reset Threshold Level These bits indicate the Brownout reset high level. 0x11: BOR High Reset Level threshold for 2.7-3.6 V range 0x10: BOR Medium Reset Level threshold for 2.4-2.7 V range 0x01: BOR Low Reset Level threshold for 2.1-2.4 V range 0x00: BOR OFF Reset Level threshold for 2.7-3.6 range 12.3.12 SYSCFG user register 3 (SYSCFG_UR3) Address offset: 0x30C Reset value: 0xXXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BOOT_ADD1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 BOOT_ADD1[15:0]: Boot Address 1 These bits define the MSB of the core boot address when BOOT pin is high. 12.3.13 SYSCFG user register 4 (SYSCFG_UR4) Address offset: 0x310 Reset value: 0x000X XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEPAD_1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r Bits 31:17 Reserved, must be kept at reset value. Bit 16 MEPAD_1: Mass Erase Protected Area Disabled for bank 1 This bit indicates if the flash protected area (Bank 1) is affected by a mass erase. 0: When a mass erase occurs the protected area is erased 1: When a mass erase occurs the protected area is not erased Bits 15:0 Reserved, must be kept at reset value. 512/3178 DocID029587 Rev 3 RM0433 System configuration controller (SYSCFG) 12.3.14 SYSCFG user register 5 (SYSCFG_UR5) Address offset: 0x314 Reset value: 0x00XX 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MESAD_1 WRPS_1[7:0] r Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 WRPN_1[7:0]: Write protection for flash bank 1 WRPN[i] bit indicates if the sector i of the Flash memory bank 1 is protected. 0: Write protection is active on sector i 1: Write protection is not active on sector i Bits 15:1 Reserved, must be kept at reset value. Bit 0 MESAD_1: Mass erase secured area disabled for bank 1 This bit indicates if the flash secured area (bank 1) is affected by a mass erase. 0: When a mass erase occurs the secured area is erased 1: When a mass erase occurs the secured area is not erased 12.3.15 SYSCFG user register 6 (SYSCFG_UR6) Address offset: 0x318 Reset value: 0x0XXX 0XXX 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 PA_END_1[11:0] r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r PA_BEG_1[11:0] r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 23:16 PA_END_1[11:0]: Protected area end address for bank 1 End address for bank 1 protected area. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 PA_BEG_1[11:0]: Protected area start address for bank 1 Start address for bank 1 protected area. DocID029587 Rev 3 513/3178 523 System configuration controller (SYSCFG) 12.3.16 RM0433 SYSCFG user register 7 (SYSCFG_UR7) Address offset: 0x31C Reset value: 0x0XXX 0XXX 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 SA_END_1[11:0] r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r SA_BEG_1[11:0] r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 23:16 SA_END_1[11:0]: Secured area end address for bank 1 End address for bank 1 secured area. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 SA_BEG_1[11:0]: Secured area start address for bank 1 Start address for bank 1 secured area. 12.3.17 SYSCFG user register 8 (SYSCFG_UR8) Address offset: 0x320 Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MESAD_2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEPAD_2 r r Bits 31:17 Reserved, must be kept at reset value. Bit 16 MESAD_2: Mass erase secured area disabled for bank 2 This bit indicates if the Flash memory secured area (Bank 2) is affected by a mass erase. 0: When a mass erase occurs the secured area is erased 1: When a mass erase occurs the secured area is not erased Bits 15:1 Reserved, must be kept at reset value. Bit 0 MEPAD_2: Mass erase protected area disabled for bank 2 This bit indicates if the Flash memory protected area (Bank 2) is affected by a mass erase. 0: When a mass erase occurs the protected area is erased 1: When a mass erase occurs the protected area is not erased 514/3178 DocID029587 Rev 3 RM0433 System configuration controller (SYSCFG) 12.3.18 SYSCFG user register 9 (SYSCFG_UR9) Address offset: 0x324 Reset value: 0x0XXX 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. r r r PA_BEG_2[11:0] WRPS_2[7:0] r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 PA_BEG_2[11:0]: Protected area start address for bank 2 Start address for bank 2 protected area. Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 WRPN_2[7:0]: Write protection for flash bank 2 WRPN[i] bit indicates if the sector i of the Flash memory bank 2 is protected. 0: Write protection is active on sector i 1: Write protection is not active on sector i 12.3.19 SYSCFG user register 10 (SYSCFG_UR10) Address offset: 0x328 Reset value: 0x0XXX 0XXX 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 SA_BEG_2[11:0] r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r PA_END_2[11:0] r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 SA_BEG_2[11:0]: Secured area start address for bank 2 Start address for bank 2 secured area. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 PA_END_2[11:0]: Protected area end address for bank 2 End address for bank 2 protected area. DocID029587 Rev 3 515/3178 523 System configuration controller (SYSCFG) 12.3.20 RM0433 SYSCFG user register 11 (SYSCFG_UR11) Address offset: 0x32C Reset value: 0x000X 0XXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IWDG1M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. r r r r r r SA_END_2[11:0] r r r r r r r Bits 31:17 Reserved, must be kept at reset value. Bit 16 IWDG1M: Independent Watchdog 1 mode This bit indicates the control mode of the Independent Watchdog 1 (IWDG1). 0: IWDG1 controlled by software 1: IWDG1 controlled by hardware Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 SA_END_2[11:0]: Secured area end address for bank 2 End address for bank 2 secured area. 12.3.21 SYSCFG user register 12 (SYSCFG_UR12) Address offset: 0x330 Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SECURE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r Bits 31:17 Reserved, must be kept at reset value. Bit 16 SECURE: Secure mode This bit indicates the Secure mode status. 0: Secure mode disabled 1: Secure mode enabled Bits 15:0 Reserved, must be kept at reset value. 516/3178 DocID029587 Rev 3 RM0433 System configuration controller (SYSCFG) 12.3.22 SYSCFG user register 13 (SYSCFG_UR13) Address offset: 0x334 Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. D1SBRST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw 0 SDRS[1:0] r r Bits 31:17 Reserved, must be kept at reset value. Bit 16 D1SBRST: D1 Standby reset This bit indicates if a reset is generated when D1 domain enters DStandby mode. 0: A reset is generated by entering D1 Standby mode 1: D1 Standby mode is entered without reset generation Bits 15:2 Reserved, must be kept at reset value. Bits 1:0 SDRS[1:0]: Secured DTCM RAM Size This bits indicates the size of the secured DTCM RAM. 00: 2 Kbytes 01: 4 Kbytes 10: 8 Kbytes 11: 16 Kbytes DocID029587 Rev 3 517/3178 523 System configuration controller (SYSCFG) 12.3.23 RM0433 SYSCFG user register 14 (SYSCFG_UR14) Address offset: 0x338 Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. D1STPRST rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:1 Reserved, must be kept at reset value. Bit 0 D1STPRST: D1 Stop Reset This bit indicates if a reset is generated when D1 domain enters in DStop mode. 0: A reset is generated entering D1 Stop mode 1: D1 Stop mode is entered without reset generation 518/3178 DocID029587 Rev 3 RM0433 System configuration controller (SYSCFG) 12.3.24 SYSCFG user register 15 (SYSCFG_UR15) Address offset: 0x33C Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FZIWDGS TB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r Bits 31:17 Reserved, must be kept at reset value. Bit 16 FZIWDGSTB: Freeze independent watchdog in Standby mode This bit indicates if the independent watchdog is frozen in Standby mode. 0: Independent Watchdog frozen in Standby mode 1: Independent Watchdog running in Standby mode Bits 15:0 Reserved, must be kept at reset value. DocID029587 Rev 3 519/3178 523 System configuration controller (SYSCFG) 12.3.25 RM0433 SYSCFG user register 16 (SYSCFG_UR16) Address offset: 0x340 Reset value: 0x000X 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FZIWDG STP r r Bits 31:17 Reserved, must be kept at reset value. Bit 16 PKP: Private key programmed This bit indicates if the device private key is programmed. 0: Private key not programmed 1: Private key programmed Bits 15:1 Reserved, must be kept at reset value. Bit 0 FZIWDGSTP: Freeze independent watchdog in Stop mode This bit indicates if the independent watchdog is frozen in Stop mode. 0: Independent Watchdog frozen in Stop mode 1: Independent Watchdog running in Stop mode 12.3.26 SYSCFG user register 17 (SYSCFG_UR17) Address offset: 0x344 Reset value: 0x0000 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IO_HSLV r Bits 31:1 Reserved, must be kept at reset value. Bit 0 IO_HSLV: I/O high speed / low voltage This bit indicates that the IOHSLV option bit is set. 0: Product is working on the full voltage range 1: Product is working below 2.7 V 520/3178 DocID029587 Rev 3 0x128 0x2FC 0x300 0x304 0x308 0x30C Reserved SYSCFG_PKGR Reserved SYSCFG_UR0 SYSCFG_UR3 Reset value Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSLV Res. Res. Res. Res. Res. Res. Res. Res. READY Res. Res. Res. Res. Res. CS EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X 0 0 0 0 0 RDP[7:0] SYSCFG_UR2 BOOT_ADD0[15:0] Reset value X X X X X X X X X X X X X X X X Reset value DocID029587 Rev 3 0 Reset value Reset value PCV[3:0] PCC[3:0] Reset value BORH[1:0] 0x124 SYSCFG_CCCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKS 0x2C 0x120 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BOOSTE PB9FMP PB8FMP PB7FMP PB6FMP I2C4FMP I2C3FMP I2C2FMP I2C1FMP EPIS[2:0] Res. Res. Res. PC3SO PC2SO PA1SO PA0SO Res. Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x28 SYSCFG_CCVR Res. 0x24 SYSCFG_CCSR Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x20 Res. 0x14 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x10 Res. 0x0C Reset value SYSCFG_ EXTICR1 Reset value SYSCFG_ EXTICR2 Reset value SYSCFG_ EXTICR3 Reset value SYSCFG_ EXTICR4 Reset value Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x08 SYSCFG_PMCR Res. 0x04 Res. Res. Res. Res. Res. Res. Res. 0x00 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12.3.27 Res. RM0433 System configuration controller (SYSCFG) SYSCFG register maps The following table gives the SYSCFG register map and the reset values. Table 85. SYSCFG register map and reset values Reserved 0 0 0 0 0 0 0 0 0 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCV[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCC[3:0] X X X X PKG[3:0] x x x x x x x x Reserved x BOOT_ADD1[15:0] X X X X X X X X X X X X X X X X X X 521/3178 523 0x330 0x334 0x338 0x33C SYSCFG_UR11 SYSCFG_UR12 SYSCFG_UR13 SYSCFG_UR14 SYSCFG_UR15 522/3178 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IWDG1M Res. Res. Res. Res. Reset value Reset value SDRS[1:0] 0x32C Res. Res. Res. Res. SYSCFG_UR10 Res. 0x328 Res. Res. Res. Res. Reset value Reset value Reset value SA_END_1[11:0] Reset value Reset value Reset value Reset value Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. PA_END_1[11:0] Res. Res. Res. Res. Reset value PA_END_2[11:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MESAD_2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEPAD_2 Res. Res. Res. Res. Res. Res. Res. Res. Res. WRPN_1[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MESAD_1 Reset value SA_BEG_2[11:0] Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_UR9 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SECURE RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. Res.. 0x324 SYSCFG_UR8 Res. 0x320 SYSCFG_UR7 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. D1SBRST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x31C SYSCFG_UR6 Res. 0x318 SYSCFG_UR5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. D1STPRST 0x314 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEPAD_1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_UR4 Res. 0x310 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FZIWDGSTB RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. System configuration controller (SYSCFG) RM0433 Table 85. SYSCFG register map and reset values (continued) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PA_BEG_1[11:0] X X X X X X X X X X X X SA_BEG_1[11:0] X X X X X X X X X X X X x x WRPN_2[7:0] PA_END_2[11:0] X X X X X X X X X X X X X X X X X X X X SA_END_2[11:0] X X X X X X X X X X X X X X X X X X X 0x340 0x344 SYSCFG_UR17 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKP RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. FZIWDGSTP Res. SYSCFG_UR16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. RES. IO_HSLV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 System configuration controller (SYSCFG) Table 85. SYSCFG register map and reset values (continued) Reset value X Reset value DocID029587 Rev 3 X X Refer to Section 2.2.2 on page 105 for the register boundary addresses. 523/3178 523 Block interconnect RM0433 13 Block interconnect 13.1 Peripheral interconnect 13.1.1 Introduction Several peripherals have direct connections between them. This enables autonomous communication and synchronization between peripherals, thus saving CPU resources and power consumption. These hardware connections remove software latency, allow the design of a predictable system and result in a reduction of the number of pins and GPIOs. 13.1.2 Connection overview There are several types of connections. • Asynchronous connections (A) The source output signal is sampled by the destination clock, leading to introduction of a possible jitter in the latency between the source output event and the destination event detection • Synchronous connections (S) Both source and destination are synchronous (they run on the same clock), and the latency from the source to the destination is deterministic. No jitter is introduced. • Immediate connections (I) Either the source or the destination is an analog signal. • Break/fault connection for TIM/HRTIM outputs (B) The source output signal disables the timer outputs through a pure combinational logic path, without any latency. 524/3178 DocID029587 Rev 3 RM0433 Block interconnect Table 86. Peripherals interconnect matrix (D2 domain) (1) (2) Destination D3 domain AHB1 DFSDM1 HRTIM LPTIM2 LPTIM3 LPTIM4 LPTIM5 COMP1 COMP2 - S S S A S - - - - I I S S - - - - A S S - - S S S S A S - - - - I I - S S - S - - S S S - - S - S S - S - - - - - - - - - - S - - S - - - - - - - S - - - - - - - - - - S - - - - - - - S S S S - S - - - - - - TIM7 - - - - S - - - - - - - S S - - - - - - - - - - TIM13 - - - - S - - - - - - - - - - - - - - - - - - - TIM14 - - - - S - - - - - - - - - - - - - - - - - - - LPTIM1 - - - - - - - - - - - - - A A A A A - - - - - - SPDIFRX - - - - - - - - - - - - S - - - - - - - - - - - - OPAMP - - - - - - - - - - - - - - A - - - - - - - - - - CAN - - - A - - - - - - - - - - A - - A - - - - - - - TIM1 S S S S - - S - - - S S - - S S S S - S - - - - I I TIM8 S - S S - - S - - - - - - - S S S - S - - - - I I TIM15 - S - - - - S - - S - - - - S S S - S - - - - I I TIM16 - - - - - - - - - - - S - - S S - - - - - - - - - - TIM17 - - - - - - - - - - - S - - S - - - - - - - - - - SAI1 A - - - - - - - - - - - - - - - - - - - - A - - - - SAI2 - - - A - - - - - - - - - - - - - - - - - - A - - - DFSDM1 - - - - - - - - - B B B B B - - - - - - - - - - - - TIM3 S - TIM4 S S TIM5 - TIM6 S A ADC3 TIM17 - ADC2 TIM16 - ADC1 CAN A S S S S S TIM15 CRS - - TIM8 DAC S TIM2 TIM1 LPTIM1 - TIM4 - TIM3 - TIM2 TIM12 APB4 TIM5 APB1 AHB1 APB2 D2 domain APB2 ETHERNET APB1 Source AHB4 D2 domain HRTIM - - - - - - A - A - - - - - S - A A A A - - - - - - ADC1 - - - - - - - - - A - - - - - A - - - - - - - - - - ADC2 - - - - - - - - - - A - - - - A - - - - - - - - - - A A - - - - - - A - - - - - - - - - - - - - - - - ETH USB1 A A - - A - - - - - - - - - - - - - - - - - - USB2 A A - - A - - - - - - - - - - - - - - - - - - 1. Letters in the table correspond to the type of connection described in Section 13.1.2: Connection overview 2. The “-” symbol in a gray cell means no interconnect. DocID029587 Rev 3 525/3178 558 Block interconnect RM0433 Table 87. Peripherals interconnect matrix (D3 domain) (1) (2) Destination D3 domain AHB4 APB4 D2 domain APB1 TIM3 TIM4 TIM5 TIM12 LPTIM1 DAC CRS CAN TIM1 TIM8 TIM15 TIM16 TIM17 DFSDM1 HRTIM ADC1 ADC2 ETHERNET ADC3 LPTIM2 LPTIM3 LPTIM4 LPTIM5 AHB1 TIM2 APB4 APB2 EXTI - - - - - - A - - - - - - - A - A A - - - - - - LPTIM2 - - - - - - A - - - - - - - A A A A - A - A A A LPTIM3 - - - - - - - - - - - - - - A - A A - A - - A A LPTIM4 - - - - - - - - - - - - - - - - - - - - - A - A LPTIM5 - - - - - - - - - - - - - - - - - - - - - A A - COMP1 A A - - - A - - - A/B A/B B B B A/B - - - - A - - - COMP2 A A - - - A - - - A/B A/B B B B A/B - - - - A - - - SAI4 - - - - - - - - - - - - - - - - - - - - - A - A RTC - - - - - A - - - - - - A - - - - - - - A - - - ADC3 - - - - - - - - - A A - - - - - - - - - - - - - RCC A - - - - - - A - - - A A A - - - - - - - - - - AHB4 D3 Domain Source 1. Letters in the table correspond to the type of connection described in Section 13.1.2: Connection overview. 2. The “-” symbol in a gray cell means no interconnect. 526/3178 DocID029587 Rev 3 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) Source Domain Bus APB2 D2 APB1 AHB1 D3 D2 D3 APB4 APB2 APB4 Destination Type Comment ITR0 S - TRGO ITR1 S - TIM3 TRGO ITR2 S - TIM4 TRGO ITR3 S - ETH PPS ITR4 S - USB1 SOF ITR5 S - USB2 SOF ITR6 S - COMP1 comp1_out ETR1 I - COMP2 comp2_out ETR2 I - RCC lse_ck ETR3 A - SAI1 SAI1_FS_A ETR4 A - SAI1 SAI1_FS_B ETR5 A - COMP1 comp1_out TI4_1 I - COMP2 comp2_out TI4_2 I - TI4_3 I - Peripheral Signal Signal TIM1 TRGO TIM8 COMP1 or comp1_out or COMP2(2) comp2_out D2 D3 TIM2 Bus Domain APB1 D2 APB2 TIM1 TRGO ITR0 S - APB1 TIM2 TRGO ITR1 S - APB2 TIM15 TRGO ITR2 S - APB1 TIM4 TRGO ITR3 S - AHB1 ETH PPS ITR4 S - COMP1 comp1_out ETR1 I - COMP1 comp1_out TI1_1 I - COMP2 comp2_out TI1_2 I - TI1_3 I - S - S - S - S - APB4 COMP1 or comp1_out or COMP2(2) comp2_out APB2 D2 Peripheral APB1 APB2 TIM1 TRGO ITR0 TIM2 TRGO ITR1 TIM3 TRGO ITR2 TIM8 TRGO ITR3 TIM3 TIM4 DocID029587 Rev 3 APB1 APB1 D2 D2 527/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Bus APB2 APB1 D2 AHB1 APB2 APB1 APB1 D2 AHB1 AHB2 D3 528/3178 AHB4 Destination Type Comment ITR0 S - TRGO ITR1 S - TIM3 TRGO ITR2 S - TIM4 TRGO ITR3 S - CAN SOC ITR6 S - USB1 SOF ITR7 S - USB2 SOF ITR8 S - SAI2 SAI2_FS_A ETR1 A - SAI2 SAI2_FS_B ETR2 A - CAN TMP TI1_1 A - CAN RTP TI1_2 A - TIM4 TRGO ITR0 S - TIM5 TRGO ITR1 S - TIM13 OC1 ITR2 S - TIM14 OC1 ITR3 S - USB1 SOF crs_sync2 CRS APB1 D2 A - USB2 SOF crs_sync0 CRS APB1 D2 A - USB1 SOF crs_sync2 CRS APB1 D2 A - USB2 SOF crs_sync0 CRS APB1 D2 A - RCC lse_ck crs_sync1 CRS APB1 D2 A - Peripheral Signal Signal TIM1 TRGO TIM8 Peripheral TIM5 TIM12 DocID029587 Rev 3 Bus Domain APB1 APB1 D2 D2 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain D2 D3 D2 Destination Type Comment ITR0 S - TRGO ITR1 S - TIM3 TRGO ITR2 S - TIM4 TRGO ITR3 S - COMP1 comp1_out ETR1 I - COMP2 comp2_out ETR2 I - ADC1 adc1_awd1 ETR3 A - ADC1 adc1_awd2 ETR4 A - ADC1 adc1_awd3 ETR5 A - ADC3 adc3_awd1 ETR6 A - A - Bus Peripheral Signal Signal APB2 TIM15 TRGO TIM2 APB1 APB4 AHB1 AHB4 D3 APB4 D2 APB2 D3 APB4 D2 APB2 Peripheral TIM1 Bus Domain APB2 D2 ADC3 adc3_awd2 ETR7 ADC3 adc3_awd3 ETR8 A - COMP1 comp1_out TI1_1 I - COMP1 comp1_out BRK_1 B - COMP2 comp2_out BRK_2 B - DFSDM1 dfsdm1_ break0 BRK_3 B - COMP1 comp1_out BRK2_1 B - COMP2 comp2_out BRK2_2 B - DFSDM1 dfsdm1_ break1 BRK2_3 B - DocID029587 Rev 3 529/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain D2 D3 D2 Type Comment ITR0 S - TRGO ITR1 S - TIM4 TRGO ITR2 S - TIM5 TRGO ITR3 S - COMP1 comp1_out ETR1 I - COMP2 comp2_out ETR2 I - ADC2 adc2_awd1 ETR3 A - ADC2 adc2_awd2 ETR4 A - ADC2 adc2_awd3 ETR5 A - ADC3 adc3_awd1 ETR6 A - A - Bus Peripheral Signal Signal APB2 TIM1 TRGO TIM2 APB1 APB4 AHB1 AHB4 D3 APB4 D2 APB2 D3 APB4 D2 APB2 530/3178 Destination Peripheral TIM8 Bus Domain APB2 D2 ADC3 adc3_awd2 ETR7 ADC3 adc3_awd3 ETR8 A - COMP2 comp2_out TI1_1 I - COMP1 comp1_out BRK_1 B - COMP2 comp2_out BRK_2 B - DFSDM1 dfsdm1_ break2 BRK_3 B - COMP1 comp1_out BRK2_1 B - COMP2 comp2_out BRK2_2 B - DFSDM1 dfsdm1_ break3 BRK2_3 B - DocID029587 Rev 3 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain D2 D2 Type Comment ITR0 S - TRGO ITR1 S - TIM16 OC1 ITR2 S - TIM17 OC1 ITR3 S - TIM2 CH1 TI1_1 A - TIM3 CH1 TI1_2 A - TIM4 CH1 TI1_3 A - RCC lse_ck TI1_4 A - A - Bus Peripheral Signal Signal APB2 TIM1 TRGO APB1 TIM3 APB2 APB1 D3 Destination AHB4 APB1 D3 APB4 D2 APB2 AHB4 D3 APB4 Peripheral TIM15 Bus Domain APB2 D2 RCC csi_ck TI1_5 RCC MCO2 TI1_6 A - TIM2 CH2 TI2_1 A - TIM3 CH2 TI2_2 A - TIM4 CH2 TI2_3 A - COMP1 comp1_out BRK_1 B - COMP2 comp2_out BRK_2 B - DFSDM1 dfsdm_ break0 BRK_3 B - RCC lsi_ck TI1_1 A - RCC lse_ck TI1_2 A - RTC WKUP_IT TI1_3 A - COMP1 comp1_out BRK_1 B - COMP2 comp2_out BRK_2 B - TIM16 APB2 D2 D2 APB2 DFSDM1 dfsdm_ break1 BRK_3 B - D2 APB1 SPDIFRX spdifrx_frame_ sync TI1_1 A - RCC HSE_1MHZ TI1_2 A - RCC MCO1 TI1_3 A - COMP1 comp1_out BRK_1 B - COMP2 comp2_out BRK_2 B - DFSDM1 dfsdm_ break2 BRK_3 B - AHB4 D3 APB4 D2 APB2 TIM17 DocID029587 Rev 3 APB2 D2 531/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Destination Type Comment hrtim_evt11 B - hrtim_evt12 B - adc1_awd1 hrtim_evt13 B - hrtim_evt21 B - hrtim_evt22 B - adc1_awd2 hrtim_evt23 B - hrtim_evt31 B - hrtim_evt32 B - ADC1 adc1_awd3 hrtim_evt33 B - OPAMP1 opamp1_out hrtim_evt41 B - hrtim_evt42 B - adc2_awd1 hrtim_evt43 B - Domain Bus Peripheral Signal Signal D3 APB4 COMP1 comp1_out APB2 TIM1 TRGO AHB1 ADC1 APB4 COMP2 OUT APB2 TIM2 TRGO AHB1 ADC1 NC NC NC APB2 TIM3 TRGO AHB1 D2 D3 D2 D3 D2 D3 D2 APB1 TIM7 TRGO Peripheral Bus Domain AHB1 ADC2 NC NC NC hrtim_evt51 B - APB1 LPTIM1 lptim1_out hrtim_evt52 B - AHB1 ADC2 adc2_awd2 hrtim_evt53 B - APB4 COMP1 comp1_out hrtim_evt61 I - APB1 TIM6 S - AHB1 ADC2 adc2_awd3 hrtim_evt63 A - APB4 COMP2 comp2_out hrtim_evt71 I - APB1 TIM7 TRGO hrtim_evt72 S - NC NC NC hrtim_evt73 - - hrtim_evt81 - - APB1 TIM6 TRGO hrtim_evt82 S - CAN TTCAN_TMP hrtim_evt83 A - OPAMP1 opamp1_out hrtim_evt91 I - hrtim_evt92 S - TTCAN_RTP hrtim_evt93 A - APB1 TRGO APB2 D2 APB2 TIM15 APB1 CAN NC NC NC hrtim_ evt101 D3 APB4 LPTIM2 lptim2_out hrtim_ evt102 A - D2 APB1 CAN TTCAN_SOC hrtim_ evt103 A - 532/3178 TRGO hrtim_evt62 HRTIM DocID029587 Rev 3 - RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain D3 Bus Destination Type Comment hrtim_in_ flt1 B - comp2_out hrtim_in_ flt2 B - TIM16 OC hrtim_upd_ en1 S - TIM17 OC hrtim_upd_ en2 S - TIM6 TRGO hrtim_upd_ en3 S - TIM7 TRGO hrtim_bm _trg S - TIM16 OC hrtim_bm _ck1 S - TIM17 OC hrtim_bm _ck2 S - TIM7 TRGO hrtim_bm _ck3 S - Peripheral Signal Signal COMP1 comp1_out COMP2 APB4 APB2 APB1 D2 APB2 APB1 D3 APB4 Peripheral HRTIM Bus Domain APB2 D2 RTC rtc_alarm_a_ lptim1_ext_ evt trg0 A - RTC rtc_alarm_b_ lptim1_ext_ evt trg1 A - RTC rtc_tamp1_evt lptim1_ext_ trg2 A - RTC rtc_tamp2_evt lptim1_ext_ trg3 A - RTC rtc_tamp3_evt lptim1_ext_ trg4 A - COMP1 comp1_out lptim1_ext_ trg5 I - COMP2 comp2_out lptim1_ext_ trg6 I - COMP1 comp1_out lptim1_in1_ mux1 I - COMP2 comp2_out lptim1_in2_ mux2 I - LPTIM1 DocID029587 Rev 3 APB1 D2 533/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain D3 D3 D2 534/3178 Bus APB4 Peripheral Destination Signal Signal Peripheral Type Comment Bus Domain RTC rtc_alarm_a_ lptim2_ext_ evt trg0 A - RTC rtc_alarm_b_ lptim2_ext_ evt trg1 A - RTC rtc_tamp1_evt lptim2_ext_ trg2 A - RTC rtc_tamp2_evt lptim2_ext_ trg3 A - RTC rtc_tamp3_evt lptim2_ext_ trg4 A - COMP1 comp1_out lptim2_ext_ trg5 I - COMP2 comp2_out lptim2_ext_ trg6 I - COMP1 comp1_out lptim2_in1_ mux1 I - COMP2 comp2_out lptim2_in1_ mux2 I - COMP1 or comp1_out or lptim2_in1_ mux3 COMP2 (2) comp2_out I - LPTIM2 APB4 D3 COMP2 comp2_out lptim2_in2_ mux1 I - LPTIM2 lptim2_out lptim3_ext_ trg0 S If same kernel clock source NC NC lptim3_ext_ trg1 - - LPTIM4 lptim4_out lptim3_ext_ trg2 S If same kernel clock source LPTIM5 lptim5_out lptim3_ext_ trg3 S If same kernel clock source SAI1 SAI1_FS_A lptim3_ext_ trg4 A - SAI1 SAI1_FS_B lptim3_ext_ trg5 A - SAI1 SAI1_FS_A lptim3_in1_ mux1 A - SAI1 SAI1_FS_B lptim3_in1_ mux2 A - APB4 APB2 LPTIM3 DocID029587 Rev 3 APB4 D3 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain D3 D2 D3 Bus Destination Type Comment lptim4_ext_ trg0 S If same kernel clock source lptim3_out lptim4_ext_ trg1 S If same kernel clock source NC NC lptim4_ext_ trg2 LPTIM5 lptim5_out lptim4_ext_ trg3 SAI2 SAI2_FS_A SAI2 Peripheral Signal Signal LPTIM2 lptim2_out LPTIM3 APB4 Bus Domain LPTIM4 APB4 D3 S If same kernel clock source lptim4_ext_ trg4 A - SAI2_FS_B lptim4_ext_ trg5 A - LPTIM2 lptim2_out lptim5_ext_ trg0 S If same kernel clock source LPTIM3 lptim3_out lptim5_ext_ trg1 S If same kernel clock source LPTIM4 lptim4_out lptim5_ext_ trg2 S If same kernel clock source SAI4 SAI4_FS_A lptim5_ext_ trg3 A - SAI4 SAI4_FS_B lptim5_ext_ trg4 A - APB2 APB4 Peripheral LPTIM5 DocID029587 Rev 3 APB4 D3 535/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Destination Type Comment dac_ch1/2_ trg0 S - TRGO dac_ch1/2_ trg1 S - TIM4 TRGO dac_ch1/2_ trg02 S - TIM5 TRGO dac_ch1/2_ trg3 S - TIM6 TRGO dac_ch1/2_ trg4 S - TIM7 TRGO dac_ch1/2_ trg5 S - TIM8 TRGO dac_ch1/2_ trg6 S - TIM15 TRGO dac_ch1/2_ trg7 S - hrtim_dac_ trg1 dac_ch1/2_ trg8 S - hrtim_dac_ trg2 dac_ch1/2_ trg9 S - LPTIM1 lptim1_out dac_ch1/2_ trg10 S - LPTIM2 lptim2_out dac_ch1/2_ trg11 S - SYSCFG EXTI9 dac_ch1/2_ trg12 S - Bus Peripheral Signal Signal APB2 TIM1 TRGO TIM2 APB1 D2 APB2 HRTIM1 APB1 D3 536/3178 APB4 Peripheral Bus Domain DAC channel APB1 1/channel 2 DocID029587 Rev 3 D2 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Bus APB2 APB1 D2 APB2 APB1 Type Comment TRG0 S - TRGO2 TRG1 S - TIM8 TRGO TRG2 S - TIM8 TRGO2 TRG3 S - TIM3 TRGO TRG4 S - TIM4 TRGO TRG5 S - TIM16 OC1 TRG6 S - TIM6 TRGO TRG7 S - TIM7 TRGO TRG8 S - HRTIM1 hrtim_adc_ trg1 TRG9 S - HRTIM1 hrtim_adc_ trg3 TRG10 S - SYSCFG EXTI11 TRG24 A - SYSCFG EXTI15 TRG25 A - LPTIM1 lptim1_out TRG26 A - LPTIM2 lptim2_out TRG27 A - LPTIM3 lptim3_out TRG28 A - TIM1 CC1 adc_ext_trg 0 S - TIM1 CC2 adc_ext_trg 1 S - TIM1 CC3 adc_ext_trg 2 S - TIM2 CC2 adc_ext_trg 3 S - TIM3 TRGO adc_ext_trg 4 S - TIM4 CC4 adc_ext_trg 5 S - SYSCFG EXTI11 adc_ext_trg 6 A - Peripheral Signal Signal TIM1 TRGO TIM1 APB2 D3 APB4 D2 APB1 D3 APB4 APB2 Destination D2 APB1 D3 APB4 Peripheral DFSDM1 ADC1 / ADC2 DocID029587 Rev 3 Bus Domain APB2 AHB1 D2 D2 537/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Destination Type Comment adc_ext_trg 7 S - TRGO2 adc_ext_trg 8 S - TIM1 TRGO adc_ext_trg 9 S - TIM1 TRGO2 adc_ext_trg 10 S - TIM2 TRGO adc_ext_trg 11 S - TIM4 TRGO adc_ext_trg 12 S - TIM6 TRGO adc_ext_trg 13 S - APB2 TIM15 TRGO adc_ext_trg 14 S - APB1 TIM3 CC4 adc_ext_trg 15 S - HRTIM1 hrtim_adc_ adc_ext_trg trg1 16 A - HRTIM1 hrtim_adc_ adc_ext_trg trg3 17 A - LPTIM1 lptim1_out adc_ext_trg 18 A - LPTIM2 lptim2_out adc_ext_trg 19 A - LPTIM3 lptim3_out adc_ext_trg 20 A - TIM1 TRGO adc_jext_ trg0 S - TIM1 CC4 adc_jext_ trg1 S - TIM2 TRGO adc_jext_ trg2 S - TIM2 CC1 adc_jext_ trg3 S - TIM3 CC4 adc_jext_ trg4 S - TIM4 TRGO adc_jext_ trg5 S - Bus Peripheral Signal Signal TIM8 TRGO TIM8 APB2 APB1 D2 APB2 D3 APB4 APB2 D2 APB1 538/3178 Peripheral ADC1 / ADC2 ADC1 / ADC2 DocID029587 Rev 3 Bus Domain AHB1 AHB1 D2 D2 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Destination Type Comment adc_jext_ trg6 A - CC4 adc_jext_ trg7 S - TIM1 TRGO2 adc_jext_ trg8 S - TIM8 TRGO adc_jext_ trg9 S - TIM8 TRGO2 adc_jext_ trg10 S - TIM3 CC3 adc_jext_ trg11 S - TIM3 TRGO adc_jext_ trg12 S - TIM3 CC1 adc_jext_ trg13 S - TIM6 TRGO adc_jext_t rg14 S - TIM15 TRGO adc_jext_ trg15 S - HRTIM1 hrtim_adc_ trg2 adc_jext_ trg16 A - HRTIM1 hrtim_adc_ trg4 adc_jext_tr g17 A - LPTIM1 lptim1_out adc_jext_ trg18 A - LPTIM2 lptim2_out adc_jext_ trg19 A - LPTIM3 lptim2_out adc_jext_ trg20 A - Domain Bus Peripheral Signal Signal D3 APB4 SYSCFG EXTI15 TIM8 APB2 D2 APB1 APB2 APB1 D3 APB4 Peripheral ADC1 / ADC2 DocID029587 Rev 3 Bus Domain AHB1 D2 539/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Bus APB2 D2 APB1 D3 APB4 APB2 Comment EXT0 S - CC2 EXT1 S - TIM1 CC3 EXT2 S - TIM2 CC2 EXT3 S - TIM3 TRGO EXT4 S - TIM4 CC4 EXT5 S - SYSCFG EXTI11 EXT6 A - TIM8 TRGO EXT7 S - TIM8 TRGO2 EXT8 S - TIM1 TRGO EXT9 S - TIM1 TRGO2 EXT10 S - S - Signal Signal TIM1 CC1 TIM1 Peripheral ADC3 Bus Domain AHB4 D3 TRGO EXT11 TIM4 TRGO EXT12 S - TIM6 TRGO EXT13 S - APB2 TIM15 TRGO EXT14 S - APB1 TIM3 CC4 EXT15 S - HRTIM1 hrtim_adc_ trg1 EXT16 A - HRTIM1 hrtim_adc_ trg3 EXT17 A - LPTIM1 lptim1_out EXT18 A - LPTIM2 lptim2_out EXT19 A - LPTIM3 lptim3_out EXT20 A - D2 APB2 540/3178 Type Peripheral TIM2 APB1 D3 Destination APB4 DocID029587 Rev 3 RM0433 Block interconnect Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Bus APB2 D2 APB1 D3 APB4 APB2 APB1 D2 APB2 APB1 D3 APB4 APB2 D2 APB1 APB2 Destination Type Comment JEXT0 SI - CC4 JEXT1 S - TIM2 TRGO JEXT2 S - TIM2 CC1 JEXT3 S - TIM3 CC4 JEXT4 S - TIM4 TRGO JEXT5 S - SYSCFG EXTI15 JEXT6 A - TIM8 CC4 JEXT7 S - TIM1 TRGO2 JEXT8 S - TIM8 TRGO JEXT9 S - TIM8 TRGO2 JEXT10 S - S - Peripheral Signal Signal TIM1 TRGO TIM1 Peripheral ADC3 Bus Domain AHB4 D3 TIM3 CC3 JEXT11 TIM3 TRGO JEXT12 S - TIM3 CC1 JEXT13 S - TIM6 TRGO JEXT14 S - TIM15 TRGO JEXT15 S - HRTIM1 hrtim_adc_ trg2 JEXT16 A - HRTIM1 hrtim_adc_ trg4 JEXT17 A - LPTIM1 OUT JEXT18 A - LPTIM2 OUT JEXT19 A - LPTIM3 OUT JEXT20 A - TIM1 OC5 comp_blk1 I - TIM1 OC3 comp_blk2 I - TIM3 OC3 comp_blk3 I - TIM3 OC4 comp_blk4 I - TIM8 OC5 comp_blk5 I - TIM15 OC1 comp_blk6 I - COMP1 / COMP2 DocID029587 Rev 3 APB4 D3 541/3178 558 Block interconnect RM0433 Table 88. Peripherals interconnect matrix details(1) (continued) Source Domain Type Comment SWT0 A - TRGO SWT1 A - ETH PPS SWT2 A - HRTIM1 hrtim_dac_ trg1 SWT3 A - TIM2 TRGO EVT0 A - TIM3 TRGO EVT1 A - AHB1 ETH PPS EVT2 A - APB2 HRTIM1 hrtim_dac_ trg1 EVT3 A - TIM2 TRGO PTP0 A - TIM3 TRGO PTP1 A - A - A - Bus Peripheral Signal Signal TIM2 TRGO TIM3 AHB1 APB2 APB1 APB1 D2 Destination APB1 APB2 HRTIM1 hrtim_dac_ trg2 PTP2 APB1 CAN TMP PTP3 Peripheral FDCAN ETH Bus Domain APB1 AHB1 D2 D2 1. Letters in the table correspond to the type of connection described in Section 13.1.2: Connection overview. 2. comp1_out and comp2_out are connected to the inputs of an OR gate. The output of this OR gate is connected to the The lptim2_in1_mux3 input. 542/3178 DocID029587 Rev 3 RM0433 13.2 Block interconnect Wakeup from low power modes The Extended interrupt and event controller module (EXTI) allows to wake up the system from Stop mode and/or a CPU from CStop mode. Wakeup events are coming from peripherals. These events are handled by the EXTI either as Configurable events (C), or as Direct events (D). See Type column in Table 89. Refer to Section 20: Extended interrupt and event controller (EXTI) for further details. Three types of peripheral output signals are connected to the EXTI input events: • The wake up signals. These signals can be generated by the peripheral without any bus interface clock, they are referred to as xxx_wkup in Table 89. Some peripherals do not have this capability. • The interrupt signals. These signals can be generated only if the peripheral bus interface clock is running. These interrupt signals are generally directly connected to the NVIC of CPU. They are referred to as xxx_it. • The signals, i.e. the pulses generated by the peripheral. Once a peripheral has generated a signal, no action (flag clearing) is required at peripheral level. Each EXTI input event has a different wakeup capability or possible target (see Target column in Table 89): • CPU wakeup (CPU): the input event can be enabled to wake up the CPU • CPU and D3 domain wakeup for autonomous Run mode (ANY): the input event can be enabled to wake up the CPU or the D3 domain only for an autonomous Run mode phase. DocID029587 Rev 3 543/3178 558 Block interconnect RM0433 Table 89. EXTI wakeup inputs(1) Source Destination Type Target Domain D3 Bus APB4 Peripheral SYSCFG Comment Signal Signal Peripheral exti0_wkup WKUP0 - exti1_wkup WKUP1 - exti2_wkup WKUP2 - exti3_wkup WKUP3 - exti4_wkup WKUP4 - exti5_wkup WKUP5 - exti6_wkup WKUP6 - exti7_wkup WKUP7 exti8_wkup WKUP8 exti9_wkup WKUP9 - exti10_wkup WKUP10 - exti11_wkup WKUP11 - exti12_wkup WKUP12 - exti13_wkup WKUP13 - exti14_wkup WKUP14 exti15_wkup WKUP15 C ANY - - EXTI - D3 AHB4 PWR pvd_avd_wkup WKUP16 C CPU - D3 APB4 RTC ALARMS WKUP17 D CPU - D3 APB4 RTC TAMPER TIMESTAMP WKUP18 C CPU D3 AHB4 RCC CSS_LSE D3 APB4 RTC WKUP WKUP19 C ANY - D3 APB4 COMP1 comp1_out WKUP20 C ANY - D3 APB4 COMP2 comp2_out WKUP21 C ANY - D2 APB1 I2C1 i2c1_wkup WKUP22 C CPU - D2 APB1 I2C2 i2c2_wkup WKUP23 D CPU - D2 APB1 I2C3 i2c3_wkup WKUP24 D CPU - D2 APB1 I2C4 i2c4_wkup WKUP25 D ANY - D2 APB2 USART1 usart1_wkup WKUP26 D CPU - D2 APB1 USART2 usart2_wkup WKUP27 D CPU - 544/3178 - DocID029587 Rev 3 RM0433 Block interconnect Table 89. EXTI wakeup inputs(1) (continued) Source Destination Type Target Comment Domain Bus Peripheral Signal Signal Peripheral D2 APB1 USART3 usart3_wkup WKUP28 D CPU - D2 APB2 USART6 usart6_wkup WKUP29 D CPU - D2 APB1 UART4 uart4_wkup WKUP30 D CPU - D2 APB1 UART5 uart5_wkup WKUP31 D CPU - D2 APB1 UART7 uart7_wkup WKUP32 D CPU - D2 APB1 UART8 uart8_wkup WKUP33 D CPU - D3 APB4 LPUART lpuart_rx_wkup WKUP34 D ANY - D3 APB4 LPUART lpuart_tx_wkup WKUP35 D ANY - D2 APB2 SPI1 spi1_wkup WKUP36 D CPU - D2 APB1 SPI2 spi2_wkup WKUP37 D CPU - D2 APB1 SPI3 spi3_wkup WKUP38 D CPU - D2 APB2 SPI4 spi4_wkup WKUP39 D CPU - D2 APB2 SPI5 spi5_wkup WKUP40 D CPU - D3 APB4 SPI6 spi6_wkup WKUP41 D ANY - D2 APB1 MDIOS mdios_wkup WKUP42 D CPU - D2 AHB1 USB1 usb1_wkup WKUP43 D CPU - D2 AHB1 USB2 usb2_wkup WKUP44 D CPU - - - NC NC WKUP45 - - - D2 APB1 LPTIM1 lptim1_wkup WKUP47 D CPU - D3 APB4 LPTIM2 lptim2_wkup WKUP48 D ANY - EXTI D3 APB4 LPTIM2 lptim2_out WKUP49 C ANY (2) D3 APB4 LPTIM3 lptim3_wkup WKUP50 D ANY - D3 APB4 LPTIM3 lptim3_out WKUP51 C ANY (2) D3 APB4 LPTIM4 lptim4_wkup WKUP52 D ANY - D3 APB4 LPTIM5 lptim5_wkup WKUP53 D ANY - D2 APB1 SWPMI swpmi_wkup WKUP54 D CPU - DocID029587 Rev 3 545/3178 558 Block interconnect RM0433 Table 89. EXTI wakeup inputs(1) (continued) Source Destination Type Target Domain D3 Bus AHB4 Peripheral Comment Signal Signal pwr_wkup1_wkup WKUP55 - pwr_wkup2_wkup WKUP56 - pwr_wkup3_wkup WKUP57 pwr_wkup4_wkup WKUP58 pwr_wkup5_wkup WKUP59 - pwr_wkup6_wkup WKUP60 - RCC rcc_it WKUP61 D CPU - I2C4 i2c4_ev_it WKUP62 D CPU (1) I2C4 i2c4_err_it WKUP63 D CPU (1) PWR Peripheral D CPU - D3 AHB4 D3 APB4 D3 APB4 LPUART1 lpuart1_it WKUP64 D CPU (1) D3 APB4 SPI6 spi6_it WKUP64 D CPU (1) bdma_ch0_it WKUP66 D CPU (1) bdma_ch1_it WKUP67 D CPU (1) bdma_ch2_it WKUP68 D CPU (1) bdma_ch3_it WKUP69 D CPU (1) bdma_ch4_it WKUP70 D CPU (1) bdma_ch5_it WKUP71 D CPU (1) bdma_ch6_it WKUP72 D CPU (1) bdma_ch7_it WKUP73 D CPU (1) CPU (1) D3 AHB4 BDMA EXTI D3 AHB4 DMAMUX2 dmamux2_it WKUP74 D3 AHB4 ADC3 adc3_it WKUP75 D CPU (1) D3 APB4 SAI4 sai4_gbl_it WKUP76 D CPU (1) D3 AHB4 HSEM hsem_int_it WKUP77 D CPU (1) - - NC NC WKUP81 - - - D1 APB3 WWDG1 wwdg1_out_rst WKUP82 C CPU (1) - - NC NC WKUP83 - - - D1 APB1 CEC cec_wkup WKUP85 C CPU - D2 AHB1 ETH eth WKUP86 C CPU - D3 AHB4 RCC hse_css_rcc_wkup WKUP87 D CPU - 1. The source peripheral needs its bus clock in order to generate the event. This is either PCLK4 or HCLK4 in D3 domain, PCLK3 in D1 domain. 2. The source peripheral signal is not connected to the NVIC. 546/3178 DocID029587 Rev 3 RM0433 Block interconnect The Extended Interrupt and Event Controller (EXTI) module event inputs able to wake up the D3 domain for autonomous Run mode have a pending request logic that can be cleared by 4 different input sources (Table 90). Refer to Section 20: Extended interrupt and event controller (EXTI) for further details. Table 90. EXTI pending requests clear inputs Source Destination Comment Domain Bus Peripheral Signal Signal dmamux2_evt6 PRC0 dmamux2_evt7 PRC1 LPTIM4 lptim4_out PRC2 LPTIM5 lptim5_out PRC3 AHB4 DMAMUX2 D3 APB4 DocID029587 Rev 3 Peripheral Bus Domain - EXTI APB4 D3 - 547/3178 558 Block interconnect 13.3 RM0433 DMA In D1 domain, the MDMA allows the memory to transfer data. It can be triggered by software or by hardware, according to the connections described in Section 13.3.1. DMA Multiplexer in D2 domain (DMAMUX1) allows to map any peripheral DMA request to any stream of the DMA1 or the DMA2. In addition to this, The DMAMUX provides two other functionalities: • It’s possible to synchronize a peripheral DMA request with a timer, with an external pin or with a DMA transfer complete of another stream. • DMA requests can be generated on a stream by the DMAMUX1 itself. This event can be triggered by a timer, by an external pin event, or by a DMA transfer complete of another stream. The number of DMA requests generated is configurable. The connections on DMAMUX1 and DMA1/DMA2 are described in Section 17: DMA request multiplexer (DMAMUX), Section 15: Direct memory access controller (DMA1, DMA2) and Section 16: Basic direct memory access controller (BDMA). DMA Multiplexer in D3 domain (DMAMUX2) has the same functionality of DMAMUX1, it is connected to the basic DMA (BDMA). The connections on DMAMUX2 and BDMA are described in Section 13.3.3: DMAMUX2, BDMA (D3 domain). Refer to Section 13.3.3: DMAMUX2, BDMA (D3 domain) and Section 16: Basic direct memory access controller (BDMA) for more details. 548/3178 DocID029587 Rev 3 RM0433 13.3.1 Block interconnect MDMA (D1 domain) Table 91. MDMA Source Destination Comment Domain Bus D2 D2 D1 AHB1 AHB1 APB3 Peripheral Signal Signal Peripheral Bus Domain dma1_tcif0 mdma_str0 DMA1 stream 0 transfer complete dma1_tcif1 mdma_str1 DMA1 stream 1 transfer complete dma1_tcif2 mdma_str2 DMA1 stream 2 transfer complete dma1_tcif3 mdma_str3 DMA1 stream 3 transfer complete dma1_tcif4 mdma_str4 DMA1 stream 4 transfer complete dma1_tcif5 mdma_str5 DMA1 stream 5 transfer complete flag dma1_tcif6 mdma_str6 DMA1 stream 6 transfer complete dma1_tcif7 mdma_str7 DMA1 stream 7 transfer complete dma2_tcif0 mdma_str8 dma2_tcif1 mdma_str9 DMA2 stream 1 transfer complete dma2_tcif2 mdma_str10 DMA2 stream 2 transfer complete dma2_tcif3 mdma_str11 DMA2 stream 3 transfer complete dma2_tcif4 mdma_str12 DMA2 stream 4 transfer complete dma2_tcif5 mdma_str13 DMA2 stream 5 transfer complete dma2_tcif6 mdma_str14 DMA2 stream 6 transfer complete dma2_tcif7 mdma_str15 DMA2 stream 7 transfer complete ltdc_li_it mdma_str16 LTDC line interrupt DMA1 MDMA DMA2 LTDC DocID029587 Rev 3 AXI D1 DMA2 stream 0 transfer complete 549/3178 558 Block interconnect RM0433 Table 91. MDMA (continued) Source Destination Comment Domain Bus D1 AHB3 Peripheral JPEG Signal Signal Peripheral Bus Domain jpeg_ift_trg mdma_str17 JPEG input FIFO threshold jpeg_ifnt_trg mdma_str18 JPEG input FIFO not full jpeg_oft_trg mdma_str19 JPEG output FIFO threshold jpeg_ofne_trg mdma_str20 JPEG output FIFO not empty jpeg_oec_trg JPEG end of conversion mdma_str21 quadspi_ft_trg mdma_str22 D1 AHB3 QUADSPI quadspi_tc_trg mdma_str23 QUADSPI FIFO threshold MDMA dma2d_clut_trg mdma_str24 D1 D1 550/3178 AHB3 AHB3 DMA2D SDMMC1 AXI D1 QUADSPI transfer complete DMA2D CLUT transfer complete dma2d_tc_trg mdma_str25 DMA2D transfer complete dma2d_tw_trg mdma_str26 DMA2D transfer watermark sdmmc1_ dataend_trg mdma_str29 DocID029587 Rev 3 End of data RM0433 13.3.2 Block interconnect DMAMUX1, DMA1 and DMA2 (D2 domain) Table 92. DMAMUX1, DMA1 and DMA2 connections(1) Source Destination Comment Domain Bus Peripheral Signal Signal Peripheral Bus Domain dmamux1_req_in0 dmamux1_req_in1 dmamux1_req_in2 D3 AHB4 dmamux1 internal (Request generator) dmamux1_req_in3 NC NC NC NC D2 AHB1 ADC1 adc1_dma dmamux1_req_in8 D2 AHB1 ADC2 adc2_dma dmamux1_req_in9 tim1_ch1_dma dmamux1_req_in10 tim1_ch2_dma dmamux1_req_in11 tim1_ch3_dma dmamux1_req_in12 tim1_ch4_dma dmamux1_req_in13 tim1_up_dma dmamux1_req_in14 tim1_trig_dma dmamux1_req_in15 tim1_com_dma dmamux1_req_in16 tim2_ch1_dma dmamux1_req_in17 tim2_ch2_dma dmamux1_req_in18 tim2_ch3_dma dmamux1_req_in19 tim2_ch4_dma dmamux1_req_in20 tim2_up_dma dmamux1_req_in21 tim3_ch1_dma dmamux1_req_in22 tim3_ch2_dma dmamux1_req_in23 tim3_ch3_dma dmamux1_req_in24 tim3_ch4_dma dmamux1_req_in25 tim3_up_dma dmamux1_req_in26 tim3_trig_dma dmamux1_req_in27 tim4_ch1_dma dmamux1_req_in28 tim4_ch2_dma dmamux1_req_in29 tim4_ch3_dma dmamux1_req_in30 tim4_up_dma dmamux1_req_in31 D2 D2 D2 D2 APB2 APB1 APB1 APB1 TIM1 TIM2 TIM3 TIM4 DocID029587 Rev 3 DMAMUX1 AHB1 D2 Requests 551/3178 558 Block interconnect RM0433 Table 92. DMAMUX1, DMA1 and DMA2 connections(1) (continued) Source Destination Comment Domain Bus Peripheral D2 APB1 I2C1 D2 APB1 I2C2 D2 APB2 SPI1 D2 APB1 SPI2 D2 APB2 USART1 D2 APB1 USART2 D2 APB1 USART3 D2 - D1 APB2 - APB1 TIM8 NC TIM3 D2 APB1 SPI3 D1 APB1 UART4 552/3178 Signal Signal i2c1_rx_dma dmamux1_req_in32 i2c1_tx_dma dmamux1_req_in33 i2c2_rx_dma dmamux1_req_in34 i2c2_tx_dma dmamux1_req_in35 spi1_rx_dma dmamux1_req_in36 spi1_tx_dma dmamux1_req_in37 spi2_rx_dma dmamux1_req_in38 spi2_tx_dma dmamux1_req_in39 usart1_rx_dma dmamux1_req_in40 usart1_tx_dma dmamux1_req_in41 usart2_rx_dma dmamux1_req_in42 usart2_tx_dma dmamux1_req_in43 usart3_rx_dma dmamux1_req_in44 usart3_tx_dma dmamux1_req_in45 tim8_ch1_dma dmamux1_req_in46 tim8_ch2_dma dmamux1_req_in47 tim8_ch3_dma dmamux1_req_in48 tim8_ch4_dma dmamux1_req_in49 tim8_up_dma dmamux1_req_in50 tim8_trig_dma dmamux1_req_in51 tim8_com_dma dmamux1_req_in52 NC NC tim5_ch1_dma dmamux1_req_in54 tim5_ch2_dma dmamux1_req_in55 tim5_ch3_dma dmamux1_req_in56 tim5_ch4_dma dmamux1_req_in57 tim5_up_dma dmamux1_req_in58 tim5_trig_dma dmamux1_req_in59 spi3_rx_dma dmamux1_req_in60 spi3_tx_dma dmamux1_req_in61 uart4_rx_dma dmamux1_req_in62 uart4_tx_dma dmamux1_req_in63 DocID029587 Rev 3 Peripheral Bus DMAMUX1 AHB1 Domain D2 Requests RM0433 Block interconnect Table 92. DMAMUX1, DMA1 and DMA2 connections(1) (continued) Source Destination Comment Domain Bus Peripheral Signal Signal uart5_rx_dma dmamux1_req_in64 uart5_tx_dma dmamux1_req_in65 D1 APB1 UART5 D2 APB1 DAC1 dac_ch1_dma dmamux1_req_in66 D2 APB1 DAC2 dac_ch2_dma dmamux1_req_in67 D2 APB1 TIM6 tim6_up_dma dmamux1_req_in68 D2 APB1 TIM7 tim7_up_dma dmamux1_req_in69 D2 APB2 USART6 usart6_rx_dma dmamux1_req_in70 usart6_tx_dma dmamux1_req_in71 D2 APB1 I2C3 i2c3_rx_dma dmamux1_req_in72 i2c3_tx_dma dmamux1_req_in73 D2 AHB2 DCMI dcmi_dma dmamux1_req_in74 D2 AHB2 CRYP cryp_in_dma dmamux1_req_in75 cryp_out_dma dmamux1_req_in76 D2 AHB2 HASH hash_in_dma dmamux1_req_in77 D2 APB1 UART7 uart7_rx_dma dmamux1_req_in78 uart7_tx_dma dmamux1_req_in79 D2 APB1 UART8 uart8_rx_dma dmamux1_req_in80 uart8_tx_dma dmamux1_req_in81 D2 APB2 SPI4 spi4_rx_dma dmamux1_req_in82 spi4_tx_dma dmamux1_req_in83 D2 APB2 SPI5 spi5_rx_dma dmamux1_req_in84 spi5_tx_dma dmamux1_req_in85 D2 APB2 SAI1 sai1_a_dma dmamux1_req_in86 sai1_b_dma dmamux1_req_in87 D2 APB2 SAI2 sai2_a_dma dmamux1_req_in88 sai2_b_dma dmamux1_req_in89 D2 APB1 SWPMI swpmi_rx_dma dmamux1_req_in90 swpmi_tx_dma dmamux1_req_in91 D2 APB1 SPDIFRX spdifrx_dt_dma dmamux1_req_in92 spdifrx_cs_dma dmamux1_req_in93 DocID029587 Rev 3 Peripheral Bus DMAMUX1 AHB1 Domain D2 Requests 553/3178 558 Block interconnect RM0433 Table 92. DMAMUX1, DMA1 and DMA2 connections(1) (continued) Source Destination Comment Domain Bus Peripheral D2 D2 D2 APB2 HRTIM1 APB2 DFSDM1 APB2 TIM15 D2 APB2 TIM16 D2 APB2 TIM17 D2 APB2 SAI3 D3 AHB4 ADC3 D2 AHB1 DMAMUX1 Signal Signal hrtim_dma1 dmamux1_req_in94 hrtim_dma2 dmamux1_req_in95 hrtim_dma3 dmamux1_req_in96 hrtim_dma4 dmamux1_req_in97 hrtim_dma5 dmamux1_req_in98 hrtim_dma6 dmamux1_req_in99 dfsdm1_dma0 dmamux1_req_in100 dfsdm1_dma1 dmamux1_req_in101 dfsdm1_dma2 dmamux1_req_in102 dfsdm1_dma3 dmamux1_req_in103 Bus tim15_ch1_dma dmamux1_req_in104 DMAMUX1 AHB1 tim15_up_dma dmamux1_req_in105 tim15_trig_dma dmamux1_req_in106 tim15_com_dma dmamux1_req_in107 tim16_ch1_dma dmamux1_req_in108 tim16_up_dma dmamux1_req_in109 tim17_ch1_mda dmamux1_req_in110 tim17_up_dma dmamux1_req_in111 sai3_a_dma dmamux1_req_in112 sai3_b_dma dmamux1_req_in113 adc3_dma dmamux1_req_in114 dmamux1_evt0 dmamux1_gen0 dmamux1_evt1 dmamux1_gen1 dmamux1_evt2 dmamux1_gen2 D2 APB1 LPTIM1 lptim1_out dmamux1_gen3 D2 APB1 LPTIM2 lptim2_out dmamux1_gen4 D2 APB1 LPTIM3 lptim3_out dmamux1_gen5 D3 APB4 EXTI exti_exti0_it dmamux1_gen6 D2 APB1 TIM12 tim12_trgo dmamux1_gen7 554/3178 Peripheral DocID029587 Rev 3 DMAMUX1 AHB1 Domain D2 Requests D2 Request generation RM0433 Block interconnect Table 92. DMAMUX1, DMA1 and DMA2 connections(1) (continued) Source Destination Comment Domain Bus Peripheral D2 Signal dmamux1_evt0 dmamux1_trg0 dmamux1_evt1 dmamux1_trg1 dmamux1_evt2 dmamux1_trg2 D2 APB1 LPTIM1 lptim1_out dmamux1_trg3 D2 APB1 LPTIM2 lptim2_out dmamux1_trg4 D2 APB1 LPTIM3 lptim3_out dmamux1_trg5 D3 APB4 EXTI exti_exti0_it dmamux1_trg6 D2 APB1 TIM12 tim12_trgo dmamux1_trg7 dmamux1_req_out0 dma1_str0 dmamux1_req_out1 dma1_str1 dmamux1_req_out2 dma1_str2 dmamux1_req_out3 dma1_str3 dmamux1_req_out4 dma1_str4 dmamux1_req_out5 dma1_str5 dmamux1_req_out6 dma1_str6 dmamux1_req_out7 dma1_str7 dmamux1_req_out8 dma2_str0 dmamux1_req_out9 dma2_str1 dmamux1_req_out10 dma2_str2 dmamux1_req_out11 dma2_str3 dmamux1_req_out12 dma2_str4 dmamux1_req_out13 dma2_str5 dmamux1_req_out14 dma2_str6 dmamux1_req_out15 dma2_str7 D2 1. AHB1 DMAMUX1 Signal AHB1 DMAMUX1 Peripheral Bus DMAMUX1 AHB1 DMA1 AHB1 Domain D2 Triggers D2 Requests out DMA2 AHB1 D2 The “-” symbol in grayed cells means no interconnect. DocID029587 Rev 3 555/3178 558 Block interconnect 13.3.3 RM0433 DMAMUX2, BDMA (D3 domain) Table 93. DMAMUX2 and BDMA connections Source Destination Comment Domain Bus Peripheral Signal Signal Peripheral Bus Domain dmamux2_req_in0 dmamux2_req_in1 dmamux2_req_in2 D3 AHB4 dmamux2 internal (Request generator) dmamux2_req_in3 NC NC NC NC D3 APB4 LPUART D3 APB4 SPI6 D2 APB1 I2C4 D3 APB4 SAI4 D3 APB4 ADC3 556/3178 dma_rx_lpuart dmamux2_req_in8 dma_tx_lpuart dmamux2_req_in9 dma_rx_spi6 dmamux2_req_in10 dma_tx_spi6 dmamux2_req_in11 dma_rx_i2c4 dmamux2_req_in12 dma_tx_i2c4 dmamux2_req_in13 dma_a_sai4 dmamux2_req_in14 dma_b_sai4 dmamux2_req_in15 dma_adc3 dmamux2_req_in16 DocID029587 Rev 3 DMAMUX2 AHB4 D3 Requests RM0433 Block interconnect Table 93. DMAMUX2 and BDMA connections (continued) Source Destination Comment Domain Bus Peripheral D3 D3 AHB4 DMAMUX2 APB4 EXTI Signal Signal dmamux2_evt0 dmamux2_gen0 dmamux2_evt1 dmamux2_gen1 dmamux2_evt2 dmamux2_gen2 dmamux2_evt3 dmamux2_gen3 dmamux2_evt4 dmamux2_gen4 dmamux2_evt5 dmamux2_gen5 dmamux2_evt6 dmamux2_gen6 it_exti_rx_lpuart dmamux2_gen7 it_exti_tx_lpuart dmamux2_gen8 it_exti_wkup_lptim2 dmamux2_gen9 it_exti_out_lptim2 dmamux2_gen10 it_exti_wkup_lptim3 dmamux2_gen11 it_exti_out_lptim3 dmamux2_gen12 it_exti_wkup_lptim4 dmamux2_gen13 it_exti_wkup_lptim5 dmamux2_gen14 it_exti_wkup_i2c4 dmamux2_gen15 it_exti_wkup_spi6 dmamux2_gen16 it_exti_out_comp1 dmamux2_gen17 it_exti_out_comp2 dmamux2_gen18 it_exti_wkup_rtc dmamux2_gen19 it_exti_exti0_syscfg dmamux2_gen20 it_exti_exti2_syscfg dmamux2_gen21 D3 APB4 I2C4 it_evt_i2c4 dmamux2_gen22 D3 APB4 SPI6 it_spi6 dmamux2_gen23 D3 APB4 LPUART it_tx_lpuart1 dmamux2_gen24 it_rx_lpuart1 dmamux2_gen25 D3 AHB4 ADC3 it_adc3 dmamux2_gen26 out_awd1_adc3 dmamux2_gen27 D3 AHB4 BDMA it_ch0_bdma dmamux2_gen28 it_ch1_bdma dmamux2_gen29 DocID029587 Rev 3 Peripheral Bus Domain DMAMUX2 AHB4 D3 Request generation 557/3178 558 Block interconnect RM0433 Table 93. DMAMUX2 and BDMA connections (continued) Source Destination Comment Domain Bus Peripheral D3 D3 D3 AHB4 DMAMUX2 APB4 EXTI AHB4 DMAMUX2 558/3178 Signal Signal dmamux2_evt0 dmamux2_trg0 dmamux2_evt1 dmamux2_trg1 dmamux2_evt2 dmamux2_trg2 dmamux2_evt3 dmamux2_trg3 dmamux2_evt4 dmamux2_trg4 dmamux2_evt5 dmamux2_trg5 it_exti_tx_lpuart1 dmamux2_trg6 it_exti_rx_lpuart1 dmamux2_trg7 it_exti_out_lptim2 dmamux2_trg8 it_exti_out_lptim3 dmamux2_trg9 it_exti_wkup_i2c4 dmamux2_trg10 it_exti_wkup_spi6 dmamux2_trg11 it_exti_out_comp1 dmamux2_trg12 it_exti_wkup_rtc dmamux2_trg13 it_exti_exti0_syscfg dmamux2_trg14 it_exti_exti2_syscfg dmamux2_trg15 dmamux1_req_out0 bdma_ch0 dmamux1_req_out1 bdma_ch1 dmamux1_req_out2 bdma_ch2 dmamux1_req_out3 bdma_ch3 dmamux1_req_out4 bdma_ch4 dmamux1_req_out5 bdma_ch5 dmamux1_req_out6 bdma_ch6 dmamux1_req_out7 bdma_ch7 DocID029587 Rev 3 Peripheral Bus Domain DMAMUX2 AHB4 BDMA AHB4 D3 Triggers D3 Requests out RM0433 MDMA controller (MDMA) 14 MDMA controller (MDMA) 14.1 MDMA introduction The master direct memory access (MDMA) is used in order to provide high-speed data transfer between memory and memory or between peripherals and memory. Data can be quickly moved by the MDMA without any CPU action. This keeps the CPU resources free for other operations. The MDMA controller provides a master AXI interface for main memory and peripheral registers access (system access port) and a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). The MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2). It offers up to 16 channels, each dedicated to manage memory access requests from one of the DMA stream memory buffer or other peripherals (w/ integrated FIFO). 14.2 MDMA main features • AXI/AHB master bus architecture, one dedicated to main memory/peripheral accesses and one dedicated to Cortex-M7 AHBS port (only for TCM accesses). • 16 channels • Up to 32 hardware trigger sources • Each channel request can be selected among any of the request sources. This selection is software-configurable and allows several peripherals to initiate DMA requests. The trigger selection can be automatically changed at the end of one block transfer. • All the channels are identical and can be connected either to a standard DMA or a peripheral request (acknowledge by data read/write) system • Each channel also supports software trigger • One 256-level memory buffer, split in two 128-level first-in, first-out (FIFO), that will be used to store temporary the data to be transferred (in burst or single transfer mode), for 1 or 2 consecutive buffers. The FIFO will store the data that will be transferred during the current channel block transfer (up to the block transfer size). The 2nd FIFO can be used for the next buffer to be transferred, either for the same channel or for the next channel transfer. • The priorities between the DMA channels are software-programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (channel 0 has priority over channel 1, etc.) • Independent source and destination transfer width (byte, half-word, word, doubleword): when the data widths of the source and destination are not equal, the MDMA can pack/unpack the necessary data to optimize the bandwidth. • The size and address increment for both source and destination can be independently selected. DocID029587 Rev 3 559/3178 587 MDMA controller (MDMA) Note: 560/3178 RM0433 Based on this separation, some more advanced packing/unpacking operations are available at software level. As an example, 2 x 16-bit data blocks can be interleaved together using two MDMA channels, in the destination memory, by simply programming the 2 channels with an increment step of 4 bytes and a data size of 16-bit + a start address shifted by 2 between the 2 channels. • Incrementing, decrementing or non incrementing/fixed addressing for source and destination • Data packing/unpacking is always done respecting the little endian convention: lower address in a data entity (double word, word or half word) contains always the lowest significant byte. This is independent of the address increment/decrement mode of both source and destination. • Supports incremental burst transfers. The size of the burst is software-configurable, up to 128 bytes. For larger data sizes the burst length is limited, as to respect the maximum 128 bytes data burst size (e.g. 16x64-bit or 32x32-bit). • For the TCM memory accesses, the burst access is only allowed when the increment and data size are identical and lower than or equal to 32-bit. • 5 event flags (MDMA Channel Transfer Complete, MDMA Block Transfer complete, MDMA Block Repeat Transfer Complete, MDMA buffer transfer Complete, MDMA Transfer Error) are available and can generate interrupts. DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.3 MDMA functional description 14.3.1 MDMA block diagram Figure 68 shows the block diagram of the MDMA. Figure 68. MDMA block diagram PGPDBVWU ),)2 $UELWHU ),)2 PGPDBVWU ELW7&0 PDVWHU$+% 5HDG ZULWH UHTXHVWV 76(/ 76(/ 6ODYH$+% SURJUDPPLQJ SRUW ELW$;,PDVWHU V\VWHPEXV 5HDG ZULWH UHTXHVWV PGPDBLW 3URJUDPPLQJ ,QWHUIDFH PGPDBKFON 06Y9 14.3.2 MDMA internal signals Table 94 shows the internal MDMA signals. Table 94. MDMA internal input/output signals Signal name Signal type Description mdma_hclk Digital input MDMA AHB clock mdma_it Digital output MDMA interrupt mdma_str[0:31] Digital input MDMA stream request DocID029587 Rev 3 561/3178 587 MDMA controller (MDMA) 14.3.3 RM0433 MDMA overview The MDMA controller performs a direct memory transfer: as an AXI/AHB master, it can take the control of the AXI/AHB bus matrix to initiate AXI/AHB transactions. It can carry out the following transactions: • memory-to-memory (software triggered) • peripheral-to-memory • memory-to-peripheral For the last two transaction types, the memory can also be replaced by a memory-mapped peripheral, which has no control over the MDMA flow. When these types of transaction are used and the request is coming from a standard DMA (DMA1 or DMA2), the peripheral register access is replaced by a memory access to the memory buffer used by this DMA. Note: Non-incrementing/decrementing mode will not be used for memory accesses. The source and destination are simply defined by the address (peripherals being memory mapped also). The AHB slave port is used to program the MDMA controller (it supports 8/16/32-bit accesses). The size of the data array to be transferred for a single request will be one of the following: 1. The buffer transfer size 2. The block size 3. Repeated block 4. Complete channel data (until the linked list pointer for the channel is null) The choice of the size is done through the TRGM[1:0] (Trigger mode) selection field. The user must choose one of them based on the data array size available (usually in the DMA1/2 memory buffer) and the “real time” requirements for other MDMA channels (knowing that a buffer transfer is the minimum data aggregate to be transferred by the MDMA without doing a new arbitration between MDMA channel requests). For each channel, there are three key data array sizes: 1. Burst size: this is the length of the data transfer which can be performed in burst mode. This burst length defines the maximum transfer length which cannot be interrupted at bus arbitration level and can block other masters from accessing the bus) 2. Buffer transfer size: this is the length of the data array to be transferred, on a channel, before checking for MDMA requests on other channels. This is the data array transfer lengths which cannot be interrupted at MDMA level (from other channel requests). 3. 562/3178 Block size: this value has two meanings which can be used together: a) main: this is length of the data block which is described in a block structure of the MDMA linked list (corresponds to one entry in the linked list) b) selectable: when TRGM[1:0] equals 01, this is the length of the data array which is transferred on a single MDMA request activation (for the respective channel) DocID029587 Rev 3 RM0433 14.3.4 MDMA controller (MDMA) MDMA channel Each of the DMA controller channel provides a unidirectional transfer link between a source and a destination. Each channel can perform: • Single block transfer: one block is transferred. At the end of the block, the DMA channel is disabled and an End of Channel Transfer interrupt is generated. • Repeated block transfer: a number of blocks is transferred before disabling the channel • Linked list transfer: when the transfer of the current data block (or last block in a repeat) is completed, a new block control structure is loaded from memory and a new block transfer is started. The minimum amount of data to be transferred for each request (buffer size, up to 128bytes) is programmable. The total amount of data in a block, is programmable up to 64 Kbytes. This value is decremented after each transfer. When this counter reaches 0, the end of the block is reached and an action is taken based on the repeat counter (for repeated block transfer) and/or linked list structure value. Note: If the block length is not a multiple of the buffer length, the last buffer transfer in the block will be shorter, covering the remaining bytes to be transferred in the current block. If the link structure address points to a valid memory address, the MDMA will reload the whole channel descriptor structure register contents from memory at this address. Then, a new block transfer will then be executed (on the next MDMA channel request) based on this information. If the link structure address is 0x0, at the end of the current/repeated block transfer, the MDMA channel will be disabled and the end of channel transfer interrupt will be generated. 14.3.5 Source, destination and transfer modes Both the source and destination transfers can address peripherals and memories in the entire 4-Gbyte area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF. The source/destination addresses can be fixed (e.g. FIFO/single data register peripherals) or incremented/decremented. The transfer can be done in single access or in burst mode (programmable). 14.3.6 Pointer update The source and destination memory pointers can optionally be automatically postincremented/decremented or kept constant after each transfer depending on the SINC[1:0] and DINC[1:0] bits in the MDMA_CxCR register. Disabling the increment mode is useful when the peripheral source or destination data are accessed through a single register/FIFO mode. If the increment/decrement mode is enabled, the address of the next data transfer will be the address of the previous one incremented/decrement by 1, 2, 4 or 8 depending on the increment size programmed in the SINCOS[1:0] or DINCOS[1:0] bits in the MDMA_CxCR register. In order to optimize the packing operation, the increment offset size and the data size are programmable independently. DocID029587 Rev 3 563/3178 587 MDMA controller (MDMA) 14.3.7 RM0433 MDMA buffer transfer This is the minimum logical amount of data (up to 128 bytes) which is transferred on an MDMA request event, on one channel. An MDMA buffer transfer consists of a sequence of a given number of data transfers (done as single or burst data transfers). The number of data items to be transferred and their width (8-bit, 16-bit, 32-bit or 64-bit) are software programmable. The length of the burst used for data transfers is also programmable, independently. After an event requiring a data array to be transferred, the DMA/peripheral sends a request signal to the MDMA controller. The MDMA controller serves the request depending on the channel priorities. The request is acknowledged by writing the mask data value to the address given mask address, when these registers are set. If the mask address register is not set (0x00 value), the request can be reset by simply reading/writing the data to the peripheral. In this case, if the request is done by a destination peripheral, the write must be set as non bufferable, in order to avoid a false new MDMA request. The total amount of data to be transferred, on the current channel, following a MDMA request, is determined by the TRGM[1:0] field. If TRGM[1:0] equals 00, a single buffer will be transferred, then the MDMA will wait for another request on the same channel. Note: In this case, the hardware request for the currently active channel (data in the FIFO) will not be considered again until the end of the write phase for this channel. In this case, even if the channel would still be active at the end of the read phase, another channel (even with lower priority) could start the read phase. Because of this, lower priority channels can be interleaved with current channel transfer. If TRGM[1:0] is different from 00 (multiple buffers need to be transferred), the mdma_strx for the current channel remains active (internally memorized) until the whole transfer defined by TRGM (block, repeated block or whole channel/linked list data) is completed. However, after transferring an individual buffer, the MDMA will enter in a new arbitration phase (between new external requests and internally memorized ones). If no other higher priority, channel request is active, a new buffer transfer will be started for the same channel. Note: 564/3178 When TRGM[1:0] is different from 00, a larger array of data will be transferred for a single request. But, as the channel arbitration is done after each buffer transfer, no higher level MDMA requests would be blocked for the more than a buffer transfer period, on any lower priority channel. DocID029587 Rev 3 RM0433 14.3.8 MDMA controller (MDMA) Request arbitration An arbiter manages the MDMA channel requests based on their priority. When MDMA is idle and after the end of each buffer transfer, all MDMA requests (hardware or software) are checked for all enabled channels. Priorities are managed in two stages: • • 14.3.9 Software: each stream priority can be configured in the MDMA_CxCR register. There are four levels: – Very high priority – High priority – Medium priority – Low priority Hardware: at hardware level, the channel priority is fixed. If two requests have the same software priority level, the channel with the lower number takes priority over the stream with the higher number. For example, Channel 2 takes priority over Channel 4 when they have the same software priority level. FIFO A FIFO structure is used to temporarily store data coming from the source before writing them to the destination. There is a central FIFO structure which is used for all channels. In order to maximize data bandwidth and bus usage, the following mechanisms are used, allowing multiple read/write operation to be executed in parallel. • During a buffer transfer, as soon as the FIFO contains enough data for a destination burst transfer, the write operation will start. • When the complete data for a buffer transfer has been read into the FIFO, the arbitration procedure will be started. Following that, the next buffer data to be transferred can be read to the FIFO. When an active channel is disabled due to an error, during a buffer transfer, the remaining data in the internal FIFO will be discarded. DocID029587 Rev 3 565/3178 587 MDMA controller (MDMA) 14.3.10 RM0433 Block transfer A block is a “contiguous” array of data, up to 64 Kbytes, which is transferred by successive buffer transfers. Each block of data is defined by the start address and the block length. When a block transfer is completed, one of the following three actions can be executed: 14.3.11 • The block is part of a repeated block transfer: the block length is reloaded and new block start address is computed (based on the information in the MDMA_CxBRUR register) • It is a single block or the last block in a repeated block transfer: the next block information is loaded from the memory (using the linked list address information, from the MDMA_CxLAR) • It is the last block which needs to be transferred for the current MDMA channel (MDMA_CxLAR = 0): the channel is disabled and no further MDMA requests will be accepted for this channel Block repeat mode The block repeat mode allows to repeat a block transfer, with different start addresses for source and destination. When the repeat block mode is active (repeat counter non 0), at the end of the current block transfer, the block parameters will be updated (the BNDT value reloaded and SAR/DAR values updated according to BRSUM/BRDUM configuration), and the repeat counter decremented by 1. When the repeat block counter reaches 0, this last block will be treated as a single block transfer. 14.3.12 Linked list mode The Linked list mode allows to load a new MDMA configuration (CxTCR, CxBNDTR, CxSAR, CxDAR, CxBRUR, CxLAR, CxTBR, CxMAR and CxMDR registers), from the address given in the CxLAR register. This address must address a memory mapped on the AXI system bus. Following this operation, the channel is ready to accept new requests, as defined in the block/repeated block modes above, or continue the transfer if TRGM[1:0] equals 11. The trigger source can be automatically changed, when loading the CxTBR value. The TRGM and SWRM values must not be changed when TRGM[1:0] equals 11. 14.3.13 MDMA transfer completion Different events can generate an end of transfer by setting the CTCIF bit in the status register (MDMA_CxISR): 566/3178 • The MDMA_CxBNDTR counter has reached zero, the Block Repeat Counter is 0 and the Link list pointer address is 0 • The channel is disabled before the end of transfer (by clearing the EN bit in the MDMA_CxCR register) and all the remaining data have been transferred from the FIFO to the destination DocID029587 Rev 3 RM0433 14.3.14 MDMA controller (MDMA) MDMA transfer suspension At any time, a MDMA transfer can be suspended in order to be to be restarted later on or to be definitively disabled before the end of the MDMA transfer. There are two cases: • The channel is disabled, with no later-on restart from the point where it was stopped. There is no particular action to do, besides clearing the EN bit in the MDMA_CxCR register to disable the channel. The stream can take time to be disabled (on going buffer transfer is completed first). The transfer complete interrupt flag is set in order to indicate the end of transfer. The value of the EN bit in MDMA_CxCR is now 0 to confirm the channel interruption. The MDMA_CxNDTR register contains the number of remaining data items at the moment when the channel was stopped so that the software can determine how many data items have been transferred before the channel was interrupted. • The channel is suspended before the number of remaining bytes to be transferred in the MDMA_CxBNDTR register reaches 0. The aim is to restart the transfer later by reenabling the channel. The channel transfer complete interrupt flag CTCIF is set in order to indicate the end of transfer. If the MDMA_CxBNDTR, SAR and DAR registers are not modified by software, the transfer will continue when the channel is re-enabled. CTCIF must also be reset before restarting the channel. Note: If the completed buffer is the last of the block, the configuration registers are also updated before disabling the channel, in order to be correctly prepared for a soft restart. Note: Before reprogramming the channel, software must wait the CTCIF register is set, in order to guarantee that any ongoing operation has been completed. 14.3.15 Error management The MDMA controller can detect the following errors: The transfer error interrupt flag (TEIF) is set when: 14.4 • A bus error occurs during a MDMA read or a write access • The address alignment does not correspond to the data size • The block size is not a multiple of the data size (for source and/or destination): this error is activated on the last transfer and the error address points to the last transfer (which cannot be done) MDMA interrupts For each MDMA channel, an interrupt can be produced on the following events: • Channel Transfer Completed • Block-Transfer Completed • Block-Transfer Repeat Completed • buffer Transfer Completed • Transfer Error Separate interrupt enable control bits are available for flexibility as shown in Table 95. DocID029587 Rev 3 567/3178 587 MDMA controller (MDMA) RM0433 Table 95. MDMA interrupt requests Interrupt event Event flag Enable control bit Channel Transfer Completed CTCIF CTCIE Block-Transfer Repeat completed BTRIF BTRIE Block-Transfer completed BTIF BTIE buffer Transfer Completed TCIF TCIE Transfer Error TEIF TEIE Note: Before setting an Enable control bit to 1, the corresponding event flag should be cleared, otherwise an interrupt might be immediately generated, if the bit is already set. Note: When at least one interrupt flag and the respective enable control bit are set, the channel interrupt bit is set in the GISR. The Interrupt output is also activated. This will generate an interrupt if the respective interrupt channel is enabled in the NVIC. 14.5 MDMA registers The MDMA registers can be accessed in word/half-word or byte format. 14.5.1 MDMA Global Interrupt/Status Register (MDMA_GISR0) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIF15 GIF14 GIF13 GIF12 GIF11 GIF10 GIF9 GIF8 GIF7 GIF6 GIF5 GIF4 GIF3 GIF2 GIF1 GIF0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, read as 0, for all unused channels. Bits 15:0 GIFx: Channel x global interrupt flag (x=0..15) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIF, BTIF, BRTIF, TEIF) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx) 0: No interrupt generated by channel x 1: Interrupt generated by channel x 568/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.5.2 MDMA channel x interrupt/status register (MDMA_CxISR) (x = 0..15) Address offset: 0x40 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRQA r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TCIF BTIF BRTIF CTCIF TEIF r r r r r r r r r r r r r r r r Bits 31:17 Reserved, must be kept at reset value. Bit 16 CRQA: Channel x ReQuest Active flag This bit is set by software writing 1 to the SWRQx bit in the MDMA_CxCR register, in order to request a MDMA transfer, and the channel x is enabled. It is also set by hardware when the channel request become active and the channel is enabled. The hardware request memorized until it is served. It is cleared by hardware, when the Channel x Request is completed (after the source write phase of the last buffer transfer due for the current request). 0: The MDMA transfer mdma_strx is inactive for channel x. 1: The MDMA transfer mdma_strx is active for channel x This bit is also reset by hardware when the channel is disabled (in case of transfer error or when reaching the end of the channel data transfer - repeat block = 0 and linked list pointer null - or by software programming the channel enable bit to 0 before that). Bits 15:5 Reserved, must be kept at reset value. Bit 4 TCIF: Channel x buffer transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the MDMA_IFCRy register. 0: No buffer transfer complete event on channel x 1: A buffer transfer complete event occurred on channel x TC is set when a single buffer was transferred. It will be activated on each channel transfer request. This can be used as a debug feature (without interrupt), indicating that (at least) an MDMA buffer transfer had been generated since the last flag reset. Bit 3 BTIF: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the MDMA_IFCRy register. 0: No block transfer complete event on channel x 1: A block transfer complete event occurred on channel x Bit 2 BRTIF: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the MDMA_IFCRy register. 0: No block repeat transfer complete event on channel x 1: A block repeat transfer complete event occurred on channel x DocID029587 Rev 3 569/3178 587 MDMA controller (MDMA) RM0433 Bit 1 CTCIF: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the MDMA_IFCRy register. 0: No channel transfer complete event on channel x 1: A channel transfer complete event occurred on channel x CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0. Bit 0 TEIF: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the MDMA_IFCRy register. 0: No transfer error on stream x 1: A transfer error occurred on stream x 14.5.3 MDMA channel x interrupt flag clear register (MDMA_CxIFCR) (x = 0..15) Address offset: 0x44 + 0x40 × channel number Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLTCIF CBTIF CBRTIF CCTCIF CTEIF r r r r r r r r r r r w w w w w Bits 31:5 Reserved, must be kept at reset value. Bit 4 CLTCIF: CLear buffer Transfer Complete Interrupt Flag for channel x Writing 1 into this bit clears TCIF in the MDMA_ISRy register Bit 3 CBTIF: Channel x Clear block transfer complete interrupt flag Writing 1 into this bit clears BTIF in the MDMA_ISRy register Bit 2 CBRTIF: Channel x clear block repeat transfer complete interrupt flag Writing 1 into this bit clears BRTIF in the MDMA_ISRy register Bit 1 CCTCIF: Clear Channel transfer complete interrupt flag for channel x Writing 1 into this bit clears CTCIF in the MDMA_ISRy register Bit 0 CTEIF: Channel x clear transfer error interrupt flag Writing 1 into this bit clears TEIF in the MDMA_ISRy register 570/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.5.4 MDMA Channel x error status register (MDMA_CxESR) (x = 0..15) Address offset: 0x48 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BSE ASE TEMD TELD TED r r r r r r r r TEA[6:0] r r r r Bits 31:12 Reserved, must be kept at reset value. Bit 11 BSE: Block Size Error These bit is set by hardware, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIF bit in the MDMA_IFCRy register. 0: No block size error. 1: Programmed block size is not an integer multiple of the data size. Bit 10 ASR: Address/Size Error These bit is set by hardware, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIF bit in the MDMA_IFCRy register. 0: No address/size error. 1: Programmed address is not coherent with the data size. Bit 9 TEMD: Transfer Error Mask Data These bit is set by hardware, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIF bit in the MDMA_IFCRy register. 0: No mask write access error. 1: The last transfer error on the channel was a related to a write of the Mask Data. Bit 8 TELD: Transfer Error Link Data These bit is set by hardware, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIF bit in the MDMA_IFCRy register. 0: No link data read access error. 1: The last transfer error on the channel was a related to a read of the Link Data structure. Bit 7 TED: Transfer Error Direction These bit is set and cleared by hardware, in case of an MDMA data transfer error. 0: The last transfer error on the channel was a related to a read access. 1: The last transfer error on the channel was a related to a write access. DocID029587 Rev 3 571/3178 587 MDMA controller (MDMA) RM0433 Bits 6:0 TEA[6:0]: Transfer Error Address These bits are set and cleared by hardware, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It can be used by software to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesn’t reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error. 572/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.5.5 MDMA channel x control register (MDMA_CxCR) (x = 0..15) This register is used to control the concerned channel. Address offset: 0x4C + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWRQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. WEX HEX BEX Res. Res. Res. Res. TCIE BTIE BRTIE CTCIE TEIE EN rw rw rw rw rw rw rw rw rw w PL[1:0] rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 SWRQ: Software Request Writing 1 into this bit sets the CRQA in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register at Address offset: 0x4E + 0x40 × channel number can be used for SWRQ activation. In case of a software request, acknowledge is not generated (neither hardware signal, nor CxMAR write access). Bit 15 Reserved, must be kept at reset value. Bit 14 WEX: Word Endianess exchange This bit is set and cleared by software. 0: Little endianess preserved for words 1: word order exchanged in double word When this bit is set, the word order in the destination double word is reversed: higher address word contains the data read from the lower address of the source. If destination is not a double word, do not care of the value of this bit. This bit is protected and can be written only if EN is 0. Bit 13 HEX: Half word Endianess exchange This bit is set and cleared by software. 0: Little endianess preserved for half words 1: half-word order exchanged in each word When this bit is set, the half-word order in each destination word is reversed: higher address half-word contains the data read from the lower address of the source. If destination length is shorter than word, do not care of the value of this bit. This bit is protected and can be written only if EN is 0. Bit 12 BEX: Byte Endianess exchange This bit is set and cleared by software. 0: Little endianess preserved for bytes 1: byte order exchanged in each half-word When this bit is set, the byte order in each destination Half Word is reversed: higher address word contains the data read from the lower address of the source. If destination is byte, do not care of the value of this bit. This bit is protected and can be written only if EN is 0. Bits 11:9 Reserved, must be kept at reset value. Bit 8 Reserved, must be kept at reset value. DocID029587 Rev 3 573/3178 587 MDMA controller (MDMA) RM0433 Bits 7:6 PL[1:0]: Priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high These bits are protected and can be written only if EN is 0. Bit 5 TCIE: buffer Transfer Complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 4 BTIE: Block Transfer interrupt enable This bit is set and cleared by software. 0: BT complete interrupt disabled 1: BT complete interrupt enabled Bit 3 BRTIE: Block Repeat transfer interrupt enable This bit is set and cleared by software. 0: BT interrupt disabled 1: BT interrupt enabled Bit 2 CTCIE: Channel Transfer Complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 1 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 0 EN: Channel enable / flag channel ready when read low This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled This bit can be cleared by hardware: – on a MDMA end of transfer (stream ready to be configured) – if a transfer error occurs on the AHB/AXI master buses (bus error/hard fault) – if another error condition is encountered (data alignment, block/data size incompatibility) When this bit is reset by software, the ongoing buffer transfer (if any) will be completed. All status/configuration registers will keep their current values. If the channel is re enabled without writing these registers, the channel will continue from the point where it was interrupted. When this bit is read as 0, the software is allowed to program the configuration registers. It is forbidden to write these registers when the EN bit is read as 1 (writes are ignored). Note: When this bit is reset by software, it is recommended to wait for the CTCIF = 1, in order to ensure that any ongoing buffer transfer has been completed, before reprogramming the channel. 574/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.5.6 MDMA channel x Transfer Configuration register (MDMA_CxTCR) (x = 0..15) This register is used to configure the concerned channel. Address offset: 0x50 + 0x40 × channel number Reset value: 0x0000 0000 31 30 BWM SWRM 29 28 TRGM[1:0] 27 26 PAM[1:0] 25 24 23 22 PKE 21 20 19 18 TLEN[6:0] 17 16 DBURST[2:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBURST [0] rw SBURST[2:0] rw rw DINCOS[1:0] rw rw rw SINCOS[1:0] DSIZE[1:0] SSIZE[1:0] rw rw rw rw rw rw DINC[1:0] rw rw SINC[1:0] rw rw Bit 31 BWM: Bufferable Write Mode This bit is set and cleared by software. 0: The destination write operation is non-bufferable. 1: The destination write operation is bufferable. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable. Bit 30 SWRM: Software Request Mode This bit is set and cleared by software. If a hardware or software request is currently active, the bit change will be delayed until the current transfer is completed. 0: hardware request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. If the CxMAR contains a valid address, the CxMDR value will also be written at CxMAR address. 1: hardware request are ignored. Transfer is triggered by software writing 1 to the SWRQ bit. This bit is protected and can be written only if EN is 0. Bits 29:28 TRGM[1:0]: Trigger Mode These bits are set and cleared by software. 00: Each MDMA request (software or hardware) triggers a buffer transfer 01: Each MDMA request (software or hardware) triggers a block transfer 10: Each MDMA request (software or hardware) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 11: Each MDMA request (software or hardware) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0. DocID029587 Rev 3 575/3178 587 MDMA controller (MDMA) RM0433 Bits 27:26 PAM[1:0]: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. 00: Right Aligned, padded w/ 0s (default) 01: Right Aligned, Sign extended 10: Left Aligned (padded with 0s) 11: Reserved Case 2: Source data size larger than destination data size. 00: Right Aligned - only the LSBs part of the Source is written to the destination address 10: Left Aligned - only the MSBs part of the Source is written to the destination address The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0 Bit 25 PKE: Pack Enable This bit is set and cleared by software. 0: The source data is written to the destination as is. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[1:0] value. 1: The source data is packed/unpacked into the destination data size. All data are right aligned, in Little Endian mode. This bit is protected and can be written only if EN is 0 Bits 24:18 TLEN[6:0]: buffer Transfer Length (number of bytes - 1) These bits are set and cleared by software. The value of TLEN+1 represents the number of bytes to be transferred in a single transfer. The Transfer Length MUST be a multiple of the data size (for both Source and Destination) Note: When the source/destination sizes are different and padding/truncation is used, the TLEN+1 refers to the source data array size. These bits are protected and can be written only if EN is 0 DBURST value must be programmed in order to ensure that the burst size will be lower than the Transfer Size. Bits 17:15 DBURST[2:0]: Destination burst transfer configuration These bits are set and cleared by software. 000: single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 DBURST value must be programmed as to ensure that the burst size will be lower than the Transfer Length. If this is not ensured, the result is unpredictable. Note: When the destination bus is TCM/AHB (DBUS=1) and DINCOS=11 or DINC=00 or DINCOS/=DSIZE, DBURST must be programmed to 000 (single transfer), else the result is unpredictable. Note: When the destination bus is system/AXI bus (DBUS=0) and DINC=00, DBURST must be maximum 100 (burst of 16), else the result is unpredictable. 576/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) Bits 14:12 SBURST[2:0]: Source burst transfer configuration These bits are set and cleared by software. 000: single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 SBURST value must be programmed as to ensure that the burst size will be lower than the transfer length. If this is not ensured, the result is unpredictable. Note: When the source bus is TCM (SBUS=1) and SINCOS=11 or SINC = 00 or SINCOS/=SSIZE, SBURST must be programmed to 000 (single transfer), else the result is unpredictable. Note: When the source bus is system/AXI bus (SBUS=0) and SINC=00, SBURST must be maximum 100 (burst of 16), else the result is unpredictable. Bits 11:10 DINCOS[1:0]: Destination increment offset size These bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: Double-Word (64-bit) This bits have no meaning if bit DINC[1:0] = '00'. These bits are protected and can be written only if EN = '0'. If DINCOS < DSIZE and DINC /= 00, the result will be unpredictable. If destination is AHB and DBURST =/ 000, destination address must be aligned with DINCOS size, else the result is unpredictable. Bits 9:8 SINCOS[1:0]: Source increment offset size These bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: Double-Word (64-bit) This bits have no meaning if bit SINC[1:0] = '00'. These bits are protected and can be written only if EN = '0'. If SINCOS < SSIZE and SINC /= 00, the result will be unpredictable. If source is TCM/AHB and SBURST =/ 000, source address must be aligned with SINCOS size, else the result is unpredictable. Bits 7:6 DSIZE[1:0]: Destination data size These bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: Double-Word (64-bit) These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC /= 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1). DocID029587 Rev 3 577/3178 587 MDMA controller (MDMA) RM0433 Bits 5:4 SSIZE[1:0]: Source data size These bits are set and cleared by software. 00: Byte (8-bit) 01: Half-word (16-bit) 10: Word (32-bit) 11: Double-Word (64-bit) These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC /= 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1). Bits 3:2 DINC[1:0]: Destination increment mode These bits are set and cleared by software. 00: Destination address pointer is fixed 10: Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 11: Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden. Bits 1:0 SINC[1:0]: Source increment mode These bits are set and cleared by software. 00: Source address pointer is fixed 10: Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 11: Source address pointer is decremented after each data transfer (decrement is done according to SINCOS) These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 14.5.7 MDMA Channel x block number of data register (MDMA_CxBNDTR) (x = 0..15) Address offset: 0x54 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 BRC[11:0] 19 18 BRDUM BRSUM 17 16 Res. BNDT[16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 rw 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw BNDT[15:0] 578/3178 rw DocID029587 Rev 3 RM0433 MDMA controller (MDMA) Bits 31:20 BRC[11:0]: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0. Bit 19 BRDUM: Block Repeat Destination address Update Mode 0: At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 1: At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) These bits are protected and can be written only if EN is 0. Bit 18 BRSUM: Block Repeat Source address Update Mode 0: At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 1: At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) These bits are protected and can be written only if EN is 0. Bit 17 Reserved, must be kept at reset value. Bits 16:0 BNDT[16:0]: Block Number of data bytes to transfer Number of bytes to be transferred (0 up to 65536) in the current block. When the channel is enabled, this register is read-only, indicating the remaining data items to be transmitted. During the channel activity, this register decrements, indicating the number of data items remaining in the current block. Once the block transfer has completed, this register can either stay at zero or be reloaded automatically with the previously programmed value if the channel is configured in block Repeat mode. If the value of this register is zero, no transaction can be served even if the stream is enabled. These bits are protected and can be written only if EN is 0. Note: 1: If the BNDT value is not an integer multiple of the TLEN+1 value, the last transfer will be shorter and contain only the remaining data in the Block. Note: 2: The size of the block must be a multiple of the source and destination data size. If this is not true, an error will be set and the no data will be written. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04) DocID029587 Rev 3 579/3178 587 MDMA controller (MDMA) 14.5.8 RM0433 MDMA channel x source address register (MDMA_CxSAR) (x = 0..15) Address offset: 0x58 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw SAR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 SAR[31:0]: Source address These bits represent the base address of the peripheral data register from/to which the data will be read. They must be aligned with the SSIZE (e.g. SAR[1:0] = 00 when SSIZE=10), but may be unaligned with the SINCOS. When source is TCM/AHB, if address is not aligned with SINCOS, access must be programmed as single (SBURST=000). These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register. During the channel activity, this register is updated, reflecting the current address from which the data will be read next. When the block repeat mode is active, when a block transfer is completed, the source address is updated by adding/subtracting the SAU value to the current value (already updated after the last transfer in the block). When the Linked List mode is active, at the end of a block (repeated or not) transfer, the SAR value will be loaded from memory (from address LSA + m) In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08) 14.5.9 MDMA channel x destination address register (MDMA_CxDAR) (x = 0..15) Address offset: 0x5C + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 M 25 24 23 22 21 20 19 18 17 16 DAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DAR[15:0] 580/3178 rw DocID029587 Rev 3 RM0433 MDMA controller (MDMA) Bits 31:0 DAR[31:0]: Destination address Base address of the destination address to which the data will be written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register. Must be aligned with the DSIZE (e.g. DAR[0] = 0 when DSIZE=01), but may be unaligned with the DINCOS. When destination is AHB, if address is not aligned with DINCOS, access must be programmed as single (DBURST=000). During the channel activity, this register is updated, reflecting the current address to which the data will be written next. When the block repeat mode is active, when a block transfer is completed, the Destination address is updated by adding/subtracting the DAU value to the current value (after the last transfer in the block). When the Linked List mode is active, at the end of a block (repeated or not) transfer, the DAR value will be loaded from memory (from address LSA + m) In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C) DocID029587 Rev 3 581/3178 587 MDMA controller (MDMA) 14.5.10 RM0433 MDMA channel x Block Repeat address Update register MDMA_CxBRUR (x = 0..15) Address offset: 0x60 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DUV[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw SUV[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 DUV[15:0]: Destination address Update Value This value is used to update (by addition or subtraction) the current destination address at the end of a block transfer. Must be an integer multiple of DSIZE, in order to keep DAR aligned to DSIZE (e.g. DAR[1:0] = 00 when DSIZE=10). If this value is 0, the next repetition of the block transfer will continue to the next address. When the block repeat mode is not active (BRC=0), this field is ignored. These bits are write-protected and can be written only when bit EN = '0' in the MDMA_CxCR register. Note: This field must be programmed to 0 when DINC[1:0] = 00. Bits 15:0 SUV[15:0]: Source address Update Value This value is used to update (by addition or subtraction) the current source address at the end of a block Transfer. Must be an integer multiple of SSIZE, in order to keep SAR aligned to SSIZE (e.g. SAR[1:0] = 00 when SSIZE=10). If this value is 0, the next repetition of the block transfer will continue from the next address. When the block repeat mode is not active (BRC=0), this field is ignored. These bits are write-protected and can be written only when bit EN = '0' in the MDMA_CxCR register. Note: This field must be programmed to 0 when SINC[1:0] = 00. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10) 582/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.5.11 MDMA channel x Link Address register (MDMA_CxLAR) (x = 0..15) Address offset: 0x64 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw r r r LAR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 LAR[31:0]: Link Address Register At the end of a (repeated) block Transfer, the current channel configuration registers (CxTCR, CxBNDTR, CxSAR, CxDAR, CxBRUR, CxMAR, CxMDR and the CxLAR register itself) are loaded with the data structure found at this address. If the value of this register is 0, no register update will take place, the channel will be disabled and the CTCIF will be set, indicating the end of the transfer for this channel. These bits are writeprotected and can be written only when bit EN = '0' in the MDMA_CxCR register. The channel configuration (LAR address) must be in the AXI address space. LAR value must be aligned at a Double Word address, i.e. LAR[2:0] = 0x0 In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). Note: The new value is only taken into account after all registers are updated, for the next end of block. DocID029587 Rev 3 583/3178 587 MDMA controller (MDMA) 14.5.12 RM0433 MDMA channel x Trigger and Bus selection Register (MDMA_CxTBR) (x = 0..15) Address offset: 0x68 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBUS SBUS rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw TSEL[5:0] rw rw rw rw Bits 31:18 Reserved, must be kept at reset value. Bit 17 DBUS: Destination BUS select 0: The system/AXI bus is used as destination (write operation) on channel x. 1: The AHB bus/TCM is used as destination (write operation) on channel x. This bit is protected and can be written only if EN is 0. Bit 16 SBUS: Source BUS select 0: The system/AXI bus is used as source (read operation) on channel x. 1: The AHB bus/TCM is used as source (read operation) on channel x. This bit is protected and can be written only if EN is 0. Bits 15:6 Reserved, must be kept at reset value. Bits 5:0 TSEL[5:0]: Trigger Selection This bit field selects the hardware trigger (RQ) input for channel x. The ACK is sent on the ACK output having the same index value. When SWRM bit is set (software request selected), this bit field is ignored. These bits are write-protected and can be written only when bit EN = '0' in the MDMA_CxCR register. Note: If multiple channels are triggered by the same event (have the same TSEL value), all of them will be triggered in parallel. However, only the channel with the lowest index will acknowledge the request . In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18) 584/3178 DocID029587 Rev 3 RM0433 MDMA controller (MDMA) 14.5.13 MDMA channel x Mask address register (MDMA_CxMAR) (x = 0..15) Address offset: 0x70 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw MAR[15:0] rw Bits 31:0 MAR[31:0]: Mask address A write of the MDR value will also be done to this address. This allows to clear the RQ signal generated by the DMA2 by writing to its Interrupt Clear register. If the value of this register is 0, this function is disabled. These bits are write-protected and can be written only when bit EN = '0' in the MDMA_CxCR register. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20) 14.5.14 MDMA channel x Mask Data register (MDMA_CxMDR) (x = 0..15) Address offset: 0x74 + 0x40 × channel number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MDR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MDR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 MDR[31:0]: Mask Data A write of the MDR value will also be done to the address defined by the MAR register. This allows to clear the RQ signal generated by the DMA2 by writing to its Interrupt Clear register. These bits are write-protected and can be written only when bit EN = '0' in the MDMA_CxCR register. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24) DocID029587 Rev 3 585/3178 587 MDMA controller (MDMA) 14.5.15 RM0433 MDMA register map Table 96 summarizes the MDMA registers. GIF0 GIF1 GIF2 GIF3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRQA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TCIF BTIF Res. Res. Res. Res. Res. Res. GIF4 GIF5 GIF6 GIF7 GIF8 GIF9 GIF11 GIF10 GIF12 GIF13 GIF14 Res. Res. Res. 0 0 0 0 Res. 0 0 Res. 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TED 0 0 0 0 0 TEIF CTCIF BRTIF CTEIF CCTCIF CBRTIF EN TEIE CTCIE 0 0 0 0 BRTIE BTIE 0 0 TCIE 0 0 0 0 0 0 0 0 0 0 SINC[1:0] PL[1:0] DSIZE[1:0] SINCOS[1:0] DINCOS[1:0] 0 0 0 0 CBTIF CLTCIF Res. Res. Res. Res. TELD 0 0 0 Res. Res. Res. BEX SBURST[2:0] 0 0 Res. HEX WEX Res. 0 0 TEA[6:0] DINC[1:0] 0 0 0 0 0 0 SSIZE[1:0] 0 0 0 0 0 0 0 BNDT[16:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAR[31:0]. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAR[31:0]. 0 0 0 0 DUV[15:0]. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. TSEL[5:0] Res. Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Reset value 0 0 SBUS 0 0 Res. 0 0 0 DBUS 0 0 Res. 0 0 Res. 0 0 Res. Reserved 0 0 Res. 0x6C + 0x40 × channel number 0 0 0 Res. MDMA_CxTBR SUV[15:0]. LAR[31:0]. Res. 0x68 + 0x40 × channel number 0 0 Res. 0 0 0 Res. 0 0 0 Res. Reset value 0 0 Res. MDMA_CxLAR Res. 0 0x64 + 0x40 × channel number Res. MDMA_CxBRUR 0x60 + 0x40 × Reset value channel number 0 0 Res. Reset value 0 Res. MDMA_CxDAR 0 0 BRC[11:0] Res. 0x5C + 0x40 × channel number 0 0 0 DBURST[2:0] 0 0 0 0 Res. 0 0 BRSUM PAM[1:0] 0 TLEN[6:0]. BRDUM TRGM[1:0] 0 PKE BWM SWRM 0 0x54 MDMA_CxBNDTR + 0x40 × channel number Reset value 0 Reset value SWRQ Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value MDMA_CxSAR TEMD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 0x58 + 0x40 × channel number Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. MDMA_CxTCR Res. 0x50 + 0x40 × channel number Res. MDMA_CxCR Res. 0x4C + 0x40 × channel number Res. MDMA_CxESR Res. 0 Res. Reset value 0x48 + 0x40 × channel number 586/3178 0 0 Res. MDMA_CxISR 0x44 MDMA_CxIFCR + 0x40 × channel number Reset value 0x70 + 0x40 × channel number 0 0 Reset value Res. 0x40 + 0x40 × channel number 0 Res. 0x04 0x3C Reserved Res. Reset value GIF15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MDMA_GISR0 Res. 0x00 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 96. MDMA register map and reset values Reset value MDMA_CxMAR Reset value MAR[31:0]. 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 MDMA controller (MDMA) Register name 0x74 + 0x40 × channel number MDMA_CxMDR Reset value 0 0 0x74 - 0x7C + 0x40 × channel number Reserved Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Res. Table 96. MDMA register map and reset values (continued) MDR[31:0]. Res. Res. Res. 0 0 0 0 Res. Res. 0 0 Res. Res. Res. 0 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. Res. 0 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. Res. 0 0 Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID029587 Rev 3 587/3178 587 Direct memory access controller (DMA1, DMA2) 15 Direct memory access controller (DMA1, DMA2) 15.1 DMA introduction RM0433 Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action. This keeps CPU resources free for other operations. The DMA controller combines a powerful dual AHB master bus architecture with independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix architecture. The two DMA controllers have 16 streams in total (8 for each controller), each dedicated to managing memory access requests from one or more peripherals. Each stream can have up to 8 channels (requests) in total. And each has an arbiter for handling the priority between DMA requests. 15.2 DMA main features The main DMA features are: • Dual AHB master bus architecture, one dedicated to memory accesses and one dedicated to peripheral accesses • AHB slave programming interface supporting only 32-bit accesses • 8 streams for each DMA controller, up to 115 channels (requests) per stream • Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be used in FIFO mode or direct mode: – FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the FIFO size – Direct mode Each DMA request immediately initiates a transfer from/to the memory. When it is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads only one data from the memory to the internal FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral. • 588/3178 Each stream can be configured by hardware to be: – a regular channel that supports peripheral-to-memory, memory-to-peripheral and memory-to-memory transfers – a double buffer channel that also supports double buffering on the memory side • Each of the 8 streams are connected to dedicated hardware DMA channels (requests) • Priorities between DMA stream requests are software-programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 0 has priority over request 1, etc.) DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) • Each stream also supports software trigger for memory-to-memory transfers • Each stream request can be selected via DMAMux1 among up to 115 possible channel requests. This selection is software-configurable and allows a great number of peripherals to initiate DMA requests • The number of data items to be transferred can be managed either by the DMA controller or by the peripheral: – DMA flow controller: the number of data items to be transferred is softwareprogrammable from 1 to 65535 – Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware • Independent source and destination transfer width (byte, half-word, word): when the data widths of the source and destination are not equal, the DMA automatically packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only available in FIFO mode • Incrementing or non-incrementing addressing for source and destination • Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is software-configurable, usually equal to half the FIFO size of the peripheral • Each stream supports circular buffer management • 5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA FIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for each stream DocID029587 Rev 3 589/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 15.3 DMA functional description 15.3.1 DMA block diagram Figure 69 shows the block diagram of a DMA. Figure 69. DMA block diagram 7R0'0$ $+%PDVWHU $+%PDVWHU 675($0 ),)2 675($0 3HULSKHUDOSRUW 675($0 ),)2 ),)2 675($0 675($0 ),)2 675($0 675($0 ),)2 GPDBLW> @ GPDBWFLI> @ 0HPRU\SRUW $+%VODYH SURJUDPPLQJ LQWHUIDFH GPDBKFON $+% 7R19,& 675($0 675($0 ),)2 675($0 675($0 675($0 675($0 ),)2 ),)2 675($0 $UELWHU $UELWUHU 675($0 )URP '0$0X[ GPDBVWU GPDBVWU GPDBVWU GPDBVWU GPDBVWU GPDBVWU GPDBVWU GPDBVWU 675($0 '0$FRQWUROOHU 3URJUDPPLQJSRUW 06Y 9 15.3.2 DMA internal signals Table 97 shows the internal DMA signals. Table 97. DMA internal input/output signals 590/3178 Signal name Signal type dma_hclk Digital input DMA AHB clock dma_it[0:7] Digital outputs DMA stream [0:7] global interrupts dma_tcif[0:7] Digital outputs MDMA triggers dma_str[0:7] Digital input DMA stream [0:7] requests Description DocID029587 Rev 3 RM0433 15.3.3 Direct memory access controller (DMA1, DMA2) DMA overview The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions. It can carry out the following transactions: • peripheral-to-memory • memory-to-peripheral • memory-to-memory The DMA controller provides two AHB master ports: the AHB memory port, intended to be connected to memories and the AHB peripheral port, intended to be connected to peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must also have access to the memories. The AHB slave port is used to program the DMA controller (it supports only 32-bit accesses). 15.3.4 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable. Each DMA transfer consists of three operations: • A loading from the peripheral data register or a location in memory, addressed through the DMA_SxPAR or DMA_SxM0AR register • A storage of the data loaded to the peripheral data register or a location in memory addressed through the DMA_SxPAR or DMA_SxM0AR register • A post-decrement of the DMA_SxNDTR register, which contains the number of transactions that still have to be performed After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the DMA controller. The peripheral releases its request as soon as it gets the Acknowledge signal from the DMA controller. Once the request has been deasserted by the peripheral, the DMA controller releases the Acknowledge signal. If there are more requests, the peripheral can initiate the next transaction. 15.3.5 DMA request mapping The DMA request mapping to peripherals and DMA channels is described in Section 17.3.2: DMAMUX1 mapping. DocID029587 Rev 3 591/3178 620 Direct memory access controller (DMA1, DMA2) 15.3.6 RM0433 Arbiter An arbiter manages the 8 DMA stream requests based on their priority for each of the two AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences. Priorities are managed in two stages: • • 15.3.7 Software: each stream priority can be configured in the DMA_SxCR register. There are four levels: – Very high priority – High priority – Medium priority – Low priority Hardware: If two requests have the same software priority level, the stream with the lower number takes priority over the stream with the higher number. For example, Stream 2 takes priority over Stream 4. DMA streams Each of the 8 DMA controller streams provides a unidirectional transfer link between a source and a destination. Each stream can be configured to perform: • Regular type transactions: memory-to-peripherals, peripherals-to-memory or memoryto-memory transfers • Double-buffer type transactions: double buffer transfers using two memory pointers for the memory (while the DMA is reading/writing from/to a buffer, the application can write/read to/from the other buffer). The amount of data to be transferred (up to 65535) is programmable and related to the source width of the peripheral that requests the DMA transfer connected to the peripheral AHB port. The register that contains the amount of data items to be transferred is decremented after each transaction. 15.3.8 Source, destination and transfer modes Both source and destination transfers can address peripherals and memories in the entire 4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF. The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory transfers. Table 98 describes the corresponding source and destination addresses. Table 98. Source and destination address 592/3178 Bits DIR[1:0] of the DMA_SxCR register Direction Source address Destination address 00 Peripheral-to-memory DMA_SxPAR DMA_SxM0AR 01 Memory-to-peripheral DMA_SxM0AR DMA_SxPAR 10 Memory-to-memory DMA_SxPAR DMA_SxM0AR 11 Reserved - - DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively. Peripheral-to-memory mode Figure 70 describes this mode. When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO. When the threshold level of the FIFO is reached, the contents of the FIFO are drained and stored into the destination. The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software. In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the corresponding data are immediately drained and stored into the destination. The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Figure 70. Peripheral-to-memory mode '0$B6[0$5 '0$FRQWUROOHU '0$B6[0$5 $+%PHPRU\SRUW 0HPRU\EXV 0HPRU\ GHVWLQDWLRQ GPDBVWU[ $UELWHU ),)2 OHYHO ),)2 $+%SHULSKHUDO SRUW '0$B6[3$5 3HULSKHUDOEXV 3HULSKHUDOVRXUFH 3HULSKHUDO'0$UHTXHVW 06Y 9 1. For double-buffer mode. DocID029587 Rev 3 593/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 Memory-to-peripheral mode Figure 71 describes this mode. When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream immediately initiates transfers from the source to entirely fill the FIFO. Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory. The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software. In direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA transfers the preloaded value into the configured destination. It then reloads again the empty internal FIFO with the next data to be transfer. The preloaded data size corresponds to the value of the PSIZE bitfield in the DMA_SxCR register. The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Figure 71. Memory-to-peripheral mode '0$B6[0$5 '0$FRQWUROOHU '0$B6[0$5 0HPRU\EXV $+%PHPRU\ SRUW 0HPRU\VRXUFH GPDBVWU[ $UELWHU ),)2 OHYHO ),)2 $+%SHULSKHUDO SRUW 3HULSKHUDOEXV '0$B6[3$5 3HULSKHUDOVRXUFH 3HULSKHUDO'0$UHTXHVW 06Y 9 1. For double-buffer mode. 594/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This is the memory-to-memory mode, described in Figure 72. When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the stream immediately starts to fill the FIFO up to the threshold level. When the threshold level is reached, the FIFO contents are drained and stored into the destination. The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the DMA_SxCR register is cleared by software. The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Note: When memory-to-memory mode is used, the Circular and direct modes are not allowed. Figure 72. Memory-to-memory mode $-!?3X-!2 $-! CONTROLLER $-!?3X-!2 !(" MEMORY PORT -EMORY BUS -EMORY DESTINATION !RBITER 3TREAM ENABLE &)&/ LEVEL &)&/ !(" PERIPHERAL PORT $-!?3X0!2 0ERIPHERAL BUS -EMORY SOURCE AI 1. For double-buffer mode. 15.3.9 Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented or kept constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR register. Disabling the Increment mode is useful when the peripheral source or destination data are accessed through a single register. If the Increment mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register. DocID029587 Rev 3 595/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 In order to optimize the packing operation, it is possible to fix the increment offset size for the peripheral address whatever the size of the data transferred on the AHB peripheral port. The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with the data size on the peripheral AHB port, or on a 32-bit address (the address is then incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only. If the PINCOS bit is set, the address of the following transfer is the address of the previous one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE value. The AHB memory port, however, is not impacted by this operation. 15.3.10 Circular mode The Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served. Note: In the circular mode, it is mandatory to respect the following rule in case of a burst mode configured for memory: DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where: – (Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR register) – ((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and PSIZE bits in the DMA_SxCR register. They are byte dependent) – DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port For example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4). If this formula is not respected, the DMA behavior and data integrity are not guaranteed. NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data size, otherwise this could result in a bad DMA behavior. 15.3.11 Double buffer mode This mode is available for all the DMA1 and DMA2 streams. The Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register. A double-buffer stream works as a regular (single buffer) stream with the difference that it has two memory pointers. When the Double buffer mode is enabled, the Circular mode is automatically enabled (CIRC bit in DMA_SxCR is don’t care) and at each end of transaction, the memory pointers are swapped. In this mode, the DMA controller swaps from one memory target to another at each end of transaction. This allows the software to process one memory area while the second memory area is being filled/used by the DMA transfer. The double-buffer stream can work in both directions (the memory can be either the source or the destination) as described in Table 99: Source and destination address registers in double buffer mode (DBM=1). 596/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) Note: In Double buffer mode, it is possible to update the base address for the AHB memory port on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the following conditions: • When the CT bit is ‘0’ in the DMA_SxCR register, the DMA_SxM1AR register can be written. Attempting to write to this register while CT = '1' sets an error flag (TEIF) and the stream is automatically disabled. • When the CT bit is ‘1’ in the DMA_SxCR register, the DMA_SxM0AR register can be written. Attempting to write to this register while CT = '0', sets an error flag (TEIF) and the stream is automatically disabled. To avoid any error condition, it is advised to change the base address as soon as the TCIF flag is asserted because, at this point, the targeted memory must have changed from memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the Double buffer mode), the memory address registers are write-protected as soon as the stream is enabled. Table 99. Source and destination address registers in double buffer mode (DBM=1) Bits DIR[1:0] of the DMA_SxCR register Direction Source address Destination address 00 Peripheral-to-memory DMA_SxPAR DMA_SxM0AR / DMA_SxM1AR 01 Memory-to-peripheral DMA_SxM0AR / DMA_SxM1AR DMA_SxPAR (1) 10 Not allowed 11 Reserved - - 1. When the Double buffer mode is enabled, the Circular mode is automatically enabled. Since the memory-to-memory mode is not compatible with the Circular mode, when the Double buffer mode is enabled, it is not allowed to configure the memory-to-memory mode. 15.3.12 Programmable data width, packing/unpacking, endianness The number of data items to be transferred has to be programmed into DMA_SxNDTR (number of data items to transfer bit, NDT) before enabling the stream (except when the flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set). When using the internal FIFO, the data widths of the source and destination data are programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-, 16- or 32-bit). When PSIZE and MSIZE are not equal: • The data width of the number of data items to transfer, configured in the DMA_SxNDTR register is equal to the width of the peripheral bus (configured by the PSIZE bits in the DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-toperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for half-word, the number of bytes to be transferred is equal to 2 × NDT. • The DMA controller only copes with little-endian addressing for both source and destination. This is described in Table 100: Packing/unpacking & endian behavior (bit PINC = MINC = 1). This packing/unpacking procedure may present a risk of data corruption when the operation is interrupted before the data are completely packed/unpacked. So, to ensure data coherence, the stream may be configured to generate burst transfers: in this case, each DocID029587 Rev 3 597/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 group of transfers belonging to a burst are indivisible (refer to Section 15.3.13: Single and burst transfers). In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is not possible. In this case, it is not allowed to have different source and destination transfer data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are don’t care). Table 100. Packing/unpacking & endian behavior (bit PINC = MINC = 1) Number AHB AHB of data memory peripheral items to port port transfer width width (NDT) Peripheral port address / byte lane Memory transfer number Memory port address / byte lane Peripheral transfer number PINCOS = 1 PINCOS = 0 8 8 4 1 2 3 4 0x0 / B1|B0[15:0] 2 0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] 0x0 / B1|B0[15:0] 16 1 2 3 4 1 8 2 0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0] 1 2 3 4 0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] 1 0x0 / B3|B2|B1|B0[31:0] 0x0 / B3|B2|B1|B0[31:0] 1 0x0 / B1|B0[15:0] 2 0x2 / B3|B2[15:0] 1 2 3 4 0x0 / B0[7:0] 0x4 / B1[7:0] 0x8 / B2[7:0] 0xC / B3[7:0] 0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] 1 0x0 / B1|B0[15:0] 1 0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0] 2 0x2 / B1|B0[15:0] 2 0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0] 1 2 0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] 1 0x0 / B3|B2|B1|B0[31:0] 0x0 / B3|B2|B1|B0[31:0] 1 0x0 / B3|B2|B1|B0[31:0] 1 2 3 4 0x0 / B0[7:0] 0x4 / B1[7:0] 0x8 / B2[7:0] 0xC / B3[7:0] 0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] 1 0x0 /B3|B2|B1|B0[31:0] 1 2 0x0 / B1|B0[15:0] 0x4 / B3|B2[15:0] 0x0 / B1|B0[15:0] 0x2 / B3|B2[15:0] 1 0x0 /B3|B2|B1|B0 [31:0] 1 0x0 /B3|B2|B1|B0 [31:0] 0x0 / B3|B2|B1|B0[31:0] 8 32 1 16 8 4 16 16 2 16 32 1 32 8 4 32 16 2 32 32 1 Note: 0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] 1 2 3 4 0x0 / B0[7:0] 0x4 / B1[7:0] 0x8 / B2[7:0] 0xC / B3[7:0] 0x0 / B0[7:0] 0x1 / B1[7:0] 0x2 / B2[7:0] 0x3 / B3[7:0] Peripheral port may be the source or the destination (it could also be the memory source in the case of memory-to-memory transfer). PSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer will not be incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is lower than the data width of the memory port (MSIZE bits). This constraint is summarized in Table 101. 598/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) Table 101. Restriction on NDT versus PSIZE and MSIZE 15.3.13 PSIZE[1:0] of DMA_SxCR MSIZE[1:0] of DMA_SxCR NDT[15:0] of DMA_SxNDTR 00 (8-bit) 01 (16-bit) must be a multiple of 2 00 (8-bit) 10 (32-bit) must be a multiple of 4 01 (16-bit) 10 (32-bit) must be a multiple of 2 Single and burst transfers The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats. The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register. The burst size indicates the number of beats in the burst, not the number of bytes transferred. To ensure data coherence, each group of transfers that form a burst are indivisible: AHB transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master during the sequence of the burst transfer. Depending on the single or burst configuration, each DMA request initiates a different number of transfers on the AHB peripheral port: • When the AHB peripheral port is configured for single transfers, each DMA request generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits in the DMA_SxCR register • When the AHB peripheral port is configured for burst transfers, each DMA request generates 4,8 or 16 beats of byte, half word or word transfers depending on the PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register. The same as above has to be considered for the AHB memory port considering the MBURST and MSIZE bits. In direct mode, the stream can only generate single transfers and the MBURST[1:0] and PBURST[1:0] bits are forced by hardware. The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer. The burst configuration has to be selected in order to respect the AHB protocol, where bursts must not cross the 1 KB address boundary because the minimum address space that can be allocated to a single slave is 1 KB. This means that the 1 KB address boundary should not be crossed by a burst block transfer, otherwise an AHB error would be generated, that is not reported by the DMA registers. DocID029587 Rev 3 599/3178 620 Direct memory access controller (DMA1, DMA2) 15.3.14 RM0433 FIFO FIFO structure The FIFO is used to temporarily store data coming from the source before transmitting them to the destination. Each stream has an independent 4-word FIFO and the threshold level is softwareconfigurable between 1/4, 1/2, 3/4 or full. To enable the use of the FIFO threshold level, the direct mode must be disabled by setting the DMDIS bit in the DMA_SxFCR register. The structure of the FIFO differs depending on the source and destination data widths, and is described in Figure 73: FIFO structure. Figure 73. FIFO structure WORDS %MPTY 3OURCE BYTE " " " " " " " " " " " " " " " " &ULL BYTE LANE " " " " BYTE LANE " " " " BYTE LANE " " " " BYTE LANE 7 " 7 " 7 " 7 " $ESTINATION WORD 7 7 7 7 WORDS %MPTY 3OURCE BYTE " " " " " " " " " " " " " " " " BYTE LANE " " " BYTE LANE ( " ( " ( " " " " BYTE LANE ( " ( " ( " BYTE LANE &ULL " ( $ESTINATION HALF WORD " ( ( ( ( ( ( ( ( " ( " WORDS %MPTY 3OURCE HALF WORD BYTE LANE ( ( ( ( ( ( ( ( &ULL BYTE LANE BYTE LANE ( ( ( ( ( ( ( ( $ESTINATION WORD 7 7 7 7 BYTE LANE 7 7 7 7 WORDS %MPTY 3OURCE HALF WORD ( ( ( ( ( ( ( ( BYTE LANE " " " BYTE LANE ( " ( " ( " " " " BYTE LANE ( " ( " ( " BYTE LANE &ULL " ( " ( $ESTINATION BYTE " " " " " " " " " " " " " " " " " " AI 600/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be generated when the stream is enabled, then the stream will be automatically disabled. The allowed and forbidden configurations are described in Table 102. The forbidden configurations are highlighted in gray in the table. Table 102. FIFO threshold configurations MSIZE Byte Half-word FIFO level MBURST = INCR4 MBURST = INCR8 1/4 1 burst of 4 beats forbidden 1/2 2 bursts of 4 beats 1 burst of 8 beats 3/4 3 bursts of 4 beats forbidden Full 4 bursts of 4 beats 2 bursts of 8 beats 1/4 forbidden 1/2 1 burst of 4 beats 3/4 forbidden Full 2 bursts of 4 beats 1/2 forbidden 3/4 Full forbidden 1 burst of 16 beats forbidden 1 burst of 8 beats 1/4 Word MBURST = INCR16 forbidden forbidden 1 burst of 4 beats In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data size can be: 1 (byte), 2 (half-word) or 4 (word)). Incomplete Burst transfer at the end of a DMA transfer may happen if one of the following conditions occurs: • For the AHB peripheral port configuration: the total number of data items (set in the DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size • For the AHB memory port configuration: the number of remaining data items in the FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the data size In such cases, the remaining data to be transferred will be managed in single mode by the DMA, even if a burst transaction was requested during the DMA stream configuration. Note: When burst transfers are requested on the peripheral AHB port and the FIFO is used (DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to avoid permanent underrun or overrun conditions, depending on the DMA stream direction: If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16. This rule ensures that enough FIFO space at a time will be free to serve the request from the peripheral. DocID029587 Rev 3 601/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 FIFO flush The FIFO can be flushed when the stream is disabled by resetting the EN bit in the DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers: If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination (even though stream is effectively disabled). When this flush is completed, the transfer complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set. The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how many data items are currently available in the destination memory. Note that during the FIFO flush operation, if the number of remaining data items in the FIFO to be transferred to memory (in bytes) is less than the memory data width (for example 2 bytes in FIFO while MSIZE is configured to word), data will be sent with the data width set in the MSIZE bit in the DMA_SxCR register. This means that memory will be written with an undesired value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address). If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions will be generated to complete the FIFO flush. Direct mode By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and the FIFO threshold level is not used. This mode is useful when the system requires an immediate and single transfer to or from the memory after each DMA request. When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral. To avoid saturating the FIFO, it is recommended to configure the corresponding stream with a high priority. This mode is restricted to transfers where: • The source and destination transfer widths are equal and both defined by the PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don’t care) • Burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR are don’t care) Direct mode must not be used when implementing memory-to-memory transfers. 15.3.15 DMA transfer completion Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR or DMA_HISR status register: • 602/3178 In DMA flow controller mode: – The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode – The stream is disabled before the end of transfer (by clearing the EN bit in the DMA_SxCR register) and (when transfers are peripheral-to-memory or memory- DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) to-memory) all the remaining data have been flushed from the FIFO into the memory • Note: In Peripheral flow controller mode: – The last external burst or single request has been generated from the peripheral and (when the DMA is operating in peripheral-to-memory mode) the remaining data have been transferred from the FIFO into the memory – The stream is disabled by software, and (when the DMA is operating in peripheralto-memory mode) the remaining data have been transferred from the FIFO into the memory The transfer completion is dependent on the remaining data in FIFO to be transferred into memory only in the case of peripheral-to-memory mode. This condition is not applicable in memory-to-peripheral mode. If the stream is configured in noncircular mode, after the end of the transfer (that is when the number of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register). 15.3.16 DMA transfer suspension At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer. There are two cases: Note: • The stream disables the transfer with no later-on restart from the point where it was stopped. There is no particular action to do, except to clear the EN bit in the DMA_SxCR register to disable the stream. The stream may take time to be disabled (ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The value of the EN bit in DMA_SxCR is now ‘0’ to confirm the stream interruption. The DMA_SxNDTR register contains the number of remaining data items at the moment when the stream was stopped so that the software can determine how many data items have been transferred before the stream was interrupted. • The stream suspends the transfer before the number of remaining data items to be transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer later by re-enabling the stream. In order to restart from the point where the transfer was stopped, the software has to read the DMA_SxNDTR register after disabling the stream by writing the EN bit in DMA_SxCR register (and then checking that it is at ‘0’) to know the number of data items already collected. Then: – The peripheral and/or memory addresses have to be updated in order to adjust the address pointers – The SxNDTR register has to be updated with the remaining number of data items to be transferred (the value read when the stream was disabled) – The stream may then be re-enabled to restart the transfer from the point it was stopped Note that a Transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the end of transfer due to the stream interruption. DocID029587 Rev 3 603/3178 620 Direct memory access controller (DMA1, DMA2) 15.3.17 RM0433 Flow controller The entity that controls the number of data to be transferred is known as the flow controller. This flow controller is configured independently for each stream using the PFCTRL bit in the DMA_SxCR register. The flow controller can be: • The DMA controller: in this case, the number of data items to be transferred is programmed by software into the DMA_SxNDTR register before the DMA stream is enabled. • The peripheral source or destination: this is the case when the number of data items to be transferred is unknown. The peripheral indicates by hardware to the DMA controller when the last data are being transferred. This feature is only supported for peripherals which are able to signal the end of the transfer, that is: When the peripheral flow controller is used for a given stream, the value written into the DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it will be forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following schemes: • Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the software to stop the stream before the last data hardware signal (single or burst) is sent by the peripheral. In such a case, the stream is switched off and the FIFO flush is triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the DMA_SxNDTR register and apply the following formula: – Note: Number_of_data_transferred = 0xFFFF – DMA_SxNDTR • Normal stream interruption due to the reception of a last data hardware signal: the stream is automatically interrupted when the peripheral requests the last transfer (single or burst) and when this transfer is complete. the TCIFx flag of the corresponding stream is set in the status register to indicate the DMA transfer completion. To know the number of data items transferred, read the DMA_SxNDTR register and apply the same formula as above. • The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is set in the status register to indicate the forced DMA transfer completion. The stream is automatically switched off even though the last data hardware signal (single or burst) has not been yet asserted. The already transferred data will not be lost. This means that a maximum of 65535 data items can be managed by the DMA in a single transaction, even in peripheral flow control mode. When configured in memory-to-memory mode, the DMA is always the flow controller and the PFCTRL bit is forced to 0 by hardware. The Circular mode is forbidden in the peripheral flow controller mode. 604/3178 DocID029587 Rev 3 RM0433 15.3.18 Direct memory access controller (DMA1, DMA2) Summary of the possible DMA configurations Table 103 summarizes the different possible DMA configurations. The forbidden configurations are highlighted in gray in the table. Table 103. Possible DMA configurations DMA transfer mode Peripheral-tomemory Destination Circular mode DMA possible Peripheral forbidden DMA possible Peripheral forbidden DMA only forbidden AHB peripheral port AHB AHB peripheral port memory port Memory-tomemory Flow controller AHB AHB peripheral port memory port AHB memory port Memory-toperipheral 15.3.19 Source Transfer type Direct mode single possible burst forbidden single possible burst forbidden single possible burst forbidden single possible burst forbidden single burst forbidden Double buffer mode possible forbidden possible forbidden forbidden Stream configuration procedure The following sequence should be followed to configure a DMA stream x (where x is the stream number): 1. If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation. Writing this bit to 0 is not immediately effective since it is actually written to 0 once all the current transfers have finished. When the EN bit is read as 0, this means that the stream is ready to be configured. It is therefore necessary to wait for the EN bit to be cleared before starting any stream configuration. All the stream dedicated bits set in the status register (DMA_LISR and DMA_HISR) from the previous data block DMA transfer should be cleared before the stream can be re-enabled. 2. Set the peripheral port register address in the DMA_SxPAR register. The data will be moved from/ to this address to/ from the peripheral port after the peripheral event. 3. Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R register in the case of a double buffer mode). The data will be written to or read from this memory after the peripheral event. 4. Configure the total number of data items to be transferred in the DMA_SxNDTR register. After each peripheral event or each beat of the burst, this value is decremented. 5. Use DMAMux1 to route a DMA request line to the DMA channel. 6. If the peripheral is intended to be the flow controller and if it supports this feature, set the PFCTRL bit in the DMA_SxCR register. 7. Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register. 8. Configure the FIFO usage (enable or disable, threshold in transmission and reception) DocID029587 Rev 3 605/3178 620 Direct memory access controller (DMA1, DMA2) 9. RM0433 Configure the data transfer direction, peripheral and memory incremented/fixed mode, single or burst transactions, peripheral and memory data widths, Circular mode, Double buffer mode and interrupts after half and/or full transfer, and/or errors in the DMA_SxCR register. 10. Activate the stream by setting the EN bit in the DMA_SxCR register. As soon as the stream is enabled, it can serve any DMA request from the peripheral connected to the stream. Once half the data have been transferred on the AHB destination port, the half-transfer flag (HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is generated if the transfer complete interrupt enable bit (TCIE) is set. Warning: 15.3.20 To switch off a peripheral connected to a DMA stream request, it is mandatory to, first, switch off the DMA stream to which the peripheral is connected, then to wait for EN bit = 0. Only then can the peripheral be safely disabled. Error management The DMA controller can detect the following errors: • • • Transfer error: the transfer error interrupt flag (TEIFx) is set when: – A bus error occurs during a DMA read or a write access – A write access is requested by software on a memory address register in Double buffer mode whereas the stream is enabled and the current target memory is the one impacted by the write into the memory address register (refer to Section 15.3.11: Double buffer mode) FIFO error: the FIFO error interrupt flag (FEIFx) is set if: – A FIFO underrun condition is detected – A FIFO overrun condition is detected (no detection in memory-to-memory mode because requests and transfers are internally managed by the DMA) – The stream is enabled while the FIFO threshold level is not compatible with the size of the memory burst (refer to Table 102: FIFO threshold configurations) Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the peripheral-to-memory mode while operating in direct mode and when the MINC bit in the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while the previous data have not yet been fully transferred into the memory (because the memory bus was not granted). In this case, the flag indicates that 2 data items were be transferred successively to the same destination address, which could be an issue if the destination is not able to manage this situation In direct mode, the FIFO error flag can also be set under the following conditions: 606/3178 • In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory bus is not granted for several peripheral requests • In the memory-to-peripheral mode, an underrun condition may occur if the memory bus has not been granted before a peripheral request occurs DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO threshold level, the faulty stream is automatically disabled through a hardware clear of its EN bit in the corresponding stream configuration register (DMA_SxCR). If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss when this kind of errors occur. When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE, FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set. Note: When a FIFO overrun or underrun condition occurs, the data are not lost because the peripheral request is not acknowledged by the stream until the overrun or underrun condition is cleared. If this acknowledge takes too much time, the peripheral itself may detect an overrun or underrun condition of its internal buffer and data might be lost. 15.4 DMA interrupts For each DMA stream, an interrupt can be produced on the following events: • Half-transfer reached • Transfer complete • Transfer error • FIFO error (overrun, underrun or FIFO level error) • Direct mode error Separate interrupt enable control bits are available for flexibility as shown in Table 104. Table 104. DMA interrupt requests Interrupt event Event flag Enable control bit Half-transfer HTIF HTIE Transfer complete TCIF TCIE Transfer error TEIF TEIE FIFO overrun/underrun FEIF FEIE DMEIF DMEIE Direct mode error Note: Before setting an Enable control bit to ‘1’, the corresponding event flag should be cleared, otherwise an interrupt is immediately generated. DocID029587 Rev 3 607/3178 620 Direct memory access controller (DMA1, DMA2) 15.5 RM0433 DMA registers The DMA registers have to be accessed by words (32 bits). 15.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res. FEIF3 TCIF2 HTIF2 TEIF2 DMEIF2 Res. FEIF2 r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. TCIF1 HTIF1 TEIF1 DMEIF1 Res. FEIF1 TCIF0 HTIF0 TEIF0 DMEIF0 Res. FEIF0 r r r r r r r r r r r r r r Bits 31:28, 15:12 Reserved, must be kept at reset value. Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. 0: No transfer complete event on stream x 1: A transfer complete event occurred on stream x Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. 0: No half transfer event on stream x 1: A half transfer event occurred on stream x Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. 0: No transfer error on stream x 1: A transfer error occurred on stream x Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. 0: No Direct Mode Error on stream x 1: A Direct Mode Error occurred on stream x Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_LIFCR register. 0: No FIFO Error event on stream x 1: A FIFO Error event occurred on stream x 608/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) 15.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 DMEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res. FEIF6 r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. TCIF5 HTIF5 TEIF5 DMEIF5 Res. FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 Res. FEIF4 r r r r r r r r r r r Bits 31:28, 15:12 Reserved, must be kept at reset value. Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. 0: No transfer complete event on stream x 1: A transfer complete event occurred on stream x Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. 0: No half transfer event on stream x 1: A half transfer event occurred on stream x Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. 0: No transfer error on stream x 1: A transfer error occurred on stream x Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. 0: No Direct mode error on stream x 1: A Direct mode error occurred on stream x Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_HIFCR register. 0: No FIFO error event on stream x 1: A FIFO error event occurred on stream x DocID029587 Rev 3 609/3178 620 Direct memory access controller (DMA1, DMA2) 15.5.3 RM0433 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 27 15 14 13 12 Res. Res. Res. Res. 26 25 24 CTCIF3 CHTIF3 CTEIF3 CDMEIF3 w w w w 11 10 9 8 CTCIF1 CHTIF1 CTEIF1 CDMEIF1 w w w 23 22 21 Res. CFEIF3 CTCIF2 20 19 18 CHTIF2 CTEIF2 CDMEIF2 w w w w w 7 6 5 4 3 2 Res. CFEIF1 CTCIF0 w w w CHTIF0 CTEIF0 CDMEIF0 w w 17 16 Res. CFEIF2 w 1 0 Res. CFEIF0 w w Bits 31:28, 15:12 Reserved, must be kept at reset value. Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0) Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0) Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0) Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register 15.5.4 DMA high interrupt flag clear register (DMA_HIFCR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. CTCIF7 CHTIF7 CTEIF7 CDMEIF7 15 14 13 12 w w w w 11 10 9 8 Res. Res. Res. Res. CTCIF5 CHTIF5 CTEIF5 CDMEIF5 w w w 23 22 21 20 Res. CFEIF7 CTCIF6 CHTIF6 w w w 7 6 5 4 Res. CFEIF5 CTCIF4 CHTIF4 w w w w 19 18 CTEIF6 CDMEIF6 w w 3 2 CTEIF4 CDMEIF4 w 17 16 Res. CFEIF6 w 1 0 Res. CFEIF4 w Bits 31:28, 15:12 Reserved, must be kept at reset value. Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register 610/3178 DocID029587 Rev 3 w RM0433 Direct memory access controller (DMA1, DMA2) Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register 15.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7) This register is used to configure the concerned stream. Address offset: 0x10 + 0x18 × stream number Reset value: 0x0000 0000 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 PINCOS rw 14 13 12 11 MSIZE[1:0] PSIZE[1:0] rw rw rw rw 24 23 MBURST [1:0] 22 rw rw rw 7 6 10 9 8 MINC PINC CIRC rw rw rw DIR[1:0] rw 21 PBURST[1:0] rw 20 19 18 Res. CT DBM rw rw rw 17 16 PL[1:0] rw rw 5 4 3 2 1 0 PFCTRL TCIE HTIE TEIE DMEIE EN rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bits 24:23 MBURST: Memory burst transfer configuration These bits are set and cleared by software. 00: single transfer 01: INCR4 (incremental burst of 4 beats) 10: INCR8 (incremental burst of 8 beats) 11: INCR16 (incremental burst of 16 beats) These bits are protected and can be written only if EN is ‘0’ In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'. Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration These bits are set and cleared by software. 00: single transfer 01: INCR4 (incremental burst of 4 beats) 10: INCR8 (incremental burst of 8 beats) 11: INCR16 (incremental burst of 16 beats) These bits are protected and can be written only if EN is ‘0’ In direct mode, these bits are forced to 0x0 by hardware. Bit 20 Reserved, must be kept at reset value. Bit 19 CT: Current target (only in double buffer mode) This bits is set and cleared by hardware. It can also be written by software. 0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) 1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) This bit can be written only if EN is ‘0’ to indicate the target memory area of the first transfer. Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. DocID029587 Rev 3 611/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 Bit 18 DBM: Double buffer mode This bits is set and cleared by software. 0: No buffer switching at the end of transfer 1: Memory target switched at the end of the DMA transfer This bit is protected and can be written only if EN is ‘0’. Bits 17:16 PL[1:0]: Priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high These bits are protected and can be written only if EN is ‘0’. Bit 15 PINCOS: Peripheral increment offset size This bit is set and cleared by software 0: The offset size for the peripheral address calculation is linked to the PSIZE 1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). This bit has no meaning if bit PINC = '0'. This bit is protected and can be written only if EN = '0'. This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or if PBURST are different from “00”. Bits 14:13 MSIZE[1:0]: Memory data size These bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: reserved These bits are protected and can be written only if EN is ‘0’. In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as bit EN = '1'. Bits 12:11 PSIZE[1:0]: Peripheral data size These bits are set and cleared by software. 00: Byte (8-bit) 01: Half-word (16-bit) 10: Word (32-bit) 11: reserved These bits are protected and can be written only if EN is ‘0’ Bit 10 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory address pointer is fixed 1: Memory address pointer is incremented after each data transfer (increment is done according to MSIZE) This bit is protected and can be written only if EN is ‘0’. Bit 9 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral address pointer is fixed 1: Peripheral address pointer is incremented after each data transfer (increment is done according to PSIZE) This bit is protected and can be written only if EN is ‘0’. 612/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) Bit 8 CIRC: Circular mode This bit is set and cleared by software and can be cleared by hardware. 0: Circular mode disabled 1: Circular mode enabled When the peripheral is the flow controller (bit PFCTRL=1) and the stream is enabled (bit EN=1), then this bit is automatically forced by hardware to 0. It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (bit EN ='1'). Bits 7:6 DIR[1:0]: Data transfer direction These bits are set and cleared by software. 00: Peripheral-to-memory 01: Memory-to-peripheral 10: Memory-to-memory 11: reserved These bits are protected and can be written only if EN is ‘0’. Bit 5 PFCTRL: Peripheral flow controller This bit is set and cleared by software. 0: The DMA is the flow controller 1: The peripheral is the flow controller This bit is protected and can be written only if EN is ‘0’. When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware. Bit 4 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 3 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 2 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 1 DMEIE: Direct mode error interrupt enable This bit is set and cleared by software. 0: DME interrupt disabled 1: DME interrupt enabled DocID029587 Rev 3 613/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 Bit 0 EN: Stream enable / flag stream ready when read low This bit is set and cleared by software. 0: Stream disabled 1: Stream enabled This bit may be cleared by hardware: – on a DMA end of transfer (stream ready to be configured) – if a transfer error occurs on the AHB master buses – when the FIFO threshold on memory AHB port is not compatible with the size of the burst When this bit is read as 0, the software is allowed to program the Configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1. Note: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared. 15.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) Address offset: 0x14 + 0x18 × stream number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw NDT[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data items to transfer Number of data items to be transferred (0 up to 65535). This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer. Once the transfer has completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases: – when the stream is configured in Circular mode. – when the stream is enabled again by setting EN bit to '1' If the value of this register is zero, no transaction can be served even if the stream is enabled. 614/3178 DocID029587 Rev 3 RM0433 Direct memory access controller (DMA1, DMA2) 15.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) Address offset: 0x18 + 0x18 × stream number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw PAR[15:0] rw Bits 31:0 PAR[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register. 15.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) Address offset: 0x1C + 0x18 × stream number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 M0A[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw M0A[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 M0A[31:0]: Memory 0 address Base address of Memory area 0 from/to which the data will be read/written. These bits are write-protected. They can be written only if: – the stream is disabled (bit EN= '0' in the DMA_SxCR register) or – the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '1' in the DMA_SxCR register (in Double buffer mode). 15.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) Address offset: 0x20 + 0x18 × stream number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw M1A[31:16] M1A[15:0] rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 615/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode) Base address of Memory area 1 from/to which the data will be read/written. This register is used only for the Double buffer mode. These bits are write-protected. They can be written only if: – the stream is disabled (bit EN= '0' in the DMA_SxCR register) or – the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '0' in the DMA_SxCR register. 15.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) Address offset: 0x24 + 0x24 × stream number Reset value: 0x0000 0021 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. FEIE Res. rw FS[2:0] r r DMDIS r Bits 31:8 Reserved, must be kept at reset value. Bit 7 FEIE: FIFO error interrupt enable This bit is set and cleared by software. 0: FE interrupt disabled 1: FE interrupt enabled Bit 6 Reserved, must be kept at reset value. Bits 5:3 FS[2:0]: FIFO status These bits are read-only. 000: 0 < fifo_level < 1/4 001: 1/4 ≤ fifo_level < 1/2 010: 1/2 ≤ fifo_level < 3/4 011: 3/4 ≤ fifo_level < full 100: FIFO is empty 101: FIFO is full others: no meaning These bits are not relevant in the direct mode (DMDIS bit is zero). 616/3178 DocID029587 Rev 3 rw FTH[1:0] rw rw RM0433 Direct memory access controller (DMA1, DMA2) Bit 2 DMDIS: Direct mode disable This bit is set and cleared by software. It can be set by hardware. 0: Direct mode enabled 1: Direct mode disabled This bit is protected and can be written only if EN is ‘0’. This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct mode is not allowed in the memory-to-memory configuration. Bits 1:0 FTH[1:0]: FIFO threshold selection These bits are set and cleared by software. 00: 1/4 full FIFO 01: 1/2 full FIFO 10: 3/4 full FIFO 11: full FIFO These bits are not used in the direct mode when the DMIS value is zero. These bits are protected and can be written only if EN is ‘0’. DocID029587 Rev 3 617/3178 620 0x002C 0x0034 0x0030 618/3178 DMA_S1NDTR Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S0FCR Res Res Res Res Res Res Res Res Res Res FEIE Res 0 0 0 0 0 0 0 0 Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S0PAR 0 0 0 0 0 DMA_S0M0AR 0 DMA_S0M1AR 0 DMA_S1M0AR 0 0 0 DMA_S1PAR 0 0 Reset value 0 0 Reset value 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 PA[31:0] M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDMEIF5 0 0 0 0 0 0 Reset value TCIE HTIE TEIE DMEIE EN 0 PFCTRL DIR[1:0] CTCIF4 CHTIF4 CTEIF4 CDMEIF4 CDMEIF1 CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0 DMEIF5 FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 TEIF1 DMEIF1 FEIF1 TCIF0 HTIF0 TEIF0 DMEIF0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FS[2:0] Reserved FEIF0 Reserved FEIF4 Res. HTIF1 0 CFEIF0 TEIF5 TCIF1 Res. Res. Res. Res. 0 Reserved HTIF5 0 Res TCIF5 Res Res Res Res 0 CFEIF4 CTEIF1 0 Res CHTIF1 Res Res Res Res Res. FEIF2 0 Reserved CFEIF5 Res CTEIF5 0 PINC CFEIF2 CTCIF1 0 CIRC CHTIF5 0 MINC 0 CTCIF5 0 PSIZE[1:0] 0 Res 0 Res 0 Res FEIF6 0 Res 0 Res 0 MSIZE[1:0] PINCOS TEIF2 DMEIF2 0 Res Res CFEIF6 Res 0 PL[1:0] 0 Res 0 Res HTIF2 0 DMEIF6 CDMEIF2 CDMEIF6 0 DBM 0 Res 0 CT 0 TEIF6 CTEIF2 0 CTEIF6 0 0 Res TCIF2 0 HTIF6 CHTIF2 0 TCIF6 CTCIF2 0 CHTIF6 0 CTCIF6 0 Res. FEIF3 0 Res TEIF3 DMEIF7 DMEIF3 TEIF7 HTIF3 HTIF7 Res. Res. 0 FEIF7 CFEIF3 0 Res PBURST[1:0] CDMEIF3 Reserved TEIF3 0 CFEIF7 Reserved CHTIF3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. DMA_LISR TCIF3 TCIF7 Res Res Res Res Register name 0 DMDIS 0 Res 0 Res CDMEIF7 MBURST[1:0] CTEIF7 0 Res 0 Res 0 Res 0 0 Res CHTIF7 0 Res CTCIF3 0 Res 0 Res 0 0 0 Res CTCIF7 0 Res Res Res 0 Res 0 Res 0 0 Res Res 0 Res 0 Res 0 Res Res Res Res 0 Res 0 Res 0 0 Res 0 Res 0 0 0 Res 0 Res 0 0 0 Res 0 Res 0 0 Res Reset value Res 0 Res Reset value 0 Res Res Reset value Res Reset value Res Reset value Res 0 Res DMA_S0NDTR 0 Res DMA_S0CR Res Res DMA_LIFCR Res Res Res Reset value Res 0 Res 0x0024 Reset value Res 0x0018 Reset value Res 0x0010 DMA_HIFCR Res 0x000C Res 0x0008 Res 0x0020 DMA_HISR Res 0x0004 Res 0x0000 Res 0x001C Res 0x0014 Res Offset Res 15.5.11 Res Direct memory access controller (DMA1, DMA2) RM0433 DMA register map Table 105 summarizes the DMA registers. Table 105. DMA register map and reset values 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 PA[31:0] M0A[31:0] M1A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH [1:0] 1 0 0 0 0 1 NDT[15:.] RM0433 Direct memory access controller (DMA1, DMA2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S1FCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 0 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res DMDIS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S3FCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FEIE Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res M1A[31:0] 0 Reset value 0 DMA_S4PAR FS[2:0] FTH [1:0] 1 0 0 0 0 1 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S4M0AR 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S4FCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FEIE Res M1A[31:0] Res DMA_S4M1AR Res 0x0084 0 0 Res 0x0080 0 0 Reset value Reset value 0 0 Res 0x007C 0 PA[31:0] DMA_S3M1AR Reset value 1 0 Res 0x0078 FS[2:0] FTH [1:0] NDT[15:.] Reset value 0x0074 FEIE Res Res Res 0 Res 0 Res 0 0 DMA_S3M0AR DMA_S4NDTR 1 0 Res 0x006C 0 0 Res 0x0068 0 0 Res 0 DMA_S3PAR Reset value 0 DMDIS 0x0064 0 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Res 0 Reset value Reset value FTH [1:0] 1 Reset value 0 DocID029587 Rev 3 FS[2:0] 1 0 0 DMDIS 0x0060 DMA_S3NDTR 0 0 Reset value 0x005C 0 M1A[31:0] Res DMA_S2FCR FS[2:0] 0 M0A[31:0] DMA_S2M1AR Reset value 0x0054 0 Res 0x0050 0 PA[31:0] DMA_S2M0AR Reset value 0 NDT[15:.] 0 DMA_S2PAR Reset value 0x004C Res Reset value Res 0x0048 DMA_S2NDTR Res 0x0044 0 Res Reset value 0 DMDIS 0 Res 0 Res 0 FEIE Reset value Res M1A[31:0] Res 0x003C DMA_S1M1AR Res 0x0038 Register name Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 105. DMA register map and reset values (continued) 0 FTH [1:0] 0 1 619/3178 620 Direct memory access controller (DMA1, DMA2) RM0433 Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S5M0AR 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S5FCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S6M0AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S6FCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FEIE Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res M1A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S7M0AR Reset value 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S7FCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FEIE Res M1A[31:0] Res DMA_S7M1AR Reset value 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 620/3178 FTH [1:0] PA[31:0] Res 0x00CC 0 DMA_S7PAR Res 0x00C8 0 FS[2:0] NDT[15:.] Res 0x00C4 1 0 0 Reset value 0 0 Reset value 0x00C0 0 0 Reset value 0x00BC 0 M0A[31:0] DMA_S6M1AR DMA_S7NDTR 0 0 Res 0x00B4 Reset value 1 PA[31:0] Res 0x00B0 0 DMA_S6PAR 0x00A8 0x00AC 0 FTH [1:0] NDT[15:.] DMDIS 0x00A4 DMA_S6NDTR FS[2:0] DMDIS Reset value Res M1A[31:0] Res DMA_S5M1AR DocID029587 Rev 3 FS[2:0] 1 0 0 DMDIS Reset value 0 FEIE Res Res Res Res Res Res Res Res Res Res Res 0 PA[31:0] Res 0x009C Reset value NDT[15:.] Res 0x0098 Res Reset value DMA_S5PAR 0x0090 0x0094 Res DMA_S5NDTR Res 0x008C Res Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 105. DMA register map and reset values (continued) 0 FTH [1:0] 0 1 RM0433 Basic direct memory access controller (BDMA) 16 Basic direct memory access controller (BDMA) 16.1 Introduction Basic direct memory access (BDMA) controller is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The BDMA controller has 8 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. 16.2 BDMA main features • 8 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of the BDMA controller are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to D3-domain memories and peripherals as source and destination • Programmable number of data to be transferred: up to 65535 DocID029587 Rev 3 621/3178 635 Basic direct memory access controller (BDMA) 16.3 RM0433 BDMA functional description The block diagram is shown in the following figure. Figure 74. BDMA block diagram %'0$ EGPDBKFON &K $+%PDVWHUSRUW ELW$+%EXV &K &K '0$B&0$5>@ EGPDBWFLI>@ '0$B&3$5>@ EGPDBLW>@ $UELWHU $+%VODYH FRQILJXUDWLRQSRUW ELW$+%EXV EGPDBUHT>@ '0$B&&5>@ '0$B&1'75>@ 06Y 9 The BDMA controller performs direct memory transfer by sharing the system bus with other system masters. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. 16.3.1 BDMA transactions After an event, the peripheral sends a request signal to the BDMA Controller. The BDMA controller serves the request depending on the channel priorities. As soon as the BDMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the BDMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the BDMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each BDMA transfer consists of three operations: • 622/3178 The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the BDMA_CPARx or BDMA_CMARx register. DocID029587 Rev 3 RM0433 16.3.2 Basic direct memory access controller (BDMA) • The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the BDMA_CPARx or BDMA_CMARx register. • The post-decrementing of the BDMA_CNDTRx register, which contains the number of transactions that have still to be performed. Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: • Software: each channel priority can be configured in the BDMA_CCRx register. There are four levels: – • 16.3.3 Very high priority – High priority – Medium priority – Low priority Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4. BDMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction. Programmable data sizes Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the BDMA_CCRx register. Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the BDMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the BDMA_CPARx/BDMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the BDMA_CNDTRx register, the DMA channel must be disabled. DocID029587 Rev 3 623/3178 635 Basic direct memory access controller (BDMA) Note: RM0433 If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (BDMA_CCRx, BDMA_CPARx and BDMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the BDMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the BDMA_CPARx/BDMA_CMARx registers. Channel configuration procedure The following sequence should be followed to configure a DMA channel x (where x is the channel number). 1. Set the peripheral register address in the BDMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. 2. Set the memory address in the BDMA_CMARx register. The data will be written to or read from this memory after the peripheral event. 3. Configure the total number of data to be transferred in the BDMA_CNDTRx register. After each peripheral event, this value will be decremented. 4. Configure the channel priority using the PL[1:0] bits in the BDMA_CCRx register 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the BDMA_CCRx register 6. Activate the channel by setting the ENABLE bit in the BDMA_CCRx register. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel. Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set. Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the BDMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode. If the MEM2MEM bit in the BDMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the BDMA_CCRx register. The transfer stops once the BDMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 624/3178 DocID029587 Rev 3 RM0433 Basic direct memory access controller (BDMA) 16.3.4 Programmable data width, data alignment and endianness When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 106: Programmable data width & endianness (when bits PINC = MINC = 1). Table 106. Programmable data width & endianness (when bits PINC = MINC = 1) Number Source of data Destination port items to port width width transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 8 8 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 8 16 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B2[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B3[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 8 32 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B2[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B3[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 16 8 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 16 16 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 16 32 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 32 8 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC 32 16 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[15:0] @0x2 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[15:0] @0x4 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[15:0] @0x6 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC 32 32 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC DocID029587 Rev 3 625/3178 635 Basic direct memory access controller (BDMA) RM0433 Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: • To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord • To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner: • An AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0 • An AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0 For instance, to write the APB backup registers (16-bit registers aligned to a 32-bit address boundary), the software must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”. 16.3.5 Error management A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (BDMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the BDMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the BDMA_CCRx register is set. 16.3.6 BDMA interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 107. BDMA interrupt requests Interrupt event Event flag Enable control bit Half-transfer HTIF HTIE Transfer complete TCIF TCIE Transfer error TEIF TEIE The BDMA request mapping is in Section 17.3.3: DMAMUX2 mapping. 626/3178 DocID029587 Rev 3 RM0433 Basic direct memory access controller (BDMA) 16.4 BDMA registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit). 16.4.1 DMA interrupt status register (BDMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEIF8 HTIF8 TCIF8 GIF8 TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 r r r r r r r r r r r r r r r r Bits 31, 27, 23, 19, TEIFx: Channel x transfer error flag (x = 1..8) 15, 11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the BDMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x Bits 30, 26, 22, 18, HTIFx: Channel x half transfer flag (x = 1..8) 14, 10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the BDMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x Bits 29, 25, 21, 17, TCIFx: Channel x transfer complete flag (x = 1..8) 13, 9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the BDMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x Bits 28, 24, 20, 16, GIFx: Channel x global interrupt flag (x = 1..8) 12, 8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the BDMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x DocID029587 Rev 3 627/3178 635 Basic direct memory access controller (BDMA) 16.4.2 RM0433 DMA interrupt flag clear register (BDMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CTEIF8 CHTIF8 CTCIF8 CGIF8 CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 w w w w w w w w w w w w w Bits 31, 27, 23, 19, CTEIFx: Channel x transfer error clear (x = 1..8) 15, 11, 7, 3 This bit is set by software. 0: No effect 1: Clears the corresponding TEIF flag in the BDMA_ISR register Bits 30, 26, 22, 18, CHTIFx: Channel x half transfer clear (x = 1..8) 14, 10, 6, 2 This bit is set by software. 0: No effect 1: Clears the corresponding HTIF flag in the BDMA_ISR register Bits 29, 25, 21, 17, CTCIFx: Channel x transfer complete clear (x = 1..8) 13, 9, 5, 1 This bit is set by software. 0: No effect 1: Clears the corresponding TCIF flag in the BDMA_ISR register Bits 28, 24, 20, 16, CGIFx: Channel x global interrupt clear (x = 1..8) 12, 8, 4, 0 This bit is set by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the BDMA_ISR register 628/3178 DocID029587 Rev 3 w w w RM0433 Basic direct memory access controller (BDMA) 16.4.3 DMA channel x configuration register (BDMA_CCRx) (x = 1..8, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. MEM2 MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw PL[1:0] rw rw MSIZE[1:0] PSIZE[1:0] rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled Bits 13:12 PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high Bits 11:10 MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bits 9:8 PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bit 7 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled Bit 6 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled DocID029587 Rev 3 629/3178 635 Basic direct memory access controller (BDMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 1 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 0 EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled 630/3178 DocID029587 Rev 3 RM0433 RM0433 Basic direct memory access controller (BDMA) 16.4.4 DMA channel x number of data register (BDMA_CNDTRx) (x = 1..8, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NDT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in circular mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 16.4.5 DMA channel x peripheral address register (BDMA_CPARx) (x = 1..8, where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw PA [15:0] rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. DocID029587 Rev 3 631/3178 635 Basic direct memory access controller (BDMA) 16.4.6 RM0433 DMA channel x memory address register (BDMA_CMARx) (x = 1..8, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw MA [15:0] rw Bits 31:0 MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. 632/3178 DocID029587 Rev 3 0x34 0x38 0x3C BDMA_CNDTR3 Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEM2MEM Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. Res. MEM2MEM Res. Res. Res. Res. Res. Res. Res. 0 0 0 BDMA_CPAR3 BDMA_CMAR3 0 0 0 Reset value 0 0 DocID029587 Rev 3 0 0 0 0 PL [1:0] 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PINC CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] MSIZE [1:0] MINC 0 Res. 0 0 EN 0 PL [1:0] Res. Res. Res. TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDMA_IFCR CTEIF8 CHTIF8 CTCIF8 CGIF8 CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGIF4 HTIF4 0 CTCIF4 0 CHTIF4 GIF5 TEIF4 0 MEM2MEM TCIF5 0 CTEIF4 HTIF5 0 Res. GIF6 TEIF5 0 CGIF5 Res. Res. Res. TCIF6 0 CTCIF3 CTCIF1 CGIF1 0 0 0 MINC 0 EN CHTIF1 0 TCIE CTEIF1 0 HTIE CGIF2 0 TEIE CTCIF2 0 DIR CHTIF2 0 PINC CTEIF2 0 CIRC CGIF3 PSIZE [1:0] CHTIF3 MSIZE [1:0] CTEIF3 0 Res. 0 Res. Res. HTIF6 0 0 Res. 0 Res. Res. Res. Res. Res. 0 0 TCIE Reset value 0 0 HTIE BDMA_CPAR2 0 0 Res. 0 Res. 0 0 TEIE 0 Res. Res. 0 Res. 0 Res. Reset value PL [1:0] DIR 0 Res. Res. Res. GIF7 TEIF6 0 0 Res. 0 Res. TCIF7 0 0 Res. 0 Res. HTIF7 0 0 PINC 0 Res. Res. GIF8 TEIF7 0 0 CIRC 0 Res. Res. TCIF8 0 0 Res. 0 Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF8 HTIF8 Reset value 0 MINC 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. BDMA_ISR 0 PSIZE [1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Register name 0 MSIZE [1:0] 0 Res. Reset value Res. 0 Res. 0 Res. 0 Res. BDMA_CMAR1 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. BDMA_CPAR1 Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value 0 Res. 0 Res. 0 Res. Reset value 0 Res. BDMA_CCR3 0 Res. 0x30 BDMA_CMAR2 0 Res. 0x2C Reset value 0 Res. 0x28 BDMA_CNDTR2 0 Res. 0x24 BDMA_CCR2 0 Res. 0x20 Reset value Res. 0x1C 0 Res. 0x18 Reset value Res. 0x14 BDMA_CNDTR1 Res. 0x10 BDMA_CCR1 Res. 0x0C Res. 0x08 Res. 0x04 Res. 0x00 Res. Offset Res. 16.4.7 Res. RM0433 Basic direct memory access controller (BDMA) BDMA register map The following table gives the DMA register map and the reset values. Table 108. BDMA register map and reset values 0 0 0 0 0 0 0 NDT[15:0] PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT[15:0] PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 NDT[15:0] PA[31:0] MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633/3178 635 0x84 BDMA_CNDTR7 634/3178 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. Res. Res. Res. Res. Res. MEM2MEM Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 Reserved Res. Res. MEM2MEM Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 Reset value DocID029587 Rev 3 0 0 0 PL [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. PINC CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] MSIZE [1:0] MINC 0 Res. 0 0 EN 0 PL [1:0] Res. Reset value 0 TCIE BDMA_CPAR6 0 Res. 0 Res. 0 HTIE 0 Res. 0 Res. 0 Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEM2MEM Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PINC CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] MSIZE [1:0] MINC 0 TEIE 0 Res. 0 0 Res. 0 Res. Res. 0 0 DIR 0 Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PINC CIRC DIR TEIE HTIE TCIE EN Res. Res. Res. Res. MINC PSIZE [1:0] MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MEM2MEM Res. 0 Res. 0 Res. Res. 0 0 0 CIRC 0 Res. Res. 0 PL [1:0] 0 Res. 0 Res. BDMA_CMAR5 0 0 PINC 0 Res. Res. 0 Res. 0 0 Res. 0 Res. Reset value 0 MINC 0 Res. BDMA_CPAR5 0 0 PSIZE [1:0] 0 Res. Res. 0 Res. Res. Res. Reset value PL [1:0] MSIZE [1:0] 0 Res. 0 Res. Reset value Res. 0 Res. Res. 0 Res. BDMA_CMAR4 Res. 0 Res. Res. 0 Res. Reset value Reset value Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. BDMA_CPAR4 Res. 0 Res. Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. Res. 0 Res. 0 0 Res. 0 Res. Res. 0 Res. 0 0 Res. 0 Res. Res. 0 Res. Reset value Reset value Res. 0 0 Res. 0 Res. Res. Res. 0 0 Res. Reset value 0 Res. BDMA_CCR7 0 Res. 0x7C 0 Res. BDMA_CMAR6 0 Res. Reset value 0 0 Res. 0x80 BDMA_CNDTR6 0 0 Res. 0x78 BDMA_CCR6 0 0 Res. 0x74 Res. 0x68 0 Res. 0x70 Reset value Res. 0x6C BDMA_CNDTR5 0 Res. 0x64 BDMA_CCR5 0 Res. 0x60 Res. 0x5C Res. 0x54 0 Res. 0x58 Reset value Res. 0x50 BDMA_CNDTR4 Res. 0x4C BDMA_CCR4 Res. 0x48 Res. 0x44 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Res. 0x40 Res. Register name Res. Offset Res. Basic direct memory access controller (BDMA) RM0433 Table 108. BDMA register map and reset values (continued) 0 0 0 0 0 0 0 0 NDT[15:0] PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT[15:0] PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT[15:0] PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 NDT[15:0] 0 0 0 0 0 0 0 0 RM0433 Basic direct memory access controller (BDMA) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xA0 Res. Res. EN Res. Res. Res. Res. TCIE Res. Res. Res. Res. Res. HTIE Res. Res. Res. Res. Res. TEIE Res. Res. Res. Res. Res. DIR Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDMA_CMAR8 Reset value 0 CIRC Res. Reset value 0 NDT[15:0] 0 BDMA_CPAR8 0 Res. Res. Res. Reset value 0x9C 0 PINC Res. Res. Res. Res. BDMA_CNDTR8 Res. 0x98 Res. Reset value PL [1:0] MINC Reserved PSIZE [1:0] 0 MSIZE [1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. MA[31:0] Reset value BDMA_CCR8 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 MEM2MEM Res. 0 Res. 0x94 Reset value BDMA_CMAR7 Res. 0x90 PA[31:0] Res. 0x8C BDMA_CPAR7 Res. 0x88 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 108. BDMA register map and reset values (continued) 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 635/3178 635 DMA request multiplexer (DMAMUX) RM0433 17 DMA request multiplexer (DMAMUX) 17.1 Introduction A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is de-asserted. In this document, the set of control signals required for the DMA request/acknowledge protocol is not explicitly shown or described, and it is referred to as DMA request line. The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controllers of the product. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. The DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals. The number of DMAMUX instances and their main characteristics are specified in Section 17.3.1. The assignment of DMAMUX request multiplexer inputs to the DMA request lines from peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX synchronizations and trigger inputs to internal and external signals depend on the product implementation, and are detailed in Section 17.3.2. 17.2 DMAMUX main features • Up to 16-channel programmable DMA request line multiplexer output • Up to 8-channel DMA request generator • Up to 32 trigger inputs to DMA request generator • Up to 16 synchronization inputs • Per DMA request generator channel: • 636/3178 – DMA request trigger input selector – DMA request counter – Event overrun flag for selected DMA request trigger input Per DMA request line multiplexer channel output: – Up to 107 input DMA request lines from peripherals – One DMA request line output – Synchronization input selector – DMA request counter – Event overrun flag for selected synchronization input – One event output, for DMA request chaining DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) 17.3 DMAMUX implementation 17.3.1 DMAMUX1 and DMAMUX2 instantiation The product integrates two instances of DMA request multiplexer: • DMAMUX1 for DMA1 and DMA2 (D2 domain) • DMAMUX2 for BDMA (D3 domain) DMAMUX1 and DMAMUX2 are instantiated with the hardware configuration parameters listed in the following table. Table 109. DMAMUX1 and DMAMUX2 instantiation 17.3.2 Feature DMAMUX1 DMAMUX2 Number of DMAMUX output request channels 16 8 Number of DMAMUX request generator channels 8 8 Number of DMAMUX request trigger inputs 8 32 Number of DMAMUX synchronization inputs 8 16 Number of DMAMUX peripheral request inputs 107 12 DMAMUX1 mapping The mapping of resources to DMAMUX1 is hardwired. DMAMUX1 is used with the DMA1 and DMA2 in D2 domain: • DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7 • DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7 Table 110. DMAMUX1: assignment of multiplexer inputs to resources DMA request MUX input Resource DMA request MUX input Resource DMA request MUX input Resource 1 dmamux1_req_gen0 40 SPI2_TX 79 UART7_RX 2 dmamux1_req_gen1 41 USART1_RX 80 UART7_TX 3 dmamux1_req_gen2 42 USART1_TX 81 UART8_RX 4 dmamux1_req_gen3 43 USART2_RX 82 UART8_TX 5 dmamux1_req_gen4 44 USART2_TX 83 SPI4_RX 6 dmamux1_req_gen5 45 USART3_RX 84 SPI4_TX 7 dmamux1_req_gen6 46 USART3_TX 85 SPI5_RX 8 dmamux1_req_gen7 47 TIM8_CH1 86 SPI5_TX 9 ADC1 48 TIM8_CH2 87 SAI1_A 10 ADC2 49 TIM8_CH3 88 SAI1_B 11 TIM1_CH1 50 TIM8_CH4 89 SAI2_A 12 TIM1_CH2 51 TIM8_UP 90 SAI2_B 13 TIM1_CH3 52 TIM8_TRIG 91 SWPMI_RX DocID029587 Rev 3 637/3178 656 DMA request multiplexer (DMAMUX) RM0433 Table 110. DMAMUX1: assignment of multiplexer inputs to resources (continued) DMA request MUX input Resource DMA request MUX input Resource DMA request MUX input Resource 14 TIM1_CH4 53 TIM8_COM 92 SWPMI_TX 15 TIM1_UP 54 Reserved 93 SPDIFRX_DT 16 TIM1_TRIG 55 TIM5_CH1 94 SPDIFRX_CS 17 TIM1_COM 56 TIM5_CH2 95 HR_REQ(1) 18 TIM2_CH1 57 TIM5_CH3 96 HR_REQ(2) 19 TIM2_CH2 58 TIM5_CH4 97 HR_REQ(3) 20 TIM2_CH3 59 TIM5_UP 98 HR_REQ(4) 21 TIM2_CH4 60 TIM5_TRIG 99 HR_REQ(5) 22 TIM2_UP 61 SPI3_RX 100 HR_REQ(6) 23 TIM3_CH1 62 SPI3_TX 101 dfsdm1_dma0 24 TIM3_CH2 63 UART4_RX 102 dfsdm1_dma1 25 TIM3_CH3 64 UART4_TX 103 dfsdm1_dma2 26 TIM3_CH4 65 USART5_RX 104 dfsdm1_dma3 27 TIM3_UP 66 UART5_TX 105 TIM15_CH1 28 TIM3_TRIG 67 DAC1 106 TIM15_UP 29 TIM4_CH1 68 DAC2 107 TIM15_TRIG 30 TIM4_CH2 69 TIM6_UP 108 TIM15_COM 31 TIM4_CH3 70 TIM7_UP 109 TIM16_CH1 32 TIM4_UP 71 USART6_RX 110 TIM16_UP 33 I2C1_RX 72 USART6_TX 111 TIM17_CH1 34 I2C1_TX 73 I2C3_RX 112 TIM17_UP 35 I2C2_RX 74 I2C3_TX 113 SAI3_A 36 I2C2_TX 75 DCMI 114 SAI3_B 37 SPI1_RX 76 CRYP_IN 115 ADC3 38 SPI1_TX 77 CRYP_OUT - - 39 SPI2_RX 78 HASH_IN - - Table 111. DMAMUX1: assignment of trigger inputs to resources 638/3178 Trigger input Resource Trigger input Resource 0 dmamux1_evt0 4 LPTIMER2_out 1 dmamux1_evt1 5 LPTIMER3_out 2 dmamux1_evt2 6 extit0 3 LPTIMER1_out 7 TIM12_TRGO DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) Table 112. DMAMUX1: assignment of synchronization inputs to resources 17.3.3 Sync. input Resource Sync. input Resource 0 dmamux1_evt0 4 LPTIMER2_out 1 dmamux1_evt1 5 LPTIMER3_out 2 dmamux1_evt2 6 extit0 3 LPTIMER1_out 7 TIM12_TRGO DMAMUX2 mapping DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7. Table 113. DMAMUX2: assignment of multiplexer inputs to resources DMA request MUX input Resource DMA request MUX input Resource 1 dmamux2_req_gen0 11 SPI6_RX 2 dmamux2_req_gen1 12 SPI6_TX 3 dmamux2_req_gen2 13 I2C4_RX 4 dmamux2_req_gen3 14 I2C4_TX 5 dmamux2_req_gen4 15 SAI4_A 6 dmamux2_req_gen5 16 SAI4_B 7 dmamux2_req_gen6 17 ADC3_REQ 8 dmamux2_req_gen7 18 Reserved 9 LP UART1_RX 19 Reserved 10 LP UART1_TX 20 Reserved Table 114. DMAMUX2: assignment of trigger inputs to resources Trigger input Resource Trigger input Resource 0 dmamux2_evt0 16 Spi6_it_async 1 dmamux2_evt1 17 Comp1_out 2 dmamux2_evt2 18 Comp2_out 3 dmamux2_evt3 19 RTC_wkup 4 dmamux2_evt4 20 Syscfg_exti0_mux 5 dmamux2_evt5 21 Syscfg_exti2_mux 6 dmamux2_evt6 22 I2c4_it_event 7 Lpuart1_it_R_WUP_ASYNC 23 Spi6_it 8 Lpuart1_it_T_WUP_ASYNC 24 Lpuart1_it_T 9 Lptim2_ait 25 Lpuart1_it_R 10 Lptim2_out 26 ADC3_it 11 Lptim3_ait 27 ADC3_AWD1_out DocID029587 Rev 3 639/3178 656 DMA request multiplexer (DMAMUX) RM0433 Table 114. DMAMUX2: assignment of trigger inputs to resources (continued) Trigger input Resource Trigger input Resource 12 Lptim3_out 28 DMA1_D3_ch0_it 13 Lptim4_ait 29 DMA1_D3_ch1_it 14 Lptim5_ait 30 Reserved 15 I2c4_it_async 31 Reserved Table 115. DMAMUX2: assignment of synchronization inputs to resources 640/3178 Sync input Resource Sync input Resource 0 dmamux2_evt0 8 Lptim2_out 1 dmamux2_evt1 9 Lptim3_out 2 dmamux2_evt2 10 I2c4_it_async 3 dmamux2_evt3 11 Spi6_it_async 4 dmamux2_evt4 12 Comp1_out 5 dmamux2_evt5 13 RTC_wkup 6 Lpuart1_it_R_WUP_ASYNC 14 Syscfg_exti0_mux 7 Lpuart1_it_T_WUP_ASYNC 15 Syscfg_exti2_mux DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) 17.4 DMAMUX functional description 17.4.1 DMAMUX block diagram Figure 75 shows the DMAMUX block diagram. Figure 75. DMAMUX block diagram ELW$+%EXV GPDPX[BKFON 7R7UXVW=RQHLQWHUUXSW FRQWUROOHU GPDPX[BVHFBLODF '0$08; 5HTXHVWPXOWLSOH[HU $+%VODYH LQWHUIDFH &KDQQHOP '0$08;B&P&5 &KDQQHO S T[ X[ BUH &KDQQHO &WUO VHOHFW GP P &KDQQHO '0$08;B&&5 DP '0$UHTXHVWV IURPSHULSKHUDOV GPDPX[BUHTBLQ[ QS 5HTXHVWJHQHUDWRU W &RQWUROUHJLVWHUV Q &KDQQHO '0$08;B5*&&5 &KDQQHO '0$08;B5*&&5 ,QWHUUXSW LQWHUIDFH 7ULJJHULQSXWV GPDPX[BWUJ[ P '0$UHTXHVWV WR'0$FRQWUROOHUV GPDPX[BUHTBRXW[ P '0$FKDQQHOV HYHQWV GPDPX[BHYW[ Q GPDPX[BUHTBJHQ[ &KDQQHOQ '0$08;B5*&Q&5 6HFXUHDQGSULYLOHJHG VWDWHRIWKH'0$ FKDQQHOV GPDBVHFP[ GPDBSULY[ 6\QF Q Q V V ,QWHUUXSWV GPDPX[BVHFBRYUBLW 6\QFKURQL]DWLRQLQSXWV GPDPX[BV\QF[ GPDPX[BQRQVHFBRYUBLW 06Y 9 DMAMUX features two main sub-blocks: the request line multiplexer and the request line generator. The implementation assigns: • DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals (dmamux_req_inx) and from channels of the DMAMUX request generator sub-block (dmamux_req_genx) • DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx) • Internal or external signals to DMA request trigger inputs (dmamux_trgx) • Internal or external signals to synchronization inputs (dmamux_syncx) DocID029587 Rev 3 641/3178 656 DMA request multiplexer (DMAMUX) 17.4.2 RM0433 DMAMUX signals Table 116 lists DMAMUX signals. Table 116. DMAMUX signals Signal name dmamux_hclk dmamux_req_inx dmamux_trgx dmamux_req_genx dmamux_reqx dmamux_syncx dmamux_req_outx dmamux_evtx dmamux_ovr_it 17.4.3 Description DMAMUX AHB clock DMAMUX DMA request line inputs from peripherals DMAMUX DMA request triggers inputs (to request generator subblock) DMAMUX request generator sub-block channels outputs DMAMUX request multiplexer sub-block inputs (from peripheral requests and request generator channels) DMAMUX synchronization inputs (to request multiplexer sub-block) DMAMUX requests outputs (to DMA controllers) DMAMUX events outputs DMAMUX overrun interrupts DMAMUX channels A DMAMUX channel is a DMAMUX request multiplexer channel that may include, depending on the selected input of the request multiplexer, an additional DMAMUX request generator channel. A DMAMUX request multiplexer channel is connected and dedicated to one single channel of DMA controller(s). Channel configuration procedure The following sequence should be followed to configure both a DMAMUX x channel and the related DMA channel y: 17.4.4 1. Set and configure completely the DMA channel y, except enabling the channel y. 2. Set and configure completely the related DMAMUX y channel. 3. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register. DMAMUX request line multiplexer The DMAMUX request multiplexer with its multiple channels ensures the actual routing of DMA request/acknowledge control signals, named DMA request lines. Each DMA request line is connected in parallel to all the channels of the DMAMUX request line multiplexer. A DMA request is sourced either from the peripherals or from the DMAMUX request generator. The DMAMUX request line multiplexer channel x selects the DMA request line number as configured by the 8-bit DMAREQ_ID field in the DMAMUX_CxCR register. 642/3178 DocID029587 Rev 3 RM0433 Note: DMA request multiplexer (DMAMUX) The null value in the field DMAREQ_ID corresponds to no DMA request line selected. The same non-null DMA_REQ_ID value shall not be programmed to different x and y DMAMUX request multiplexer channels (via DMAMUX_CxCR and DMAMUX CyCR). It is not allowed to configure a same non-null DMAREQ_ID to two different channels of the DMAMUX request line multiplexer. On top of the DMA request selection, the synchronization mode and/or the event generation may be configured and enabled, if required. Synchronization mode and channel event generation Each DMAMUX request line multiplexer channel x can be individually synchronized by setting the synchronization enable (SE) bit in the DMAMUX_CxCR register. DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in parallel to all the channels of the request multiplexer. The synchronization input is selected via the 5-bit SYNC_ID field in the DMAMUX_CxCR register of a given channel x. When a channel is in this synchronization mode, the selected input DMA request line is propagated to the multiplexer channel output, once is detected a programmable rising/falling edge on the selected input synchronization signal, via the SPOL[1:0] field of the DMAMUX_CxCR register. Additionally, there is a programmable DMA request counter, internally to the DMAMUX request multiplexer, which may be used for the channel request output generation and also possibly for an event generation. An event generation on the channel x output is enabled through the EGE bit (event generation enable) of the DMAMUX_CxCR register. As shown in the two next figures, upon the detected edge of the synchronization input, the selected input DMA request line is connected to the DMAMUX multiplexer channel x output. From this point on, each served DMA request (for example when the request signal is deasserted) on the selected DMAMUX request line decrements the DMA request counter. At its underrun, the DMA request counter is automatically loaded with the value in NBREQ field of the DMAMUX_CxCR register and the input DMA request line is disconnected from the multiplexer channel x output. Thus, the number of DMA requests transferred to the multiplexer channel x output following a detected synchronization event, is equal to the value in NBREQ field, plus one. Note: The NBREQ field value shall only be written by software when both synchronization enable bit SE and event generation enable EGE bit of the corresponding multiplexer channel x are disabled. If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one AHB clock cycle, when its DMA request counter is automatically reloaded with the value of the programmed NBREQ field. DocID029587 Rev 3 643/3178 656 DMA request multiplexer (DMAMUX) RM0433 Figure 76. Synchronization mode of the DMAMUX request line multiplexer channel 6HOHFWHG'0$UHTXHVWOLQHWUDQVIHUUHGWRWKHRXWSXW '0$UHTXHVWVVHUYHG '0$UHTXHVWSHQGLQJ 6HOHFWHG GPDPX[BUHT[ 1RWSHQGLQJ GPDPX[BV\QF[ GPDPX[BUHTBRXW[ '0$UHTXHVWFRXQWHU GPDPX[BHYW[ '0$UHTXHVWFRXQWHUXQGHUUXQ '0$UHTXHVWFRXQWHUDXWRUHORDGWR1%5(4 ,QSXW'0$UHTXHVWOLQHGLVFRQQHFWHGIURPRXWSXW 6\QFKURQL]DWLRQHYHQW ,QSXW'0$UHTXHVWOLQHFRQQHFWHGWRRXWSXW ([DPSOH '0$08;B&&5[FRQILJXUHGZLWK 1%5(4 6( (*( 632/ ULVLQJHGJH 06Y 9 Figure 77. Event generation of the DMA request line multiplexer channel 6HOHFWHG'0$UHTXHVWOLQHWUDQVIHUUHGWRWKHRXWSXW 6HOHFWHG GPDPX[BUHT[ '0$UHTXHVWSHQGLQJ 1RWSHQGLQJ GPDPX[BUHTBRXW[ '0$UHTXHVWFRXQWHU 6( (*( GPDPX[BHYW[ '0$UHTXHVWFRXQWHUUHDFKHV]HUR (YHQWLVJHQHUDWHGRQWKHRXWSXW '0$UHTXHVWFRXQWHUDXWRUHORDGVZLWK1%5(4YDOXH ([DPSOHZLWK '0$08;B&&5[FRQILJXUHGZLWK 1%5(4 6( (*( 06Y 9 Note: 644/3178 A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles. Synchronization overrun and interrupt If a new synchronization event occurs while the value of the DMA request counter is lower than the programmed NBREQ field value of the multiplexer channel x, the synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register. Note: The request multiplexer channel x synchronization shall be disabled (DMAMUX_CxCR.SE=0) at the completion of the usage of the related channel of the DMA controller. Else, upon a new detected synchronization event, there will be a synchronization overrun due to the absence of a DMA acknowledge (a.k.a. no served request) received from the DMA controller. The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag bit CSOFx in the DMAMUX_CFR register. Setting the synchronization overrun flag generates an interrupt if the synchronization overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register. 17.4.5 DMAMUX request generator The DMAMUX request generator produces DMA requests following trigger events on its DMA request trigger inputs. The DMAMUX request generator has multiple channels. DMA request trigger inputs are connected in parallel to all channels. The outputs of DMAMUX request generator channels are inputs to the DMAMUX request line multiplexer. Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the corresponding DMAMUX_RGxCR register. The DMA request trigger input for the DMAMUX request generator channel x is selected through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register. Trigger events on a DMA request trigger input can be rising edge, falling edge or either edge. The active edge is selected through the GPOL (generator polarity) field in the corresponding DMAMUX_RGxCR register. Upon the trigger event, the corresponding generator channel starts generating DMA requests on its output. Each served DMA request (i.e. when the request signal is deasserted) decrements a built-in DMA request counter, internally to the DMAMUX request generator. At its underrun, the DMA request counter is automatically loaded with the value in GNBREQ field of the corresponding DMAMUX_RGxCR register and the request generator channel stops generating DMA requests. Thus, the number of DMA requests generated after the trigger event is GNBREQ+1. The DMA request counter is kept at GNBREQ field value as long as the corresponding channel is disabled i.e. the DMAMUX_RGxCR.GE bit is low. DocID029587 Rev 3 645/3178 656 DMA request multiplexer (DMAMUX) Note: RM0433 The GNBREQ field value shall only be written by software when the enable GE bit of the corresponding generator channel x is disabled. A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three AHB clock cycles. Trigger overrun and interrupt If a new DMA request trigger event occurs while the value of the DMAMUX request generator counter is lower than the programmed GNBREQ field value of the corresponding request generator channel x, and if the request generator channel x was enabled via GE, then the request trigger event overrun flag bit OFx is asserted by the hardware in the status DMAMUX_RGSR register. Note: The request generator channel x shall be disabled (DMAMUX_RGxCR.GE=0) at the completion of the usage of the related channel of the DMA controller. Else, upon a new detected trigger event, there will be a trigger overrun due to the absence of an acknowledge (a.k.a. no served request) received from the DMA. The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the DMAMUX_RGCFR register. Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register. 17.5 DMAMUX interrupts An interrupt can be generated upon: • a synchronization event overrun in each DMA request line multiplexer channel • a trigger event overrun in each DMA request generator channel For each case, per-channel individual interrupt enable, status and clear flag register bits are available. Table 117. DMAMUX interrupts Interrupt signal dmamuxovr_it 646/3178 Interrupt event Event flag Clear bit Enable bit Synchronization event overrun on channel x of the DMAMUX request line multiplexer SOFx CSOFx SOIE Trigger event overrun on channel x of the DMAMUX request generator OFx COFx OIE DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) 17.6 DMAMUX registers Refer to the table containing register boundary addresses for the DMAMUX1 and DMAMUX2 base address. DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word. The address shall be aligned with the data size. 17.6.1 DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR) Address offset: 0x04 * x (x = 0 to 15) Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 28 27 26 25 24 23 22 21 20 19 18 17 16 SYNC_ID[4:0] NBREQ[4:0] SPOL[1:0] SE rw rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. EGE SOIE 7 6 5 DMAREQ_ID[7:0] 4 3 rw rw rw 2 1 0 Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SYNC_ID[4:0]: Synchronization identification Selects the synchronization input (see Table 112: DMAMUX1: assignment of synchronization inputs to resources). Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. Bits 18:17 SPOL[1:0]: Synchronization polarity Defines the edge polarity of the selected synchronization input: 00: no event, i.e. no synchronization nor detection. 01: rising edge 10: falling edge 11: rising and falling edge Bit 16 SE: Synchronization enable 0: synchronization disabled 1: synchronization enabled Bits 15:10 Reserved, must be kept at reset value. Bit 9 EGE: Event generation enable 0: event generation disabled 1: event generation enabled Bit 8 SOIE: Synchronization overrun interrupt enable 0: interrupt disabled 1: interrupt enabled Bits 7:0 DMAREQ_ID[7:0]: DMA request identification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources. DocID029587 Rev 3 647/3178 656 DMA request multiplexer (DMAMUX) 17.6.2 RM0433 DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR) Address offset: 0x04 * x, where x = 0 to 7 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. EGE SOIE DMAREQ_ID[7:0] rw rw rw SYNC_ID[4:0] 21 20 19 NBREQ[4:0] rw rw 7 6 5 4 3 18 17 16 SPOL[1:0] SE rw rw 2 1 0 Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SYNC_ID[4:0]: Synchronization identification Selects the synchronization input. (C.f. table: DMAMUX- assignments of synchronization inputs to resources) Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low. Bits 18:17 SPOL[1:0]: Synchronization polarity Defines the edge polarity of the selected synchronization input: 00: no event. I.e. None synchronization nor detection. 01: rising edge 10: falling edge 11: rising and falling edge Bit 16 SE: Synchronization enable 0: synchronization disabled 1: synchronization enabled Bits 15:10 Reserved, must be kept at reset value. Bit 9 EGE: Event generation enable 0: event generation disabled 1: event generation enabled Bit 8 SOIE: Synchronization overrun interrupt enable 0: interrupt disabled 1: interrupt enabled Bits 7:0 DMAREQ_ID[7:0]: DMA request identification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources. 648/3178 DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) 17.6.3 DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR) Address offset: 0x080 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOF15 SOF14 SOF13 SOF12 SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 SOF[15:0]: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. For DMAMUX2_CFR bits 15:8 are reserved. 17.6.4 DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR) Address offset: 0x080 Reset value: 0x0000 0000 This register shall be accessed at bit level by a non-secure or secure read, according to the secure mode of the considered DMAMUX2 request line multiplexer channel x, depending on the secure control bit of the connected DMA controller channel y, and considering that the DMAMUX2 x channel output is connected to the y channel of the DMA (refer to the DMAMXUX2 mapping implementation section). This register shall be accessed at bit level by an unprivileged or privileged read, according to the privileged mode of the considered DMAMUX2 request line multiplexer channel x, depending on the privileged control bit of the connected DMA controller channel y, and considering that the DMAMUX2 x channel output is connected to the y channel of the DMA (refer to the DMAMXUX2 mapping implementation section). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 r r r r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 SOF[7:0]: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX2_CFR register. DocID029587 Rev 3 649/3178 656 DMA request multiplexer (DMAMUX) 17.6.5 RM0433 DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR) Address offset: 0x084 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSOF 15 CSOF 14 CSOF 13 CSOF 12 CSOF 11 CSOF 10 CSOF 9 CSOF 8 CSOF 7 CSOF 6 CSOF 5 CSOF 4 CSOF 3 CSOF 2 CSOF 1 CSOF 0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CSOF[15:0]: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. 17.6.6 DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) Address offset: 0x084 Reset value: 0x0000 0000 This register shall be written at bit level by a non-secure or secure write, according to the secure mode of the considered DMAMUX request line multiplexer channel x, depending on the secure control bit of the connected DMA controller channel y, and considering that the DMAMUX x channel output is connected to the y channel of the DMA (refer to the DMAMXUX mapping implementation section). This register shall be written at bit level by an unprivileged or privileged write, according to the privileged mode of the considered DMAMUX request line multiplexer channel x, depending on the privileged control bit of the connected DMA controller channel y, and considering that the DMAMUX x channel output is connected to the y channel of the DMA (refer to the DMAMXUX mapping implementation section). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. CSOF6 CSOF6 CSOF5 CSOF4 CSOF3 CSOF2 CSOF1 CSOF0 w w w w w w w Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 CSOF[7:0]: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX2_CSR register. 650/3178 DocID029587 Rev 3 w RM0433 DMA request multiplexer (DMAMUX) 17.6.7 DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) Address offset: 0x100 + 0x04 * (x-0) (x = 0 to 7) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. 20 19 GNBREQ[4:0] 18 17 16 GPOL[1:0] GE rw rw rw 4 rw 3 2 1 0 SIG_ID[4:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ+1. Note: This field shall only be written when GE bit is disabled. Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 00: no event. I.e. none trigger detection nor generation. 01: rising edge 10: falling edge 11: rising and falling edge Bit 16 GE: DMA request generator channel x enable 0: DMA request generator channel x disabled 1: DMA request generator channel x enabled Bits 15:9 Reserved, must be kept at reset value. Bit 8 OIE: Trigger overrun interrupt enable 0: interrupt on a trigger overrun event occurrence is disabled 1: interrupt on a trigger overrun event occurrence is enabled Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 SIG_ID[4:0]: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 17.6.8 DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR) Address offset: 0x100 + 0x04 * (x-0) (x = 0 to 7) Reset value: 0x0000 0000 This register shall be written by a non-secure or secure write, according to the secure mode of the considered DMAMUX request line multiplexer channel y it is assigned to, and considering that the DMAMUX request generator x channel output is selected by the y channel of the DMAMUX request line channel (see DMAMUX2_CyCR.DMAREQ_ID[7:0] and the DMAMUX mapping implementation section). DocID029587 Rev 3 651/3178 656 DMA request multiplexer (DMAMUX) RM0433 This register shall be written by an unprivileged or privileged write, according to the privileged mode of the considered DMAMUX request line multiplexer channel y it is assigned to, and considering that the DMAMUX request generator x channel output is selected by the y channel of the DMAMUX request line channel (see DMAMUX2_CyCR.DMAREQ_ID[7:0] and the DMAMXUX mapping implementation section). 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 17 16 GNBREQ[4:0] 21 GPOL[1:0] GE rw rw rw 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. 20 4 rw 19 3 18 2 1 0 SIG_ID[4:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ+1. Note: This field shall only be written when GE bit is disabled. Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 00: no event. I.e. none trigger detection nor generation. 01: rising edge 10: falling edge 11: rising and falling edge Bit 16 GE: DMA request generator channel x enable 0: DMA request generator channel x disabled 1: DMA request generator channel x enabled Bits 15:9 Reserved, must be kept at reset value. Bit 8 OIE: Trigger overrun interrupt enable 0: interrupt on a trigger overrun event occurrence is disabled 1: interrupt on a trigger overrun event occurrence is enabled Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 SIG_ID[4:0]: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator 652/3178 DocID029587 Rev 3 RM0433 DMA request multiplexer (DMAMUX) 17.6.9 DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR) Address offset: 0x140 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 r r r r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 OF[7:0]: Trigger overrun event flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. 17.6.10 DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR) Address offset: 0x140 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 r r r r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 OF[7:0]: Trigger overrun event flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX2_RGCFR register. DocID029587 Rev 3 653/3178 656 DMA request multiplexer (DMAMUX) 17.6.11 RM0433 DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR) Address offset: 0x144 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. COF7 COF6 COF5 COF4 COF3 COF2 COF1 COF0 w w w w w w w w Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 COF[7:0]: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. 17.6.12 DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR) Address offset: 0x144 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. COF7 COF6 COF5 COF4 COF3 COF2 COF1 COF0 r r r r r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 COF[7:0]: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX2_RGSR register. 654/3178 DocID029587 Rev 3 RM0433 17.6.13 DMA request multiplexer (DMAMUX) DMAMUX register map The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. SOIE SOIE SOIE SOIE SOIE SOIE SOIE SOIE SOIE SOIE 0 0 SOIE SOIE 0 0 0 SOIE Res. EGE EGE EGE EGE EGE EGE EGE EGE Res. Res. Res. Res. Res. Res. Res. Res. EGE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EGE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 EGE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 EGE Res. Res. Res. Res. SE Res. Res. SE SE Res. Res. SE SE Res. Res. SE SE 0 DocID029587 Rev 3 Res. 0 Res. NBREQ[4:0] Res. SE SE 0 Res. SYNC_ID[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 DMAREQ_ID[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 Res. NBREQ[4:0] 0 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 0 Res. 0 0 0 SOIE 0 0 0 SOIE 0 0 0 DMAREQ_ID[7:0] SOIE 0 0 0 Res. 0 0 0 Res. 0 NBREQ[4:0] 0 0 EGE 0 0 0 EGE NBREQ[4:0] 0 0 0 EGE 0 0 EGE 0 Res. 0 Res. 0 0 Res. 0 0 Res. NBREQ[4:0] 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. NBREQ[4:0] 0 0 Res. SPOL 0 Res. 0 0 DMAREQ_ID[7:0] Res. 0 0 Res. 0 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 NBREQ[4:0] 0 SE 0 0 Res. 0 SPOL NBREQ[4:0] 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. 0 0 Res. 0 SPOL NBREQ[4:0] 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 0 SE 0 0 Res. 0 SPOL NBREQ[4:0] 0 0 SE 0 0 Res. 0 0 SE 0 0 Res. 0 0 0 SE 0 0 SPOL 0 0 Res. 0 0 SE 0 0 Res. 0 0 NBREQ[4:0] 0 SE 0 0 0 SPOL 0 0 SPOL 0 0 SPOL 0 0 0 Res. Res. Res. Reserved Res. Reset value 0x040 0x07C 0 0 0 Res. Res. DMAMUX_C15CR Res. 0x03C(1) 0 SYNC_ID[4:0] 0 Res. Reset value 0 0 0 0 Res. Res. Res. Res. DMAMUX_C14CR Res. 0x038(1) 0 0 NBREQ[4:0] SYNC_ID[4:0] 0 Res. Reset value 0 SYNC_ID[4:0] 0 Res. Reset value 0 0 0 Res. 0x034(1) DMAMUX_C13CR Res. DMAMUX_C12CR Res. 0x030(1) 0 SYNC_ID[4:0] 0 Res. Reset value 0 0 0 0 Res. Res. DMAMUX_C11CR Res. 0x02C(1) 0 0 NBREQ[4:0] SYNC_ID[4:0] 0 Res. Reset value 0 0 SPOL Res. Res. Res. DMAMUX_C10CR Res. 0x028(1) 0 SYNC_ID[4:0] 0 Res. Reset value 0 SYNC_ID[4:0] 0 Res. Reset value 0 0 0 Res. 0x024(1) DMAMUX_C9CR Res. DMAMUX_C8CR Res. 0x020(1) 0 0 NBREQ[4:0] SYNC_ID[4:0] 0 Res. Reset value 0 0 0 SPOL Res. DMAMUX_C7CR Res. 0x01C 0 SYNC_ID[4:0] 0 Res. Reset value 0 0 SPOL Res. DMAMUX_C6CR Res. 0x018 0 SYNC_ID[4:0] 0 Res. Reset value 0 0 SPOL Res. Res. 0x014 0 SYNC_ID[4:0] 0 Res. Reset value DMAMUX_C5CR 0 0 SPOL Res. DMAMUX_C4CR Res. 0x010 0 0 NBREQ[4:0] SYNC_ID[4:0] 0 Res. Reset value 0 SPOL Res. Res. DMAMUX_C3CR Res. 0x00C 0 SYNC_ID[4:0] 0 Res. Reset value 0 Res. DMAMUX_C2CR Res. 0x008 0 SYNC_ID[4:0] 0 Res. Reset value 0 NBREQ[4:0] SPOL Res. Res. 0x004 0 Res. Reset value DMAMUX_C1CR SYNC_ID[4:0] SPOL DMAMUX_C0CR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 Register name Res. Offset Res. Table 118. DMAMUX register map and reset values DMAREQ_ID[7:0] 655/3178 656 0x148 0x3FC 656/3178 Reserved 1. Only applies to DMAMUX1. For DMAMUX2, the word is reserved. 2. For DMAMUX2, the bits 15:8 are reserved. DocID029587 Rev 3 COF6 COF5 COF4 COF3 COF2 COF1 COF0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Reset value Res. COF5 COF4 COF3 COF2 COF1 COF0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. OF0 COF6 0 OF1 COF7 0 OF2 COF8 0 OF3 COF9 0 OF4 COF10 0 OF5 COF11 0 OF6 COF12 0 OF7 Reset value COF7 COF13 0 Res. OF14 OF13 OF12 OF11 OF10 OF9 OF8 OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 Res. Res. Res. OIE Res. Res. Res. Res. Res. Res. 0 Res. COF14 0 Res. Res. Res. Res. OIE Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. Res. Res. Res. Res. GE 0 Res. Res. Res. Res. Res. Res. Res. Reset value OF15 Reset value COF15 0 Res. GE CSOF5 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. Res. Res. Res. Res. Res. CSOF0 CSOF6 0 0 0 0 0 0 Res. CSOF7 0 CSOF1 CSOF8 0 Res. CSOF9 0 CSOF2 CSOF10 0 Res. CSOF11 0 CSOF3 CSOF12 0 Res. CSOF13 0 CSOF4 CSOF14 0 Res. Res. Res. Res. CSOF15 Res. Res. Res. Res. 0 Res. Res. GE GPOL Reset value Res. 0 GE GPOL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAMUX_CSR(2) Res. SOF14 SOF13 SOF12 SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name SOF15 Reset value Res. 0 Res. 0 Res. GPOL 0 Res. GPOL 0 Res. 0 Res. 0 Res. Res. GNBREQ[4:0] Res. 0 Res. GNBREQ[4:0] Res. 0 Res. 0 Res. GNBREQ[4:0] Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. DMAMUX_RGCFR Res. 0x144 DMAMUX_RGSR Res. 0x140 DMAMUX_RGCFR Res. 0x144 DMAMUX_RGSR Res. 0x140 DMAMUX_RG3CR Res. 0x10C DMAMUX_RG2CR Res. 0x108 DMAMUX_RG1CR Res. 0x104 DMAMUX_RG0CR Res. 0x100 Reserved Res. 0x088 0x0FC DMAMUX_CFR(2) Res. 0x084 Res. 0x080 Res. Offset Res. DMA request multiplexer (DMAMUX) RM0433 Table 118. DMAMUX register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID[4:0] 0 0 0 0 0 0 0 0 0 0 0 SIG_ID[4:0] 0 0 SIG_ID[4:0] 0 0 SIG_ID[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18 Chrom-Art Accelerator™ controller (DMA2D) 18.1 DMA2D introduction The Chrom-Art Accelerator™ (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations: • Filling a part or the whole of a destination image with a specific color • Copying a part or the whole of a source image into a part or the whole of a destination image • Copying a part or the whole of a source image into a part or the whole of a destination image with a pixel format conversion • Blending a part and/or two complete source images with different pixel format and copy the result into a part or the whole of a destination image with a different color format. All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with indexed or direct color mode, including block based YCbCr to handle JPEG decoder output. The DMA2D has its own dedicated memories for CLUTs (color look-up tables). DocID029587 Rev 3 657/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.2 RM0433 DMA2D main features The main DMA2D features are: • Single AXI master bus architecture. • AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT accesses which are 32-bit). • User programmable working area size • User programmable offset for sources and destination areas • User programmable sources and destination addresses on the whole memory space • Up to 2 sources with blending operation • Alpha value can be modified (source value, fixed value or modulated value) • User programmable source and destination color format • Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct color coding • Block based (8x8) YCbCr support with 4:4:4, 4:2:2 and 4:2:0 chroma sub-sampling factors • 2 internal memories for CLUT storage in indirect color mode • Automatic CLUT loading or CLUT programming via the CPU • User programmable CLUT size • Internal timer to control AXI bandwidth • 4 operating modes: register-to-memory, memory-to-memory, memory-to-memory with pixel format conversion, and memory-to-memory with pixel format conversion and blending • Area filling with a fixed color • Copy from an area to another • Copy with pixel format conversion between source and destination images • Copy from two sources with independent color format and blending • Abort and suspend of DMA2D operations • Watermark interrupt on a user programmable destination line • Interrupt generation on bus error or access conflict • Interrupt generation on process completion 18.3 DMA2D functional description 18.3.1 General description The DMA2D controller performs direct memory transfer. As an AXI master, it can take the control of the AXI bus matrix to initiate AXI transactions. The DMA2D can operate in the following modes: 658/3178 • Register-to-memory • Memory-to-memory • Memory-to-memory with Pixel Format Conversion • Memory-to-memory with Pixel Format Conversion and Blending DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) The AHB slave port is used to program the DMA2D controller. The block diagram of the DMA2D is shown in Figure 78: DMA2D block diagram. Figure 78. DMA2D block diagram ELW $;,EXV )*3)& ĮPRGH &RORUPRGH GPDGB DFON )* ),)2 Į 5*% ([SDQGHU GPDGB JEOBLW &/87LWI GPDGB FOXWBWUJ [ELW 5$0 ; Į &RORUPRGH Į &RQYHUWHU *UHHQ &RORU 287 ),)2 %OXH %*3)& ĮPRGH &RORUPRGH %* ),)2 2873)& %/(1'(5 5HG GPDGB WFBWUJ GPDGB WZBWUJ ELWĮ ELWĮ Į 5*% ([SDQGHU ; Į &/87LWI [ELW 5$0 ELW $+%EXV 069 18.4 DMA2D pins and internal signals Table 119 lists the DMA2D internal signals. Table 119. DMA2D internal input/output signals Signal name Signal type dma2d_aclk Digital input 32-bit AXI bus clock dma2d_gbl_it Digital output DMA2D global interrupt dma2d_clut_trg Digital output CLUT transfer complete (to MDMA) dma2d_tc_trg Digital output Transfer complete (to MDMA) dma2d_tw_trg Digital output Transfer watermark (to MDMA) Description DocID029587 Rev 3 659/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.4.1 RM0433 DMA2D control The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) which allows selecting: The user application can perform the following operations: 18.4.2 • Select the operating mode • Enable/disable the DMA2D interrupt • Start/suspend/abort ongoing data transfers DMA2D foreground and background FIFOs The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to be copied and/or processed. The FIFOs fetch the pixels according to the color format defined in their respective pixel format converter (PFC). They are programmed through a set of control registers: • DMA2D foreground memory address register (DMA2D_FGMAR) • DMA2D foreground offset register (DMA2D_FGOR) • DMA2D background memory address register (DMA2D_BGMAR) • DMA2D background offset register (DMA2D_BGBOR) • DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR) When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated. When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor blending operation), only the FG FIFO is activated and acts as a buffer. When the DMA2D operates in memory-to-memory operation with pixel format conversion (no blending operation), the BG FIFO is not activated. 18.4.3 DMA2D foreground and background pixel format converter (PFC) DMA2D foreground pixel format converter (PFC) and background pixel format converter perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also modify the alpha channel. The first stage of the converter converts the color format. The original color format of the foreground pixel and background pixels are configured through the CM[3:0] bits of the DMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively. The supported input formats are given in Table 120: Supported color mode in input. Table 120. Supported color mode in input CM[3:0] 660/3178 Color mode 0000 ARGB8888 0001 RGB888 0010 RGB565 0011 ARGB1555 0100 ARGB4444 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) Table 120. Supported color mode in input CM[3:0] Color mode 0101 L8 0110 AL44 0111 AL88 1000 L4 1001 A8 1010 A4 1011 YCbCr (only for foreground) The color format are coded as follows: • Alpha value field: transparency 0xFF value corresponds to an opaque pixel and 0x00 to a transparent one. • R field for Red • G field for Green • B field for Blue • L field: luminance This field is the index to a CLUT to retrieve the three/four RGB/ARGB components. If the original format was direct color mode, then the extension to 8-bit per channel is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of the conversion. If the original format does not include an alpha channel, the alpha value is automatically set to 0xFF (opaque). If the original format is indirect color mode, a CLUT is required and each pixel format converter is associated with a 256 entry 32-bit CLUT. For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color to be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for foreground pixels and in the DMA2D_BGCOLR register for background pixels. The order of the fields in the system memory is defined in Table 121: Data order in memory. DocID029587 Rev 3 661/3178 690 Chrom-Art Accelerator™ controller (DMA2D) RM0433 Table 121. Data order in memory Color Mode @+3 @+2 @+1 @+0 ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0] B1[7:0] R0[7:0] G0[7:0] B0[7:0] G2[7:0] B2[7:0] R1[7:0] G1[7:0] R3[7:0] G3[7:0] B3[7:0] R2[7:0] RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0] ARGB1555 A1[0]R1[4:0]G1[4:3] G1[2:0]B1[4:0] A0[0]R0[4:0]G0[4:3] G0[2:0]B0[4:0] ARGB4444 A1[3:0]R1[3:0] G1[3:0]B1[3:0] A0[3:0]R0[3:0] G0[3:0]B0[3:0] L8 L3[7:0] L2[7:0] L1[7:0] L0[7:0] AL44 A3[3:0]L3[3:0] A2[3:0]L2[3:0] A1[3:0]L1[3:0] A0[3:0]L0[3:0] AL88 A1[7:0] L1[7:0] A0[7:0] L0[7:0] L4 L7[3:0]L6[3:0] L5[3:0]L4[3:0] L3[3:0]L2[3:0] L1[3:0]L0[3:0] A8 A3[7:0] A2[7:0] A1[7:0] A0[7:0] A4 A7[3:0]A6[3:0] A5[3:0]A4[3:0] A3[3:0]A2[3:0] A1[3:0]A0[3:0] RGB888 The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode. Once the 32-bit value is generated, the alpha channel can be modified according to the AM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in Table 122: Alpha mode configuration. The alpha channel can be: • kept as it is (no modification), • replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR, • or replaced by the original alpha value multiplied by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255. Table 122. Alpha mode configuration Note: AM[1:0] Alpha mode 00 No modification 01 Replaced by value in DMA2D_xxPFCCR 10 Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255 11 Reserved To support the alternate format, the incoming alpha value can be inverted setting the AI bit of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the Alpha value stored in the DMA2D_FGPFCCR/DMA2D_BGPFCCR and in the CLUT. The R and B fields can also be swapped setting the RBS bit of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the RGB order used in the CLUT and in the DMA2D_FGCOLR/DMA2D_BGCOLR registers. 662/3178 DocID029587 Rev 3 RM0433 18.4.4 Chrom-Art Accelerator™ controller (DMA2D) DMA2D foreground and background CLUT interface The CLUT interface manages the CLUT memory access and the automatic loading of the CLUT. Three kinds of accesses are possible: • CLUT read by the PFC during pixel format conversion operation • CLUT accessed through the AHB slave port when the CPU is reading or writing data into the CLUT • CLUT written through the AXI master port when an automatic loading of the CLUT is performed The CLUT memory loading can be done in two different ways: • Automatic loading The following sequence should be followed to load the CLUT: a) Program the CLUT address into the DMA2D_FGCMAR register (foreground CLUT) or DMA2D_BGCMAR register (background CLUT) b) Program the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT). c) Set the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT) to start the transfer. During this automatic loading process, the CLUT is not accessible by the CPU. If a conflict occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in DMA2D_CR. • Manual loading The application has to program the CLUT manually through the DMA2D AHB slave port to which the local CLUT memory is mapped.The foreground CLUT is located at address offset 0x0400 and the background CLUT at address offset 0x0800. The CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT) as shown in Table 123: Supported CLUT color mode. Table 123. Supported CLUT color mode CCM CLUT color mode 0 32-bit ARGB8888 1 24-bit RGB888 The way the CLUT data are organized in the system memory is specified in Table 124: CLUT data order in memory. Table 124. CLUT data order in memory CLUT Color Mode ARGB8888 RGB888 @+3 @+2 @+1 @+0 A0[7:0] R0[7:0] G0[7:0] B0[7:0] B1[7:0] R0[7:0] G0[7:0] B0[7:0] G2[7:0] B2[7:0] R1[7:0] G1[7:0] R3[7:0] G3[7:0] B3[7:0] R2[7:0] DocID029587 Rev 3 663/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.4.5 RM0433 DMA2D blender The DMA2D blender blends the source pixels by pair to compute the resulting pixel. The blending is performed according to the following equation: with αMult = αFG . αBG 255 αOUT = αFG + αBG - αMult COUT = CFG.αFG + CBG.αBG - CBG.αMult αOUT with C = R or G or B Division is rounded to the nearest lower integer No configuration register is required by the blender. The blender usage depends on the DMA2D operating mode defined in MODE[1:0] field of the DMA2D_CR register. 18.4.6 DMA2D output PFC The output PFC performs the pixel format conversion from 32 bits to the output format defined in the CM[2:0] field of the DMA2D output pixel format converter configuration register (DMA2D_OPFCCR). The supported output formats are given in Table 125: Supported color mode in output Table 125. Supported color mode in output CM[2:0] Note: Color mode 000 ARGB8888 001 RGB888 010 RGB565 011 ARGB1555 100 ARGB4444 To support the alternate format, the calculated alpha value can be inverted setting the AI bit of the DMA2D_OPFCCR registers. This applies also to the Alpha value used in the DMA2D_OCOLR. The R and B fields can also be swapped setting the RBS bit of the DMA2D_OPFCCR registers. This applies also to the RGB order used in the DMA2D_OCOLR. 18.4.7 DMA2D output FIFO The output FIFO programs the pixels according to the color format defined in the output PFC. 664/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) The destination area is defined through a set of control registers: • DMA2D output memory address register (DMA2D_OMAR) • DMA2D output offset register (DMA2D_OOR) • DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR) If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the DMA2D_OPFCCR register. The data are stored into the memory in the order defined in Table 126: Data order in memory Table 126. Data order in memory Color Mode @+3 @+2 @+1 @+0 ARGB8888 A0[7:0] R0[7:0] G0[7:0] B0[7:0] B1[7:0] R0[7:0] G0[7:0] B0[7:0] G2[7:0] B2[7:0] R1[7:0] G1[7:0] R3[7:0] G3[7:0] B3[7:0] R2[7:0] RGB565 R1[4:0]G1[5:3] G1[2:0]B1[4:0] R0[4:0]G0[5:3] G0[2:0]B0[4:0] ARGB1555 A1[0]R1[4:0]G1[4:3] G1[2:0]B1[4:0] A0[0]R0[4:0]G0[4:3] G0[2:0]B0[4:0] ARGB4444 A1[3:0]R1[3:0] G1[3:0]B1[3:0] A0[3:0]R0[3:0] G0[3:0]B0[3:0] RGB888 The RGB888 aligned on 32-bit is supported through the ARGB8888 mode. 18.4.8 DMA2D AXI master port timer An 8-bit timer is embedded into the AXI master port to provide an optional limitation of the bandwidth on the crossbar. This timer is clocked by the AXI clock and counts a dead time between two consecutive accesses. This limits the bandwidth usage. The timer enabling and the dead time value are configured through the AXI master port timer configuration register (DMA2D_AMPTCR). 18.4.9 DMA2D transactions DMA2D transactions consist of a sequence of a given number of data transfers. The number of data and the width can be programmed by software. Each DMA2D data transfer is composed of up to 4 steps: DocID029587 Rev 3 665/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.4.10 RM0433 1. Data loading from the memory location pointed by the DMA2D_FGMAR register and pixel format conversion as defined in DMA2D_FGCR. 2. Data loading from a memory location pointed by the DMA2D_BGMAR register and pixel format conversion as defined in DMA2D_BGCR. 3. Blending of all retrieved pixels according to the alpha channels resulting of the PFC operation on alpha values. 4. Pixel format conversion of the resulting pixels according to the DMA2D_OCR register and programming of the data to the memory location addressed through the DMA2D_OMAR register. DMA2D configuration Both source and destination data transfers can target peripherals and memories in the whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and 0xFFFF FFFF. The DMA2D can operate in any of the four following modes selected through MODE[1:0] bits of the DMA2D_CR register: • Register-to-memory • Memory-to-memory • Memory-to-memory with PFC • Memory-to-memory with PFC and blending Register-to-memory The register-to-memory mode is used to fill a user defined area with a predefined color. The color format is set in the DMA2D_OPFCCR. The DMA2D does not perform any data fetching from any source. It just writes the color defined in the DMA2D_OCOLR register to the area located at the address pointed by the DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR. Memory-to-memory In memory-to-memory mode, the DMA2D does not perform any graphical data transformation. The foreground input FIFO acts as a buffer and the data are transferred from the source memory location defined in DMA2D_FGMAR to the destination memory location pointed by DMA2D_OMAR. The color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines the number of bits per pixel for both input and output. The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination. Memory-to-memory with PFC In this mode, the DMA2D performs a pixel format conversion of the source data and stores them in the destination memory location. The size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination. 666/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) Data are fetched from the location defined in the DMA2D_FGMAR register and processed by the foreground PFC. The original pixel format is configured through the DMA2D_FGPFCCR register. If the original pixel format is direct color mode, then the color channels are all expanded to 8 bits. If the pixel format is indirect color mode, the associated CLUT has to be loaded into the CLUT memory. The CLUT loading can be done automatically by following the sequence below: 1. Set the CLUT address into the DMA2D_FGCMAR. 2. Set the CLUT size in the CS[7:0] bits of the DMA2D_FGPFCCR register. 3. Set the CLUT format (24 or 32 bits) in the CCM bit of the DMA2D_FGPFCCR register. 4. Start the CLUT loading by setting the START bit of the DMA2D_FGPFCCR register. Once the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised, and an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT loading process can not work in parallel with classical DMA2D transfers. The CLUT can also be filled by the CPU or by any other master through the AHB port. The access to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT (indirect color format). In parallel to the color conversion process, the alpha value can be added or changed depending on the value programmed in the DMA2D_FGPFCCR register. If the original image does not have an alpha channel, a default alpha value of 0xFF is automatically added to obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits of the DMA2D_FGPFCCR register: • It can be unchanged. • It can be replaced by the value defined in the ALPHA[7:0] value of the DMA2D_FGPFCCR register. • It can be replaced by the original value multiplied by the ALPHA[7:0] value of the DMA2D_FGPFCCR register divided by 255. The resulting 32-bit data are encoded by the OUT PFC into the format specified by the CM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the indirect mode since no CLUT generation process is supported. The processed data are written into the destination memory location pointed by DMA2D_OMAR. Memory-to-memory with PFC and blending In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR. The two pixel format converters have to be configured as described in the memory-tomemory mode. Their configurations can be different as each pixel format converter are independent and have their own CLUT memory. DocID029587 Rev 3 667/3178 690 Chrom-Art Accelerator™ controller (DMA2D) RM0433 Once each pixel has been converted into 32 bits by their respective PFCs, they are blended according to the equation below: with αMult = αFG . αBG 255 αOUT = αFG + αBG - αMult COUT = CFG.αFG + CBG.αBG - CBG.αMult αOUT with C = R or G or B Division are rounded to the nearest lower integer The resulting 32-bit pixel value is encoded by the output PFC according to the specified output format, and the data are written into the destination memory location pointed by DMA2D_OMAR. Configuration error detection The DMA2D checks that the configuration is correct before any transfer. The configuration error interrupt flag is set by hardware when a wrong configuration is detected when a new transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the DMA2D_CR is set. The wrong configurations that can be detected are listed below: 668/3178 • Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR not aligned with CCM of DMA2D_FGPFCCR. • Background CLUT automatic loading: MA of DMA2D_BGCMAR not aligned with CCM of DMA2D_BGPFCCR • Memory transfer (except in register-to-memory mode): MA of DMA2D_FGMAR not aligned with CM of DMA2D_FGPFCCR • Memory transfer (except in register-to-memory mode): CM in DMA2D_FGPFCCR are invalid • Memory transfer (except in register-to-memory mode): PL bits of DMA2D_NLR odd while CM of DMA2D_FGPFCCR is A4 or L4 • Memory transfer (except in register-to-memory mode): LO bits in DMA2D_FGOR odd while CM of DMA2D_FGPFCCR is A4 or L4 • Memory transfer (only in blending mode): MA bits in DMA2D_BGMAR are not aligned with the CM of DMA2D_BGPFCCR • Memory transfer: CM of DMA2D_BGPFCCR invalid (only in blending mode) • Memory transfer (only in blending mode): PL bits of DMA2D_NLR odd while CM of DMA2D_BGPFCCR is A4 or L4 • Memory transfer (only in blending mode): LO bits of DMA2D_BGOR odd while CM of DMA2D_BGPFCCR is A4 or L4 • Memory transfer (except in memory to memory mode): MA bits in DMA2D_OMAR are not aligned with CM bits in DMA2D_OPFCCR. • Memory transfer (except in memory to memory mode): CM bits in DMA2D_OPFCCR invalid • Memory transfer: NL bits in DMA2D_NLR = 0 DocID029587 Rev 3 RM0433 18.4.11 Chrom-Art Accelerator™ controller (DMA2D) • Memory transfer: PL bits in DMA2D_NLR = 0 • YCbCr format: when a CLUT loading starts setting the START bit of the DMA2D_FGPFCCR. • YCbCr format: when the memory-to-memory mode is selected. • YCbCr format: when YCbCR4:4:4 is selected and the sum of the number of pixel (PL) and the line offset LO is not a multiple of 8 pixels. • YCbCr format: when YCbCr4:2:2 or YCbCr4:2:0 is selected and the sum of the number of pixel (PL) and the line offset LO is not a multiple of 16 pixels. YCbCr support The DMA2D foreground plane can support 8x8 block based YCbCr as output by the JPEG decoder with different chroma sub-sampling factors: The memory organization follows the standard JFIF rules: • Each of the three color component must be coded on 8-bit • Each component must be arranged by blocks of 8x8 (64 bytes) called MCU Depending of the chroma sub-sampling factor the MCU must be arranged in the memory as described in Table 127: MCU order in memory. Table 127. MCU order in memory Sub-sampling @ @ + 64 @ + 128 @+192 @+256 @ + 320 4:4:4 Y1 Cb1 Cr1 Y2 Cb2 Cr2 4:2:2 Y1 Y2 Cb12 Cr12 Y3 Y4 4:2:0 Y1 Y2 Y3 Y4 Cb1234 Cr1234 The chroma sub-sampling factor is configured through the CSS field of the DMA2D_FGPFCCR register. Once the DMA2D has started with the foreground configured in YCbCr color mode, the first 2 chroma MCU are loaded in the foreground CLUT. Once the chroma MCU are loaded, the DMA2D performs the loading of the Y MCU as for a classical color mode. 18.4.12 DMA2D transfer control (start, suspend, abort and completion) Once the DMA2D is configured, the transfer can be launched by setting the START bit of the DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the TCIE bit of the DMA2D_CR is set. The user application can suspend the DMA2D at any time by setting the SUSP bit of the DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR register. The user application can abort at any time an ongoing transaction by setting the ABORT bit of the DMA2D_CR register. In this case, the TCIF flag is not raised. Automatic CLUT transfers can also be aborted or suspended by using their own START bits in the DMA2D_FGPFCCR and DMA2D_BGPFCCR registers. DocID029587 Rev 3 669/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.4.13 RM0433 Watermark A watermark can be programmed to generate an interrupt when the last pixel of a given line has been written to the destination memory area. The line number is defined in the LW[15:0] field of the DMA2D_LWR register. When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set. 18.4.14 Error management Two kind of errors can be triggered: • AXI master port errors signaled by the TEIF flag of the DMA2D_ISR register. • Conflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT loading or a DMA2D transfer is ongoing) signaled by the CAEIF flag of the DMA2D_ISR register. Both flags are associated to their own interrupt enable flag in the DMA2D_CR register to generate an interrupt if need be (TEIE and CAEIE). 18.4.15 AXI dead time To limit the AXI bandwidth usage, a dead time between two consecutive AXI accesses can be programmed. This feature can be enabled by setting the EN bit in the DMA2D_AMTCR register. The dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This value represents the guaranteed minimum number of cycles between two consecutive transactions on the AXI bus. The update of the dead time value while the DMA2D is running will be taken into account for the next AXI transfer. 18.5 DMA2D interrupts An interrupt can be generated on the following events: • Configuration error • CLUT transfer complete • CLUT access error • Transfer watermark reached • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 128. DMA2D interrupt requests Interrupt event Configuration error CLUT transfer complete 670/3178 Event flag Enable control bit CEIF CEIE CTCIF CTCIE DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) Table 128. DMA2D interrupt requests (continued) Interrupt event Event flag Enable control bit CLUT access error CAEIF CAEIE Transfer watermark TWF TWIE Transfer complete TCIF TCIE Transfer error TEIF TEIE DocID029587 Rev 3 671/3178 690 Chrom-Art Accelerator™ controller (DMA2D) RM0433 18.6 DMA2D registers 18.6.1 DMA2D control register (DMA2D_CR) Address offset: 0x0000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. CEIE CTCIE CAEIE TWIE TCIE TEIE Res. Res. Res. Res. Res. ABORT SUSP START rw rw rw rw rw rw rs rw rs MODE Bits 31:18 Reserved, must be kept at reset value. Bits 17:16 MODE: DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. 00: Memory-to-memory (FG fetch only) 01: Memory-to-memory with PFC (FG fetch only with FG PFC active) 10: Memory-to-memory with blending (FG and BG fetch with PFC and blending) 11: Register-to-memory (no FG nor BG, only output stage active) Bits 15:14 Reserved, must be kept at reset value. Bit 13 CEIE: Configuration Error Interrupt Enable This bit is set and cleared by software. 0: CE interrupt disable 1: CE interrupt enable Bit 12 CTCIE: CLUT transfer complete interrupt enable This bit is set and cleared by software. 0: CTC interrupt disable 1: CTC interrupt enable Bit 11 CAEIE: CLUT access error interrupt enable This bit is set and cleared by software. 0: CAE interrupt disable 1: CAE interrupt enable Bit 10 TWIE: Transfer watermark interrupt enable This bit is set and cleared by software. 0: TW interrupt disable 1: TW interrupt enable Bit 9 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disable 1: TC interrupt enable 672/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) Bit 8 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disable 1: TE interrupt enable Bits 7:3 Reserved, must be kept at reset value. Bit 2 ABORT: Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. 0: No transfer abort requested 1: Transfer abort requested Bit 1 SUSP: Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. 0: Transfer not suspended 1: Transfer suspended Bit 0 START: Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers. This bit is automatically reset by the following events: – At the end of the transfer – When the data transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR – When a data transfer error occurs – When the data transfer has not started due to a configuration error or another transfer operation already ongoing (automatic CLUT loading). DocID029587 Rev 3 673/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.2 RM0433 DMA2D Interrupt Status Register (DMA2D_ISR) Address offset: 0x0004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEIF CTCIF CAEIF TWIF TCIF TEIF r r r r r r Bits 31:6 Reserved, must be kept at reset value. Bit 5 CEIF: Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed. Bit 4 CTCIF: CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. Bit 3 CAEIF: CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. Bit 2 TWIF: Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. Bit 1 TCIF: Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). Bit 0 TEIF: Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). 674/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18.6.3 DMA2D interrupt flag clear register (DMA2D_IFCR) Address offset: 0x0008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CCEIF CCTCIF CAECIF CTWIF CTCIF CTEIF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:6 Reserved, must be kept at reset value. Bit 5 CCEIF: Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register Bit 3 CAECIF: Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register Bit 2 CTWIF: Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register Bit 1 CTCIF: Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register Bit 0 CTEIF: Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register DocID029587 Rev 3 675/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.4 RM0433 DMA2D foreground memory address register (DMA2D_FGMAR) Address offset: 0x000C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MA[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 MA[31:0]: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4bit per pixel format must be 8-bit aligned. 18.6.5 DMA2D foreground offset register (DMA2D_FGOR) Address offset: 0x0010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. rw rw rw rw rw rw LO[13:0] rw rw rw rw rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 LO[13:0]: Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. 676/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18.6.6 DMA2D background memory address register (DMA2D_BGMAR) Address offset: 0x0014 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MA[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MA[31:0]: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is readonly. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4bit per pixel format must be 8-bit aligned. 18.6.7 DMA2D background offset register (DMA2D_BGOR) Address offset: 0x0018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. rw rw rw rw rw rw LO[13:0] rw rw rw rw rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 LO[13:0]: Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. DocID029587 Rev 3 677/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.8 RM0433 DMA2D foreground PFC control register (DMA2D_FGPFCCR) Address offset: 0x001C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 ALPHA[7:0] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 CS[7:0] rw rw rw rw rw rw rw 23 22 21 20 Res. Res. RBS AI rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. START CCM rc_w1 rw rw rw rw 19 18 17 CSS[1:0] 16 AM[1:0] CM[3:0] rw rw Bits 31:24 ALPHA[7:0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only. Bits 23:22 Reserved, must be kept at reset value. Bit 21 RBS: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 0: Regular mode (RGB or ARGB) 1: Swap mode (BGR or ABGR) Bit 20 AI: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. 0: Regular alpha 1: Inverted alpha Bits 19:18 CSS[1:0]: Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. 00: 4:4:4 (no chroma sub-sampling) 01: 4:2:2 10: 4:2:0 others: meaningless Bits 17:16 AM[1:0]: Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. 00: No modification of the foreground image alpha channel value 01: Replace original foreground image alpha channel value by ALPHA[7: 0] 10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value other configurations are meaningless 678/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) Bits 15:8 CS[7:0]: CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. Bits 7:6 Reserved, must be kept at reset value. Bit 5 START: Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR – when a transfer error occurs – when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer). Bit 4 CCM: CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. 0: ARGB8888 1: RGB888 Bits 3:0 CM[3:0]: Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 0000: ARGB8888 0001: RGB888 0010: RGB565 0011: ARGB1555 0100: ARGB4444 0101: L8 0110: AL44 0111: AL88 1000: L4 1001: A8 1010: A4 1011: YCbCr others: meaningless DocID029587 Rev 3 679/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.9 RM0433 DMA2D foreground color register (DMA2D_FGCOLR) Address offset: 0x0020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 rw rw rw rw 19 18 17 16 RED[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw GREEN[7:0] rw 20 BLUE[7:0] rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 RED[7:0]: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 15:8 GREEN[7:0]: Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. Bits 7:0 BLUE[7:0]: Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. 680/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18.6.10 DMA2D background PFC control register (DMA2D_BGPFCCR) Address offset: 0x0024 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 ALPHA[7:0] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 CS[7:0] rw rw rw rw rw rw rw 23 22 21 20 19 18 Res. Res. RBS AI Res. Res. rw rw 7 6 5 4 3 2 Res. Res. START CCM rc_w1 rw rw 17 16 AM[1:0] rw rw 1 0 rw rw CM[3:0] rw rw Bits 31:24 ALPHA[7:0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 23:22 Reserved, must be kept at reset value. Bit 21 RBS: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 0: Regular mode (RGB or ARGB) 1: Swap mode (BGR or ABGR) Bit 20 AI: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. 0: Regular alpha 1: Inverted alpha Bits 19:18 Reserved, must be kept at reset value. Bits 17:16 AM[1:0]: Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 00: No modification of the foreground image alpha channel value 01: Replace original background image alpha channel value by ALPHA[7: 0] 10: Replace original background image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value others: meaningless Bits 15:8 CS[7:0]: CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. Bits 7:6 Reserved, must be kept at reset value. DocID029587 Rev 3 681/3178 690 Chrom-Art Accelerator™ controller (DMA2D) RM0433 Bit 5 START: Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR – when a transfer error occurs – when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer). Bit 4 CCM: CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. 0: ARGB8888 1: RGB888 Bits 3:0 CM[3:0]: Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are readonly. 0000: ARGB8888 0001: RGB888 0010: RGB565 0011: ARGB1555 0100: ARGB4444 0101: L8 0110: AL44 0111: AL88 1000: L4 1001: A8 1010: A4 others: meaningless 682/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18.6.11 DMA2D background color register (DMA2D_BGCOLR) Address offset: 0x0028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 rw rw rw rw 19 18 17 16 RED[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw GREEN[7:0] rw 20 BLUE[7:0] rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 RED[7:0]: Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 15:8 GREEN[7:0]: Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 7:0 BLUE[7:0]: Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 18.6.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR) Address offset: 0x002C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MA[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MA[31:0]: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. DocID029587 Rev 3 683/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.13 RM0433 DMA2D background CLUT memory address register (DMA2D_BGCMAR) Address offset: 0x0030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MA[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MA[31:0]: Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned. 18.6.14 DMA2D output PFC control register (DMA2D_OPFCCR) Address offset: 0x0034 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RBS AI Res. Res. Res. Res. rw rw 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CM[2:0] rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 RBS: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 0: Regular mode (RGB or ARGB) 1: Swap mode (BGR or ABGR) 684/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) Bit 20 AI: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. 0: Regular alpha 1: Inverted alpha Bits 19:3 Reserved, must be kept at reset value. Bits 2: 0 CM[2:0]: Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 000: ARGB8888 001: RGB888 010: RGB565 011: ARGB1555 100: ARGB4444 others: meaningless 18.6.15 DMA2D output color register (DMA2D_OCOLR) Address offset: 0x0038 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 ALPHA[7:0] 19 18 17 16 RED[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GREEN[7:0] BLUE[7:0] RED[4:0] A GREEN[5:0] RED[4:0] GREEN[4:0] ALPHA[3:0] rw rw rw RED[3:0] rw BLUE[4:0] rw rw rw BLUE[4:0] GREEN[3:0] rw rw rw rw BLUE[3:0] rw rw rw rw rw Bits 31:24 ALPHA[7:0]: Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 23:16 RED[7:0]: Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 15:8 GREEN[7:0]: Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 7:0 BLUE[7:0]: Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. DocID029587 Rev 3 685/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.16 RM0433 DMA2D output memory address register (DMA2D_OMAR) Address offset: 0x003C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MA[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MA[31:0]: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned. 686/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18.6.17 DMA2D output offset register (DMA2D_OOR) Address offset: 0x0040 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. rw rw rw rw rw rw LO[13:0] rw rw rw rw rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 LO[13:0]: Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 18.6.18 DMA2D number of line register (DMA2D_NLR) Address offset: 0x0044 Reset value: 0x0000 0000 31 30 Res. Res. 15 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PL[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NL[15:0] rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:16 PL[13:0]: Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even. Bits 15:0 NL[15:0]: Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. DocID029587 Rev 3 687/3178 690 Chrom-Art Accelerator™ controller (DMA2D) 18.6.19 RM0433 DMA2D line watermark register (DMA2D_LWR) Address offset: 0x0048 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw LW[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 LW[15:0]: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. 18.6.20 DMA2D AXI master timer configuration register (DMA2D_AMTCR) Address offset: 0x004C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. EN DT[7:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DT[7:0]: Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. Bits 7:1 Reserved, must be kept at reset value. Bit 0 EN: Enable Enables the dead time functionality. 688/3178 DocID029587 Rev 3 RM0433 Chrom-Art Accelerator™ controller (DMA2D) 18.6.21 DMA2D register map The following table summarizes the DMA2D registers. Refer to Section 2.2.2 on page 105 for the DMA2D register base address. CTCIF CTEIF Res. Res. Res. CTWIF 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA2D_FGOR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 LO[13:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 APLHA[7:0] DMA2D_BGPFCCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APLHA[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RED[7:0] ALPHA[7:0] DMA2D_BGCOLR 0 AM[1:0] 0 CSS[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GREEN[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GREEN[7:0] 0 0 DMA2D_FGCMAR 0 0 CM[3:0] 0 0 0 0 0 0 0 CM[3:0] 0 0 0 0 BLUE[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA2D_OPFCCR Res. Res. Res. Res. Res. RBS AI Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MA[31:0] Res. DMA2D_BGCMAR 0 0 Reset value 0 BLUE[7:0] CS[7:0] RED[7:0] 0 0 CCM 0 0 START 0 0 Res. 0 0 0 Res. 0 0 0 CS[7:0] AM[1:0] 0 DMA2D_FGCOLR 0 Res. 0 Res. 0 AI 0 AI ALPHA[7:0] RBS DMA2D_FGPFCCR Res. 0 Res. Reset value LO[13:0] Res. 0x0034 0 Res. 0x0030 0 CCM 0 Reset value 0 Res. 0x002C 0 START 0 Reset value 0 Res. 0x0028 0 Res. 0 Reset value 0 Res. Reset value DMA2D_BGOR RBS 0x0024 0 MA[31:0] Res. DMA2D_BGMAR Reset value SUSP TEIF 0 CAECIF 0 Res. 0x0020 START TCIF 0 CCTCIF 0 Reset value Res. 0 CCEIF 0 Res. 0x001C 0 Res. 0x0018 0 Res. 0x0014 Reset value Res. 0x0010 ABORT Res. TWIF Res. 0 MA[31:0] Res. 0x000C 0 0 Reset value DMA2D_FGMAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2D_IFCR 0 0 Reset value 0x0008 0 CAEIF Res. Res. TEIE 0 CTCIF TCIE 0 Res. TWIE 0 CEIF CAEIE 0 Res. CTCIE 0 Res. Res. CEIE Res. 0 Res. Res. Res. Res. 0 Res. MODE[1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2D_ISR Res. 0x0004 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2D_CR Res. 0x0000 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 129. DMA2D register map and reset values DocID029587 Rev 3 CM[2:0] 0 0 0 689/3178 690 Chrom-Art Accelerator™ controller (DMA2D) RM0433 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA2D_OOR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2D_FGCLUT 0x08000x0BFF DMA2D_BGCLUT Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 RED[7:0][255:0] 0 0 0 0 0 0 0 0 0 0 LW[15:0] 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. DT[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 GREEN[7:0][255:0] BLUE[7:0][255:0] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X APLHA[7:0][255:0] RED[7:0][255:0] GREEN[7:0][255:0] BLUE[7:0][255:0] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Refer to Section 2.2.2 on page 105 for the register boundary addresses. 690/3178 Res. 0 Res. 0 Res. 0 Res. 0 APLHA[7:0][255:0] 0 Res. 0 Res. Res. Res. 0x04000x07FF 0 Res. 0 Reset value 0x0050Ox03FF 0 Res. 0 Res. Res. Res. DMA2D_AMTCR 0 NL[15:0] 0 Reset value 0x004C 0 LO[13:0] PL[13:0] 0 Res. Res. DMA2D_LWR Res. Reset value 0x0048 0 Res. Res. DMA2D_NLR Res. Reset value 0x0044 BLUE[3:0] 0 MA[31:0] Res. 0x0040 GREEN[3:0] 0 Res. 0x003C RED[3:0] 0 Res. DMA2D_OMAR ALPHA[3:0] EN Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 BLUE[4:0] Res. Res. Res. Res. 0 GREEN[4:0] Res. Res. Res. Res. 0 RED[4:0] BLUE[4:0] Res. Res. Res. Res. 0 BLUE[7:0] GREEN[6:0] Res. Res. Res. Res. A RED[4:0] Res. Res. Res. Res. Reset value Res. Res. Res. 0x0038 GREEN[7:0] Res. Res. Res. DMA2D_OCOLR RED[7:0] Res. Res. Res. APLHA[7:0] Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 129. DMA2D register map and reset values (continued) DocID029587 Rev 3 RM0433 Nested Vectored Interrupt Controllers 19 Nested Vectored Interrupt Controllers 19.1 NVIC features The NVIC includes the following features: • up to 150 maskable interrupt channels for STM32H7xxx (not including the 16 interrupt lines of Cortex®-M7 with FPU) • 16 programmable priority levels (4 bits of interrupt priority are used) • low-latency exception and interrupt handling • power management control • implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts, including the core exceptions, are managed by the NVIC. For more information on exceptions and NVIC programming, refer to PM0253 programming manual for Cortex®-M7. 19.1.1 SysTick calibration value register The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz). 19.1.2 Interrupt and exception vectors The exception vectors connected to the NVIC are the following: reset, NMI, HardFault, MemManage, Bus Fault, UsageFault, SVCall, DebugMonitor, PendSV, SysTick. Signal - Priority Table 130. NVIC(1) NVIC position Acronym - - - -3 - Reset Description Address offset Reserved 0x0000 0000 Reset 0x0000 0004 Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000 0008 All classes of fault 0x0000 000C - -2 - NMI - -1 - HardFault - 0 - MemManage Memory management 0x0000 0010 - 1 - BusFault Prefetch fault, memory access fault 0x0000 0014 - 2 - UsageFault Undefined instruction or illegal state 0x0000 0018 - - - - Reserved 0x0000 001C0x0000 002B DocID029587 Rev 3 691/3178 698 Nested Vectored Interrupt Controllers RM0433 Priority Table 130. NVIC(1) (continued) NVIC position Acronym 3 - SVCall - 4 - DebugMonitor - - - - - 5 - - 6 wwdg1_it exti_pwr_pvd_wkup Signal - Description Address offset System service call via SWI instruction 0x0000 002C Debug monitor 0x0000 0030 Reserved 0x0000 0034 PendSV Pendable request for system service 0x0000 0038 - SysTick System tick timer 0x0000 003C 7 0 WWDG1 Window Watchdog interrupt 0x0000 0040 8 1 PVD_PVM PVD through EXTI line detection interrupt 0x0000 0044 9 2 exti_wkup_rtc_wkup 10 3 RTC_WKUP flash_it 11 4 FLASH rcc_it 12 5 exti_exti0_wkup 13 exti_exti1_wkup exti_tamp_rtc_wkup lsecss_rcc_it RTC_TAMP_STAMP_ RTC tamper, timestamp CSS_LSE CSS LSE 0x0000 0048 RTC Wakeup interrupt through the EXTI line 0x0000 004C Flash memory global interrupt 0x0000 0050 RCC RCC global interrupt 0x0000 0054 6 EXTI0 EXTI Line 0 interrupt 0x0000 0058 14 7 EXTI1 EXTI Line 1 interrupt 0x0000 005C exti_exti2_wkup 15 8 EXTI2 EXTI Line 2 interrupt 0x0000 0060 exti_exti3_wkup 16 9 EXTI3 EXTI Line 3interrupt 0x0000 0064 exti_exti4_wkup 17 10 EXTI4 EXTI Line 4interrupt 0x0000 0068 dma1_it0 18 11 DMA_STR0 DMA1 Stream0 global interrupt 0x0000 006C dma1_it1 19 12 DMA_STR1 DMA1 Stream1 global interrupt 0x0000 0070 dma1_it2 20 13 DMA_STR2 DMA1 Stream2 global interrupt 0x0000 0074 dma1_it3 21 14 DMA_STR3 DMA1 Stream3 global interrupt 0x0000 0078 dma1_it4 22 15 DMA_STR4 DMA1 Stream4 global interrupt 0x0000 007C dma1_it5 23 16 DMA_STR5 DMA1 Stream5 global interrupt 0x0000 0080 dma1_it6 24 17 DMA_STR6 DMA1 Stream6 global interrupt 0x0000 0084 25 18 ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088 adc1_it adc2_it 692/3178 DocID029587 Rev 3 RM0433 Nested Vectored Interrupt Controllers Priority Table 130. NVIC(1) (continued) NVIC position Acronym 26 19 FDCAN1_IT0 FDCAN1 Interrupt 0 0x0000 008C fdcan_intr0_it 27 20 FDCAN2_IT0 FDCAN2 Interrupt 0 0x0000 0090 ttfdcan_intr1_it 28 21 FDCAN1_IT1 FDCAN1 Interrupt 1 0x0000 0094 fdcan_intr1_it 29 22 FDCAN2_IT1 FDCAN2 Interrupt 1 0x0000 0098 30 23 EXTI9_5 EXTI Line[9:5] interrupts 0x 0000 009C tim1_brk_it 31 24 TIM1_BRK TIM1 break interrupt 0x0000 00A0 tim1_upd_it 32 25 TIM1_UP TIM1 update interrupt 0x0000 00A4 tim1_trg_it 33 26 TIM1_TRG_COM TIM1 trigger and commutation interrupts 0x0000 00A8 tim1_cc_it 34 27 TIM_CC TIM1 capture / compare interrupt 0x0000 00AC tim2_it 35 28 TIM2 TIM2 global interrupt 0x0000 00B0 tim3_it 36 29 TIM3 TIM3 global interrupt 0x0000 00B4 tim4_it 37 30 TIM4 TIM4 global interrupt 0x0000 00B8 38 31 I2C1_EV I2C1 event interrupt 0x0000 00BC 39 32 I2C1_ER I2C1 error interrupt 0x0000 00C0 40 33 I2C2_EV I2C2 event interrupt 0x0000 00C4 41 34 I2C2_ER I2C2 error interrupt 0x0000 00C8 42 35 SPI1 SPI1 global interrupt 0x0000 00CC 43 36 SPI2 SPI2 global interrupt 0x0000 00D0 44 37 USART1 USART1 global interrupt 0x0000 00D4 45 38 USART2 USART2 global interrupt 0x0000 00D8 46 39 USART3 USART3 global interrupt 0x0000 00DC Signal ttfdcan_intr0_it Description Address offset exti_exti5_wkup exti_exti6_wkup exti_exti7_wkup exti_exti8_wkup exti_exti9_wkup i2c1_ev_it exti_i2c1_ev_wkup i2c1_err_it i2c2_ev_it exti_i2c2_ev_wkup i2c2_err_it spi1_it exti_spi1_it spi2_it exti_spi2_it usart1_gbl_it exti_usart1_wkup usart2_gbl_it exti_usart2_wkup usart3_gbl_it exti_usart3_wkup DocID029587 Rev 3 693/3178 698 Nested Vectored Interrupt Controllers RM0433 Priority Table 130. NVIC(1) (continued) NVIC position Acronym 47 40 EXTI15_10 exti_rtc_al 48 41 RTC_ALARM - 49 42 - 50 43 51 Signal Description Address offset exti_exti10_it exti_exti11_wkup exti_exti12_wkup EXTI Line[15:10] interrupts 0x0000 00E0 RTC alarms (A and B) through EXTI Line interrupts 0x0000 00E4 - 0x0000 00E8 TIM8_BRK_TIM12 TIM8 break and TIM12 global interrupts 0x0000 00EC 44 TIM8_UP_TIM13 TIM8 update and TIM13 global interrupts 0x0000 00F0 52 45 TIM8_TRG_COM _TIM14 TIM8 trigger /commutation and TIM14 global interrupts 0x0000 00F4 tim8_cc_it 53 46 TIM8_CC TIM8 capture / compare interrupts 0x0000 00F8 dma1_it7 54 47 DMA1_STR7 DMA1 Stream7 global interrupt 0x0000 00FC fmc_gbl_it 55 48 FMC FMC global interrupt 0x0000 0100 sdmmc_gbl_it 56 49 SDMMC1 SDMMC global interrupt 0x0000 0104 tim5_gbl_it 57 50 TIM5 TIM5 global interrupt 0x0000 0108 58 51 SPI3 SPI3 global interrupt 0x0000 010C 59 52 UART4 UART4 global interrupt 0x0000 0110 60 53 UART5 UART5 global interrupt 0x0000 0114 61 54 TIM6_DAC tim7_gbl_it 62 55 TIM7 dma2_it0 63 56 dma2_it1 64 dma2_it2 65 exti_exti13_wkup exti_exti14_wkup exti_exti15_wkup tim8_brk_it tim12_gbl_it tim8_upd_it tim13_gbl_it tim8_trg_it tim14_gbl_it spi3_it exti_spi3_wkup uart4_gbl_it exti_uart4_wkup uart5_gbl_it exti_uart5_wkup tim6_gbl_it dac_unr_it 694/3178 TIM6 global interrupt DAC underrun error interrupt 0x0000 0118 TIM7 global interrupt 0x0000 011C DMA2_STR0 DMA2 Stream0 interrupt 0x0000 0120 57 DMA2_STR1 DMA2 Stream1 interrupt 0x0000 0124 58 DMA2_STR2 DMA2 Stream2 interrupt 0x0000 0128 DocID029587 Rev 3 RM0433 Nested Vectored Interrupt Controllers Priority Table 130. NVIC(1) (continued) NVIC position Acronym 66 59 DMA2_STR3 DMA2 Stream3 interrupt 0x0000 012C dma2_it4 67 60 DMA2_STR4 DMA2 Stream4 interrupt 0x0000 0130 eth_sbd_intr_it 68 61 ETH Ethernet global interrupt 0x0000 0134 exti_eth_wkup 69 62 ETH_WKUP Ethernet wakeup through EXTI line interrupt 0x0000 0138 can_cal_it 70 63 FDCAN_CAL CAN2TX interrupts 0x0000 013C NC 71 64 - - 0x0000 0140 NC 72 65 - - 0x0000 0144 NC 73 66 - - 0x0000 0148 NC 74 67 - - 0x0000 014C dma2_it5 75 68 DMA2_STR5 DMA2 Stream5 interrupt 0x0000 0150 dma2_it6 76 69 DMA2_STR6 DMA2 Stream6 interrupt 0x0000 0154 dma2_it7 77 70 DMA2_STR7 DMA2 Stream7 interrupt 0x0000 0158 78 71 USART6 79 72 I2C3_EV I2C3 event interrupt 0x0000 0160 i2c3_err_it 80 73 I2C3_ER I2C3 error interrupt 0x0000 0164 usb1_out_it 81 74 usb1_in_it 82 75 OTG_HS_EP1_IN OTG_HS in global interrupt 0x0000 016C exti_usb1_wkup 83 76 OTG_HS_WKUP OTG_HS wakeup interrupt 0x0000 0170 usb1_gbl_it 84 77 OTG_HS OTG_HS global interrupt 0x0000 0174 dcmi_it 85 78 DCMI DCMI global interrupt 0x0000 0178 cryp_it 86 79 CRYP CRYP global interrupt 0x0000 017C hash_rng_it 87 80 HASH_RNG HASH and RNG global interrupt 0x0000 0180 cpu_fpu_it 88 81 FPU CPU FPU 0x0000 0184 89 82 UART7 UART7 global interrupt 0x0000 0188 90 83 UART8 UART8 global interrupt 0x0000 018C 91 84 SPI4 SPI4 global interrupt 0x0000 0190 Signal dma2_it3 usart6_gbl_it exti_usart6_wkup i2c3_ev_it exti_i2c3_ev_wkup uart7_gbl_it exti_uart7_wkup uart8_gbl_it exti_uart8_wkup spi4_it exti_spi4_wkup Description USART6 global interrupt USART6 wakeup interrupt OTG_HS_EP1_OUT OTG_HS out global interrupt DocID029587 Rev 3 Address offset 0x0000 015C 0x0000 0168 695/3178 698 Nested Vectored Interrupt Controllers RM0433 Priority Table 130. NVIC(1) (continued) NVIC position Acronym 92 85 SPI5 SPI5 global interrupt 0x0000 0194 93 86 SPI6 SPI6 global interrupt 0x0000 0198 sai1_it 94 87 SAI1 SAI1 global interrupt 0x0000 019C ltdc_it 95 88 LTDC LCD-TFT global interrupt 0x0000 01A0 ltdc_err_it 96 89 LTDC_ER LCD-TFT error interrupt 0x0000 01A4 dma2d_gbl_it 97 90 DMA2D DMA2D global interrupt 0x0000 01A8 - 98 91 SAI2 SAI2 global interrupt 0x0000 01AC - 99 92 QUADSPI QuadSPI global interrupt 0x0000 01B0 100 93 LPTIM1 LPTIM1 global interrupt 0x0000 01B4 101 94 CEC HDMI-CEC global interrupt 0x0000 01B8 102 95 I2C4_EV I2C4 event interrupt 0x0000 01BC i2c4_err_it 103 96 I2C4_ER I2C4 error interrupt 0x0000 01C0 - 104 97 SPDIF SPDIFRX global interrupt 0x0000 01C4 usb2_out_it 105 98 usb2_in_it 106 99 OTG_FS_EP1_IN OTG_FS in global interrupt 0x0000 01CC exti_usb2_wkup 107 100 OTG_FS_WKUP OTG_FS wakeup 0x0000 01D0 usb2_gbl_it 108 101 OTG_FS OTG_FS global interrupt 0x0000 01D4 dmamux1_ovr_it 109 102 DMAMUX1_OV DMAMUX1 overrun interrupt 0x0000 01D8 hrtim1_mst_it 110 103 HRTIM1_MST HRTIM1 master timer interrupt 0x0000 01DC hrtim1_tima_it 111 104 HRTIM1_TIMA HRTIM1 timer A interrupt 0x0000 01E0 hrtim1_timb_it 112 105 HRTIM_TIMB HRTIM1 timer B interrupt 0x0000 01E4 hrtim1_timc_it 113 106 HRTIM1_TIMC HRTIM1 timer C interrupt 0x0000 01E8 hrtim1_timd_it 114 107 HRTIM1_TIMD HRTIM1 timer D interrupt 0x0000 01EC hrtim1_time_it 115 108 HRTIM_TIME HRTIM1 timer E interrupt 0x0000 01F0 hrtim1_fault_it 116 109 HRTIM1_FLT HRTIM1 fault interrupt 0x0000 01F4 dfsdm1_it0 117 110 DFSDM1_FLT0 DFSDM1 filter 0 interrupt 0x0000 01F8 dfsdm1_it1 118 111 DFSDM1_FLT1 DFSDM1 filter 1 interrupt 0x0000 01FC dfsdm1_it2 119 112 DFSDM1_FLT2 DFSDM1 filter 2 interrupt 0x0000 0200 Signal spi5_it exti_spi5_wkup spi6_it exti_spi6_wkup lptim1_it exti_lptim_wkup cec_it exti_cec_it i2c4_ev_it exti_i2c4_ev_it 696/3178 Description OTG_FS_EP1_OUT OTG_FS out global interrupt DocID029587 Rev 3 Address offset 0x0000 01C8 RM0433 Nested Vectored Interrupt Controllers Priority Table 130. NVIC(1) (continued) NVIC position Acronym 120 113 DFSDM1_FLT3 121 114 SAI3 122 115 SWPMI1 tim15_gbl_it 123 116 TIM15 TIM15 global interrupt 0x0000 0210 tim16_gbl_it 124 117 TIM16 TIM16 global interrupt 0x0000 0214 tim17_gbl_it 125 118 TIM17 TIM17 global interrupt 0x0000 0218 - 126 119 MDIOS_WKUP MDIOS wakeup 0x0000 021C mdios_it 127 120 MDIOS MDIOS global interrupt 0x0000 0220 - 128 121 JPEG JPEG global interrupt 0x0000 0224 mdma_it 129 122 MDMA MDMA 0x0000 0228 - 131 124 SDMMC SDMMC global interrupt 0x0000 0230 hsem_it 132 125 HSEM0 HSEM global interrupt 1 0x0000 0234 - 133 - - - 134 127 ADC3 - 135 128 DMAMUX2_OVR bdma_ch0_it 136 129 bdma_ch1_it 137 bdma_ch2_it Signal dfsdm1_it3 sai3_gbl_it_it swpmi_gbl_it exti_swpmi_wup Description Address offset DFSDM1 filter 3 interrupt 0x0000 0204 SAI3 global interrupt 0x0000 0208 SWPMI global interrupt SWPMI wakeup - 0x0000 020C 0x0000 0238 ADC3 global interrupt 0x0000 023C DMAMUX2 overrun interrupt 0x0000 0240 BDMA_CH1 BDMA channel 1 interrupt 0x0000 0244 130 BDMA_CH2 BDMA channel 2 interrupt 0x0000 0248 138 131 BDMA_CH3 BDMA channel 3 interrupt 0x0000 024C bdma_ch3_it 139 132 BDMA_CH4 BDMA channel 4 interrupt 0x0000 0250 bdma_ch4_it 140 133 BDMA_CH5 BDMA channel 5 interrupt 0x0000 0254 bdma_ch5_it 141 134 BDMA_CH6 BDMA channel 6 interrupt 0x0000 0258 bdma_ch6_it 142 135 BDMA_CH7 BDMA channel 7 interrupt 0x0000 025C bdma_ch7_it 143 136 BDMA_CH8 BDMA channel 8 interrupt 0x0000 0260 144 137 COMP COMP1 and COMP2 global interrupt 0x0000 0264 145 138 LPTIM2 LPTIM2 timer interrupt 0x0000 0268 146 139 LPTIM3 LPTIM2 timer interrupt 0x0000 026C 147 140 LPTIM4 LPTIM2 timer interrupt 0x0000 0270 comp_gbl_it exti_comp1_wkup exti_comp2_wkup lptim2_it exti_lptim2_wkup lptim3_it exti_lptim3_wkup lptim4_it exti_lptim4_wkup DocID029587 Rev 3 697/3178 698 Nested Vectored Interrupt Controllers RM0433 Priority Table 130. NVIC(1) (continued) NVIC position Acronym 148 141 LPTIM5 LPTIM2 timer interrupt 0x0000 0274 149 142 LPUART LPUART global interrupt 0x0000 0278 exti_d1_wwdg1_wkup 150 143 WWDG1_RST Window Watchdog interrupt 0x0000 027C crs_it 151 144 CRS Clock Recovery System global interrupt 0x0000 0280 - 152 145 - - 0x0000 0284 - 153 146 SAI4 - 154 147 - - 0x0000 028C - 155 148 - - 0x0000 0290 156 149 WKUP Signal lptim5_it exti_lptim5_wkup Description Address offset lpuart_gbl_it exti_lpuart_rx_it exti_lpuart_tx_it SAI4 global interrupt 0x0000 0288 exti_wkup1_wkup exti_wkup2_wkup exti_wkup3_wkup exti_wkup4_wkup WKUP1 to WKUP6 pins exti_wkup5_wkup exti_wkup6_wkup 1. When different signals are connected to the same NVIC interrupt line, they are OR-ed. 698/3178 DocID029587 Rev 3 0x0000 0294 RM0433 20 Extended interrupt and event controller (EXTI) Extended interrupt and event controller (EXTI) The Extended Interrupt and event controller (EXTI) manages wakeup through configurable and direct event inputs. It provides wakeup requests to the Power Control, and generates interrupt requests to the CPU NVIC and to the D3 domain DMAMUX2, and events to the CPU event input. The EXTI wakeup requests allow the system to be woken up from Stop mode, and the CPU to be woken up from CStop mode. Both the interrupt request and event request generation can also be used in Run modes. 20.1 EXTI main features The EXTI main features are the following: • All Event inputs allow the CPU to wakeup and to generate a CPU interrupt and/or CPU event • Some Event inputs allow the user to wakeup the D3 domain for autonomous Run mode and generate an interrupt to the D3 domain, i.e. the DMAMUX2 The asynchronous event inputs are classified in 2 groups: • • 20.2 Configurable events (signals from I/Os or peripherals able to generate a pulse), they have the following features: – Selectable active trigger edge – Interrupt pending status register bit – Individual Interrupt and Event generation mask – SW trigger possibility – Configurable System D3 domain wakeup events have a D3 Pending mask and status register and may have a D3 interrupt signal. Direct events (interrupt and wakeup sources from other peripherals, requiring to be cleared in the peripheral), they feature – Fixed rising edge active trigger – No interrupt pending status register bit in the EXTI (the interrupt pending status is provided by the peripheral generating the event) – Individual Interrupt and Event generation mask – No SW trigger possibility – Direct system D3 domain wakeup events have a D3 Pending mask and status register and may have a D3 interrupt signal EXTI block diagram As shown in Figure 79, the EXTI consists of a Register block accessed via an APB interface, an Event input Trigger block, and a Masking block. The Register block contains all EXTI registers. The Event input trigger block provides Event input edge triggering logic. DocID029587 Rev 3 699/3178 730 Extended interrupt and event controller (EXTI) RM0433 The Masking block provides the Event input distribution to the different wakeup, interrupt and event outputs, and their masking. Figure 79. EXTI block diagram $3%LQWHUIDFH 5HJLVWHUV &RQILJXUDEOHHYHQW [ FSXBLWBH[WLBSHU [ 3HULSKHUDOV FSXBHYHQW (YHQW 7ULJJHU HYHQWV QYLF Q U[HY &38 H[WLBFSXBZNXS 0DVNLQJ H[WLBGBZNXS 'LUHFWHYHQW [ 3:5 GBLWBH[WLBSHU [ GBSHQGFOHDUBLQ> @ ' (;7, 06Y 9 20.2.1 EXTI connections between peripherals, CPU, and D3 domain The peripherals able to generate wakeup events when the system is in Stop mode or the CPU is in CStop mode are connected to an EXTI Configurable event input or Direct Event input: • Peripheral signals that generate a pulse are connected to an EXTI Configurable Event input. For these events the EXTI provides a CPU status pending bit that has to be cleared. • Peripheral Interrupt and Wakeup sources that have to be cleared in the peripheral are connected to an EXTI Direct Event input. There is no CPU status pending bit within the EXTI. The Interrupt or Wakeup is cleared by the CPU in the peripheral. The Event inputs able to wakeup D3 for autonomous Run mode are provided with a D3 domain pending request function, that has to be cleared. This clearing request is taken care of by the signal selected by the Pending clear selection. The CPU interrupts are connected to their respective CPU NVIC, and, similarly, the CPU event is connected to the CPU rxev input. The EXTI Wakeup signals are connected to the PWR block, and are used to wakeup the D3 domain and/or the CPU. The D3 domain interrupts allow the system to trigger events for D3 domain autonomous Run mode operation. 700/3178 DocID029587 Rev 3 RM0433 EXTI functional description Depending on the EXTI Event input type and wakeup target(s), different logic implementations are used. The applicable features are controlled from register bits: • Active trigger edge enable, by EXTI rising trigger selection register (EXTI_RTSR1), EXTI rising trigger selection register (EXTI_RTSR2), EXTI rising trigger selection register (EXTI_RTSR3), and EXTI falling trigger selection register (EXTI_FTSR1), EXTI falling trigger selection register (EXTI_FTSR2), EXTI falling trigger selection register (EXTI_FTSR3) • Software trigger, by EXTI software interrupt event register (EXTI_SWIER1), EXTI software interrupt event register (EXTI_SWIER2), EXTI software interrupt event register (EXTI_SWIER3) • CPU Interrupt enable, by EXTI interrupt mask register (EXTI_CPUIMR1), EXTI interrupt mask register (EXTI_CPUIMR2), EXTI interrupt mask register (EXTI_CPUIMR3) • CPU Event enable, by EXTI event mask register (EXTI_CPUEMR1), EXTI event mask register (EXTI_CPUEMR2), EXTI event mask register (EXTI_CPUEMR3) • D3 domain wakeup pending, by EXTI D3 pending mask register (EXTI_D3PMR1), EXTI D3 pending mask register (EXTI_D3PMR2), EXTI D3 pending mask register (EXTI_D3PMR3) CPU Configurable event input, CPU wakeup logic Any(2) Configurable event input, Any wakeup logic CPU Direct event input, CPU wakeup logic Any(2) Direct event input, Any wakeup logic X X X X X - - - X X EXTI_D3PMR EXTI_CPUEMR Direct Logic implementation EXTI_CPUIMR Configurable Wakeup target(s) EXTI_SWIER Event input type EXTI_FTSR Table 131. EXTI Event input configurations and register control(1) EXTI_RTSR 20.3 Extended interrupt and event controller (EXTI) X X 1. X indicates that functionality is available. 2. Waking-up D3 domain for autonomous Run mode, and/or CPU. DocID029587 Rev 3 701/3178 730 Extended interrupt and event controller (EXTI) 20.3.1 RM0433 EXTI Configurable event input CPU wakeup Figure 81 is a detailed representation of the logic associated with Configurable Event inputs which will always wake up the CPU. Figure 80. Configurable event triggering logic CPU wakeup 3HULSKHUDOLQWHUIDFH 5LVLQJ WULJJHU VHOHFWLRQ UHJLVWHU &38 (YHQW PDVN UHJLVWHU &38 ,QWHUUXSW PDVN UHJLVWHU &38 3HQGLQJ UHTXHVW UHJLVWHU UFFBIFONBFSX FSXBLWBH[WLBSHU [ )DOOLQJ WULJJHU VHOHFWLRQ UHJLVWHU $V\QFKURQRXV HGJHGHWHFWLRQ FLUFXLW UVW &RQILJXUDEOH (YHQWLQSXW [ 'HOD\ UFFBIFONBFSX &38 5LVLQJ(GJH GHWHFW3XOVH JHQHUDWRU &38(YHQW [ 2WKHU&38(YHQWV &38:DNHXS [ 2WKHU&38 :DNHXSV 6\QFK FNBV\V ':DNHXS [ 2WKHU':DNHXSV (;7, FSXBHYHQW 6RIWZDUH LQWHUUXSW HYHQW UHJLVWHU GBZDNHXS FSXBZDNHXS $3% LQWHUIDFH 06Y 9 The Software interrupt event register allows the system to trigger Configurable events by software, writing the EXTI software interrupt event register (EXTI_SWIER1), the EXTI software interrupt event register (EXTI_SWIER2), or the EXTI software interrupt event register (EXTI_SWIER3) register bit. The rising edge EXTI rising trigger selection register (EXTI_RTSR1), EXTI rising trigger selection register (EXTI_RTSR2), EXTI rising trigger selection register (EXTI_RTSR3), and falling edge EXTI falling trigger selection register (EXTI_FTSR1), EXTI falling trigger selection register (EXTI_FTSR2), EXTI falling trigger selection register (EXTI_FTSR3) selection registers allow the system to enable and select the Configurable event active trigger edge or both edges. The devices feature dedicated interrupt mask registers, namely EXTI interrupt mask register (EXTI_CPUIMR1) and EXTI interrupt mask register (EXTI_CPUIMR2), EXTI interrupt mask register (EXTI_CPUIMR3), and EXTI pending register (EXTI_CPUPR1), EXTI pending register (EXTI_CPUPR2), EXTI pending register (EXTI_CPUPR3) for Configurable events pending request registers. The CPU pending register will only be set for an unmasked CPU interrupt. Each event provides a individual CPU interrupt to the CPU NVIC. The Configurable events interrupts need to be acknowledged by software in the EXTI_CPUPR register. 702/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) The devices feature dedicated event mask registers, i.e. EXTI event mask register (EXTI_CPUEMR1), EXTI event mask register (EXTI_CPUEMR2), and EXTI event mask register (EXTI_CPUEMR3). The enabled event then generates an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The CPU Pending register (EXTI_CPUPR) will not be set for an unmasked CPU event. When a CPU interrupt or CPU event is enabled, the Asynchronous edge detection circuit is reset by the clocked Delay and Rising edge detect pulse generator. This guarantees that the CPU clock is woken up before the Asynchronous edge detection circuit is reset. Note: A detected Configurable event, enabled by the CPU, is only cleared when the CPU wakes up. 20.3.2 EXTI configurable event input Any wakeup Figure 81 is a detailed representation of the logic associated with Configurable Event inputs that can wakeup D3 domain for autonomous Run mode and/or CPU (“Any” target). It provides the same functionality as the Configurable event input CPU wakeup, with additional functionality to wake up the D3 domain independently. When all CPU interrupts and CPU events are disabled, the Asynchronous edge detection circuit is reset by the D3 domain clocked Delay and Rising edge detect pulse generator. This guarantees that the D3 domain clock is woken up before the Asynchronous edge detection circuit is reset. EXTI_C1IMR EXTI_C1EMR Table 132. Configurable Event input Asynchronous Edge detector reset Asynchronous Edge detector reset by Both = 0 D3 domain clock rising edge detect pulse generator At least one = 1 CPU clock rising edge detect pulse generator DocID029587 Rev 3 703/3178 730 Extended interrupt and event controller (EXTI) RM0433 Figure 81. Configurable event triggering logic Any wakeup 3HULSKHUDOLQWHUIDFH $3% LQWHUIDFH &38 3HQGLQJ UHTXHVW UHJLVWHU $V\QFKURQRXV HGJHGHWHFWLRQ FLUFXLW UVW &RQILJXUDEOH (YHQW LQSXW [ 'HOD\ UFFBIFONBFSX &38 5LVLQJ(GJH GHWHFW3XOVH JHQHUDWRU ' 3HQGLQJ PDVN UHJLVWHU 2WKHU&38(YHQWV &38(YHQW [ FNBIFONBG 'HOD\ ' 3HQGLQJ UHTXHVW ''RPDLQ 5LVLQJ(GJH GHWHFW3XOVH JHQHUDWRU FNBIFONBG 2WKHU&38 :DNHXSV &38:DNHXS [ 6\QFK FNBV\V ':DNHXS [ 2WKHU':DNHXSV (;7, FSXBLWBH[WLBSHU [ &38 ,QWHUUXSW PDVN UHJLVWHU FSXBHYHQW &38 (YHQW PDVN UHJLVWHU GBZDNHXS FSXBZDNHXS 5LVLQJ WULJJHU VHOHFWLRQ UHJLVWHU GBLWBDLHFBSHU [ GBSHQGFOHDU [ )DOOLQJ WULJJHU VHOHFWLRQ UHJLVWHU UFFBIFONBFSX 6RIWZDUH LQWHUUXSW HYHQW UHJLVWHU 06Y 9 The event triggering logic for “Any” target has additional D3 Pending mask register EXTI D3 pending mask register (EXTI_D3PMR1), EXTI D3 pending mask register (EXTI_D3PMR2), EXTI D3 pending mask register (EXTI_D3PMR3)and D3 Pending request logic. The D3 Pending request logic will only be set for unmasked D3 Pending events. The D3 Pending request logic keeps the D3 domain in Run mode until the D3 Pending request logic is cleared by the selected D3 domain pendclear source. 704/3178 DocID029587 Rev 3 RM0433 20.3.3 Extended interrupt and event controller (EXTI) EXTI direct event input CPU wakeup Figure 82 is a detailed representation of the logic associated with Direct Event inputs waking up the CPU. Direct events only provide CPU interrupt enable and CPU event enable functionality. Figure 82. Direct event triggering logic CPU Wakeup 3HULSKHUDOLQWHUIDFH $3% LQWHUIDFH FSXBLWBH[WLBSHU [ UFFBIFONBFSX &38 ,QWHUUXSWPDVNUHJLVWHU FNBV\V 6\QFK 'HOD\ 'LUHFW(YHQW LQSXW [ $V\QFKURQRXV 5LVLQJHGJH GHWHFWLRQFLUFXLW UVW UFFBIFONBFSX &38 5LVLQJ(GJH GHWHFW 3XOVHJHQHUDWRU 2WKHU&38(YHQWV &38(YHQW [ FSXBHYHQW &38 (YHQWPDVNUHJLVWHU )DLOLQJHGJH GHWHFW 3XOVHJHQHUDWRU &38:DNHXS [ ':DNHXS [ 2WKHU':DNHXSV (;7, GBZDNHXS FSXBZDNHXS 2WKHU&38 :DNHXSV 6\QFK FNBV\V FNBV\V 06Y 9 1. The CPU interrupt for asynchronous Direct Event inputs (peripheral Wakeup signals) is synchronized with the CPU clock. The synchronous Direct Event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt without resynchronization. DocID029587 Rev 3 705/3178 730 Extended interrupt and event controller (EXTI) 20.3.4 RM0433 EXTI direct event input Any wakeup Figure 83 is a detailed representation of the logic associated with Direct Event inputs waking up D3 domain for autonomous Run mode and/or CPU, (“Any” target). It provides the same functionality as the Direct event input CPU wakeup, plus additional functionality to wakeup the D3 domain independently. &38 ,QWHUUXSWPDVNUHJLVWHU ' 3HQGLQJPDVNUHJLVWHU FNBIFONBG FNBIFONBG ' 3HQGLQJ UHTXHVW 6\QFK UFFBIFONBFSX FNBV\V 6\QFK UFFBIFONBFSX 'LUHFW(YHQW LQSXW [ $V\QFKURQRXV 5LVLQJHGJH GHWHFWLRQFLUFXLW UVW &38 5LVLQJ(GJH GHWHFW 3XOVHJHQHUDWRU &38(YHQW [ FSXBHYHQW 'HOD\ 2WKHU&38(YHQWV GBSHQGLQJ GBLWBH[WLBSHU [ &38 (YHQWPDVNUHJLVWHU FSXBLWBH[WLBSHU [ 3HULSKHUDOLQWHUIDFH $3% LQWHUIDFH GBSHQGFOHDU [ Figure 83. Direct event triggering logic Any Wakeup &38:DNHXS [ FNBV\V 2WKHU':DNHXSV (;7, ':DNHXS [ GBZDNHXS FSXBZDNHXS 2WKHU&38 :DNHXSV 6\QFK FNBV\V )DLOLQJHGJH GHWHFW 3XOVHJHQHUDWRU 06Y 9 1. The CPU interrupt and D3 domain interrupt for asynchronous Direct Event inputs (peripheral Wakeup signals) are synchronized, respectively, with the CPU clock and the D3 domain clock. The synchronous Direct Event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt and the D3 domain interrupt without resynchronization in the EXTI. 706/3178 DocID029587 Rev 3 RM0433 20.3.5 Extended interrupt and event controller (EXTI) EXTI D3 pending request clear selection Event inputs able to wake up D3 domain for autonomous Run mode have D3 Pending request logic that can be cleared by the selected D3 pendclear source. For each D3 Pending request a D3 domain pendclear source can be selected from four different inputs. Figure 84 is a detailed representation of the logic selecting the D3 pendclear source. Figure 84. D3 domain Pending request clear logic $3%LQWHUIDFH 3HULSKHUDOLQWHUIDFH ' SHQGLQJFOHDU VHOHFWLRQUHJLVWHU (YHQW [ ' SHQGLQJ UHTXHVW GBSHQGFOHDU [ GBSHQGFOHDUBLQ>@ '0$BFKBHYW GBSHQGFOHDUBLQ>@ '0$BFKBHYW GBSHQGFOHDUBLQ>@ /37,0RXW GBSHQGFOHDUBLQ>@ /37,0RXW (;7, 069 The D3 Pending request clear selection registers EXTI D3 pending clear selection register low (EXTI_D3PCR1L), EXTI D3 pending clear selection register high (EXTI_D3PCR1H), EXTI D3 pending clear selection register low (EXTI_D3PCR2L), EXTI D3 pending clear selection register high (EXTI_D3PCR2H), EXTI D3 pending clear selection register low (EXTI_D3PCR3L) and EXTI D3 pending clear selection register high (EXTI_D3PCR3H) allow the system to select the source to reset the D3 Pending request. 20.4 EXTI event input mapping For the sixteen GPIO Event inputs the associated IOPORT pin has to be selected in the SYSCFG register SYSCFG_EXTICRn. The same pin from each IOPORT maps to the corresponding EXTI Event input. The wakeup capabilities of each Event input are detailed in Table 133. An Event input can either wake up the CPU, and in the case of “Any” can also wake up D3 domain for autonomous Run mode. The EXTI Event inputs with a connection to the CPU NVIC are indicated in the Connection to NVIC column. For the EXTI events not having a connection to the NVIC, the peripheral interrupt is directly connected to the NVIC in parallel with the connection to the EXTI. All EXTI Event inputs are OR-ed together and connected to the CPU event input (rxev). DocID029587 Rev 3 707/3178 730 Extended interrupt and event controller (EXTI) RM0433 Table 133. EXTI Event input mapping Event input 0 - 15 Source EXTI[15:0] (1) Event input type Wakeup target(s) Connection to NVIC Configurable Any Yes 16 PVD and AVD Configurable CPU only Yes 17 RTC alarms Configurable CPU only Yes 18 RTC tamper, RTC timestamp, RCC LSECSS(2) Configurable CPU only Yes 19 RTC wakeup timer Configurable Any Yes 20 COMP1 Configurable Any Yes 21 COMP2 Configurable Any Yes 22 I2C1 wakeup Direct CPU only Yes 23 I2C2 wakeup Direct CPU only Yes 24 I2C3 wakeup Direct CPU only Yes 25 I2C4 wakeup Direct Any Yes 26 USART1 wakeup Direct CPU only Yes 27 USART2 wakeup Direct CPU only Yes 28 USART3 wakeup Direct CPU only Yes 29 USART6 wakeup Direct CPU only Yes 30 UART4 wakeup Direct CPU only Yes 31 UART5 wakeup Direct CPU only Yes 32 UART7 wakeup Direct CPU only Yes 33 UART8 wakeup Direct CPU only Yes 34 LPUART1 RX wakeup Direct Any Yes 35 LPUART1 TX wakeup Direct Any Yes 36 SPI1 wakeup Direct CPU only Yes 37 SPI2 wakeup Direct CPU only Yes 38 SPI3 wakeup Direct CPU only Yes 39 SPI4 wakeup Direct CPU only Yes 40 SPI5 wakeup Direct CPU only Yes 41 SPI6 wakeup Direct Any Yes 42 MDIO wakeup Direct CPU only Yes 43 USB1 wakeup Direct CPU only Yes 44 USB2 wakeup Direct CPU only Yes 45 Reserved - - - 46 Reserved - - - 47 LPTIM1 wakeup Direct CPU only Yes 48 LPTIM2 wakeup Direct Any Yes 708/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) Table 133. EXTI Event input mapping (continued) Event input Source Event input type Wakeup target(s) Connection to NVIC Configurable Any No(3) Direct Any Yes Configurable Any No(3) 49 LPTIM2 output 50 LPTIM3 wakeup 51 LPTIM3 output 52 LPTIM4 wakeup Direct Any Yes 53 LPTIM5 wakeup Direct Any Yes 54 SWPMI wakeup Direct CPU only Yes 55 WKUP1 Direct CPU only Yes 56 WKUP2 Direct CPU only Yes 57 WKUP3 Direct CPU only Yes 58 WKUP4 Direct CPU only Yes 59 WKUP5 Direct CPU only Yes 60 WKUP6 Direct CPU only Yes 61 RCC interrupt Direct CPU only No(4) 62 I2C4 Event interrupt Direct CPU only No(4) 63 I2C4 Error interrupt Direct CPU only No(4) 64 LPUART1 global Interrupt Direct CPU only No(4) 65 SPI6 interrupt Direct CPU only No(4) 66 BDMA CH0 interrupt Direct CPU only No(4) 67 BDMA CH1 interrupt Direct CPU only No(4) 68 BDMA CH2 interrupt Direct CPU only No(4) 69 BDMA CH3 interrupt Direct CPU only No(4) 70 BDMA CH4 interrupt Direct CPU only No(4) 71 BDMA CH5 interrupt Direct CPU only No(4) 72 BDMA CH6 interrupt Direct CPU only No(4) 73 BDMA CH7 interrupt Direct CPU only No(4) 74 DMAMUX2 interrupt Direct CPU only No(4) 75 ADC3 interrupt Direct CPU only No(4) 76 SAI4 interrupt Direct CPU only No(4) 77 Reserved - - - 78 Reserved - - - 79 Reserved - - - 80 Reserved - - - 81 Reserved - - - 82 Reserved - - - 83 Reserved - - - DocID029587 Rev 3 709/3178 730 Extended interrupt and event controller (EXTI) RM0433 Table 133. EXTI Event input mapping (continued) Event input Source Event input type Wakeup target(s) Connection to NVIC - - - 84 Reserved 85 HDMI-CEC wakeup Configurable CPU only Yes 86 ETHERNET wakeup Configurable CPU only Yes 87 HSECSS interrupt Direct CPU only No(4) 88 Reserved - - - 1. PVD and AVD signals are OR-ed together on the same EXTI event input. 2. RTC Tamper, RTC timestamp and RCC LSECSS signals are OR-ed together on the same EXTI event input. 3. Not available on CPU NVIC, to be used for system wakeup only or CPU event input (rxev). 4. Available on CPU NVIC directly from the peripheral 20.5 EXTI functional behavior The Direct event inputs are enabled in the respective peripheral generating the event. The Configurable events are enabled by enabling at least one of the trigger edges. When in Stop mode an event will always wake up the D3 domain. In system Run and Stop modes an event will always generate an associated D3 domain interrupt. An event will only wake up the CPU when the event associated CPU interrupt is unmasked and/or the CPU event is unmasked. Table 134. Masking functionality CPU Interrupt enable MRx bits of EXTI_CPUIMR Event enable MRx bits of EXTI_CPUEMR 0 0 0 Configurable event inputs PRx bits of EXTI_CPUPR CPU D3 domain wakeup Interrupt Event Wakeup No Masked Masked Masked Yes(1) / Masked(2) 1 No Masked Yes Yes Yes 1 0 Status latched Yes Masked Yes Yes 1 1 Status latched Yes Yes Yes Yes 1. Only for Event inputs that allow the system to wakeup D3 domain for autonomous Run mode (Any target). 2. For Event inputs that will always wake up CPU. For Configurable event inputs, when the enabled edge(s) occur on the event input, an event request is generated. When the associated CPU interrupt is unmasked, the corresponding pending PRx bit in EXTI_CPUPR is set and the CPU interrupt signal is activated. EXTI_CPUPR PRx pending bit shall be cleared by software writing it to ‘1’. This will clear the CPU interrupt. For Direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit. When the associated CPU interrupt is unmasked the corresponding CPU interrupt signal is activated. 710/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) The CPU event has to be unmasked to generate an event. When the enabled edge(s) occur on the Event input a CPU event pulse is generated. There is no CPU Event pending bit. Both a CPU interrupt and a CPU event may be enabled on the same Event input. They will both trigger the same Event input condition(s). For the Configurable Event inputs an event input request can be generated by software when writing a ‘1’ in the software interrupt/event register EXTI_SWIER. Whenever an Event input is enabled and a CPU interrupt and/or CPU event is unmasked, the Event input will also generate a D3 domain wakeup next to the CPU wakeup. Some Event inputs are able to wakeup the D3 domain autonomous Run mode, in this case the CPU interrupt and CPU event are masked, preventing the CPU to be woken up. Two D3 domain autonomous Run mode wakeup mechanisms are supported: • • 20.5.1 D3 domain wakeup without pending (EXTI_D3PMR = 0) – On a Configurable Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal automatically after the Delay + Rising Edge detect Pulse generator. – On a Direct Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal after the Direct Event input signal is cleared. D3 domain wakeup with pending (EXTI_D3PMR = 1) – On a Configurable Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal after the Delay + Rising Edge detect Pulse generator and when the D3 Pending request is cleared. – On a Direct Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal after the Direct Event input signal is cleared and when the D3 Pending request is cleared. EXTI CPU interrupt procedure • Unmask the Event input interrupt by setting the corresponding mask bits in the EXTI_CPUIMR register. • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers. • Enable the associated interrupt source in the CPU NVIC or use the SEVONPEND, so that an interrupt coming from the CPU interrupt signal is detectable by the CPU after a WFI/WFE instruction. – 20.5.2 For Configurable event inputs the associated EXTI pending bit needs to be cleared. EXTI CPU event procedure • Unmask the Event input by setting the corresponding mask bits of the EXTI_CPUEMR register. • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers. • The CPU event signal is detected by the CPU after a WFE instruction. – For Configurable event inputs there is no EXTI pending bit to clear. DocID029587 Rev 3 711/3178 730 Extended interrupt and event controller (EXTI) 20.5.3 20.5.4 EXTI CPU wakeup procedure • Unmask the Event input by setting at least one of the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers. The CPU wakeup is generated at the same time as the unmasked CPU interrupt and/or CPU event. • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers. • Direct Events will automatically generate a CPU wakeup. EXTI D3 domain wakeup for autonomous Run mode procedure • Mask the Event input for waking up the CPU, by clearing both the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers. • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers. • Direct Events will automatically generate a D3 domain wakeup. • Select the D3 domain wakeup mechanism in EXTI_D3PMR. • 20.5.5 RM0433 – When D3 domain wakeup without pending (EXTI_PMR = 0) is selected, the Wakeup will be cleared automatically following the clearing of the Event input. – When D3 domain wakeup with pending (EXTI_PMR = 1) is selected the Wakeup needs to be cleared by a selected D3 domain pendclear source. A pending D3 domain wakeup signal can also be cleared by FW clearing the associated EXTI_D3PMR register bit. After the D3 domain wakeup a D3 domain interrupt is generated. – Configurable Event inputs will generate a pulse on D3 domain interrupt. – Direct Event inputs will activate the D3 domain interrupt until the event input is cleared in the peripheral. EXTI software interrupt/event trigger procedure Any of the Configurable Event inputs can be triggered from the software interrupt/event register (the associated CPU interrupt and/or CPU event shall be enabled by their respective procedure). Note: • Enable the Event input by setting at least one of the corresponding edge trigger bits in the EXTI_RTSR and/or EXTI_FTSR registers. • Unmask the software interrupt/event trigger by setting at least one of the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers. • Trigger the software interrupt/event by writing “1” to the corresponding bit in the EXTI_SWIER register. • The Event input may be disabled by clearing the EXTI_RTSR and EXTI_FTSR register bits. An edge on the Configurable event input will also trigger an interrupt/event. A software trigger can be used to set the D3 Pending request logic, keeping the D3 domain in Run until the D3 Pending request logic is cleared. 712/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) 20.6 EXTI register description Every register can only be accessed with 32-bit (word). A byte or half-word cannot be read or written. 20.6.1 EXTI rising trigger selection register (EXTI_RTSR1) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR21 TR20 TR19 TR18 TR17 TR16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:0 TRx: Rising trigger event configuration bit of Configurable Event input x.(1) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set. Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger. 20.6.2 EXTI falling trigger selection register (EXTI_FTSR1) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR21 TR20 TR19 TR18 TR17 TR16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:0 TRx: Falling trigger event configuration bit of Configurable Event input x.(1) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set. Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger. DocID029587 Rev 3 713/3178 730 Extended interrupt and event controller (EXTI) 20.6.3 RM0433 EXTI software interrupt event register (EXTI_SWIER1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 SWIER SWIER SWIER SWIER SWIER SWIER SWIER 15 14 13 12 11 10 9 rw rw rw rw rw rw rw 21 20 19 18 17 16 SWIER SWIER SWIER SWIER SWIER SWIER 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:0 SWIERx: Software interrupt on line x Will alway return 0 when read. 0: Writing 0 has no effect. 1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW. 20.6.4 EXTI D3 pending mask register (EXTI_D3PMR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. MR25 Res. Res. Res. MR21 MR20 MR19 Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 MRx: D3 Pending Mask on Event input x 0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. Bits 24:22 Reserved, must be kept at reset value. 714/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) Bits 21:19 MRx: D3 Pending Mask on Event input x 0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. Bits 18:16 Reserved, must be kept at reset value. Bits 15:0 MRx: D3 Pending Mask on Event input x 0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. 20.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L) Address offset: 0x10 Reset value: 0x0000 0000 31 30 PCS15 29 28 PCS14 27 26 25 PCS13 24 23 PCS12 22 21 PCS11 20 19 PCS10 18 17 PCS9 16 PCS8 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCS7 rw PCS6 rw rw PCS5 rw rw PCS4 rw rw PCS3 rw rw PCS2 rw rw PCS1 rw rw PCS0 rw rw rw Bits 31:0 PCSx: D3 Pending request clear input signal selection on Event input x = truncate (n/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source 20.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. PCS21 rw rw PCS20 rw PCS19 rw rw 19 18 17 16 Res. Res. 2 1 0 Res. Res. Res. PCS25 rw DocID029587 Rev 3 715/3178 730 Extended interrupt and event controller (EXTI) RM0433 Bits 31:20 Reserved, must be kept at reset value. Bits 19:18 PCSx: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source Bits 17:12 Reserved, must be kept at reset value. Bits 11:6 PCSx: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source Bits 5:0 Reserved, must be kept at reset value. 20.6.7 EXTI rising trigger selection register (EXTI_RTSR2) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR51 Res. TR49 Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:20 Reserved, must be kept at reset value. Bit 19 TRx: Rising trigger event configuration bit of Configurable Event input x+32.(1) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bit 18 Reserved, must be kept at reset value. Bit 17 TRx: Rising trigger event configuration bit of Configurable Event input x+32.(1) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bits 16:0 Reserved, must be kept at reset value. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set. Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger. 716/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) 20.6.8 EXTI falling trigger selection register (EXTI_FTSR2) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR51 Res. TR49 Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw Bits 31:20 Reserved, must be kept at reset value. Bit 19 TRx: Falling trigger event configuration bit of Configurable Event input x+32.(1) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bit 18 Reserved, must be kept at reset value. Bit 17 TRx: Falling trigger event configuration bit of Configurable Event input x+32.(1) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bits 16:0 Reserved, must be kept at reset value. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set. Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger. 20.6.9 EXTI software interrupt event register (EXTI_SWIER2) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 SWIER 51 18 17 16 Res. SWIER 49 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw Bits 31:20 Reserved, must be kept at reset value. Bit 19 SWIERx: Software interrupt on line x+32 Will alway return 0 when read. 0: Writing 0 has no effect. 1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW. DocID029587 Rev 3 717/3178 730 Extended interrupt and event controller (EXTI) RM0433 Bit 18 Reserved, must be kept at reset value. Bit 17 SWIERx: Software interrupt on line x+32 Will alway return 0 when read. 0: Writing 0 has no effect. 1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW. Bits 16:0 Reserved, must be kept at reset value. 20.6.10 EXTI D3 pending mask register (EXTI_D3PMR2) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MR53 MR52 MR51 MR50 MR49 MR48 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. MR41 Res. Res. Res. Res. Res. MR35 MR34 Res. Res. rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:16 MRx: D3 Pending Mask on Event input x+32 0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. Bits 15:10 Reserved, must be kept at reset value. Bit 9 MRx: D3 Pending Mask on Event input x+32 0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. Bits 8:4 Reserved, must be kept at reset value. Bits 3:2 MRx: D3 Pending Mask on Event input x+32 0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. Bits 1:0 Reserved, must be kept at reset value. 718/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) 20.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. PCS35 rw PCS34 rw rw 19 18 PCS41 17 16 Res. Res. rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:18 PCSx: D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source Bits 17:8 Reserved, must be kept at reset value. Bits 7:4 PCSx: D3 Pending request clear input signal selection on Event input x= truncate ((n+64)/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source Bits 3:0 Reserved, must be kept at reset value. 20.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. PCS53 rw rw PCS52 rw PCS51 rw rw rw PCS50 rw rw PCS49 rw rw PCS48 rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 PCSx: D3 Pending request clear input signal selection on Event input x= truncate ((n+96)/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source DocID029587 Rev 3 719/3178 730 Extended interrupt and event controller (EXTI) 20.6.13 RM0433 EXTI rising trigger selection register (EXTI_RTSR3) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR86 TR85 TR84 Res. TR82 Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 TRx: Rising trigger event configuration bit of Configurable Event input x+64.(1) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bit 19 Reserved, must be kept at reset value. Bit 18 TRx: Rising trigger event configuration bit of Configurable Event input x+64.(1) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bits 17:0 Reserved, must be kept at reset value. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set. Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger. 20.6.14 EXTI falling trigger selection register (EXTI_FTSR3) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR86 TR85 TR84 Res. TR82 Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 TRx: Falling trigger event configuration bit of Configurable Event input x+64.(1) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line 720/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) Bit 19 Reserved, must be kept at reset value. Bit 18 TRx: Falling trigger event configuration bit of Configurable Event input x+64.(1) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bits 17:0 Reserved, must be kept at reset value. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set. Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger. 20.6.15 EXTI software interrupt event register (EXTI_SWIER3) Address offset: 0x48 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 SWIER SWIER SWIER 86 85 84 19 18 17 16 Res. SWIER 82 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 SWIERx: Software interrupt on line x+64 Will alway return 0 when read. 0: Writing 0 has no effect. 1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW. Bit 19 Reserved, must be kept at reset value. Bit 18 SWIERx: Software interrupt on line x+64 Will alway return 0 when read. 0: Writing 0 has no effect. 1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW. Bits 17:0 Reserved, must be kept at reset value. 20.6.16 EXTI D3 pending mask register (EXTI_D3PMR3) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. MR88 Res. Res. Res. Res. Res. Res. Res. Res. rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 721/3178 730 Extended interrupt and event controller (EXTI) RM0433 Bits 31:25 Reserved, must be kept at reset value. Bit 24 MRx: D3 Pending Mask on Event input x+64 0: D3 Pending request from Line x+64 is masked. Writing this bit to 0 will also clear the D3 Pending request. 1: D3 Pending request from Line x+64 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared. Bits 23:0 Reserved, must be kept at reset value. 20.6.17 EXTI D3 pending clear selection register low (EXTI_D3PCR3L) Address offset: 0x50 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:0 Reserved, must be kept at reset value. 20.6.18 EXTI D3 pending clear selection register high (EXTI_D3PCR3H) Address offset: 0x54 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17 16 PCS88 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:18 Reserved, must be kept at reset value. Bits 17:16 PCSx: D3 Pending request clear input signal selection on Event input x= truncate ((n+160)/2) 00: DMA ch6 event selected as D3 domain pendclear source 01: DMA ch7 event selected as D3 domain pendclear source 10: LPTIM4 out selected as D3 domain pendclear source 11: LPTIM5 out selected as D3 domain pendclear source Bits 15:0 Reserved, must be kept at reset value. 722/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) 20.6.19 EXTI interrupt mask register (EXTI_CPUIMR1) Address offset: 0x80 Reset value: 0xFFC0 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MR31 MR30 MR29 MR28 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 MRx: CPU interrupt Mask on Direct Event input x(1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bits 21:0 MRx: CPU interrupt Mask on Configurable Event input x (2) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked 1. The reset value for Direct Event inputs is set to ‘1’ in order to enable the interrupt by default. 2. The reset value for Configurable Event inputs is set to ‘0’ in order to disable the interrupt by default. 20.6.20 EXTI event mask register (EXTI_CPUEMR1) Address offset: 0x84 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MR31 MR30 MR29 MR28 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 MRx: CPU Event mask on Event input x 0: Event request from Line x is masked 1: Event request from Line x is unmasked DocID029587 Rev 3 723/3178 730 Extended interrupt and event controller (EXTI) 20.6.21 RM0433 EXTI pending register (EXTI_CPUPR1) Address offset: 0x88 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR21 PR21 PR19 PR18 PR17 PR16 rc1 rc1 rc1 rc1 rc1 rc1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 Bits 31:22 Reserved, must be kept at reset value. Bits 21:0 PRx: Configurable event inputs x Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. 20.6.22 EXTI interrupt mask register (EXTI_CPUIMR2) Address offset: 0x90 Reset value: 0xFFF5 FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MR63 MR62 MR61 MR60 MR59 MR58 MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50 MR49 MR48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR47 MR46 Res. MR44 MR43 MR42 MR41 MR40 MR39 MR38 MR37 MR36 MR35 MR34 MR33 MR32 rw rw 1 rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 MRx: CPU Interrupt Mask on Direct Event input x+32(1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bit 19 MRx: CPU interrupt Mask on Configurable Event input x+32 (2) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bit 18 MRx: CPU Interrupt Mask on Direct Event input x+32 (1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bit 17 MRx: CPU interrupt Mask on Configurable Event input x+32 (2) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked 724/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) Bits 16:14 MRx: CPU Interrupt Mask on Direct Event input x+32 (1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bit 13 Reserved, must be kept at reset value (1). Bits 12:0 MRx: CPU Interrupt Mask on Direct Event input x+32 (1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked 1. The reset value for Direct Event inputs is set to ‘1’ in order to enable the interrupt by default. 2. The reset value for Configurable Event inputs is set to ‘0’ in order to disable the interrupt by default. 20.6.23 EXTI event mask register (EXTI_CPUEMR2) Address offset: 0x94 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MR63 MR62 MR61 MR60 MR59 MR58 MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50 MR49 MR48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR47 MR46 Res. MR44 MR43 MR42 MR41 MR40 MR39 MR38 MR37 MR36 MR35 MR34 MR33 MR32 rw rw 0 rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:14 MRx: CPU Event mask on Event input x+32 0: Event request from Line x is masked 1: Event request from Line x is unmasked Bit 13 Reserved, must be kept at reset value. Bits 12:0 MRx: CPU Event mask on Event input x+32 0: Event request from Line x is masked 1: Event request from Line x is unmasked 20.6.24 EXTI pending register (EXTI_CPUPR2) Address offset: 0x98 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR51 Res. PR49 Res. rc1 rc1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 725/3178 730 Extended interrupt and event controller (EXTI) RM0433 Bits 31:20 Reserved, must be kept at reset value. Bit 19 PRx: Configurable event inputs x+32 Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. Bit 18 Reserved, must be kept at reset value. Bit 17 PRx: Configurable event inputs x+32 Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. Bits 16:0 Reserved, must be kept at reset value. 20.6.25 EXTI interrupt mask register (EXTI_CPUIMR3) Address offset: 0xA0 Reset value: 0x018B FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. MR88 MR87 MR86 MR85 MR84 Res. MR82 Res. MR80 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR79 MR78 MR77 MR76 MR75 MR74 MR73 MR72 MR71 MR70 MR69 MR68 MR67 MR66 MR65 MR64 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bits 24:23 MRx: CPU Interrupt Mask on Direct Event input x+64 (1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bits 22:20 MRx: CPU interrupt Mask on Configurable Event input x+64 (2) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bit 19 Reserved, must be kept at reset value (1). Bit 18 MRx: CPU interrupt Mask on Configurable Event input x+64 (2) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked Bit 17 Reserved, must be kept at reset value (1). Bits 16:0 MRx: CPU Interrupt Mask on Direct Event input x+64 (1) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is unmasked 1. The reset value for Direct Event inputs is set to ‘1’ in order to enable the interrupt by default. 2. The reset value for Configurable Event inputs is set to ‘0’ in order to disable the interrupt by default. 726/3178 DocID029587 Rev 3 RM0433 Extended interrupt and event controller (EXTI) 20.6.26 EXTI event mask register (EXTI_CPUEMR3) Address offset: 0xA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. MR88 MR87 MR86 MR85 MR84 Res. MR82 Res. MR80 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR79 MR78 MR77 MR76 MR75 MR74 MR73 MR72 MR71 MR70 MR69 MR68 MR67 MR66 MR65 MR64 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bits 24:0 MRx: CPU Event mask on Event input x+64 0: Event request from Line x is masked 1: Event request from Line x is unmasked 20.6.27 EXTI pending register (EXTI_CPUPR3) Address offset: 0xA8 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. PR86 PR85 PR84 Res. PR82 Res. Res. rc1 rc1 rc1 rc1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 PRx: Configurable event inputs x+64 Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. Bit 19 Reserved, must be kept at reset value. Bit 18 PRx: Configurable event inputs x+64 Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector. Bits 17:0 Reserved, must be kept at reset value. DocID029587 Rev 3 727/3178 730 0x40 EXTI_RTSR3 728/3178 TR[84] 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. MR[34] Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. PCS[19] PCS[0] PCS[1] PCS[2] 0 PCS[48] Res. Res. MR[35] 0 PCS[3] 0 0 Res. 0 Res. 0 0 0 Res. MR[15:0] 0 0 Res. Res. Res. Res. 0 PCS[49] Res. Res. Res. SWIER[21:0] 0 0 Res. 0 Res. TR[21:0] 0 0 PCS[34] Res. Res. Res. PCS[4] 0 PCS[20] 0 PCS[50] Res. Res. Res. 0 0 Res. 0 Res. 0 PCS[35] Res. Res. Res. 0 0 PCS[51] Res. Res. MR[41] 0 0 Res. PCS[5] 0 Res. PCS[21] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PCS[52] Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. PCS[6] 0 Res. 0 Res. 0 PCS[53] 0 Res. 0 Res. Res. 0 0 Res. Res. Res. Res. 0 0 Res. Res. Res. Res. PCS[7] Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. PCS[8] 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 0 Res. 0 0 Res. MR[53:48] Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. Res. 0 Res. 0 0 Res. Reset value 0 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 0 Res. Reset value 0 Res. Reset value 0 TR[49] PCS[9] PCS[10] 0 Res. Reset value 0 TR[49] Res. 0 0 SWIER[49] Reset value 0 Res. Res. PCS[11] 0 0 Res. EXTI_D3PCR1H 0 Res. 0 PCS[25] 0 Res. 0 TR[51] 0 Res. Res. Res. MR[21:19] Res. 0 Res. PCS[12] 0 TR[51] 0 Res. MR[25] Res. 0 Res. 0 Res. PCS[13] 0 SWIER[51] 0 Res. Res. Res. Res. 0 PCS[41] Res. 0 Res. PCS[14] 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 TR[82] 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. PCS[15] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. TR[85] Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value TR[86] Reset value Res. EXTI_D3PCR2H Res. EXTI_D3PCR2L Res. 0x34 EXTI_D3PMR2 Res. 0x30 EXTI_SWIER2 Res. 0x2C EXTI_FTSR2 Res. 0x24 Res. 0x28 EXTI_RTSR2 Res. 0x20 EXTI_D3PCR1L Res. 0x14 EXTI_D3PMR1 Res. 0x10 EXTI_SWIER1 Res. 0x0C EXTI_FTSR1 Res. 0x04 Res. 0x08 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI_RTSR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 20.6.28 Res. Extended interrupt and event controller (EXTI) RM0433 EXTI register map The following table gives the EXTI register map and the reset values. Table 135. Asynchronous interrupt/event controller register map and reset values TR[21:0] 0 0 0 0xA4 EXTI_CPUEMR3 Reset value 0 0 0 0 0 0 0 0 EXTI_CPUPR2 Res. Res. Res. 0 0 Reset value 1 1 0 0 0 MR[88:84] 0 1 0 0 0 0 1 1 0 DocID029587 Rev 3 0 1 1 0 0 MR[31:0] PR[21:0] MR[48:46] 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 MR[63:46] 1 0 1 0 0 1 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCS[88] Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. MR[21:0] Res. 0 Res. Reserved Res. 0 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR[80:64] 1 MR[80:64] 0 Res. 0 0 Res. 0 Res. 1 0 0 Res. 1 0 0 Res. MR[63:52] 0 Res. MR[31:22] Res. 1 0 0 0 Res. EXTI_CPUEMR1 0 Res. 0 0 0 Res. Reset value 0 0 Res. EXTI_CPUPR1 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 MR[49] 0 Res. Reset value Res. 0 PR[49] 0 Res. 1 MR[50] 0 Res. Res. Res. 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MR[88] Res. Res. Res. TR[84] SWIER[84] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWIER[82] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR[82] Res. TR[85] SWIER[85] Res. TR[86] Res. Res. Res. Res. Res. Res. Res. SWIER[86] Res. Res. Res. Res. Res. Res. Res. 0 MR[51] 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 1 0 Res. Reset value 1 1 0 MR[82] EXTI_CPUEMR2 1 0 MR[82] 0 PR[51] 0 Res. Res. Res. Reset value 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Reset value Res. 0 Res. 1 MR[84] 1 MR[85] 0 Res. 1 1 MR[86] 0 Res. 1 1 MR[87] 0 Res. 0 Res. Res. Res. Res. Res. Res. Reset value Res. Reset value MR[88] 0 Res. EXTI_CPUIMR2 1 Res. 0 Res. 1 1 Res. 1 1 Res. EXTI_CPUIMR3 1 1 Res. 0 Res. Reset value 1 Res. Reset value Res. Reset value Res. 0xA0 0 Res. 0x98 Reset value Res. 0x94 EXTI_CPUIMR1 Res. 0x90 EXTI_D3PCR3H Res. 0x88 EXTI_D3PCR3L Res. 0x84 EXTI_D3PMR3 Res. 0x80 Res. 0x580x7C Res. 0x54 Res. 0x50 Res. 0x4C EXTI_SWIER3 Res. 0x48 EXTI_FTSR3 Res. 0x44 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. RM0433 Extended interrupt and event controller (EXTI) Table 135. Asynchronous interrupt/event controller register map and reset values 0 0 0 0 0 0 0 0 0 0 0 0 MR[44:32] MR[44:32] 1 1 1 1 1 1 1 0 0 0 0 0 0 0 729/3178 730 0xAC0xBC 730/3178 Reserved 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[82] Res. 0 Res. Res. Res. PR[84] 0 Res. PR[85] 0 Res. Res. Res. Res. Res. Res. Res. Res. PR[86] Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI_CPUPR3 Res. 0xA8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. Extended interrupt and event controller (EXTI) RM0433 Table 135. Asynchronous interrupt/event controller register map and reset values Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 RM0433 Cyclic redundancy check calculation unit (CRC) 21 Cyclic redundancy check calculation unit (CRC) 21.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 21.2 CRC main features • Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1 • Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32 bits) • Handles 8-,16-, 32-bit data size • Programmable CRC initial value • Single input/output 32-bit data register • Input buffer to avoid bus stall during calculation • CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size • General-purpose 8-bit register (can be used for temporary storage) • Reversibility option on I/O data DocID029587 Rev 3 731/3178 736 Cyclic redundancy check calculation unit (CRC) RM0433 21.3 CRC functional description 21.3.1 CRC block diagram Figure 85. CRC calculation unit block diagram ELW$+%EXV ELW UHDGDFFHVV 'DWDUHJLVWHU RXWSXW FUFBKFON &5&FRPSXWDWLRQ ELW ZULWHDFFHVV 'DWDUHJLVWHU LQSXW D^ϭϵϴϴϮsϮ 21.3.2 CRC internal signals Table 136. CRC internal input/output signals 21.3.3 Signal name Signal type crc_hclk Digital input Description AHB clock CRC operation The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access). Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written. The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width: • 4 AHB clock cycles for 32-bit • 2 AHB clock cycles for 16-bit • 1 AHB clock cycles for 8-bit An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation. The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write. 732/3178 DocID029587 Rev 3 RM0433 Cyclic redundancy check calculation unit (CRC) The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: 0x58D43CB2 with bit-reversal done by byte 0xD458B23C with bit-reversal done by half-word 0xB23CD458 with bit-reversal done on the full word The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register. The operation is done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488. The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access. The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register. Polynomial programmability The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported. If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register. To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial. The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7. DocID029587 Rev 3 733/3178 736 Cyclic redundancy check calculation unit (CRC) 21.4 CRC registers 21.4.1 Data register (CRC_DR) RM0433 Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DR[31:16] rw 15 14 13 12 11 10 9 8 7 DR[15:0] rw Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 21.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IDR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 734/3178 DocID029587 Rev 3 RM0433 Cyclic redundancy check calculation unit (CRC) 21.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. REV_ OUT Res. Res. RESET Res. Res. Res. Res. Res. Res. Res. rw REV_IN[1:0] rw rw POLYSIZE[1:0] rw rw rs Bits 31:8 Reserved, must be kept cleared. Bit 7 REV_OUT: Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format Bits 6:5 REV_IN[1:0]: Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word Bits 4:3 POLYSIZE[1:0]: Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial Bits 2:1 Reserved, must be kept cleared. Bit 0 RESET: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 21.4.4 Initial CRC value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CRC_INIT[31:16] rw 15 14 13 12 11 10 9 8 7 CRC_INIT[15:0] rw DocID029587 Rev 3 735/3178 736 Cyclic redundancy check calculation unit (CRC) RM0433 Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 21.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C11DB7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 POL[31:16] rw 15 14 13 12 11 10 9 8 7 POL[15:0] rw Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 21.4.6 CRC register map Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 137. CRC register map and reset values CRC_DR DR[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_IDR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Res. 1 RESET 1 Res. Reset value REV_OUT 0x00 IDR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x08 Reset value 0x10 CRC_INIT Reset value 0x14 0 0 0 0 0 1 1 1 1 1 0 CRC_INIT[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_POL Polynomial coefficients Reset value 0x04C11DB7 1 1 1 1 1 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 736/3178 Res. 0 POLYSIZE[1:0] 0 REV_IN[1:0] Reset value Res. 0x04 DocID029587 Rev 3 1 1 1 RM0433 22 Flexible memory controller (FMC) Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: 22.1 • The NOR/PSRAM memory controller • The NAND memory controller • The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static memories, SDRAM memories, and NAND flash memory. Its main purposes are: • to translate AXI transactions into the appropriate external device protocol • to meet the access time requirements of the external memory devices All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device. The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories • Burst mode support for faster access to synchronous devices such as NOR Flash memory, PSRAM and SDRAM) • Programmable continuous clock output for asynchronous and synchronous accesses • 8-,16- or 32-bit wide data bus • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM devices • External asynchronous wait control • Write FIFO with 16 x32-bit depth The Write FIFO is common to all memory controllers and consists of: • – a Write Data FIFO which stores the data to be written to the memory – a Write Address FIFO which stores the address (up to 28 bits) plus the data size (up to 2 bits). When operating in burst mode, only the start address is stored except when crossing a page boundary (for PSRAM and SDRAM). In this case, the burst is broken into two FIFO entries. Cacheable Read FIFO with 6 x64-bit depth (6 x14-bit address tag) for SDRAM controller. At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes. DocID029587 Rev 3 737/3178 818 Flexible memory controller (FMC) RM0433 The FMC registers that define the external device type and associated characteristics are set at boot time and do not change until the next reset or power-up. However, only few bits can be changed on-the-fly. • ECCEN and PBEN bits in FMC_PCR register • IFS, IRS and ILS bits in FMC_SR register • MODE[2:0], CTB1/CTB2, NRFS and MRD bits in FMC_SDCMR register • REIE and CRE bits in the FMC_SDRTR register. Follow the below sequence to modify some parameters while FMC is enabled: 1. First disable the FMC controller to prevent any further accesses to any memory controller during register modification. 2. Update all required configurations. 3. Enable the FMC controller again. When the SDRAM controller is used, if the SDCLK Clock ratio or refresh rate has to be modified after initialization phase, the following procedure must be followed. 22.2 1. Put the SDRAM device in Self-refresh mode. 2. Disable the FMC controller by resetting the FMCEN bit in the FMC_BCR1 register. 3. Update the required parameters. 4. Enable the FMC controller once all parameters are updated. 5. Then, send the Clock Configuration Enable command to exit Self-fresh mode. FMC block diagram The FMC consists of the following main blocks: • The NOR Flash/PSRAM/SRAM controller • The NAND controller • The SDRAM controller • The AXI interface • The AHB interface (including the FMC configuration registers) The block diagram is shown in the figure below. 738/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Figure 86. FMC block diagram IPFBLWWR19,& 125365$0 PHPRU\ FRQWUROOHU IPFBKFON ELW$;,EXV ELW$+%EXV IPFBNHUBFN $;,$+% LQWHUIDFH &RQILJXUDWLRQ UHJLVWHUV 1$1')ODVK PHPRU\ FRQWUROOHU 6'5$0 FRQWUROOHU )0&B1/ RU1$'9 )0&B&/. 125365$0 VLJQDOV )0&B1%/> @ 12565$0VKDUHG VLJQDOV )0&B$> @ )0&B'> @ 6KDUHGVLJQDOV )0&B1(> @ )0&B12( )0&B1:( )0&B1:$,7 125365$065$0 VKDUHGVLJQDOV )0&B1&( )0&B,17 1$1'VLJQDOV )0&B6'&/. )0&B6'1:( )0&B6'&.(> @ )0&B6'1(> @ )0&B15$6 )0&B1&$6 6'5$0VLJQDOV 06Y9 DocID029587 Rev 3 739/3178 818 Flexible memory controller (FMC) 22.3 RM0433 FMC internal signals Table 138 gives the list of FMC internal signals. FMC pins (or external signals) are described in Section 22.7.1: External memory interface signals. Table 138. FMC pins 22.4 Names Signal type Description fmc_it Digital output fmc_ker_ck Digital input FMC kernel clock fmc_hclk Digital input FMC interface clock FMC interrupt AHB interface The AHB slave interface allows internal CPUs to configure the FMC registers. The AHB clock (fmc_hclk) is the reference clock for the FMC register accesses. 22.5 AXI interface The AXI slave interface allows internal CPUs and other bus master peripherals to access the external memories. AXI transactions are translated into the external device protocol. As the AXI data bus is 64bit wide, the AXI transactions might be split into several consecutive 32-, 16- or 8-bit accesses according to data size accesses. The FMC Chip Select (FMC_NEx) does not toggle between consecutive accesses except in case of accesses in Mode D when the extended mode is enabled. The FMC generates an AXI slave error when one of the following conditions is met: • Reading or writing to an FMC bank (Bank 1 to 4) which is not enabled. • Reading or writing to the NOR Flash bank while the FACCEN bit is reset in the FMC_BCRx register. • Writing to a write protected SDRAM bank (WP bit set in the SDRAM_SDCRx register). • Violation of the SDRAM address range (access to reserved address range) • Attempting to read/write access from/to SDRAM bank when it is not yet initialized The FMC generates an AXI decoder error when ADDR[31:28] address bits are not supported by the FMC bank base address following the BMAP[1:0] bits configuration. The kernel clock for the FMC controller is the asynchronous fmc_ker_ck clock (refer to Section 8: Reset and Clock Control (RCC) for fmc_ker_ck clock source selection). 22.5.1 Supported memories and transactions General transaction rules The requested AXI transaction data size can be 8-, 16-, 32- or 64-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers. 740/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Therefore, some simple transaction rules can be followed, depending on AXI transaction size versus memory data size: • AXI transaction size and memory data size are equal to prevent issues from occurring. • AXI transaction size is greater than the memory size: In this case, the FMC splits the AXI transaction into smaller consecutive memory accesses to meet the external data width. • AXI transaction size is smaller than the memory size: The transfer may or not be consistent depending on the type of external device: – Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM, SDRAM) In this case, the FMC allows read/write transactions and accesses the right data through its NBL[3:0] byte lanes. Bytes to be written are addressed by NBL[3:0]. All memory bytes are read (NBL[3:0] are driven low during read transaction) and the useless ones are discarded. – Accesses to devices that do not have the byte select feature (NOR and NAND Flash memories) This situation occurs when a byte access is requested to a 16-bit wide Flash memory. Since the device cannot be accessed in byte mode (only 16-bit words can be read/written from/to the Flash memory), write transactions are not allowed while read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM and SDRAM The synchronous memories must be configured in linear burst mode of undefined length as not all masters can issue wrap transactions. If a master generates a wrap transaction: • The read is split into two linear burst transactions. • The write is split into two linear burst transactions if the write FIFO is enabled and into several linear burst transactions if the write FIFO is disabled. Configuration registers The FMC can be configured through a set of registers. Refer to Section 22.7.6, for a detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 22.8.7, for a detailed description of the NAND Flash registers and to Section 22.9.5 for a detailed description of the SDRAM controller registers. DocID029587 Rev 3 741/3178 818 Flexible memory controller (FMC) 22.6 RM0433 External device address mapping From the FMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each (see Figure 87): • Bank 1 is used to address up to 4 NOR Flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows: – Bank 1 - NOR/PSRAM 1 – Bank 1 - NOR/PSRAM 2 – Bank 1 - NOR/PSRAM 3 – Bank 1 - NOR/PSRAM 4 • Bank 2 is used for SDRAM device, SDRAM bank 1 or SDRAM bank 2 depending on BMAP bits configuration. • Bank 3 is used to address NAND Flash memory devices.The MPU memory attribute for this space must be reconfigured by software to Device. • Bank 4 and 5 are used to address SDRAM devices (1 device per bank). For each bank the type of memory to be used can be configured by the user application through the Configuration register. Figure 87. FMC memory banks $GGUHVV %DQN 6XSSRUWHG PHPRU\W\SH [ %DQN [0% 125365$0 65$0 [))))))) [ 6'5$0%DQN [0% [))))))) [ %DQN [0% 1$1')ODVK PHPRU\ [))))))) [ %DQN 5HVHUYHG [ ))))))) [& 6'5$0%DQN [0% 6'5$0 [&))))))) [' 6'5$0%DQN [0% ['))))))) 06Y9 742/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) The FMC bank mapping can be modified through the BMAP[1:0] bits in the FMC_BCR1 register. Table 139 shows the configuration to swap the NOR/PSRAM bank with SDRAM banks or remap the SDRAM bank2, thus allowing to access the SDRAM banks at two different address mapping. Table 139. FMC bank mapping options BMAP[1:0]=00 (Default mapping) BMAP[1:0]=01 NOR/PSRAM and SDRAM banks swapped BMAP[1:0]=10 SDRAM bank 2 remapped 0x6000 0000 - 0x6FFF FFFF NOR/PSRAM bank SDRAM bank1 NOR/PSRAM bank 0x7000 0000 - 0x7FFF FFFF SDRAM bank1 SDRAM bank2 SDRAM bank2 0x8000 0000 - 0x8FFF FFFF NAND bank NAND bank NAND bank 0x9000 0000 - 0x9FFF FFFF Reserved Reserved Reserved 0xC000 0000 - 0xCFFF FFFF SDRAM bank1 NOR/PSRAM bank SDRAM bank1 0xD000 0000 - 0xDFFF FFFF SDRAM bank2 SDRAM bank2 SDRAM bank2 Start -End address 22.6.1 NOR/PSRAM address mapping ADDR[27:26] bits are used to select one of the four memory banks as shown in Table 140. Table 140. NOR/PSRAM bank selection ADDR[27:26](1) Selected bank 00 Bank 1 - NOR/PSRAM 1 01 Bank 1 - NOR/PSRAM 2 10 Bank 1 - NOR/PSRAM 3 11 Bank 1 - NOR/PSRAM 4 1. ADDR are internal address lines that are translated to external memory. The ADDR[25:0] bits contain the external memory address. Since ADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 141. NOR/PSRAM External memory address Memory width(1) Data address issued to the memory Maximum memory capacity (bits) 8-bit ADDR[25:0] 64 Mbytes x 8 = 512 Mbit 16-bit ADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit 32-bit ADDR[25:2] >> 2 64 Mbytes/4 x 32 = 512 Mbit 1. In case of a 16-bit external memory width, the FMC will internally use ADDR[25:1] to generate the address for external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC will internally use ADDR[25:2] to generate the external address. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. DocID029587 Rev 3 743/3178 818 Flexible memory controller (FMC) 22.6.2 RM0433 NAND Flash memory address mapping The NAND bank is divided into memory areas as indicated in Table 142. Table 142. NAND memory mapping and timing registers Start address End address 0x8800 0000 0x8BFF FFFF 0x8000 0000 0x83FF FFFF FMC bank Bank 3 - NAND Flash Memory space Timing register Attribute FMC_PATT (0x8C) Common FMC_PMEM (0x88) For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 143 below) located in the lower 256 Kbytes: • Data section (first 64 Kbytes in the common/attribute memory space) • Command section (second 64 Kbytes in the common / attribute memory space) • Address section (next 128 Kbytes in the common / attribute memory space) Table 143. NAND bank selection Section name ADDR[17:16] Address range Address section 1X 0x020000-0x03FFFF Command section 01 0x010000-0x01FFFF Data section 00 0x000000-0x0FFFF The application software uses the 3 sections to access the NAND Flash memory: • To send a command to NAND Flash memory, the software must write the command value to any memory location in the command section. • To specify the NAND Flash address that must be read or written, the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive write operations to the address section are required to specify the full address. • To read or write data, the software reads or writes the data from/to any memory location in the data section. Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations. 22.6.3 SDRAM address mapping Two SDRAM banks are available as indicated in Table 144. Table 144. SDRAM bank selection Selected bank Control register Timing register SDRAM Bank1 FMC_SDCR1 FMC_SDTR1 SDRAM Bank2 FMC_SDCR2 FMC_SDTR2 Table 145 shows SDRAM mapping for a 13-bit row and an 11-bit column configuration. 744/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 145. SDRAM address mapping Memory width(1) Internal bank Row address Column address(2) Maximum memory capacity (Mbytes) 8-bit ADDR[25:24] ADDR[23:11] ADDR[10:0] 64 Mbytes: 4 x 8K x 2K 16-bit ADDR[26:25] ADDR[24:12] ADDR[11:1] 128 Mbytes: 4 x 8K x 2K x 2 32-bit ADDR[27:26] ADDR[25:13] ADDR[12:2] 256 Mbytes: 4 x 8K x 2K x 4 1. When interfacing with a 16-bit memory, the FMC internally uses the ADDR[11:1] internal address lines to generate the external address. When interfacing with a 32-bit memory, the FMC internally uses ADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to be connected to the external memory address A[0]. 2. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address A[10] but it will be always driven low. The ADDR[27:0] bits are translated into an external SDRAM address depending on the SDRAM controller configuration: • Data size:8, 16 or 32 bits • Row size:11, 12 or 13 bits • Column size: 8, 9, 10 or 11 bits • Number of internal banks: two or four internal banks The following tables show the SDRAM address mapping versus the SDRAM controller configuration. ) Row size configuration Table 146. SDRAM address mapping with 8-bit data bus width(1)(2) ADDR(Internal Address Lines) 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank [1:0] Res. 11-bit row size configuration Bank [1:0] Res. Bank [1:0] Res. Bank [1:0] Res. Res. Res. Row[10:0] Bank [1:0] Res. 12-bit row size configuration Row[10:0] Row[10:0] Bank [1:0] Res. Row[10:0] Bank [1:0] Bank [1:0] Row[11:0] Row[11:0] Row[11:0] Row[11:0] DocID029587 Rev 3 Column[7:0] Column[8:0] Column[9:0] Column[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] 745/3178 818 Flexible memory controller (FMC) RM0433 Table 146. SDRAM address mapping with 8-bit data bus width(1)(2) (continued) ADDR(Internal Address Lines) Row size configuration 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank [1:0] Res. Bank [1:0] Res. 13-bit row size configuration Column[7:0] Row[12:0] Bank [1:0] Res. Res. Row[12:0] Column[8:0] Row[12:0] Bank [1:0] Column[9:0] Row[12:0] Column[10:0] 1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’. 2. Access to Reserved (Res.) address range generates an AXI slave error. ) Table 147. SDRAM address mapping with 16-bit data bus width(1)(2) Bank Row[10:0] [1:0] Bank Res. Row[10:0] 11-bit row size [1:0] Bank configuration Res. Row[10:0] [1:0] Bank Res. Row[10:0] [1:0] Bank Res. Row[11:0] [1:0] Bank Res. Row[11:0] 12-bit row size [1:0] Bank configuration Res. Row[11:0] [1:0] Bank Res. Row[11:0] [1:0] Bank Res. Row[12:0] [1:0] Bank Res. Row[12:0] 13-bit row size [1:0] Bank configuration Res. Row[12:0] [1:0] Re Bank Row[12:0] s. [1:0] Res. Column[7:0] Column[8:0] Column[9:0] Column[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] 1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’. 2. Access to Reserved space (Res.) generates an AXI Slave error. 3. BM0: is the byte mask for 16-bit access. 746/3178 DocID029587 Rev 3 0 11 10 9 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Row size Configuration 27 ADDR(address Lines) BM0(3) BM0 BM0 BM0 BM0 BM0 BM0 BM0 BM0 BM0 BM0 BM0 RM0433 Flexible memory controller (FMC) Table 148. SDRAM address mapping with 32-bit data bus width(1)(2) Bank Row[10:0] [1:0] Bank Res. Row[10:0] [1:0] Bank Res. Row[10:0] [1:0] Bank Res. Row[10:0] [1:0] Bank Res. Row[11:0] [1:0] Bank Res. Row[11:0] [1:0] Bank Res. Row[11:0] [1:0] Bank Res. Row[11:0] [1:0] Bank Res. Row[12:0] [1:0] Bank Res. Row[12:0] [1:0] Bank Res. Row[12:0] [1:0] Bank Row[12:0] [1:0] Res. 11-bit row size configuration 12-bit row size configuration 13-bit row size configuration Column[7:0] Column[8:0] Column[9:0] Column[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] 0 1 11 10 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Row size configuration 27 ADDR(address Lines) BM[1:0 ](3) BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 BM[1:0 1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’. 2. Access to Reserved space (Res.) generates an AXI slave error. 3. BM[1:0]: is the byte mask for 32-bit access. 22.7 NOR Flash/PSRAM controller The FMC generates the appropriate signal timings to drive the following types of memories: • • • Asynchronous SRAM and ROM – 8 bits – 16 bits – 32 bits PSRAM (Cellular RAM) – Asynchronous mode – Burst mode for synchronous accesses with configurable option to split burst access when crossing boundary page for CRAM 1.5. – Multiplexed or non-multiplexed NOR Flash memory – Asynchronous mode – Burst mode for synchronous accesses – Multiplexed or non-multiplexed DocID029587 Rev 3 747/3178 818 Flexible memory controller (FMC) RM0433 The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared. The FMC supports a wide range of devices through a programmable timings among which: • Programmable wait states (up to 15) • Programmable bus turnaround cycles (up to 15) • Programmable output enable and write enable delays (up to 15) • Independent read and write timings and protocol to support the widest variety of memories and timings • Programmable continuous clock (FMC_CLK) output. The FMC output Clock (FMC_CLK) is a sub-multiple of the fmc_ker_ck clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register: • If the CCLKEN bit is reset, the FMC generates the clock (FMC_CLK) only during synchronous accesses (Read/write transactions). • If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must be configured in synchronous mode (see Section 22.7.6: NOR/PSRAM controller registers). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the AXI data size has to be the same as the memory data width (MWID) otherwise the FMC_CLK frequency will be changed depending on AXI data transaction (refer to Section 22.7.5: Synchronous transactions for FMC_CLK divider ratio formula). The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 22.7.6: NOR/PSRAM controller registers). The programmable memory parameters include access times (see Table 149) and support for wait management (for PSRAM and NOR Flash memory accessed in burst mode). Table 149. Programmable NOR/PSRAM access parameters 748/3178 Parameter Function Access mode Unit Min. Max. Address setup Duration of the address setup phase Asynchronous FMC clock cycle (fmc_ker_ck) 0 15 Address hold Duration of the address hold phase Asynchronous, muxed I/Os FMC clock cycle (fmc_ker_ck) 1 15 Data setup Duration of the data setup phase Asynchronous FMC clock cycle (fmc_ker_ck) 1 256 Bust turn Duration of the bus turnaround phase Asynchronous and FMC clock cycle synchronous read (fmc_ker_ck) 0 15 Clock divide ratio Number of FMC clock cycles (fmc_ker_ck) to build one memory clock cycle (CLK) Synchronous FMC clock cycle (fmc_ker_ck) 2 16 Data latency Number of clock cycles to issue to the memory before the first data of the burst Synchronous Memory clock cycle (fmc_ker_ck) 2 17 DocID029587 Rev 3 RM0433 22.7.1 Flexible memory controller (FMC) External memory interface signals Table 150, Table 151 and Table 152 list the signals that are typically used to interface with NOR Flash memory, SRAM and PSRAM. Note: The prefix “N” identifies the signals which are active low. NOR Flash memory, non-multiplexed I/Os Table 150. Non-multiplexed I/O NOR Flash memory FMC signal name I/O Function CLK O Clock (for synchronous access) A[25:0] O Address bus D[31:0] I/O Bidirectional data bus NE[x] O Chip Select, x = 1..4 NOE O Output enable NWE O Write enable NL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT I NOR Flash wait input signal to the FMC The maximum capacity is 512 Mbits (26 address lines). NOR Flash memory, 16-bit multiplexed I/Os Table 151. 16-bit multiplexed I/O NOR Flash memory FMC signal name I/O Function CLK O Clock (for synchronous access) A[25:16] O Address bus AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] O Chip Select, x = 1..4 NOE O Output enable NWE O Write enable NL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT I NOR Flash wait input signal to the FMC The maximum capacity is 512 Mbits. DocID029587 Rev 3 749/3178 818 Flexible memory controller (FMC) RM0433 PSRAM/SRAM, non-multiplexed I/Os Table 152. Non-multiplexed I/Os PSRAM/SRAM FMC signal name I/O Function CLK O Clock (only for PSRAM synchronous access) A[25:0] O Address bus D[31:0] I/O Data bidirectional bus NE[x] O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) NOE O Output enable NWE O Write enable NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV) NWAIT I PSRAM wait input signal to the FMC NBL[3:0] O Byte lane output. Byte 0 to Byte 3 control (Upper and lower byte enable) The maximum capacity is 512 Mbits. PSRAM, 16-bit multiplexed I/Os Table 153. 16-Bit multiplexed I/O PSRAM FMC signal name I/O Function CLK O Clock (for synchronous access) A[25:16] O Address bus AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) NOE O Output enable NWE O Write enable NL(= NADV) O Address valid PSRAM input (memory signal name: NADV) NWAIT I PSRAM wait input signal to the FMC NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable) The maximum capacity is 512 Mbits (26 address lines). 750/3178 DocID029587 Rev 3 RM0433 22.7.2 Flexible memory controller (FMC) Supported memories and transactions Table 154 below shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example. Table 154. NOR Flash/PSRAM: Example of supported memories and transactions(1) Device NOR Flash (muxed I/Os and nonmultiplexed I/Os) PSRAM (multiplexed I/Os and nonmultiplexed I/Os) AXI data Memory size data size Allowed/ not allowed Mode R/W Asynchronous R 8 16 Y Asynchronous W 8 16 N Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Asynchronous R 64 16 Y Split into 4 FMC accesses Asynchronous W 64 16 Y Split into 4 FMC accesses Asynchronous page R - 16 N Mode is not supported Synchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32/64 16 Y Asynchronous R 8 16 Y Asynchronous W 8 16 Y Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Asynchronous R 64 16 Y Split into 4 FMC accesses Asynchronous W 64 16 Y Split into 4 FMC accesses Asynchronous page R - 16 N Mode is not supported Synchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32/64 16 Y Synchronous W 8 16 Y Synchronous W 16/32/64 16 Y DocID029587 Rev 3 Comments Use of byte lanes NBL[1:0] Use of byte lanes NBL[1:0] 751/3178 818 Flexible memory controller (FMC) RM0433 Table 154. NOR Flash/PSRAM: Example of supported memories and transactions(1) Device SRAM and ROM AXI data Memory size data size Allowed/ not allowed Mode R/W Asynchronous R 8/16 16 Y Asynchronous W 8/16 16 Y Use of byte lanes NBL[1:0] Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Use of byte lanes NBL[1:0] Asynchronous R 64 16 Y Split into 4 FMC accesses Asynchronous W 64 16 Y Split into 4 FMC accesses Use of byte lanes NBL[1:0] Comments 1. NBL[1:0] are also driven by AXI write strobes. 22.7.3 General timing rules Signal synchronization is performed as follows: 22.7.4 • All controller output signals change on the rising edge of the fmc_ker_ck clock. • In synchronous read and write modes, all output signals change on the rising edge of fmc_ker_ck clock. Whatever the CLKDIV value, all outputs change as follows: – NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FMC_CLK clock. – NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FMC_CLK clock. NOR Flash/PSRAM controller asynchronous transactions Asynchronous transactions on static memories (NOR Flash memory, PSRAM, SRAM) are performed as follows: 752/3178 • Signals are synchronized by the internal clock. This clock is not issued to the memory. • The FMC always samples the data before de-asserting the Chip Select signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) • If the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B. • If the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the FMC can operate in Mode1 or Mode2 as follows: – Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01 in the FMC_BCRx register) – Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FMC_BCRx register). DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers. Figure 88. Mode 1 read access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1%/>[ @ 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ 'DWDEXV $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y 9 DocID029587 Rev 3 753/3178 818 Flexible memory controller (FMC) RM0433 Figure 89. Mode 1 write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1%/>[ @ 1([ 12( IPFBNHUBFN 1:( 'DWDEXV GDWDGULYHQE\)60& $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 The fmc_ker_ck cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this fmc_ker_ck cycle, the DATAST value must be greater than zero (DATAST > 0). Table 155. FMC_BCRx bit fields 754/3178 Bit number Bit name 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x0 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 Value to set 0x0 0x000 As needed 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 155. FMC_BCRx bit fields (continued) Bit number Bit name 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don’t care 5-4 MWID As needed 3-2 MTYP As needed, exclude 0x2 (NOR Flash memory) 1 MUXE 0x0 0 MBKEN 0x1 Value to set Table 156. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD Don’t care 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST+1 fmc_ker_ck cycles for write accesses, DATAST fmc_ker_ck cycles for read accesses). 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles). Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) DocID029587 Rev 3 755/3178 818 Flexible memory controller (FMC) RM0433 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 90. Mode A read access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1%/>[ @ 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ 'DWDEXV $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 1. NBL[3:0] are driven low during the read access 756/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Figure 91. Mode A write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1%/>[ @ 1([ 12( IPFBNHUBFN 1:( 'DWDEXV GDWDGULYHQE\)60& $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 157. FMC_BCRx bit fields Bit number Bit name 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 Value to set 0x0 0x000 As needed 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. DocID029587 Rev 3 757/3178 818 Flexible memory controller (FMC) RM0433 Table 157. FMC_BCRx bit fields (continued) Bit number Bit name 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don’t care 5-4 MWID As needed 3-2 MTYP As needed, exclude 0x2 (NOR Flash memory) 1 MUXEN 0x0 0 MBKEN 0x1 Value to set Table 158. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x0 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST fmc_ker_ck cycles) for read accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles) for read accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) Table 159. FMC_BWTRx bit fields 758/3178 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x0 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST fmc_ker_ck cycles) for write accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles) for write accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Mode 2/B - NOR Flash Figure 92. Mode 2 and mode B read access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ 'DWDEXV $''6(7 '$7$67 IPFBNHUBFNF\FOHV IPFBNHUBFNF\FOHV 06Y9 Figure 93. Mode 2 write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( IPFBNHUBFN 1:( 'DWDEXV GDWDGULYHQE\)60& $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 DocID029587 Rev 3 759/3178 818 Flexible memory controller (FMC) RM0433 Figure 94. Mode B write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( IPFBNHUBFN 1:( 'DWDEXV GDWDGULYHQE\)60& $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). Table 160. FMC_BCRx bit fields 760/3178 Bit number Bit name 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 for mode B, 0x0 for mode 2 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 Value to set 0x0 0x000 As needed 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 160. FMC_BCRx bit fields (continued) Bit number Bit name 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID As needed 3-2 MTYP 0x2 (NOR Flash memory) 1 MUXEN 0x0 0 MBKEN 0x1 Value to set Table 161. FMC_BTRx bit fields Bit number Bit name Value to set 31-30 Reserved 0x0 29-28 ACCMOD 0x1 if extended mode is set 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the access second phase (DATAST fmc_ker_ck cycles) for read accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the access first phase (ADDSET fmc_ker_ck cycles) for read accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) Table 162. FMC_BWTRx bit fields Bit number Bit name Value to set 31-30 Reserved 0x0 29-28 ACCMOD 0x1 if extended mode is set 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the access second phase (DATAST fmc_ker_ck cycles) for write accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the access first phase (ADDSET fmc_ker_ck cycles) for write accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) DocID029587 Rev 3 761/3178 818 Flexible memory controller (FMC) Note: RM0433 The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its content is don’t care. Mode C - NOR Flash - OE toggling Figure 95. Mode C read access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ 'DWDEXV $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 Figure 96. Mode C write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( IPFBNHUBFN 1:( 'DWDEXV GDWDGULYHQE\)60& $''6(7 IPFBNHUBFNF\FOHV '$7$67 IPFBNHUBFNF\FOHV 06Y9 762/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 163. FMC_BCRx bit fields Bit No. Bit name Value to set 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID As needed 3-2 MTYP 0x02 (NOR Flash memory) 1 MUXEN 0x0 0 MBKEN 0x1 0x0 0x000 As needed 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. DocID029587 Rev 3 763/3178 818 Flexible memory controller (FMC) RM0433 Table 164. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x2 27-24 DATLAT 0x0 23-20 CLKDIV 0x0 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST fmc_ker_ck cycles) for read accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles) for read accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) Table 165. FMC_BWTRx bit fields 764/3178 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x2 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST fmc_ker_ck cycles) for write accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles) for write accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Mode D - asynchronous access with extended address Figure 97. Mode D read access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ 'DWDEXV $''6(7 $''+/' IPFBNHUBFN IPFBNHUBFN '$7$67 IPFBNHUBFN 06Y9 Figure 98. Mode D write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ 'DWDEXV $''6(7 IPFBNHUBFN $''+/' IPFBNHUBFN '$7$67 IPFBNHUBFN 06Y 9 DocID029587 Rev 3 765/3178 818 Flexible memory controller (FMC) RM0433 The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 166. FMC_BCRx bit fields Bit No. Bit name Value to set 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Set according to memory support 5-4 MWID As needed 3-2 MTYP As needed 1 MUXEN 0x0 0 MBKEN 0x1 0x0 0x000 As needed 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. Table 167. FMC_BTRx bit fields 766/3178 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x3 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Time between NEx high to NEx low (BUSTURN fmc_ker_ck) Duration of the second access phase (DATAST fmc_ker_ck cycles) for read accesses. DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 167. FMC_BTRx bit fields (continued) Bit number Bit name Value to set 7-4 ADDHLD Duration of the middle phase of the read access (ADDHLD fmc_ker_ck cycles) 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles) for read accesses. Minimum value for ADDSET is 1. Table 168. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x3 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST + 1 fmc_ker_ck cycles) for write accesses. 7-4 ADDHLD Duration of the middle phase of the write access (ADDHLD fmc_ker_ck cycles) 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles) for write accesses. Minimum value for ADDSET is 1. Time between NEx high to NEx low (BUSTURN fmc_ker_ck) DocID029587 Rev 3 767/3178 818 Flexible memory controller (FMC) RM0433 Muxed mode - multiplexed asynchronous access to NOR Flash memory Figure 99. Muxed read access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( 1:( $'> @ +LJK GDWDGULYHQ E\PHPRU\ /RZHUDGGUHVV $''6(7 '$7$67 IPFBNHUBFNF\FOHV IPFBNHUBFNF\FOHV $''+/' IPFBNHUBFNF\FOHV 06Y9 Figure 100. Muxed write access waveforms 0HPRU\WUDQVDFWLRQ $> @ 1$'9 1([ 12( IPFBNHUBFN 1:( $'> @ /RZHUDGGUHVV GDWDGULYHQE\)60& $''6(7 '$7$67 IPFBNHUBFNF\FOHV IPFBNHUBFNF\FOHV $''+/' IPFBNHUBFNF\FOHV 06Y9 The difference with Mode D is the drive of the lower address byte(s) on the data bus. 768/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 169. FMC_BCRx bit fields Bit No. Bit name Value to set 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x0 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID As needed 3-2 MTYP 0x2 (NOR Flash memory) 1 MUXEN 0x1 0 MBKEN 0x1 0x0 0x000 As needed 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. Table 170. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x0 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Time between NEx high to NEx low (BUSTURN fmc_ker_ck) Duration of the second access phase (DATAST fmc_ker_ck cycles for read accesses and DATAST+1 fmc_ker_ck cycles for write accesses). DocID029587 Rev 3 769/3178 818 Flexible memory controller (FMC) RM0433 Table 170. FMC_BTRx bit fields (continued) Bit number Bit name Value to set 7-4 ADDHLD Duration of the middle phase of the access (ADDHLD fmc_ker_ck cycles). 3-0 ADDSET Duration of the first access phase (ADDSET fmc_ker_ck cycles). Minimum value for ADDSET is 1. WAIT management in asynchronous accesses If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register. If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged. The data setup phase must be programmed so that WAIT can be detected 4 fmc_ker_ck cycles before the end of the memory transaction. The following cases must be considered: 1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ ( 4 × FMC_CLK ) + max_wait_assertion_time 2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): if max_wait_assertion_time > address_phase + hold_phase then: DATAST ≥ ( 4 × FMC_CLK ) + ( max_wait_assertion_time – address_phase – hold_phase otherwise DATAST ≥ ( 4 × FMC_CLK ) where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low. Figure 101 and Figure 102 show the number of fmc_ker_ck clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases). 770/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Figure 101. Asynchronous wait during a read access waveforms 0HPRU\WUDQVDFWLRQ $> @ DGGUHVVSKDVH GDWDVHWXSSKDVH 1([ 1:$,7 GRQ¶WFDUH GRQ¶WFDUH 12( GDWDGULYHQE\PHPRU\ 'DWDEXV IPFBNHUBFN 06Y9 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. Figure 102. Asynchronous wait during a write access waveforms 0HPRU\WUDQVDFWLRQ $> @ DGGUHVVSKDVH GDWDVHWXSSKDVH 1([ 1:$,7 GRQ¶WFDUH GRQ¶WFDUH IPFBNHUBFN 1:( 'DWDEXV GDWDGULYHQE\)60& IPFBNHUBFN 06Y9 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. DocID029587 Rev 3 771/3178 818 Flexible memory controller (FMC) 22.7.5 RM0433 Synchronous transactions The memory clock, FMC_CLK, is a sub-multiple of fmc_ker_ck. It depends on the value of CLKDIV and the MWID/ AXI data size, following the formula given below: FMC_CLK divider ratio = max (CLKDIV + 1,MWID ( AXI data size )) If MWID is 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed CLKDIV value. If MWID is 32-bit, the FMC_CLK divider ratio depends also on AXI data size. Example: • If CLKDIV=1, MWID = 32 bits, AXI data size=8 bits, FMC_CLK=fmc_ker_ck/4. • If CLKDIV=1, MWID = 16 bits, AXI data size=8 bits, FMC_CLK=fmc_ker_ck/2. NOR Flash memories specify a minimum time from NADV assertion to FMC_CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse. For some PSRAM memories which must be configured to synchronous mode, during the BCR register writing, the memory attribute space must be configured to device or stronglyordered. Once PSRAM BCR register is configured, the memory attribute of PSRAM address space can be programmed to cacheable. Data latency versus NOR memory latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register. The FMC does not include the clock cycle when NADV is low in the data latency count. Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) FMC_CLK clock cycles • or NOR Flash latency = (DATLAT + 3) FMC_CLK clock cycles Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed. Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access. 772/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Single-burst transfer When the selected bank is configured in burst mode for synchronous accesses, if for example a single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AXI transfer is 16 bits), or length 2 (if the AXI transfer is 32 bits) and de-assert the Chip Select signal when the last data is strobed. Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer. Cross boundary page for Cellular RAM 1.5 Cellular RAM 1.5 does not allow burst access to cross the page boundary. The FMC controller allows to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory page size. Wait management For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) FMC_CLK clock cycles. If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when WAITPOL = 1). When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0). During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the Chip Select and output enable signals valid. It does not consider the data as valid. In burst mode, there are two timing configurations for the NOR Flash NWAIT signal: • The Flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset). • The Flash memory asserts the NWAIT signal during the wait state The FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3). DocID029587 Rev 3 773/3178 818 Flexible memory controller (FMC) RM0433 Figure 103. Wait configuration waveforms 0HPRU\WUDQVDFWLRQ EXUVWRIKDOIZRUGV IPFBNHUBFN )0&B&/. $> @ DGGU> @ 1$'9 1:$,7 :$,7&)* 1:$,7 :$,7&)* LQVHUWHGZDLWVWDWH $'> @ DGGU> @ GDWD GDWD GDWD 06Y9 Figure 104. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 0HPRU\WUDQVDFWLRQ EXUVWRIKDOIZRUGV IPFBNHUBFN )0&B&/. $> @ DGGU> @ 1([ 12( 1:( +LJK 1$'9 1:$,7 :$,7&)* $'> @ '$7/$7 IPFBNHUBFN F\FOHV $GGU> @ LQVHUWHGZDLWVWDWH GDWD FORFN FORFN F\FOH F\FOH GDWD 'DWDVWUREHV GDWD GDWD 'DWDVWUREHV 06Y9 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. 774/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 171. FMC_BCRx bit fields Bit No. Bit name Value to set 31 MC 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 18:16 CPSIZE 15 ASYNCWAIT 0x0 14 EXTMOD 0x0 13 WAITEN to be set to 1 if the memory supports this feature, to be kept at 0 otherwise 12 WREN no effect on synchronous read 11 WAITCFG to be set according to memory 10 Reserved 0x0 9 WAITPOL to be set according to memory 8 BURSTEN 0x1 7 Reserved 0x1 6 FACCEN Set according to memory support (NOR Flash memory) 5-4 MWID As needed 3-2 MTYP 0x1 or 0x2 1 MUXEN As needed 0 MBKEN 0x1 0x1 0x000 As needed 0x000 No effect on synchronous read As needed. (0x1 when using CRAM 1.5) Table 172. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29:28 ACCMOD 0x0 27-24 DATLAT Data latency 27-24 DATLAT Data latency 23-20 CLKDIV 0x0 to get CLK = fmc_ker_ck (Not supported) 0x1 to get CLK = 2 × fmc_ker_ck .. 19-16 BUSTURN 15-8 DATAST Time between NEx high to NEx low (BUSTURN fmc_ker_ck) Don’t care DocID029587 Rev 3 775/3178 818 Flexible memory controller (FMC) RM0433 Table 172. FMC_BTRx bit fields (continued) Bit number Bit name Value to set 7-4 ADDHLD Don’t care 3-0 ADDSET Don’t care Figure 105. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 0HPRU\WUDQVDFWLRQ EXUVWRIKDOIZRUGV IPFBNHUBFN )0&B&/. DGGU> @ $> @ 1([ +L= 12( 1:( 1$'9 1:$,7 :$,7&)* '$7/$7 IPFBNHUBFNF\FOHV $'> @ $GGU> @ LQVHUWHGZDLWVWDWH GDWD FORFN FORFN F\FOH F\FOH GDWD 06Y9 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 173. FMC_BCRx bit fields 776/3178 Bit No. Bit name Value to set 31 FMCEN 30-26 Reserved 25-24 BMAP 23-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 0x000 As needed 0x000 No effect on synchronous read DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Table 173. FMC_BCRx bit fields (continued) Bit No. Bit name Value to set 18:16 CPSIZE 15 ASYNCWAIT 0x0 14 EXTMOD 0x0 13 WAITEN to be set to 1 if the memory supports this feature, to be kept at 0 otherwise. 12 WREN 0x1 11 WAITCFG 0x0 10 Reserved 0x0 9 WAITPOL to be set according to memory 8 BURSTEN no effect on synchronous write 7 Reserved 0x1 6 FACCEN Set according to memory support 5-4 MWID As needed 3-2 MTYP 0x1 1 MUXEN As needed 0 MBKEN 0x1 As needed. (0x1 when using CRAM 1.5) Table 174. FMC_BTRx bit fields Bit number Bit name Value to set 31-30 Reserved 0x0 29:28 ACCMOD 0x0 27-24 DATLAT Data latency 23-20 CLKDIV 0x0 to get CLK = fmc_ker_ck (not supported) 0x1 to get CLK = 2 × fmc_ker_ck 19-16 BUSTURN 15-8 DATAST Don’t care 7-4 ADDHLD Don’t care 3-0 ADDSET Don’t care Time between NEx high to NEx low (BUSTURN fmc_ker_ck) DocID029587 Rev 3 777/3178 818 Flexible memory controller (FMC) 22.7.6 RM0433 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 rw 2 rw rw rw 1 0 MBKEN 3 MUXEN 4 MTYP Res. 5 MWID 6 FACCEN rw 7 rw rw BURSTEN rw rw rw Res. rw 8 WAITPOL WREN WAITCFG rw 9 rw CPSIZE[2:0] WAITEN CBURSTRW WFDIS Res. CCLKEN rw rw rw 14 13 12 11 10 EXTMOD rw Res. BMAP[1:0] Res. Res. Res. Res. Res. FMCEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw 15 ASYNCWAIT This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. rw rw Bit 31 FMCEN: FMC controller Enable This bit enables/disables the FMC controller. 0: Disable the FMC controller 1: Enable the FMC controller Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bits 30: 26 Reserved, must be kept at reset value. Bits 25: 24 BMAP[1:0]: FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for 01: Default mapping (Refer to Figure 2 and Table 10). 01: NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped. 10: SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping 11: reserved. Note: The BMAP bits of the FMC_BCR2..4 registers are don’t care. It is only enabled through the FMC_BCR1 register. Bits 23: 22 Reserved, must be kept at reset value. Bit 21 WFDIS: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. 0: Write FIFO enabled (Default after reset) 1: Write FIFO disabled Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. 778/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Bit 20 CCLKEN: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. 0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset). 1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) Bit 19 CBURSTRW: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 0: Write operations are always performed in asynchronous mode 1: Write operations are performed in synchronous mode. Bits 18:16 CPSIZE[2:0]: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). 000: No burst split when crossing page boundary (default after reset). 001: 128 bytes 010: 256 bytes 100: 1024 bytes Other configuration: reserved. Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset) 1: NWAIT signal is taken in to account when running an asynchronous protocol Bit 14 EXTMOD: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. 0: values inside FMC_BWTR register are not taken into account (default after reset) 1: values inside FMC_BWTR register are taken into account Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) – Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). DocID029587 Rev 3 779/3178 818 Flexible memory controller (FMC) RM0433 Bit 13 WAITEN: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset) Bit 12 WREN: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 0: Write operations are disabled in the bank by the FMC, an AXI slave error is reported, 1: Write operations are enabled for the bank by the FMC (default after reset). Bit 11 WAITCFG: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 0: NWAIT signal is active one data cycle before wait state (default after reset), 1: NWAIT signal is active during wait state (not used for PSRAM). Bit 10 Reserved, must be kept at reset value. Bit 9 WAITPOL: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 0: NWAIT active low (default after reset), 1: NWAIT active high. Bit 8 BURSTEN: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable. Read accesses are performed in synchronous mode. Bit 7 Reserved, must be kept at reset value. Bit 6 FACCEN: Flash access enable This bit enables NOR Flash memory access operations. 0: Corresponding NOR Flash memory access is disabled 1: Corresponding NOR Flash memory access is enabled (default after reset) Bits 5:4 MWID[1:0]: Memory data bus width Defines the external memory device width, valid for all type of memories. 00: 8 bits 01: 16 bits (default after reset) 10: 32 bits 11: reserved 780/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Bits 3:2 MTYP[1:0]: Memory type These bits define the type of external memory attached to the corresponding memory bank: 00: SRAM (default after reset for Bank 2...4) 01: PSRAM (CRAM) 10: NOR Flash/OneNAND Flash (default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 0: Address/Data non-multiplexed 1: Address/Data multiplexed on databus (default after reset) Bit 0 MBKEN: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0: Corresponding memory bank is disabled 1: Corresponding memory bank is enabled DocID029587 Rev 3 781/3178 818 Flexible memory controller (FMC) RM0433 SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4) Address offset: 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 31 30 Res. Res. 15 14 29 28 27 ACCMOD 26 25 24 23 22 DATLAT rw 20 19 18 17 16 BUSTURN rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAST rw 21 CLKDIV rw rw rw ADDHLD rw rw rw rw rw rw ADDSET rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 ACCMOD[1:0]: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write burst mode enabled (BURSTEN / CBURSTRW bits set), these bits define the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in fmc_ker_ck periods, but in FMC_CLK periods. For asynchronous access, this value is don't care. 0000: Data latency of 2 FMC_CLK clock cycles for first burst access 1111: Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset) Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of fmc_ker_ck cycles: 0000: Reserved 0001: FMC_CLK period = 2 × fmc_ker_ck periods 0010: FMC_CLK period = 3 × fmc_ker_ck periods 1111: FMC_CLK period = 16 × fmc_ker_ck periods (default value after reset) In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 22.7.5: Synchronous transactions for FMC_CLK divider ratio formula) 782/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-towrite) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D. In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows: • The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for modes muxed and D. • There is a bus turnaround delay of 1 FMC clock cycle between: –Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. –An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for modes muxed and D. –An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank. • There is a bus turnaround delay of 2 FMC clock cycle between: –Two consecutive synchronous writes (burst or single) to the same bank. –A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different for the case of read. –Two consecutive synchronous reads (burst or single) followed by any synchronous/asynchronous read or write from/to another static memory bank. • There is a bus turnaround delay of 3 FMC clock cycle between: –Two consecutive synchronous writes (burst or single) to different static bank. –A synchronous write (burst or single) access and a synchronous read from the same or a different bank. 0000: BUSTURN phase duration = 0 fmc_ker_ck clock cycle added ... 1111: BUSTURN phase duration = 15 x fmc_ker_ck clock cycles added (default value after reset) Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 88 to Figure 100), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × fmc_ker_ck clock cycles 0000 0010: DATAST phase duration = 2 × fmc_ker_ck clock cycles ... 1111 1111: DATAST phase duration = 255 × fmc_ker_ck clock cycles (default value after reset) For each memory type and access mode data-phase duration, please refer to the respective figure (Figure 88 to Figure 100). Example: Mode1, write access, DATAST = 1: Data-phase duration = DATAST+1 = 1 x fmc_ker_ck clock cycles. Note: In synchronous accesses, this value is don’t care. DocID029587 Rev 3 783/3178 818 Flexible memory controller (FMC) RM0433 Bits 7:4 ADDHLD: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 88 to Figure 100), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 × fmc_ker_ck clock cycle 0010: ADDHLD phase duration = 2 × fmc_ker_ck clock cycle ... 1111: ADDHLD phase duration = 15 × fmc_ker_ck clock cycles (default value after reset) For each access mode address-hold phase duration, please refer to the respective figure (Figure 88 to Figure 100). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. Bits 3:0 ADDSET: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 88 to Figure 100), used in SRAMs, ROMs and asynchronous NOR Flash: 0000: ADDSET phase duration = 0 × fmc_ker_ck clock cycle ... 1111: ADDSET phase duration = 15 × fmc_ker_ck clock cycles (default value after reset) For each access mode address setup phase duration, please refer to the respective figure (refer to Figure 88 to Figure 100). Note: In synchronous accesses, this value is don’t care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. Note: 784/3178 PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to extend the latency as needed. On PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready. This method can be used also with the latest generation of synchronous Flash memories that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the specific Flash memory being used). DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4) Address offset: 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 31 30 Res. Res. 15 14 29 28 ACCMOD rw rw 13 12 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 DATAST rw rw rw rw rw 19 rw rw rw rw rw 17 16 BUSTURN rw rw rw rw 3 2 1 0 ADDHLD rw 18 ADDSET[3:0] rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 ACCMOD: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:20 Reserved, must be kept at reset value. Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) fmc_ker_ck period ≥ tEHELmin. The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different expect for muxed or mode D. In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows: • The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for modes muxed and D. • There is a bus turnaround delay of 2 FMC clock cycle between: –Two consecutive synchronous writes (burst or single) to the same bank. –A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or from static memory bank. • There is a bus turnaround delay of 3 FMC clock cycle between: –Two consecutive synchronous writes (burst or single) to different static bank. –A synchronous write (burst or single) transfer and a synchronous read from the same or a different bank. 0000: BUSTURN phase duration = 0 fmc_ker_ck clock cycle added ... 1111: BUSTURN phase duration = 15 fmc_ker_ck clock cycles added (default value after reset) DocID029587 Rev 3 785/3178 818 Flexible memory controller (FMC) RM0433 Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 88 to Figure 100), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × fmc_ker_ck clock cycles 0000 0010: DATAST phase duration = 2 × fmc_ker_ck clock cycles ... 1111 1111: DATAST phase duration = 255 × fmc_ker_ck clock cycles (default value after reset) Bits 7:4 ADDHLD: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 88 to Figure 100), used in asynchronous multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration = 1 × fmc_ker_ck clock cycle 0010: ADDHLD phase duration = 2 × fmc_ker_ck clock cycle ... 1111: ADDHLD phase duration = 15 × fmc_ker_ck clock cycles (default value after reset) Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. Bits 3:0 ADDSET: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in fmc_ker_ck cycles (refer to Figure 88 to Figure 100), used in asynchronous accesses: 0000: ADDSET phase duration = 0 × fmc_ker_ck clock cycle ... 1111: ADDSET phase duration = 15 × fmc_ker_ck clock cycles (default value after reset) Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 786/3178 DocID029587 Rev 3 RM0433 22.8 Flexible memory controller (FMC) NAND Flash controller The FMC generates the appropriate signal timings to drive 8- and 16-bit NAND Flash memories. The NAND bank is configured through dedicated registers (Section 22.8.7). The programmable memory parameters include access timings (shown in Table 175) and ECC configuration. Table 175. Programmable NAND Flash access parameters 22.8.1 Parameter Function Access mode Unit Min. Max. Memory setup time Number of clock cycles (fmc_ker_ck) required to set up the address before the command assertion Read/Write AHB clock cycle (fmc_ker_ck) 1 255 Memory wait Minimum duration (in fmc_ker_ck clock cycles) of the command assertion Read/Write AHB clock cycle (fmc_ker_ck) 2 255 Memory hold Number of clock cycles (fmc_ker_ck) during which the address must be held (as well as the data if a write access is performed) after the command deassertion Read/Write AHB clock cycle (fmc_ker_ck) 1 254 Memory databus highZ Number of clock cycles (fmc_ker_ck) during which the data bus is kept in high-Z state after a write access has started Write AHB clock cycle (fmc_ker_ck) 0 254 External memory interface signals The following tables list the signals that are typically used to interface NAND Flash memories. Note: The prefix “N” identifies the signals which are active low. 8-bit NAND Flash memory t Table 176. 8-bit NAND Flash memory FMC signal name I/O Function A[17] O NAND Flash address latch enable (ALE) signal A[16] O NAND Flash command latch enable (CLE) signal D[7:0] I/O 8-bit multiplexed, bidirectional address/data bus NCE O Chip Select NOE(= NRE) O Output enable (memory signal name: read enable, NRE) NWE O Write enable NWAIT/INT I NAND Flash ready/busy input signal to the FMC DocID029587 Rev 3 787/3178 818 Flexible memory controller (FMC) RM0433 Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed. 16-bit NAND Flash memory Table 177. 16-bit NAND Flash memory FMC signal name I/O Function A[17] O NAND Flash address latch enable (ALE) signal A[16] O NAND Flash command latch enable (CLE) signal D[15:0] I/O 16-bit multiplexed, bidirectional address/data bus NCE O Chip Select NOE(= NRE) O Output enable (memory signal name: read enable, NRE) NWE O Write enable NWAIT/INT I NAND Flash ready/busy input signal to the FMC Note: Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed. 22.8.2 NAND Flash supported memories and transactions Table 178 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 178. Supported memories and transactions Device NAND 8-bit 788/3178 AXI data Memory Allowed/ size data size not allowed Mode R/W Asynchronous R 8 8 Y - Asynchronous W 8 8 Y - Asynchronous R 16 8 Y Split into 2 FMC accesses Asynchronous W 16 8 Y Split into 2 FMC accesses Asynchronous R 32 8 Y Split into 4 FMC accesses Asynchronous W 32 8 Y Split into 4 FMC accesses Asynchronous R 32 8 Y Split into 8 FMC accesses Asynchronous W 32 8 Y Split into 8 FMC accesses DocID029587 Rev 3 Comments RM0433 Flexible memory controller (FMC) Table 178. Supported memories and transactions (continued) Device NAND 16-bit 22.8.3 AXI data Memory Allowed/ size data size not allowed Mode R/W Comments Asynchronous R 8 16 Y - Asynchronous W 8 16 N - Asynchronous R 16 16 Y - Asynchronous W 16 16 Y - Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Asynchronous R 32 16 Y Split into 4 FMC accesses Asynchronous W 32 16 Y Split into 4 FMC accesses Timing diagrams for NAND Flash memories The NAND Flash memory bank is managed through a set of registers: • Control register: FMC_PCR • Interrupt status register: FMC_SR • ECC register: FMC_ECCR • Timing register for Common memory space: FMC_PMEM • Timing register for Attribute memory space: FMC_PATT Each timing configuration register contains three parameters used to define the number of fmc_ker_ck cycles for the three phases of any NAND Flash access, plus one parameter that defines the timing to start driving the data bus when a write access is performed. Figure 106 shows the timing parameter definitions for common memory accesses, knowing that Attribute memory space access timings are similar. DocID029587 Rev 3 789/3178 818 Flexible memory controller (FMC) RM0433 Figure 106. NAND Flash controller waveforms for common memory access IPFBNHUBFN $> @ 1&([ 15(* +LJK 1,2: 1,25 -%-X3%4 -%-X(/,$ 0(0[:$,7 1:( 12( 0(0[+,= ZULWHBGDWD UHDGBGDWD 9DOLG 06Y9 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 2. For write accesses, the hold phase delay is (MEMHOLD) fmc_ker_ck cycles and for read access is (MEMHOLD + 1) fmc_ker_ck cycles. 22.8.4 NAND Flash operations The command latch enable (CLE) and address latch enable (ALE) signals of the NAND Flash memory device are driven by address signals from the FMC controller. This means that to send a command or an address to the NAND Flash memory, the CPU has to perform a write to a specific address in its memory space. A typical page read operation from the NAND Flash device requires the following steps: 790/3178 1. Program and enable the corresponding memory bank by configuring the FMC_PCR and FMC_PMEM (and for some devices, FMC_PATT, see Section 22.8.5: NAND Flash prewait feature) registers according to the characteristics of the NAND Flash memory (PWID bits for the data bus width of the NAND Flash memory, PWAITEN = 0 or 1 as needed, see Section 22.6.2: NAND Flash memory address mapping for timing configuration). 2. The CPU performs a byte write to the common memory space, with data byte equal to one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The LE input of the NAND Flash memory is active during the write strobe (low pulse on NWE), thus the written byte is interpreted as a command by the NAND Flash memory. Once the command is latched by the memory device, it does not need to be written again for the following page read operations. 3. The CPU can send the start address (STARTAD) for a read operation by writing four bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9], STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in the common memory or attribute space. The ALE input of the NAND Flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FMC, which can be used DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) to implement the prewait functionality needed by some NAND Flash memories (see details in Section 22.8.5: NAND Flash prewait feature). 22.8.5 4. The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low). 5. The CPU can then perform byte read operations from the common memory space to read the NAND Flash page (data field + Spare field) byte by byte. 6. The next NAND Flash page can be read without any CPU command or address write operation. This can be done in three different ways: – by simply performing the operation described in step 5 – a new random address can be accessed by restarting the operation at step 3 – a new command can be sent to the NAND Flash device by restarting at step 2 NAND Flash prewait feature Some NAND Flash devices require that, after writing the last part of the address, the controller waits for the R/NB signal to go low. (see Figure 107). Figure 107. Access to non ‘CE don’t care’ NAND-Flash .#% MUST STAY LOW .#% #,% !,% .7% (IGH ./% T2 )/;= X ! ! ! ! ! ! ! T7" 2." AI 1. CPU wrote byte 0x00 at address 0x7001 0000. 2. CPU wrote byte A7~A0 at address 0x7002 0000. 3. CPU wrote byte A16~A9 at address 0x7002 0000. 4. CPU wrote byte A24~A17 at address 0x7002 0000. 5. CPU wrote byte A25 at address 0x8802 0000: FMC performs a write access using FMC_PATT2 timing definition, where ATTHOLD ≥ 7 (providing that (7+1) × fmc_ker_ck = 112 ns > tWB max). This guarantees that NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where NCE is not don’t care). DocID029587 Rev 3 791/3178 818 Flexible memory controller (FMC) RM0433 When this function is required, it can be performed by programming the MEMHOLD value to meet the tWB timing. However, any CPU read access to NAND Flash memory has a hold delay of (MEMHOLD + 1) fmc_ker_ck cycles, and any CPU write access has a hold delay of (MEMHOLD) fmc_ker_ck cycles that is inserted between the rising edge of the NWE signal and the next access. To cope with this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the tWB timing, and by keeping the MEMHOLD value at its minimum value. The CPU must then use the common memory space for all NAND Flash read and write accesses, except when writing the last address byte to the NAND Flash device, where the CPU must write to the attribute memory space. 22.8.6 Computation of the error correction code (ECC) in NAND Flash memory The FMC controller includes an error correction code computation hardware block. It reduces the host CPU workload when processing the ECC by software.The ECC block is associated with NAND bank. The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the NAND Flash memory. It is based on the BCH8 coding algorithm and consists in calculating the row and column parity. The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and NWE) each time the NAND Flash memory bank is active. The ECC operates as follows: • When accessing NAND Flash bank, the data present on the D[15:0] bus is latched and used for ECC computation. • When accessing any other address in NAND Flash memory, the ECC logic is idle, and does not perform any operation. As a result, write operations to define commands or addresses to the NAND Flash memory are not taken into account for ECC computation. Once the desired number of bytes has been read/written from/to the NAND Flash memory by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value. Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to one in the FMC_PCR registers. 792/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Execute below the sequence to perform an ECC computation: 22.8.7 1. Enable the ECCEN bit in the FMC_PCR register. 2. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. 3. Wait until the ECC code is ready (FIFO empty). 4. Read the ECC value available in the FMC_ECCR register and store it in a variable. 5. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back the written data from the NAND page. While the NAND page is read, the ECC block computes the ECC value. 6. Read the new ECC value available in the FMC_ECCR register. 7. If the two ECC values are the same, no correction is required, otherwise there is an ECC error and the software correction routine returns information on whether the error can be corrected or not. NAND Flash controller registers NAND Flash control registers (FMC_PCR) Address offset: 0x80 rw rw rw rw rw rw rw 1 0 PWID Res. rw 2 PBKEN rw 3 PWAITEN rw TCLR 4 Res. rw TAR 8 7 6 Res. ECCPS 9 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ECCEN Reset value: 0x0000 0018 5 rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:17 ECCPS: ECC page size. These bits define the page size for the extended ECC: 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes Bits 16:13 TAR: ALE to RE delay. These bits set time from ALE low to RE low in number of fmc_ker_ck clock cycles. Time is: t_ar = (TAR + SET + 2) × tfmc_ker_ck where tfmc_ker_ck is the FMC clock period 0000: 1 x fmc_ker_ck cycle (default) 1111: 16 x fmc_ker_ck cycles Note: Set is MEMSET or ATTSET according to the addressed space. DocID029587 Rev 3 793/3178 818 Flexible memory controller (FMC) RM0433 Bits 12:9 TCLR: CLE to RE delay. These bits set time from CLE low to RE low in number of fmc_ker_ck clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) × tfmc_ker_ck where tfmc_ker_ck is the fmc_ker_ck clock period 0000: 1 x fmc_ker_ck cycle (default) 1111: 16 x fmc_ker_ck cycles Note: Set is MEMSET or ATTSET according to the addressed space. Bits 8:7 Reserved, must be kept at reset value. Bit 6 ECCEN: ECC computation logic enable bit 0: ECC logic is disabled and reset (default after reset), 1: ECC logic is enabled. Bits 5:4 PWID: Data bus width. These bits define the external memory device width. 00: 8 bits 01: 16 bits (default after reset). 10: reserved. 11: reserved. Bit 3 Reserved, must be kept at reset value. Bit 2 PBKEN: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 0: Corresponding memory bank is disabled (default after reset) 1: Corresponding memory bank is enabled Bit 1 PWAITEN: Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank: 0: disabled 1: enabled Bit 0 Reserved, must be kept at reset value. FIFO status and interrupt register (FMC_SR) Address offset: 0x84 Reset value: 0x0000 0040 This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data. This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes. The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty. 794/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN IFS ILS IRS r rw rw rw rw rw rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit 0: Interrupt falling edge detection request disabled 1: Interrupt falling edge detection request enabled Bit 4 ILEN: Interrupt high-level detection enable bit 0: Interrupt high-level detection request disabled 1: Interrupt high-level detection request enabled Bit 3 IREN: Interrupt rising edge detection enable bit 0: Interrupt rising edge detection request disabled 1: Interrupt rising edge detection request enabled Bit 2 IFS: Interrupt falling edge status The flag is set by hardware and reset by software. 0: No interrupt falling edge occurred 1: Interrupt falling edge occurred Note: If this bit is written by software to 1 it will be set. Bit 1 ILS: Interrupt high-level status The flag is set by hardware and reset by software. 0: No Interrupt high-level occurred 1: Interrupt high-level occurred Bit 0 IRS: Interrupt rising edge status The flag is set by hardware and reset by software. 0: No interrupt rising edge occurred 1: Interrupt rising edge occurred Note: If this bit is written by software to 1 it will be set. Common memory space timing register 2..4 (FMC_PMEM) Address offset: Address: 0x88 Reset value: 0xFCFC FCFC The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access. DocID029587 Rev 3 795/3178 818 Flexible memory controller (FMC) 31 30 29 28 rw rw rw rw 15 14 13 12 27 RM0433 26 25 24 23 22 21 rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 MEMHIZx rw rw rw rw 19 18 17 16 rw rw rw rw 3 2 1 0 rw rw rw MEMHOLDx MEMWAITx rw 20 MEMSETx rw rw rw rw rw rw rw rw Bits 31:24 MEMHIZ: Common memory x data bus Hi-Z time These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 0000 0000: 0 x fmc_ker_ck cycle 1111 1110: 254 x fmc_ker_ck cycles 1111 1111: reserved. Bits 23:16 MEMHOLD: Common memory hold time These bits define the number of fmc_ker_ck clock cycles for write accesses and fmc_ker_ck+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 0000 0000: reserved. 0000 0001: 1 fmc_ker_ck cycle for write access / 3 fmc_ker_ck cycle for read access 1111 1110: 254 fmc_ker_ck cycles for write access / 257 fmc_ker_ck cycles for read access 1111 1111: reserved. Bits 15:8 MEMWAIT: Common memory wait time These bits define the minimum number of fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck: 0000 0000: reserved 0000 0001: x fmc_ker_ck cycles (+ wait cycle introduced by de-asserting NWAIT) 1111 1110: 255 x fmc_ker_ck cycles (+ wait cycle introduced by de-asserting NWAIT) 1111 1111: reserved. Bits 7:0 MEMSET: Common memory x setup time These bits define the number of fmc_ker_ck (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0000 0000: fmc_ker_ck cycles 1111 1110: 255 x fmc_ker_ck cycles 1111 1111: reserved 796/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Attribute memory space timing registers (FMC_PATT) Address offset: 0x8C Reset value: 0xFCFC FCFC The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section 22.8.5: NAND Flash prewait feature). 31 30 29 28 27 26 25 24 23 22 21 ATTHIZ 20 19 18 17 16 ATTHOLD rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw ATTWAIT rw rw rw rw rw ATTSET rw rw rw rw rw rw rw rw Bits 31:24 ATTHIZx: Attribute memory data bus Hi-Z time These bits define the number of fmc_ker_ck clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0000 0000: 0 x fmc_ker_ck cycle 1111 1110: 254 x fmc_ker_ck cycles 1111 1111: reserved. Bits 23:16 ATTHOLD: Attribute memory hold time These bits define the number of fmc_ker_ck clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0000 0000: reserved 0000 0001: 1 x fmc_ker_ck cycle 1111 1110: 254 x fmc_ker_ck cycles 1111 1111: reserved. Bits 15:8 ATTWAIT: Attribute memory wait time These bits define the minimum number of x fmc_ker_ck (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of fmc_ker_ck: 0000 0000: reserved 0000 0001: 2 x fmc_ker_ck cycles (+ wait cycle introduced by de-assertion of NWAIT) 1111 1110: 255 x fmc_ker_ck cycles (+ wait cycle introduced by de-asserting NWAIT) 1111 1111: reserved. Bits 7:0 ATTSET: Attribute memory setup time These bits define the number of fmc_ker_ck (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0000 0000: 1 x fmc_ker_ck cycle 1111 1110: 255 x fmc_ker_ck cycles 1111 1111: reserved. DocID029587 Rev 3 797/3178 818 Flexible memory controller (FMC) RM0433 ECC result registers (FMC_ECCR) Address offset: 0x94 Reset value: 0x0000 0000 This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section 22.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECC[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r ECC[15:0] r r r r r r r r r Bits 31:0 ECC[31:0]: ECC result This field contains the value computed by the ECC computation logic. Table 179 describes the contents of these bit fields. Table 179. ECC result relevant bits 798/3178 ECCPS[2:0] Page size in bytes ECC bits 000 256 ECC[21:0] 001 512 ECC[23:0] 010 1024 ECC[25:0] 011 2048 ECC[27:0] 100 4096 ECC[29:0] 101 8192 ECC[31:0] DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) 22.9 SDRAM controller 22.9.1 SDRAM controller main features The main features of the SDRAM controller are the following: 22.9.2 • Two SDRAM banks with independent configuration • 8-bit, 16-bit, 32-bit data bus width • 13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx32bit (256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB) • Word, half-word, byte access • SDRAM clock can be fmc_ker_ck/2 or fmc_ker_ck/3 • Automatic row and bank boundary management • Multibank ping-pong access • Programmable timing parameters • Automatic Refresh operation with programmable Refresh rate • Self-refresh mode • Power-down mode • SDRAM power-up initialization by software • CAS latency of 1,2,3 • Cacheable Read FIFO with depth of 6 lines x32-bit (6 x14-bit address tag) SDRAM External memory interface signals At startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the external SDRAM devices must configured by the user application. The SDRAM controller I/O pins which are not used by the application, can be used for other purposes. Table 180. SDRAM signals SDRAM signal I/O type Description Alternate function SDCLK O SDRAM clock - SDCKE[1:0] O SDCKE0: SDRAM Bank 1 Clock Enable SDCKE1: SDRAM Bank 2 Clock Enable - SDNE[1:0] O SDNE0: SDRAM Bank 1 Chip Enable SDNE1: SDRAM Bank 2 Chip Enable - A[12:0] O Address FMC_A[12:0] D[31:0] I/O Bidirectional data bus FMC_D[31:0] BA[1:0] O Bank Address FMC_A[15:14] NRAS O Row Address Strobe - NCAS O Column Address Strobe - SDNWE O Write Enable - NBL[3:0] O Output Byte Mask for write accesses (memory signal name: DQM[3:0] FMC_NBL[3:0] DocID029587 Rev 3 799/3178 818 Flexible memory controller (FMC) 22.9.3 RM0433 SDRAM controller functional description All SDRAM controller outputs (signals, address and data) change on the falling edge of the memory clock (FMC_SDCLK). SDRAM initialization The initialization sequence is managed by software. If the two banks are used, the initialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting the Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register: 1. Program the memory device features into the FMC_SDCRx register. The SDRAM clock frequency, RBURST and RPIPE must be programmed in the FMC_SDCR1 register. 2. Program the memory device timing into the FMC_SDTRx register. The TRP and TRC timings must be programmed in the FMC_SDTR1 register. 3. Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register to start delivering the clock to the memory (SDCKE is driven high). 4. Wait during the prescribed delay period. Typical delay is around 100 μs (refer to the SDRAM datasheet for the required delay after power-up). 5. Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register to issue a “Precharge All” command. 6. Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 and/or CTB2) as well as the number of consecutive Auto-refresh commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM datasheet for the number of Auto-refresh commands that should be issued. Typical number is 8. 7. Configure the MRD field, set the MODE bits to ‘100’, and configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register to issue a “Load Mode Register” command and program the SDRAM device. In particular the Burst Length (BL) has to be set to ‘1’) and the CAS latency has to be selected. If the Mode Register is not the same for both SDRAM banks, this step has to be repeated twice, once for each bank and the Target Bank bits set accordingly. For mobile SDRAM devices, the MRD field is also used to configure the extended mode register while issuing the Load Mode Register” 8. Program the refresh rate in the FMC_SDRTR register The refresh rate corresponds to the delay between refresh cycles. Its value must be adapted to SDRAM devices. At this stage the SDRAM device is ready to accept commands. If a system reset occurs during an ongoing SDRAM access, the data bus might still be driven by the SDRAM device. Therefor the SDRAM device must be first reinitialized after reset before issuing any new access by the NOR Flash/PSRAM/SRAM or NAND Flash controller. Note: 800/3178 If two SDRAM devices are connected to the FMC, all the accesses performed at the same time to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for SDRAM Bank 1 (TMRD andTRAS timings) in the FMC_SDTR1 register. DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) SDRAM controller write cycle The SDRAM controller accepts single and burst write requests and translates them into single memory accesses. In both cases, the SDRAM controller keeps track of the active row for each bank to be able to perform consecutive write accesses to different banks (Multibank ping-pong access). Before performing any write access, the SDRAM bank write protection must be disabled by clearing the WP bit in the FMC_SDCRx register. Figure 108. Burst write SDRAM access waveforms 75&' 6'1( 6'&/. 5RZQ &ROD &ROE &ROF &ROG &ROH &ROI &RJ &ROK &ROL &ROM &RON &ROO $> @ 15$6 1&$6 6'1:( 'QD '$7$> @ 'QE 'QF 'QG 'QH 'QI 'QJ 'QK 'QL 'QM 'QN 'QO 069 The SDRAM controller always checks the next access. • If the next access is in the same row or in another active row, the write operation is carried out, • if the next access targets another row (not active), the SDRAM controller generates a precharge command, activates the new row and initiates a write command. DocID029587 Rev 3 801/3178 818 Flexible memory controller (FMC) RM0433 SDRAM controller read cycle The SDRAM controller accepts single and burst read requests and translates them into single memory accesses. In both cases, the SDRAM controller keeps track of the active row in each bank to be able to perform consecutive read accesses in different banks (Multibank ping-pong access). Figure 109. Burst read SDRAM access 75&' &$6ODWHQF\ 6'1( 6'&/. $> @ 5RZQ &ROD &ROE &ROF &ROG &ROH &ROI 15$6 1&$6 1:( '$7$> @ 'QD 'QE 'QF 'QG 'QH 'QI 06 9 The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to store data read in advance during the CAS latency period (up to 3 memory clock cycles, programmed FMC_SDCRx) and during the RPIPE delay when set to 2xfmc_ker_ck clock cycles as configured in FMC_SDCR1) following this formula: CAS Latency + 1 + (RPIPE DIV2). The RBURST bit must be set in the FMC_SDCR1 register to anticipate the next read access. Examples: • CAS=3, RPIPE= 2xfmc_ker_ck. In this case, 5 data (not committed) are stored in the FIFO (4 data during CAS latency and 1 data during RPIPE delay) • CAS=3, RPIPE= 1xfmc_ker_ck. In this case, 4 data (not committed) are stored in the FIFO (4 data during CAS latency) The read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the column address, 2 bits to select the internal bank and the active row, and 1 bit to select the SDRAM device When the end of the row is reached in advance during an burst read transaction, the data read in advance (not committed) are not stored in the read FIFO. For single read access, data are correctly stored in the FIFO. 802/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Each time a read request occurs, the SDRAM controller checks: • If the address matches one of the address tags, data are directly read from the FIFO and the corresponding address tag/ line content is cleared and the remaining data in the FIFO are compacted to avoid empty lines. • Otherwise, a new read command is issued to the memory and the FIFO is updated with new data. If the FIFO is full, the older data are lost. Figure 110. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) VW5HDGDFFHVV 5HTXHVWHGGDWDLVQRWLQWKH),)2 )0&6'5$0&RQWUROOHU $;,0DVWHU UHDGUHTXHVW#[ 'DWD 6'5$0 'HYLFH &$6 OLQHV),)2 #[ 'DWD #[ 'DWD $GG7DJUHDG),)2 'DWDVWRUHGLQ),)2 LQDGYDQFHGXULQJ WKH&$6ODWHQF\SHULRG QG5HDGDFFHVV 5HTXHVWHGGDWDZDVSUHYLRXVO\VWRUHGLQWKH),)2 $GGUHVVPDWFKHVZLWK RQHRIWKHDGGUHVVWDJV $;,0DVWHU )0&6'5$0&RQWUROOHU UHDGUHTXHVW#[ 'DWD 6'5$0 'HYLFH &$6 OLQHV),)2 #[ 'DWD #[ 'DWD $GG7DJUHDG),)2 'DWDUHDGIURP),)2 069 During a write access or a Precharge command, the read FIFO is flushed and ready to be filled with new data. After the first read request, if the current access was not performed to a row boundary, the SDRAM controller anticipates the next read access during the CAS latency period and the RPIPE delay (if configured). This is done by incrementing the memory address. The following condition must be met: • RBURST control bit should be set to ‘1’ in the FMC_SDCR1 register. DocID029587 Rev 3 803/3178 818 Flexible memory controller (FMC) RM0433 The address management depends on the next AXI request: • Next request is sequential (Burst access) In this case, the SDRAM controller increments the address. • Next request is not sequential – If the new read request targets the same row or another active row, the new address is passed to the memory and the master is stalled for the CAS latency period, waiting for the new data from memory. – If the new read request does not target an active row, the SDRAM controller generates a Precharge command, activates the new row, and initiates a read command. If the RBURST is reset, the read FIFO is not used. Row and bank boundary management When a read or write access crosses a row boundary, if the next read or write access is sequential and the current access was performed to a row boundary, the SDRAM controller executes the following operations: 1. Precharge of the active row, 2. Activation of the new row 3. Start of a read/write command. At a row boundary, the automatic activation of the next row is supported for all columns and data bus width configurations. If necessary, the SDRAM controller inserts additional clock cycles between the following commands: • Between Precharge and Active commands to match TRP parameter (only if the next access is in a different row in the same bank), • Between Active and Read commands to match the TRCD parameter. These parameters are defined into the FMC_SDTRx register. Refer to Figure 108 and Figure 109 for read and burst write access crossing a row boundary. 804/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Figure 111. Read access crossing row boundary 420 42#$ #!3 LATENCY 3$.% 3$#,+ !;= 2OW N #OL A 2OW N #OL A #OL B .2!3 .#!3 .7% $ATA;= $NA $N A 0RECHARGE !CTIVATE 2OW 2EAD #OMMAND -36 Figure 112. Write access crossing row boundary 420 42#$ 3$.% 3$#,+ !;= #NA 2OW N #OLB #OLA #OLB .2!3 .#!3 .7% $ATA;= $NA $N A $NB 0RECHARGE !CTIVATE 2OW $N B 7RITE COMMAND -36 DocID029587 Rev 3 805/3178 818 Flexible memory controller (FMC) RM0433 If the next access is sequential and the current access crosses a bank boundary, the SDRAM controller activates the first row in the next bank and initiates a new read/write command. Two cases are possible: • If the current bank is not the last one, the active row in the new bank must be precharged.At a bank boundary, the automatic activation of the next row is supported for all rows/columns and data bus width configuration. • If the current bank is the last one, the automatic activation of the next row is supported only when addressing 13-bit rows, 11-bit columns, 4 internal banks and 32-bit data bus SDRAM devices. Otherwise, the SDRAM address range is violated and an AXI slave error is generated. • In case of 13-bit row address, 11-bit column address, 4 internal banks and bus width 32-bit SDRAM memories, at boundary bank, the SDRAM controller continues to read/write from the second SDRAM device (assuming it has been initialized): a) The SDRAM controller activates the first row (after precharging the active row, if there is already an active row in the first internal bank, and initiates a new read/write command. b) If the first row is already activated, the SDRAM controller just initiates a read/write command. SDRAM controller refresh cycle The Auto-refresh command is used to refresh the SDRAM device content. The SDRAM controller periodically issues auto-refresh commands. An internal counter is loaded with the COUNT value in the register FMC_SDRTR. This value defines the number of memory clock cycles between the refresh cycles (refresh rate). When this counter reaches zero, an internal pulse is generated. If a memory access is ongoing, the auto-refresh request is delayed. However, if the memory access and the auto-refresh requests are generated simultaneously, the auto-refresh request takes precedence. If the memory access occurs during an auto-refresh operation, the request is buffered and processed when the auto-refresh is complete. If a new auto-refresh request occurs while the previous one was not served, the RE (Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been enabled (REIE = ‘1’). If SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates a PALL (Precharge ALL) command before the auto-refresh. If the Auto-refresh command is generated by the FMC_SDCMR Command Mode register (Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first. 806/3178 DocID029587 Rev 3 RM0433 22.9.4 Flexible memory controller (FMC) Low-power modes Two low-power modes are available: • Self-refresh mode The auto-refresh cycles are performed by the SDRAM device itself to retain data without external clocking. • Power-down mode The auto-refresh cycles are performed by the SDRAM controller. Self-refresh mode This mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register. The SDRAM clock stops running after a TRAS delay and the internal refresh timer stops counting only if one of the following conditions is met: • A Self-refresh command is issued to both devices • One of the devices is not activated (SDRAM bank is not initialized). Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL command. If the Write data FIFO is not empty, all data are sent to the memory before activating the Self-refresh mode and the BUSY status flag remains set. In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which remains low. The SDRAM device must remain in Self-refresh mode for a minimum period of time of TRAS and can remain in Self-refresh mode for an indefinite period beyond that. To guarantee this minimum period, the BUSY status flag remains high after the Self-refresh activation during a TRAS delay. As soon as an SDRAM device is selected, the SDRAM controller generates a sequence of commands to exit from Self-refresh mode. After the memory access, the selected device remains in Normal mode. To exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register. DocID029587 Rev 3 807/3178 818 Flexible memory controller (FMC) RM0433 Figure 113. Self-refresh mode 4 4 4 4N 4 4 3$#,+ T2!3MIN 3$#+% #/--!.$ 02%#(!2'% ./0 !54/ 2%&2%3( ./0 OR #/--!.$ ).(%2)4 !54/ 2%&2%3( $/- $/-,$/-5 ! ! ! ! !,, "!.+3 ! $ATA;= (I : T20 0RECHARGE ALL ACTIVE BANKS T832 %XIT 3ELF REFRESH MODE RESTART REFRESH TIMEBASE #,+ STABLE PRIOR TO EXISTING 3ELF REFRESH MODE %NTER 3ELF REFRESH MODE -36 808/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Power-down mode This mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register. Figure 114. Power-down mode 3$#,+ 3$#+% #/--!.$ ./0 ./0 !#4)6% T2#$ !LL BANKS IDLE )NPUT BUFFERS GATED OFF T2!3 %NTER 0OWER DOWN %XIT 0OWER DOWN T2# -36 If the Write data FIFO is not empty, all data are sent to the memory before activating the Power-down mode. As soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down mode. After the memory access, the selected SDRAM device remains in Normal mode. During Power-down mode, all SDRAM device input and output buffers are deactivated except for the SDCKE which remains low. The SDRAM device cannot remain in Power-down mode longer than the refresh period and cannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries out the refresh operation by executing the operations below: 1. Exit from Power-down mode and drive the SDCKE high 2. Generate the PALL command only if a row was active during Power-down mode 3. Generate the auto-refresh command 4. Drive SDCKE low again to return to Power-down mode. To exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register. DocID029587 Rev 3 809/3178 818 Flexible memory controller (FMC) 22.9.5 RM0433 SDRAM controller registers SDRAM Control registers 1,2 (FMC_SDCR1,2) Address offset: 0x140+ 4* (x – 1), x = 1,2 Reset value: 0x0000 02D0 21 20 19 18 17 16 15 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 rw rw rw rw rw rw rw rw 3 2 1 0 15 rw rw rw NR[1:0] Res. rw rw NC51:0] 4 MWID[1:0] 5 NB WP RBURST Res. rw Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 CAS[1:0] 29 SDCLK[1:0] 30 RPIPE[1:0] 31 Res. This register contains the control parameters for each SDRAM memory bank rw Bits 31:15 Reserved, must be kept at reset value. Bits 14:13 RPIPE[1:0]: Read pipe These bits define the delay, in fmc_ker_ck clock cycles, for reading data after CAS latency. 00: No fmc_ker_ck clock cycle delay 01: One fmc_ker_ck clock cycle delay 10: Two fmc_ker_ck clock cycle delay 11: reserved. Note: The corresponding bits in the FMC_SDCR2 register is read only. Bit 12 RBURST: Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. 0: single read requests are not managed as bursts 1: single read requests are always managed as bursts Note: The corresponding bit in the FMC_SDCR2 register is read only. Bits 11:10 SDCLK[1:0]: SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. 00: SDCLK clock disabled 01: Reserved 10: SDCLK period = 2 x fmc_ker_ck periods 11: SDCLK period = 3 x fmc_ker_ck periods Note: The corresponding bits in the FMC_SDCR2 register is read only. Bit 9 WP: Write protection This bit enables write mode access to the SDRAM bank. 0: Write accesses allowed 1: Write accesses ignored 810/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Bits 8:7 CAS[1:0]: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles 00: reserved. 01: 1 cycle 10: 2 cycles 11: 3 cycles Bit 6 NB: Number of internal banks This bit sets the number of internal banks. 0: Two internal Banks 1: Four internal Banks Bits 5:4 MWID[1:0]: Memory data bus width. These bits define the memory device width. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved. Bits 3:2 NR[1:0]: Number of row address bits These bits define the number of bits of a row address. 00: 11 bit 01: 12 bits 10: 13 bits 11: reserved. Bits 1:0 NC[1:0]: Number of column address bits These bits define the number of bits of a column address. 00: 8 bits 01: 9 bits 10: 10 bits 11: 11 bits. Note: Before modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user must first send a PALL command to make sure ongoing operations are complete. SDRAM Timing registers 1,2 (FMC_SDTR1,2) Address offset: 0x148 + 4 * (x – 1), x = 1,2 Reset value: 0x0FFF FFFF This register contains the timing parameters of each SDRAM bank 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 27 26 rw rw 11 10 rw 24 23 22 rw rw rw rw 9 8 7 6 TRCD TRC rw 25 rw rw rw 20 19 18 rw rw rw rw 5 4 3 2 TRP TRAS rw 21 rw rw rw 16 rw rw 1 0 rw rw TWR TXSR rw 17 TMRD rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. DocID029587 Rev 3 811/3178 818 Flexible memory controller (FMC) RM0433 Bits 27:24 TRCD[3:0]: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. 0000: 1 cycle. 0001: 2 cycles .... 1111: 16 cycles Bits 23:20 TRP[3:0]: Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. 0000: 1 cycle 0001: 2 cycles .... 1111: 16 cycles Note: The corresponding bits in the FMC_SDTR2 register are don’t care. Bits 19:16 TWR[3:0]: Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. 0000: 1 cycle 0001: 2 cycles .... 1111: 16 cycles Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR ³ TRAS - TRCD and TWR ³TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Bits 15:12 TRC[3:0]: Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. 0000: 1 cycle 0001: 2 cycles .... 1111: 16 cycles Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care. Bits 11:8 TRAS[3:0]: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. 0000: 1 cycle 0001: 2 cycles .... 1111: 16 cycles 812/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Bits 7:4 TXSR[3:0]: Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. 0000: 1 cycle 0001: 2 cycles .... 1111: 16 cycles Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device. Bits 3:0 TMRD[3:0]: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. 0000: 1 cycle 0001: 2 cycles .... 1111: 16 cycles Note: If two SDRAM devices are connected, all the accesses performed simultaneously to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for Bank 1 (TMRD and TRAS timings) in the FMC_SDTR1 register. The TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP and TRC timings must be programmed with the timings of the slowest device. SDRAM Command Mode register (FMC_SDCMR) Address offset: 0x150 Reset value: 0x0000 0000 This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks. 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 rw rw rw 21 20 rw rw rw 6 5 NRFS rw rw rw rw rw 19 18 17 16 rw rw rw rw 2 1 0 MRD 7 MRD rw 22 rw rw 4 3 CTB1 CTB2 rw rw MODE rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:9 MRD[13:0]: Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM. DocID029587 Rev 3 813/3178 818 Flexible memory controller (FMC) RM0433 Bits 8:5 NRFS[3:0]: Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’. 0000: 1 Auto-refresh cycle 0001: 2 Auto-refresh cycles .... 1110: 15 Auto-refresh cycles 1111: 16 Auto-refresh cycles Bit 4 CTB1: Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. 0: Command not issued to SDRAM Bank 1 1: Command issued to SDRAM Bank 1 Bit 3 CTB2: Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. 0: Command not issued to SDRAM Bank 2 1: Command issued to SDRAM Bank 2 Bits 2:0 MODE[2:0]: Command mode These bits define the command issued to the SDRAM device. 000: Normal Mode 001: Clock Configuration Enable 010: PALL (“All Bank Precharge”) command 011: Auto-refresh command 100: Load Mode Register 101: Self-refresh command 110: Power-down command 111: Reserved Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the unused bank must be kept to 0. SDRAM Refresh Timer register (FMC_SDRTR) Address offset:0x154 Reset value: 0x0000 0000 This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value. Refresh rate = ( COUNT + 1 ) × SDRAM clock frequency COUNT = ( SDRAM refresh period ⁄ Number of rows ) – 20 814/3178 DocID029587 Rev 3 RM0433 Flexible memory controller (FMC) Example Refresh rate = 64 ms ⁄ ( 8196rows ) = 7.81μs where 64 ms is the SDRAM refresh period. 7.81μs × 60MHz = 468.6 The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of ‘0000111000000’ (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles. As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is ’0’, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate. Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter. If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete. This register is common to SDRAM bank 1 and bank 2. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. REIE rw rw rw rw rw rw rw rw rw rw rw rw rw COUNT rw CRE w Bits 31: 15 Reserved, must be kept at reset value. Bit 14 REIE: RES Interrupt Enable 0: Interrupt is disabled 1: An Interrupt is generated if RE = 1 Bits 13:1 COUNT[12:0]: Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 Bit 0 CRE: Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register. 0: no effect 1: Refresh Error flag is cleared Note: The programmed COUNT value must not be equal to the sum of the following timings: TWR+TRP+TRC+TRCD+4 memory clock cycles . DocID029587 Rev 3 815/3178 818 Flexible memory controller (FMC) RM0433 SDRAM Status register (FMC_SDSR) Address offset: 0x158 Reset value: 0x0000 0000 8 7 6 5 Res. Res. Res. Res. 9 4 3 2 1 0 r r r Bits 31:5 Reserved, must be kept at reset value. Bits 4:3 MODES2: Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2. 00: Normal Mode 01: Self-refresh mode 10: Power-down mode Bits 2:1 MODES1: Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1. 00: Normal Mode 01: Self-refresh mode 10: Power-down mode Bit 0 RE: Refresh error flag 0: No refresh error has been detected 1: A refresh error has been detected An interrupt is generated if REIE = 1 and RE = 1 816/3178 DocID029587 Rev 3 RE 10 Res. 11 Res. 12 MODES1 Res. 13 Res. Res. 14 Res. Res. 15 MODES2 Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 r r RM0433 22.10 Flexible memory controller (FMC) FMC register map The following table summarizes the FMC registers. 1 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ECCPS [2:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MUXEN MBKEN MUXEN MBKEN MBKEN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ADDHLD[3:0] ADDSET[3:0] 1 1 1 1 1 1 1 1 1 1 ADDHLD[3:0] ADDSET[3:0] 1 1 1 1 1 1 1 1 1 1 ADDHLD[3:0] ADDSET[3:0] 1 1 1 1 1 1 1 1 1 1 ADDHLD[3:0] ADDSET[3:0] 1 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. TCLR[3:0] 0 DocID029587 Rev 3 1 ADDHLD[3:0] ADDSET[3:0] Res. TAR[3:0] 1 Res. Res. 1 1 ADDHLD[3:0] ADDSET[3:0] DATAST[7:0] 1 Reset value 1 DATAST[7:0] BUSTURN[3:0] 1 1 DATAST[7:0] BUSTURN[3:0] 1 1 DATAST[7:0] BUSTURN[3:0] 1 1 1 ADDHLD[3:0] ADDSET[3:0] DATAST[7:0] 1 1 1 DATAST[7:0] 1 1 1 Res. Res. Res. 1 1 Res. Res. Res. 1 1 0 ADDHLD[3:0] ADDSET[3:0] DATAST[7:0] 1 1 1 0 1 1 1 1 1 1 1 1 PWID [1:0] 1 0 0 1 1 0 0 1 0 0 0 0 0 0 Res. 1 0 1 PWAITEN 1 1 0 0 ILS 1 DATAST[7:0] 1 MUXEN 0 MWID MTYP [1:0] [1:0] MBKEN FACCEN FACCEN 0 0 MUXEN BURSTEN BURSTEN 0 Res. BURSTEN WAITPOL 1 MTYP BURSTEN Res. WAITPOL WAITCFG 1 0 Res. WAITPOL WREN 0 0 1 1 IRS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WAITPOL WAITCFG WAITCFG WAITEN 0 0 BUSTURN[3:0] 1 Res. 0 FACCEN WREN WAITCFG WREN WREN CPSIZE [2:0] 0 0 Res. Res. 1 FACCEN WAITEN WAITEN 1 PBKEN 1 Res. EXTMOD EXTMOD WAITEN 0 MWID ASYNCWAIT ASYNCWAIT EXTMOD 0 CLKDIV[3:0] BUSTURN[3:0] Res. Res. 0 IFS 1 Res. Res. 1 MWID MTYP [1:0] [1:0] 0 IREN 1 1 Res. 1 0 1 ILEN 1 0 Res. 0 1 0 IFEN 1 Res. Res. 0 0 ECCEN 1 1 Res. 0 0 CLKDIV[3:0] BUSTURN[3:0] 0 Res. CPSIZE [2:0] 0 MWID MTYP [1:0] [1:0] FEMPT 1 1 Res. 1 Res. 1 1 Res. 0 Res. 1 1 Res. 0 Res. 1 0 Res. Res. Res. Res. FMC_SR 0 Res. 1 Reset value 0x84 1 CLKDIV[3:0] BUSTURN[3:0] Res. FMC_PCR Res. 0x80 0 Res. Reset value 1 1 Res. FMC_BWTR4 1 1 Res. 0x11C 0 Res. Reset value 1 1 1 Res. FMC_BWTR3 1 1 1 1 Res. 0x114 0 Res. Reset value 1 1 1 Res. FMC_BWTR2 1 Res. 0x10C 0 Res. Reset value 1 1 1 CLKDIV[3:0] BUSTURN[3:0] 1 Res. FMC_BWTR1 0 1 Res. 0x104 0 Res. Reset value 0 Res. FMC_BTR4 Res. 0x1C 0 1 1 0 0 ASYNCWAIT ACCM OD[1:0] Reset value 0 1 Res. FMC_BTR3 Res. 0x14 0 0 0 0 EXTMOD ACCM OD[1:0] Reset value Res. FMC_BTR2 Res. 0x0C 0 0 CPSIZE [2:0] ASYNCWAIT ACCM OD[1:0] Reset value Res. Res. FMC_BTR1 0 CPSIZE[2:0] CCLKEN Res. Res. CBURSTRW ACCM OD[1:0] Res. ACCM DATLAT[3:0] OD[1:0] Res. ACCM DATLAT[3:0] OD[1:0] Res. ACCM DATLAT[3:0] OD[1:0] Res. Res. Res. Res. Res. CBURSTRW Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ACCM DATLAT[3:0] OD[1:0] Res. FMC_BCR4 Res. 0 Res. Reset value Reset value 0x04 CBURSTRW CBURSTRW Res. Res. WFDIS Res. Res. Res. Res. Res. BMAP[1:0] Res. Res. Res. Res. Res. Res. Res. Res. FMC_BCR3 Res. 0 Res. 0x18 Reset value Res. 0x10 FMC_BCR2 Res. 0x08 Res. FMC_BCR1 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 Res. Register name Res. Offset FMCEN Table 181. FMC register map 817/3178 818 Flexible memory controller (FMC) RM0433 FMC_PMEM 1 1 1 MEMHOLDx[7:0] 0 0 1 1 1 1 1 1 1 1 1 1 1 1 MEMWAITx[7:0] 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 ATTSET[7:0] 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPIPE [1:0] 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Res. 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 TMRD[3:0] 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 MODE[2:0] COUNT[12:0] 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 0 TMRD[3:0] 0 DocID029587 Rev 3 0 TXSR[3:0] 1 Res. 0 Res. 1 Res. 0 Res. 0 Res. 0 0 TXSR[3:0] TRAS[3:0] 1 0 Res. 0 Res. 1 Res. 0 0 SDCLK CAS MWID WP NB NR[1:0] NC [1:0] [1:0] [1:0] Res. 0 Res. 1 Res. 0 Res. 0 NRFS[3:0] 0 Res. 0 Res. Res. 1 TRAS[3:0] TRC[3:0] 1 0 MRD Res. Res. Res. Res. Res. 1 REIE Res. Res. 1 TWR[3:0] 1 0 1 0 CRE 1 0 1 0 RE 1 1 Res. Res. 1 1 Res. Res. 1 1 Res. 1 Res. 1 Res. 1 Res. 1 0 TRC[3:0] Res. 1 Res. 1 0 SDCLK CAS MWID WP NB NR[1:0] NC [1:0] [1:0] [1:0] Reset value 818/3178 1 MODES1[1:0] 1 TRP[3:0] 1 Res. TRCD[3:0] Res. Res. Res. Res. Res. FMC_SDSR 1 Res. 1 TWR[3:0] Reset value 0x158 0 1 RPIPE[ 1:0] Res. 1 1 Res. Res. Res. Res. Res. 0x154 0 Res. 1 Res. Res. Res. Res. 1 TRP[3:0] Reset value FMC_SDRTR MEMSETx[7:0] 0 CTB2 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value FMC_SDCMR TRCD[3:0] 1 Res. 0x150 Reset value FMC_SDTR2 1 CTB1 0 0 Res. 0x14C 1 MODES2[1:0] 0 0 Res. 0x148 1 RBURST 0 Reset value FMC_SDTR1 1 RBURST 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. FMC_SDCR2 1 ATTWAIT[7:0] Reset value 0x144 1 ECC[31:0] Res. FMC_SDCR1 1 ATTHOLD[7:0] FMC_ECCR Reset value 0 Res. Reset value 1 ATTHIZ[7:0] Res. 0x140 1 FMC_PATT 0x8C 0x94 MEMHIZx[7:0] 1 Res. Reset value Res. 0x88 Res. Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 181. FMC register map (continued) 0 0 RM0433 Quad-SPI interface (QUADSPI) 23 Quad-SPI interface (QUADSPI) 23.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers • status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting • memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad-SPI Flash memories are accessed simultaneously. 23.2 QUADSPI main features • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two Flash memories in parallel. • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • MDMA trigger generation for FIFO threshold and transfer complete • Interrupt generation on FIFO threshold, timeout, operation complete, and access error DocID029587 Rev 3 819/3178 848 Quad-SPI interface (QUADSPI) RM0433 23.3 QUADSPI functional description 23.3.1 QUADSPI block diagram Figure 115. QUADSPI block diagram when dual-flash mode is disabled ELW $+%EXV 48$'63, 5HJLVWHUV FRQWURO &ORFN PDQDJHPHQW TXDGVSLBNHUBFN TXDGVSLBKFON TXDGVSLBLW TXDGVSLBIWBWUJ TXDGVSLBWFBWUJ ),)2 6KLIWUHJLVWHU ELW $;,EXV 63,)/$6+ &/. %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 &/. 46, 462 4:3 4+2/' &6 06Y9 Figure 116. QUADSPI block diagram when dual-flash mode is enabled 48$'63, ELW $+%EXV 5HJLVWHUV FRQWURO &ORFN PDQDJHPHQW 63,)/$6+ &/. %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 TXDGVSLBNHUBFN TXDGVSLBKFON TXDGVSLBLW TXDGVSLBIWBWUJ &/. 46, 462 4:3 4+2/' &6 TXDGVSLBWFBWUJ 63,)/$6+ 6KLIWUHJLVWHU ELW $;,EXV ),)2 %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 &/. 46, 462 4:3 4+2/' &6 06Y9 820/3178 DocID029587 Rev 3 RM0433 23.3.2 Quad-SPI interface (QUADSPI) QUADSPI pins and internal signals Table 182 lists the QUADSPI internal signals. Table 182. QUADSPI internal signals Signal name Signal type Description quadspi_ker_ck Digital input QUADSPI kernel clock quadspi_hclk Digital input QUADSPI register interface clock quadspi_it Digital output QUADSPI global interrupt quadspi_ft_trg Digital output QUADSPI FIFO threshold trigger for MDMA quadspi_tc_trg Digital output QUADSPI transfer complete trigger for MDMA Table 183 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode. Table 183. QUADSPI pins 23.3.3 Signal name Signal type Description CLK Digital output Clock to FLASH 1 and FLASH 2 BK1_IO0/SO Digital input/output Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 1 BK1_IO1/SI Digital input/output Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 1 BK1_IO2 Digital input/output Bidirectional IO in quad mode, for FLASH 1 BK1_IO3 Digital input/output Bidirectional IO in quad mode, for FLASH 1 BK2_IO0/SO Digital input/output Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 2 BK2_IO1/SI Digital input/output Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 2 BK2_IO2 Digital input/output Bidirectional IO in quad mode, for FLASH 2 BK2_IO3 Digital input/output Bidirectional IO in quad mode, for FLASH 2 BK1_nCS Digital output Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSPI is always used in dual-flash mode. BK2_nCS Digital output Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI is always used in dual-flash mode. QUADSPI Command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present. nCS falls before the start of each command and rises again after each command finishes. DocID029587 Rev 3 821/3178 848 Quad-SPI interface (QUADSPI) RM0433 Figure 117. An example of a read command in quad mode ,QVWUXFWLRQ $GGUHVV $OW 'XPP\ 'DWD Q&6 6&/. ,2 ,2 ,2 ,2 $ $ $ 0 %\WH ,2VZLWFKIURP RXWSXWWRLQSXW %\WH 069 Instruction phase During this phase, an 8-bit instruction, configured in INSTRUCTION field of QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation to be performed. Though most Flash memories can receive instructions only one bit at a time from the IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register. When IMODE = 00, the instruction phase is skipped, and the command sequence starts with the address phase, if present. Address phase In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in memory-mapped mode the address is given directly via the AXI (from the Cortex® or from a DMA). The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ADMODE[1:0] field of QUADSPI_CCR[11:10] register. When ADMODE = 00, the address phase is skipped, and the command sequence proceeds directly to the next phase, if any. Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register. The alternate-bytes phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. 822/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) When ABMODE = 00, the alternate-bytes phase is skipped, and the command sequence proceeds directly to the next phase, if any. There may be times when only a single nibble needs to be sent during the alternate-byte phase rather than a full byte, such as when dual-mode is used and only two cycles are used for the alternate bytes. In this case, firmware can use quad-mode (ABMODE = 11) and send a byte with bits 7 and 3 of ALTERNATE set to ‘1’ (keeping the IO3 line high), and bits 6 and 2 set to ‘0’ (keeping the IO2 line low). In this case the upper two bits of the nibble to be sent are placed in bits 4:3 of ALTERNATE while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE should be set to 0x8A (1000_1010). Dummy-cycles phase In the dummy-cycles phase, 1-31 cycles are given without any data being sent or received, in order to allow the Flash memory the time to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in the DCYC[4:0] field of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the duration is specified as a number of full CLK cycles. When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence proceeds directly to the data phase, if present. The operating mode of the dummy-cycles phase is determined by DMODE. In order to assure enough “turn-around” time for changing the data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the Flash memory. Data phase During the data phase, any number of bytes can be sent to, or received from the Flash memory. In indirect and automatic-polling modes, the number of bytes to be sent/received is specified in the QUADSPI_DLR register. In indirect write mode the data to be sent to the Flash memory must be written to the QUADSPI_DR register, while in indirect read mode the data received from the Flash memory is obtained by reading from the QUADSPI_DR register. In memory-mapped mode, the data which is read is sent back directly over the AXI to the Cortex or to a DMA. The data phase can send/receive 1 bit at a time (over SO/SI in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode. DocID029587 Rev 3 823/3178 848 Quad-SPI interface (QUADSPI) 23.3.4 RM0433 QUADSPI signal interface protocol modes Single SPI mode Legacy SPI mode allows just a single bit to be sent/received serially. In this mode, data is sent to the Flash memory over the SO signal (whose I/O shared with IO0). Data received from the Flash memory arrives via SI (whose I/O shared with IO1). The different phases can each be configured separately to use this single bit mode by setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01. In each phase which is configured in single mode: • IO0 (SO) is in output mode • IO1 (SI) is in input mode (high impedance) • IO2 is in output mode and forced to ‘0’ (to deactivate the “write protect” function) • IO3 is in output mode and forced to ‘1’ (to deactivate the “hold” function) This is the case even for the dummy phase if DMODE = 01. Dual SPI mode In dual SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals. The different phases can each be configured separately to use dual SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10. In each phase which is configured in dual mode: • IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases • IO2 is in output mode and forced to ‘0’ • IO3 is in output mode and forced to ‘1’ In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance. Quad SPI mode In quad SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals. The different phases can each be configured separately to use quad SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11. In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at highimpedance (input) during the data phase for read operations, and outputs in all other cases. In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance. IO2 and IO3 are used only in Quad SPI mode. If none of the phases are configured to use Quad SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions even while QUADSPI is active. SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. 824/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge. By default (when SSHIFT = 0), the signals are sampled using the following (rising) edge of CLK. DDR mode When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double data rate (DDR) mode. In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the address/alternate-byte/data phases, a bit is sent on each of the falling and rising edges of CLK. The instruction phase is not affected by DDRM. The instruction is always sent using CLK’s falling edge. When receiving data in DDR mode, the QUADSPI assumes that the Flash memories also send the data using both rising and falling CLK edges. When DDRM = 1, firmware must clear SSHIFT bit (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge). Figure 118. An example of a DDR command in quad mode ,QVWUXFWLRQ $GGUHVV $OW 'XPP\ 'DWD Q&6 6&/. ,2 ,2 ,2 ,2 $$ $ 0 %\WH%\WH ,2VZLWFKIURP RXWSXWWRLQSXW 069 Dual-flash mode When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where two external quad SPI Flash memories (FLASH 1 and FLASH 2) are used in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput as well as the capacity. Each of the Flash memories use the same CLK and optionally the same nCS signals, but each have separate IO0, IO1, IO2, and IO3 signals. Dual-flash mode can be used in conjunction with single-bit, dual-bit, and quad-bit modes, as well as with either SDR or DDR mode. The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored in FLASH 1 and bytes at odd addresses are all stored in FLASH 2. DocID029587 Rev 3 825/3178 848 Quad-SPI interface (QUADSPI) RM0433 When reading the Flash memories status registers in dual-flash mode, twice as many bytes should be read compared to doing the same read in single-flash mode. This means that if each Flash memory gives 8 valid bits after the instruction for fetching the status register, then the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the QUADSPI will receive one byte from each Flash memory. If each Flash memory gives a status of 16 bits, then the QUADSPI must be configured to read 4 bytes to get all the status bits of both Flash memories in dual-flash mode. The least-significant byte of the result (in the data register) is the least-significant byte of FLASH 1 status register, while the next byte is the least-significant byte of FLASH 2 status register. Then, the third byte of the data register is FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the Flash memories have 16-bit status registers). An even number of bytes must always be accessed in dual-flash mode. For this reason, bit 0 of the data length field (QUADSPI_DLR[0]) is stuck at 1 when DRM = 1. In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1 during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each Flash memory always receives the same instruction and the same address. Then, during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of FLASH 2. 23.3.5 QUADSPI indirect mode When in indirect mode, commands are started by writing to QUADSPI registers and data is transferred by writing or reading the data register, in the same way as for other communication peripherals. When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode, where bytes are sent to the Flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR). When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from the Flash memory during the data phase. Data are recovered by reading QUADSPI_DR. The number of bytes to be read/written is specified in the data length register (QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1’s), then the data length is considered undefined and the QUADSPI simply continues to transfer data until the end of Flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE (QUADSPI_CCR[25:24]) should be set to 00. If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4GB Flash memory), then in this special case the transfers continue indefinitely, stopping only after an abort request or after the QUADSPI is disabled. After the last memory address is read (at address 0xFFFF_FFFF), reading continues with address = 0x0000_0000. When the programmed number of bytes to be transmitted or received is reached, TCF is set and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. 826/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. Depending on the QUADSPI configuration, there are three different ways to trigger the start of a command in indirect mode. The commands starts immediately after: 1. a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is necessary (when ADMODE = 00) and if no data needs to be provided by the firmware (when FMODE = 01 or DMODE = 00) 2. a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is necessary (when ADMODE != 00) and if no data needs to be provided by the firmware (when FMODE = 01 or DMODE = 00) 3. a write is performed to DATA[31:0] (QUADSPI_DR), if an address is necessary (when ADMODE != 00) and if data needs to be provided by the firmware (when FMODE = 00 and DMODE != 00) Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start. If alternate bytes are required, they must be programmed before. As soon as a command is started, the BUSY bit (bit 5 of QUADSPI_SR) is automatically set. FIFO and data management In indirect mode, data go through a 32-byte FIFO which is internal to the QUADSPI. FLEVEL[5:0] (QUADSPI_SR[13:8]) indicates how many bytes are currently being held in the FIFO. In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte writes add only 1 byte. If firmware adds too many bytes to the FIFO (more than is indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation (when TCF is set). Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register. FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF (FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after the last byte is read from the Flash memory, regardless of the FTHRES setting. In indirect write mode, FTF is set when the number of empty bytes in the FIFO is above the threshold. If FTIE = 1, there is an interrupt when FTF is set. FTF is cleared by HW as soon as the threshold condition is no longer true (after enough data has been transferred by the CPU or DMA). In indirect read mode when the FIFO becomes full, the QUADSPI temporarily stops reading bytes from the Flash memory to avoid an overrun. Note that the reading of the Flash memory does not restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11). Thus, when FTHRES ≥ 13, the application must take care to read enough bytes to assure that the QUADSPI starts retrieving data from the Flash memory again. Otherwise, the FTF flag stays at '0' as long as 11 < FLEVEL < FTHRES. DocID029587 Rev 3 827/3178 848 Quad-SPI interface (QUADSPI) 23.3.6 RM0433 QUADSPI status flag polling mode In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value. The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. BUSY goes high at this point and stays high even between the periodic accesses. The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the Flash memory in automatic-polling mode. If the MASK[n] = 0, then bit n of the result is masked and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] (QUADSPI_PSMAR), then there is a match for bit n. If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then “AND” match mode is activated. This means status match flag (SMF) is set only when there is a match on all of the unmasked bits. If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match on any of the unmasked bits. An interrupt is called when SMF is set if SMIE = 1. If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses continue until there is an abort or the QUADSPI is disabled (EN = 0). The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated). The content of the data register is not affected by the masking used in the matching logic. The FTF status bit is set as soon as a new reading of the status is complete, and FTF is cleared as soon as the data is read. 23.3.7 QUADSPI memory-mapped mode When configured in memory-mapped mode, the external SPI device is seen as an internal memory. It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. No more than 256MB can addressed even if the Flash memory capacity is larger. If an access is made to an address outside of the range defined by FSIZE but still within the 256MB range, then a bus error is given. The effect of this error depends on the bus master that attempted the access: • If it is the Cortex® CPU, bus fault exception is generated when enabled (or a hard fault exception when bus fault is disabled) • If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled. Byte, halfword, and word access types are all supported. Support for execute in place (XIP) operation is implemented, where the QUADSPI anticipates the next microcontroller access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access will be completed faster since the value is already prefetched. 828/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled. 23.3.8 QUADSPI Free running clock mode When configured in Free running clock mode, the QUADSPI peripheral continuously outputs the clock for test and calibration purposes. Free running clock mode is entered as soon as the Free running clock mode bit (FRCM) is set in the QUADSPI communication configuration register (QUADSPI_CCR). It is exited by setting the ABORT bit of the QUADSPI control register (QUADSPI_CR). When the QUADSPI operates in Free running clock mode: 23.3.9 • the clock is running continuously, • nCS stays High (external device deselected), • data lines are released (High-Z), • the BUSY flag of the QUADSPI status register (QUADSPI_SR) is set. QUADSPI Flash memory configuration The device configuration register (QUADSPI_DCR) can be used to specify the characteristics of the external SPI Flash memory. The FSIZE[4:0] field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. When the QUADSPI executes two commands, one immediately after the other, it raises the chip select signal (nCS) high between the two commands for only one CLK cycle by default. If the Flash memory requires more time between commands, the chip select high time (CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS must remain high. The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands (when nCS = 1). 23.3.10 QUADSPI delayed data sampling By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK cycle after the Flash memory drives the signal. DocID029587 Rev 3 829/3178 848 Quad-SPI interface (QUADSPI) RM0433 In case of external signal delays, it may be beneficial to sample the data later. Using the SSHIFT bit (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of a CLK cycle. Clock shifting is not supported in DDR mode: the SSHIFT bit must be clear when DDRM bit is set. 23.3.11 QUADSPI configuration The QUADSPI configuration is done in two phases: • QUADSPI IP configuration • QUADSPI Flash memory configuration Once configured and enabled, the QUADSPI can be used in one of its three operating modes: indirect mode, status-polling mode, or memory-mapped mode. QUADSPI IP configuration The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data. DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode. FIFO level for either MDMA trigger generation or interrupt generation is programmed in the FTHRES bits. If timeout counter is needed, the TCEN bit can be set and the timeout value programmed in the QUADSPI_LPTR register. Dual-flash mode can be activated by setting DFM to 1. QUADSPI Flash memory configuration The parameters related to the targeted external Flash memory are configured through the QUADSPI_DCR register.The user shall program the Flash memory size in the FSIZE bits, the Chip Select minimum high time in the CSHT bits, and the functional mode (Mode 0 or Mode 3) in the MODE bit. 23.3.12 QUADSPI usage The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]). Indirect mode procedure When FMODE is programmed to 00, indirect write mode is selected and data can be sent to the Flash memory. With FMODE = 01, indirect read mode is selected where data can be read from the Flash memory. 830/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) When the QUADSPI is used in indirect mode, the frames are constructed in the following way: 1. Specify a number of data bytes to read or write in the QUADSPI_DLR. 2. Specify the frame format, mode and instruction code in the QUADSPI_CCR. 3. Specify optional alternate byte to be sent right after the address phase in the QUADSPI_ABR. 4. Specify the operating mode in the QUADSPI_CR. 5. Specify the targeted address in the QUADSPI_AR. 6. Read/Write the data from/to the FIFO through the QUADSPI_DR. When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • Timeout counter enable bit (TCEN) • Sample shift setting (SSHIFT) • FIFO threshold level (FTRHES) to indicate when the FTF flag should be set • Interrupt enables • Automatic polling mode parameters: match mode and stop mode (valid when FMODE = 11) • Clock prescaler When writing the communication configuration register (QUADSPI_CCR) the user specifies the following parameters: • The instruction byte through the INSTRUCTION bits • The way the instruction has to be sent through the IMODE bits (1/2/4 lines) • The way the address has to be sent through the ADMODE bits (None/1/2/4 lines) • The address size (8/16/24/32-bit) through the ADSIZE bits • The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines) • The alternate bytes number (1/2/3/4) through the ABSIZE bits • The presence or not of dummy bytes through the DBMODE bit • The number of dummy bytes through the DCYC bits • The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to be updated for a particular command, then the command sequence starts as soon as QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01). When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the address is updated with a write to QUADSPI_AR. In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is triggered by a write in the FIFO through QUADSPI_DR. DocID029587 Rev 3 831/3178 848 Quad-SPI interface (QUADSPI) RM0433 Status flag polling mode The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to 10. In this mode, the programmed frame will be sent and the data retrieved periodically. The maximum amount of data read in each frame is 4 bytes. If more data is requested in QUADSPI_DLR, it will be ignored and only 4 bytes will be read. The periodicity is specified in the QUADSPI_PISR register. Once the status data has been retrieved, it can internally be processed i order to: • set the status match flag and generate an interrupt if enabled • stop automatically the periodic retrieving of the status bytes The received value can be masked with the value stored in the QUADSPI_PSMKR and ORed or ANDed with the value stored in the QUADSPI_PSMAR. In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses. Only read operations are allowed to the external Flash memory in this mode. Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR register. The programmed instruction and frame is sent when a master is accessing the memory mapped space. The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to QUADSPI_DR in this mode returns zero. The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode. 23.3.13 Sending the instruction only once Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be sent only with the first command sequence, while subsequent commands start directly with the address. One can take advantage of such a feature using the SIOO bit (QUADSPI_CCR[28]). SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR. SIOO has no effect when IMODE = 00 (no instruction). 832/3178 DocID029587 Rev 3 RM0433 23.3.14 Quad-SPI interface (QUADSPI) QUADSPI error management An error can be generated in the following case: 23.3.15 • In indirect mode or status flag polling mode when a wrong address has been programmed in the QUADSPI_AR (according to the Flash memory size defined by FSIZE[4:0] in the QUADSPI_DCR): this will set the TEF and an interrupt is generated if enabled. • Also in indirect mode, if the address plus the data length exceeds the Flash memory size, TEF will be set as soon as the access is triggered. • In memory-mapped mode, when an out of range access is done by a master or when the QUADSPI is disabled: this will generate a bus error as a response to the faulty bus master request. • When a master is accessing the memory mapped space while the memory mapped mode is disabled: this will generate a bus error as a response to the faulty bus master request. QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty. In automatic-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1, or due to an abort. After the first access in memory-mapped mode, BUSY goes low only on a timeout event or on an abort. Any operation can be aborted by setting the ABORT bit in the QUADSPI_CR. Once the abort is completed, the BUSY bit and the ABORT bit are automatically reset, and the FIFO is flushed. Note: Some Flash memories might misbehave if a write operation to a status registers is aborted. 23.3.16 nCS behavior By default, nCS is high, deselecting the external Flash memory. nCS falls before an operation begins and rises as soon as it finishes. When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress) nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 119. Figure 119. nCS when CKMODE = 0 (T = CLK period) 7 7 Q&6 6&/. 06 9 DocID029587 Rev 3 833/3178 848 Quad-SPI interface (QUADSPI) RM0433 When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 120. Figure 120. nCS when CKMODE = 1 in SDR mode (T = CLK period) 7 7 Q&6 6&/. 069 When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 121. Because DDR operations must finish with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK cycle afterwards. Figure 121. nCS when CKMODE = 1 in DDR mode (T = CLK period) 7 7 7 Q&6 6&/. 069 When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, nCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later, as shown in Figure 122. Figure 122. nCS when CKMODE = 1 with an abort (T = CLK period) 7 &ORFNVWDOOHG 7 Q&6 6&/. $ERUW 069 834/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) When not in dual-flash mode (DFM = 0), only FLASH 1 is accessed and thus the BK2_nCS stays high. In dual-flash mode, BK2_nCS behaves exactly the same as BK1_nCS. Thus, if there is a FLASH 2 and if the application always stays in dual-flash mode, then FLASH 2 may use BK1_nCS and the pin outputting BK2_nCS can be used for other functions. 23.4 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 184. QUADSPI interrupt requests Interrupt event Event flag Enable control bit Timeout TOF TOIE Status match SMF SMIE FIFO threshold FTF FTIE Transfer complete TCF TCIE Transfer error TEF TEIE DocID029587 Rev 3 835/3178 848 Quad-SPI interface (QUADSPI) RM0433 23.5 QUADSPI registers 23.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 PRESCALER 23 22 21 20 19 18 17 16 PMM APMS Res. TOIE SMIE FTIE TCIE TEIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. FSEL DFM Res. SSHIFT TCEN Res. ABORT EN rw rw rw rw rw w1s FTHRES rw rw rw rw rw Bits 31: 24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the quadspi_ker_ck clock (value+1). 0: FCLK = Fquadspi_ker_ck, quadspi_ker_ck clock used directly as QUADSPI CLK (prescaler bypassed) 1: FCLK = Fquadspi_ker_ck/2 2: FCLK = Fquadspi_ker_ck/3 ... 255: FCLK = Fquadspi_ker_ck/256 For odd clock division factors, CLK’s duty cycle is not 50%. The clock signal remains low one cycle longer than it stays high. This field can be modified only when BUSY = 0. Bit 23 PMM: Polling match mode This bit indicates which method should be used for determining a “match” during automatic polling mode. 0: AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register. 1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register. This bit can be modified only when BUSY = 0. Bit 22 APMS: Automatic poll mode stop This bit determines if automatic polling is stopped after a match. 0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI. 1: Automatic polling mode stops as soon as there is a match. This bit can be modified only when BUSY = 0. Bit 21 Reserved, must be kept at reset value. Bit 20 TOIE: TimeOut interrupt enable This bit enables the TimeOut interrupt. 0: Interrupt disable 1: Interrupt enabled 836/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) Bit 19 SMIE: Status match interrupt enable This bit enables the status match interrupt. 0: Interrupt disable 1: Interrupt enabled Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt. 0: Interrupt disable 1: Interrupt enabled Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 FTHRES[4:0] FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): 0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO 1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO ... 31: FTF is set if there are 32 free bytes available to be written to in the FIFO In indirect read mode (FMODE = 01): 0: FTF is set if there are 1 or more valid bytes that can be read from the FIFO 1: FTF is set if there are 2 or more valid bytes that can be read from the FIFO ... 31: FTF is set if there are 32 valid bytes that can be read from the FIFO Bit 7 FSEL: Flash memory selection This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). 0: FLASH 1 selected 1: FLASH 2 selected This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1. Bit 6 DFM: Dual-flash mode This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. 0: Dual-flash mode disabled 1: Dual-flash mode enabled This bit can be modified only when BUSY = 0. Bit 5 Reserved, must be kept at reset value. DocID029587 Rev 3 837/3178 848 Quad-SPI interface (QUADSPI) RM0433 Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. 0: No shift 1: 1/2 cycle shift Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0. Bit 3 TCEN: Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. 0: Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode. 1: Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity. This bit can be modified only when BUSY = 0. Bit 2 Reserved Bit 1 ABORT: Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit. 0: No abort requested 1: Abort requested Bit 0 EN: Enable Enable the QUADSPI. 0: QUADSPI is disabled 1: QUADSPI is enabled 838/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) 23.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. CSHT rw rw Res. Res. rw Res. 20 19 18 17 16 rw FSIZE rw rw rw rw 4 3 2 1 0 Res. CKMODE Res. Res. Res. rw Bits 31: 21 Reserved, must be kept at reset value. Bits 20: 16 FSIZE[4:0]: Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. This field can be modified only when BUSY = 0. Bits 15: 11 Reserved, must be kept at reset value. Bits 10:8 CSHT[2:0]: Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. 0: nCS stays high for at least 1 cycle between Flash memory commands 1: nCS stays high for at least 2 cycles between Flash memory commands ... 7: nCS stays high for at least 8 cycles between Flash memory commands This field can be modified only when BUSY = 0. Bits 7: 1 Reserved, must be kept at reset value. Bit 0 CKMODE: Mode 0 / mode 3 This bit indicates the level that CLK takes between commands (when nCS = 1). 0: CLK must stay low while nCS is high (chip select released). This is referred to as mode 0. 1: CLK must stay high while nCS is high (chip select released). This is referred to as mode 3. This field can be modified only when BUSY = 0. DocID029587 Rev 3 839/3178 848 Quad-SPI interface (QUADSPI) 23.5.3 RM0433 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BUSY TOF SMF FTF TCF TEF r r r r r r FLEVEL[5:0] r r r r r r Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 FLEVEL[5:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero. Bits 7:6 Reserved, must be kept at reset value. Bit 5 BUSY: Busy This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty. Bit 4 TOF: Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. Bit 3 SMF: Status match flag This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF. Bit 2 FTF: FIFO threshold flag In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true. In automatic polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read. Bit 1 TCF: Transfer complete flag This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. Bit 0 TEF: Transfer error flag This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF. 840/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) 23.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF w1o w1o w1o w1o Bits 31: 5 Reserved, must be kept at reset value. Bit 4 CTOF: Clear timeout flag Writing 1 clears the TOF flag in the QUADSPI_SR register Bit 3 CSMF: Clear status match flag Writing 1 clears the SMF flag in the QUADSPI_SR register Bit 2 Reserved, must be kept at reset value. Bit 1 CTCF: Clear transfer complete flag Writing 1 clears the TCF flag in the QUADSPI_SR register Bit 0 CTEF: Clear transfer error flag Writing 1 clears the TEF flag in the QUADSPI_SR register 23.5.5 QUADSPI data length register (QUADSPI_DLR) Address offset: 0x0010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DL[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DL[15:0] rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 841/3178 848 Quad-SPI interface (QUADSPI) RM0433 Bits 31:0 DL[31: 0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE. 0x0000_0000: 1 byte is to be transferred 0x0000_0001: 2 bytes are to be transferred 0x0000_0002: 3 bytes are to be transferred 0x0000_0003: 4 bytes are to be transferred ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred 0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F. DL[0] is stuck at ‘1’ in dual-flash mode (DFM = 1) even when ‘0’ is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in memory-mapped mode (FMODE = 10). This field can be written only when BUSY = 0. 23.5.6 QUADSPI communication configuration register (QUADSPI_CCR) Address offset: 0x0014 Reset value: 0x0000 0000 31 DDRM 30 29 28 DHHC FRCM SIOO 27 26 25 FMODE[1:0] 24 DMODE rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 ABMODE rw rw ADSIZE rw rw ADMODE rw rw 23 22 21 Res. 7 rw 19 18 17 DCYC[4:0] ABSIZE rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw INSTRUCTION[7:0] rw rw rw rw rw Bit 31 DDRM: Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: 0: DDR Mode disabled 1: DDR Mode enabled This field can be written only when BUSY = 0. Bit 30 DHHC: DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: 0: Delay the data output using analog delay 1: Delay the data output by 1/4 of a QUADSPI output clock cycle. This feature is only active in DDR mode. This field can be written only when BUSY = 0. Bit 29 FRCM: Free Running Clock Mode When this bit is set, the QUADSPI peripheral enters Free running clock mode regardless of the FMODE bits. 0: Normal mode 1: Free running clock mode This bit can be written only when BUSY = 0. 842/3178 16 rw IMODE rw 20 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) Bit 28 SIOO: Send instruction only once mode See Section 23.3.13: Sending the instruction only once on page 832. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0. Bits 27:26 FMODE[1:0]: Functional mode This field defines the QUADSPI functional mode of operation. 00: Indirect write mode 01: Indirect read mode 10: Automatic polling mode 11: Memory-mapped mode This field can be written only when BUSY = 0. Bits 25:24 DMODE[1:0]: Data mode This field defines the data phase’s mode of operation: 00: No data 01: Data on a single line 10: Data on two lines 11: Data on four lines This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0. Bit 23 Reserved, must be kept at reset value. Bits 22:18 DCYC[4:0]: Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0. Bits 17:16 ABSIZE[1:0]: Alternate bytes size This bit defines alternate bytes size: 00: 8-bit alternate byte 01: 16-bit alternate bytes 10: 24-bit alternate bytes 11: 32-bit alternate bytes This field can be written only when BUSY = 0. Bits 15:14 ABMODE[1:0]: Alternate bytes mode This field defines the alternate-bytes phase mode of operation: 00: No alternate bytes 01: Alternate bytes on a single line 10: Alternate bytes on two lines 11: Alternate bytes on four lines This field can be written only when BUSY = 0. Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. DocID029587 Rev 3 843/3178 848 Quad-SPI interface (QUADSPI) RM0433 Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line 10: Address on two lines 11: Address on four lines This field can be written only when BUSY = 0. Bits 9:8 IMODE[1:0]: Instruction mode This field defines the instruction phase mode of operation: 00: No instruction 01: Instruction on a single line 10: Instruction on two lines 11: Instruction on four lines This field can be written only when BUSY = 0. Bits 7: 0 INSTRUCTION[7: 0]: Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0. 23.5.7 QUADSPI address register (QUADSPI_AR) Address offset: 0x0018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDRESS[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ADDRESS[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 ADDRESS[31 0]: Address Address to be send to the external Flash memory Writes to this field are ignored when BUSY = 0 or when FMODE = 11 (memory-mapped mode). In dual flash mode, ADDRESS[0] is automatically stuck to ‘0’ as the address should always be even 844/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) 23.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ALTERNATE[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ALTERNATE[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 ALTERNATE[31: 0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 23.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATA[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 DATA[31: 0]: Data Data to be sent/received to/from the external SPI device. In indirect write mode, data written to this register is stored on the FIFO before it is sent to the Flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In indirect read mode, reading this register gives (via the FIFO) the data which was received from the Flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In automatic polling mode, this register contains the last data read from the Flash memory (without masking). Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0]. DocID029587 Rev 3 845/3178 848 Quad-SPI interface (QUADSPI) 23.5.10 RM0433 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MASK[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MASK[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MASK[31: 0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is considered in the matching logic This field can be written only when BUSY = 0. 23.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) Address offset: 0x0028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MATCH[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MATCH[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MATCH[31: 0]: Status match Value to be compared with the masked status register to get a match. This field can be written only when BUSY = 0. 846/3178 DocID029587 Rev 3 RM0433 Quad-SPI interface (QUADSPI) 23.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INTERVAL[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 INTERVAL[15: 0]: Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0. 23.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) Address offset: 0x0030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TIMEOUT[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 TIMEOUT[15: 0]: Timeout period After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state. This field can be written only when BUSY = 0. DocID029587 Rev 3 847/3178 848 Quad-SPI interface (QUADSPI) 23.5.14 RM0433 QUADSPI register map 0 0x001C Reset value 0 0 0 0 0 0 0 0 0 0x0020 0x0024 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUADSPI_ PSMAR 0 0 EN CKMODE Res. TEF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUADSPI_PIR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MATCH[31:0] 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 INTERVAL[15:0] 0 Reset value 0 DocID029587 Rev 3 0 0 0 0 TIMEOUT[15:0] 0 0 0 Refer to Section 2.2.2 for the register boundary addresses. 848/3178 0 MASK[31:0] Reset value 0x0030 0 DATA[31:0] QUADSPI_ PSMKR QUADSPI_ LPTR ABORT 0 ALTERNATE[31:0] Res. 0x002C Res. TCF 0 ADDRESS[31:0] QUADSPI_DR Reset value 0x0028 0 DCYC[4:0] QUADSPI_ABR Reset value TCEN 0 CTEF 0 0 QUADSPI_AR 0x0018 Res. FTF 0 CTCF 0 0 IMODE[1:0] SIOO 0 0 ADMODE[1:0] FRCM Reset value 0 ADSIZE[1:0] QUADSPI_CCR 0 ABMODE[1:0] 0 ABSIZE[1:0] 0 Res. 0 DMODE[1:0] 0 FMODE[1:0] Reset value DHHC 0x0014 Res. DFM Res. Res. 0 DL[31:0] DDRM 0x0010 SSHIFT 0 Reset value QUADSPI_DLR Res. FSEL Res. Res. SMF 0 Res. 0 CSMF 0 0 TOF 0 CTOF 0 0 BUSY 0 0 Res. 0 Res. Res. Res. FLEVEL[6:0] 0 0 Res. 0 0 Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QUADSPI_FCR Res. Res. Res. 0 Reset value 0x000C CSHT Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. Res. 0 Res. Res. Res. FSIZE[4:0] 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 FTHRES [4:0] Res. Res. Res. TEIE Res. Res. 0 Res. Res. Res. Res. Res. QUADSPI_SR Res. Reset value 0x0008 0 Res. QUADSPI_DCR Res. 0x0004 0 Res. 0 FTIE 0 TCIE 0 Res. 0 SMIE 0 Res. 0 Res. 0 Res. 0 TOIE 0 PRESCALER[7:0] Res. 0 QUADSPI_CR 0x0000 Res. PMM APMS Reset value Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 185. QUADSPI register map and reset values Register name 0 0 0 0 0 0 RM0433 Delay block (DLYB) 24 Delay block (DLYB) 24.1 Introduction The delay block (DLYB) is used to generate an output clock which is dephased from the input clock. The phase of the output clock must be programmed by the user application. The output clock is then used to clock the data received by another peripheral such as an SDMMC or QUADSPI interface. The delay is voltage- and temperature-dependent, which may require the application to reconfigure and recenter the output clock phase with the receive data. 24.2 DLYB main features The delay block has the following features: • Input clock frequency ranging from 25 to 208 MHz • Up to 12 oversampling phases. 24.3 DLYB functional description 24.3.1 DLYB diagram The delay block includes of the following sub-blocks: • Register interface block providing AHB access to the Delay Block registers. • Delay line supporting the unit delays. • Delay line length sampling • Output clock selection multiplexer 'HOD\EORFN '/<% GO\EBKFON 5(*,67(5 ,17(5)$&( '(/$</,1( 8QLW 'HOD\ GO\EBLQBFN 8QLW 'HOD\ 8QLW 'HOD\ 81,7 8QLW 'HOD\ 8QLW 'HOD\ '(1 6$03/(5 6(1 /(1*7+ ELW$+%EXV Figure 123. DLYB block diagram GO\EBRXWBFN 08; /1* /1*) 6(/ &/2&.28708; 06Y9 DocID029587 Rev 3 849/3178 853 Delay block (DLYB) 24.3.2 RM0433 DLYB pins and internal signals Table 186 lists the DLYB internal signals. Table 186. DLYB internal input/output signals 24.3.3 Signal name Signal type Description dlyb_hclk Digital input Delay block register interface clock dlyb_in_ck Digital input Delay block input clock dlyb_out_ck Digital output Delay block output clock General description The delay block is enabled by setting the DEN bit in the DLYB_CR register (see Section 24.4.1: DLYB control register (DLYB_CR)). The length sampler is enabled through the SEN bit in DLYB_CR register. When the delay block is enabled, the delay added by a unit delay is defined by the UNIT bits in DLYB_CFGR register (see Section 24.4.2: DLYB configuration register (DLYB_CFGR)). Note that the UNIT bits can be programmed only when the output clock is disabled (SEN = ‘1’). When the delay block is enabled, the output clock phase is selected through the SEL bit in DLYB_CFGR register. Note that SEL can be programmed only when the output clock is disabled (SEN = ‘1’). Before dephasing the output clock, the delay line length shall be configured to one input clock period. The delay line length can be configured by enabling the length sampler through the SEN bit, which gives access to the delay line length (LNG bits) and Length valid flag (LNGF) in DLYB_CFGR. Once the delay line length has been configured, a dephased output clock can be selected by the output clock multiplexer. This is done through SEL bits. The output clock is only available on the selected phase when SEN is set to ‘0’. Table 187. gives a summary of the delay block control. Table 187. Delay block control DEN SEN UNIT SEL LNG LNGF Output clock Don’t care Don’t care Enabled (= Input clock) 0 0 Don’t care Don’t care x 1 Unit delay Output clock phase 1 0 Unit delay(1) Output clock phase(2) Length Length flag Don’t care 1. The unit delay can only be changed when SEN = ‘1’. 2. The output clock phase can only be changed when SEN = ‘1’. 850/3178 DocID029587 Rev 3 Don’t care Disabled Enabled (= selected phase) RM0433 24.3.4 Delay block (DLYB) Delay line length configuration procedure LNG bits are used to determine the delay line length with respect to the input clock period. The length shall be configured so that one full input clock period is covered by the delay line length. To configure the delay line length to one period of the Input clock, follow the sequence below: 1. Enable the delay block by setting DEN bit to ‘1’. 2. Enable the length sampling by setting SEN bit to ‘1’. 3. Enable all delay cells by setting SEL bits to 12. 4. For UNIT = 0 to 127 (this step must be repeated until the delay line length is configured): a) Update the UNIT value and wait till the length flag LNGF is set to ‘1’. b) Read LNG bits. If (LNG[10:0] > 0) and (LNG[11] or LNG[10] = 0), the delay line length is configured to one input clock period. 5. Determine how many unit delays (N) span one input clock period. – For N = 10 to 0: If LNG[N] = ‘1’, the number of unit delays spanning the input clock period = N. 6. 24.3.5 Disable the length sampling by clearing SEN to ‘0’. Output clock phase configuration procedure When the delay line length is configured to one input clock period, the output clock phase can be selected between the unit delays spanning one Input clock period. Follow the steps below to select the output clock phase: 1. Disable the output clock and enable the access to the phase selection SEL bits by setting SEN bit to ‘1’. 2. Program SEL bits with the desired output clock phase value. 3. Enable the output clock on the selected phase by clearing SEN to ‘0’. DocID029587 Rev 3 851/3178 853 Delay block (DLYB) 24.4 RM0433 DLYB registers All registers can be accessed in word, half-word and byte access. 24.4.1 DLYB control register (DLYB_CR) Address offset: 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SEN DEN Reset value: 0x0000 0000 rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 SEN: Sampler length enable bit 0: Sampler length and register access to UNIT and SEL disabled, output clock enabled. 1: Sampler length and register access to UNIT and SEL enabled, output clock disabled. Bit 0 DEN: Delay block enable bit 0: Delay block disabled. 1: Delay block enabled. 24.4.2 DLYB configuration register (DLYB_CFGR) Address offset: 0x004 31 30 29 28 LNGF Reset value: 0x0000 0000 Res. Res. Res. r 15 14 13 12 Res. 26 rw rw 25 24 23 22 21 20 19 18 17 16 r r r r r r 3 2 1 0 rw rw LNG r r r r 11 10 9 8 UNIT rw 852/3178 27 rw r r 7 6 5 4 Res. Res. Res. Res. rw DocID029587 Rev 3 SEL rw rw RM0433 Delay block (DLYB) Bit 31 LNGF: Length valid flag This flag indicates when the delay line length value contained in LNG bits is valid after UNIT bits changed. 0: Length value in LNG is not valid. 1: Length value in LNG is valid. Bits 30:28 Reserved, must be kept at reset value. Bits 27:16 LNG: Delay line length value These bits reflect the 12 unit delay values sampled at the rising edge of the input clock. The value is only valid when LNGF = ‘1’. Bit 15 Reserved, must be kept at reset value. Bits 14:8 UNIT: Delay Defines the delay of a Unit delay cell. These bits can only be written when SEN = ‘1’. Unit delay = Initial delay + UNIT x delay step Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 SEL: Select the phase for the Output clock. These bits can only be written when SEN = ‘1’. Output clock phase = Input clock + SEL x Unit delay 24.4.3 DLYB register map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res Res Res UNIT Res LNG Res 0 Res Reset value Res DLYB_CFGR Res 0x004 Res. SEN DEN 0 0 LNGF Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DLYB_CR Res. 0x000 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 188. DLYB register map and reset values SEL 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 853/3178 853 Analog-to-digital converters (ADC) RM0433 25 Analog-to-digital converters (ADC) 25.1 Introduction This section describes the implementation of up to 3 ADCs • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). • ADC3 is instantiated separately. Each ADC consists of a 16-bit successive approximation analog-to-digital converter. Each ADC has up to 20 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 32-bit data register. The ADCs are mapped on the AHB bus to allow fast data handling. The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined high or low thresholds. A built-in hardware oversampler allows to improve analog performances while off-loading the related computational burden from the CPU. An efficient low-power mode is implemented to allow very low consumption at low frequency. 854/3178 DocID029587 Rev 3 RM0433 25.2 Analog-to-digital converters (ADC) ADC main features • • • • • • • High-performance features – Up to 2x ADCs which can operate in dual mode – 16, 14, 12, 10 or 8-bit configurable resolution – ADC conversion time is independent from the AHB bus clock frequency – Faster conversion time by lowering resolution – Can manage Single-ended or differential inputs (programmable per channels) – AHB slave bus interface to allow fast data handling – Self-calibration (both offset and linearity) – Channel-wise programmable sampling time – Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable) – Hardware assistant to prepare the context of the injected channels to allow fast context switching – Data alignment with in-built data coherency – Data can be managed by GP-DMA for regular channel conversions with FIFO – Data can be routed to DFSDM for post processing – 4 dedicated data registers for the injected channels Oversampler – 32-bit data register – Oversampling ratio adjustable from 2 to 1024x – Programmable data right and left shift Low-power features – Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency – Allows slow bus frequency application while keeping optimum ADC performance – Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application (auto-delayed mode) Each ADC features an external analog input channel – Up to 6 fast channels from dedicated GPIO pads – Up to 14 slow channels from dedicated GPIO pads In addition, there are 5 internal dedicated channels – The internal reference voltage (VREFINT), connected to ADC3 – The internal temperature sensor (VSENSE), connected to ADC3 – The VBAT monitoring channel (VBAT/4), connected to ADC3 – The internal DAC channel 1 and channel 2, connected to ADC2 Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions Conversion modes – Each ADC can convert a single channel or can scan a sequence of channels DocID029587 Rev 3 855/3178 979 Analog-to-digital converters (ADC) RM0433 – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode • Dual ADC mode for ADC1 and 2 • Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or 3 or overrun events • 3 analog watchdogs per ADC • ADC input range: VREF– ≤ VIN ≤ VREF+ Figure 124 shows the block diagram of one ADC. 856/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.3 ADC functional description 25.3.1 ADC block diagram Figure 124 shows the ADC block diagram and Table 190 gives the ADC pin description. Figure 124. ADC block diagram 95() WR9 $QDORJ6XSSO\ 9''$ 9WR9 %2267 5'$7$> @ '((33:' -$872 7RLQWHUQDOGLJLWDOFLUFXLW -/> @-64[ /> @64[ $'95(*(1 &217 -'$7$> @ -'$7$> @ -'$7$> @ -'$7$> @ 5(* ',)6(/> @ 9,17'$&[ 96(16( 95(),17 9%$7 $'&[B,13> @ $'&[B,11> @ 9,13> @ ,QSXW 9,11> @ 95() $'(1$'',6 $'&$/ $'&$/',) VODYH $+% LQWHUIDFH $+% LQWHUIDFH DGFBGPD 75296 2966> @ /,1&$/5' <: &$/)$&7B' > @ &$/)$&7B6 > @ /,1&$/)$&7 > @ $'67$57 VWDUWFRQY $'673 VWRSFRQY DGFBH[WBWUJ DGFBH[WBWUJ DGFBH[WBWUJ DGFBH[WBWUJ 265> @ 29502' RYHUUXQPRGH -296( $/,*1 OHIWULJKW 5(6> @ ELWV 2))6(7\> @ 2))6(7\B&+> @ KZ WULJJHU (;7(1> @ WULJJHUHQDEOH DQGHGJHVHOHFWLRQ (;7LPDSSHGDW SURGXFWOHYHO -$'67$57 -$'673 DGFBNHUBFN DGFBKFON VWDUW 6:WULJJHU ')6'0 52960 6WDUW 6WRS &RQWURO $87'/< DXWRGHOD\HG '01*7> @ '$0')> @ 6$5$'& &219(57(' '$7$ %2267 PDVWHU 2YHUVDPSOHU 9,1 603[> @ VDPSOLQJWLPH DGFBLW %LDV 5HI VHOHFWLRQ VFDQFRQWURO DQDORJLQSXW FKDQQHOV $'5'< (2603 (2& (26 295 -(2& -(26 -429) $:'[ $+% 3&6(/ > @ 5296( 56+,)7 /6+,)7> @ 2YHUVDPSOLQJ RSWLRQV 66$7( ',6&(1 ',6&18> @ 'LVFRQWLQXRXV PRGH $QDORJZDWFKGRJ $:' $:' $:' (;76(/> @ WULJJHUVHOHFWLRQ DGFBDZG DGFBDZG DGFBDZG 6:WULJJHU $:'(1 -$:'(1 DGFBMH[WBWUJ DGFBMH[WBWUJ DGFBMH[WBWUJ DGFBMH[WBWUJ +: WULJJHU -(;7(1> @ WULJJHUHQDEOH DQGHGJHVHOHFWLRQ -(;7LPDSSHGDW SURGXFWOHYHO -(;76(/> @ WULJJHUVHOHFWLRQ $:'6*/ $:'&+> @ -',6&(1 -',6&180> @ /75> @ -4',6 +75> @ -40 ,QMFHG&RQWH[W $:'&+> @ 4XHXH0RGH /75> @ +75> @ $:'&+> @ /75> @ +75> @ 2QO\$'&DQG$'& 06Y9 DocID029587 Rev 3 857/3178 979 Analog-to-digital converters (ADC) 25.3.2 RM0433 ADC pins and internal signals Table 189. ADC internal input/output signals Internal signal name adc_ext_trg[20:0] adc_jext_trg[20:0] Signal type Description Inputs Up to 21 external trigger inputs for the regular conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave. Inputs Up to 21 external trigger inputs for the injected conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave. adc_awd1 adc_awd2 adc_awd3 Outputs Internal analog watchdog output signal connected to on-chip timers. (x = Analog watchdog number 1,2,3) VSENSE Analog input Output voltage from internal temperature sensor VREFINT Analog input Output voltage from internal reference voltage VBAT Analog input External battery voltage supply voltage adc_it Output ADC interrupt adc_hclk Input AHB clock adc_ker_ck Input ADC kernel clock adc_dma Output ADC DMA requests Table 190. ADC input/output pins Name 858/3178 Signal type Comments VREF+ Input, analog reference positive The higher/positive reference voltage for the ADC, 1.62 V ≤ VREF+ ≤ VDDA VDDA Input, analog supply Analog power supply equal VDDA: 1.62 V ≤ VDDA ≤ 3.6 V VREF- Input, analog reference negative The lower/negative reference voltage for the ADC, VREF- = VSSA VSSA Input, analog supply ground Ground for analog power supply equal to VSS VINP[19:0] Positive input analog channels for each ADC Connected either to external channels: ADCx_INPi or internal channels. VINN[19:0] Negative input analog channels for each ADC Connected to VREF- or external channels: ADCx_INNi DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Table 190. ADC input/output pins (continued) Name Signal type ADCx_INP[19:0] External analog input signals ADCx_INN[19:0] PCSEL[19:0] 25.3.3 Comments Up to 20 analog input channels (x = ADC number= 1 to 3): – ADCx_INP[0:5] fast channels – ADCx_INP[6:19] slow channels Up to 20 analog input channels (x = ADC number= 1 to 3): – ADCx_INN[0:5] fast channels – ADCx_INN[6:19] slow channels Output, channel preselection Connected to GPIO to select the channel in control signal advance Clocks Dual clock domain architecture The dual clock-domain architecture means that the ADCs clock is independent from the AHB bus clock. The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 125: ADC clock scheme): 1. The ADC clock can be a specific clock source, named adc_ker_ck which is independent and asynchronous with the AHB clock. It can be configured in the RCC (refer to RCC Section for more information on how to generate the ADC clock (adc_ker_ck) dedicated clock). To select this scheme, CKMODE[1:0] bits of the ADCx_CCR register must be reset. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]). To select this scheme, CKMODE[1:0] bits of the ADCx_CCR register must be different from “00”. Note: For option b), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register). Option a) has the advantage of reaching the maximum ADC clock frequency whatever the AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio: 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in the ADCx_CCR register. Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains). The clock configured through CKMODE[1:0] bits must be compliant with the operating frequency specified in the product datasheet. DocID029587 Rev 3 859/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 125. ADC clock scheme 5&& 5HVHWDQG FORFN FRQWUROOHU $'&$'&RU$'& DGFBKFON $+%LQWHUIDFH %LWV&.02'(> @ RI$'&[B&&5 $QDORJ$'&RU$'& PDVWHU RURU DGFBNHUBFN %LWV35(&> @ RI$'&[B&&5 2WKHUV $QDORJ$'& VODYH %LWV&.02'(> @ RI$'&[B&&5 06Y9 1. Refer to the RCC section to see how adc_hclk and adc_ker_ck can be generated. Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio: • FHCLK >= FADC / 4 if the resolution of all channels are 16-bit, 14-bit,12-bit or 10-bit • FHCLK >= FADC / 3 if there are some channels with resolutions equal to 8-bit (and none with lower resolutions) BOOST bit control There is ADC boost control bit BOOST in the ADCx_CR register. This bit must be set when ADC clock is more than 20 MHz. When ADC clock is less than 20 MHz, this bit can be cleared to save power. 860/3178 DocID029587 Rev 3 RM0433 25.3.4 Analog-to-digital converters (ADC) ADC1/2/3 connectivity ADC1 and ADC2 are tightly coupled and share some external channels as described in the following figures. ADC3 is instantiated separately, but some inputs are shared with ADC1 and ADC2. Figure 126. ADC1 connectivity $'& $'&B,13 $'&B,11 966$ $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ 966$ 966$ 966$ $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ $'&B,13 966$ $'&B,13 966$ $'&B,13 $'&B,13 $'&B,11 966$ $'&B,13 $'&B,13 $'&B,11 966$ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13> @ 9,11> @ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13> @ 9,11> @ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95() 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 06Y9 1. ADCx_INNy signal can only be used when the corresponding ADC input channel is configured as differential mode. DocID029587 Rev 3 861/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 127. ADC2 connectivity $'& $'&B,13 $'&B,11 966$ $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ 966$ 966$ 966$ $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ $'&B,13 966$ $'&B,13 966$ '$&BLQW 966$ '$&BLQW 966$ $'&B,13 $'&B,13 $'&B,11 966$ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13> @ 9,11> @ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13> @ 9,11> @ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95() 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 06Y 9 1. ADCx_INNy signal can only be used when the corresponding ADC input channel is configured as differential mode. 862/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 128. ADC3 connectivity $'& $'&B,13 $'&B,11 966$ $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ 966$ 966$ 966$ $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ $'&B,13 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 966$ 9%$7 966$ 96(16( 966$ 95(),17 966$ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13> @ 9,11> @ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13> @ 9,11> @ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95() 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 06Y9 1. ADCx_INNy signal can only be used when the corresponding ADC input channel is configured as differential mode. DocID029587 Rev 3 863/3178 979 Analog-to-digital converters (ADC) 25.3.5 RM0433 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors. 25.3.6 ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN) By default, the ADC is in deep-power-down mode where its supply is internally switched off to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADCx_CR register). To start ADC operations, it is first needed to exit deep-power-down mode by clearing bit DEEPPWD=0. Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit ADVREGEN=1 into ADCx_CR register. The software must wait for the startup time of the ADC voltage regulator (TADCVREG_STUP) before launching a calibration or enabling the ADC. This delay must be implemented by software. For the startup time of the ADC voltage regulator, please refer to device datasheet for TADCVREG_STUP parameter. After ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to save power by also disabling the ADC voltage regulator. This is done by writing bit ADVREGEN=0. Then, to save more power by reducing the leakage currents, it is also possible to re-enter in ADC deep-power-down mode by setting bit DEEPPWD=1 into ADCx_CR register. This is particularly interesting before entering STOP mode. Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN is automatically cleared. Note: When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog calibration is kept. In ADC deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it is necessary to either relaunch a calibration or re-apply the calibration factor which was previously saved (refer to Section 25.3.8: Calibration (ADCAL, ADCALDIF, ADCALLIN, ADCx_CALFACT)). 864/3178 DocID029587 Rev 3 RM0433 25.3.7 Analog-to-digital converters (ADC) Single-ended and differential input channels Channels can be configured to be either single-ended input or differential input by writing into bits DIFSEL[19:0] in the ADCx_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). In single-ended input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage VINP[i] (positive input) and VREF- (negative input). In differential input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage VINP[i] (positive input) and VINN[i] (negative input). The output data for the differential mode is an unsigned data. When VINP[i] is VREF-, VINN[i] is VREF+, the output data is 0x0000 (16-bit resolution mode), when VINP[i] is VREF+, VINN[i] is VREF-, the output data is 0xFFFF. V INP – V INN ADC_Full_Scale Converted value = -------------------------------------------- × 1 + -----------------------------------2 V REF+ When ADC is configured as differential mode, both input should be biased at VREF+ / 2 voltage. The input signal are supposed to be differential (common mode voltage should be fixed). For a complete description of how the input channels are connected for each ADC, refer to Figure 126: ADC1 connectivity to Figure 128: ADC3 connectivity. Caution: When configuring the channel “i” in differential input mode, its negative input voltage is connected to VINN[i]. As a consequence, channel “i+n”, which is connected to VINN[i], should not be converted at same time by different ADCs. Some channels are shared between ADC1/ADC2: this can make the channel on the other ADC unusable. 25.3.8 Calibration (ADCAL, ADCALDIF, ADCALLIN, ADCx_CALFACT) Each ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 11-bits of offset or 160-bits of linearity and which is applied internally to the ADC until the next ADC power-off. During the calibration procedure, the application must not use the ADC and must wait until calibration is complete. Calibration is preliminary to any ADC operation. It removes the systematic errors which may vary from chip to chip and allows to compensate offset and linearity deviation. The calibration factor for the offset to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions: • Write ADCALDIF=0 before launching a calibration which will be applied for singleended input conversions. • Write ADCALDIF=1 before launching a calibration which will be applied for differential input conversions. DocID029587 Rev 3 865/3178 979 Analog-to-digital converters (ADC) RM0433 The linearity correction must be done once only, regardless of single / differential configuration. • Write ADCALLIN=1 before launching a calibration which will run the linearity calibration same time as the offset calibration. • Write ADCALLIN=0 before launching a calibration which will not run the linearity calibration but only the offset calibration. The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. At this time, the associated calibration factor is stored internally in the analog ADC and also in the bits CALFACT_S[10:0] or CALFACT_D[10:0] of ADCx_CALFACT register (depending on single-ended or differential input calibration). The 160-bit linearity calibration factor can be accessed using the ADCx_CALFACT2 register with ADEN set to 1. The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC. The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADCx_CALFACT and ADCx_CALFACT2 register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration. The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor will automatically be injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. It is recommended to recalibrate when VREF+ voltage changed more than 10%. The calibration requires 131,072 ADC clock cycle for the linear calibration and 520 ADC clock cycle for the offset calibration. Software procedure to calibrate the ADC 866/3178 1. Ensure DEEPPWD=0, ADVREGEN=1 and check that the ADC voltage regulator startup time has elapsed. 2. Ensure that ADEN=0. 3. Select the input mode for this calibration by setting ADCALDIF=0 (Single-ended input) or ADCALDIF=1 (Differential input). Select if Linearity calibration enable or not by ADCALLIN=1(enabled) or ADCALLIN=0(disabled). 4. Set ADCAL=1. 5. Wait until ADCAL=0. 6. The offset calibration factor can be read from ADCx_CALFACT register. 7. The linearity calibration factor can be read from ADCx_CALFACT2 register, following the procedure described in Section : Linearity calibration reading procedure (ADEN must be set to 1 prior to accessing ADCx_CALFACT2 register). DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 129. ADC calibration $'&$/',) 6LQJOHHQGHGLQSXW 'LIIHUHQWLDOLQSXW $'&$//,1 /LQHDUFDOLEUDULRQGLVDEOH /LQHDUFDOLEUDWLRQHQDEOH W&$% $'&$/ $'&6WDWH 2)) 6WDUWXS 2)) &DOLEUDWH &$/)$&7B[> @ &DOLEUDWLRQIDFWRU [ /,1&$/)$&7 > @ &DOLEUDWLRQIDFWRU [ E\6: E\+: ,QGLFDWLYHWLPLQJV 06Y9 Software procedure to re-inject a calibration factor into the ADC 1. Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing). 2. Write CALFACT_S and CALFACT_D with the new offset calibration factors. 3. Write LINCALFACT bits with the new linearity calibration factors, following the procedure described in Section : Linearity calibration writing procedure. 4. When a conversion is launched, the calibration factor will be injected into the analog ADC only if the internal analog calibration factor differs from the one stored in bits CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel. Figure 130. Updating the ADC offset calibration factor $'&VWDWH 5HDG\ QRWFRQYHUWLQJ &RQYHUWLQJFKDQQHO 6LQJOHHQGHG 5HDG\ &RQYHUWLQJFKDQQHO 6LQJOHHQGHG 8SGDWLQJFDOLEUDWLRQ ,QWHUQDO FDOLEUDWLRQIDFWRU> @ ) ) 6WDUWFRQYHUVLRQ KDUGZDUHRUVRIZDUH :5,7( $'&B&$/)$&7 &$/)$&7B6> @ E\VZ ) E\KZ 06Y9 DocID029587 Rev 3 867/3178 979 Analog-to-digital converters (ADC) RM0433 Converting single-ended and differential analog inputs with a single ADC If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following: 1. Disable the ADC. 2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0) and Linearity calibration enable (with ADCALLIN=1). This updates the registers CALFACT_S[10:0] and LINCALFACT[159:0]. 3. Calibrate the ADC in Differential input modes (with ADCALDIF=1) and Linearity calibration disable (with ADCALLIN=0). This updates the register CALFACT_D[10:0]. 4. Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration will automatically be injected into the analog ADC. Figure 131. Mixing single-ended and differential channels 7ULJJHUHYHQW $'&VWDWH 5'< &219&+ 6LQJOHHQGHG LQSXWVFKDQQHO ,QWHUQDOFDOLEUDWLRQ IDFWRU> @ ) &$/)$&7B6> @ ) &$/)$&7B'> @ ) 5'< &219&+ 5'< &219&+ 5'< 'LIIHUHQWLDO LQSXWVFKDQQHO ) 'LIIHUHQWLDO LQSXWVFKDQQHO &219&+ 6LQJOHLQSXWV FKDQQHO ) 06Y9 Linearity calibration reading procedure Once the calibration is done (ADCAL bit cleared by hardware) with ADCALLIN=1, the 160bit linearity correction factor can be read using the ADCx_CALFACT2 30-bit registers (6 read accesses are necessary). The six LINCALRDYW1..6 control/status bits in ADCx_CR are set when the calibration is complete. When ADEN is set to 1, clearing one of these bits launches the transfer of part of the linearity factor into the LINCALFACT[29:0] of the ADCx_CALFACT2 register. The bit will be reset by hardware when the ADCx_CALFACT2 register can be read (software must poll the bit until it is cleared). The complete procedure is as following: 868/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 1. Ensure DEEPPWD=0, ADVREGEN=1 and that the ADC voltage regulator startup time has elapsed. 2. Set ADEN = 1 and wait until ADRDY=1. 3. Clear LINCALRDYW6 bit (Linearity calibration ready Word 6). 4. Poll LINCALRDYW6 bit until returned value is zero, indicating linearity correction bits[159:150] are available in ADCx_CALFACT2[29:0]. 5. Read ADCx_CALFACT2[29:0]. 6. Clear LINCALRDYW5 bit. 7. Poll LINCALRDYW5 bit until returned value is zero, indicating linearity correction bits[149:120] are available in ADCx_CALFACT2[29:0]. 8. Read ADCx_CALFACT2[29:0]. 9. Clear LINCALRDYW4 bit. 10. Poll LINCALRDYW4 bit until returned value is zero, indicating linearity correction bits[119:90] are available in ADCx_CALFACT2[29:0]. 11. Read ADCx_CALFACT2[29:0]. 12. Clear LINCALRDYW3 bit. 13. Poll LINCALRDYW3 bit until returned value is zero, indicating linearity correction bits[89:60] are available in ADCx_CALFACT2[29:0]. 14. Read ADCx_CALFACT2[29:0]. 15. Clear LINCALRDYW2 bit. 16. Poll LINCALRDYW2 bit until returned value is zero, indicating linearity correction bits[59:30] are available in ADCx_CALFACT2[29:0]. 17. Read ADCx_CALFACT2[29:0]. 18. Clear LINCALRDYW1 bit. 19. Poll LINCALRDYW1 bit until returned value is zero, indicating linearity correction bits[29:0] are available in ADCx_CALFACT2[29:0]. 20. Read ADCx_CALFACT2[29:0]. Note: The software is allowed to toggle a single LINCALRDYWx bit at once (other bits left unchanged), otherwise causing unexpected behavior. The software can access the linearity calibration factor by writing LINCALRDYW1..6 bits only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing). DocID029587 Rev 3 869/3178 979 Analog-to-digital converters (ADC) RM0433 Linearity calibration writing procedure The six LINCALRDYW1..6 control/status bits in ADCx_CR are reset when the calibration has not yet been done or a new linearity calibration factor have been rewritten. It is possible to force directly a linearity calibration factor or re-inject it using the following procedure: 1. Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has elapsed. 2. Set ADEN = 1 and wait until ADRDY=1. 3. Write ADCx_CALFACT2[9:0] with previously saved linearity correction factor bits[159:150]. 4. Set LINCALRDYW6 bit. 5. Poll LINCALRDYW6 bit until returned value is one, indicating linearity correction bits[159:150] have been effectively written. 6. Write ADCx_CALFACT2[29:0] with previously saved linearity correction factor bits[149:120]. 7. Set LINCALRDYW5 bit. 8. Poll LINCALRDYW5 bit until returned value is one, indicating linearity correction bits[149:120] have been effectively written. 9. Write ADCx_CALFACT2[29:0] with previously saved linearity correction factor bits[119:90]. 10. Set LINCALRDYW4 bit. 11. Poll LINCALRDYW4 bit until returned value is one, indicating linearity correction bits[119:90] have been effectively written. 12. Write ADCx_CALFACT2[29:0] with previously saved linearity correction factor bits[89:60]. 13. Set LINCALRDYW3 bit. 14. Poll LINCALRDYW3 bit until returned value is one, indicating linearity correction bits[89:60] have been effectively written. 15. Write ADCx_CALFACT2[29:0] with previously saved linearity correction factor bits[59:30]. 16. Set LINCALRDYW2 bit. 17. Poll LINCALRDYW2 bit until returned value is one, indicating linearity correction bits[59:30] have been effectively written. 18. Write ADCx_CALFACT2[29:0] with previously saved linearity correction factor bits[29:0]. 19. Set LINCALRDYW1 bit. 20. Poll LINCALRDYW1 bit until returned value is one, indicating linearity correction bits[29:0] have been effectively written. Note: The software is allowed to toggle a single LINCALRDYWx bit at once (other bits left unchanged), otherwise causing unexpected behavior. The software is allowed to update the linearity calibration factor by writing LINCALRDYW1..6 bits only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing). 870/3178 DocID029587 Rev 3 RM0433 25.3.9 Analog-to-digital converters (ADC) ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 25.3.6: ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of tSTAB before it starts converting accurately, as shown in Figure 132. Two control bits enable or disable the ADC: • ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation. • ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled. Regular conversion can then start either by setting ADSTART=1 (refer to Section 25.3.19: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)) or when an external trigger event occurs, if triggers are enabled. Injected conversions start by setting JADSTART=1 or when an external injected trigger event occurs, if injected triggers are enabled. Software procedure to enable the ADC 1. Clear the ADRDY bit in the ADCx_ISR register by writing ‘1’. 2. Set ADEN=1. 3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE=1). 4. Clear the ADRDY bit in the ADCx_ISR register by writing ‘1’ (optional). Software procedure to disable the ADC 1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0. 2. Set ADDIS=1. 3. If required by the application, wait until ADEN=0, until the analog ADC is effectively disabled (ADDIS will automatically be reset once ADEN=0). Figure 132. Enabling / Disabling the ADC $'(1 W67$% $'5'< $'',6 $'& VWDWH E\6: 2)) 6WDUWXS 5'< &RQYHUWLQJ&+ E\+: 5'< 5(4 2) 2)) 06Y9 DocID029587 Rev 3 871/3178 979 Analog-to-digital converters (ADC) 25.3.10 RM0433 Constraints when writing the ADC control bits The software can write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the control bits DIFSEL in the ADCx_DIFSEL register, ADCx_CCR register and the control bits ADCAL and ADEN in the ADCx_CR register, only if the ADC is disabled (ADEN must be equal to 0). The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of the ADCx_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN must be equal to 1 and ADDIS to 0). For all the other control bits of the ADCx_CFGR, ADCx_SMPRy, ADCx_TRy, ADCx_SQRy, ADCx_JDRy, ADCx_OFRy and ADCx_IER registers: • For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion ongoing (ADSTART must be equal to 0). • For control bits related to configuration of injected conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no injected conversion ongoing (JADSTART must be equal to 0). The software can write ADSTP or JADSTP control bits in the ADCx_CR register only if the ADC is enabled and eventually converting and if there is no pending request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0). The software can write the register ADCx_JSQR at any time, when the ADC is enabled (ADEN=1). Note: There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN=0 as well as all the bits of ADCx_CR register). 25.3.11 Channel selection (SQRx, JSQRx) There are up to 20 multiplexed channels per ADC: • 6 fast analog inputs coming from Analog PADs and GPIO pads (ADCx_INP/INN[0..5]) • Up to 14 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6..19]). • The ADCs are connected to 5 internal analog inputs: – the internal temperature sensor (VSENSE) is connected to ADC3_INP/INN18 – the internal reference voltage (VREFINT) is connected to ADC3_INP/INN19 – the VBAT monitoring channel (VBAT/4) is connected to ADC3_INP/INN17 – DAC internal channel 1, connected to ADC2_INP/INN16 – DAC internal channel 2, connected to ADC2_INP/INN17 It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN0, ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15. • 872/3178 A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADCx_SQRy registers. The DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) total number of conversions in the regular group must be written in the L[3:0] bits in the ADCx_SQR1 register. • An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADCx_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADCx_JSQR register. ADCx_SQRy registers must not be modified while regular conversions can occur. For this, the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to Section 25.3.18: Stopping an ongoing conversion (ADSTP, JADSTP)). It is possible to modify the ADCx_JSQR registers on-the-fly while injected conversions are occurring. Refer to Section 25.3.22: Queue of context for injected conversions Temperature sensor, VREFINT and VBAT internal channels The temperature sensor VSENSE is connected to channel ADC3 VINP[18. The internal reference voltage VREFINT is connected to ADC3 VINP[19]. The VBAT channel is connected to channel ADC3 VINP[17]. Note: To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, VSENSEEN or VBATEN in the ADCx_CCR registers. 25.3.12 Channel preselection register (ADCx_PCSEL) For each channel selected through SQRx or JSQRx, the corresponding ADCx_PCSEL bit must be previously configured. This ADCx_PCSEL bit controls the transmission gate integrated in the IO level. The ADC input MUX selects the ADC input according to the SQRx and JSQRx with very high speed, the transmission gate integrated in the IO cannot react as fast as ADC mux do. To avoid the delay on transmission gate control on IO, it is necessary to pre select the input channels which will be selected in the SQRx, JSQRx. The selection is based on the VINP[i] of the each ADC input. If ADC1 will convert the ADC123_INP2(VINP[2]) as differential mode, ADC123_INP6(VINP[6]) also need to be selected in ADCx_PCSEL. Some ADC input are connected several VINP[i] of the ADCx. Those input are ORed by ADCx_PCSEL register bits. 25.3.13 Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level. DocID029587 Rev 3 873/3178 979 Analog-to-digital converters (ADC) RM0433 Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADCx_SMPR1 and ADCx_SMPR2 registers. It is therefore possible to select among the following sampling time values: • SMP = 000: 1.5 ADC clock cycles • SMP = 001: 2.5 ADC clock cycles • SMP = 010: 8.5 ADC clock cycles • SMP = 011: 16.5 ADC clock cycles • SMP = 100: 32.5 ADC clock cycles • SMP = 101: 64.5 ADC clock cycles • SMP = 110: 387.5 ADC clock cycles • SMP = 111: 810.5 ADC clock cycles The total conversion time is calculated as follows: TCONV = Sampling time + 7.5 ADC clock cycles Example: With Fadc_ker_ck = 24 MHz and a sampling time of 1.5 ADC clock cycles (14-bit mode): TCONV = (1.5 + 7.5) ADC clock cycles = 9 ADC clock cycles = 0.375 µs (14 bit mode for fast channels) The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion). Constraints on the sampling time for fast and slow channels For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time as specified in the ADC characteristics section of the datasheets. I/O analog switches voltage booster The I/O analog switches resistance increases when the VDDA voltage is too low. This requires to have the sampling time adapted accordingly (cf datasheet for electrical characteristics). This resistance can be minimized at low VDDA by enabling an internal voltage booster with BOOSTE bit in the SYSCFG_PMCR register. 25.3.14 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either: • Setting the ADSTART bit in the ADCx_CR register (for a regular channel, with software trigger selected) • Setting the JADSTART bit in the ADCx_CR register (for an injected channel, with software trigger selected) • External hardware trigger event (for a regular or injected channel) ADSTART bit or JADSTART bit must be set before triggering an external event. Inside the regular sequence, after each conversion is complete: 874/3178 • The converted data are stored into the 32-bit ADCx_DR register • The EOC (end of regular conversion) flag is set • An interrupt is generated if the EOCIE bit is set DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Inside the injected sequence, after each conversion is complete: • The converted data are stored into one of the four 32-bit ADCx_JDRy registers • The JEOC (end of injected conversion) flag is set • An interrupt is generated if the JEOCIE bit is set After the regular sequence is complete: • The EOS (end of regular sequence) flag is set • An interrupt is generated if the EOSIE bit is set After the injected sequence is complete: • The JEOS (end of injected sequence) flag is set • An interrupt is generated if the JEOSIE bit is set Then the ADC stops until a new external regular or injected trigger occurs or until bit ADSTART or JADSTART is set again. Note: To convert a single channel, program a sequence with a length of 1. 25.3.15 Continuous conversion mode (CONT=1) This mode applies to regular channels only. In continuous conversion mode, when a software or hardware regular trigger event occurs, the ADC performs once all the regular conversions of the channels and then automatically re-starts and continuously converts each conversions of the sequence. This mode is started with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the ADCx_CR register. Inside the regular sequence, after each conversion is complete: • The converted data are stored into the 32-bit ADCx_DR register • The EOC (end of conversion) flag is set • An interrupt is generated if the EOCIE bit is set After the sequence of conversions is complete: • The EOS (end of sequence) flag is set • An interrupt is generated if the EOSIE bit is set Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence. Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection mode section). DocID029587 Rev 3 875/3178 979 Analog-to-digital converters (ADC) 25.3.16 RM0433 Starting conversions (ADSTART, JADSTART) Software starts ADC regular conversions by setting ADSTART=1. When ADSTART is set, the conversion starts: • Immediately: if EXTEN = 0x0 (software trigger) • At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0 Software starts ADC injected conversions by setting JADSTART=1. When JADSTART is set, the conversion starts: Note: • Immediately, if JEXTEN = 0x0 (software trigger) • At the next active edge of the selected injected hardware trigger: if JEXTEN /= 0x0 In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions followed by the auto-injected conversions (JADSTART must be kept cleared). ADSTART and JADSTART also provide information on whether any ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and JADSTART=0 are both true, indicating that the ADC is idle. ADSTART is cleared by hardware: • In single mode with software trigger (CONT=0, EXTEN=0x0) – • In discontinuous mode with software trigger (CONT=0, DISCEN=1, EXTEN=0x0) – • at end of conversion (EOC=1) In all other cases (CONT=x, EXTEN=x) – Note: at any end of conversion sequence (EOS =1) after execution of the ADSTP procedure asserted by the software. In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of EOS because the sequence is automatically relaunched. When a hardware trigger is selected in single mode (CONT=0 and EXTEN /=0x00), ADSTART is not cleared by hardware with the assertion of EOS to help the software which does not need to reset ADSTART again for the next hardware trigger event. This ensures that no further hardware triggers are missed. JADSTART is cleared by hardware: • in single mode with software injected trigger (JEXTEN=0x0) – • in all cases (JEXTEN=x) – Note: 876/3178 at any end of injected conversion sequence (JEOS assertion) or at any end of sub-group processing if JDISCEN=1 after execution of the JADSTP procedure asserted by the software. When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still high. DocID029587 Rev 3 RM0433 25.3.17 Analog-to-digital converters (ADC) Timing The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: TCONV= TSMPL + TSAR = [1.5 |min + 7.5 |14bit] x Tadc_ker_ck TCONV = TSMPL + TSAR = 62.5 ns |min + 312.5 ns |14bit = 375.0 ns (for Fadc_ker_ck = 24 MHz) Figure 133. Analog to digital conversion time $'&VWDWH 5'< 6DPSOLQJ&K 1 $QDORJFKDQQHO &K 1 &K 1 ,QWHUQDO6+ $'67$57 6DPSOLQJ&K 1 &RQYHUWLQJ&K 1 6HW E\6: (2603 +ROG$,1 1 W6$5 6DPSOH$,1 1 W603/ 6HW E\+: &OHDUHG E\6: 6HW E\+: (2& $'&B'5 6DPSOH$,1 1 'DWD1 &OHDUHG E\6: 'DWD1 ,QGLFDWLYHWLPLQJV 069 1. TSMPL depends on SMP[2:0] 2. TSAR depends on RES[2:0] 25.3.18 Stopping an ongoing conversion (ADSTP, JADSTP) The software can decide to stop regular conversions ongoing by setting ADSTP=1 and injected conversions ongoing by setting JADSTP=1. Stopping conversions will reset the ongoing ADC operation. Then the ADC can be reconfigured (ex: changing the channel selection or the trigger) ready for a new operation. Note that it is possible to stop injected conversions while regular conversions are still operating and vice-versa. This allows, for instance, re-configuration of the injected conversion sequence and triggers while regular conversions are still operating (and viceversa). When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADCx_DR register is not updated with the current conversion). When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADCx_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence). Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC is completely stopped. DocID029587 Rev 3 877/3178 979 Analog-to-digital converters (ADC) Note: RM0433 In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used). Figure 134. Stopping ongoing regular conversions 7ULJJHU 7ULJJHU $'&VWDWH 6DPSOH &K 1 5'< &RQYHUW &K 1 6DPSOH &K 1 5'< & 5'< -$'67$57 &OHDUHG E\6: $'67$57 &OHDUHG E\+: 5(*8/$5&219(56,216RQJRLQJ VRIWZDUHLVQRWDOORZHGWRFRQILJXUHUHJXODUFRQYHUVLRQVVHOHFWLRQDQGWULJJHUV &OHDUHG E\6: $'673 $'&B'5 &OHDUHG E\+: 'DWD1 'DWD1 069 Figure 135. Stopping ongoing regular and injected conversions 2EGULAR TRIGGER $'&VWDWH 2$9 3AMPLE #H. )NJECTED TRIGGER #ONVERT #H. 2$9 2EGULAR TRIGGER 3AMPLE #H- # 2$9 3AMPL 2$9 #LEARED 3ET *!$34!24 BY 37 BY (7 ).*%#4%$ #/.6%23)/.3 ONGOING SOFTWARE IS NOT ALLOWED TO CONFIGURE INJECTED CONVERSIONS SELECTION AND TRIGGERS 3ET BY 37 *!$340 !$#?*$2 #LEARED BY (7 $!4! - 3ET BY 37 !$34!24 !$340 !$#?$2 #LEARED BY (7 2%'5,!2 #/.6%23)/.3 ONGOING SOFTWARE IS NOT ALLOWED TO CONFIGURE REGULAR CONVERSIONS SELECTION AND TRIGGERS 3ET BY 37 $!4! . #LEARED BY (7 $!4! . 069 878/3178 DocID029587 Rev 3 RM0433 25.3.19 Analog-to-digital converters (ADC) Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity. When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not possible. The regular trigger selection is effective once software has set bit ADSTART=1 and the injected trigger selection is effective once software has set bit JADSTART=1. Any hardware triggers which occur while a conversion is ongoing are ignored. • If bit ADSTART=0, any regular hardware triggers which occur are ignored. • If bit JADSTART=0, any injected hardware triggers which occur are ignored. Table 191 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity. Table 191. Configuring the trigger polarity for regular external triggers EXTEN[1:0] Note: Source 00 Hardware Trigger detection disabled, software trigger detection enabled 01 Hardware Trigger with detection on the rising edge 10 Hardware Trigger with detection on the falling edge 11 Hardware Trigger with detection on both the rising and falling edges The polarity of the regular trigger cannot be changed on-the-fly. Table 192. Configuring the trigger polarity for injected external triggers Note: JEXTEN[1:0] Source 00 – If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software trigger detection enabled – If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled 01 Hardware Trigger with detection on the rising edge 10 Hardware Trigger with detection on the falling edge 11 Hardware Trigger with detection on both the rising and falling edges The polarity of the injected trigger can be anticipated and changed on-the-fly when the queue is enabled (JQDIS=0). Refer to Section 25.3.22: Queue of context for injected conversions. The EXTSEL[4:0] and JEXTSEL[4:0] control bits select which out of 21 possible events can trigger conversion for the regular and injected groups. A regular group conversion can be interrupted by an injected trigger. DocID029587 Rev 3 879/3178 979 Analog-to-digital converters (ADC) Note: RM0433 The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 25.3.22: Queue of context for injected conversions on page 885 Each ADC master shares the same input triggers with its ADC slave as described in Figure 136. Figure 136. Triggers are shared between ADC master and ADC slave $'&0$67(5 DGFBH[WBWUJ (;7LPDSSHGDW DGFBH[WBWUJ SURGXFWOHYHO DGFBH[WBWUJ ([WHUQDOUHJXODUWULJJHU (;76(/> @ ([WHUQDOLQMHFWHGWULJJHU -(;76(/> @ $'&6/$9( ([WHUQDOUHJXODUWULJJHU (;76(/> @ DGFBMH[WBWUJ -(;7LPDSSHGDW DGFBMH[WBWUJ SURGXFWOHYHO DGFBMH[WBWUJ ([WHUQDOLQMHFWHGWULJJHU -(;76(/> @ 06Y9 Table 193 and Table 194 give all the possible external triggers of the three ADCs for regular and injected conversion. Table 193. ADC1, ADC2 and ADC3 - External triggers for regular channels Name Source Type EXTSEL[4:0] adc_ext_trg0 TIM1_CC1 event Internal signal from on-chip timers 00000 adc_ext_trg1 TIM1_CC2 event Internal signal from on-chip timers 00001 adc_ext_trg2 TIM1_CC3 event Internal signal from on-chip timers 00010 adc_ext_trg3 TIM2_CC2 event Internal signal from on-chip timers 00011 adc_ext_trg4 TIM3_TRGO event Internal signal from on-chip timers 00100 adc_ext_trg5 TIM4_CC4 event Internal signal from on-chip timers 00101 adc_ext_trg6 EXTI line 11 External pin 00110 adc_ext_trg7 TIM8_TRGO event Internal signal from on-chip timers 00111 adc_ext_trg8 TIM8_TRGO2 event Internal signal from on-chip timers 01000 880/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Table 193. ADC1, ADC2 and ADC3 - External triggers for regular channels (continued) Name Source Type EXTSEL[4:0] adc_ext_trg9 TIM1_TRGO event Internal signal from on-chip timers 01001 adc_ext_trg10 TIM1_TRGO2 event Internal signal from on-chip timers 01010 adc_ext_trg11 TIM2_TRGO event Internal signal from on-chip timers 01011 adc_ext_trg12 TIM4_TRGO event Internal signal from on-chip timers 01100 adc_ext_trg13 TIM6_TRGO event Internal signal from on-chip timers 01101 adc_ext_trg14 TIM15_TRGO event Internal signal from on-chip timers 01110 adc_ext_trg15 TIM3_CC4 event Internal signal from on-chip timers 01111 adc_ext_trg16 HRTIM1_ADCTRG1 event Internal signal from on-chip timers 10000 adc_ext_trg17 HRTIM1_ADCTRG3 event Internal signal from on-chip timers 10001 adc_ext_trg18 LPTIM1_OUT event Internal signal from on-chip timers 10010 adc_ext_trg19 LPTIM2_OUT event Internal signal from on-chip timers 10011 adc_ext_trg20 LPTIM3_OUT event Internal signal from on-chip timers 10100 adc_ext_trg21 Reserved - 10101 adc_ext_trg22 Reserved - 10110 adc_ext_trg23 Reserved - 10111 adc_ext_trg24 Reserved - 11000 adc_ext_trg25 Reserved - 11001 adc_ext_trg26 Reserved - 11010 adc_ext_trg27 Reserved - 11011 adc_ext_trg28 Reserved - 11100 adc_ext_trg29 Reserved - 11101 adc_ext_trg30 Reserved - 11110 adc_ext_trg31 Reserved - 11111 Table 194. ADC1, ADC2 and ADC3 - External triggers for injected channels Name Source Type EXTSEL[4:0] adc_ext_trg0 TIM1_TRGO event Internal signal from on-chip timers 00000 adc_ext_trg1 TIM1_CC4 event Internal signal from on-chip timers 00001 adc_jext_trg2 TIM2_TRGO event Internal signal from on-chip timers 00010 adc_jext_trg3 TIM2_CC1 event Internal signal from on-chip timers 00011 adc_jext_trg4 TIM3_CC4 event Internal signal from on-chip timers 00100 adc_jext_trg5 TIM4_TRGO event Internal signal from on-chip timers 00101 adc_jext_trg6 EXTI line 15 External pin 00110 adc_jext_trg7 TIM8_CC4 event Internal signal from on-chip timers 00111 adc_jext_trg8 TIM1_TRGO2 event Internal signal from on-chip timers 01000 DocID029587 Rev 3 881/3178 979 Analog-to-digital converters (ADC) RM0433 Table 194. ADC1, ADC2 and ADC3 - External triggers for injected channels (continued) Name Source Type EXTSEL[4:0] adc_jext_trg9 TIM8_TRGO event Internal signal from on-chip timers 01001 adc_jext_trg10 TIM8_TRGO2 event Internal signal from on-chip timers 01010 adc_jext_trg11 TIM3_CC3 event Internal signal from on-chip timers 01011 adc_jext_trg12 TIM3_TRGO event Internal signal from on-chip timers 01100 adc_jext_trg13 TIM3_CC1 event Internal signal from on-chip timers 01101 adc_jext_trg14 TIM6_TRGO event Internal signal from on-chip timers 01110 adc_jext_trg15 TIM15_TRGO event Internal signal from on-chip timers 01111 adc_jext_trg16 HRTIM1_ADCTRG2 event Internal signal from on-chip timers 10000 adc_jext_trg17 HRTIM1_ADCTRG4 event Internal signal from on-chip timers 10001 adc_jext_trg18 LPTIM1_OUT event Internal signal from on-chip timers 10010 adc_jext_trg19 LPTIM2_OUT event Internal signal from on-chip timers 10011 adc_jext_trg20 LPTIM3_OUT event Internal signal from on-chip timers 10100 adc_jext_trg21 Reserved - 10101 adc_jext_trg22 Reserved - 10110 adc_jext_trg23 Reserved - 10111 adc_jext_trg24 Reserved - 11000 adc_jext_trg25 Reserved - 11001 adc_jext_trg26 Reserved - 11010 adc_jext_trg27 Reserved - 11011 adc_jext_trg28 Reserved - 11100 adc_jext_trg29 Reserved - 11101 adc_jext_trg30 Reserved - 11110 adc_jext_trg31 Reserved - 11111 25.3.20 Injected channel management Triggered injection mode To use triggered injection, the JAUTO bit in the ADCx_CFGR register must be cleared. 882/3178 1. Start the conversion of a group of regular channels either by an external trigger or by setting the ADSTART bit in the ADCx_CR register. 2. If an external injected trigger occurs, or if the JADSTART bit in the ADCx_CR register is set during the conversion of a regular group of channels, the current conversion is DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) reset and the injected channel sequence switches are launched (all the injected channels are converted once). Note: 3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. 4. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence. Figure 137 shows the corresponding timing diagram. When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 20 ADC clock cycles (that is two conversions with a sampling time of 1.5 clock periods), the minimum interval between triggers must be 21 ADC clock cycles. Auto-injection mode If the JAUTO bit in the ADCx_CFGR register is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADCx_SQRy and ADCx_JSQR registers. In this mode, the ADSTART bit in the ADCx_CR register must be set to start regular conversions, followed by injected conversions (JADSTART must be kept cleared). Setting the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used). In this mode, external trigger on injected channels must be disabled. If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer Complete event. DocID029587 Rev 3 883/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 137. Injected conversion latency DGFBNHUBFN ,QMHFWLRQHYHQW 5HVHW$'& PD[ODWHQF\ 62& 06Y9 1. The maximum latency value can be found in the electrical characteristics of the device datasheet. 25.3.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADCx_CFGR register. It is used to convert a short sequence (sub-group) of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADCx_SQRy registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADCx_CFGR register. When an external trigger occurs, it starts the next n conversions selected in the ADCx_SQR registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADCx_SQR1 register. Example: • • 884/3178 DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11 – 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each conversion). – 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each conversion) and an EOS event is generated after the conversion of channel 11. – 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – ... DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11 – 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event. – all the next trigger events will relaunch the complete sequence. DocID029587 Rev 3 RM0433 Note: Analog-to-digital converters (ADC) When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions). When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the 1st subgroup. It is not possible to have both discontinuous mode and continuous mode enabled. In this case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled. Injected group mode This mode is enabled by setting the JDISCEN bit in the ADCx_CFGR register. It converts the sequence selected in the ADCx_JSQR register, channel by channel, after an external injected trigger event. This is equivalent to discontinuous mode for regular channels where ‘n’ is fixed to 1. When an external trigger occurs, it starts the next channel conversions selected in the ADCx_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADCx_JSQR register. Example: • Note: JDISCEN=1, channels to be converted = 1, 2, 3 – 1st trigger: channel 1 converted (a JEOC event is generated) – 2nd trigger: channel 2 converted (a JEOC event is generated) – 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated – ... When all injected channels have been converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. 25.3.22 Queue of context for injected conversions A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. JQDIS bit of ADCx_CFGR register must be reset to enable this feature. Only hardware-triggered conversions are possible when the context queue is enabled. This context consists of: • Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL[4:0] in ADCx_JSQR register) • Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADCx_JSQR register) DocID029587 Rev 3 885/3178 979 Analog-to-digital converters (ADC) RM0433 All the parameters of the context are defined into a single register ADCx_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: Note: • The JSQR register can be written at any moment even when injected conversions are ongoing. • Each data written into the JSQR register is stored into the Queue of context. • At the beginning, the Queue is empty and the first write access into the JSQR register immediately changes the context and the ADC is ready to receive injected triggers. • Once an injected sequence is complete, the Queue is consumed and the context changes according to the next JSQR parameters stored in the Queue. This new context is applied for the next injected sequence of conversions. • A Queue overflow occurs when writing into register JSQR while the Queue is full. This overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the write access of JSQR register which has created the overflow is ignored and the queue of context is unchanged. An interrupt can be generated if bit JQOVFIE is set. • Two possible behaviors are possible when the Queue becomes empty, depending on the value of the control bit JQM of register ADCx_CFGR: 886/3178 If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be empty during run operations: the Queue always maintains the last active context and any further valid start of injected sequence will be served according to the last active context. – If JQM=1, the Queue can be empty after the end of an injected sequence or if the Queue is flushed. When this occurs, there is no more context in the queue and hardware triggers are disabled. Therefore, any further hardware injected triggers are ignored until the software re-writes a new injected context into JSQR register. • Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000. • The Queue is flushed when stopping injected conversions by setting JADSTP=1 or when disabling the ADC by setting ADDIS=1: – If JQM=0, the Queue is maintained with the last active context. – If JQM=1, the Queue becomes empty and triggers are ignored. When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the injected sequence changes the context and consumes the Queue.The 1st trigger only consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length = 3 for both contexts): • • • • • • Note: – 1st trigger, discontinuous. Sequence 1: context 1 consumed, 1st conversion carried out 2nd trigger, disc. Sequence 1: 2nd conversion. 3rd trigger, discontinuous. Sequence 1: 3rd conversion. 4th trigger, discontinuous. Sequence 2: context 2 consumed, 1st conversion carried out. 5th trigger, discontinuous. Sequence 2: 2nd conversion. 6th trigger, discontinuous. Sequence 2: 3rd conversion. When queue of context enabled (bit JQDIS=0), only hardware trigger can be used. DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Behavior when changing the trigger or sequence context The Figure 138 and Figure 139 show the behavior of the context Queue when changing the sequence or the triggers. Figure 138. Example of JSQR queue of context (sequence change) 3 3 3 :ULWH-645 -645TXHXH (037< 3 (037< 3 33 3 3 33 7ULJJHU $'&-FRQWH[W UHWXUQHGE\UHDGLQJ -465 $'&VWDWH 3 5'< &RQYHUVLRQ &RQYHUVLRQ 3 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 3 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 4 conversions, hardware trigger 1 Figure 139. Example of JSQR queue of context (trigger change) 3 3 3 :ULWH-645 -645TXHXH (037< 3 33 3 3 33 ,JQRUHG 7ULJJHU ,JQRUHG 7ULJJHU $'&-FRQWH[W UHWXUQHGE\UHDGLQJ -465 $'&VWDWH (037< 3 3 5'< &RQYHUVLRQ &RQYHUVLRQ 3 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 4 conversions, hardware trigger 1 DocID029587 Rev 3 887/3178 979 Analog-to-digital converters (ADC) RM0433 Queue of context: Behavior when a queue overflow occurs The Figure 140 and Figure 141 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 140. Example of JSQR queue of context with overflow before conversion 3 3 3 :ULWH-645 -645 (037< TXHXH 3 3 !2YHUIORZ LJQRUHG 33 3 33 &OHDUHGE\6: -429) 7ULJJHU 7ULJJHU $'& -FRQWH[W (037< UHWXUQHGE\ UHDGLQJ-465 $'&VWDWH 3 3 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< &RQYHUVLRQ -(26 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 3 conversions, hardware trigger 1 P4: sequence of 4 conversions, hardware trigger 1 Figure 141. Example of JSQR queue of context with overflow during conversion 3 3 3 :ULWH-645 -645 (037< TXHXH 3 3 !2YHUIORZ LJQRUHG 33 3 33 &OHDUHGE\6: -429) 7ULJJHU 7ULJJHU $'& -FRQWH[W UHWXUQHGE\ (037< UHDGLQJ-465 $'&VWDWH 3 3 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< &RQYHUVLRQ -(26 06 9 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 3 conversions, hardware trigger 1 P4: sequence of 4 conversions, hardware trigger 1 888/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). • Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the previous context P2 has been set. This ensures that the previous context has been consumed and that the queue is not full. Queue of context: Behavior when the queue becomes empty Figure 142 and Figure 143 show the behavior of the context Queue when the Queue becomes empty in both cases JQM=0 or 1. Figure 142. Example of JSQR queue of context with empty queue (case JQM=0) 3 7KHTXHXHLVQRWHPSW\ DQGPDLQWDLQV3EHFDXVH-40 3 4XHXHQRWHPSW\ 3PDLQWDLQHG 3 :ULWH-645 (037< 3 $'&-FRQWH[W UHWXUQHGE\ (037< UHDGLQJ-465 3 -645TXHXH 33 3 3 7ULJJHU $'&VWDWH 5'< 3 #ONVERSION 5'< 3 #ONVERSION 5'< #ONVERSION 5'< #ONVERSION 5'< #ONV 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately. DocID029587 Rev 3 889/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 143. Example of JSQR queue of context with empty queue (case JQM=1) 3 1UEUE BECOMES EMPTY AND TRIGGERS ARE IGNORED BECAUSE *1- 3 3 :ULWH-645 -645 TXHXH (037< 3 33 3 (037< )GNORED )GNORED 7ULJJHU $'& 3 -FRQWH[W (037< UHWXUQHGE\UHDGLQJ-465 $'&VWDWH 3 (037< 3 5'< &RQYHUVLRQ 5'< (037< [ &RQYHUVLRQ 5'< 3 (037< &RQYHUVLRQ 5'< -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Flushing the queue of context The figures below show the behavior of the context Queue in various situations when the queue is flushed. Figure 144. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. 3 3 4XHXHLVIOXVKHGDQGPDLQWDLQV WKHODVWDFWLYHFRQWH[W 3LVORVW 3 :ULWH-645 -645TXHXH (037< 3 33 3 6HW E\6: -$'673 3 5HVHW E\+: -$'67$57 5HVHW E\+: 6HW E\6: 7ULJJHU $'&-FRQWH[W (037< 3 3 UHWXUQHGE\UHDGLQJ-645 $'&VWDWH 5'< 673 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 890/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 145. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. 0 1UEUE IS FLUSHED AND MAINTAINS THE LAST ACTIVE CONTEXT 0 0 IS LOST 0 7RITE *312 *312 QUEUE %-049 0 0 0 0 *!$340 0 0 0 2ESET BY (7 3ET BY 37 *!$34!24 2ESET BY (7 3ET BY 37 4RIGGER !$# * %-049 0 CONTEXT RETURNED BY READING *312 !$# STATE 0 2$9 #ONV 340 !BORTED 2$9 #ONVERSION 2$9 #ONVERSION 2$9 -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 146. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion 3 3 :ULWH-645 -645TXHXH (037< WKHODVWDFWLYHFRQWH[W 3LVORVW 3 33 3 6HW E\6: -$'673 3 3 5HVHW E\+: -$'67$57 5HVHW E\+: 6HW E\6: 7ULJJHU $'&-FRQWH[W (037< 3 UHWXUQHGE\UHDGLQJ-645 $'&VWDWH 3 5'< 673 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 DocID029587 Rev 3 891/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 147. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) 0 1UEUE IS FLUSHED AND BECOMES EMPTY 0 IS LOST 0 0 7RITE *312 *312 QUEUE %-049 0 0 0 %-049 %-049 0 %-049 2ESET BY (7 3ET BY 37 *!$340 *!$34!24 0 2ESET BY (7 3ET BY 37 )GNORED 4RIGGER !$# * CONTEXT %-049 0 RETURNED BY READING *312 !$# STATE 2$9 %-049 X #ONV 340 #ONVERSION 2$9 !BORTED 2$9 -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 148. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0) 1UEUE IS FLUSHED AND MAINTAINS THE LAST ACTIVE CONTEXT 0 WHICH WAS NOT CONSUMED IS LOST *312 QUEUE 0 0 0 3ET BY 37 !$$)3 2ESET BY (7 0 !$# * CONTEXT RETURNED BY READING *312 !$# STATE 2$9 2%1 /&& /&& -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 892/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 149. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) 1UEUE IS FLUSHED AND BEOMES EMPTY *312 IS READ AS X *312 QUEUE 0 0 %-049 2ESET BY (7 3ET BY 37 !$$)3 0 !$# * CONTEXT RETURNED BY READING *312 !$# STATE 2$9 %-049 X 2%1 /&& /&& -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Queue of context: Starting the ADC with an empty queue The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized. This procedure is only applicable when JQM bit is reset: 5. Write a dummy JSQR with JEXTEN not equal to 0 (otherwise triggering a software conversion) 6. Set JADSTART 7. Set JADSTP 8. Wait until JADSTART is reset 9. Set JADSTART. Disabling the queue It is possible to disable the queue by setting bit JQDIS=1 into the ADCx_CFGR register. Queue of context: Programming of the register ADCx_JSQR When the injected conversion queue of context is enabled (JQDIS=0), the ADCx_JSQR must be programmed at one register write access. As JL[1:0] register define the number of the injected sequence, corresponding JSQ1 to JSQ4 must be written at same time. If ADCx_JSQR is reprogrammed before the injected conversion start, reprogrammed data is put on the queue. When queue of context is empty, ADCx_JSQR read back as 0x0000. Register access should not use the ‘read modify write’ sequence. When ADCx_JSQR is programmed when already 2 contexts are queued, it will raise JQOVF flag and generate the interrupt. DocID029587 Rev 3 893/3178 979 Analog-to-digital converters (ADC) 25.3.23 RM0433 Programmable resolution (RES) - fast conversion mode It is possible to perform faster conversion by reducing the ADC resolution. The resolution can be configured to be either 16, 14, 12, 10, 8 bits by programming the control bits RES[1:0]. Figure 154, Figure 155, Figure 156 and Figure 157 show the conversion result format with respect to the resolution as well as to the data alignment. Lower resolution allows faster conversion time for applications where high-data precision is not required. It reduces the conversion time spent by the successive approximation steps according to Table 195. Table 195. TSAR timings depending on resolution 25.3.24 RES TSAR (ADC clock cycles) TSAR (ns) at FADC=24 MHz TADC (ADC clock cycles) (with Sampling Time= 1.5 ADC clock cycles) TADC (ns) at FADC=24 MHz 16 8.5 ADC clock cycles 354.2 10 ADC clock cycles 416.7 14 7.5 ADC clock cycles 312.5 9 ADC clock cycles 375 12 6.5 ADC clock cycles 270.8 8 ADC clock cycles 333.3 10 5.5 ADC clock cycles 229.2 7 ADC clock cycles 291.7 8 4.5 ADC clock cycles 187.5 6 ADC clock cycles 250.0 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) The ADC notifies the application for each end of regular conversion (EOC) event and each injected conversion (JEOC) event. The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADCx_DR. The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADCx_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is cleared by the software either by writing 1 to it or by reading the corresponding ADCx_JDRy register. The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set. 25.3.25 End of conversion sequence (EOS, JEOS) The ADC notifies the application for each end of regular sequence (EOS) and for each end of injected sequence (JEOS) event. The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADCx_DR register. An interrupt can be generated if bit EOSIE is set. EOS flag is cleared by the software either by writing 1 to it. The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the software either by writing 1 to it. 894/3178 DocID029587 Rev 3 RM0433 25.3.26 Analog-to-digital converters (ADC) Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 150. Single conversions of a sequence, software trigger $'67$57 (2& (26 $'&VWDWH 5'< &+ &+ &+ &+ ' ' ' $'&B'5 E\VZ 5'< &+ ' &+ &+ &+ 5'< ' ' ' ' E\KZ ,QGLFDWLYHWLPLQJV 06 9 1. EXTEN=0x0, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 151. Continuous conversion of a sequence, software trigger $'67$57 (2& (26 $'673 $'&VWDWH 5($'< &+ $'&B'5 E\VZ &+ &+ &+ &+ &+ ' ' ' ' ' &+ 673 5($'< &+ ' &+ ' ,QGLFDWLYHWLPLQJV E\KZ -36 1. EXTEN=0x0, CONT=1 2. Channels selected = 1,9, 10, 17; AUTDLY=0. DocID029587 Rev 3 895/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 152. Single conversions of a sequence, hardware trigger $'67$57 (2& (26 75*; $'&VWDWH &+ 5'< $'&B'5 E\VZ E\KZ &+ &+ &+ ' ' ' WULJJHUHG 5($'< &+ ' &+ &+ &+ 5'< ' ' ' ' ,QGLFDWLYHWLPLQJV LJQRUHG 069 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. Figure 153. Continuous conversions of a sequence, hardware trigger $'67$57 (2& (26 $'673 75*[ $'& 5'< &+ &+ &+ ' $'&B'5 E\VZ E\KZ ' &+ &+ &+ &+ &+ &+ ' ' ' ' ' ' WULJJHUHG LJQRUHG 6723 5'< 1RWLQVFDOHWLPLQJV 069 1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. 25.3.27 Data management Data register, data alignment and offset (ADCx_DR, ADCx_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADCx_DR data register which is 32 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADCx_JDRy data register which is 32 bits wide. The OVSS[3:0] and LSHIFT[3:0] bitfields in the ADCx_CFGR2 register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 154, Figure 155, Figure 156 and Figure 157. Note: 896/3178 The data can be re-aligned in normal and in oversampling mode. DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Offset An offset y (y=1,2,3,4) can be applied to a channel by programming a value different from 0 in OFFSETy[25:0] bit field into ADCx_OFRy register. The channel to which the offset will be applied is programmed into the bits OFFSETy_CH[4:0] of ADCx_OFRy register. In this case, the converted value is decreased by the user-defined offset written in the bits OFFSETy[25:0]. The result may be a negative value so the read data is signed and the SEXT bit represents the extended sign value. The offset value should be lower than the max conversion value (ex. 16bit mode, offset value max is 0xFFFF). The offset correction is also supported in oversampling mode. For the oversampling mode, offset is subtracted before OVSS right shift applied. Table 196 describes how the comparison is performed for all the possible resolutions for analog watchdog 1, 2, 3. Table 196. Offset computation versus data resolution Subtraction between raw converted data and offset: Resolution (bits RES[2:0]) Raw converted Data, left aligned Result Comments Offset 000: 16-bit DATA[15:0] OFFSET[25:0] signed 27-bit data - 001: 14-bit DATA[15:2],00 OFFSET[25:0] signed 27-bit data The user must configure OFFSET[1:0] to 00 010: 12-bit DATA[15:4],00 signed 27-bit OFFSET[25:0] 00 data The user must configure OFFSET[3:0] to 0000 011: 10-bit DATA[15:6],00 signed 27-bit OFFSET[25:0] 0000 data The user must configure OFFSET[5:0] to 000000 100: 8-bit DATA[15:8],00 signed 27-bit OFFSET[25:0] 0000 data The user must configure OFFSET[7:0] to 00000000 When reading data from ADCx_DR (regular channel) or from ADCx_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”: • If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed. • If none of the four offsets is enabled for this channel, the read data is not signed. Figure 154, Figure 155, Figure 156 and Figure 157 show alignments for signed and unsigned data together with corresponding OVSS and LSHIFT values. DocID029587 Rev 3 897/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 154. Right alignment (offset disabled, unsigned value) ELWGDWD '' ELWGDWD ELWGDWD '' ELWGDWD 265 '' '' ELWGDWD 265 2966 2966 '' 06Y9 Figure 155. Right alignment (offset enabled, signed value) ELWGDWD 6(;7 ELWGDWD ELWGDWD ELWGDWD 6(;7 6LJQHGELW IRUPDW '' 6(;7 66$7( 25 56+,)7 6(;7 '' ELWGDWD 6LJQHGELW IRUPDW '' 6(;7 '' 6(;7 ELWGDWD 265 '' '' 66$7( 25 56+,)7 6LJQHGELW IRUPDW 2966 06Y9 898/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 156. Left alignment (offset disabled, unsigned value) ELWGDWD ELWGDWD '' /6+,)7 '' ELWGDWD /6+,)7 '' ELWGDWD 265 /6+,)7 '' /6+,)7 06Y9 Figure 157. Left alignment (offset enabled, signed value) ELWGDWD 6 ELWGDWD ELWGDWD 6 '' '' 6$7(1 6LJQHGELW IRUPDW /6+,)7 6LJQHGELW IRUPDW /6+,)7 6LJQHGELW IRUPDW 6(;7 '' 6LJQHGELW IRUPDW '' /6+,)7 '' ELWGDWD 6(;7 ELWGDWD 6(;7 '' 6(;7 ELWGDWD 265 66$7( 25 56+,)7 6LJQHGELW IRUPDW /6+,)7 6LJQHGELW IRUPDW 06Y9 16-bit and 8-bit signed format management: RSHIFTx,SSATE The offset correction sign-extends the data format, resulting in an unsigned 16-bit conversion being extended to 17-bit signed format, for instance. Three options are offered for formatting 8-bit and 16-bit conversion results. DocID029587 Rev 3 899/3178 979 Analog-to-digital converters (ADC) RM0433 For each offset correction channel 1 to 4, a RSHIFT1..4 bit in the ADCx_CFGR2 register allows to have the result right-shifted 1-bit and have it fitting a standard 8 or 16-bit format. Another option is to have the result saturated to the 16-bit and 8-bit signed formats, for the following cases only: RES[2:0] = 000 (16-bit format) and RES[2:0] = 100 (8-bit format). This mode is enabled with the SSATE bit in the ADCx_OFRy register. The table below summarizes the 3 available use case for 16-bit format. Table 197. 16-bit data formats SSATE RSHIFTx Data range Format (offset = 0x8000) 0 0 Sign-extended 17-bit significant data SEXT[31:16] DATA[15:0] 0x00007FFF - 0x FFFF8000 0 1 Sign-extended right-shifted 16-bit significant data SEXT[31:15] DATA[14:0] 0x3FFF - 0xC000 1 0 Sign-extended saturated 16-bit significant data SEXT[31:15] DATA[14:0] 7FFF - 0x8000 1 1 Reserved - Numerical examples are given in Table 198 with 3 different offset values. Table 198. Numerical examples for 16-bit format (bold indicates saturation) Raw conversion result Offset value 0xFFFF Result Result Result SSATE = 0 SSATE = 0 SSATE = 1 RSHIFT = 0 RSHIFT = 1 RSHIFT = 0 0x0000 7FFF 3FFF 7FFF 0x0000 0000 0 0 0x0000 0xFFFF 8000 C000 8000 0xFFFF 0x0000 7FDF 3FEF 7FDF 0xFFFF FFE0 FFF0 FFE0 0x0000 0xFFFF 7FE0 BFF0 8000 0xFFFF 0x0000 800F 4007 7FFF 0x0000 0010 8 0010 0xFFFF 8010 C008 8010 0x8000 0x8000 0x8000 0x0000 0x8000 0x8020 0x7FF0 When oversampling mode is active, the SSATE and RSHIFT1..4 bits are not supported. 900/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1. When an overrun condition occurs, the ADC is still operating and can continue to convert unless the software decides to stop and reset the sequence by setting bit ADSTP=1. OVR flag is cleared by software by writing 1 to it. It is possible to configure if data is preserved or overwritten when an overrun event occurs by programming the control bit OVRMOD: • OVRMOD=0: The overrun event preserves the data register from being overrun: the old data is maintained and the new conversion is discarded and lost. If OVR remains at 1, any further conversions will occur but the result data will be also discarded. • OVRMOD=1: The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, any further conversions will operate normally and the ADCx_DR register will always contain the latest converted data. Figure 158. Example of overrun (OVR) $'67$57 (2& (26 295 $'673 75*[ $'&VWDWH 5'< &+ &+ &+ &+ &+ $'&B'5UHDGDFFHVV $'&B'5 29502' ' ' ' ' $'&B'5 29502' ' ' ' ' E\VZ &+ &+ ' ' 6723 5'< 2YHUXQ E\KZ WULJJHUHG ,QGLFDWLYHWLPLQJV -36 Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels. Managing a sequence of conversion without using the DMA If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the software must use the EOC flag and its associated interrupt to handle each data. Each time a conversion is complete, EOC is set and the ADCx_DR register can be read. OVRMOD should be configured to 0 to manage overrun events as an error. DocID029587 Rev 3 901/3178 979 Analog-to-digital converters (ADC) RM0433 Managing conversions without using the DMA and without overrun It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software. An overrun event will not prevent the ADC from continuing to convert and the ADCx_DR register will always contain the latest conversion. Managing conversions using the DMA Since converted channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one channel. This avoids the loss of the data already stored in the ADCx_DR register. When the DMA mode is enabled (DMNGT bit = 01 or 11 in the ADCx_CFGR register in single ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated after each conversion of a channel. This allows the transfer of the converted data from the ADCx_DR register to the destination location selected by the software. Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid. Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD)). The DMA transfer requests are blocked until the software clears the OVR bit. Two different DMA modes are proposed depending on the application use and are configured with bit DMNGT of the ADCx_CFGR register in single ADC mode, or with bit DAMDF of the ADCx_CCR register in dual ADC mode: • DMA one shot mode (DMNGT bit = 01). This mode is suitable when the DMA is programmed to transfer a fixed number of data. • DMA circular mode (DMNGT bit = 11) This mode is suitable when programming the DMA in circular mode. DMA one shot mode (DMNGT=01) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion has been started again. When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): 902/3178 • The content of the ADC data register is frozen. • Any ongoing conversion is aborted with partial result discarded. • No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started. • Scan sequence is stopped and reset. • The DMA is stopped. DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) DMA circular mode (DMNGT=11) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream. DMA with FIFO The output data register has 8 stage FIFO. Two different DMA requests are generated parallel. When a data is available, “SREQ single request” generated, when 4 data are available, “BREQ burst request” generated. DMA2 can be programmed either single transfer mode or incremental burst mode(4 beats), according to this mode, correct request line is selected by the DMA2. Please refer to the DMA2 chapter for further information. 25.3.28 Managing conversions using the DFSDM The ADC conversion results can be transferred directly to the Digital Filter for Sigma Delta Modulators (DFSDM). In this case, the DMNGT[1:0] bits must be set to 10. The ADC transfers 16 least significant bits of the regular data register data to the DFSDM, which in turns will reset the EOC flag once the transfer is effective. The data format must be 16-bit signed: ADCx_DR[31:16] = don’t care ADCx_DR[15] = sign ADCx_DR[14:0] = data Any value above 16-bit signed format will be truncated. 25.3.29 Dynamic low-power features Auto-delayed conversion mode (AUTDLY) The ADC implements an auto-delayed conversion mode controlled by the AUTDLY configuration bit. Auto-delayed conversions are useful to simplify the software as well as to optimize performance of an application clocked at low frequency where there would be risk of encountering an ADC overrun. When AUTDLY=1, a new conversion can start only if all the previous data of the same group has been treated: • For a regular conversion: once the ADCx_DR register has been read or if the EOC bit has been cleared (see Figure 159). • For an injected conversion: when the JEOS bit has been cleared (see Figure 160). This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data. The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1). Note: There is no delay inserted between each conversions of the injected sequence, except after the last one. DocID029587 Rev 3 903/3178 979 Analog-to-digital converters (ADC) RM0433 During a conversion, a hardware trigger event (for the same group of conversions) occurring during this delay is ignored. Note: This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to re-start a conversion: it is up to the software to read the data before launching a new conversion. No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely): • If an injected trigger occurs during the automatic delay of a regular conversion, the injected conversion starts immediately (see Figure 160). • Once the injected sequence is complete, the ADC waits for the delay (if not ended) of the previous regular conversion before launching a new regular conversion (see Figure 162). The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular conversion can start only when the automatic delay of the previous injected sequence of conversion has ended (when JEOS has been cleared). This is to ensure that the software can read all the data of a given sequence before starting a new sequence (see Figure 163). To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure: 1. Wait until JEOS=1 (no more conversions are restarted) 2. Clear JEOS, 3. Set ADSTP=1 4. Read the regular data. If this procedure is not respected, a new regular sequence can re-start if JEOS is cleared after ADSTP has been set. In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence. It is however considered pending if it occurs after this delay, even if it occurs during an injected sequence of the delay that follows it. The conversion then starts at the end of the delay of the injected sequence. In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the sequence. 904/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 159. AUTODLY=1, regular conversion in continuous mode, software trigger $'67$57 (2& (26 $'673 $'&B'5UHDGDFFHVV $'&VWDWH &+ 5'< '/< $'&B'5 &+ ' E\VZ '/< '/< &+ ' &+ '/< 6723 ' 5'< ' E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3 3. Injected configuration DISABLED Figure 160. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) 1RWLJQRUHG RFFXUVGXULQJLQMHFWHGVHTXHQFH ,JQRUHG 5HJXODU WULJJHU $'&VWDWH 5'< &+ '/< &+ '/< &+ UHJXODU UHJXODU '/< &+ &+ &+ LQMHFWHG UHJXODU '/< &+ &+ '/< '/< &+ UHJXODU UHJXODU LQMHFWHG '/< &+ '/< &+ (2& (26 $'&B'5 UHDGDFFHVV ' $'&B'5 ' ' ' ,JQRUHG ,QMHFWHG WULJJHU '/< LQM -(26 ' $'&B-'5 ' $'&B-'5 E\VZ E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 DocID029587 Rev 3 905/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 161. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) 1RWLJQRUHG RFFXUVGXULQJLQMHFWHGVHTXHQFH ,JQRUHG 5HJXODU WULJJHU $'& VWDWH 5'< &+ UHJXODU &+ '/< 5'< &+ '/< 5'< &+ 5'< &+ '/< 5'< &+ '/< 5'<&+ UHJXODU UHJXODU LQMHFWHG LQMHFWHG UHJXODU UHJXODU '/< &+ '/< &+ '/< &+ '/< &+ (2& (26 $'&B'5UHDGDFFHVV $'&B'5 ' ' ,JQRUHG ,QMHFWHG WULJJHU ' ' ,JQRUHG '/< LQM -(26 $'&B-'5 ' ' $'&B-'5 E\VZ ,QGLFDWLYHWLPLQJV E\KZ 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3. 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6 906/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 162. AUTODLY=1, regular continuous conversions interrupted by injected conversions $'67$57 $'& VWDWH 5'< &+ &+ '/< UHJXODU '/< UHJXODU &+ &+ LQMHFWHG LQMHFWHG '/< &+ '/< &+ '/< &+ UHJXODU '/< &+ UHJXODU '/< &+ (2& (26 $'&B'5UHDGDFFHVV ' $'&B'5 ' ' ,JQRUHG ,QMHFWHG WULJJHU '/< LQM -(26 $'&B-'5 ' $'&B-'5 ' E\VZ E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 Figure 163. AUTODLY=1 in auto- injected mode (JAUTO=1) ^dZd;ϭͿ ƐƚĂƚĞ EŽĚĞůĂLJ Zz ,ϭ >z;,ϭͿ ,Ϯ ƌĞŐƵůĂƌ ƌĞŐƵůĂƌ ,ϱ ŝŶũĞĐƚĞĚ ,ϲ >z;ŝŶũͿ >z;,ϮͿ ,ϯ ƌĞŐƵůĂƌ ŝŶũĞĐƚĞĚ >z ,ϭ ƌĞŐƵůĂƌ K K^ ͺZƌĞĂĚĂĐĐĞƐƐ ͺZ ϭ Ϯ ϯ : K^ ͺ:Zϭ ϱ ϲ ͺ:ZϮ ďLJƐͬǁ ďLJŚͬǁ /ŶĚŝĐĂƚŝǀĞƚŝŵŝŶŐƐ D^ϯϭϬϮϰsϯ 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2 3. Injected configuration: JAUTO=1, CHANNELS = 5,6 DocID029587 Rev 3 907/3178 979 Analog-to-digital converters (ADC) 25.3.30 RM0433 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 164. Analog watchdog guarded area $QDORJYROWDJH +LJKHUWKUHVKROG +75 *XDUGHGDUHD /RZHUWKUHVKROG /75 DL AWDx flag and interrupt An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDyIE in the ADCx_IER register (x=1,2,3). AWDy (y=1,2,3) flag is cleared by software by writing 1 to it. The ADC conversion result is compared to the lower and higher thresholds before alignment. Description of analog watchdog 1 The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADCx_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels(1) remain within a configured voltage range (window). Table 199 shows how the ADCx_CFGRy registers should be configured to enable the analog watchdog on one or more channels. Table 199. Analog watchdog channel selection Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit JAWD1EN bit None x 0 0 All injected channels 0 0 1 All regular channels 0 1 0 All regular and injected channels 0 1 1 1 0 1 1 1 0 1 1 1 (1) Single injected channel Single(1) regular channel (1) Single regular or injected channel 1. Selected by the AWDyCH[4:0] bits. The channels must also be programmed to be converted in the appropriate regular or injected sequence. The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. 908/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) These thresholds are programmed in bits HTR1[25:0] of the ADCx_HTR1 register and LTR1[25:0] of the ADCx_LTR1 register for the analog watchdog 1. The threshold can be up to 26-bits (16-bit resolution with oversampling, OSR=1024). When converting data with a resolution of less than 16 bits (according to bits RES[2:0]), the LSBs of the programmed thresholds must be kept cleared, the internal comparison being performed on the full 16-bit converted data (left aligned to the half-word boundary). Table 200 describes how the comparison is performed for all the possible resolutions for analog watchdog 1,2,3. Table 200. Analog watchdog 1,2,3 comparison Resolution (bit RES[2:0]) Analog watchdog comparison between: Raw converted data, left aligned(1) Comments Thresholds 000: 16-bit DATA[15:0] LTR1[25:0] and HTR1[25:0] 001: 14-bit DATA[15:2],00 LTR1[25:0] and HTR1[25:0] User must configure LTR1[1:0] and HTR1[1:0] to 00 010: 12-bit DATA[15:4],0000 LTR1[25:0] and HTR1[25:0] User must configure LTR1[3:0] and HTR1[3:0] to 0000 011: 10-bit DATA[15:6],00000 LTR1[25:0] and 0 HTR1[25:0] User must configure LTR1[5:0] and HTR1[5:0] to 000000 100: 8-bit DATA[15:8],00000 LTR1[25:0] and 000 HTR1[25:0] User must configure LTR1[7:0] and HTR1[7:0] to 00000000 - 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). Description of analog watchdog 2 and 3 The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDCHy[19:0] (y=2,3). The corresponding watchdog is enabled when any bit of AWDCHy[19:0] (y=2,3) is set. The threshold can be up to 26-bits (16-bit resolution with oversampling, OSR=1024) and are programmed with the ADCx_HTR2, ADCx_LTR2, ADCx_LTR3, and ADCx_HTR3 registers. When converting data with a resolution of less than 16 bits (according to bits RES[2:0]), the LSBs of the programmed thresholds must be kept cleared, the internal comparison being performed on the full 16-bit converted data (left aligned to the half-word boundary). ADCx_AWDy_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCx_AWDy_OUT (x=ADC number, y=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCx_AWDy_OUT signal as ETR. DocID029587 Rev 3 909/3178 979 Analog-to-digital converters (ADC) RM0433 ADCx_AWDy_OUT is activated when the associated analog watchdog is enabled: Note: • ADCx_AWDy_OUT is set when a guarded conversion is outside the programmed thresholds. • ADCx_AWDy_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds (It remains at 1 if the next guarded conversions are still outside the programmed thresholds). • ADCx_AWDy_OUT is also reset when disabling the ADC (when setting ADDIS=1). Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1) has no influence on the generation of ADCy_AWDx_OUT. AWDx flag is set by hardware and reset by software: AWDy flag has no influence on the generation of ADCx_AWDy_OUT (ex: ADCy_AWDy_OUT can toggle while AWDx flag remains at 1 if the software did not clear the flag). Figure 165. ADCy_AWDx_OUT signal generation (on all regular channels) $'& 67$7( 5'< &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH (2&)/$* FOHDUHG E\6: $:'[)/$* FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOV 5HJXODUFKDQQHOVDUHDOOJXDUGHG 069 Figure 166. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) $'& 67$7( 5'< &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH (2&)/$* $:'[)/$* QRWFOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOV 5HJXODUFKDQQHOVDUHDOOJXDUGHG 069 910/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 167. ADCy_AWDx_OUT signal generation (on a single regular channel) $'& &RQYHUVLRQ 67$7( RXWVLGH &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH (2&)/$* (26)/$* FOHDUHG E\6: FOHDUHG E\6: $:'[)/$* $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOVDQG 2QO\FKDQQHOLVJXDUGHG 069 Figure 168. ADCy_AWDx_OUT signal generation (on all injected channels) $'& 67$7( 5'< &RQYHUVLRQ &RQYHUVLRQ LQVLGH RXWVLGH &RQYHUVLRQ &RQYHUVLRQ LQVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH -(26)/$* $:'[)/$* FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJWKHLQMHFWHGFKDQQHOV $OOLQMHFWHGFKDQQHOVDUHJXDUGHG 069 25.3.31 Oversampler The oversampling unit performs data preprocessing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 26-bit (16-bit values and OSR = 1024). It provides a result with the following form, where N and M can be adjusted: n = N–1 1 Result = ----- × M ∑ Conversion(t n) n=0 It allows to perform by hardware the following functions: averaging, data rate reduction, SNR improvement, basic filtering. DocID029587 Rev 3 911/3178 979 Analog-to-digital converters (ADC) RM0433 The oversampling ratio N is defined using the OSR[9:0] bits in the ADCx_CFGR2 register, and can range from 2x to 1024x. The division coefficient M consists of a right bit shift up to 10 bits, and is defined using the OVSS[3:0] bits in the ADCx_CFGR2 register. The summation unit can yield a result up to 26 bits (1024 x 16-bit results), which can be left or right shifted. When right shifting is selected, it is rounded to the nearest value using the least significant bits left apart by the shifting, before being transferred into the ADCx_DR data register. The Table 169 gives a numerical example of the processing, from a raw 26-bit accumulated data to the final 16-bit result. Figure 169. 16-bit result oversampling with 10-bits right shift and rouding ELWGDWD 265 '' 2966> @ 5LJKWVKLIWLQJDQGURXQGLQJ ELWGDWD 265 ELWGDWD 265 2966> @ '' [))( 2966> @ 5LJKWVKLIWLQJDQGURXQGLQJ ELWGDWD 265 [))) 2966> @ 06Y9 There are no changes for conversion timings in oversampled mode: the sample time is maintained equal during the whole oversampling sequence. A new data is provided every N conversions, with an equivalent delay equal to N x TCONV = N x (tSMPL + tSAR). The flags are set as follow: 912/3178 • the end of the sampling phase (EOSMP) is set after each sampling phase • the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available • the end of sequence (EOS) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total) DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Single ADC operating modes support when oversampling In oversampling mode, most of the ADC operating modes are maintained: • Single or continuous mode conversions • ADC conversions start either by software or with triggers • ADC stop during a conversion (abort) • Data read via CPU or DMA with overrun detection • Low-power modes (AUTDLY) • Programmable resolution: in this case, the reduced conversion values (as per RES[2:0] bits in ADCx_CFGR register) are accumulated, truncated, rounded and shifted in the same way as 16-bit conversions are Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in ADCx_CFGR is ignored and the data are always provided right-aligned. Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset). Analog watchdog The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference: Note: • the RES[2:0] bits are ignored, comparison is always done on using the full 26-bit values HTRx[25:0] and LTRx[25:0] • the comparison is performed on the oversampled accumulated value before shifting Care must be taken when using high shifting values, this will reduce the comparison range. For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data rightaligned, the effective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADCx_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8] must be kept reset. Triggered mode The averager can also be used for basic filtering purpose. Although not a very powerful filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TROVS bit in ADCx_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself. The Figure 170 below shows how conversions are started in response to triggers during discontinuous mode. If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1. DocID029587 Rev 3 913/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 170. Triggered regular oversampling mode (TROVS bit = 1) &217 ',6&(1 75296 7ULJJHU &K 1 7ULJJHU &K 1 &K 1 &K 1 &K 1 &K 1 &K 1 &K 1 (2&IODJVHW &217 ',6&(1 75296 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 (2&IODJVHW 069 Injected and regular sequencer management when oversampling In oversampling mode, it is possible to have differentiated behavior for injected and regular sequencers. The oversampling can be enabled for both sequencers with some limitations if they have to be used simultaneously (this is related to a unique accumulation unit). Oversampling regular channels only The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion: – in continued mode, the accumulation re-starts from the last valid data (prior to the conversion abort request due to the injected trigger). This ensures that oversampling will be completed whatever the injection frequency (providing at least one regular conversion can be completed between triggers); – in resumed mode, the accumulation re-starts from 0 (previous conversions results are ignored). This mode allows to guarantee that all data used for oversampling were converted back-to-back within a single timeslot. Care must be taken to have a injection trigger period above the oversampling period length. If this condition is not respected, the oversampling cannot be completed and the regular sequencer will be blocked. The Figure 171 gives examples for a 4x oversampling ratio. 914/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 171. Regular oversampling modes (4x ratio) 2YHUVDPSOLQJ VWRSSHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ FRQWLQXHG &K 0 $ERUW &K 0 ,QMHFWHGFKDQQHOV &K - &K 0 &K 0 &K 2 &K 0 &K 0 &K . -(2& &RQWLQXHGPRGH 5296( -296( 52960 75296 ; 2YHUVDPSOLQJ DERUWHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ UHVXPHG &K 0 $ERUW &K 0 ,QMHFWHGFKDQQHOV &K - &K 0 &K . -(2& 5HVXPHGPRGH 5296( -296( 52960 75296 ; 069 Oversampling Injected channels only The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in the injected sequencer. Oversampling regular and Injected channels It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on Figure 172 below. Figure 172. Regular and injected oversampling modes used simultaneously 2YHUVDPSOLQJ DERUWHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ UHVXPHG &K 0 $ERUW ,QMHFWHGFKDQQHOV &K - &K 0 &K - &K - &K - &K 0 -(2& 5296( -296( 52960 ;75296 069 DocID029587 Rev 3 915/3178 979 Analog-to-digital converters (ADC) RM0433 Triggered regular oversampling with injected conversions It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on Figure 173 below. Figure 173. Triggered regular oversampling with injection 2YHUVDPSOLQJ UHVXPHG 7ULJJHU 5HJXODUFKDQQHOV &K 1 7ULJJHU &K 1 7ULJJHU 7ULJJHU 7ULJJHU 7ULJJHU &K 1 $ERUW ,QMHFWHGFKDQQHOV &K - &K 1 &K . 5296( -296( 52960 ;75296 069 Autoinjected mode It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 174 below shows how the conversions are sequenced. Figure 174. Oversampling in auto-injected mode 5HJXODUFKDQQHOV 1 1 1 1 1 1 1 1 ,QMHFWHGFKDQQHOV , , , , - - - - . . . . / / / / -$872 5296( -296( 52960 ;75296 06 9 It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO=1, DISCEN=0, JDISCEN=0, ROVSE=1, JOVSE=1 and TROVSE=1. Dual ADC modes support when oversampling It is possible to have oversampling enabled when working in dual ADC configuration, for the injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs must be programmed with the very same settings (including oversampling). All other dual ADC modes are not supported when either regular or injected oversampling is enabled (ROVSE = 1 or JOVSE = 1). 916/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Combined modes summary The Table 201 below summarizes all combinations, including modes not supported. Table 201. Oversampler operating modes summary Regular Over- Injected Oversampling sampling ROVSE JOVSE Oversampler mode ROVSM Triggered Regular mode 0 = continued TROVS Comment 1 = resumed 25.3.32 1 0 0 0 Regular continued mode 1 0 0 1 Not supported 1 0 1 0 Regular resumed mode 1 0 1 1 Triggered regular resumed mode 1 1 0 X Not supported 1 1 1 0 Injected and regular resumed mode 1 1 1 1 Not supported 0 1 X X Injected oversampling Dual ADC modes In devices with two ADCs or more, dual ADC modes can be used (see Figure 175): • ADC1 and ADC2 can be used together in dual mode (ADC1 is master) In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register. Four possible modes are implemented: • Injected simultaneous mode • Regular simultaneous mode • Interleaved mode • Alternate trigger mode It is also possible to use these modes combined in the following ways: • Injected simultaneous mode + Regular simultaneous mode • Regular simultaneous mode + Alternate trigger mode • Injected simultaneous mode + Interleaved mode In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADCx_CFGR register are shared between the master and slave ADC: the bits in the slave ADC are always equal to the corresponding bits of the master ADC. To start a conversion in dual mode, the user must program the bits EXTEN, EXTSEL, JEXTEN, JEXTSEL of the master ADC only, to configure a software or hardware trigger, DocID029587 Rev 3 917/3178 979 Analog-to-digital converters (ADC) RM0433 and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC are don’t care). In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit. In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit. In dual ADC mode, the converted data of the master and slave ADC can be read in parallel, by reading the ADC common data register (ADCx_CDR). The status bits can be also read in parallel by reading the dual-mode status register (ADCx_CSR). 918/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 175. Dual ADC block diagram(1) 5HJXODUGDWDUHJLVWHU ELWV ,QMHFWHGGDWDUHJLVWHUV [ELWV ,QWHUQDODQDORJLQSXWV 6ODYH$'& ,QMHFWHG FKDQQHOV $'&[B,13 $'&[B,11 $'&[B,13 $'&[B,11 $GGUHVVGDWDEXV 5HJXODU FKDQQHOV ,QWHUQDOWULJJHUV 5HJXODUGDWDUHJLVWHU ELWV *3,2 SRUWV $'&[B,13 $'&[B,11 ,QMHFWHGGDWDUHJLVWHUV [ELWV 5HJXODU FKDQQHOV ,QWHUQDODQDORJLQSXWV ,QMHFWHG FKDQQHOV 'XDOPRGH FRQWURO 6WDUWWULJJHUPX[ UHJXODUJURXS 0DVWHU$'& 6WDUWWULJJHUPX[ LQMHFWHGJURXS 06Y 9 1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram. 2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data. DocID029587 Rev 3 919/3178 979 Analog-to-digital converters (ADC) RM0433 Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL[4:0] bits in the ADCx_JSQR register). Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). In simultaneous mode, one must convert sequences with the same length and inside a sequence, the N-th conversion in master ans slave must be configured with the same sampling time. Regular conversions can be performed on one or all ADCs. In that case, they are independent of each other and are interrupted when an injected event occurs. They are resumed at the end of the injected conversion group. • At the end of injected sequence of conversion event (JEOS) on the master ADC, the converted data is stored into the master ADCx_JDRy registers and a JEOS interrupt is generated (if enabled) • At the end of injected sequence of conversion event (JEOS) on the slave ADC, the converted data is stored into the slave ADCx_JDRy registers and a JEOS interrupt is generated (if enabled) • If the duration of the master injected sequence is equal to the duration of the slave injected one (like in Figure 176), it is possible for the software to enable only one of the two JEOS interrupt (ex: master JEOS) and read both converted data (from master ADCx_JDRy and slave ADCx_JDRy registers). Figure 176. Injected simultaneous mode on 4 channels: dual ADC mode 0$67(5$'& &+ &+ &+ &+ 6/$9($'& &+ &+ &+ &+ 7ULJJHU 6DPSOLQJ (QGRILQMHFWHGVHTXHQFHRQ 0$67(5DQG6/$9($'& &RQYHUVLRQ 06 9 If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected trigger event to occur. This mode can be combined with AUTDLY mode: 920/3178 • Once a simultaneous injected sequence of conversions has ended, a new injected trigger event is accepted only if both JEOS bits of the master and the slave ADC have been cleared (delay phase). Any new injected trigger events occurring during the ongoing injected sequence and the associated delay phase are ignored. • Once a regular sequence of conversions of the master ADC has ended, a new regular trigger event of the master ADC is accepted only if the master data register (ADCx_DR) has been read. Any new regular trigger events occurring for the master ADC during the ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of the master ADC (selected by the EXTSEL[4:0] bits in the ADCx_CFGR register). A simultaneous trigger is provided to the slave ADC. In this mode, independent injected conversions are supported. An injection request (either on master or on the slave) will abort the current simultaneous conversions, which are restarted once the injected conversion is completed. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). In regular simultaneous mode, one must convert sequences with the same length and inside a sequence, the N-th conversion in master ans slave must be configured with the same sampling time. Software is notified by interrupts when it can read the data: • At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt is generated (if EOCIE is enabled) and software can read the ADCx_DR of the master ADC. • At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is generated (if EOCIE is enabled) and software can read the ADCx_DR of the slave ADC. • If the duration of the master regular sequence is equal to the duration of the slave one (like in Figure 177), it is possible for the software to enable only one of the two EOC interrupt (ex: master EOC) and read both converted data from the Common Data register (ADCx_CDR). It is also possible to read the regular data using the DMA. Two methods are possible: • • Note: Using two DMA channels (one for the master and one for the slave). In this case bits DAMDF[1:0] must be kept cleared. – Configure the DMA master ADC channel to read ADCx_DR from the master. DMA requests are generated at each EOC event of the master ADC. – Configure the DMA slave ADC channel to read ADCx_DR from the slave. DMA requests are generated at each EOC event of the slave ADC. Configuring Dual ADC mode data format DAMDF[1:0] bits, which leaves one DMA channel free for other uses: – Configure DAMDF[1:0]=0b10 or 0b11 (depending on resolution). – A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR) – A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register. – both EOC flags are cleared when the DMA reads the ADCx_CCR register. When DAMDF[1:0]=0b10 or 0b11, the user must program the same number of conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining conversions will not generate a DMA request. DocID029587 Rev 3 921/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 177. Regular simultaneous mode on 16 channels: dual ADC mode 0$67(5$'& 6/$9($'& &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ 7ULJJHU 6DPSOLQJ (QGRIUHJXODUVHTXHQFHRQ 0$67(5DQG6/$9($'& &RQYHUVLRQ DLE If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n” is defined by DISCNUM). This mode can be combined with AUTDLY mode: • Once a simultaneous conversion of the sequence has ended, the next conversion in the sequence is started only if the common data register, ADCx_CDR (or the regular data register of the master ADC) has been read (delay phase). • Once a simultaneous regular sequence of conversions has ended, a new regular trigger event is accepted only if the common data register (ADCx_CDR) has been read (delay phase). Any new regular trigger events occurring during the ongoing regular sequence and the associated delay phases are ignored. It is possible to use the DMA to handle data in regular simultaneous mode combined with AUTDLY mode, assuming that multi-DMA mode is used: bits DAMDF must be set to 0b10 or 0b11. When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the user to ensure that: Note: • The number of conversions in the master’s sequence is equal to the number of conversions in the slave’s. • For each simultaneous conversions of the sequence, the length of the conversion of the slave ADC is inferior to the length of the conversion of the master ADC. Note that the length of the sequence depends on the number of channels to convert and the sampling time and the resolution of each channels. This combination of regular simultaneous mode and AUTDLY mode is restricted to the use case when only regular channels are programmed: it is forbidden to program injected channels in this combined mode. Interleaved mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00111. This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of the master ADC. After an external trigger occurs: • The master ADC starts immediately. • The slave ADC starts after a delay of several ADC clock cycles after the sampling phase of the master ADC has complete. The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts to count after the end of the sampling phase of the master conversion. This way, an ADC cannot start a conversion if the 922/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). • The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase. • The maximum DELAY is equal to the number of cycles corresponding to the selected resolution. However the user must properly calculate this delay to ensure that an ADC does not start a conversion while the other ADC is still sampling its input. If the CONT bit is set on both master and slave ADCs, the selected regular channels of both ADCs are continuously converted. The software is notified by interrupts when it can read the data at the end of each conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are generated (if EOCIE is enabled) and the software can read the ADCx_DR of the slave/master ADC. Note: It is possible to enable only the EOC interrupt of the slave and read the common data register (ADCx_CDR). But in this case, the user must ensure that the duration of the conversions are compatible to ensure that inside the sequence, a master conversion is always followed by a slave conversion before a new master conversion restarts. It is recommended to use the MDMA mode. It is also possible to have the regular data transferred by DMA. In this case, individual DMA requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as following: • Configure DAMDF[1:0]=0b10 or 0b11 (depending on resolution). • A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR). • A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register. • Both EOC flags are cleared when the DMA reads the ADCx_CCR register. Figure 178. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode 0$67(5$'& 6/$9($'& 7ULJJHU &+ &+ &+ $'&&/. $'&&/. F\FOHV F\FOHV &+ (QGRIFRQYHUVLRQRQPDVWHUDQG VODYH$'& 6DPSOLQJ &RQYHUVLRQ 06Y9 DocID029587 Rev 3 923/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 179. Interleaved mode on 1 channel in single conversion mode: dual ADC mode 0$67(5$'& &+ &+ 6/$9($'& 7ULJJHU &+ &+ $'&&/. (QGRIFRQYHUVLRQRQ $'&&/. F\FOHV F\FOHV PDVWHUDQGVODYH$'& (QGRIFRQYHUVLRQRQ PDVWHUDQGVODYH$'& 6DPSOLQJ &RQYHUVLRQ 06Y9 If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur. In this mode, injected conversions are supported. When injection is done (either on master or on slave), both the master and the slave regular conversions are aborted and the sequence is re-started from the master (see Figure 180 below). Figure 180. Interleaved conversion with injection ,QMHFWHGWULJJHU 5HVXPH DOZD\VRQPDVWHU &+ $'& PDVWHU &+ $'& VODYH &+ &+ 6DPSOLQJ &+ UHDG &'5 /HJHQG &+ &+ &+ UHDG &'5 &+ &+ FRQYHUVLRQV DERUWHG &+ &+ UHDG &'5 &RQYHUVLRQ &+ UHDG &'5 069 Alternate trigger mode This mode is selected by programming bits DUAL[4:0] = 01001. This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC. This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0. Injected discontinuous mode disabled (JDISCEN=0 for both ADC) 924/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 1. When the 1st trigger occurs, all injected master ADC channels in the group are converted. 2. When the 2nd trigger occurs, all injected slave ADC channels in the group are converted. 3. And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted. A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted. JEOC interrupts, if enabled, can also be generated after each injected conversion. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected channels of the master ADC in the group. Figure 181. Alternate trigger: injected group of each ADC -(2&RQ PDVWHU$'& VWWULJJHU -(2&RQ PDVWHU$'& -(2&-(26RQ PDVWHU$'& 0$67(5$'& 6/$9($'& QGWULJJHU -(2&RQ VODYH$'& UGWULJJHU -(2&RQ VODYH$'& -(2&-(26RQ VODYH$'& -(2&RQ PDVWHU$'& -(2&RQ PDVWHU$'& -(2&-(26RQ PDVWHU$'& 0$67(5$'& 6/$9($'& WKWULJJHU -(2&RQ VODYH$'& -(2&RQ VODYH$'& -(2&-(26RQ VODYH$'& 6DPSOLQJ &RQYHUVLRQ DL P Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion. It is resumed when the injected conversion is finished. The time interval between 2 trigger events must be greater than or equal to 1 ADC clock period. The minimum time interval between 2 trigger events that start conversions on the same ADC is the same as in the single ADC mode. Injected discontinuous mode enabled (JDISCEN=1 for both ADC) DocID029587 Rev 3 925/3178 979 Analog-to-digital converters (ADC) RM0433 If the injected discontinuous mode is enabled for both master and slave ADCs: • When the 1st trigger occurs, the first injected channel of the master ADC is converted. • When the 2nd trigger occurs, the first injected channel of the slave ADC is converted. • And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted. A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted. JEOC interrupts, if enabled, can also be generated after each injected conversions. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts. Figure 182. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode VWWULJJHU UGWULJJHU WKWULJJHU WKWULJJHU -(2&-(26RQ -(2&RQ -(2&RQ -(2&RQ PDVWHU$'& PDVWHU$'& PDVWHU$'& PDVWHU$'& 0$67(5$'& 6/$9($'& -(2&RQ PDVWHU$'& QGWULJJHU -(2&RQ PDVWHU$'& WKWULJJHU -(2&RQ PDVWHU$'& WKWULJJHU WKWULJJHU -(2&-(26RQ PDVWHU$'& 6DPSOLQJ &RQYHUVLRQ DL9P Combined regular/injected simultaneous mode This mode is selected by programming bits DUAL[4:0] = 00001. It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group. Note: The sequences must be converted with the same length, the N-th conversion in master and slave mode must be configured with the same sampling time inside a given sequence, or the interval between triggers has to be longer than the long conversion time of the 2 sequences. If the above conditions are not respected, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Combined regular simultaneous + alternate trigger mode This mode is selected by programming bits DUAL[4:0]=00010. It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. Figure 183 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion. The injected alternate conversion is immediately started after the injected event. If a regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion. 926/3178 DocID029587 Rev 3 RM0433 Note: Analog-to-digital converters (ADC) The sequences must be converted with the same length, the N-th conversion in master and slave mode must be configured with the same sampling time inside a given sequence, or the interval between triggers has to be longer than the long conversion time of the 2 sequences. If the above conditions are not respected, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Figure 183. Alternate + regular simultaneous VWWULJJHU $'&0$67(5UHJ &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ $'&0$67(5LQM $'&6/$9(UHJ &+ &+ &+ &+ &+ $'&6/$9(LQM V\QFKURQRWORVW QGWULJJHU DL9P If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 184 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete). Figure 184. Case of trigger occurring during injected conversion VWWULJJHU $'&0$67(5UHJ &+ &+ &+ &+ $'&0$67(5LQM $'&6/$9(UHJ $'&6/$9(LQM UGWULJJHU &+ &+ &+ &+ &+ &+ &+ &+ WKWULJJHU &+ &+ &+ QGWULJJHU &+ &+ &+ &+ &+ &+ &+ &+ WKWULJJHU WKWULJJHU LJQRUHG DL9 Combined injected simultaneous plus interleaved This mode is selected by programming bits DUAL[4:0]=00011 It is possible to interrupt an interleaved conversion with a simultaneous injected event. Caution: In this case the interleaved conversion is interrupted immediately and the simultaneous injected conversion starts. At the end of the injected sequence the interleaved conversion is resumed. When the interleaved regular conversion resumes, the first regular conversion which is performed is alway the master’s one. Figure 185, Figure 186 and Figure 187 show the behavior using an example. In this mode, it is mandatory to use the Common Data Register to read the regular data with a single read access. On the contrary, master-slave data coherency is not guaranteed. DocID029587 Rev 3 927/3178 979 Analog-to-digital converters (ADC) RM0433 Figure 185. Interleaved single channel CH0 with injected sequence CH11, CH12 $'& PDVWHU &+ &+ $'& VODYH &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU &RQYHUVLRQ 069 Figure 186. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first $'& PDVWHU &+ &+ $'& VODYH &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU &RQYHUVLRQ 069 Figure 187. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first $'& PDVWHU &+ $'& VODYH &+ &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 928/3178 &RQYHUVLRQ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU 069 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 188: DMA Requests in regular simultaneous mode when DAMDF=0b00). Figure 188. DMA Requests in regular simultaneous mode when DAMDF=0b00 7ULJJHU $'&0DVWHUUHJXODU 7ULJJHU &+ &+ $'&0DVWHU(2& $'&6ODYHUHJXODU &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP$'&0DVWHU '0$UHDGV0DVWHU $'&B'5 '0$UHDGV0DWHU $'&B'5 '0$UHTXHVWIURP$'&6ODYH '0$UHDGV6ODYH $'&B'5 '0$UHDGV6ODYH $'&B'5 &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this DAMDF bits must be configured in the ADCx_CCR register: • DAMDF=0b10, 32-bit format: A single DMA request is generated alternatively when either the master or slave EOC events have occurred. At that time, the data items are alternatively available in the ADCx_CDR2 32-bit register. This mode is used in interleaved mode and in regular simultaneous mode when resolution is above 16-bit. Example: Interleaved dual mode: a DMA request is generated each time a new 32-bit data is available: 1st DMA request: ADCx_CDR2[31:0] = MST_ADCx_DR[31:0] 2nd DMA request: ADCx_CDR2[31:0] = SLV_ADCx_DR[31:0] • DAMDF=0b10, 16-bit format: A single DMA request is generated each time both master and slave EOC events have occurred. At that time, two data items are available and the 32-bit register ADCx_CDR contains the two half-words representing two ADC- DocID029587 Rev 3 929/3178 979 Analog-to-digital converters (ADC) RM0433 converted data items. The slave ADC data take the upper half-word and the master ADC data take the lower half-word. This mode is used in interleaved mode and in regular simultaneous mode when resolution is ranging from 10 to 16-bit. Any value above 16-bit in the master or the slave converter will be truncated to the least 16 significant bits. Example: Interleaved dual mode: a DMA request is generated each time 2 data items are available: 1st DMA request: ADCx_CDR[31:0] = SLV_ADCx_DR[15:0] | MST_ADCx_DR[15:0] 2nd DMA request: ADCx_CDR[31:0] = SLV_ADCx_DR[15:0] | MST_ADCx_DR[15:0] Figure 189. DMA requests in regular simultaneous mode when DAMDF=0b10 7ULJJHU $'&0DVWHUUHJXODU 7ULJJHU &+ 7ULJJHU &+ 7ULJJHU &+ &+ $'&6ODYH(2& $'&6ODYHUHJXODU &+ &+ &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP $'&0DVWHU '0$UHTXHVWIURP $'&6ODYH &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 930/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 190. DMA requests in interleaved mode when DAMDF=0b10 7ULJJHU $'&0DVWHUUHJXODU $'&0DVWHU(2& 7ULJJHU &+ &+ $'&6ODYHUHJXODU &+ &+ &+ 'HOD\ 'HOD\ 'HOD\ 'HOD\ &+ 7ULJJHU 7ULJJHU 7ULJJHU &+ &+ 'HOD\ &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP $'&0DVWHU '0$UHTXHVWIURP $'&6ODYH &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 Note: When using Multi ADC mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. • DAMDF=0b11: This mode is similar to the DAMDF=0b10. The only differences are that on each DMA request (two data items are available), two bytes representing two ADC converted data items are transferred as a half-word. This mode is used in interleaved and regular simultaneous mode when the result is 8bit. A new DMA request is issued when 4 new 8-bit values are available. Example: Interleaved dual mode: a DMA request is generated each time 4 data items are available (t0, t1,... are corresponding to the consecutive sampling instants) 1st DMA request: ADCx_CDR[7:0] = MST_ADCx_DR[7:0]t0 ADCx_CDR[15:8] = SLV_ADCx_DR[7:0]t0 ADCx_CDR[23:16] = MST_ADCx_DR[7:0]t1 ADCx_CDR[31:24] = SLV_ADCx_DR[7:0]t1 2nd DMA request: ADCx_CDR[7:0] = MST_ADCx_DR[7:0]t2 ADCx_CDR[15:8] = SLV_ADCx_DR[7:0]t2 ADCx_CDR[23:16] = MST_ADCx_DR[7:0]t3 ADCx_CDR[31:24] = SLV_ADCx_DR[7:0]t3 Overrun detection In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on one of the ADCs, the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid (this behavior occurs whatever the DAMDF configuration). DocID029587 Rev 3 931/3178 979 Analog-to-digital converters (ADC) RM0433 It may happen that the EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data. DMA one shot mode/ DMA circular mode when Multi ADC mode is selected When DAMDF mode is selected (0b10 or 0b11), bit DMNGT[1:0]=0b10 in the master ADC’s ADCx_CCR register must also be configured to select between DMA one shot mode and circular mode, as explained in section Section : Managing conversions using the DMA. Stopping the conversions in dual ADC modes The user must set the control bits ADSTP/JADSTP of the master ADC to stop the conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC has no effect in dual ADC mode. Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and slave ADCs are both cleared by hardware. DFSDM mode in dual ADC mode interleaved mode In dual ADC interleaved modes, the ADC conversion results can be transferred directly to the Digital Filter for Sigma Delta Modulators (DFSDM). This mode is enabled by setting the bits DMNGT[1:0] = 0b10 in the master ADC’s ADCx_CFGR register. The ADC transfers alternatively the 16 least significant bits of the regular data register from the master and the slave converter to a single channel of the DFSDM. The data format must be 16-bit signed: ADCx_DR[31:16] = 0x0000 ADCx_DR[15] = sign ADCx_DR[14:0] = data Any value above 16-bit signed format in any converter will be truncated. DFSDM mode in dual ADC simultaneous mode The dual mode is not required to use DFSDM in dual ADC simultaneous mode since conversion data will be treated by each individual channel. Single mode with same trigger source results in simultaneous conversion with DFSDM interface. 25.3.33 Temperature sensor The temperature sensor can measure the junction temperature (TJ) of the device in the –40 to 125 °C temperature range. The temperature sensor is internally connected to ADC3 VINP[18] input channel which is used to convert the sensor’s output voltage to a digital value. The sampling time for the temperature sensor’s analog pin must be greater than the stabilization time specified in the product datasheet. When not in use, the sensor can be put in power-down mode. Figure 191 shows the block diagram of the temperature sensor. 932/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Figure 191. Temperature sensor channel block diagram FRQYHUWHG GDWD $'&[ 7HPSHUDWXUH VHQVRU 96(16( $GGUHVVGDWDEXV 96(16((1FRQWURO ELW $'&LQSXW 06Y9 Note: The VSENSEEN bit must be set to enable the conversion of internal channel ADC3 VINP[18] (temperature sensor, VSENSE). Reading the temperature To use the sensor: 1. Select the ADC3 VINP[18] input channels (with the appropriate sampling time). 2. Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet). 3. Set the VSENSEEN bit in the ADCx_CCR register to wake up the temperature sensor from power-down mode. 4. Start the ADC conversion. 5. Read the resulting VSENSE data in the ADC data register. 6. Calculate the actual temperature using the following formula: 110 °C – 30 °C Temperature ( in °C ) = ---------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + 30 °C TS_CAL2 – TS_CAL1 Where: • TS_CAL2 is the temperature sensor calibration value acquired at 110°C • TS_CAL1 is the temperature sensor calibration value acquired at 30°C • TS_DATA is the actual temperature sensor output value converted by ADC Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points. Note: The sensor has a startup time after waking from power-down mode before it can output VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and SENSEEN bits should be set at the same time. 25.3.34 VBAT supply monitoring The VBATEN bit in the ADCx_CCR register is used to switch to the battery voltage. As the VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider by 4. This bridge is automatically enabled when VBATEN is set, to connect VBAT/4 to the ADC3 VINP[17]input channels. As a consequence, the converted digital value is one fourth of the VBAT voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion. DocID029587 Rev 3 933/3178 979 Analog-to-digital converters (ADC) RM0433 Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the VBAT/4 voltage. Figure 192 shows the block diagram of the VBAT sensing feature. Figure 192. VBAT channel block diagram 9%$7 $GGUHVVGDWDEXV 9%$7(1FRQWUROELW $'&[ 9%$7 $'&LQSXW 06Y9 Note: The VBATEN bit must be set to enable the conversion of internal channels ADC3 VINP[17] (VBAT/4). 25.3.35 Monitoring the internal voltage reference The internal voltage reference can be monitored to have a reference point for evaluating the ADC VREF+ voltage level. The internal voltage reference is internally connected to the input channel ADC3 VINP[19]. The sampling time for this channel must be greater than the stabilization time specified in the product datasheet. Figure 192 shows the block diagram of the VREFINT sensing feature. Figure 193. VREFINT channel block diagram 95()(1FRQWUROELW ,QWHUQDOSRZHU EORFN 95(),17 $'&[ $'&LQSXW 06Y9 Note: 934/3178 The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels ADC3 VINP[19] (VREFINT). DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Calculating the actual VDDA voltage using the internal reference voltage The VDDA power supply voltage applied to the microcontroller may be subject to variation or not precisely known. The embedded internal voltage reference (VREFINT) and its calibration data acquired by the ADC during the manufacturing process at VDDA = 3.3 V can be used to evaluate the actual VDDA voltage level. The following formula gives the actual VDDA voltage supplying the device: VDDA = 3.3 V x VREFINT_CAL / VREFINT_DATA Where: • VREFINT_CAL is the VREFINT calibration value • VREFINT_DATA is the actual VREFINT output value converted by ADC Converting a supply-relative ADC measurement to an absolute voltage value The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of VDDA. For applications where VDDA is known and ADC converted values are right-aligned you can use the following formula to get this absolute value: V DDA V CHANNELx = ------------------------------------- × ADCx_DATA FULL_SCALE For applications where VDDA value is not known, you must use the internal voltage reference and VDDA can be replaced by the expression provided in Section : Calculating the actual VDDA voltage using the internal reference voltage, resulting in the following formula: 3.3 V × VREFINT_CAL × ADCx_DATA V CHANNELx = -------------------------------------------------------------------------------------------------------VREFINT_DATA × FULL_SCALE Where: Note: • VREFINT_CAL is the VREFINT calibration value • ADCx_DATA is the value measured by the ADC on channel x (right-aligned) • VREFINT_DATA is the actual VREFINT output value converted by the ADC • FULL_SCALE is the maximum digital value of the ADC output. For example with 16-bit resolution, it will be 216 - 1 = 65535 or with 8-bit resolution, 28 - 1 = 255. If ADC measurements are done using an output format other than 16-bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done. DocID029587 Rev 3 935/3178 979 Analog-to-digital converters (ADC) 25.4 RM0433 ADC interrupts For each ADC, an interrupt can be generated: • After ADC power-up, when the ADC is ready (flag ADRDY) • On the end of any conversion for regular groups (flag EOC) • On the end of a sequence of conversion for regular groups (flag EOS) • On the end of any conversion for injected groups (flag JEOC) • On the end of a sequence of conversion for injected groups (flag JEOS) • When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3) • When the end of sampling phase occurs (flag EOSMP) • When the data overrun occurs (flag OVR) • When the injected sequence context queue overflows (flag JQOVF) Separate interrupt enable bits are available for flexibility. Table 202. ADC interrupts per each ADC Interrupt event Event flag Enable control bit ADRDY ADRDYIE End of conversion of a regular group EOC EOCIE End of sequence of conversions of a regular group EOS EOSIE End of conversion of a injected group JEOC JEOCIE End of sequence of conversions of an injected group JEOS JEOSIE Analog watchdog 1 status bit is set AWD1 AWD1IE Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE EOSMP EOSMPIE OVR OVRIE JQOVF JQOVFIE ADC ready End of sampling phase Overrun Injected context queue overflows 936/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5 ADC registers (for each ADC) Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. 25.5.1 ADC x interrupt and status register (ADCx_ISR) (x=1 to 3) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. AWD2 AWD1 JEOS JEOC OVR EOS EOC rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 JQOVF AWD3 rc_w1 rc_w1 EOSMP ADRDY rc_w1 rc_w1 Bits 31:11 Reserved, must be kept at reset value. Bit 10 JQOVF: Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 25.3.22: Queue of context for injected conversions for more information. 0: No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software) 1: Injected context queue overflow has occurred Bit 9 AWD3: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADCx_TR3 register. It is cleared by software writing 1 to it. 0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 3 event occurred Bit 8 AWD2: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADCx_TR2 register. It is cleared by software writing 1 to it. 0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 2 event occurred Bit 7 AWD1: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADCx_TR1 register. It is cleared by software. writing 1 to it. 0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 1 event occurred Bit 6 JEOS: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 1: Injected conversions complete DocID029587 Rev 3 937/3178 979 Analog-to-digital converters (ADC) RM0433 Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADCx_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADCx_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1: Injected channel conversion complete Bit 4 OVR: ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. 0: No overrun occurred (or the flag event was already acknowledged and cleared by software) 1: Overrun has occurred Bit 3 EOS: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. 0: Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software) 1: Regular Conversions sequence complete Bit 2 EOC: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADCx_DR register. It is cleared by software writing 1 to it or by reading the ADCx_DR register 0: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1: Regular channel conversion complete Bit 1 EOSMP: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. 0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 1: End of sampling phase reached Bit 0 ADRDY: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 1: ADC is ready to start conversion 938/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.2 ADC x interrupt enable register (ADCx_IER) (x=1 to 3) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. JQOVF AWD3 AWD2 AWD1 JEOSIE JEOCIE OVRIE IE IE IE IE rw rw rw rw rw rw rw EOSIE rw EOSMP ADRDY EOCIE IE IE rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 JQOVFIE: Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. 0: Injected Context Queue Overflow interrupt disabled 1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). Bit 9 AWD3IE: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. 0: Analog watchdog 3 interrupt disabled 1: Analog watchdog 3 interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 8 AWD2IE: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. 0: Analog watchdog 2 interrupt disabled 1: Analog watchdog 2 interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 7 AWD1IE: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. 0: Analog watchdog 1 interrupt disabled 1: Analog watchdog 1 interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. 0: JEOS interrupt disabled 1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). DocID029587 Rev 3 939/3178 979 Analog-to-digital converters (ADC) RM0433 Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing). Bit 4 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. 0: Overrun interrupt disabled 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 3 EOSIE: End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. 0: EOS interrupt disabled 1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 2 EOCIE: End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. 0: EOC interrupt disabled. 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. 0: EOSMP interrupt disabled. 1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 0 ADRDYIE: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. 0: ADRDY interrupt disabled 1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 940/3178 DocID029587 Rev 3 RM0433 25.5.3 Analog-to-digital converters (ADC) ADC x control register (ADCx_CR) (x=1 to 3) Address offset: 0x08 Reset value: 0x2000 0000 31 ADCA L 30 ADCA LDIF 29 28 27 26 LINCA LINCA DEEP ADVREG LRDY LRDY PWD EN W6 W5 25 24 LINCA LRDY W4 23 22 LINCAL LINCAL LINCAL RDYW3 RDYW2 RDYW1 rs rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. BOOST Res. Res. rw 21 20 19 18 17 16 Res. Res. Res. Res. Res. ADCAL LIN 5 4 3 2 1 0 ADDIS ADEN rs rs rw JADSTP ADSTP rs rs JADST ADSTA ART RT rs rs Bit 31 ADCAL: ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. 0: Calibration complete 1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress. Note: Software is allowed to launch a calibration by setting ADCAL only when ADEN=0. Note: Software is allowed to update the calibration factor by writing ADCx_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing) Bit 30 ADCALDIF: Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. 0: Writing ADCAL will launch a calibration in Single-ended inputs Mode. 1: Writing ADCAL will launch a calibration in Differential inputs Mode. Note: Software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 29 DEEPPWD: Deep-power-down enable This bit is set and cleared by software to put the ADC in deep-power-down mode. 0: ADC not in deep-power down 1: ADC in deep-power-down (default reset state) Note: Software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 28 ADVREGEN: ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. 0: ADC Voltage regulator disabled 1: ADC Voltage regulator enabled. For more details about the ADC voltage regulator enable and disable sequences, refer to Section 25.3.6: ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). DocID029587 Rev 3 941/3178 979 Analog-to-digital converters (ADC) RM0433 Bit 27 LINCALRDYW6: Linearity calibration ready Word 6 This control / status bit allows to read/write the 6th linearity calibration factor. When the linearity calibration is complete, this bit is set. A bit clear will launch the transfer of the linearity factor 6 into the LINCALFACT[29:0] of the ADCx_CALFACT2 register. The bit will be reset by hardware when the ADCx_CALFACT2 register can be read (software must poll the bit until it is cleared). When the LINCALRDYW6 bit is reset, a new linearity factor 6 value can be written into the LINCALFACT[29:0] of the ADCx_CALFACT2 register. A bit set will launch the linearity factor 6 update and the bit will be effectively set by hardware once the update will be done (software must poll the bit until it is set to indicate the write is effective). Note: ADCx_CALFACT2[29:10] contains 0. ADCx_CALFACT2[9:0] corresponds linearity correction factor bits[159:150]. Software is allowed to toggle this bit only if the LINCALRDYW5, LINCALRDYW4, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged, see chapter 25.3.8: Calibration (ADCAL, ADCALDIF, ADCALLIN, ADCx_CALFACT) for details. Software is allowed to update the linearity calibration factor by writing LINCALRDYWx only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing) Bit 26 LINCALRDYW5: Linearity calibration ready Word 5 Refer to LINCALRDYW6 description. Note: ADCx_CALFACT2[29:0] corresponds linearity correction factor bits[149:120]. Software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged. Bit 25 LINCALRDYW4: Linearity calibration ready Word 4 Refer to LINCALRDYW6 description. Note: ADCx_CALFACT2[29:0] correspond linearity correction factor bits[119:90]. Software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged. Bit 24 LINCALRDYW3: Linearity calibration ready Word 3 Refer to LINCALRDYW6 description. Note: ADCx_CALFACT2[29:0] corresponds linearity correction factor bits[89:60]. Software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged. Bit 23 LINCALRDYW2: Linearity calibration ready Word 2 Refer to LINCALRDYW6 description. Note: ADCx_CALFACT2[29:0] corresponds linearity correction factor bits[59:30]. Software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW1 bits are left unchanged. Bit 22 LINCALRDYW1: Linearity calibration ready Word 1 Refer to LINCALRDYW6 description. Note: ADCx_CALFACT2[29:0] corresponds linearity correction factor bits[29:0]. Software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW2 bits are left unchanged. Bits 21:17 Reserved, must be kept at reset value. 942/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bit 16 ADCALLIN: Linearity calibration This bit is set and cleared by software to enable the Linearity calibration. 0: Writing ADCAL will launch a calibration without the Linearity calibration. 1: Writing ADCAL will launch a calibration with he Linearity calibration. Note: Software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 15:9 Reserved, must be kept at reset value. Bit 8 BOOST: Boost mode control This bit is set and cleared by software to enable/disable the Boost mode. 0: Boost mode off. Used when ADC clock < 20 MHz to save power at lower clock frequency. 1: Boost mode on. Must be used when ADC clock > 20 MHz. Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit BOOST of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC. Bits 7:6 Reserved, must be kept at reset value. Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). 0: No ADC stop injected conversion command ongoing 1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress. Note: Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP) Bit 4 ADSTP: ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). 0: No ADC stop regular conversion command ongoing 1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress. Note: Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master ADC must be used to stop regular conversions. The other ADSTP bit is inactive. DocID029587 Rev 3 943/3178 979 Analog-to-digital converters (ADC) RM0433 Bit 3 JADSTART: ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: – in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. – in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. 0: No ADC injected conversion is ongoing. 1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel. Note: Software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 944/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: – in single conversion mode (CONT=0, DISCEN=0) when software trigger is selected (EXTEN=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. – In discontinuous conversion mode (CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=0x0): at the end of conversion (EOC) flag. – in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. 0: No ADC regular conversion is ongoing. 1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel. Note: Software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) Bit 1 ADDIS: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). 0: no ADDIS command ongoing 1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. Note: Software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing) Bit 0 ADEN: ADC enable control This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. 0: ADC is disabled (OFF state) 1: Write 1 to enable the ADC. Note: Software is allowed to set ADEN only when all bits of ADCx_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator) DocID029587 Rev 3 945/3178 979 Analog-to-digital converters (ADC) 25.5.4 RM0433 ADC x configuration register (ADCx_CFGR) (x=1 to 3) Address offset: 0x0C Reset value: 0x8000 0000 31 30 29 JQDIS 28 27 26 25 24 23 22 JAWD1 AWD1 AWD1S JAUTO EN EN GL AWD1CH[4:0] 21 20 JQM JDISC EN 19 18 17 16 DISC EN DISCNUM[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. AUT DLY CONT OVR MOD rw rw rw EXTEN[1:0] rw rw EXTSEL[4:0] rw rw rw RES[2:0] rw rw rw rw DMNGT[1:0] rw rw rw Bit 31 JQDIS: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism: 0: Injected Queue enabled 1: Injected Queue disabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. 00000: ADC analog input channel-0 monitored by AWD1 00001: ADC analog input channel-1 monitored by AWD1 ..... 10010: ADC analog input channel-19 monitored by AWD1 others: reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 25 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: Automatic injected group conversion disabled 1: Automatic injected group conversion enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC. Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on injected channels 1: Analog watchdog 1 enabled on injected channels Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). 946/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on regular channels 1: Analog watchdog 1 enabled on regular channels Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels 0: Analog watchdog 1 enabled on all channels 1: Analog watchdog 1 enabled on a single channel Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 21 JQM: JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. 0: JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR. 1: JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence. Refer to Section 25.3.22: Queue of context for injected conversions for more information. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC. Bit 20 JDISCEN: Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC. Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels ... 111: 8 channels Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC. DocID029587 Rev 3 947/3178 979 Analog-to-digital converters (ADC) RM0433 Bit 16 DISCEN: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. 0: Discontinuous mode for regular channels disabled 1: Discontinuous mode for regular channels enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC. Bit 15 Reserved, must be kept at reset value. Bit 14 AUTDLY: Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. 0: Auto-delayed conversion mode off 1: Auto-delayed conversion mode on Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC. Bit 13 CONT: Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC. Bit 12 OVRMOD: Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. 0: ADCx_DR register is preserved with the old data when an overrun is detected. 1: ADCx_DR register is overwritten with the last conversion result when an overrun is detected. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. 00: Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). 948/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bits 9:5 EXTSEL[4:0]: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: 00000: Event 0 00001: Event 1 00010: Event 2 00011: Event 3 00100: Event 4 00101: Event 5 00110: Event 6 00111: Event 7 ... 11111: Event 31 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bits 4:2 RES[2:0]: Data resolution These bits are written by software to select the resolution of the conversion. 000: 16-bit 001: 14-bit 010: 12-bit 011: 10-bit 100: 8-bit All other codes reserved Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 1:0 DMNGT[1:0]: Data Management configuration This bit is set and cleared by software to select how ADC interface output data are managed. 00: Regular conversion data stored in DR only 01: DMA One Shot Mode selected 10: DFSDM mode selected 11: DMA Circular Mode selected Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). In dual-ADC modes, this bit is not relevant and replaced by control bit DAMDF of the ADCx_CCR register. DocID029587 Rev 3 949/3178 979 Analog-to-digital converters (ADC) 25.5.5 RM0433 ADC x configuration register 2 (ADCx_CFGR2) (x=1 to 3) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 LSHIFT[3:0] 27 26 Res. Res. 10 rw rw rw rw 15 14 13 12 11 Res. RSHIF T4 RSHIF T3 RSHIF T2 RSHIF T1 rw rw rw rw 25 24 22 21 20 19 18 17 16 OSR[9:0] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. ROVSM TROVS rw 23 rw OVSS[3:0] rw rw rw rw JOVSE ROVSE rw rw Bits 31:28 LSHIFT[3:0]: Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. 0000: No left shift 0001: Shift left 1-bit 0010: Shift left 2-bits 0011: Shift left 3-bits 0100: Shift left 4-bits 0101: Shift left 5-bits 0110: Shift left 6-bits 0111: Shift left 7-bits 1000: Shift left 8-bits 1001: Shift left 9-bits 1010: Shift left 10-bits 1011: Shift left 11-bits 1100: Shift left 12-bits 1101: Shift left 13-bits 1101: Shift left 14-bits 1111: Shift left 15-bits Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 27:26 Reserved, must be kept at reset value. Bits 25:16 OSR[9:0]: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 0: 1x (no oversampling) 1: 2x 2: 3x ... 1023: 1024x Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 15 Reserved, must be kept at reset value. Bit 14 RSHIFT4: Right-shift data after Offset 4 correction Refer to RSHIFT1 description. 950/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bit 13 RSHIFT3: Right-shift data after Offset 3 correction Refer to RSHIFT1 description Bit 12 RSHIFT2: Right-shift data after Offset 2 correction Refer to RSHIFT1 description Bit 11 RSHIFT1: Right-shift data after Offset 1 correction This bitfield is set and cleared by software to right-shift 1-bit data after offset1 correction. This bit can only be used for 8-bit and 16-bit data format (see Section : Data register, data alignment and offset (ADCx_DR, ADCx_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). 0: Right-shifting disabled 1: Data is right-shifted 1-bit. Bit 10 ROVSM: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. 0: Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 9 TROVS: Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling 0: All oversampled conversions for a channel are done consecutively following a trigger 1: Each oversampled conversion for a channel needs a new trigger Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 8:5 OVSS[3:0]: Oversampling right shift This bit field is set and cleared by software to define the right shifting applied to the raw oversampling result. 0000: No right shift 0001: Shift right 1-bit 0010: Shift right 2-bits 0011: Shift right 3-bits 0100: Shift right 4-bits 0101: Shift right 5-bits 0110: Shift right 6-bits 0111: Shift right 7-bits 1000: Shift right 8-bits 1001: Shift right 9-bits 1010: Shift right 10-bits 1011: Shift right 11-bits Other codes reserved Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). DocID029587 Rev 3 951/3178 979 Analog-to-digital converters (ADC) RM0433 Bits 4:2 Reserved, must be kept at reset value. Bit 1 JOVSE: Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. 0: Injected Oversampling disabled 1: Injected Oversampling enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing) Bit 0 ROVSE: Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. 0: Regular Oversampling disabled 1: Regular Oversampling enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing) 25.5.6 ADC x sample time register 1 (ADCx_SMPR1) (x=1 to 3) Address offset: 0x14 Reset value: 0x0000 0000 31 Res. 30 29 Res. 15 14 SMP5[0] rw 28 27 SMP9[2:0] 25 24 23 SMP8[2:0] 22 21 20 SMP7[2:0] 19 18 SMP6[2:0] 17 16 SMP5[2:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw SMP4[2:0] rw 26 rw SMP3[2:0] rw SMP2[2:0] rw SMP1[2:0] rw SMP0[2:0] rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. 000: 1.5 ADC clock cycles 001: 2.5 ADC clock cycles 010: 8.5 ADC clock cycles 011: 16.5 ADC clock cycles 100: 32.5 ADC clock cycles 101: 64.5 ADC clock cycles 110: 387.5.5 ADC clock cycles 111: 810.5 ADC clock cycles Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 952/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.7 ADC x sample time register 2 (ADCx_SMPR2) (x=1 to 3) Address offset: 0x18 Reset value: 0x0000 0000 31 30 Res. Res. 15 14 SMP15[0] rw 29 28 27 25 24 23 SMP18[2:0] 22 21 20 SMP17[2:0] 19 18 SMP16[2:0] 17 16 SMP15[2:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw SMP14[2:0] rw 26 SMP19[2:0] rw SMP13[2:0] rw SMP12[2:0] rw SMP11[2:0] rw SMP10[2:0] rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. 000: 1.5 ADC clock cycles 001: 2.5 ADC clock cycles 010: 8.5 ADC clock cycles 011: 16.5 ADC clock cycles 100: 32.5 ADC clock cycles 101: 64.5 ADC clock cycles 110: 387.5 ADC clock cycles 111: 810.5 ADC clock cycles Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). DocID029587 Rev 3 953/3178 979 Analog-to-digital converters (ADC) 25.5.8 RM0433 ADC x channel preselection register (ADCx_PCSEL) (x=1 to 3) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 19 18 17 16 PCSEL19 PCSEL18 PCSEL17 PCSEL16 rw rw rw rw 3 2 1 0 PCSEL PCSEL PCSEL PCSEL PCSEL PCSEL PCSEL9 PCSEL8 PCSEL7 PCSEL6 PCSEL5 PCSEL4 PCSEL3 PCSEL2 PCSEL1 PCSEL0 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:0 PCSELx: Channel x (V ) pre selection INP[i] These bits are written by software to pre select the input channel at IO instance to be converted. 0: Input Channel x (Vinp x) is not pre selcted for conversion, the ADC conversion result with this channel shows wrong result. 1: Input Channel x (Vinp x) is pre selcted for conversion Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 25.5.9 ADC x watchdog threshold register 1 (ADCx_LTR1) (x=1 to 3) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 25 24 23 22 21 20 19 18 17 16 LTR1[25:16] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw LTR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:0 LTR1[25:0]: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to Section 25.3.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 954/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.10 ADC x watchdog threshold register 1 (ADCx_HTR1) (x=1 to 3) Address offset: 0x24 Reset value: 0x03FF FFFF 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 25 24 23 22 21 20 19 18 17 16 HTR1[25:16] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw HTR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:0 HTR1[25:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 25.3.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). DocID029587 Rev 3 955/3178 979 Analog-to-digital converters (ADC) 25.5.11 RM0433 ADC x regular sequence register 1 (ADCx_SQR1) (x=1 to 3) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 28 26 25 24 SQ4[4:0] rw rw rw rw rw 11 10 9 8 rw rw Res. rw 23 22 21 Res. 12 SQ2[3:0] rw 27 19 18 rw rw rw rw rw 7 6 5 4 3 2 Res. Res. rw rw rw rw SQ1[4:0] rw 20 SQ3[4:0] 17 16 Res. SQ2[4] rw 1 0 rw rw L[3:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the regular conversion sequence. Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 17 Reserved, must be kept at reset value. Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bits 5:4 Reserved, must be kept at reset value. Bits 3:0 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ... 1111: 16 conversions Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). 956/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.12 ADC x regular sequence register 2 (ADCx_SQR2) (x=1 to 3) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 28 26 25 24 SQ9[4:0] rw rw rw rw rw 11 10 9 8 rw rw Res. rw 23 22 21 Res. 12 SQ7[3:0] rw 27 19 18 rw rw rw rw rw 7 6 5 4 3 2 rw rw rw rw SQ6[4:0] rw 20 SQ8[4:0] Res. 17 16 Res. SQ7[4] rw 1 0 rw rw SQ5[4:0] rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 9th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 8th in the regular conversion sequence Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 17 Reserved, must be kept at reset value. Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 7th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 6th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 Reserved, must be kept at reset value. Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 5th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). DocID029587 Rev 3 957/3178 979 Analog-to-digital converters (ADC) 25.5.13 RM0433 ADC x regular sequence register 3 (ADCx_SQR3) (x=1 to 3) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 28 26 25 24 SQ14[4:0] rw rw rw rw rw 11 10 9 8 rw rw Res. rw 23 22 21 Res. 12 SQ12[3:0] rw 27 19 18 rw rw rw rw rw 7 6 5 4 3 2 rw rw rw rw SQ11[4:0] rw 20 SQ13[4:0] Res. 17 16 Res. SQ12[4] rw 1 0 rw rw SQ10[4:0] rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 14th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 13th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 17 Reserved, must be kept at reset value. Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 12th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 11th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 Reserved, must be kept at reset value. Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 10th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). 958/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.14 ADC x regular sequence register 4 (ADCx_SQR4) (x=1 to 3) Address offset: 0x3C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. rw rw rw rw rw rw rw rw SQ16[4:0] rw Res. SQ15[4:0] rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 16th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 Reserved, must be kept at reset value. Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 15th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). DocID029587 Rev 3 959/3178 979 Analog-to-digital converters (ADC) 25.5.15 RM0433 ADC x regular Data Register (ADCx_DR) (x=1 to 3) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDATA[15:0] r r r r r r r r r Bits 31:0 RDATA[31:0]: Regular Data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in Section 25.3.27: Data management. 960/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.16 ADC x injected sequence register (ADCx_JSQR) (x=1 to 3) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 JSQ4[4:0] rw rw rw rw rw 15 14 13 12 11 JSQ2[0] Res. rw rw rw 26 25 24 Res. 22 21 rw rw rw rw rw 9 8 7 6 5 rw rw rw rw JEXTEN[1:0] rw 20 19 Res. 10 JSQ1[4:0] rw 23 JSQ3[4:0] 4 18 17 rw rw rw rw 3 2 1 0 rw rw rw JEXTSEL[4:0] rw 16 JSQ2[4:1] JL[1:0] rw Bits 31:27 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bit 26 Reserved, must be kept at reset value. Bits 25:21 JSQ3[4:0]: 3rd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bit 20 Reserved, must be kept at reset value. Bits 19:15 JSQ2[4:0]: 2nd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bit 14 Reserved, must be kept at reset value. Bits 13:9 JSQ1[4:0]: 1st conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). DocID029587 Rev 3 961/3178 979 Analog-to-digital converters (ADC) RM0433 Bits 8:7 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled 00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Section 25.3.22: Queue of context for injected conversions) Bits 6:2 JEXTSEL[4:0]: External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: 00000: Event 0 00001: Event 1 00010: Event 2 00011: Event 3 00100: Event 4 00101: Event 5 00110: Event 6 00111: Event 7 ... 11111: Event 31: Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bits 1:0 JL[1:0]: Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). 962/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.17 ADC x offset register (ADCx_OFRy) (x=1 to 3) Address offset: 0x60 + 0x04 * (y-1), y= 1 to 4 Reset value: 0x0000 0000 31 30 SSATE 29 28 27 26 25 24 23 22 OFFSETy_CH[4:0] 21 20 19 18 17 16 OFFSETy[25:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw OFFSETy[15:0] rw rw Bit 31 SSATE: Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see Section : Data register, data alignment and offset (ADCx_DR, ADCx_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). 0: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format). 1: Offset is subtracted and result is saturated to maintain result size. Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 30:26 OFFSETy_CH[4:0]: Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 25:0 OFFSETy[25:0]: Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADCx_DR (regular conversion) or from in the ADCx_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4. DocID029587 Rev 3 963/3178 979 Analog-to-digital converters (ADC) 25.5.18 RM0433 ADC x injected data register (ADCx_JDRy) (x=1 to 3) Address offset: 0x80 + 0x04 * (y-1), y= 1 to 4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 JDATA[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r JDATA[15:0] r Bits 31:0 JDATA[31:0]: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 25.3.27: Data management. 25.5.19 ADC x Analog Watchdog 2 Configuration Register (ADCx_AWD2CR) (x=1 to 3) Address offset: 0xA0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw AWD2CH[19:16] AWD2CH[15:0] rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:0 AWD2CH[19:0]: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 964/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.20 ADC x Analog Watchdog 3 Configuration Register (ADCx_AWD3CR) (x=1 to 3) Address offset: 0xA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw AWD3CH[19:16] AWD3CH[15:0] rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:0 AWD2CH[19:0]: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 25.5.21 ADC x watchdog lower threshold register 2 (ADCx_LTR2) (x=1 to 3) Address offset: 0xB0 Reset value: 0x0000 0000 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 25 24 23 22 21 20 19 18 17 16 LTR2[25:16] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw LTR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:0 LTR2[25:0]: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to Section 25.3.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). DocID029587 Rev 3 965/3178 979 Analog-to-digital converters (ADC) 25.5.22 RM0433 ADC x watchdog higher threshold register 2 (ADCx_HTR2) (x=1 to 3) Address offset: 0xB4 Reset value: 0x03FF FFFF 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 25 24 23 22 21 rw rw rw rw rw 9 8 7 6 5 rw rw 20 19 18 17 16 rw rw rw rw rw 4 3 2 1 0 rw rw rw rw rw HTR2[25:16] HTR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:0 HTR2[25:0]: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to Section 25.3.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 25.5.23 ADC x watchdog lower threshold register 3 (ADCx_LTR3) (x=1 to 3) Address offset: 0xB8 Reset value: 0x0000 0000 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 25 24 23 22 21 20 19 18 17 16 LTR3[25:16] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw LTR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:0 LTR3[25:0]: Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to Section 25.3.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 966/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 25.5.24 ADC x watchdog higher threshold register 3 (ADCx_HTR3) (x=1 to 3) Address offset: 0xBC Reset value: 0x03FF FFFF 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 rw rw rw rw rw rw rw rw rw rw 20 19 18 17 16 rw rw rw rw rw 4 3 2 1 0 rw rw rw rw rw HTR3[25:16] HTR3[15:0] rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:0 HTR3[25:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to Section 25.3.30: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 25.5.25 ADC x Differential Mode Selection register (ADCx_DIFSEL) (x=1 to 3) Address offset: 0xC0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DIFSEL[19:16] DIFSEL[15:0] rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:0 DIFSEL[19:0]: Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow to select if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). DocID029587 Rev 3 967/3178 979 Analog-to-digital converters (ADC) 25.5.26 RM0433 ADC x Calibration Factors register (ADCx_CALFACT) (x=1 to 3) Address offset: 0xC4 Reset value: 0x0000 0000 31 30 29 28 27 Res. Res. Res. Res. Res. 15 14 13 12 11 Res. Res. Res. Res. Res. 26 25 24 23 22 21 20 19 18 17 16 CALFACT_D[10:0] rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw CALFACT_S[10:0] rw rw rw rw rw rw rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:16 CALFACT_D[10:0]: Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential calibration is launched. Note: Software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Bits 15:11 Reserved, must be kept at reset value. Bits 10:0 CALFACT_S[10:0]: Calibration Factors In Single-Ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. Note: Software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). 25.5.27 ADC x Calibration Factor register 2 (ADCx_CALFACT2) (x=1 to 3) Address offset: 0xC8 Reset value: 0x0000 0000 31 30 Res. Res. 15 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LINCALFACT[29:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw LINCALFACT[15:0] rw 968/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 LINCALFACT[29:0]: Linearity Calibration Factor These bits are written by hardware or by software. They hold 30-bit out of the 160-bit linearity calibration factor. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. Note: Software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). DocID029587 Rev 3 969/3178 979 Analog-to-digital converters (ADC) 25.6 RM0433 ADC common registers These registers define the control and status registers common to master and slave ADCs: 25.6.1 ADC x common status register (ADCx_CSR) (x=12 or 3) Address offset: 0x00 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing 0 to it in the corresponding ADCx_ISR register. ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately. 31 30 Res. Res. 15 14 Res. Res. 29 28 27 26 25 24 21 20 19 18 17 16 EOS_ SLV EOC_ SLV EOSMP_ SLV ADRDY_ SLV Res. r r r r r r r r r r r 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. JQOVF_ MST OVR_ MST EOS_ MST EOC_ MST EOSMP_ MST ADRDY_ MST r r r r r r r AWD1_ MST JEOS_ JEOC_ SLV SLV OVR_ SLV Res. AWD3_ AWD2_ MST MST AWD1_ SLV 22 Res. r AWD3_ AWD2_ SLV SLV 23 JQOVF_ SLV JEOS_ JEOC_ MST MST r r r Bits 31:27 Reserved, must be kept at reset value. Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADCx+1_ISR register. Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register. Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register. Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register. Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register. Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register. Bit 20 OVR_SLV: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register. Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register. Bit 18 EOC_SLV: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register. Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register. 970/3178 DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bit 16 ADRDY_SLV: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register. Bits 15:11 Reserved, must be kept at reset value. Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADCx_ISR register. Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADCx_ISR register. Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADCx_ISR register. Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADCx_ISR register. Bit 6 JEOS_MST: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADCx_ISR register. Bit 5 JEOC_MST: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADCx_ISR register. Bit 4 OVR_MST: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADCx_ISR register. Bit 3 EOS_MST: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADCx_ISR register. Bit 2 EOC_MST: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADCx_ISR register. Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADCx_ISR register. Bit 0 ADRDY_MST: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx_ISR register. DocID029587 Rev 3 971/3178 979 Analog-to-digital converters (ADC) 25.6.2 RM0433 ADC x common control register (ADCx_CCR) (x=12 or 3) Address offset: 0x08 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 Res. Res. DAMDF[1:0] rw rw 24 rw rw 22 21 20 19 18 PRESC[3:0] 17 CKMODE[1:0] rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 Res. Res. Res. rw rw rw DUAL[4:0] rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 VBATEN: VBAT enable This bit is set and cleared by software to control VBAT channel. 0: VBAT channel disabled 1: VBAT channel enabled Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 23 VSENSEEN: Temperature sensor voltage enable This bit is set and cleared by software to control VSENSE channel. 0: Temperature sensor channel disabled 1: Temperature sensor channel enabled Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 22 VREFEN: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel. 0: VREFINT channel disabled 1: VREFINT channel enabled Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 972/3178 16 rw DELAY[3:0] rw 23 VSENSE VBATEN VREFEN EN DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) Bits 21:18 PRESC[3:0]: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 0000: input ADC clock not divided 0001: input ADC clock divided by 2 0010: input ADC clock divided by 4 0011: input ADC clock divided by 6 0100: input ADC clock divided by 8 0101: input ADC clock divided by 10 0110: input ADC clock divided by 12 0111: input ADC clock divided by 16 1000: input ADC clock divided by 32 1001: input ADC clock divided by 64 1010: input ADC clock divided by 128 1011: input ADC clock divided by 256 other: reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. Bits 17:16 CKMODE[1:0]: ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): 00: CK_ADCx (x=1 to 3) (Asynchronous clock mode), generated at product level (refer to Section Reset and Clock Control (RCC)) 01: adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle. 10: adc_hclk/2 (Synchronous clock mode) 11: adc_hclk/4 (Synchronous clock mode) In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 15:14 DAMDF[1:0]: Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register ADCx_CDR. 00: Dual ADC mode without data packing (ADCx_CDR and ADCx_CDR2 registers not used). 01: Reserved 10: Data formatting mode for 32 down to 10-bit resolution 11: Data formatting mode for 8-bit resolution Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bits 13:12 Reserved, must be kept at reset value. DocID029587 Rev 3 973/3178 979 Analog-to-digital converters (ADC) RM0433 Bits 11:8 DELAY: Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 203 for the value of ADC resolution versus DELAY bits values. Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DUAL[4:0]: Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs independent: 00000: Independent mode 00001 to 01001: Dual mode, master and slave ADCs working together 00001: Combined regular simultaneous + injected simultaneous mode 00010: Combined regular simultaneous + alternate trigger mode 00011: Combined Interleaved mode + injected simultaneous mode 00100: Reserved 00101: Injected simultaneous mode only 00110: Regular simultaneous mode only 00111: Interleaved mode only 01001: Alternate trigger mode only All other combinations are reserved and must not be programmed Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Table 203. DELAY bits versus ADC resolution DELAY bits 14-bit resolution 12-bit resolution 10-bit resolution 8-bit resolution 0000 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 1.5 * Tadc_ker_ck 0001 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 2.5 * Tadc_ker_ck 0010 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 3.5 * Tadc_ker_ck 0011 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 0100 5.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 0101 6.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 0110 7.5 * Tadc_ker_ck 7.5 * Tadc_ker_ck 6.5 * Tadc_ker_c 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 0111 8.5 * Tadc_ker_ck 7.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck 1000 8.5 * Tadc_ker_ck 7.5 * Tadc_ker_ck 6.5 * Tadc_ker_ck 5.5 * Tadc_ker_ck 4.5 * Tadc_ker_ck others: reserved 974/3178 16-bit resolution - - DocID029587 Rev 3 - - - RM0433 Analog-to-digital converters (ADC) 25.6.3 ADC x common regular data register for dual mode (ADCx_CDR) (x=12 or 3) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA_SLV[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r RDATA_MST[15:0] r r Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 25.3.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADCx_DR, ADCx_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE)) Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to Section 25.3.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADCx_DR, ADCx_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE)) In MDMA=0b11 mode, bits 15:8 contains SLV_ADCx_DR[7:0], bits 7:0 contains MST_ADCx_DR[7:0]. 25.6.4 ADC x common regular data register for 32-bit dual mode (ADCx_CDR2) (x=12 or 3) Address offset: 0x10 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 ADC1 and ADC2 are controlled by the same interface, while ADC3 is controlled separately. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDATA_ALT[31:16] RDATA_ALT[15:0] r r r r r r r r r DocID029587 Rev 3 975/3178 979 Analog-to-digital converters (ADC) RM0433 Bits 31:0 RDATA_ALT[31:0]: Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to Section 25.3.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADCx_DR, ADCx_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE). 25.6.5 ADC register map The following table summarizes the ADC registers. Table 204. ADC global register map Offset Register 0x000 - 0x0D0 Master ADC1 or Master ADC3 0x0D4 - 0x0FC Reserved 0x100 - 0x1D0 Slave ADC2 0x1D4 - 0x2FC Reserved 0x300 - 0x310 Master and slave ADCs common registers (ADC12 or ADC3) AWD3 AWD2 AWD1 JEOS JEOC OVR EOS EOC EOSMP ADRDY Res. JQOVF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_ISR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 Register name Res. Offset Res. Table 205. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) 0 0 0 0 0 0 0 0 0 0 0 JQOVFIE AWD3IE AWD2IE AWD1IE JEOSIE JEOCIE OVRIE EOSIE EOCIE EOSMPIE ADRDYIE 0 0 0 0 0 0 0 0 0 0 0 Res. BOOST Res. Res. JADSTP ADSTP JADSTART ADSTART ADDIS ADEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_IER 0x04 Res. Reset value 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. ADCALLIN Res. LINCALRDYW1 Res. LINCALRDYW2 Res. LINCALRDYW3 Reset value 1 0 0 0 0 0 ADCx_CFGR2 SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:0] SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Reset value 976/3178 0 Res. 0 Res. Res. 0 Res. ADCx_SMPR2 0 0 0 0 0 0 0 0 SMP17 [2:0] 0 0 0 0 0 0 SMP16 [2:0] 0 0 0 0 0 0 0 SMP15 [2:0] 0 0 DocID029587 Rev 3 0 EXTEN[1:0] 0 0 0 0 0 0 0 0 0 SMP14 [2:0] 0 0 0 0 0 0 SMP13 [2:0] 0 0 0 0 0 0 OVSS[3:0] 0 0 0 0 0 0 SMP12 [2:0] 0 0 0 0 0 0 0 0 JOVSE 0 0 ROVSE 0 0 Res. 0 0 DMN GT [1:0] RES [2:0] Res. 0 0 EXTSEL [4:0] Res. 0 0 TROVS 0 0 ROVSM 0 0 RSHIFT1 0 OVRMOD 0 RSHIFT2 0 CONT 0 OSR[9:0] SMP18 [2:0] 0 0 RSHIFT3 0 AUTDLY JDISCEN 0 RSHIFT4 JQM 0 Res. AWD1SGL 0 0 Res. AWD1EN 0 DISCNUM [2:0] DISCEN JAWD1EN 0 0 Res. ADCx_SMPR1 0 JAUTO AWD1CH[4:0] Reset value 0x18 Res. LINCALRDYW4 ADCx_CFGR Reset value 0x14 Res. LINCALRDYW5 0 Res. LINCALRDYW6 0 Res. DEEPPWD ADVREGEN 0 Res. 0 Res. ADCAL 0 JQDIS. 0 Res. 0 Res. 1 Res. 0 Reset value Res. 0x10 0 ADCx_CR 0x08 0x0C ADCALDIF Reset value 0 0 0 0 0 0 SMP11 [2:0] 0 0 0 0 0 0 SMP10 [2:0] 0 0 0 RM0433 Analog-to-digital converters (ADC) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Res. 0 0 0 0 SQ12[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 SQ1[4:0] 0 0 0 0 SQ6[4:0] 0 0 0 0 0 0 0 SQ16[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 SQ5[4:0] 0 0 0 L[3:0] 0 0 SQ11[4:0] 0 0 0 0 0 0 0 0 JSQ2[4:0] 0 0 0 0 JSQ1[4:0] 0 0 0 0 0 SQ10[4:0] 0 0 0 0 0 SQ15[4:0] 0 0 0 0 0 0 0 0 0 0 0 JEXTSEL[4:0] JL[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. ADCx_OFR2 Reset value 0 ADCx_OFR3 Reset value 0 0 0 0 0 0 0 0 OFFSET1[25:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET2[25:0] Reset value 0 OFFSET3[25:0] ADCx_OFR1 OFFSET1_CH[4:0] Reserved 0 JEXTEN[1:0] JSQ3[4:0] Res. Res. JSQ4[4:0] SSATE 0x68 0 Res. ADCx_JSQR SSATE 0x64 0 Res. SSATE 0x60 0 Reserved Reset value 0x500x5C 0 RDATA[31:0] OFFSET2_CH[4:0] 0x4C ADCx_DR Reset value 0 0 0 Res. 0 0 1 0 SQ7[4:0] 0 Res. 0 0 Res. Res. SQ13[4:0] 0 0 Res. Res. 0 0 Res. Res. 0 1 Res. 0 0 Res. 0 0 1 SQ2[4:0] 0 Res. SQ8[4:0] 0 Res. 0 0 Res. 0 Res. SQ14[4:0] 0 0 Res. Res. 0 0 Res. 0 0 1 OFFSET3_CH[4:0] 0x440x48 0 Res. 1 Reset value 0x40 0 Res. 1 Res. 0 Res. 0 0 Res. 1 SQ3[4:0] 0 Res. Res. 0 SQ9[4:0] Res. Res. ADCx_SQR4 Res. 0x3C Res. Reset value 0 Res. ADCx_SQR3 Res. 0x38 SQ4[4:0] 0 Res. Reset value 0 Res. 1 Res. Res. Res. Res. Res. Res. ADCx_SQR2 0 Res. 1 Res. 0x34 0 Res. 1 Reserved 0 PCSEL0 0 0x2C 0 PCSEL1 0 Res. 0 0 HTR1[25:0] 1 Reset value PCSEL2 0 Reserved ADCx_SQR1 PCSEL3 0 0x28 0x30 0 Res. Reset value PCSEL4 PCSEL11 PCSEL10 0 PCSEL5 PCSEL12 0 Res. PCSEL13 0 PCSEL6 PCSEL14 0 Res. PCSEL15 0 PCSEL7 PCSEL16 0 PCSEL8 PCSEL17 0 PCSEL9 PCSEL18 Res. 0 Res. Res. Res. Res. Res. 0x24 0 LTR1[25:0] 0 Res. Reset value ADCx_HTR1 0 Res. Res. Res. Res. Res. 0x20 Res. Reset value ADCx_LTR1 PCSEL19 Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_PCSEL Res. 0x1C Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 205. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) DocID029587 Rev 3 977/3178 979 Analog-to-digital converters (ADC) RM0433 0 0 0 OFFSET4[25:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 978/3178 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 DIFSEL[19:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. 0 0 0 0 CALFACT_S[10:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 CALFACT_D[10:0] Res. Res. 1 Res. Res. 1 Res. Res. 1 Res. 1 Res. 1 Res. 1 Res. 1 Res. 1 Res. 1 Res. HTR3[25:0] 0 0 0 0 0 0 Res. Res. Res. Res. Res. LINCALFACT[29:0] 0 Res. Reserved 0 Res. 1 Res. 0x0D Res. Reserved Res. Reset value 0xCC 0 Res. Res. 0xC8 0 AWD3CH[19:0] 0 Reset value ADCx_ CALFACT2 0 Res. 0 Reset value ADCx_CALFACT 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value ADCx_DIFSEL Res. Res. Res. Res. Res. Res. 0xBC 0 LTR3[25:0] 0 Res. Reset value ADCx_HTR3 Res. Res. Res. Res. Res. Res. Res. Res. 0xB8 0 HTR2[25:0] 1 Res. Reset value ADCx_LTR3 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xB4 0 LTR2[25:0] 0 Res. Reset value ADCx_HTR2 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_LTR2 0xB0 0 AWD2CH[19:0] 0 Res. Reserved 0 Res. Reset value 0xA80xAC 0 JDATA4[31:0] Reset value ADCx_AWD3CR 0 JDATA3[31:0] Reserved ADCx_AWD2CR 0 Res. Reset value 0 JDATA2[31:0] ADCx_JDR4 0x8C0x9C 0 JDATA1[31:0] 0 ADCx_JDR3 Reset value 0 Res. Reset value 0 Res. ADCx_JDR2 0x8C 0xC4 0 Res. Reset value 0x88 0xC0 0 ADCx_JDR1 0x84 0xA4 0 Reserved 0x80 0xA0 Reset value Res. 0x700x7C ADCx_OFR4 OFFSET4_CH[4:0] 0x6C SSATE Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 205. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) DocID029587 Rev 3 RM0433 Analog-to-digital converters (ADC) 0x10 ADCx_CDR Reset value 0 0 0 0 0 0 0 0 EOSMP_MST ADRDY_MST 0 0 DELAY[3:0] Res. Res. Res. Res. 0 DMACFG 0 DAMDF[1:0] VREFEN 0 PRESC[3:0] 0 0 RDATA_SLV[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUAL[4:0] 0 0 0 0 0 RDATA_MST[15:0] 0 0 ADCx_CDR2 Reset value EOS_MST 0 EOC_MST 0 OVR_MST AWD1_MST 0 master ADC1 CKMODE[1:0] VSENSEEN Res. VBATEN Res. Res. Res. Res. ADCx_CCR Reset value 0x0C 0 Res. Res. 0x08 0 Reserved Res. 0x04 0 JEOS_MST AWD2_MST 0 slave ADC2 Reset value JEOC_MST AWD3_MST Res. JQOVF_MST 0 Res. 0 Res. ADRDY_SLV 0 Res. EOSMP_SLV 0 Res. EOS_SLV 0 EOC_SLV 0 OVR_SLV AWD1_SLV 0 JEOS_SLV AWD2_SLV 0 JEOC_SLV AWD3_SLV Res. JQOVF_SLV Res. Res. ADCx_CSR Res. 0x00 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 206. ADC register map and reset values (master and slave ADC common registers) offset =0x300) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA_ALT[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID029587 Rev 3 979/3178 979 Digital-to-analog converter (DAC) RM0433 26 Digital-to-analog converter (DAC) 26.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, VREF+ (shared with others analog peripherals) is available for better resolution. An internal reference can also be set on the same input. Refer to voltage reference buffer (VREFBUF) section. The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC output is disconnected from output pad and connected to on chip peripheral. The DAC output buffer can be optionally enabled to allow a high drive output current. An individual calibration can be applied on each DAC output channel. The DAC output channels support a low power mode; the Sample and Hold mode. 26.2 DAC main features The DAC main features are the following (see Figure 194: DAC channel block diagram) • Two DAC interfaces, maximum two output channels each • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave and Triangular-wave generation • Dual DAC channel for independent or simultaneous conversions • DMA capability for each channel including DMA underrun error detection • External triggers for conversion • DAC output channel buffered/unbuffered modes • buffer offset calibration • Each DAC output can be disconnected from the DAC_OUTx output pin • DAC output connection to on chip peripherals • Sample and Hold mode for low power operation in Stop mode • Input voltage reference from VREF+ pin or internal VREFBUF reference Figure 194 shows the block diagram of a DAC channel and Table 207 gives the pin description. 980/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) 26.3 DAC functional description 26.3.1 DAC block diagram Figure 194. DAC channel block diagram 9''$ GDFBFKBWUJ 75,* '$&B287 2IIVHW FDOLEUDWLRQ 275,0> @ ELWV 02'(ELWV GDFBFKBWUJ 76(/ > @ ELWV %XIIHU '$& FRQYHUWHU '25 ELW GDFBFKBGPD 6DPSOH +ROG UHJLVWHUV 76$03/( &RQWUROUHJLVWHUV ORJLF&KDQQHO OVLBFN GDFBXQUBLW GDFBRXW 7+2/' 75()5(6+ 95() 2IIVHW FDOLEUDWLRQ 275,0> @ ELWV &RQWUROUHJLVWHUV ORJLF&KDQQHO GDFBFKBGPD 02'(ELWV 76(/ > @ ELWV ELW 6DPSOH +ROG UHJLVWHUV 76$03/( 75,* GDFBFKBWUJ %XIIHU '$& FRQYHUWHU '25 GDFBFKBWUJ '$&B287 ELW$3% EXV GDFBSFON OVLBFN 7+2/' GDFBRXW 75()5(6+ 966$ 06Y9 1. The output mode controller switches between the Normal mode in buffer/unbuffered configuration and the Sample and Hold mode. DocID029587 Rev 3 981/3178 1013 Digital-to-analog converter (DAC) 26.3.2 RM0433 DAC pins and internal signals The DAC includes: • Up to two output channels • The DAC_OUTx can be disconnected from the output pin and used as an ordinary GPIO • The dac_outx can use an internal pin connection to on-chip peripherals such as comparators and OPAMPs. • DAC output channel buffered or non buffered • Sample and Hold block and registers using LSI clock source and operational in Stop mode for static conversion The DAC includes up to two separate output channels. Each output channel can be connected to on-chip peripherals such as COMP, OPAMP and ADC. In this case, the DAC output channel can be disconnected from the DAC_OUTx output pin and the corresponding GPIO can be used for another purpose. The DAC output can be buffered or not. The Sample and Hold block and its associated registers can run in Stop mode using the LSI clock source. Table 207. DAC input/output pins Pin name Signal type Remarks VREF+ Input, analog reference positive The higher/positive reference voltage for the DAC, VREF+ ≤ VDDAmax (refer to datasheet) VDDA Input, analog supply Analog power supply VSSA Input, analog supply ground Ground for analog power supply DAC_OUTx Analog output signal DAC channelx analog output Table 208. DAC internal input/output signals Internal signal name Signal type 982/3178 Description dac_ch1_dma Bidirectional DACx channel 1 DMA request dac_ch2_dma Bidirectional DACx channel 2 DMA request dac_ch1_trg[0:15] Inputs DACx channel 1 dac_ch2_trg[0:15] Inputs DACx channel 2 dac_unr_it Output DACx underrun interrupt dac_pclk Input dac_out1 Analog output DACx channel 1 output for on-chip peripherals dac_out2 Analog output DACx channel 2 output for on-chip peripherals DACx peripheral clock DocID029587 Rev 3 RM0433 26.3.3 Digital-to-analog converter (DAC) DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DACx_CR register. The DAC channel is then enabled after a tWAKEUP startup time. Note: The ENx bit enables the analog DAC Channelx only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. 26.3.4 DAC data format Depending on the selected configuration mode, the data have to be written into the specified register as described below: • Single DAC channelx, there are three possibilities: – 8-bit right alignment: the software has to load data into the DACx_DHR8Ry[7:0] bits (stored into the DHRy[11:4] bits) – 12-bit left alignment: the software has to load data into the DACx_DHR12Ly [15:4] bits (stored into the DHRy[11:0] bits) – 12-bit right alignment: the software has to load data into the DACx_DHR12Ry [11:0] bits (stored into the DHRx[11:0] bits) Depending on the loaded DACx_DHRyyyw register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal nonmemory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger. Figure 195. Data registers in single DAC channel mode ELWULJKWDOLJQHG ELWOHIWDOLJQHG ELWULJKWDOLJQHG DLE • Dual DAC channels (when available), there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DACx_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DACx_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) – 12-bit left alignment: data for DAC channel1 to be loaded into the DACx_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DACx_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits) – 12-bit right alignment: data for DAC channel1 to be loaded into the DACx_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DACx_DHR12RD [27:16] bits (stored into the DHR2[11:0] bits) Depending on the loaded DACx_DHRyyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memorymapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DocID029587 Rev 3 983/3178 1013 Digital-to-analog converter (DAC) RM0433 DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger. Figure 196. Data registers in dual DAC channel mode ELWULJKWDOLJQHG ELWOHIWDOLJQHG ELWULJKWDOLJQHG DL E 26.3.5 DAC conversion The DACx_DORy cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DACx_DHRy register (write to DACx_DHR8Ry, DACx_DHR12Ly, DACx_DHR12Ry, DACx_DHR8RD, DACx_DHR12RD or DACx_DHR12LD). Data stored in the DACx_DHRy register are automatically transferred to the DACx_DORy register after one dac_pclk clock cycle, if no hardware trigger is selected (TENx bit in DACx_CR register is reset). However, when a hardware trigger is selected (TENx bit in DACx_CR register is set) and a trigger occurs, the transfer is performed three dac_pclk clock cycles after the trigger signal. When DACx_DORy is loaded with the DACx_DHRy contents, the analog output voltage becomes available after a time tSETTLING that depends on the power supply voltage and the analog output load. Figure 197. Timing diagram for conversion with trigger disabled TEN = 0 GDFBSFON '+5 '25 [$& [$& /UTPUT VOLTAGE AVAILABLE ON $!#?/54 PIN W6(77/,1* 06 9 26.3.6 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+. The analog output voltages on each DAC channel pin are determined by the following equation: DOR DACoutput = V REF × -------------4096 984/3178 DocID029587 Rev 3 RM0433 26.3.7 Digital-to-analog converter (DAC) DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 possible events will trigger conversion as shown in bits TSEL1[3:0] and TSEL2[3:0] in Section 26.6.1: DAC x control register (DACx_CR) (x=1 to 2). Each time a DAC interface detects a rising edge on the selected trigger source (refer to the table below), the last data stored into the DACx_DHRy register are transferred into the DACx_DORy register. The DACx_DORy register is updated three dac_pclk cycles after the trigger occurs. If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DACx_DORy register has been loaded with the DACx_DHRy register contents. Note: TSELx[3:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DACx_DHRy register to the DACx_DORy register takes only one dac_pclk clock cycle. Table 209. DAC trigger selection Source Type TSELx[3:0] SWTRIG Software control bit 0000 TIM1_TRGO Internal signal from on-chip timers 0001 TIM2_TRGO Internal signal from on-chip timers 0010 TIM4_TRGO Internal signal from on-chip timers 0011 TIM5_TRGO Internal signal from on-chip timers 0100 TIM6_TRGO Internal signal from on-chip timers 0101 TIM7_TRGO Internal signal from on-chip timers 0110 TIM8_TRGO Internal signal from on-chip timers 0111 TIM15_TRGO Internal signal from on-chip timers 1000 HRTIM1_DACTRG1 Internal signal from on-chip timers 1001 HRTIM1_DACTRG2 Internal signal from on-chip timers 1010 LPTIM1_OUT Internal signal from on-chip timers 1011 LPTIM2_OUT Internal signal from on-chip timers 1100 EXTI9 External pin 1101 Reserved - 1110 Reserved - 1111 DocID029587 Rev 3 985/3178 1013 Digital-to-analog converter (DAC) 26.3.8 RM0433 DMA requests Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the value of the DACx_DHRy register is transferred into the DACx_DORy register when the transfer is complete, and a DMA request is generated. In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, only the corresponding DMAENx bit should be set. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel. As DACx_DHRy to DACx_DORy data transfer occurred before the DMA request, the very first data has to written to the DACx_DHRy before the first trigger event occurs. DMA underrun The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgment for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DACx_SR register is set, reporting the error condition. The DAC channelx continues to convert old data. The software should clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by enabling both DMA data transfer and conversion trigger. For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DACx_CR register is enabled. 26.3.9 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01”. The preloaded value in LFSR is 0xAAA. This register is updated three dac_pclk clock cycles after each trigger event, following a specific calculation algorithm. 986/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) Figure 198. DAC LFSR register calculation algorithm ;25 ; ; ; ; ; 125 DLF The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DACx_CR register, is added up to the DACx_DHRy contents without overflow and this value is then transferred into the DACx_DORy register. If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism). It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits. Figure 199. DAC conversion (SW trigger enabled) with LFSR wave generation GDFBSFON '+5 [ '25 [$$$ [' 6:75,* 069 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DACx_CR register. 26.3.10 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”. The amplitude is configured through the MAMPx[3:0] bits in the DACx_CR register. An internal triangle counter is incremented three dac_pclk clock cycles after each trigger event. The value of this counter is then added to the DACx_DHRy register without overflow and the sum is transferred into the DACx_DORy register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured DocID029587 Rev 3 987/3178 1013 Digital-to-analog converter (DAC) RM0433 amplitude is reached, the counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 200. DAC triangle wave generation N TIO EN EM EN EM CR TA $E -!-0X;= MAX AMPLITUDE $!#?$(2X BASE VALUE )N CR N TIO TA $!#?$(2X BASE VALUE AIC Figure 201. DAC conversion (SW trigger enabled) with triangle wave generation GDFBSFON '+5 [$%( '25 [$%( [$%) [$& 6:75,* 069 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DACx_CR register. The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. 26.3.11 DAC channel modes Each DAC channel can be configured in Normal mode or Sample and Hold mode. The output buffer can be enabled to allow a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation. Normal mode In Normal mode, there are four combinations, by changing the buffer state and by changing the DAC_OUTx pin interconnections. To enable the output buffer, the MODEx[2:0] bits in DACx_MCR register should be: 988/3178 • 000: DAC is connected to the external pin • 001: DAC is connected to external pin and to on-chip peripherals DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) To disable the output buffer, the MODEx[2:0] bits in DACx_MCR register should be: • 010: DAC is connected to the external pin • 011: DAC is connected to on-chip peripherals Sample and Hold mode In sample and Hold mode, the DAC core converts data on a triggered conversion, then, holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption. A new stabilization period (Tstab-BON or Tstab-BOFF depending on buffer state) is needed before each new conversion. In this mode, the DAC core and all corresponding logic and registers are driven by the lowspeed clock (LSI) in addition to the dac_pclk clock, allowing to use the DAC channels in deep low power modes such as Stop mode. The sample/hold mode operations can be divided into 3 phases: 1. Sample phase: the sample/hold element is charged to the desired voltage. The charging time depends on capacitor value (internal or external, selected by the user). The sampling time is configured with the TSAMx[9:0] bits in DACx_SHSRy register. During the write of the TSAMx[9:0] bits; the BWSTx bit in DACx_SR register is set to 1 to synchronize between both clocks domains (APB and low speed clock) and allowing the software to change the value of sample phase during the DAC channel operation 2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are turned off, to reduce the current consumption. The hold time is configured with the THOLDx[9:0] bits in DACx_SHHR register 3. Refresh phase: the refresh time is configured with the TREFx[7:0] bits in DACx_SHRR register The timings for the three phases above are in units of LSI clocks. As example, to configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs assuming LSI ~32 KHz is selected: 12 cycles are required for sample phase: SAMx[9:0] = 11, 62 cycles are required for hold phase: THOLDx[9:0] = 62, and 4 cycles are required for refresh period: TREFx[7:0] = 4. In this example, the power consumption is reduced by almost a factor of 15 versus Normal modes. The Formulas to compute the right sample and refresh timings are described in the table below, the Hold time depends on the leakage current. Table 210. Sample and refresh timings Buffer State tsampling (1)(3) trefresh (2)(3) Enable Tstab-BON + (10*RBON*Cload) Tstab-BON + (RBON*Cload)*ln(2*Nlsb) Disable Tstab-BOFF + (10*RBOFF*Cload) Tstab-BOFF + (RBOFF*Cload)*ln(2*Nlsb) DocID029587 Rev 3 989/3178 1013 Digital-to-analog converter (DAC) Note: RM0433 In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB error accuracy requires ln(2*Nlsb) constant time of the DAC. The parameters Tstab-BON,Tstab-BOFF, RBON and RBOFF are specified in the datasheet. Example of the sample and refresh time calculation with output buffer on Note: The values used in the example below are provided as indication only. Please refer to the product datasheet for product data. Cload = 100 nF VDDA = 3.0 V Sampling phase: tsampling = 7 μs + (10 * 2000 * 100 * 10-9) = 2.007 ms (where Tstab-BON = 7 μs, RBON = 2 kΩ) Refresh phase: trefresh = 7 μs + (2000 * 100 * 10-9) * ln(2*10) = 606.1 μs (where Nlsb = 10 (10 LSB drop during the hold phase) Hold phase: Dv = ileak * thold / Cload = 0.0073 V (10 LSB of 12bit at 3 V) ileak = 150 nA (worst case on the IO leakage on all the temperature range) thold = 0.0073 * 100 * 10-9 / (150 * 10-9) = 4.867 ms 990/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) Figure 202. DAC Sample and Hold mode phase diagram 9G OVLB FN '$& 21 21 21 06Y9 Like in Normal mode, the Sample and Hold mode has different configurations. To enable the output buffer, the MODEx[2:0] bits in DACx_MCR register should be: • 100: DAC is connected to the external pin • 101: DAC is connected to external pin and to on chip peripherals To disabled the output buffer, The MODEx[2:0] bits in DACx_MCR register should be: • 110: DAC is connected to external pin and to on chip peripherals • 111: DAC is connected to on chip peripherals When MODEx[2:0] bits in DACx_MCR register is equal to 111. An internal capacitor “Cloadint“ will hold the voltage output of the DAC Core and then drive it to on-chip peripherals. All Sample and Hold phases are interruptible and any change in DACx_DHRyDACx_ will trigger immediately a new sample phase. Table 211. Channel output modes summary MODEx[2:0] 0 0 0 0 0 1 0 1 0 0 1 1 Mode Buffer Enabled Normal mode Disabled Output connections Connected to external pin Connected to external pin and to on chip-peripherals (ex, comparators) Connected to external pin Connected to on chip peripherals (ex, comparators) DocID029587 Rev 3 991/3178 1013 Digital-to-analog converter (DAC) RM0433 Table 211. Channel output modes summary (continued) MODEx[2:0] 1 0 0 1 0 1 1 1 0 1 1 1 26.3.12 Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip peripherals (ex, comparators) Sample and Hold mode Disabled Connected to external pin and to on chip peripherals (ex, comparators) Connected to on chip peripherals (ex, comparators) DAC channel buffer calibration The transfer function for an N-bit digital-to-analog converter (DAC) is: V out = ( ( D ⁄ 2N – 1 ) × G × V ref )+V OS Where VOUT is the analog output, D is the digital input, G is the gain, Vref is the nominal fullscale voltage, and Vos is the offset voltage.For an ideal DAC channel, G = 1 and Vos = 0. Due to output buffer characteristics, the voltage offset may differ from part-to-part and introduce an absolute offset error on the analog output. To compensate the Vos, a calibration is required by a trimming technique. The calibration is only valid when the DAC channelx is operating with buffer enabled (MODEx[2:0] = 000b or 001b or 100b or 101b). if applied in other modes when the buffer is off, it has no effect. During the calibration: • The buffer output will be disconnected from the pin internal/external connections and put in tristate mode (HiZ), • The buffer will act as a comparator, to sense the middle-code value 0x800 and compare it to VREF+/2 signal through an internal bridge, then toggle its output signal to 0 or 1 depending on the comparison result (CAL_FLAGx bit) Two calibration techniques are provided: • Factory trimming (always enabled) The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in DACx_CCR register is the factory trimming value and it is loaded once DAC digital interface is reset. • User trimming The user trimming can be done when the operating conditions differs from nominal factory trimming conditions and in particular when VDD/VDDA voltage, temperature, VREF+ values change and can be done at any point during application by software. Note: Refer to the datasheet for more details of the Nominal factory trimming conditions In addition, when VDD/VDDA is removed (example the device enters in STANDBY or VBAT modes) the calibration is required. The steps to perform a user trimming calibration are as below: 992/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) 1. If the DAC channel is active, Write 0 to ENx bit in DACx_CR to disable the channel. 2. Select a mode where the buffer is enabled, by writing to DACx_MCR register, MODEx[2:0] = 000b or 001b or 100b or 101b, 3. Start the DAC channelx calibration, by setting the CENx bit in DACx_CR register to 1, 4. Apply a trimming algorithm: a) Write a code into OTRIMx[4:0] bits, starting by 00000b b) Wait for tOFFTRIMmax delay c) Check if CAL_FLAGx bit in DACx_SR is set to 1 d) if CAL_FLAGx is set to 1 the trimming code OTRIMx[4:0] is found and will be used during operation to compensate the output value, else increment OTRIMx[4:0] and repeat sub-steps from (a) to (d) again. The software algorithm may use either a successive approximation or dichotomy techniques to compute and set the content of OTRIMx[4:0] bits in a faster way, The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in DACx_CCR register. Note: A tOFFTRIMmax delay must be respected between the write to the OTRIMx[4:0] bits and the read of the CAL_FLAGx bit in DACx_SR register in order to get a correct value.This parameter is specified into datasheet electrical characteristics section. If the VDD/VDDA, VREF+ and temperature conditions will not change during the device operation while it enters more often in standby and VBAT mode, the software may store the OTRIMx[4:0] bits found in the first user calibration in the flash or in back-up registers. then to load/write them directly when the device power is back again thus avoiding to wait for a new calibration time. When CENx bit is set, it is not allowed to set ENx bit. 26.3.13 Dual DAC channel conversion (if available) To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time. For the wave generation, no accesses to DHRxxxD registers are required. As a result, two output channels can be used either independently or simultaneously. 11 possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed. All modes are described in the paragraphs below. Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2. 2. Configure different trigger sources by setting different values in the TSEL1[3:0] and TSEL2[3:0] bits. 3. Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD). DocID029587 Rev 3 993/3178 1013 Digital-to-analog converter (DAC) RM0433 When a DAC channel1 trigger arrives, the DHR1 register is transferred into DACx_DOR1 (three dac_pclk clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DACx_DOR2 (three dac_pclk clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2. 2. Configure different trigger sources by setting different values in the TSEL1[3:0] and TSEL2[3:0] bits. 3. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value in the MAMPx[3:0] bits. 4. Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD). When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). Then the LFSR2 counter is updated. Independent trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2. 2. Configure different trigger sources by setting different values in the TSEL1[3:0] and TSEL2[3:0] bits. 3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits. 4. Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD). When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). Then the LFSR2 counter is updated. Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: 994/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) 1. Set the two DAC channel trigger enable bits TEN1 and TEN2. 2. Configure different trigger sources by setting different values in the TSEL1[3:0] and TSEL2[3:0] bits. 3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum amplitude value in the MAMPx[3:0] bits. 4. Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD). When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). The DAC channel2 triangle counter is then updated. Independent trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2. 2. Configure different trigger sources by setting different values in the TSEL1[3:0] and TSEL2[3:0] bits. 3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits. 4. Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD). When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous software start To configure the DAC in this conversion mode, the following sequence is required: • Load the dual DAC channel data to the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD) In this configuration, one dac_pclk clock cycle later, the DHR1 and DHR2 registers are transferred into DACx_DOR1 and DACx_DOR2, respectively. DocID029587 Rev 3 995/3178 1013 Digital-to-analog converter (DAC) RM0433 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[3:0] and TSEL2[3:0] bits • Load the dual DAC channel data to the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD) When a trigger arrives, the DHR1 and DHR2 registers are transferred into DACx_DOR1 and DACx_DOR2, respectively (after three dac_pclk clock cycles). Simultaneous trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[3:0] and TSEL2[3:0] bits • Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value in the MAMPx[3:0] bits • Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). The LFSR2 counter is then updated. Simultaneous trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[3:0] and TSEL2[3:0] bits • Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR mask values using the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD) When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). The LFSR2 counter is then updated. 996/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[3:0] and TSEL2[3:0] bits • Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum amplitude value using the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three dac_pclk clock cycles later). The DAC channel1 triangle counter is then updated. At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[3:0] and TSEL2[3:0] bits • Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DACx_DHR12RD, DACx_DHR12LD or DACx_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DACx_DOR1 (three APB clock cycles later). Then the DAC channel1 triangle counter is updated. At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DACx_DOR2 (three dac_pclk clock cycles later). Then the DAC channel2 triangle counter is updated. DocID029587 Rev 3 997/3178 1013 Digital-to-analog converter (DAC) 26.4 RM0433 DAC low-power modes Table 212. Effect of low-power modes on DAC Mode 26.5 Description Sleep No effect, DAC can be used with DMA Stop DAC remains active with a static output value if Sample and Hold mode is selected using lsi_ck clock Standby The DAC peripheral is powered down and must be reinitialized after exiting Standby mode. DAC interrupts Table 213. DAC interrupts 26.6 Interrupt event Event flag Enable control bit DMA underrun DMAUDRx DMAUDRIEx DAC registers Refer to Section 1 on page 98 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 26.6.1 DAC x control register (DACx_CR) (x=1 to 2) Address offset: 0x00 Reset value: 0x0000 0000 31 Res. 15 Res. 30 29 28 CEN2 DMAU DRIE2 DMA EN2 rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 14 13 12 CEN1 DMAU DRIE1 DMA EN1 rw rw rw 998/3178 27 26 25 24 MAMP2[3:0] rw rw 22 WAVE2[1:0] MAMP1[3:0] rw 23 WAVE1[1:0] rw rw rw DocID029587 Rev 3 21 20 19 18 17 16 TSEL2 3 TSEL2 2 TSEL2 1 TSEL2 0 TEN2 EN2 rw rw rw rw rw rw 5 4 3 2 1 0 TSEL1 3 TSEL1 2 TSEL1 1 TSEL1 0 TEN1 EN1 rw rw rw rw rw rw RM0433 Digital-to-analog converter (DAC) Bit 31 Reserved, must be kept at reset value. Bit 30 CEN2: DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DACx_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 0: DAC channel 2 in Normal operating mode 1: DAC channel 2 in calibration mode Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 0: DAC channel2 DMA underrun interrupt disabled 1: DAC channel2 DMA underrun interrupt enabled Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software. 0: DAC channel2 DMA mode disabled 1: DAC channel2 DMA mode enabled Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bits 21:18 TSEL2[3:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Refer to the trigger selection tables for the details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). Bit 17 TEN2: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into the DACx_DHR2 register are transferred one dac_pclk clock cycle later to the DACx_DOR2 register 1: DAC channel2 trigger enabled and data from the DACx_DHR2 register are transferred three dac_pclk clock cycles later to the DACx_DOR2 register Note: When software trigger is selected, the transfer from the DACx_DHR2 register to the DACx_DOR2 register takes only one dac_pclk clock cycle. DocID029587 Rev 3 999/3178 1013 Digital-to-analog converter (DAC) RM0433 Bit 16 EN2: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Bit 15 Reserved, must be kept at reset value. Bit 14 CEN1: DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DACx_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 0: DAC channel 1 in Normal operating mode 1: DAC channel 1 in calibration mode Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel1 DMA Underrun Interrupt disabled 1: DAC channel1 DMA Underrun Interrupt enabled Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 1000/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 Refer to the trigger selection tables for the details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bit 1 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. 0: DAC channel1 trigger disabled and data written into the DACx_DHR1 register are transferred one dac_pclk clock cycle later to the DACx_DOR1 register 1: DAC channel1 trigger enabled and data from the DACx_DHR1 register are transferred three dac_pclk clock cycles later to the DACx_DOR1 register Note: When software trigger is selected, the transfer from the DACx_DHR1 register to the DACx_DOR1 register takes only one dac_pclk clock cycle. Bit 0 EN1: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0: DAC channel1 disabled 1: DAC channel1 enabled 26.6.2 DAC x software trigger register (DACx_SWTRGR) (x=1 to 2) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTRIG2 SWTRIG1 w w Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DACx_DHR2 register value has been loaded into the DACx_DOR2 register. Bit 0 SWTRIG1: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DACx_DHR1 register value has been loaded into the DACx_DOR1 register. DocID029587 Rev 3 1001/3178 1013 Digital-to-analog converter (DAC) 26.6.3 RM0433 DAC x channel1 12-bit right-aligned data holding register (DACx_DHR12R1) (x=1 to 2) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. rw rw rw rw rw rw rw rw rw rw DACC1DHR[11:0] rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1. 26.6.4 DAC x channel1 12-bit left aligned data holding register (DACx_DHR12L1) (x=1 to 2) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. rw rw rw rw rw rw rw rw rw rw DACC1DHR[11:0] rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 26.6.5 DAC x channel1 8-bit right aligned data holding register (DACx_DHR8R1) (x=1 to 2) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[7:0] rw 1002/3178 rw DocID029587 Rev 3 rw rw rw RM0433 Digital-to-analog converter (DAC) Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1. 26.6.6 DAC x channel2 12-bit right aligned data holding register (DACx_DHR12R2) (x=1 to 2) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. DACC2DHR[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2. 26.6.7 DAC x channel2 12-bit left aligned data holding register (DACx_DHR12L2) (x=1 to 2) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 3:0 Reserved, must be kept at reset value. DocID029587 Rev 3 1003/3178 1013 Digital-to-analog converter (DAC) 26.6.8 RM0433 DAC x channel2 8-bit right-aligned data holding register (DACx_DHR8R2) (x=1 to 2) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 26.6.9 Dual DAC x 12-bit right-aligned data holding register (DACx_DHR12RD) (x=1 to 2) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 rw rw rw rw rw rw 11 10 9 8 7 6 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw rw DACC2DHR[11:0] DACC1DHR[11:0] rw rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 26.6.10 Dual DAC x 12-bit left aligned data holding register (DACx_DHR12LD) (x=1 to 2) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 rw rw rw rw rw rw rw rw rw rw DACC1DHR[11:0] 1004/3178 rw rw DocID029587 Rev 3 19 18 17 16 Res. Res. Res. Res. 3 2 1 0 Res. Res. Res. Res. RM0433 Digital-to-analog converter (DAC) Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 19:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 26.6.11 Dual DAC x 8-bit right aligned data holding register (DACx_DHR8RD) (x=1 to 2) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw DACC2DHR[7:0] rw DACC1DHR[7:0] rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 26.6.12 DAC x channel1 data output register (DACx_DOR1) (x=1 to 2) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. r r r r r r r r r r DACC1DOR[11:0] r r Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. DocID029587 Rev 3 1005/3178 1013 Digital-to-analog converter (DAC) 26.6.13 RM0433 DAC x channel2 data output register (DACx_DOR2) (x=1 to 2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r 15 14 13 12 Res. Res. Res. Res. DACC2DOR[11:0] r r r r r r r Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 26.6.14 DAC x status register (DACx_SR) (x=1 to 2) Address offset: 0x34 Reset value: 0x0000 0000 31 30 CAL_ BWST2 FLAG2 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAU DR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BWST1 CAL_ FLAG1 DMAU DR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r rc_w1 Bit 31 BWST2: DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample and Hold mode enable. It is set each time the software writes the register DACx_SHSR2, It is cleared by hardware when the write operation of DACx_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 0:There is no write operation of DACx_SHSR2 ongoing: DACx_SHSR2 can be written 1:There is a write operation of DACx_SHSR2 ongoing: DACx_SHSR2 cannot be written Bit 30 CAL_FLAG2: DAC Channel 2 calibration offset status This bit is set and cleared by hardware 0: calibration trimming value is lower than the offset correction value 1: calibration trimming value is equal or greater than the offset correction value Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel2 1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate) Bit 28 Reserved, must be kept at reset value. Bit 27 Reserved, must be kept at reset value. Bits 26:16 Reserved, must be kept at reset value. 1006/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) Bit 15 BWST1: DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample and Hold mode enable and is set each time the software writes the register DACx_SHSR1, It is cleared by hardware when the write operation of DACx_SHSR1 is complete. (It takes about 3 LSI periods of synchronization). 0:There is no write operation of DACx_SHSR1 ongoing: DACx_SHSR1 can be written 1:There is a write operation of DACx_SHSR1 ongoing: DACx_SHSR1 cannot be written Bit 14 CAL_FLAG1: DAC Channel 1 calibration offset status This bit is set and cleared by hardware 0: calibration trimming value is lower than the offset correction value 1: calibration trimming value is equal or greater than the offset correction value Bit 13 DMAUDR1: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel1 1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) Bit 12 Reserved, must be kept at reset value. Bit 11 Reserved, must be kept at reset value. Bits 10:0 Reserved, must be kept at reset value. 26.6.15 DAC x calibration control register (DACx_CCR) (x=1 to 2) Address offset: 0x38 Reset value: 0x00XX 00XX 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20 19 18 17 16 1 0 OTRIM2[4:0] rw 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 Res. Res. Res. 4 3 2 OTRIM1[4:0] rw Bits 31:21 Reserved, must be kept at reset value. Bits 20:16 OTRIM2[4:0]: DAC Channel 2 offset trimming value Bits 15:5 Reserved, must be kept at reset value. Bits 4:0 OTRIM1[4:0]: DAC Channel 1 offset trimming value DocID029587 Rev 3 1007/3178 1013 Digital-to-analog converter (DAC) 26.6.16 RM0433 DAC x mode control register (DACx_MCR) (x=1 to 2) Address offset: 0x3C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18 17 16 MODE2[2:0] rw 2 1 0 MODE1[2:0] rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 Reserved, must be kept at reset value. Bit 24 Reserved, must be kept at reset value. Bits 23:19 Reserved, must be kept at reset value. Bits 18:16 MODE2[2:0]: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DACx_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: – DAC Channel 2 in Normal mode 000: DAC Channel 2 is connected to external pin with Buffer enabled 001: DAC Channel 2 is connected to external pin and to on chip peripherals with buffer enabled 010: DAC Channel 2 is connected to external pin with buffer disabled 011: DAC Channel 2 is connected to on chip peripherals with Buffer disabled – DAC Channel 2 in Sample and Hold mode 100: DAC Channel 2 is connected to external pin with Buffer enabled 101: DAC Channel 2 is connected to external pin and to on chip peripherals with Buffer enabled 110: DAC Channel 2 is connected to external pin and to on chip peripherals with Buffer disabled 111: DAC Channel 2 is connected to on chip peripherals with Buffer disabled Note: This register can be modified only when EN2=0. Bits 15:14 Reserved, must be kept at reset value. Bits 13:10 Reserved, must be kept at reset value. Bit 9 Reserved, must be kept at reset value. 1008/3178 DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) Bit 8 Reserved, must be kept at reset value. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 MODE1[2:0]: DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DACx_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: – DAC Channel 1 in Normal mode 000: DAC Channel 1 is connected to external pin with Buffer enabled 001: DAC Channel 1 is connected to external pin and to on chip peripherals with Buffer enabled 010: DAC Channel 1 is connected to external pin with Buffer disabled 011: DAC Channel 1 is connected to on chip peripherals with Buffer disabled – DAC Channel 1 in sample & hold mode 100: DAC Channel 1 is connected to external pin with Buffer enabled 101: DAC Channel 1 is connected to external pin and to on chip peripherals with Buffer enabled 110: DAC Channel 1 is connected to external pin and to on chip peripherals with Buffer disabled 111: DAC Channel 1 is connected to on chip peripherals with Buffer disabled Note: This register can be modified only when EN1=0. 26.6.17 DAC x Sample and Hold sample time register 1 (DACx_SHSR1) (x=1 to 2) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. rw rw rw rw rw rw rw rw TSAMPLE1[9:0] rw rw Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE1[9:0]: DAC Channel 1 sample Time (only valid in Sample and Hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DACx_SCR register is low, If BWSTx=1, the write operation is ignored. Note: It represents the number of LSI clocks to perform a sample phase. Sampling time = (TSAMPLE1[9:0] + 1) x LSI clock period. DocID029587 Rev 3 1009/3178 1013 Digital-to-analog converter (DAC) 26.6.18 RM0433 DAC x Sample and Hold sample time register 2 (DACx_SHSR2) (x=1 to 2) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9 8 7 6 5 4 3 2 1 0 rw rw rw rw 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. TSAMPLE2[9:0] rw rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE2[9:0]: DAC Channel 2 sample Time (only valid in Sample and Hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DACx_SR register is low, if BWSTx=1, the write operation is ignored. Note: It represents the number of LSI clocks to perform a sample phase. Sampling time = (TSAMPLE1[9:0] + 1) x LSI clock period. 26.6.19 DAC x Sample and Hold hold time register (DACx_SHHR)(x=1 to 2) Address offset: 0x48 Reset value: 0x0001 0001 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 25 24 23 22 21 20 19 18 17 16 3 2 1 0 THOLD2[9:0] rw 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. 9 8 7 6 5 4 THOLD1[9:0] rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:16 THOLD2[9:0]: DAC Channel 2 hold time (only valid in Sample and Hold mode). Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. Bits 15:10 Reserved, must be kept at reset value. Bits 9:0 THOLD1[9:0]: DAC Channel 1 hold Time (only valid in Sample and Hold mode) Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. Note: 1010/3178 These bits can be written only when the DAC channel is disabled and in Normal operating mode (when bit ENx=0 and bit CEN2x=0 in the DACx_CR register). If ENx=1 or CENx=1 the write operation is ignored. DocID029587 Rev 3 RM0433 Digital-to-analog converter (DAC) 26.6.20 DAC x Sample and Hold refresh time register (DACx_SHRR)(x=1 to 2) Address offset: 0x4C Reset value: 0x0001 0001 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 2 1 0 TREFRESH2[7:0] rw 7 6 5 4 3 TREFRESH1[7:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 TREFRESH2[7:0]: DAC Channel 2 refresh Time (only valid in Sample and Hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 TREFRESH1[7:0]: DAC Channel 1 refresh Time (only valid in Sample and Hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. Note: These bits can be written only when the DAC channel is disabled and in Normal operating mode (when bit ENx=0 and bit CEN2x=0 in the DACx_CR register). If ENx=1 or CENx=1 the write operation is ignored. DocID029587 Rev 3 1011/3178 1013 0x34 DACx_SR Reset value 0 0 0 1012/3178 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Reset value Res. Reset value Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 0 0 0 0 Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 Reset value 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR[7:0] 0 0 0 0 0 0 0 DACC2DHR[11:0] 0 0 0 0 0 0 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 0 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. 0 DACC2DHR[11:0] 0 0 0 0 0 0 0 Res. 0 Res. DACC1DHR[11:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. EN2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL13 TSEL12 TSEL11 TSEL10 TEN1 EN1 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTRIG1 DMAEN1 0 SWTRIG2 CEN1 DMAUDRIE1 0 Res. Res. WAVE2[2:0] 0 WAVE1[2:0] MAMP1[3:0] Res. 0 Res. Reset value Res. 0 Res. 0 Res. 0 Res. Reset value Res. 0 Res. Reset value Res. Reset value Res. Reset value Res. TEN2 0 Res. TSEL20 0 Res. Res. TSEL21 0 Res. Res. Res. TSEL22 0 Res. Res. Res. Res. TSEL23 0 Res. Res. Res. Res. Res. Res. DMAEN2 0 Res. Res. Res. Res. Res. Res. DMAUDRIE2 0 Res. DACC2DHR[11:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEN2 0 Res. Res. 0 DMAUDR1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CAL_FLAG1 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 BWST1 Res. Res. DACx_ DHR8RD Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. DACC2DHR[11:0] Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. 0 MAMP2[3:0] Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. DACx_ DOR2 0 Res. 0x30 Res. 0 Res. DACx_ DHR12LD Res. Reset value Res. Reset value Res. 0x2C DACx_ DOR1 Res. DACx_ DHR12RD Res. DACx_ DHR8R2 Res. DACx_ DHR12L2 Res. 0x28 DACx_ DHR12R2 Res. 0x24 DACx_ DHR8R1 Res. 0x20 DMAUDR2 0x1C DACx_ DHR12L1 Res. 0x18 DACx_ DHR12R1 Res. 0x14 DACx_ SWTRGR Res. 0x10 Res. 0x0C Res. Reset value Res. 0x08 DACx_CR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Offset name Res. 26.6.21 Res. 0x04 CAL_FLAG2 0x00 BWST2 Digital-to-analog converter (DAC) RM0433 DAC register map Table 214 summarizes the DAC registers. Table 214. DAC register map and reset values 0 0 DACC1DHR[11:0] DACC1DHR[7:0] DACC2DHR[7:0] DACC1DHR[7:0] DACC1DOR[11:0] 0 0 0 0 0 0 DACC2DOR[11:0] RM0433 Digital-to-analog converter (DAC) Reset value TREFRESH2[7:0] 0 0 0 0 0 0 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. 1 X X MODE1 [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 THOLD1[9:0] 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x4C DACx_ SHRR Res. Reset value THOLD2[9:0] X TSAMPLE2[9:0] 0 Res. 0x48 DACx_ SHHR Res. Reset value X TSAMPLE1[9:0] 0 Res. 0x44 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Reset value DACx_ SHSR2 Res. Res. Res. Res. Res. Res. Res. 0 OTRIM1[4:0] X Res. X Res. X MODE2 [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x40 DACx_ SHSR1 Res. Reset value X Res. X Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACx_MCR Res. 0x3C X Res. Reset value OTRIM2[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. DACx_CCR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x38 Register name Res. Offset Res. Table 214. DAC register map and reset values (continued) 0 0 0 0 0 TREFRESH1[7:0] 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID029587 Rev 3 1013/3178 1013 Voltage reference buffer (VREFBUF) RM0433 27 Voltage reference buffer (VREFBUF) 27.1 Introduction The STM32H7x3 devices embed a voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. 27.2 VREFBUF functional description The internal voltage reference buffer supports four voltages(2), which are configured with VRS bits in the VREFBUF_CSR register: • VRS = 000: around 2.5 V. • VRS = 001: around 2.048 V. • VRS = 010: around 1.8 V. • VRS = 011: around 1.5 V. The internal voltage reference can be configured in four different modes depending on ENVR and HIZ bits configuration. These modes are provided in the table below: Table 215. VREF buffer modes ENVR HIZ 0 0 VREFBUF buffer OFF: – VREF+ pin pulled-down to VSSA 0 1 External voltage reference mode (default value): – VREFBUF buffer OFF – VREF+ pin input mode 1 0 Internal voltage reference mode: – VREFBUF buffer ON – VREF+ pin connected to VREFBUF buffer output 1 Hold mode: – VREFBUF buffer OFF – VREF+ pin floating. The voltage is held with the external capacitor – VRR detection disabled and VRR bit keeps last state 1 VREF buffer configuration After enabling the VREFBUF by setting ENVR bit and clearing HIZ bit in the VREFBUF_CSR register, the user must wait until VRR bit is set, meaning that the voltage reference output has reached its expected value. 2. The minimum VDDA voltage depends on VRS setting, please refer to the product datasheet. 1014/3178 DocID029587 Rev 3 RM0433 Voltage reference buffer (VREFBUF) 27.3 VREFBUF registers 27.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 6 5 4 15 14 13 12 11 10 9 8 7 Res Res Res Res Res Res Res Res Res VRS[2:0] rw rw 3 2 1 0 VRR Res HIZ ENVR rw rw rw r Bits 31:7 Reserved, must be kept at reset value. Bits 6:4 VRS[2:0]: Voltage reference scale These bits select the value generated by the voltage reference buffer. 000: Voltage reference set to 2.5 V 001: Voltage reference set to 2.048 V 010: Voltage reference set to 1.8 V 011: Voltage reference set to 1.5 V Others: Reserved Bit 3 VRR: Voltage reference buffer ready 0: the voltage reference buffer output is not ready. 1: the voltage reference buffer output reached the requested level. Bit 2 Reserved, must be kept at reset value. Bit 1 HIZ: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. 0: VREF+ pin is internally connected to the voltage reference buffer output. 1: VREF+ pin is high impedance. Refer to Table 215: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. Bit 0 ENVR: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. 0: Internal voltage reference mode disable (external voltage reference mode). 1: Internal voltage reference mode (reference buffer enable or hold mode) enable. DocID029587 Rev 3 1015/3178 1016 Voltage reference buffer (VREFBUF) 27.3.2 RM0433 VREFBUF calibration control register (VREFBUF_CCR) Address offset: 0x04 Reset value: 0x0000 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res rw rw rw rw rw TRIM[5:0] rw Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 TRIM[5:0]: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. 27.3.3 VREFBUF register map The following table gives the VREFBUF register map and the reset values. Reset value DocID029587 Rev 3 HIZ 0 ENVR Res. VRR 0 1 0 TRIM[5:0] x Refer to Section 2.2.2 on page 105 for the register boundary addresses. 1016/3178 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VREFBUF_CCR 0 Res. Reset value 0x04 VRS[2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VREFBUF_CSR Res. 0x00 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 216. VREFBUF register map and reset values x x x x x RM0433 Comparator (COMP) 28 Comparator (COMP) 28.1 Introduction The device embeds two ultra-low-power comparator channels (COMP1 and COMP2). They can be used for a variety of functions including: 28.2 • wake up from low-power mode triggered by an analog signal • analog signal conditioning • cycle-by-cycle current control loop when combined with a PWM output from a timer COMP main features • Selectable inverting analog inputs: – I/O pins (different for either channel) – DAC Channel1 and Channel2 outputs – internal reference voltage and three sub multiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider) • Two I/O pins per channel selectable as non-inverting analog inputs • Programmable hysteresis • Programmable speed / consumption • Mapping of outputs to I/Os • Redirection of outputs to timer inputs for triggering: – capture events – OCREF_CLR events (for cycle-by-cycle current control) – break events for fast PWM shutdowns • Blanking of comparator outputs • Window comparator • Interrupt generation capability with wake up from Sleep and Stop modes (through the EXTI controller) • Direct interrupt output to the CPU DocID029587 Rev 3 1017/3178 1033 Comparator (COMP) RM0433 28.3 COMP functional description 28.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 203: Comparator functional block diagram. Figure 203. Comparator functional block diagram ,136(/ :,102'( FPSBLQS &KDQQHO 32/$5,7< &203B,13 &203B,13 FPSBRXW &PS FPSBLQS FRPSBZNXS FPSBLQP FRPSBRXW ,106(/ &203B,10 &203B,10 FRPSBLQP FRPSBLQP 95(),17 ó95()B&203 6&$/(1 ò95()B&203 ô95()B&203 %5*(1 ,7(1 &203B287 95()B&203 6FDOHU $)23 FPSBEON FRPSBEON FRPSBEON %/$1.,1* ')) $3%EXV FRPSBSFON &203B,13 &203B,13 &/5 &203B287 &203B287 &&,) &KDQQHO ,136(/ WRFK &203B287 32/$5,7< FPSBLQS FPSBRXW &PS FRPSBZNXS FPSBLQP FRPSBRXW ,106(/ &203B,10 &203B,10 FRPSBLQP FRPSBLQP 95(),17 *3,2DOWHUQDWH IXQFWLRQV ó95()B&203 6&$/(1 ò95()B&203 ô95()B&203 ,7(1 FPSBLW %5*(1 95()B&203 6FDOHU FPSBEON FRPSBEON FRPSBEON %/$1.,1* FRPSBLW ')) FRPSBSFON &/5 &&,) FPSBLW &203 06Y9 28.3.2 COMP pins and internal signals The I/Os used as comparator inputs must be configured in analog mode in the GPIO registers. The comparator outputs can be connected to the I/Os through their alternate functions. Refer to the product datasheet. 1018/3178 DocID029587 Rev 3 RM0433 Comparator (COMP) The outputs can also be internally redirected to a variety of timer inputs for the following purposes: • emergency shut-down of PWM signals, using BKIN and BKIN2 inputs • cycle-by-cycle current control, using ETR inputs of timers • input capture for timing measurements The comparator output can be routed simultaneously internally and to the I/O pins. Table 217. COMP input/output internal signals Signal name Signal type Description comp_inm1 Analog input Inverting input source for both COMP channels: DAC ch.1 comp_inm2 Analog input Inverting input source for both COMP channels: DAC ch.2 comp_blk1 Digital input Blanking input source for both COMP channels: TIM1 OC5 comp_blk2 Digital input Blanking input source for both COMP channels: TIM2 OC3 comp_blk3 Digital input Blanking input source for both COMP channels: TIM3 OC3 comp_blk4 Digital input Blanking input source for both COMP channels: TIM3 OC4 comp_blk5 Digital input Blanking input source for both COMP channels: TIM8 OC5 comp_blk6 Digital input Blanking input source for both COMP channels: TIM15 OC1 comp_pclk Digital input APB clock for both COMP channels comp1_wkup Digital output COMP channel 1 wakeup out comp1_out Digital output COMP channel 1 out comp2_wkup Digital output COMP channel 2 wakeup out comp2_out Digital output COMP channel 2 out comp_it Digital output COMP interrupt out Table 218. COMP input/output pins Signal name Signal type Description COMP1_INM1 Analog input COMP channel 1 inverting input source 1 (PB1) COMP1_INM2 Analog input COMP channel 1 inverting input source 2 (PC4) COMP1_INP1 Analog input COMP channel 1 non-inverting input source 1 (PB0) COMP1_INP2 Analog input COMP channel 1 non-inverting input source 2 (PB2) COMP2_INM1 Analog input COMP channel 2 inverting input source 1 (PE10) COMP2_INM2 Analog input COMP channel 2 inverting input source 2 (PE7) COMP2_INP1 Analog input COMP channel 2 non-inverting input source 1 (PE9) COMP2_INP2 Analog input COMP channel 2 non-inverting input source 2 (PE11) COMP1_OUT Digital output COMP channel 1 output: see Section 28.3.8: Comparator output on GPIOs. COMP2_OUT Digital output COMP channel 2 output: see Section 28.3.8: Comparator output on GPIOs. DocID029587 Rev 3 1019/3178 1033 Comparator (COMP) 28.3.3 RM0433 COMP reset and clocks The clock comp_pclk provided by the clock controller is synchronous with the APB clock. Note: Important: The polarity selection logic and the output redirection to the port works independently from the APB clock. This allows the comparator to work even in Stop mode. The interrupt line, connected to the NVIC of CPU, requires the APB clock (comp_pclk) to work. In absence of the APB clock, the interrupt signal comp_it cannot be generated. 28.3.4 Comparator LOCK mechanism The comparators can be used for safety purposes, such as over-current or thermal protection. For applications with specific functional safety requirements, the comparator configuration can be protected against undesired alteration that could happen, for example, at program counter corruption. For this purpose, the comparator configuration registers can be write-protected (read-only). Upon configuring a comparator channel, its LOCK bit is set to 1. This causes the whole register set of the comparator channel, as well as the common COMP_OR register, to become read-only, the LOCK bit inclusive. The write protection can only be removed through the MCU reset. The COMP_OR register is locked by the LOCK bit of COMP_CFGR1 OR COMP_CFGR2. 28.3.5 Window comparator The purpose of the window comparator is to monitor the analog voltage and check that it is comprised within the specified voltage range defined by lower and upper thresholds. The window comparator requires both COMP channels. The monitored analog voltage is connected to their non-inverting (plus) inputs and the upper and lower threshold voltages are connected to the inverting (minus) input of either comparator, respectively. The noninverting input of the COMP channel 2 can be connected internally with the non-inverting input of the COMP channel 1 by enabling WINMODE bit. This can save the input pins of COMP channel 2 for other purposes. See Figure 203: Comparator functional block diagram. 28.3.6 Hysteresis The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components. 1020/3178 DocID029587 Rev 3 RM0433 Comparator (COMP) Figure 204. Comparator hysteresis ).0 ).).- 6HYST #/-0?/54 06 9 28.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It uses a blanking window defined with a timer output compare signal. Refer to the register description for selectable blanking signals. The blanking signal gates the internal comparator output such as to clean the comp_out from spurious pulses due to current spikes, as depicted in Figure 205 (the COMP channel number is not represented). Figure 205. Comparator output blanking 3:0 FXUUHQW VSLNH ,QYHUWLQJLQSXW UHSUHVHQWVFXUUHQWOLPLW 1RQLQYHUWLQJLQSXW UHSUHVHQWVFXUUHQW VSXULRXV SXOVH FPSBRXW EHIRUHEODQNLQJJDWH FPSBEON EODQNLQJZLQGRZ FRPSBRXW &203RXWSXW FPSBRXW FRPSBRXW WR,2V7,0B%.« FPSBEON %ODQNLQJJDWH DocID029587 Rev 3 06 9 1021/3178 1033 Comparator (COMP) 28.3.8 RM0433 Comparator output on GPIOs The COMP1_OUT and COMP2_OUT outputs of the comparator channels are mapped to GPIOs through the AFOP field of the COMP_OR register, bits [10:0], and through the GPIO alternate function. Table 219. COMP1_OUT assignment to GPIOs COMP1_OUT Alternate Function PC5 AF13 PE12 AF13 PA6 AF10, AF12 (can be used as timer break in) PA8 AF12 (can be used as timer break in) PB12 AF13 (can be used as timer break in) PE6 AF11 (can be used as timer break in) PE15 AF13 (can be used as timer break in) PG2 AF11 (can be used as timer break in) PG3 AF11 (can be used as timer break in) PG4 AF11 (can be used as timer break in) PI1 AF11 (can be used as timer break in) PI4 AF11 (can be used as timer break in) PK2 AF10, AF11 (can be used as timer break in) Table 220. COMP2_OUT assignment to GPIOs COMP2_OUT 1022/3178 Alternate Function PE8 AF13 PE13 AF13 PA6 AF10, AF12 (can be used as timer break in) PA8 AF12 (can be used as timer break in) PB12 AF13 (can be used as timer break in) PE6 AF11 (can be used as timer break in) PE15 AF13 (can be used as timer break in) PG2 AF11 (can be used as timer break in) PG3 AF11 (can be used as timer break in) PG4 AF11 (can be used as timer break in) PI1 AF11 (can be used as timer break in) PI4 AF11 (can be used as timer break in) PK2 AF10, AF11 (can be used as timer break in) DocID029587 Rev 3 RM0433 Comparator (COMP) The assignment to GPIOs for both comparator channel outputs must be done before locking registers of any channel, because the common COMP_OR register is locked when locking the registers of either comparator channel. 28.3.9 Comparator output redirection The outputs of either COMP channel can be redirected to timer break inputs (TIMx_BKIN or TIMx_BKIN2), as shown in Figure 206. For that end, the COMP channel output is connected to one of GPIOs programmable in alternate function as timer break input. See Table 219 and Table 220. The selected GPIO(s) must be set in open drain mode. The COMP output passes through the GPIO to the timer break input. With a pull-up resistor, the selected GPIO can be used as timer break input logic OR-ed with the comparator output. Figure 206. Output redirection %.,13 7RWKHWLPHUEUHDNLQSXW DFWLYHKLJK 7,0[B%.,1\ [ \ $), $)LQSXWHQDEOHG DFWLYHORZ 3$' &203 $)2 $)RXWSXWFRQILJXUHGDVRSHQGUDLQ 06Y9 28.3.10 COMP power and speed modes The power consumption of the COMP channels versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits PWRMODE[1:0] in COMP_CFGRx registers can be programmed as follows: 00: High speed / full power 01: Medium speed / medium power 10: Medium speed / medium power 11: Very-low speed / ultra-low-power DocID029587 Rev 3 1023/3178 1033 Comparator (COMP) 28.4 RM0433 COMP low-power modes Table 221. Comparator behavior in the low-power modes Mode Description Sleep No effect on the comparators. Comparator interrupts cause the device to exit the Sleep mode. Stop No effect on the comparators. Comparator interrupts cause the device to exit the Stop mode. Note: The comparators cannot be used to exit the device from Sleep or Stop mode when the internal reference voltage is switched off. 28.5 COMP interrupts There are two ways to use the comparator as interrupt source. The comparator outputs are internally connected to the Extended interrupt and event controller. Each comparator has its own EXTI line and can generate either interrupts or events to make the device exit low-power modes. The comparators also provide an interrupt line to the NVIC of CPU. This functionality is used when the CPU is active to handle low latency interrupt. It requires APB clock running. 28.5.1 Interrupt through EXTI block Refer to Interrupt and events section for more details. Sequence to enable the COMPx interrupt through EXTI block: 1. Configure the EXTI line, receiving the comp_wkup signal, in interrupt mode, select the rising, falling or either-edge sensitivity and enable the EXTI line. 2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines. 3. Enable the COMPx. Table 222. Interrupt control bits Interrupt event Event flag Enable control bit Exit from Sleep mode Exit from Stop modes Exit from Standby mode comp1_wkup through EXTI through EXTI yes yes N/A comp2_whup through EXTI through EXTI yes yes N/A 28.5.2 Interrupt through NVIC of the CPU Sequence to enable the COMPx interrupt through NVIC of the CPU: 1024/3178 1. Configure and enable the NVIC IRQ channel mapped to the comp_it line. 2. Configure and enable the ITEN in COMP_CFGRx. 3. Enable the COMPx. DocID029587 Rev 3 RM0433 Comparator (COMP) Table 223. Interrupt control bits Interrupt event Interrupt flag Enable control bit Interrupt clear bit Exit from Sleep mode Exit from Stop modes comp_it C1IF in ITEN in COMP_CFGR1 CC1IF yes (With APB clock) no comp_it C2IF in ITEN in COMP_CFGR2 CC2IF yes (With APB clock) no Note: It is mandatory to enable APB clock to use this interrupt. If clock is not enabled, interrupt is not generated. 28.6 SCALER function The scaler block is available to provide the different voltage reference levels to the comparator inputs. It is based on an amplifier driving a resistor bridge. The amplifier input is connected to the internal voltage reference. The amplifier and the resistor bridge can be enabled separately. The amplifier is enabled by the SCALEN bits of the COMP_CFGRx registers. The resistor bridge is enabled by the BRGEN bits of the COMP_CFGRx registers. When the resistor divided voltage is not used, the resistor bridge can be disconnected in order to reduce the consumption. When it is disconnected, the 1/4 VREF_COMP, 1/2 VREF_COMP and 3/4 VREF_COMP levels are equal to VREF_COMP. Figure 207. Scaler block diagram 95(),17 95()B&203 95()B&203 6&$/(1 FK 95()B&203 6&$/(1 FK 95()B&203 %5*(1 FK %5*(1 FK 06Y 9 DocID029587 Rev 3 1025/3178 1033 Comparator (COMP) RM0433 28.7 COMP registers 28.7.1 Comparator status register (COMP_SR) The COMP_SR is the comparator status register. Address offset: 0x00 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. C2IF C1IF r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. C2VAL C1VAL r r Bits 31:18 Reserved, must be kept at reset value. Bit 17 C2IF: COMP channel 2 Interrupt Flag This bit is set by hardware when the COMP channel 2 output is set This bit is cleared by software writing 1 the CC2IF bit in the COMP_ICFR register. Bit 16 C1IF: COMP channel 1 Interrupt Flag This bit is set by hardware when the COMP channel 1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register. Bits 15:2 Reserved, must be kept at reset value. Bit 1 C2VAL: COMP channel 2 output status bit This bit is read-only. It reflects the current COMP channel 2 output taking into account POLARITY and BLANKING bits effect. Bit 0 C1VAL: COMP channel 1 output status bit This bit is read-only. It reflects the current COMP channel 1 output taking into account POLARITY and BLANKING bits effect. 28.7.2 Comparator interrupt clear flag register (COMP_ICFR) The COMP_ICFR is the Comparator interrupt clear flag register. Address offset: 0x00 System reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC2IF CC1IF w1o w1o 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1026/3178 DocID029587 Rev 3 RM0433 Comparator (COMP) Bits 31:18 Reserved, must be kept at reset value. Bit 17 CC2IF: Clear COMP channel 2 Interrupt Flag Writing 1 clears the C2IF flag in the COMP_SR register. Bit 16 CC1IF: Clear COMP channel 1 Interrupt Flag Writing 1 clears the C1IF flag in the COMP_SR register. Bits 15:0 Reserved, must be kept at reset value. 28.7.3 Comparator option register (COMP_OR) The COMP_OR is the Comparator option register. Address offset: 0x08 System reset value: 0x0000 0000 When OR_CFG=0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 OR15 OR14 OR13 OR12 OR11 AFOP rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:11 OR: Option Register (When OR_CFG=0) Bits 10:0 AFOP[10:0]: Selection of source for alternate function of output ports Bits of this field are set end cleared by software (only if LOCK not set). Output port (GPIO) correspondence: bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PK2 PI4 PI1 PG4 PG3 PG2 PE15 PE6 PB12 PA8 PA6 For each bit: 0: COMP1_OUT is selected for the alternate function of the corresponding GPIO 1: COMP2_OUT is selected for the alternate function of the corresponding GPIO When OR_CFG=1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OR31 OR30 OR29 OR28 OR27 OR26 OR25 OR24 OR23 OR22 OR21 OR20 OR19 OR18 OR17 OR16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OR15 OR14 OR13 OR12 OR11 AFOP rw rw rw rw rw rw DocID029587 Rev 3 1027/3178 1033 Comparator (COMP) RM0433 Bits 31:11 OR: Option Register (When OR_CFG=1) Bits 10:0 AFOP[10:0]: Selection of source for alternate function of output ports Bits of this field are set end cleared by software (only if LOCK not set). Output port (GPIO) correspondence: bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PK2 PI4 PI1 PG4 PG3 PG2 PE15 PE6 PB12 PA8 PA6 For each bit: 0: COMP1_OUT is selected for the alternate function of the corresponding GPIO 1: COMP2_OUT is selected for the alternate function of the corresponding GPIO 28.7.4 Comparator configuration register 1 (COMP_CFGR1) The COMP_CFGR1 is the COMP channel 1 configuration register. Address offset: 0x0C System reset value: 0x0000 0000 31 30 29 28 LOCK Res. Res. Res. 27 26 rw 15 Res. 25 24 BLANKING[3:0] 23 22 21 20 19 Res. Res. Res. INPSEL Res. rw 14 Res. 13 12 PWRMODE[1:0] rw 11 Res. 10 Res. 18 rw 9 8 HYST[1:0] 7 Res. rw 6 ITEN 5 Res. 4 Res. rw 17 16 INMSEL[2:0] rw 3 2 1 POLARI SCALEN BRGEN TY rw rw rw 0 EN rw Bit 31 LOCK: Lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP channel 1 configuration register COMP_CFGR1[31:0], and COMP_OR register 0: COMP_CFGR1[31:0] register is read/write 1: COMP_CFGR1[31:0] and COMP_OR registers are read-only Bits 30:28 Reserved, must be kept at reset value. Bits 27:24 BLANKING[3:0]: COMP channel 1 blanking source selection bits Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP channel 1 output blanking: 0000: No blanking 0001: comp_blk1 0010: comp_blk2 0011: comp_blk3 0100: comp_blk4 0101: comp_blk5 0110: comp_blk6 All other values: reserved Bits 23:21 Reserved, must be kept at reset value. Bit 20 INPSEL: COMP channel 1 non-inverting input selection bit This bit is set and cleared by software (only if LOCK not set). 0: COMP1_INP1 (PB0) 1: COMP1_INP2 (PB2) Bit 19 Reserved, must be kept at reset value. 1028/3178 DocID029587 Rev 3 RM0433 Comparator (COMP) Bits 18:16 INMSEL[2:0]: COMP channel 1 inverting input selection field These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of COMP channel 1. 000 = 1/4 VREF_COMP 001 = 1/2 VREF_COMP 010 = 3/4 VREF_COMP 011 = VREF_COMP 100 = comp_inm1 (DAC channel 1 output) 101 = comp_inm2 (DAC channel 2 output) 110 = COMP1_INM1 (PB1) 111 = COMP1_INM2 (PC4) Bits 15:14 Reserved, must be kept at reset value. Bits 13:12 PWRMODE[1:0]: Power Mode of the COMP channel 1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel 1. 00: High speed / full power 01: Medium speed / medium power 10: Medium speed / medium power 11: Ultra low power / ultra-low-power Bits 11:10 Reserved, must be kept at reset value. Bits 9:8 HYST[1:0]: COMP channel 1 hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the COMP channel 1. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Bit 7 Reserved, must be kept at reset value. Bit 6 ITEN: COMP channel 1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel 1. 0: Interrupt generation disabled for COMP channel 1 1: Interrupt generation enabled for COMP channel 1 Bits 5:4 Reserved, must be kept at reset value. Bit 3 POLARITY: COMP channel 1 polarity selection bit This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel 1 polarity. 0: COMP channel 1 output is not inverted 1: COMP channel 1output is inverted DocID029587 Rev 3 1029/3178 1033 Comparator (COMP) RM0433 Bit 2 SCALEN: Voltage scaler enable bit This bit is set and cleared by software (only if LOCK not set). This bit enables the VREFINT scaler for the COMP channels. 0: VREFINT scaler disabled (if SCALEN bit of COMP_CFGR2 register is also low) 1: VREFINT scaler enabled Bit 1 BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. 0: Scaler resistor bridge disabled (if BRGEN bit of COMP_CFGR2 register is also low) 1: Scaler resistor bridge enabled If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level VREF_COMP (similar to VREFINT). If SCALEN and BRGEN are set, the four scaler outputs provide VREF_COMP, 3/4 VREF_COMP, 1/2 VREF_COMP and 1/4 VREF_COMP levels, respectively. Bit 0 EN: COMP channel 1 enable bit This bit is set and cleared by software (only if LOCK not set). It enables the COMP channel 1. 0: Disable 1: Enable 28.7.5 Comparator configuration register 2 (COMP_CFGR2) The COMP_CFGR2 is the COMP channel 1 configuration register. Address offset: 0x10 System reset value: 0x0000 0000 31 30 29 28 LOCK Res. Res. Res. 27 26 rw 15 Res. 25 24 BLANKING[3:0] 23 22 21 20 19 Res. Res. Res. INPSEL Res. rw 14 Res. 13 12 PWRMODE[1:0] rw 1030/3178 11 Res. 10 Res. 18 rw 9 8 HYST[1:0] rw 7 Res. 6 ITEN rw DocID029587 Rev 3 5 Res. 4 17 rw 3 2 1 WINMO POLAR SCALEN BRGEN DE ITY rw 16 INMSEL[2:0] rw rw rw 0 EN rw RM0433 Comparator (COMP) Bit 31 LOCK: Lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP channel 2 configuration register COMP_CFGR2[31:0], and COMP_OR register 0: COMP_CFGR2[31:0] register is read/write 1: COMP_CFGR2[31:0] and COMP_OR registers are read-only Bits 30:28 Reserved, must be kept at reset value. Bits 27:24 BLANKING[3:0]: COMP channel 2 blanking source selection bits These bits are set and cleared by software (only if LOCK not set). These bits select which timer output controls the COMP channel 2 output blanking. 0000: No blanking 0001: TIM1 OC5 selected as blanking source 0010: TIM2 OC3 selected as blanking source 0011: TIM3 OC3 selected as blanking source 0100: TIM3 OC4 selected as blanking source 0101: TIM8 OC5 selected as blanking source 0110: TIM15 OC1 selected as blanking source All other values: reserved Bits 23:21 Reserved, must be kept at reset value. Bit 20 INPSEL: COMP channel 2 non-inverting input selection bit This bit is set and cleared by software (only if LOCK not set). 0: COMP2_INP1 (PE9) 1: COMP2_INP2 (PE11) Bit 19 Reserved, must be kept at reset value. Bits 18:16 INMSEL[2:0]: COMP channel 2 inverting input selection field These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of COMP channel 2. 000 = 1/4 VREF_COMP 001 = 1/2 VREF_COMP 010 = 3/4 VREF_COMP 011 = VREF_COMP 100 = comp_inm1 (DAC channel 1 output) 101 = comp_inm2 (DAC channel 2 output) 110 = COMP2_INM1 (PE10) 111 = COMP2_INM2 (PE7) Bits 15:14 Reserved, must be kept at reset value. Bits 13:12 PWRMODE[1:0]: Power Mode of the COMP channel 2 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel 2. 00: High speed / full power 01: Medium speed / medium power 10: Medium speed / medium power 11: Ultra low power / ultra-low-power Bits 11:10 Reserved, must be kept at reset value. DocID029587 Rev 3 1031/3178 1033 Comparator (COMP) RM0433 Bits 9:8 HYST[1:0]: COMP channel 2 hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the COMP channel 2. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Bit 7 Reserved, must be kept at reset value. Bit 6 ITEN: COMP channel 2 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel 2. 0: Interrupt generation disabled for COMP channel 2 1: Interrupt generation enabled for COMP channel 2 Bit 5 Reserved, must be kept at reset value. Bit 4 WINMODE: Window comparator mode selection bit This bit is set and cleared by software (only if LOCK not set). This bit selects the window mode of the comparators. If set, the non-inverting input of COMP channel 2 is connected to the non-inverting input of the COMP channel 1. Depending on the bit value, the non-inverting input of COMP channel 2 is connected to: 0: COMP2_INP input selector 1: Non-inverting input comp1_inp of COMP channel 1 Bit 3 POLARITY: COMP channel 2 polarity selection bit This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel 2 polarity. 0: COMP channel 2 output is not inverted 1: COMP channel 2 output is inverted Bit 2 SCALEN: Voltage scaler enable bit This bit is set and cleared by software (only if LOCK not set). This bit enables the VREFINT scaler for the COMP channels. 0: VREFINT scaler disabled (if SCALEN bit of COMP_CFGR1 register is also low) 1: VREFINT scaler enabled Bit 1 BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. 0: Scaler resistor bridge disabled (if BRGEN bit of COMP_CFGR1 register is also low) 1: Scaler resistor bridge enabled If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level VREF_COMP (similar to VREFINT). If SCALEN and BRGEN are set, the four scaler outputs provide VREF_COMP, 3/4 VREF_COMP, 1/2 VREF_COMP and 1/4 VREF_COMP levels, respectively. Bit 0 EN: COMP channel 2 enable bit This bit is set and cleared by software (only if LOCK not set). It enables the COMP channel 2. 0: Disable 1: Enable 1032/3178 DocID029587 Rev 3 OR29 0x10 Reset value 0 0 0 COMP_CFG R1 Res. 0x0C COMP_OR (OR_CFG=1) Res. 0x08 OR30 Reset value 0 COMP_CFG R2 Reset value 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 OR14 OR13 0 0 0 0 0 Res. 0 OR11 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 0 0 0 0 EN 0 BRGEN 0 BRGEN 0 SCALEN 0 SCALEN 0 POLARITY 0 POLARITY 0 Res. 0 WINMODE 0 Res. Res. OR11 0 ITEN Res. OR12 0 Res. Res. OR13 0 Res. Res. 0 Res. AFOP Res. Res. Res. Res. Res. Res. Res. Res. Res. OR14 C2VAL C1VAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. C1IF CC1IF Res. Res. OR15 0 HYST OR12 PWRMODE OR15 C2IF Res. Res. Res. Res. CC2IF 0 Res. 0 0 ITEN 0 OR16 Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 HYST 0 0 Res. OR17 Res. Res. Reset value Res. OR18 0 Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. COMP_SR 0 PWRMODE OR19 0 INPSEL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name 0 Res. OR20 0 INMSEL OR21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 INMSEL Res. INPSEL Res. Res. 0 Res. 0 OR22 0 0 Res. 0 OR23 0 0 Res. 0 Res. OR25 0 OR24 OR26 BLANKING OR27 0 BLANKING OR28 Res. COMP_OR (OR_CFG=0) Res. COMP_ICFR Res. 0x08 OR31 0x04 Res. 0x00 LOCK Offset Res. 28.7.6 LOCK RM0433 Comparator (COMP) COMP register map The following table summarizes the comparator registers. Table 224. COMP register map and reset values 0 0 0 0 0 0 0 AFOP 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1033/3178 1033 Operational amplifiers (OPAMP) RM0433 29 Operational amplifiers (OPAMP) 29.1 Introduction The devices embed two operational amplifiers with two inputs and one output each. The three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. The positive input can be connected to the internal DAC. One of the output can be connected to the internal ADC. 29.2 OPAMP main features • Rail-to-rail input and output voltage range • Low input bias current (down to 1 nA) • Low input offset voltage (1.5 mV after calibration, 10 mV with factory calibration) • 7 MHz gain bandwidth • High-speed mode to achieve a better slew rate Note: Refer to the product datasheet for detailed OPAMP characteristics. 29.3 OPAMP functional description The OPAMP has several modes. Each OPAMP can be individually enabled, when disabled the output is high-impedance. When enabled, it can be in calibration mode, all input and output of the OPAMP are then disconnected, or in functional mode. There are two functional modes, the high-speed mode and the normal mode. In functional mode the inputs and output of the OPAMP are connected as described in Section 29.3.3: Signal routing. 29.3.1 OPAMP reset and clocks The operational amplifier clock is necessary for accessing the registers. When the application does not need to have read or write access to those registers, the clock can be switched off using the peripheral clock enable register (see OPAMPEN bit in Section 8.7.43: RCC APB1 Clock Register (RCC_APB1LENR)). The bit OPAEN enables and disables the OPAMP operation. The OPAMP registers configurations should be changed before enabling the OPAEN bit in order to avoid spurious effects on the output. When the output of the operational amplifier is no more needed the operational amplifier can be disabled to save power. All the configurations previously set (including the calibration) are maintained while OPAMP is disabled. 1034/3178 DocID029587 Rev 3 RM0433 29.3.2 Operational amplifiers (OPAMP) Initial configuration The default configuration of the operational amplifier is a functional mode where the three input/outputs are connected to external pins. In the default mode the operational amplifier uses the factory trimming values for its offset calibration. See electrical characteristics section of the datasheet for factory trimming conditions, usually the temperature is 30 °C and the voltage is 3 V. The trimming values can be adjusted, see Section 29.3.5: Calibration for changing the trimming values. The default configuration uses the normal mode, which provides the standard performance. The bit OPAHSM can be set in order to switch the operational amplifier to high-speed mode for a better slew rate. Both normal and high-speed mode characteristics are defined in Section: Electrical characteristics of the datasheet. As soon as the OPAEN bit in OPAMPx_CSR register is set, the operational amplifier is functional. The two input pins and the output pin are connected as defined in Section 29.3.3: Signal routing and the default connection settings can be changed. Note: The inputs and output pins must be configured in analog mode (default state) in the corresponding GPIOx_MODER register. 29.3.3 Signal routing The routing for the operational amplifier pins is determined by OPAMPx_CSR register. The connections of the two operational amplifiers (OPAMP1 and OPAMP2) are described in the table below. Table 225. Operational amplifier possible connections Signal Pin Internal OPAMP1_VINM PC5(INM0) PA7(INM1) ADC1_IN8 ADC2_IN8 OPAMP1_VOUT or PGA PB0 dac_out1 ADC1_IN9 ADC2_IN9 COMP1_INP OPAMP1_VOUT PC4 ADC1_IN4 ADC2_IN4 COMP1_INM7 OPAMP2_VINM PE8(INM0) PG1(INM1) OPAMP2_VOUT or PGA OPAMP2_VINP PE9 dac_out2 COMP2_INP OPAMP2_VOUT PE7 COMP2_INM7 OPAMP1_VINP DocID029587 Rev 3 comment controlled by bits PGA_GAIN and VM_SEL. controlled by bit VP_SEL. The pin is connected when the OPAMP is enabled. The ADC input is controlled by ADC. controlled by bits PGA_GAIN and VM_SEL. controlled by bit VP_SEL - 1035/3178 1051 Operational amplifiers (OPAMP) 29.3.4 RM0433 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: Note: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes The amplifier output pin is directly connected to the output pad to minimize the output impedance. When the amplifier is enabled, it cannot be used as a general purpose I/O, even if the amplifier is configured as a PGA and only connected to the internal channel. The impedance of the signal must be maintained below a level which avoids the input leakage to create significant artifacts (due to a resistive drop in the source). Please refer to the electrical characteristics section in the datasheet for further details. Standalone mode (external gain setting mode) The procedure to use the OPAMP in standalone mode is presented hereafter. Starting from the default value of OPAMPx_CSR, and the default state of GPIOx_MODER, as soon as the OPAEN bit is set, the two input pins and the output pin are connected to the operational amplifier. This default configuration uses the factory trimming values and operates in normal mode (highest performance). The behavior of the OPAMP can be changed as follows: • OPAHSM can be set to “operational amplifier high-speed” mode in order to have high slew rate. • USERTRIM can be set to modify the trimming values for input offsets. Figure 208. Standalone mode: external gain setting mode 670 ,13 GDFBRXW[ /EDϬŽƌϭ RSDPSBRXW 9287 06Y9 1036/3178 DocID029587 Rev 3 RM0433 Operational amplifiers (OPAMP) Follower configuration mode The procedure to use the OPAMP in follower mode is presented hereafter. Note: • configure VM_SEL bits as “opamp_out connected to OPAMPx_VINM input”, 11 • configure VP_SEL bits as “GPIO connected to OPAMPx_VINP”, 00 • As soon as the OPAEN bit is set, the voltage on pin OPAMPx_VINP is buffered to pin OPAMPx_VOUT. The pin corresponding to OPAMPx_VINM is free for another usage. The signal on the OPAMP1 output is also seen as an ADC input. As a consequence, the OPAMP configured in follower mode can be used to perform impedance adaptation on input signals before feeding them to the ADC input, assuming the input signal frequency is compatible with the operational amplifier gain bandwidth specification. Figure 209. Follower configuration 670 9,13 GDFBRXW[ s/EDϬŽƌϭ RSDPSBRXW $OZD\VFRQQHFWHGWR 23$03RXWSXW 9287 06Y9 DocID029587 Rev 3 1037/3178 1051 Operational amplifiers (OPAMP) RM0433 Programmable gain amplifier mode The procedure to use the OPAMP as programmable gain amplifier is presented hereafter. • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, 10 • configure PGA_GAIN bits as “internal Gain 2, 4, 8 or 16”, 0000 to 0011 • configure VP_SEL bits as “GPIO connected to OPAMPx_VINP”, 00 As soon as the OPAEN bit is set, the voltage on pin OPAMPx_VINP is amplified by the selected gain and visible on pin OPAMPx_VOUT. Note: To avoid saturation, the input voltage should stay below VDDA divided by the selected gain. Figure 210. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used 670 9,13 GDFBRXW[ s/EDϬŽƌϭ RSDPSBRXW $OZD\VFRQQHFWHGWR 23$03RXWSXW 9287 06Y9 1038/3178 DocID029587 Rev 3 RM0433 Operational amplifiers (OPAMP) Programmable gain amplifier mode with external filtering The procedure to use the OPAMP to amplify the amplitude of an input signal, with an external filtering, is presented hereafter. • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, 10 • configure PGA_GAIN bits as “internal Gain 2, 4, 8 or 16 with filtering on INM0”, 0100 to 0111 • configure VP_SEL bits as “GPIO connected to OPAMPx_VINP”. Any external connection on INM can be used in parallel with the internal PGA, for example a capacitor can be connected between opamp_out and INM for filtering purpose (see datasheet for the value of resistors used in the PGA resistor network). Figure 211. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering 670 9,13 GDFBRXW[ RSDPSBRXW s/EDϬ $OORZVRSWLRQDO ORZSDVV ILOWHULQJ (TXLYDOHQWWR sKhd 06Y9 1. The gain depends on the cut-off frequency. DocID029587 Rev 3 1039/3178 1051 Operational amplifiers (OPAMP) RM0433 Programmable gain amplifier, non-inverting with external bias or inverting mode The procedure to use the OPAMP to amplify the amplitude of an input signal with bias voltage for non-inverting mode or inverting mode. • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, 10 • configure PGA_GAIN bits as “Inverting gain=-1,-3,-7,-15/ Non-inverting gain =2,4,8,16 with INM0”, 1000 to 1011 • configure VP_SEL bits as “GPIO connected to OPAMPx_VINP”. Figure 212. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain setting (x-1/x-3/x-7/x-15) 670 9,13 GDFBRXW[ RSDPSBRXW 9,10 $OZD\VFRQQHFWHGWR 23$03RXWSXW 9287 06Y9 Figure 213. Example configuration 9287 9,13 Žƌ 9,10 %LDVYROWDJH 9,13 %LDVYROWDJH ,QSXWVLJQDO 9,10 9287 9,10 9,10 'ĂŝŶ͗džϮ͕džϰ͕džϴ͕džϭϲ 'ĂŝŶ͗džͲϭ͕džͲϯ͕džͲϳ͕džͲϭϱ 06Y9 1040/3178 DocID029587 Rev 3 RM0433 Operational amplifiers (OPAMP) Programmable gain amplifier, non-inverting with external bias or inverting mode with filtering The procedure to use the OPAMP to amplify the amplitude of an input signal with bias voltage for non-inverting mode or inverting mode with filtering • configure VM_SEL bits as “Feedback resistor is connected to OPAMPx_VINM input”, 10 • configure PGA_GAIN bits as “Inverting gain=-1,-3,-7,-15/ Non-inverting gain =2,4,8,16 with INM0, INM1 node for filtering”, 1100 to 1111 • configure VP_SEL bits as “GPIO connected to OPAMPx_VINP”. Any external connection on VM1 can be used in parallel with the internal PGA, for example a capacitor can be connected between opamp_out and VM1 for filtering purpose (see datasheet for the value of resistors used in the PGA resistor network). Figure 214. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain setting (x-1/x-3/x-7/x-15) with filtering 670 9,13 GDFBRXW[ RSDPSBRXW 9,10 9,10 $OORZVRSWLRQDO ORZSDVV ILOWHULQJ (TXLYDOHQWWR 9287 06Y9 Figure 215. Example configuration 9287 9,13 Žƌ 9,10 %LDVYROWDJH 9,13 %LDVYROWDJH ,QSXWVLJQDO 9,10 9287 9,10 9,10 'ĂŝŶ͗džϮ͕džϰ͕džϴ͕džϭϲ 'ĂŝŶ͗džͲϭ͕džͲϯ͕džͲϳ͕džͲϭϱ 06Y9 DocID029587 Rev 3 1041/3178 1051 Operational amplifiers (OPAMP) 29.3.5 RM0433 Calibration The OPAMP interface continuously sends trimmed offset values to the operational amplifiers. At startup, the trimming values are initialized with the preset ‘factory’ trimming value. Each operational amplifier can be trimmed by the user. Specific registers allow to have different trimming values for normal mode and for high-speed mode. The aim of the calibration is to cancel as much as possible the OPAMP inputs offset voltage. The calibration circuitry allows to reduce the input offset voltage to less than +/-1.5 mV within stable voltage and temperature conditions. For each operational amplifier and each mode two trimming value needs to be trimmed, one for N differential pair and one for P differential pair. There are two registers for trimming the offsets for each operational amplifiers, one for normal mode (OPAMPx_OTR) and one high-speed mode (OPAMPx_HSOTR). Each register is composed of five bits for P differential pair trimming and five bits for N differential pair trimming. These are the ‘user’ values. The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the USERTRIM bit in the OPAMPx_CSR register. This bit is reset at startup and so the ‘factory’ value are applied by default to the OPAMP option registers. User is liable to change the trimming values in calibration or in functional mode. The offset trimming registers are typically configured after the calibration operation is initialized by setting bit CALON to 1. When CALON = 1 the inputs of the operational amplifier are disconnected from the functional environment. • Setting CALSEL to 01 initializes the offset calibration for the P differential pair (low voltage reference used). • Resetting CALSEL to 11 initializes the offset calibration for the N differential pair (high voltage reference used). When CALON = 1, the bit CALOUT will reflect the influence of the trimming value selected by CALSEL and OPAHSM. The software should increment the TRIMOFFSETN bits in the OPAMP control register from 0x00 to the first value that causes the CALOUT bit to change from 1 to 0 in the OPAMP register. If the CALOUT bit is reset, the offset is calibrated correctly and the corresponding trimming value must be stored. The CALOUT flag needs up to 1 ms after the trimming value is changed to become steady (see tOFFTRIMmax delay specification in the electrical characteristics section of the datasheet). Note: The closer the trimming value is to the optimum trimming value, the longer it takes to stabilize (with a maximum stabilization time remaining below 1 ms in any case). Table 226. Operating modes and calibration Control bits Output Mode 1042/3178 OPAEN OPAHSM CALON CALSEL VOUT CALOUT flag Normal operating mode 1 0 0 X analog 0 High-speed mode 1 1 0 X analog 0 Power down 0 X X X Z 0 DocID029587 Rev 3 RM0433 Operational amplifiers (OPAMP) Table 226. Operating modes and calibration (continued) Control bits Output Mode OPAEN OPAHSM CALON CALSEL VOUT CALOUT flag Offset cal N diff for normal mode 1 0 1 11 analog X Offset cal P diff for normal mode 1 0 1 01 analog X Offset cal N diff for high-speed mode 1 1 1 11 analog X Offset cal P diff for high-speed mode 1 1 1 01 analog X Calibration procedure Here are the steps to perform a full calibration of either one of the operational amplifiers: 1. Set the OPAEN bit in OPAMPx_CSR to 1 to enable the operational amplifier. 2. Set the USERTRIM bit in the OPAMPx_CSR register to 1. 3. Choose a calibration mode (refer to Table 226: Operating modes and calibration). The steps 3 to 4 will have to be repeated 4 times. For the first iteration select – Normal mode and N differential pair The above calibration mode correspond to OPAHSM=0 and CALSEL=11 in the OPAMPx_CSR register. 4. Note: Increment TRIMOFFSETN[4:0] in OPAMPx_OTR starting from 00000b until CALOUT changes to 0 in OPAMPx_CSR. Between the write to the OPAMPx_OTR register and the read of the CALOUT value, make sure to wait for the tOFFTRIMmax delay specified in the electrical characteristics section of the datasheet, to get the correct CALOUT value. The commutation means that the is correctly compensated and that the corresponding trim code must be saved in the OPAMPx_OTR register. Repeat steps 3 to 4 for: • Normal_mode and P differential pair, CALSEL=01 • High-speed mode and N differential pair • High-speed mode and P differential pair If a mode is not used, it is not necessary to perform the corresponding calibration. All operational amplifier can be calibrated at the same time. Note: During the whole calibration phase the external connection of the operational amplifier output must not pull up or down currents higher than 500 µA. DocID029587 Rev 3 1043/3178 1051 Operational amplifiers (OPAMP) 29.4 RM0433 OPAMP low-power modes Table 227. Effect of low-power modes on the OPAMP Mode 29.5 Description Sleep No effect. D2 Stop No effect, OPAMP registers content is kept. Standby The OPAMP registers are powered down and must be re-initialized after exiting Standby. OPAMP PGA gain When OPAMP is configured as PGA mode, it can select the gain of x2,x4,x8,x16 for noninverting mode and x-1, x-3, x-7, x-15 for inverting mode. When OPAMP is configured as non-inverting mode, the Gain error can be refer to the product datasheet. When it is configured as inverting mode, Gain factor is defined not only the on chip feedback resistor but also the signal source output impedance. If signal source output impedance is not negligible compare to the input feedback resistance of PGA, it will create the gain error. Please refer to the PGA resistance value in the product datasheet. 29.6 OPAMP registers 29.6.1 OPAMP1 control/status register (OPAMP1_CSR) Address: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. CAL OUT TST REF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USER TRIM r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. OPA HSM PGA_GAIN rw rw CALSEL rw rw CALON rw Res. Res. rw VM_SEL rw rw Res. PGA_GAIN rw rw 2 1 0 rw FORCE OPAEN _VP rw Bit 31 Reserved, must be kept at reset value. Bit 30 CALOUT: Operational amplifier calibration output OPAMP output status flag. During the calibration mode, OPAMP is used as comparator. 0: Non-inverting < inverting 1: Non-inverting > inverting Bit 29 TSTREF: OPAMP calibration reference voltage output control (reserved for test) 0: INTVREF of OPAMP is not output 1: INTVREF of OPAMP is output Bits 28:19 Reserved, must be kept at reset value. 1044/3178 DocID029587 Rev 3 16 rw VP_SEL rw 17 rw RM0433 Operational amplifiers (OPAMP) Bit 18 USERTRIM: User trimming enable This bit allows to switch from ‘factory’ AOP offset trimmed values to ‘user’ AOP offset trimmed values This bit is active for both mode normal and high-power. 0: ‘factory’ trim code used 1: ‘user’ trim code used Bits 17:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 0000: Non-inverting internal Gain 2, VREF- referenced 0001: Non-inverting internal Gain 4, VREF- referenced 0010: Non-inverting internal Gain 8, VREF- referenced 0011: Non-inverting internal Gain 16, VREF- referenced 0100: Non-inverting internal Gain 2 with filtering on INM0, VREF- referenced 0101: Non-inverting internal Gain 4 with filtering on INM0, VREF- referenced 0110: Non-inverting internal Gain 8 with filtering on INM0, VREF- referenced 0111: Non-inverting internal Gain 16 with filtering on INM0, VREF- referenced 1000: Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias 1001: Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias 1010: Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias 1011: Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias 1100: Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias, INM1 node for filtering 1101: Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias, INM1 node for filtering 1110: Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias, INM1 node for filtering 1111: Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering Bits 13:12 CALSEL: Calibration selection It is used to select the offset calibration bus used to generate the internal reference voltage when CALON = 1 or FORCE_VP= 1. 00: 0.033*VDDA applied on OPAMP inputs 01: 0.1*VDDA applied on OPAMP inputs (for PMOS calibration) 10: 0.5*VDDA applied on OPAMP inputs 11: 0.9*VDDA applied on OPAMP inputs (for NMOS calibration) Bit 11 CALON: Calibration mode enabled 0: Normal mode 1: Calibration mode (all switches opened by HW) Bits 10:9 Reserved, must be kept at reset value. Bit 8 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration. 0: operational amplifier in normal mode 1: operational amplifier in high-speed mode Bit 7 Reserved, must be kept at reset value. DocID029587 Rev 3 1045/3178 1051 Operational amplifiers (OPAMP) RM0433 Bits 6:5 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01, 10 or 11. 00: INM0 connected to OPAMP INM input 01: INM1 connected to OPAMP NM input 10: Feedback resistor is connected to OPAMP INM input (PGA mode), Inverting input selection is depends on the PGA_GAIN setting 11: opamp_out connected to OPAMP INM input (Follower mode) Bit 4 Reserved, must be kept at reset value. Bits 3:2 VP_SEL: Non inverted input selection 00: GPIO connected to OPAMPx_VINP 01: dac_outx connected to OPAMPx_VINP 10: Reserved 11: Reserved Bit 1 FORCE_VP: Force internal reference on VP (reserved for test) 0: Normal operating mode. Non-inverting input connected to inputs. 1: Calibration verification mode: Non-inverting input connected to calibration reference voltage. Bit 0 OPAEN: Operational amplifier Enable 0: operational amplifier disabled 1: operational amplifier enabled 29.6.2 OPAMP1 trimming register in normal mode (OPAMP1_OTR) Address: 0x04 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 4 3 2 1 0 rw rw 15 14 13 Res. Res. Res. TRIMOFFSETP rw rw rw rw 7 6 5 Res. Res. Res. rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs 1046/3178 DocID029587 Rev 3 TRIMOFFSETN rw rw rw RM0433 Operational amplifiers (OPAMP) 29.6.3 OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR) Address: 0x08 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. rw rw rw rw TRIMHSOFFSETP rw rw rw TRIMHSOFFSETN rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMHSOFFSETP[4:0]: High-speed mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMHSOFFSETN[4:0]: High-speed mode trim for NMOS differential pairs 29.6.4 OPAMP option register (OPAMP_OR) Address: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17 16 Bits 31:0 Reserved, must be kept at reset value. 29.6.5 OPAMP2 control/status register (OPAMP2_CSR) Address: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. CAL OUT TST REF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USER TRIM r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 PGA_GAIN rw rw CALSEL rw rw OPA MODE CALON rw rw OPA HSM rw Res. rw DocID029587 Rev 3 VM_SEL rw rw Res. rw rw rw 2 1 0 VP_SEL rw PGA_GAIN rw FORCE OPAEN _VP rw rw 1047/3178 1051 Operational amplifiers (OPAMP) RM0433 Bit 31 Reserved, must be kept at reset value. Bit 30 CALOUT: Operational amplifier calibration output OPAMP output status flag. During the calibration mode, OPAMP is used as comparator. 0: Non-inverting < inverting 1: Non-inverting > inverting Bit 29 TSTREF: OPAMP calibration reference voltage output control (reserved for test) 0: INTVREF of OPAMP is not output 1: INTVREF of OPAMP is output Bits 28:19 Reserved, must be kept at reset value. Bit 18 USERTRIM: User trimming enable This bit allows to switch from ‘factory’ AOP offset trimmed values to ‘user’ AOP offset trimmed values This bit is active for both mode normal and high-power. 0: ‘factory’ trim code used 1: ‘user’ trim code used Bits 17:14 PGA_GAIN: Operational amplifier Programmable amplifier gain value 0000: Non-inverting internal Gain 2, VREF- referenced 0001: Non-inverting internal Gain 4, VREF- referenced 0010: Non-inverting internal Gain 8, VREF- referenced 0011: Non-inverting internal Gain 16, VREF- referenced 0100: Non-inverting internal Gain 2 with filtering on INM0, VREF- referenced 0101: Non-inverting internal Gain 4 with filtering on INM0, VREF- referenced 0110: Non-inverting internal Gain 8 with filtering on INMINM0, VREF- referenced 0111: Non-inverting internal Gain 16 with filtering on INM0, VREF- referenced 1000: Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias 1001: Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias 1010: Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias 1011: Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias 1100: Inverting gain=-1/ Non-inverting gain =2 with INM0 node for input or bias, INM1 node for filtering 1101: Inverting gain=-3/ Non-inverting gain =4 with INM0 node for input or bias, INM1 node for filtering 1110: Inverting gain=-7/ Non-inverting gain =8 with INM0 node for input or bias, INM1 node for filtering 1111: Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering Bits 13:12 CALSEL: Calibration selection It is used to select the offset calibration bus used to generate the internal reference voltage when CALON = 1 or FORCE_VP= 1. 00: 0.033*VDDA applied on OPAMP inputs 01: 0.1*VDDA applied on OPAMP inputs (for PMOS calibration) 10: 0.5*VDDA applied on OPAMP inputs 11: 0.9*VDDA applied on OPAMP inputs (for NMOS calibration) Bit 11 CALON: Calibration mode enabled 0: Normal mode 1: Calibration mode (all switches opened by HW) Bits 10:9 Reserved, must be kept at reset value. 1048/3178 DocID029587 Rev 3 RM0433 Operational amplifiers (OPAMP) Bit 8 OPAHSM: Operational amplifier high-speed mode The operational amplifier must be disable to change this configuration. 0: operational amplifier in normal mode 1: operational amplifier in high-speed mode Bit 7 Reserved, must be kept at reset value. Bits 6:5 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01, 10 or 11. 00: INM0 connected to OPAMP INM input 01: INM1 connected to OPAMP INM input 10: Feedback resistor is connected to OPAMP INM input (PGA mode), Inverting input selection is depends on the PGA_GAIN setting 11: opamp_out connected to OPAMP INM input (Follower mode) Bit 4 Reserved, must be kept at reset value. Bits 3:2 VP_SEL: Non inverted input selection 00: GPIO connected to OPAMPx_VINP 01: DAC connected to OPAMPx_VINP 10: Reserved 11: Reserved Bit 1 FORCE_VP: Force internal reference on VP (reserved for test) 0: Normal operating mode. Non-inverting input connected to inputs. 1: Calibration verification mode: Non-inverting input connected to calibration reference voltage. Bit 0 OPAEN: Operational amplifier Enable 0: operational amplifier disabled 1: operational amplifier enabled 29.6.6 OPAMP2 trimming register in normal mode (OPAMP2_OTR) Address: 0x14 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 4 3 2 1 0 rw rw 15 14 13 Res. Res. Res. TRIMOFFSETP rw rw rw rw 7 6 5 Res. Res. Res. rw TRIMOFFSETN rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs DocID029587 Rev 3 1049/3178 1051 Operational amplifiers (OPAMP) 29.6.7 RM0433 OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR) Address: 0x18 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. rw rw rw rw TRIMHSOFFSETP rw rw rw TRIMHSOFFSETN rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMHSOFFSETP[4:0]: High-speed mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMHSOFFSETN[4:0]: High-speed mode trim for NMOS differential pairs 1050/3178 DocID029587 Rev 3 rw rw 0x18 Reset value (1) (1) OPAMP2_ HSOTR TRIMHS OFFSETP[4:0] TRIMHS OFFSETN[4:0] Reset value DocID029587 Rev 3 0 TRIM OFFSETP[4:0] 0 (1) 0 Res. 0 Res. Res. Res. Res. OPAHSM Res. 0 0 Res. 0 Res. Res. Res. Res. OPAEN VP_SEL Res. VM_SEL Res. OPAHSM Res. Res. CALON CALSEL PGA_GAIN USERTRIM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FORCE_VP 0 OPAEN (1) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 FORCE_VP VP_SEL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. TRIMHS OFFSETN[4:0] Res. Res. TSTREF 0 Res. VM_SEL Res. Res. Res. Res. CALON Reset value 0 Res. Res. Res. Res. CALSEL Res. Res. Res. TRIMHS OFFSETP[4:0] Res. Res. Res. TRIM OFFSETP[4:0] Res. Res. USERTRIM 0 0 Res. Res. Res. 0 0 Res. Res. Res. OPAMP1_ HSOTR Res. Res. CALOUT 0 Res. Res. Res. Res. 0 Res. Res. Res. 0 0 Res. Res. Res. (1) Res. Res. Res. 0 Res. Res. Res. PGA_GAIN Res. Res. 0 Res. Res. Res. (1) Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. TSTREF 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OPAMP2_OTR Res. Reset value Res. Reset value 0 Res. 0x14 OPAMP2_CSR 0 Res. 0x10 OPAMP_OR Res. Reset value Res. 0x0C Res. 0x08 OPAMP1_OTR CALOUT 0x04 OPAMP1_CSR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 29.6.8 Res. RM0433 Operational amplifiers (OPAMP) OPAMP register map Table 228. OPAMP register map and reset values TRIM OFFSETN[4:0] 0 0 (1) TRIM OFFSETN[4:0] 0 0 (1) 1. Factory trimmed values. Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1051/3178 1051 Digital filter for sigma delta modulators (DFSDM) RM0433 30 Digital filter for sigma delta modulators (DFSDM) 30.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution. DFSDM also features optional parallel data stream input from internal ADC peripherals or from microcontroller memory. An external Σ∆ modulator provides digital data stream of converted analog values from the external Σ∆ modulator analog input. This digital data stream is sent into a DFSDM input channel through a serial interface. DFSDM supports several standards to connect various Σ∆ modulator outputs: SPI interface and Manchester coded 1-wire interface (both with adjustable parameters). DFSDM module supports the connection of up to 8 multiplexed input digital serial channels which are shared with up to 4 DFSDM modules. DFSDM module also supports alternative parallel data inputs from up to 8 internal 16-bit data channels (from internal ADCs or from microcontrollers memory). DFSDM is converting an input data stream into a final digital data word which represents an analog input value on a Σ∆ modulator analog input. The conversion is based on a configurable digital process: the digital filtering and decimation of the input serial data stream. The conversion speed and resolution are adjustable according to configurable parameters for digital processing: filter type, filter order, length of filter, integrator length. The maximum output data resolution is up to 24 bits. There are two conversion modes: single conversion mode and continuous mode. The data can be automatically stored in a system RAM buffer through DMA, thus reducing the software overhead. A flexible timer triggering system can be used to control the start of conversion of DFSDM. This timing control is capable of triggering simultaneous conversions or inserting a programmable delay between conversions. DFSDM features an analog watchdog function. Analog watchdog can be assigned to any of the input channel data stream or to final output data. Analog watchdog has its own digital filtering of input data stream to reach the required speed and resolution of watched data. To detect short-circuit in control applications, there is a short-circuit detector. This block watches each input channel data stream for occurrence of stable data for a defined time duration (several 0’s or 1’s in an input data stream). An extremes detector block watches final output data and stores maximum and minimum values from the output data values. The extremes values stored can be restarted by software. Two power modes are supported: normal mode and stop mode. 1052/3178 DocID029587 Rev 3 RM0433 30.2 Digital filter for sigma delta modulators (DFSDM) DFSDM main features • • • • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – clock output for Σ∆ modulator(s) Alternative inputs from up to 8 internal digital parallel channels: – inputs with up to 16 bit resolution – internal sources: ADCs data or memory (CPU/DMA write) data streams Adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) Up to 24-bit output data resolution: – right bit-shifter on final data (0..31 bits) • Signed output data format • Automatic data offset correction (offset stored in register by user) • Continuous or single conversion • Start-of-conversion synchronization with: • • – software trigger – internal timers – external events – start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0) Analog watchdog feature: – low value and high value data threshold registers – own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from output data register or from one or more input digital serial channels – continuous monitoring independently from standard conversion Short-circuit detector to detect saturated analog input values (bottom and top ranges): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream – monitoring continuously each channel (8 serial channel transceiver outputs) • Break generation on analog watchdog event or short-circuit detector event • Extremes detector: – store minimum and maximum values of output data values – refreshed by software • DMA may be used to read the conversion data • Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions DocID029587 Rev 3 1053/3178 1108 Digital filter for sigma delta modulators (DFSDM) 30.3 RM0433 DFSDM implementation This section describes the configuration implemented in DFSDMx. Table 229. DFSDM1 implementation DFSDM features 1054/3178 DFSDM1 Number of channels 8 Number of filters 4 Input from internal ADC X Supported trigger sources 32 Pulses skipper - ID registers support - DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) 30.4 DFSDM functional description 30.4.1 DFSDM block diagram Figure 216. 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This example shows 4 DFSDM filters and 8 input channels (max. configuration). DocID029587 Rev 3 1055/3178 1108 Digital filter for sigma delta modulators (DFSDM) 30.4.2 RM0433 DFSDM pins and internal signals Table 230. DFSDM external pins Name Signal Type Remarks VDD Power supply Digital power supply. VSS Power supply Digital ground power supply. CKIN[7:0] Clock input Clock signal provided from external Σ∆ modulator. FT input. DATIN[7:0] Data input Data signal provided from external Σ∆ modulator. FT input. CKOUT Clock output Clock output to provide clock signal into external Σ∆ modulator. EXTRG[1:0] External trigger Input trigger from two EXTI signals to start analog signal conversion (from GPIOs: EXTI11, EXTI15). Table 231. DFSDM internal signals Name Signal Type Remarks dfsdm_jtrg[31:0] Internal/ external trigger signal Input trigger from internal/external trigger sources in order to start analog conversion (from internal sources: synchronous input, from external sources: asynchronous input with synchronization). See Table 232 for details. dfsdm_break[3:0] break signal output Break signals event generation from Analog watchdog or short-circuit detector dfsdm_dma[3:0] DMA request signal DMA request signal from each DFSDM_FLTx (x=0..3): end of injected conversion event. dfsdm_it[3:0] Interrupt request signal Interrupt signal for each DFSDM_FLTx (x=0..3) dfsdm_dat_adc[15:0] ADC input data Up to 4 internal ADC data buses as parallel inputs. Table 232. DFSDM triggers connection Trigger name 1056/3178 Trigger source dfsdm_jtrg0 TIM1_TRGO dfsdm_jtrg1 TIM1_TRGO2 dfsdm_jtrg2 TIM8_TRGO dfsdm_jtrg3 TIM8_TRGO2 dfsdm_jtrg4 TIM3_TRGO dfsdm_jtrg5 TIM4_TRGO dfsdm_jtrg6 TIM16_OC1 dfsdm_jtrg7 TIM6_TRGO dfsdm_jtrg8 TIM7_TRGO dfsdm_jtrg9 HRTIM1_ADCTRG1 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Table 232. DFSDM triggers connection (continued) Trigger name Trigger source dfsdm_jtrg10 HRTIM1_ADCTRG3 dfsdm_jtrg[23:11] Reserved dfsdm_jtrg24 EXTI11 dfsdm_jtrg25 EXTI15 dfsdm_jtrg26 LPTIMER1 dfsdm_jtrg27 LPTIMER2 dfsdm_jtrg28 LPTIMER3 dfsdm_jtrg[31:29] Reserved Table 233. DFSDM break connection Break name 30.4.3 Break destination dfsdm_break[0] TIM15 break dfsdm_break[1] TIM16 break2 dfsdm_break[2] TIM1/TIM17/TIM8 break dfsdm_break[3] TIM1/TIM8 break2 DFSDM reset and clocks DFSDM on-off control The DFSDM interface is globally enabled by setting DFSDMEN=1 in the DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7) and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in DFSDM_FLTxCR1). Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sincx digital filter unit and integrator unit are reinitialized. By clearing DFEN, any conversion which may be in progress is immediately stopped and DFSDM_FLTx is put into stop mode. All register settings remain unchanged except DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset). Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register. Once the channel is enabled, it receives serial data from the external Σ∆ modulator or parallel internal data sources (ADCs or CPU/DMA wire from memory). DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before stopping the system clock to enter in the STOP mode of the device. DFSDM clocks The internal DFSDM clock fDFSDMCLK, which is used to drive the channel transceivers, digital processing blocks (digital filter, integrator) and next additional blocks (analog DocID029587 Rev 3 1057/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC block and is derived from the system clock SYSCLK (max. up to fSYSCLK = MHz) or peripheral clock PCLK2 (see DFSDMSEL bit description in ). The DFSDM clock is automatically stopped in stop mode (if DFEN = 0 for all DFSDM_FLTx, x=0..3). The DFSDM serial channel transceivers can receive an external serial clock to sample an external serial data stream. The internal DFSDM clock must be at least 4 times faster than the external serial clock if standard SPI coding is used, and 6 times faster than the external serial clock if Manchester coding is used. DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock input(s). It is provided on CKOUT pin. This output clock signal must be in the range specified in given device datasheet and is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) by programmable divider in the range 2 - 256 (CKOUTDIV in DFSDM_CH0CFGR1 register). Audio clock source is SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration (see ). 30.4.4 Serial channel transceivers There are 8 multiplexed serial data channels which can be selected for conversion by each filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester coded format (see SITP[1:0] bits in DFSDM_CHyCFGR1 register). The channel is enabled for operation by setting CHEN=1 in DFSDM_CHyCFGR1 register. Channel inputs selection Serial inputs (data and clock signals) from DATINy and CKINy pins can be redirected from the following channel pins. This serial input channel redirection is set by CHINSEL bit in DFSDM_CHyCFGR1 register. Channel redirection can be used to collect audio data from PDM (pulse density modulation) stereo microphone type. PDM stereo microphone has one data and one clock signal. Data signal provides information for both left and right audio channel (rising clock edge samples for left channel and falling clock edge samples for right channel). Configuration of serial channels for PDM microphone input: 1058/3178 • PDM microphone signals (data, clock) will be connected to DFSDM input serial channel y (DATINy, CKOUT) pins. • Channel y will be configured: CHINSEL = 0 (input from given channel pins: DATINy, CKINy). • Channel (y-1) (modulo 8) will be configured: CHINSEL = 1 (input from the following channel ((y-1)+1) pins: DATINy, CKINy). • Channel y: SITP[1:0] = 0 (rising edge to strobe data) => left audio channel on channel y. • Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) => right audio channel on channel y-1. • Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and right channels from PDM microphone). DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Figure 217. Input channel pins redirection 'HFRGH '$7,1 \PD[ &.,1 \PD[ &+ \PD[ )/7 [PD[ 'HFRGH '$7,1\ &.,1\ &+\ )/7 [ )/7[ 'HFRGH '$7,1 \ &.,1 \ &+ \ )/7 'HFRGH '$7$,1 &.,1 &+ 5&+ &+,16(/ 06Y9 Output clock generation A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CH0CFGR1 register). If the output clock is stopped, then CKOUT signal is set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHyCFGR1 register or by DFSDMEN=0 in DFSDM_CH0CFGR1 register). The output clock stopping is performed: • 4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0) • 1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1) Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid glitch on CKOUT pin. The output clock signal frequency must be in the range 0 - 20 MHz. DocID029587 Rev 3 1059/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 SPI data input format operation In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DATINy pin. A clock signal can be provided externally from CKINy pin or internally from a signal derived from the CKOUT signal source. In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DATINy pin) is sampled on rising or falling clock edge (of CKINy pin) according SITP[1:0] bits setting (in DFSDM_CHyCFGR1 register). Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHyCFGR1 register: • • • Note: CKOUT signal: – For connection to external Σ∆ modulator which uses directly its clock input (from CKOUT) to generate its output serial communication clock. – Sampling point: on rising/falling edge according SITP[1:0] setting. CKOUT/2 signal (generated on CKOUT rising edge): – For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). – Sampling point: on each second CKOUT falling edge. CKOUT/2 signal (generated on CKOUT falling edge): – For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). – Sampling point: on each second CKOUT rising edge. An internal clock source can only be used when the external Σ∆ modulator uses CKOUT signal as a clock input (to have synchronous clock and data operation). Internal clock source usage can save CKINy pin connection (CKINy pins can be used for other purpose). The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less than fDFSDMCLK/4. Manchester coded data input format operation In Manchester coded format, the data stream is sent in serial format through DATINy pin only. Decoded data and clock signal are recovered from serial stream after Manchester decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in DFSDM_CHyCFGR1 register): • signal rising edge = log 0; signal falling edge = log 1 • signal rising edge = log 1; signal falling edge = log 0 The recovered clock signal frequency for Manchester coding must be in the range 0 - 10 MHz and less than fDFSDMCLK/6. To correctly receive Manchester coded data, the CKOUTDIV divider (in DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate according formula: ( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK ) 1060/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) &.,1\ 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 '$7,1\ 63,WLPLQJ 63,&.6(/ Figure 218. Channel transceiver timing diagrams WVX WK 6,73 &.287 63,&.6(/ 63,&.6(/ WVX WK WZO WZK 6,73 '$7,1\ 63,WLPLQJ 63,&.6(/ 63,&.6(/ WVX WK 6,73 '$7,1\ 0DQFKHVWHUWLPLQJ 6,73 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD 069 DocID029587 Rev 3 1061/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register. If enabled, then this clock absence detection is performed continuously on a given channel. A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in case of an input clock error (see CKABF[7:0] in DFSDM_FLT0ISR register and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in DFSDM_FLT0ICR register), the clock absence flag is refreshed. Clock absence status bit CKABF[y] is set also by hardware when corresponding channel y is disabled (if CHEN[y] = 0 then CKABF[y] is held in set state). When a clock absence event has occurred, the data conversion (and/or analog watchdog and short-circuit detector) provides incorrect data. The user should manage this event and discard given data while a clock absence is reported. The clock absence feature is available only when the system clock is used for the CKOUT signal (CKOUTSRC=0 in DFSDM_CH0CFGR1 register). When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register). The software sequence concerning clock absence detection feature should be: • Enable given channel by CHEN = 1 • Try to clear the clock absence flag (by CLRCKABF = 1) until the clock absence flag is really cleared (CKABF = 0). At this time, the transceiver is synchronized (signal clock is valid) and is able to receive data. • Enable the clock absence feature CKABEN = 1 and the associated interrupt CKABIE = 1 to detect if the SPI clock is lost or Manchester data edges are missing. If SPI data format is used, then the clock absence detection is based on the comparison of an external input clock with an output clock generation (CKOUT signal). The external input clock signal into the input channel must be changed at least once per 8 signal periods of CKOUT signal (which is controlled by CKOUTDIV field in DFSDM_CH0CFGR1 register). Figure 219. Clock absence timing diagram for SPI 63,FORFNSUHVHQFH WLPLQJ PD[SHULRGV &.287 UHVWDUWFRXQWLQJ &.,1\ ODVWFORFNFKDQJH &.$%)>\@ HUURUUHSRUWHG 069 If Manchester data format is used, then the clock absence means that the clock recovery is unable to perform from Manchester coded signal. For a correct clock recovery, it is first necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 221 for Manchester synchronization). 1062/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register). This condition also defines the minimum data rate to be able to correctly recover the Manchester coded data and clock signals. The maximum data rate of Manchester coded data must be less than the CKOUT signal. So to correctly receive Manchester coded data, the CKOUTDIV divider must be set according the formula: ( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK ) A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in case of an input clock recovery error (see CKABF[7:0] in DFSDM_FLT0ISR register and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in DFSDM_FLT0ICR register), the clock absence flag is refreshed. Figure 220. Clock absence timing diagram for Manchester coding PD[SHULRGV &.287 6,73 '$7,1\ 0DQFKHVWHUFORFNSUHVHQFH WLPLQJ UHVWDUWFRXQWLQJ ODVWGDWDFKDQJH 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD " " &.$%)>\@ HUURUUHSRUWHG 069 DocID029587 Rev 3 1063/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter: CKABF[y] flag is cleared by setting CLRCKABF[y] bit. If channel y is not yet synchronized the hardware immediately set the CKABF[y] flag. Software is then reading back the CKABF[y] flag and if it is set then perform again clearing of this flag by setting CLRCKABF[y] bit. This software sequence (polling of CKABF[y] flag) continues until CKABF[y] flag is set (signalizing that Manchester stream is synchronized). To be able to synchronize/receive Manchester coded data the CKOUTDIV divider (in DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate according the formula below. ( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK ) SPI coded stream is synchronized after first detection of clock input signal (valid rising/falling edge). Note: 1064/3178 When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register). DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Figure 221. First conversion for Manchester coding (Manchester synchronization) '$7,1\ 0DQFKHVWHUWLPLQJ 6,73 6,73 UHFRYHUHGFORFN GDWDIURP PRGXODWRU &+(1 UHDOVWDUWRIILUVWFRQYHUVLRQ ILUVWFRQYHUVLRQ VWDUWWULJJHU UHFRYHUHGGDWD ILUVWGDWDELWWRJJOHHQGRI0DQFKHVWHUV\QFKURQL]DWLRQ " " &.$%)>\@ FOHDULQJRI&.$%)>\@IODJE\VRIWZDUHSROOLQJ 06 9 External serial clock frequency measurement The measuring of a channel serial clock input frequency provides a real data rate from an external Σ∆ modulator, which is important for application purposes. An external serial clock input frequency can be measured by a timer counting DFSDM clocks (fDFSDMCLK) during one conversion duration. The counting starts at the first input data clock after a conversion trigger (regular or injected) and finishes by last input data clock before conversion ends (end of conversion flag is set). Each conversion duration (time between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in register DFSDM_FLTxCNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1). The user can then compute the data rate according to the digital filter settings (FORD, FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter is bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in DFSDM_FLTxCNVTIMR register). In case of parallel data input (Section 30.4.6: Parallel data inputs) the measured frequency is the average input data rate during one conversion. DocID029587 Rev 3 1065/3178 1108 Digital filter for sigma delta modulators (DFSDM) Note: RM0433 When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1): for Sincx filters (x=1..5): t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN for FastSinc filter: t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN regular conversion with FAST = 1 (except first conversion): for Sincx and FastSinc filters: t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: • fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate (in case of parallel data input) • FOSR is the filter oversampling ratio: FOSR = FOSR[9:0]+1 (see DFSDM_FLTxFCR register) • IOSR is the integrator oversampling ratio: IOSR = IOSR[7:0]+1 (see DFSDM_FLTxFCR register) • FORD is the filter order: FORD = FORD[2:0] (see DFSDM_FLTxFCR register) Channel offset setting Each channel has its own offset setting (in register) which is finally subtracted from each conversion result (injected or regular) from a given channel. Offset correction is performed after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0] field in DFSDM_CHyCFGR2 register. Data right bit shift To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts which will be applied on each conversion result (injected or regular) from a given channel. The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register. The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained, in order to have valid 24-bit signed format of result data. 1066/3178 DocID029587 Rev 3 RM0433 30.4.5 Digital filter for sigma delta modulators (DFSDM) Configuring the input serial interface The following parameters must be configured for the input serial interface: 30.4.6 • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in DFSDM_CH0CFGR1 register. • Serial interface type and input clock phase. Selection of SPI or Manchester coding and sampling edge of input clock. It is defined by SITP [1:0] bits in DFSDM_CHyCFGR1 register. • Input clock source. External source from CKINy pin or internal from CKOUT pin. It is defined by SPICKSEL[1:0] field in DFSDM_CHyCFGR1 register. • Final data right bit-shift. Defines the final data right bit shift to have the result aligned to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHyCFGR2 register. • Channel offset per channel. Defines the analog offset of a given serial channel (offset of connected external Σ∆ modulator). It is defined by OFFSET[23:0] bits in DFSDM_CHyCFGR2 register. • short-circuit detector and clock absence per channel enable. To enable or disable the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by CKABEN bit) on a given serial channel in register DFSDM_CHyCFGR1. • Analog watchdog filter and short-circuit detector threshold settings. To configure channel analog watchdog filter parameters and channel short-circuit detector parameters. Configurations are defined in DFSDM_CHyAWSCDR register. Parallel data inputs Each input channel provides a register for 16-bit parallel data input (besides serial data input). Each 16-bit parallel input can be sourced from internal data sources only: • internal ADC results(3) • direct CPU/DMA writing. The selection for using serial or parallel data input for a given channel is done by field DATMPX[1:0] of DFSDM_CHyCFGR1 register. In DATMPX[1:0] is also defined the parallel data source: internal ADC(3) or direct write by CPU/DMA. Each channel contains a 32-bit data input register DFSDM_CHyDATINR in which it can be written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to the digital filter which is accepting 16-bit parallel data. If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHyDATINR register is write protected. Input from internal ADC(3) In case of ADC data parallel input (DATMPX[1:0]=1) the ADC[y+1] result is assigned to channel y input (ADC1 is filling DFSDM_CHDATIN0R register, ADC2 is filling DFSDM_CHDATIN1R register, ... , ADC8 is filling DFSDM_CHDATIN7R register). End of conversion event from ADC[y+1] causes update of channel y data (parallel data from ADC[y+1] are put as next sample to digital filter). Data from ADC[y+1] is written into DFSDM_CHyDATINR register (field INDAT0[15:0]) when end of conversion event occurred. 3. ADC1 and ADC2 only. DocID029587 Rev 3 1067/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 The setting of data packing mode (DATPACK[1:0] in the DFSDM_CHyCFGR1 register) has no effect in case of ADC data input. Note: Extension of ADC specification: in case the internal ADC is configured in interleaved mode (e.g. ADC1 together with ADC2 - see ADC specification) then each result from ADC1 or from ADC2 will come to the same 16-bit bus - to the bus of ADC1 - which is coming into DFSDM channel 0 (fixed connection). So there will be double input data rate into DFSDM channel 0 (even samples come from ADC1 and odd samples from ADC2). Channel 1 associated with ADC2 will be free. Input from memory (direct CPU/DMA write) The direct data write into DFSDM_CHyDATINR register by CPU or DMA (DATMPX[1:0]=2) can be used as data input in order to process digital data streams from memory or peripherals. Data can be written by CPU or DMA into DFSDM_CHyDATINR register: 1. CPU data write: Input data are written directly by CPU into DFSDM_CHyDATINR register. 2. DMA data write: The DMA should be configured in memory-to-memory transfer mode to transfer data from memory buffer into DFSDM_CHyDATINR register. The destination memory address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input. This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading. The accesses to DFSDM_CHyDATINR can be either 16-bit or 32-bit wide, allowing to load respectively one or two samples in one write operation. 32-bit input data register (DFSDM_CHyDATINR) can be filled with one or two 16-bit data samples, depending on the data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHyCFGR1 register: 1. Standard mode (DATPACK[1:0]=0): Only one sample is stored in field INDAT0[15:0] of DFSDM_CHyDATINR register which is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and write protected. The digital filter must perform one input sampling (from INDAT0[15:0]) to empty data register after it has been filled by CPU/DMA. This mode is used together with 16-bit CPU/DMA access to DFSDM_CHyDATINR register to load one sample per write operation. 2. Interleaved mode (DATPACK[1:0]=1): DFSDM_CHyDATINR register is used as a two sample buffer. The first sample is stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR register. This mode is used together with 32-bit CPU/DMA access to DFSDM_CHyDATINR register to load two samples per write operation. 3. Dual mode (DATPACK[1:0]=2): Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is automatically copied INDAT0[15:0] of the following (y+1) channel data register 1068/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR registers. Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y = 0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0] and INDAT1[15:0] parts are write protected for this channel. If even channel is set to Dual mode then the following odd channel must be set into Standard mode (DATPACK[1:0]=0) for correct cooperation with even channels. See Figure 222 for DFSDM_CHyDATINR registers data modes and assignments of data samples to channels. Figure 222. DFSDM_CHyDATINR registers operation modes and assignment 6WDQGDUGPRGH ,QWHUOHDYHGPRGH 'XDOPRGH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG \ &K VDPSOH \ &K VDPSOH &K VDPSOH \ 8QXVHG &K VDPSOH \ &K VDPSOH &K VDPSOH \ 8QXVHG &K VDPSOH \ &K VDPSOH &K VDPSOH \ 8QXVHG &K VDPSOH \ 069 The write into DFSDM_CHyDATINR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y). Otherwise written data are lost for next processing. For example: for single conversion and interleaved mode, do not start writing pair of data samples into DFSDM_CHyDATINR before the single conversion is started (any data present in the DFSDM_CHyDATINR before starting a conversion is discarded). 30.4.7 Channel selection There are 8 multiplexed channels which can be selected for conversion using the injected channel group and/or using the regular channel. The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the DFSDM_FLTxJCHGR register selects the channels of the injected group, where JCHG[y]=1 means that channel y is selected. Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In scan mode, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first, followed immediately by the next higher channel until all the channels selected by JCHG[7:0] have been converted. In single mode (JSCAN=0), only one channel from the selected channels is converted, and the channel selection is moved to the next channel. Writing to JCHG[7:0] if JSCAN=0 resets the channel selection to the lowest selected channel. DocID029587 Rev 3 1069/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Injected conversions can be launched by software or by a trigger. They are never interrupted by regular conversions. The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the DFSDM_FLTxCR1 register indicates the selected channel. Regular conversions can be launched only by software (not by a trigger). A sequence of continuous regular conversions is temporarily interrupted when an injected conversion is requested. Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHyCFGR1 register) causes that the conversion will never end - because no input data is provided (with no clock signal). In this case, it is necessary to enable a given channel (CHEN=1 in DFSDM_CHyCFGR1 register) or to stop the conversion by DFEN=0 in DFSDM_FLTxCR1 register. 30.4.8 Digital filter configuration DFSDM contains a Sincx type digital filter implementation. This Sincx filter performs an input digital data stream filtering, which results in decreasing the output data rate (decimation) and increasing the output data resolution. The Sincx digital filter is configurable in order to reach the required output data rates and required output data resolution. The configurable parameters are: • • Filter order/type: (see FORD[2:0] bits in DFSDM_FLTxFCR register): – FastSinc – Sinc1 – Sinc2 – Sinc3 – Sinc4 – Sinc5 Filter oversampling/decimation ratio (see FOSR[9:0] bits in DFSDM_FLTxFCR register): – FOSR = 1-1024 – FOSR = 1-215 – FOSR = 1-73 - for FastSinc filter and Sincx filter x = FORD = 1..3 - for Sincx filter x = FORD = 4 - for Sincx filter x = FORD = 5 The filter has the following transfer function (impulse response in H domain): • x Sincx filter type: ⎛ 1 – z – FOSR⎞ -⎟ H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠ FastSinc filter type: ⎛ 1 – z– FOSR⎞ -⎟ ⋅ ( 1 + z –( 2 ⋅ H ( z ) = ⎜ ---------------------------–1 ⎝ 1–z ⎠ 2 • 1070/3178 DocID029587 Rev 3 FOSR ) ) RM0433 Digital filter for sigma delta modulators (DFSDM) *DLQ G% Figure 223. Example: Sinc3 filter response 1RUPDOL]HGIUHTXHQF\ I,1I'$7$ 069 Table 234. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc1 Sinc2 FastSinc Sinc3 Sinc4 Sinc5 x +/- x +/- x2 +/- 2x2 +/- x3 +/- x4 +/- x5 4 +/- 4 +/- 16 +/- 32 +/- 64 +/- 256 +/- 1024 8 +/- 8 +/- 64 +/- 128 +/- 512 +/- 4096 - 32 +/- 32 +/- 1024 +/- 2048 +/- 32768 +/- 1048576 +/- 33554432 64 +/- 64 +/- 4096 +/- 8192 +/- 262144 +/- 16777216 +/- 1073741824 128 +/- 128 +/- 16384 +/- 32768 +/- 2097152 +/- 268435456 256 +/- 256 +/- 65536 +/- 131072 +/- 16777216 1024 +/- 1024 +/- 1048576 Result can overflow on full scale input (> 32-bit signed integer) +/- 2097152 +/- 1073741824 For more information about Sinc filter type properties and usage, it is recommended to study the theory about digital filters (more resources can be downloaded from internet). 30.4.9 Integrator unit The integrator performs additional decimation and a resolution increase of data coming from the digital filter. The integrator simply performs the sum of data from a digital filter for a given number of data samples from a filter. The integrator oversampling ratio parameter defines how many data counts will be summed to one data output from the integrator. IOSR can be set in the range 1-256 (see IOSR[7:0] bits description in DFSDM_FLTxFCR register). DocID029587 Rev 3 1071/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Table 235. Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) IOSR x 30.4.10 Sinc1 Sinc2 FastSinc +/- FOSR. x +/- FOSR2. x +/- 2.FOSR2. x Sinc3 Sinc4 Sinc5 +/- FOSR3. x +/- FOSR4. x +/- FOSR5. x 4 - - - +/- 67 108 864 - - 32 - - - +/- 536 870 912 - - 128 - - - +/- 2 147 483 648 - - 256 - - - +/- 232 - - Analog watchdog The analog watchdog purpose is to trigger an external signal (break or interrupt) when an analog signal reaches or crosses given maximum and minimum threshold values. An interrupt/event/break generation can then be invoked. Each analog watchdog will supervise serial data receiver outputs (after the analog watchdog filter on each channel) or data output register (current injected or regular conversion result) according to AWFSEL bit setting (in DFSDM_FLTxCR1 register). The input channels to be monitored or not by the analog watchdog x will be selected by AWDCH[7:0] in DFSDM_FLTxCR2 register. Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0). There are high and low threshold registers which are compared with given data values (set by AWHT[23:0] bits in DFSDM_FLTxAWHTR register and by AWLT[23:0] bits in DFSDM_FLTxAWLTR register). 1072/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) There are 2 options for comparing the threshold registers with the data values • • Option1: in this case, the input data are taken from final output data register (AWFSEL=0). This option is characterized by: – high input data resolution (up to 24-bits) – slow response time - inappropriate for fast response applications like overcurrent detection – for the comparison the final data are taken after bit shifting and offset data correction – final data are available only after main regular or injected conversions are performed – can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in DFSDM_CHyCFGR1 register) Option2: in this case, the input data are taken from any serial data receivers output (AWFSEL=1). This option is characterized by: – input serial data are processed by dedicated analog watchdog Sincx channel filters with configurable oversampling ratio (1..32) and filter order (1..3) (see AWFOSR[4:0] and AWFORD[1:0] bits setting in DFSDM_CHyAWSCDR register) – lower resolution (up to 16-bit) – fast response time - appropriate for applications which require a fast response like overcurrent/overvoltage detection) – data are available in continuous mode independently from main regular or injected conversions activity In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is taken from channels selected by AWDCH[7:0] field (DFSDM_FLTxCR2 register). Each of the selected channels filter result is compared to one threshold value pair (AWHT[23:0] / AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit threshold compared with the analog watchdog filter output because data coming from the analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken into comparison in this case (AWFSEL=1). Parameters of the analog watchdog filter configuration for each input channel are set in DFSDM_CHyAWSCDR register (filter order AWFORD[1:0] and filter oversampling ratio AWFOSR[4:0]). Each input channel has its own comparator which compares the analog watchdog data (from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When several channels are selected (field AWDCH[7:0] field of DFSDM_FLTxCR2 register), several comparison requests may be received simultaneously. In this case, the channel request with the lowest number is managed first and then continuing to higher selected channels. For each channel, the result can be recorded in a separate flag (fields AWHTF[7:0], AWLTF[7:0] of DFSDM_FLTxAWSR register). Each channel request is executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog feature at this input clock speed. Therefore user must properly configure the number of watched channels and analog watchdog filter parameters with respect to input sampling clock speed and DFSDM frequency. DocID029587 Rev 3 1073/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Analog watchdog filter data for given channel y is available for reading by firmware on field WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate given by the analog watchdog filter setting and the channel input clock frequency. The analog watchdog filter conversion works like a regular Fast Continuous Conversion without the intergator. The number of serial samples needed for one result from analog watchdog filter output (at channel input clock frequency fCKIN): first conversion: for Sincx filters (x=1..5): number of samples = [FOSR * FORD + FORD + 1] for FastSinc filter: number of samples = [FOSR * 4 + 2 + 1] next conversions: for Sincx and FastSinc filters: number of samples = [FOSR * IOSR] where: FOSR ....... filter oversampling ratio: FOSR = AWFOSR[4:0]+1 (see DFSDM_CHyAWSCDR register) FORD ....... the filter order: FORD = AWFORD[1:0] (see DFSDM_CHyAWSCDR register) In case of output data register monitoring (AWFSEL=0), the comparison is done after a right bit shift and an offset correction of final data (see OFFSET[23:0] and DTRBS[4:0] fields in DFSDM_CHyCFGR2 register). A comparison is performed after each injected or regular end of conversion for the channels selected by AWDCH[7:0] field (in DFSDM_FLTxCR2 register). The status of an analog watchdog event is signalized in DFSDM_FLTxAWSR register where a given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on channel y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched events in DFSDM_FLTxAWSR register are cleared by writing ‘1’ into the corresponding clearing bit CLRAWHTF[y] or CLRAWLTF[y] in DFSDM_FLTxAWCFR register. The global status of an analog watchdog is signalized by the AWDF flag bit in DFSDM_FLTxISR register (it is used for the fast detection of an interrupt source). AWDF=1 signalizes that at least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one channel). AWDF bit is cleared when all AWHTF[7:0] and AWLTF[7:0] are cleared. An analog watchdog event can be assigned to break output signal. There are four break outputs to be assigned to a high or low threshold crossing event (dfsdm_break[3:0]). The break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and BKAWL[3:0] fields in DFSDM_FLTxAWHTR and DFSDM_FLTxAWLTR register. 30.4.11 Short-circuit detector The purpose of a short-circuit detector is to signalize with a very fast response time if an analog signal reached saturated values (out of full scale ranges) and remained on this value given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or overvoltage). An interrupt/event/break generation can be invoked. Input data into a short-circuit detector is taken from channel transceiver outputs. There is an upcounting counter on each input channel which is counting consecutive 0’s or 1’s on serial data receiver outputs. A counter is restarted if there is a change in the data stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit threshold register value (SCDT[7:0] bits in DFSDM_CHyAWSCDR register), then a short- 1074/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) circuit event is invoked. Each input channel has its short-circuit detector. Any channel can be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1 register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits, status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]). Status flag SCDF[y] is cleared also by hardware when corresponding channel y is disabled (CHEN[y] = 0). On each channel, a short-circuit detector event can be assigned to break output signal dfsdm_break[3:0]. There are four break outputs to be assigned to a short-circuit detector event. The break signal assignment to a given channel short-circuit detector event is done by BKSCD[3:0] field in DFSDM_CHyAWSCDR register. Short circuit detector cannot be used in case of parallel input data channel selection (DATMPX[1:0] ≠ 0 in DFSDM_CHyCFGR1 register). Four break outputs are totally available (shared with the analog watchdog function). 30.4.12 Extreme detector The purpose of an extremes detector is to collect the minimum and maximum values of final output data words (peak to peak values). If the output data word is higher than the value stored in the extremes detector maximum register (EXMAX[23:0] bits in DFSDM_FLTxEXMAX register), then this register is updated with the current output data word value and the channel from which the data is stored is in EXMAXCH[2:0] bits (in DFSDM_FLTxEXMAX register) . If the output data word is lower than the value stored in the extremes detector minimum register (EXMIN[23:0] bits in DFSDM_FLTxEXMIN register), then this register is updated with the current output data word value and the channel from which the data is stored is in EXMINCH[2:0] bits (in DFSDM_FLTxEXMIN register). The minimum and maximum register values can be refreshed by software (by reading given DFSDM_FLTxEXMAX or DFSDM_FLTxEXMIN register). After refresh, the extremes detector minimum data register DFSDM_FLTxEXMIN is filled with 0x7FFFFF (maximum positive value) and the extremes detector maximum register DFSDM_FLTxEXMAX is filled with 0x800000 (minimum negative value). The extremes detector performs a comparison after a right bit shift and an offset data correction. For each extremes detector, the input channels to be considered into computing the extremes value are selected in EXCH[7:0] bits (in DFSDM_FLTxCR2 register). 30.4.13 Data unit block The data unit block is the last block of the whole processing path: External Σ∆ modulators Serial transceivers - Sinc filter - Integrator - Data unit block. The output data rate depends on the serial data stream rate, and filter and integrator settings. The maximum output data rate is: Datarate samples ⁄ s f CKIN = ---------------------------------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 ) Datarate samples ⁄ s f CKIN = ----------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 ) DocID029587 Rev 3 ...FAST = 0, Sincx filter ...FAST = 0, FastSinc filter 1075/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 or Datarate samples ⁄ s f CKIN = ---------------------------------F OSR ⋅ I OSR ...FAST = 1 Maximum output data rate in case of parallel data input: Datarate samples ⁄ s f DATAIN_RATE = ---------------------------------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 ) ...FAST = 0, Sincx filter or Datarate samples ⁄ s f DATAIN_RATE = ----------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 ) ...FAST = 0, FastSinc filter or Datarate samples ⁄ s f DATAIN_RATE = -----------------------------------F OSR ⋅ I OSR ...FAST=1 or any filter bypass case ( F OSR = 1 ) where: f DATAIN_RATE ...input data rate from ADC or from CPU/DMA The right bit-shift of final data is performed in this module because the final data width is 24bit and data coming from the processing path can be up to 32 bits. This right bit-shift is configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained - to have valid 24-bit signed format of result data. In the next step, an offset correction of the result is performed. The offset correction value (OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate calibration routine. Due to the fact that all operations in digital processing are performed on 32-bit signed registers, the following conditions must be fulfilled not to overflow the result: FOSR FORD . IOSR <= 231 ... for Sincx filters, x = 1..5) 2 . FOSR 2 . IOSR <= 231 ... for FastSinc filter) Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate (fDATAIN_RATE) must be limited to be able to read all output data: fDATAIN_RATE ≤ fAPB where fAPB is the bus frequency to which the DFSDM peripheral is connected. 30.4.14 Signed data format Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be used for a differential or single-ended signal measurement. A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and ones from a Σ∆ modulator represents values -1 and +1). 1076/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction. The msb of output data word represents the sign of value (two’s complement format). 30.4.15 Launching conversions Injected conversions can be launched using the following methods: • Software: writing ‘1’ to JSWSTART in the DFSDM_FLTxCR1 register. • Trigger: JEXTSEL[4:0] selects the trigger signal while JEXTEN activates the trigger and selects the active edge at the same time (see the DFSDM_FLTxCR1 register). • Synchronous with DFSDM_FLT0 if JSYNC=1: for DFSDM_FLTx (x>0), an injected conversion is automatically launched when in DFSDM_FLT0; the injected conversion is started by software (JSWSTART=1 in DFSDM_FLT0CR2 register). Each injected conversion in DFSDM_FLTx (x>0) is always executed according to its local configuration settings (JSCAN, JCHG, etc.). If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is triggered, all of the selected channels in the injected group (JCHG[7:0] bits in DFSDM_FLTxJCHGR register) are converted sequentially, starting with the lowest channel (channel 0, if selected). If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is triggered, only one of the selected channels in the injected group (JCHG[7:0] bits in DFSDM_FLTxJCHGR register) is converted and the channel selection is then moved to the next selected channel. Writing to the JCHG[7:0] bits when JSCAN=0 sets the channel selection to the lowest selected injected channel. Only one injected conversion can be ongoing at a given time. Thus, any request to launch an injected conversion is ignored if another request for an injected conversion has already been issued but not yet completed. Regular conversions can be launched using the following methods: • Software: by writing ‘1’ to RSWSTART in the DFSDM_FLTxCR1 register. • Synchronous with DFSDM_FLT0 if RSYNC=1: for DFSDM_FLTx (x>0), a regular conversion is automatically launched when in DFSDM_FLT0; a regular conversion is started by software (RSWSTART=1 in DFSDM_FLT0CR2 register). Each regular conversion in DFSDM_FLTx (x>0) is always executed according to its local configuration settings (RCONT, RCH, etc.). Only one regular conversion can be pending or ongoing at a given time. Thus, any request to launch a regular conversion is ignored if another request for a regular conversion has already been issued but not yet completed. A regular conversion can be pending if it was interrupted by an injected conversion or if it was started while an injected conversion was in progress. This pending regular conversion is then delayed and is performed when all injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit in DFSDM_FLTxRDATAR register. 30.4.16 Continuous and fast continuous modes Setting RCONT in the DFSDM_FLTxCR1 register causes regular conversions to execute in continuous mode. RCONT=1 means that the channel selected by RCH[2:0] is converted repeatedly after ‘1’ is written to RSWSTART. DocID029587 Rev 3 1077/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 The regular conversions executing in continuous mode can be stopped by writing ‘0’ to RCONT. After clearing RCONT, the on-going conversion is stopped immediately. In continuous mode, the data rate can be increased by setting the FAST bit in the DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh data if converting continuously from one channel because data inside the filter is valid from previously sampled continuous data. The speed increase depends on the chosen filter order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is finished in shorter intervals. Conversion time in continuous mode: if FAST = 0 (or first conversion if FAST=1): for Sincx filters: t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN for FastSinc filter: t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN if FAST = 1 (except first conversion): for Sincx and FastSinc filters: t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN in case FOSR = FOSR[9:0]+1 = 1 (filter bypassed, only integrator active): t = IOSR / fCKIN (... but CNVCNT=0) Continuous mode is not available for injected conversions. Injected conversions can be started by timer trigger to emulate the continuous mode with precise timing. If a regular continuous conversion is in progress (RCONT=1) and if a write access to DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is performed, then regular continuous conversion is restarted from the next conversion cycle (like new regular continuous conversion is applied for new channel selection - even if there is no change in DFSDM_FLTxCR1 register). 30.4.17 Request precedence An injected conversion has a higher precedence than a regular conversion. A regular conversion which is already in progress is immediately interrupted by the request of an injected conversion; this regular conversion is restarted after the injected conversion finishes. An injected conversion cannot be launched if another injected conversion is pending or already in progress: any request to launch an injected conversion (either by JSWSTART or by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register). Similarly, a regular conversion cannot be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored as long as bit RCIP is ‘1’ (in the DFSDM_FLTxISR register). However, if an injected conversion is requested while a regular conversion is already in progress, the regular conversion is immediately stopped and an injected conversion is launched. The regular conversion is then restarted and this delayed restart is signalized in bit RPEND. Injected conversions have precedence over regular conversions in that a injected conversion can temporarily interrupt a sequence of continuous regular conversions. When 1078/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) the sequence of injected conversions finishes, the continuous regular conversions start again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular conversion result). Precedence also matters when actions are initiated by the same write to DFSDM, or if multiple actions are pending at the end of another action. For example, suppose that, while an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1 writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence finishes, the precedence dictates that the regular conversion is performed next and its delayed start is signalized in RPEND bit. 30.4.18 Power optimization in run mode In order to reduce the consumption, the DFSDM filter and integrator are automatically put into idle when not used by conversions (RCIP=0, JCIP=0). 30.5 DFSDM interrupts In order to increase the CPU performance, a set of interrupts related to the CPU event occurrence has been implemented: • • • • • End of injected conversion interrupt: – enabled by JEOCIE bit in DFSDM_FLTxCR2 register – indicated in JEOCF bit in DFSDM_FLTxISR register – cleared by reading DFSDM_FLTxJDATAR register (injected data) – indication of which channel end of conversion occurred, reported in JDATACH[2:0] bits in DFSDM_FLTxJDATAR register End of regular conversion interrupt: – enabled by REOCIE bit in DFSDM_FLTxCR2 register – indicated in REOCF bit in DFSDM_FLTxISR register – cleared by reading DFSDM_FLTxRDATAR register (regular data) – indication of which channel end of conversion occurred, reported in RDATACH[2:0] bits in DFSDM_FLTxRDATAR register Data overrun interrupt for injected conversions: – occurred when injected converted data were not read from DFSDM_FLTxJDATAR register (by CPU or DMA) and were overwritten by a new injected conversion – enabled by JOVRIE bit in DFSDM_FLTxCR2 register – indicated in JOVRF bit in DFSDM_FLTxISR register – cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register Data overrun interrupt for regular conversions: – occurred when regular converted data were not read from DFSDM_FLTxRDATAR register (by CPU or DMA) and were overwritten by a new regular conversion – enabled by ROVRIE bit in DFSDM_FLTxCR2 register – indicated in ROVRF bit in DFSDM_FLTxISR register – cleared by writing ‘1’ into CLRROVRF bit in DFSDM_FLTxICR register Analog watchdog interrupt: DocID029587 Rev 3 1079/3178 1108 Digital filter for sigma delta modulators (DFSDM) • • RM0433 – occurred when converted data (output data or data from analog watchdog filter according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR registers – enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels AWDCH[7:0]) – indicated in AWDF bit in DFSDM_FLTxISR register – separate indication of high or low analog watchdog threshold error by AWHTF[7:0] and AWLTF[7:0] fields in DFSDM_FLTxAWSR register – cleared by writing ‘1’ into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits in DFSDM_FLTxAWCFR register Short-circuit detector interrupt: – occurred when the number of stable data crosses over thresholds in DFSDM_CHyAWSCDR register – enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by SCDEN bi tin DFSDM_CHyCFGR1 register) – indicated in SCDF[7:0] bits in DFSDM_FLTxISR register (which also reports the channel on which the short-circuit detector event occurred) – cleared by writing ‘1’ into the corresponding CLRSCDF[7:0] bit in DFSDM_FLTxICR register Channel clock absence interrupt: – occurred when there is clock absence on CKINy pin (see Clock absence detection in Section 30.4.4: Serial channel transceivers) – enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by CKABEN bit in DFSDM_CHyCFGR1 register) – indicated in CKABF[y] bit in DFSDM_FLTxISR register – cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDM_FLTxICR register Table 236. DFSDM interrupt requests Interrupt event 1080/3178 Event flag Event/Interrupt clearing method Interrupt enable control bit End of injected conversion JEOCF reading DFSDM_FLTxJDATAR End of regular conversion REOCF reading DFSDM_FLTxRDATAR REOCIE Injected data overrun JOVRF writing CLRJOVRF = 1 JOVRIE Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE Analog watchdog AWDF, AWHTF[7:0], AWLTF[7:0] writing CLRAWHTF[7:0] = 1 writing CLRAWLTF[7:0] = 1 AWDIE, (AWDCH[7:0]) short-circuit detector SCDF[7:0] writing CLRSCDF[7:0] = 1 SCDIE, (SCDEN) Channel clock absence CKABF[7:0] writing CLRCKABF[7:0] = 1 CKABIE, (CKABEN) DocID029587 Rev 3 JEOCIE RM0433 Digital filter for sigma delta modulators (DFSDM) 30.6 DFSDM DMA transfer To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in DFSDM_FLTxCR1 register. Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register. 30.7 DFSDM channel y registers (y=0..7) 30.7.1 DFSDM channel configuration y register (DFSDM_CHyCFGR1) (y=0..7) This register specifies the parameters used by channel y (y = 0..7). Address offset: 0x00 + 0x20 * y Reset value: 0x0000 0000 31 30 DFSDM CKOUT EN SRC rw rw 15 14 DATPACK[1:0] rw rw 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. rw rw rw rw 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. CHIN SEL CHEN CKAB EN SCDEN Res. rw rw rw rw DATMPX[1:0] rw rw 23 22 21 20 19 18 17 16 rw rw rw rw 3 2 1 0 CKOUTDIV[7:0] SPICKSEL[1:0] rw rw SITP[1:0] rw rw Bit 31 DFSDMEN: Global enable for DFSDM interface 0: DFSDM interface disabled 1: DFSDM interface enabled If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: –all registers DFSDM_FLTxISR are set to reset state (x = 0..3) –all registers DFSDM_FLTxAWSR are set to reset state (x = 0..3) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0) Bit 30 CKOUTSRC: Output serial clock source selection 0: Source for output clock is from system clock 1: Source for output clock is from audio clock This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0) Bits 29:24 Reserved, must be kept at reset value. DocID029587 Rev 3 1081/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider 0: Output clock generation is disabled (CKOUT signal is set to low state) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) Bits 15:14 DATPACK[1:0]: Data packing mode in DFSDM_CHyDATINR register. 0: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 1: Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y 0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 1: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: DATMPX[1:0] = 1 is supported only by ADC1 and ADC2. Bits 11:9 Reserved, must be kept at reset value. Bit 8 CHINSEL: Channel inputs selection 0: Channel inputs are taken from pins of the same channel y. 1: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Bit 7 CHEN: Channel y enable 0: Channel y disabled 1: Channel y enabled If channel y is enabled, then serial data receiving is started according to the given channel setting. 1082/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Bit 6 CKABEN: Clock absence detector enable on channel y 0: Clock absence detector disabled on channel y 1: Clock absence detector enabled on channel y Bit 5 SCDEN: Short-circuit detector enable on channel y 0: Input channel y will not be guarded by the short-circuit detector 1: Input channel y will be continuously guarded by the short-circuit detector Bit 4 Reserved, must be kept at reset value. Bits 3:2 SPICKSEL[1:0]: SPI clock select for channel y 0: clock coming from external CKINy input - sampling point according SITP[1:0] 1: clock coming from internal CKOUT output - sampling point according SITP[1:0] 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Bits 1:0 SITP[1:0]: Serial interface type for channel y 00: SPI with rising edge to strobe data 01: SPI with falling edge to strobe data 10: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 11: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register). 30.7.2 DFSDM channel configuration y register (DFSDM_CHyCFGR2) (y=0..7) This register specifies the parameters used by channel y (y = 0..7). Address offset: 0x04 + 0x20 * y Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OFFSET[23:8] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. OFFSET[7:0] rw rw rw rw rw DTRBS[4:0] rw rw rw rw rw DocID029587 Rev 3 rw rw rw 1083/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software. Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Bits 2:0 Reserved, must be kept at reset value. 30.7.3 DFSDM channel analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) (y=0..7) Short-circuit detector and analog watchdog settings for channel y (y = 0..7) Address offset: 0x08 + 0x20 * y Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. BKSCD[3:0] rw rw rw rw 23 22 AWFORD[1:0] rw rw 7 6 21 20 19 Res. 18 17 16 AWFOSR[4:0] 5 rw rw rw rw rw 4 3 2 1 0 rw rw rw SCDT[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y 0: FastSinc filter type 1: Sinc1 filter type 2: Sinc2 filter type 3: Sinc3 filter type x ⎛ 1 – z – FOSR⎞ Sincx filter type transfer function: -⎟ H ( z ) = ⎜ ---------------------------⎝ 1 – z –1 ⎠ 2 FastSinc filter type transfer function: ⎛ 1 – z– FOSR⎞ -⎟ ⋅ ( 1 + z –( 2 ⋅ H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠ FOSR ) ) This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Bit 21 Reserved, must be kept at reset value. Bits 20:16 AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 1084/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y Bits 11:8 Reserved, must be kept at reset value. Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. 30.7.4 DFSDM channel watchdog filter data register (DFSDM_CHyWDATR) (y=0..7) This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). Address offset: 0x0C + 0x20 * y Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r WDATA[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 WDATA[15:0]: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3). 30.7.5 DFSDM channel data input register (DFSDM_CHyDATINR) (y=0..7) This register contains 16-bit input data to be processed by DFSDM filter module. Address offset: 0x10 + 0x20 * y Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INDAT1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INDAT0[15:0] rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 1085/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bits 31:16 INDAT1[15:0]: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See Section 30.4.6: Parallel data inputs for more details. INDAT0[15:1] is in the16-bit signed format. Bits 15:0 INDAT0[15:0]: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See Section 30.4.6: Parallel data inputs for more details. INDAT0[15:0] is in the16-bit signed format. 30.8 DFSDM filter x module registers (x=0..3) 30.8.1 DFSDM control register 1 (DFSDM_FLTxCR1) Address offset: 0x100 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 Res. AWF SEL FAST Res. Res. rw rw 15 14 13 12 11 Res. JEXTEN[1:0] rw 1086/3178 rw 26 25 24 RCH[2:0] rw rw rw 10 9 8 JEXTSEL[4:0] rw rw rw 23 22 21 20 19 18 17 16 Res. Res. RDMA EN Res. RSYNC RCON T RSW START Res. rw rw r0w 7 6 5 3 2 1 0 Res. JDMA EN Res. JSW START DFEN r0w rw rw Res. rw rw DocID029587 Rev 3 rw 4 JSCAN JSYNC rw rw RM0433 Digital filter for sigma delta modulators (DFSDM) Bit 31 Reserved, must be kept at reset value. Bit 30 AWFSEL: Analog watchdog fast mode select 0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 1: Analog watchdog on channel transceivers value (after watchdog filter) Bit 29 FAST: Fast conversion mode selection for regular conversions 0: Fast conversion mode disabled 1: Fast conversion mode enabled When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input. Bits 28:27 Reserved, must be kept at reset value. Bits 26:24 RCH[2:0]: Regular channel selection 0: Channel 0 is selected as the regular channel 1: Channel 1 is selected as the regular channel ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion). Bits 23:22 Reserved, must be kept at reset value. Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion 0: The DMA channel is not enabled to read regular data 1: The DMA channel is enabled to read regular data This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Bit 20 Reserved, must be kept at reset value. Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM_FLT0 0: Do not launch a regular conversion synchronously with DFSDM_FLT0 1: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Bit 18 RCONT: Continuous mode selection for regular conversions 0: The regular channel is converted just once for each conversion request 1: The regular channel is converted repeatedly after each conversion request Writing ‘0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately. DocID029587 Rev 3 1087/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bit 17 RSWSTART: Software start of a conversion on the regular channel 0: Writing ‘0’ has no effect 1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1. This bit is always read as ‘0’. Bits 16:15 Reserved, must be kept at reset value. Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions 00: Trigger detection is disabled 01: Each rising edge on the selected trigger makes a request to launch an injected conversion 10: Each falling edge on the selected trigger makes a request to launch an injected conversion 11: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Bits 12:8 JEXTSEL[4:0]: Trigger signal selection for launching injected conversions 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger). This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLT0 DFSDM_FLT1 0x00 dfsdm_jtrg0 dfsdm_jtrg0 0x01 dfsdm_jtrg1 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 dfsdm_jtrg30 0x1F dfsdm_jtrg31 dfsdm_jtrg31 Refer to Table 232: DFSDM triggers connection. DFSDM_FLT2 dfsdm_jtrg0 dfsdm_jtrg1 DFSDM_FLT3 dfsdm_jtrg0 dfsdm_jtrg1 dfsdm_jtrg30 dfsdm_jtrg31 dfsdm_jtrg30 dfsdm_jtrg31 Bits 7:6 Reserved, must be kept at reset value. Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group 0: The DMA channel is not enabled to read injected data 1: The DMA channel is enabled to read injected data This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Bit 4 JSCAN: Scanning conversion mode for injected conversions 0: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 1: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel. Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger 0: Do not launch an injected conversion synchronously with DFSDM_FLT0 1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). 1088/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Bit 2 Reserved, must be kept at reset value. Bit 1 JSWSTART: Start a conversion of the injected group of channels 0: Writing ‘0’ has no effect. 1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1. This bit is always read as ‘0’. Bit 0 DFEN: DFSDM_FLTx enable 0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. 1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. Data which are cleared by setting DFEN=0: –register DFSDM_FLTxISR is set to the reset state –register DFSDM_FLTxAWSR is set to the reset state 30.8.2 DFSDM control register 2 (DFSDM_FLTxCR2) Address offset: 0x104 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 EXCH[7:0] rw rw rw rw rw rw rw rw 23 22 21 20 19 18 17 16 rw AWDCH[7:0] rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. CKAB IE ROVR IE JOVRI E REOC IE JEOCI E rw rw rw rw rw SCDIE AWDIE rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 AWDCH[7:0]: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y Bits 15:8 EXCH[7:0]: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y Bit 7 Reserved, must be kept at reset value. Bit 6 CKABIE: Clock absence interrupt enable 0: Detection of channel input clock absence interrupt is disabled 1: Detection of channel input clock absence interrupt is enabled Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0) DocID029587 Rev 3 1089/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bit 5 SCDIE: Short-circuit detector interrupt enable 0: short-circuit detector interrupt is disabled 1: short-circuit detector interrupt is enabled Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0) Bit 4 AWDIE: Analog watchdog interrupt enable 0: Analog watchdog interrupt is disabled 1: Analog watchdog interrupt is enabled Please see the explanation of AWDF in DFSDM_FLTxISR. Bit 3 ROVRIE: Regular data overrun interrupt enable 0: Regular data overrun interrupt is disabled 1: Regular data overrun interrupt is enabled Please see the explanation of ROVRF in DFSDM_FLTxISR. Bit 2 JOVRIE: Injected data overrun interrupt enable 0: Injected data overrun interrupt is disabled 1: Injected data overrun interrupt is enabled Please see the explanation of JOVRF in DFSDM_FLTxISR. Bit 1 REOCIE: Regular end of conversion interrupt enable 0: Regular end of conversion interrupt is disabled 1: Regular end of conversion interrupt is enabled Please see the explanation of REOCF in DFSDM_FLTxISR. Bit 0 JEOCIE: Injected end of conversion interrupt enable 0: Injected end of conversion interrupt is disabled 1: Injected end of conversion interrupt is enabled Please see the explanation of JEOCF in DFSDM_FLTxISR. 30.8.3 DFSDM interrupt and status register (DFSDM_FLTxISR) Address offset: 0x108 + 0x80 * x, x = 0..3 Reset value: 0x00FF 0000 31 30 29 28 27 26 25 24 23 22 21 SCDF[7:0] 20 19 18 17 16 CKABF[7:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RCIP JCIP Res. Res. Res. Res. Res. Res. Res. Res. r r 1090/3178 AWDF ROVRF JOVRF REOCF JEOCF r DocID029587 Rev 3 r r r r RM0433 Digital filter for sigma delta modulators (DFSDM) Bits 31:24 SCDF[7:0]: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0) Bits 23:16 CKABF[7:0]: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0) Bit 15 Reserved, must be kept at reset value. Bit 14 RCIP: Regular conversion in progress status 0: No request to convert the regular channel has been issued 1: The conversion of the regular channel is in progress or a request for a regular conversion is pending A request to start a regular conversion is ignored when RCIP=1. Bit 13 JCIP: Injected conversion in progress status 0: No request to convert the injected channel group (neither by software nor by trigger) has been issued 1: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection A request to start an injected conversion is ignored when JCIP=1. Bits 12:5 Reserved, must be kept at reset value. Bit 4 AWDF: Analog watchdog 0: No Analog watchdog event occurred 1: The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing ‘1’ into the clear bits in DFSDM_FLTxAWCFR register). Bit 3 ROVRF: Regular conversion overrun flag 0: No regular conversion overrun has occurred 1: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register. DocID029587 Rev 3 1091/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bit 2 JOVRF: Injected conversion overrun flag 0: No injected conversion overrun has occurred 1: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register. Bit 1 REOCF: End of regular conversion flag 0: No regular conversion has completed 1: A regular conversion has completed and its data may be read This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR. Bit 0 JEOCF: End of injected conversion flag 0: No injected conversion has completed 1: An injected conversion has completed and its data may be read This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR. Note: For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in DFSDM_FLTxCR2. If an interrupt is called, the flag must be cleared before exiting the interrupt service routine. All the bits of DFSDM_FLTxISR are automatically reset when DFEN=0. 30.8.4 DFSDM interrupt flag clear register (DFSDM_FLTxICR) Address offset: 0x10C + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 CLRSCDF[7:0] 20 19 18 17 16 CLRCKABF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. CLRR OVRF CLR J OVRF Res. Res. rc_w1 rc_w1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 CLRSCDF[7:0]: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing ‘0’ has no effect CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0) Bits 23:16 CLRCKABF[7:0]: Clear the clock absence flag CLRCKABF[y]=0: Writing ‘0’ has no effect CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0) Bits 15:4 Reserved, must be kept at reset value. 1092/3178 DocID029587 Rev 3 RM0433 Digital filter for sigma delta modulators (DFSDM) Bit 3 CLRROVRF: Clear the regular conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register Bit 2 CLRJOVRF: Clear the injected conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register Bits 1:0 Reserved, must be kept at reset value. Note: The bits of DFSDM_FLTxICR are always read as ‘0’. 30.8.5 DFSDM injected channel group selection register (DFSDM_FLTxJCHGR) Address offset: 0x110 + 0x80 * x, x = 0..3 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw JCHG[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 JCHG[7:0]: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored. 30.8.6 DFSDM filter control register (DFSDM_FLTxFCR) Address offset: 0x114 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 FORD[2:0] 28 27 26 Res. Res. Res. rw rw rw 15 14 13 12 11 Res. Res. Res. Res. Res. 25 24 23 22 21 20 19 18 17 16 FOSR[9:0] rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. rw rw rw IOSR[7:0] rw rw DocID029587 Rev 3 rw rw rw 1093/3178 1108 Digital filter for sigma delta modulators (DFSDM) Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc1 filter type 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: RM0433 ⎛ 1 – z –FOSR⎞ -⎟ H ( z ) = ⎜ ---------------------------⎝ 1 – z –1 ⎠ x 2 ⎛ 1 – z– FOSR⎞ -⎟ ⋅ ( 1 + z – ( 2 ⋅ H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠ FastSinc filter type transfer function: FOSR ) ) This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1). Bits 28:26 Reserved, must be kept at reset value. Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate) 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length) 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 30.8.7 DFSDM data register for injected group (DFSDM_FLTxJDATAR) Address offset: 0x118 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 JDATA[23:8] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. JDATA[7:0] r r 1094/3178 r r r r r r DocID029587 Rev 3 JDATACH[2:0] r r r RM0433 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 JDATACH[2:0]: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]. Note: DMA may be used to read the data from this register. Half-word accesses may be used to read only the MSBs of conversion data. Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not read this register if DMA is activated to read data from this register. 30.8.8 DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) Address offset: 0x11C + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Res. Res. Res. RPEND Res. RDATA[23:8] 15 14 13 12 11 10 9 8 RDATA[7:0] r r r r r r r r r RDATACH[2:0] r r r Bits 31:8 RDATA[23:0]: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF. Bits 7:5 Reserved, must be kept at reset value. Bit 4 RPEND: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion Bit 3 Reserved, must be kept at reset value. Bits 2:0 RDATACH[2:0]: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]. Note: Half-word accesses may be used to read only the MSBs of conversion data. Reading this register also clears REOCF in DFSDM_FLTxISR. DocID029587 Rev 3 1095/3178 1108 Digital filter for sigma delta modulators (DFSDM) 30.8.9 RM0433 DFSDM analog watchdog high threshold register (DFSDM_FLTxAWHTR) Address offset: 0x120 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AWHT[23:8] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. AWHT[7:0] rw rw rw rw rw rw rw rw BKAWH[3:0] rw rw rw rw Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event 30.8.10 DFSDM analog watchdog low threshold register (DFSDM_FLTxAWLTR) Address offset: 0x124 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AWLT[23:8] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. AWLT[7:0] rw rw 1096/3178 rw rw rw rw rw rw DocID029587 Rev 3 BKAWL[3:0] rw rw rw rw RM0433 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event 30.8.11 DFSDM analog watchdog status register (DFSDM_FLTxAWSR) Address offset: 0x128 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r AWHTF[7:0] r r r r r AWLTF[7:0] r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 AWHTF[7:0]: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register. Bits 7:0 AWLTF[7:0]: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register. Note: All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0. 30.8.12 DFSDM analog watchdog clear flag register (DFSDM_FLTxAWCFR) Address offset: 0x12C + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rc_w1 rc_w1 rc_w1 CLRAWHTF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 CLRAWLTF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 DocID029587 Rev 3 rc_w1 rc_w1 rc_w1 1097/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing ‘0’ has no effect CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing ‘0’ has no effect CLRAWLTF[y]=1: Writing ‘1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register 30.8.13 DFSDM Extremes detector maximum register (DFSDM_FLTxEXMAX) Address offset: 0x130 + 0x80 * x, x = 0..3 Reset value: 0x8000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXMAX[23:8] r1 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. EXMAX[7:0] r0 r0 r0 r0 r0 r0 r0 r0 EXMAXCH[2:0] r r r Bits 31:8 EXMAX[23:0]: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 EXMAXCH[2:0]: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register. 30.8.14 DFSDM Extremes detector minimum register (DFSDM_FLTxEXMIN) Address offset: 0x134 + 0x80 * x, x = 0..3 Reset value: 0x7FFF FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXMIN[23:8] r0 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. EXMIN[7:0] r1 r1 1098/3178 r1 r1 r1 r1 r1 r1 DocID029587 Rev 3 EXMINCH[2:0] r r r RM0433 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 EXMIN[23:0]: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 EXMINCH[2:0]: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register. 30.8.15 DFSDM conversion timer register (DFSDM_FLTxCNVTIMR) Address offset: 0x138 + 0x80 * x, x = 0..3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNVCNT[27:12] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. CNVCNT[11:0] r r r r r r r r r r r r Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time. Bits 3:0 Reserved, must be kept at reset value. DocID029587 Rev 3 1099/3178 1108 Digital filter for sigma delta modulators (DFSDM) 30.8.16 RM0433 DFSDM register map The following table summarizes the DFSDM registers. 0 0 0 0 0 0 0 Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 Res. 0 0 0 0 0 BKSCD[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. INDAT0[15:0] Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 WDATA[15:0] Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Reserved 0 SCDT[7:0] Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 Res. AWFOSR[4:0] 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 DTRBS[4:0] Res. Res. Res. 0 0 SITP[1:0] Res. Res. SPICKSEL [1:0] Res. Res. 0 Res. Res. Res. CHINSEL Res. Res. Res. SCDEN Res. Res. Res. Res. Res. 0 Res. Res. 0 CHEN Res. DATMPX[1:0] 0 CKABEN Res. Res. Res. DATPACK[1:0] Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. 0 0 0 INDAT1[15:0] reset value 0 0 0 DFSDM_ CH1DATINR 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. Res. 0 0 0 Res. DFSDM_ CH1AWSCDR 0 Res. 0 Res. 0 AWFORD[1:0] 0 Res. 0 0 0 Res. 0 0 0 Res. 0 Res. 0 0 0 Res. 0 0 0 OFFSET[23:0] reset value 0 SCDT[7:0] WDATA[15:0] 0 DFSDM_ CH1CFGR2 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 0 INDAT0[15:0] DFSDM_ CH1CFGR1 1100/3178 0 INDAT1[15:0] Reserved 0x34 0x3C 0 0 DFSDM_ CH0DATINR DFSDM_ CH1WDATR 0 0 Res. 0 BKSCD[3:0] SITP[1:0] Res. 0 SPICKSEL [1:0] Res. Res. Res. DATMPX[1:0] 0 Res. 0 Res. Res. AWFOSR[4:0] Res. 0 Res. AWFORD [1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM_ CH0WDATR Res. Res. Res. Res. Res. Res. DFSDM_ CH0AWSCDR reset value 0x30 0 0 reset value 0x2C 0 0 reset value 0x28 0 reset value reset value 0x24 0 DTRBS[4:0] 0x14 0x1C 0x20 0 OFFSET[23:0] reset value 0x10 0 Res. 0 SCDEN 0 CHEN 0 CKABEN 0 CHINSEL 0 reset value 0x0C DATPACK[1:0] Res. Res. Res. Res. 0 Res. DFSDMEN CKOUTSRC 0 CKOUTDIV[7:0] DFSDM_ CH0CFGR2 Res. 0x08 reset value Res. 0x04 DFSDM_ CH0CFGR1 Res. 0x00 Res. Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 237. DFSDM register map and reset values DocID029587 Rev 3 0 0 0 0 0 0 0 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. 0 0 Res. 0 reset value DocID029587 Rev 3 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. CHINSEL 0 0 0 0 0 0 0 BKSCD[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT1[15:0] 0 0 0 0 OFFSET[23:0] 0 0 0 Res. Res. Res. Res. Res. SCDT[7:0] WDATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS[4:0] SCDT[7:0] WDATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. DATMPX[1:0] DATPACK[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SCDEN 0 SITP[1:0] SPICKSEL[1:0] Res. CHEN CKABEN CHINSEL 0 0 0 Res. Res. DTRBS[4:0] Res. 0 0 0 SITP[1:0] 0 0 SPICKSEL[1:0] Res. Res. Res. 0 0 0 0 Res. 0 Res. INDAT1[15:0] 0 Res. 0 Res. 0 SCDEN 0 Res. 0 Res. 0 0 CHEN 0 0 CKABEN Res. 0 0 Res. 0 Res. Res. Res. OFFSET[23:0] Res. 0 Res. Res. Res. BKSCD[3:0] 0 SITP[1:0] 0 0 0 SPICKSEL[1:0] 0 0 Res. 0 0 Res. 0 0 Res. AWFOSR[4:0] 0 0 Res. 0 Res. 0 Res. reset value 0 DATMPX[1:0] 0 DATPACK[1:0] 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 0 SCDEN 0 0 Res. Res. Res. 0 Res. Res. AWFORD[1:0] Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DFSDM_ CH2CFGR1 Res. Register name 0 Res. 0 0 Res. 0 0 Res. Res. Res. Res. 0 Res. reset value 0 Res. Res. Res. Res. Res. AWFOSR[4:0] 0 0 Res. 0 0 0 0 CHEN 0 0 0 0 CKABEN 0 Res. Res. Res. Res. Res. 0 DATMPX[1:0] 0 Res. Res. Res. Res. reset value DATPACK[1:0] 0 0 0 0 Res. Res. Res. reset value 0 0 0 CHINSEL Res. Res. DFSDM_ CH3AWSCDR 0 Res. DFSDM_ CH3CFGR2 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. Res. Res. 0 0 0 0 Res. Res. Res. DFSDM_ CH3DATINR 0 Res. reset value 0 Res. Res. Res. DFSDM_ CH2AWSCDR 0 Res. Res. Res. 0 0 Res. 0 AWFORD[1:0] Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 0 Res. 0 Res. Res. Res. DFSDM_ CH2DATINR Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 Res. 0 Res. 0 Res. reset value Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. reset value Res. reset value Res. Res. DFSDM_ CH4CFGR1 Res. DFSDM_ CH3WDATR 0 Res. Res. reset value Res. Res. DFSDM_ CH3CFGR1 Res. DFSDM_ CH2CFGR2 Res. Res. 0x80 Reserved Res. 0x74 0x7C Res. 0x70 Res. 0x6C Res. 0x68 Res. 0x64 Reserved Res. 0x60 Res. 0x54 0x5C Res. 0x50 DFSDM_ CH2WDATR Res. 0x4C Res. 0x48 Res. 0x44 Res. 0x40 Res. Offset Res. RM0433 Digital filter for sigma delta modulators (DFSDM) Table 237. DFSDM register map and reset values (continued) 0 INDAT0[15:0] 0 INDAT0[15:0] 0 0 0 1101/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 AWFOSR[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHINSEL CHEN CKABEN SCDEN Res. 0 0 0 0 0 0 0 0 BKSCD[3:0] Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP[1:0] 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHINSEL CHEN CKABEN SCDEN Res. 0 0 0 0 0 0 0 0 DTRBS[4:0] 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP[1:0] 0 0 0 Res. DATMPX[1:0] Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 OFFSET[23:0] 0 0 SCDT[7:0] WDATA[15:0] 0 0 0 0 0 DFSDM_ CH6CFGR1 0 0 0 0 Reserved DFSDM_ CH6CFGR2 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 INDAT0[15:0] Res. 0 0 0 Res. 0 0 Res. AWFOSR[4:0] 0 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 Res. Res. 0 0 Res. 0 Res. 0 DTRBS[4:0] Res. 0 Res. Res. Res. 0 SPICKSEL[1:0] Res. Res. Res. Res. Res. Res. Res. DATMPX[1:0] Res. Res. Res. Res. Res. DATPACK[1:0] Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 INDAT1[15:0] 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. 0 DFSDM_ CH5DATINR 1102/3178 0 0 Res. Res. 0 0 0 Res. DFSDM_ CH5AWSCDR 0 Res. 0 0 0 Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 AWFORD[1:0] 0 0 0 Res. 0 reset value 0 0 Res. 0 0 SCDT[7:0] OFFSET[23:0] reset value 0 0 0 reset value 0xC4 0 0 0 Res. 0xC0 0 0 WDATA[15:0] 0 DFSDM_ CH5CFGR2 reset value 0 0 0 DFSDM_ CH5CFGR1 0xB4 0xBC BKSCD[3:0] 0 0 reset value 0xB0 0 0 Reserved DFSDM_ CH5WDATR 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 reset value 0xAC 0 INDAT0[15:0] Res. 0 Res. 0xA8 0 0 0 INDAT1[15:0] reset value 0xA4 0 0 Res. 0xA0 0 DATPACK[1:0] reset value 0x94 0x9C 0 Res. 0x90 Res. 0 reset value DFSDM_ CH4DATINR Res. 0 SPICKSEL[1:0] Res. 0 Res. Res. Res. 0 0 Res. Res. Res. 0 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0x8C DFSDM_ CH4WDATR Res. reset value 0 Res. DFSDM_ CH4AWSCDR 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 DTRBS[4:0] Res. 0 AWFORD[1:0] 0 Res. 0 Res. reset value Res. OFFSET[23:0] Res. 0x88 DFSDM_ CH4CFGR2 Res. 0x84 Res. Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 237. DFSDM register map and reset values (continued) 0x108 reset value 0 DFSDM_ FLT0ISR 0 0 0 0 0 0 reset value 0 0 1 0 SCDF[7:0] 1 0 1 0 1 0 1 0 1 CKABF[7:0] 0 0 1 1 DocID029587 Rev 3 AWDCH[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 JEXTSEL[4:0] 0 EXCH[7:0] 0 0 0 0 0 0 0 0 0 0 0 SCDT[7:0] WDATA[15:0] 0 Res. Res. Res. Res. Res. Res. Res. CKABEN SCDEN Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 0 Res. Res. CHEN 0 0 DFEN DTRBS[4:0] Res. 0 Res. SITP[1:0] SPICKSEL[1:0] 0 Res. 0 CHINSEL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 JSW START Res. 0 0 JEOCIE 0 0 Res. INDAT1[15:0] 0 0 0 0 0 0 0 0 JEOCF 0 0 REOCIE 0 0 REOCF 0 0 JOVRIE 0 0 0 Res. 0 0 JOVRF 0 0 JSYNC 0 0 ROVRIE 0 ROVRF BKSCD[3:0] 0 Res. 0 JSCAN OFFSET[23:0] AWDIE 0 0 0 AWDF 0 0 0 Res. 0 DATMPX[1:0] INDAT1[15:0] 0 Res. reset value 0 0 0 Res. 0 0 Res. 0 DATPACK[1:0] 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 0 JDMAEN 0 0 Res. AWFOSR[4:0] 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 0 SCDIE 0 Res. 0 0 0 CKABIE 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. reset value 0 Res. Res. Res. 0 0 Res. 0 0 0 Res. 0 0 0 0 Res. 0 Res. 0 0 Res. AWFORD[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKSCD[3:0] Res. 0 Res. Res. Res. Res. reset value Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 0 Res. 0 0 0 0 JEXTEN[1:0] reset value 0 Res. DFSDM_ CH7AWSCDR 0 0 Res. 0 Res. DFSDM_ CH7CFGR2 0 Res. 0 0 Res. 0 0 Res. 0 AWFORD[1:0] 0 Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 RSYNC DFSDM_ CH7DATINR Res. Res. Res. Res. Res. Res. DFSDM_ CH7CFGR1 Res. 0 RCONT 0 Res. Res. Res. 0 Res. 0 Res. Res. RDMAEN 0 Res. 0 Res. Res. Res. 0 0 Res. Res. Res. 0 0 Res. Res. RCH[2:0] 0 RSW START Res. Res. 0 0 Res. 0 Res. 0 0 Res. Res. DFSDM_ FLT0CR2 Res. reset value Res. DFSDM_ FLT0CR1 Res. Reserved Res. 0 FAST reset value 0 0 JCIP 0x104 DFSDM_ CH6DATINR 0 RCIP 0x100 Reserved Res. reset value AWFOSR[4:0] Res. 0xF4 0xFC 0 Res. 0xF0 DFSDM_ CH7WDATR Res. 0xEC 0 Res. 0xE8 reset value Res. 0xE4 0 Res. 0xE0 Res. reset value Res. 0xD4 0xDC Res. 0xD0 DFSDM_ CH6WDATR Res. 0xCC DFSDM_ CH6AWSCDR AWFSEL 0xC8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. RM0433 Digital filter for sigma delta modulators (DFSDM) Table 237. DFSDM register map and reset values (continued) SCDT[7:0] WDATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0[15:0] 0 INDAT0[15:0] 0 0 0 0 0 0 0 1103/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM_ FLT0AWSR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Res. 0 0 0 0 0 0 CLRAWHTF[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Reserved 0 Res. 0 DocID029587 Rev 3 0 0 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 BKAWL[3:0] 0 Res. 0 0 0 0 0 0 0 0 CLRAWLTF[7:0] Res. 0 RDATA CH[2:0] AWLTF[7:0] Res. 0 0 BKAWH[3:0] 0 Res. 0 0 0 0 Res. 0 Res. Res. 0 CNVCNT[27:0] reset value Res. Res. Res. 0 AWHTF[7:0] 0 Res. Res. 0 EXMIN[23:0] DFSDM_ FLT0CNVTIMR 0 Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 EXMAX[23:0] DFSDM_ FLT0EXMIN 1104/3178 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM_ FLT0EXMAX 0x13C 0x17C 0 0 Res. 0x138 0 AWLT[23:0] 0 reset value 0 Res. 0x134 0 Res. 0 reset value reset value 0 AWHT[23:0] reset value 0x130 0 Res. 0 reset value 0x12C 0 RDATA[23:0] DFSDM_ FLT0AWLTR DFSDM_ FLT0AWCFR 0 Res. 0 Res. Res. 0 0 0 0 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 CLR JOVRF Res. 0 0 JDATACH [2:0] Res. 0 0 EXMAXCH[2:0] Res. 0 0 EXMINCH[2:0] Res. 0 JDATA[23:0] 0 IOSR[7:0] Res. Res. 0 1 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 CLR ROVRF Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. Res. Res. 0 0 Res. Res. 0 Res. 0x128 0 DFSDM_ FLT0AWHTR reset value 0x124 0 DFSDM_ FLT0RDATAR reset value 0x120 0 DFSDM_ FLT0JDATAR reset value 0x11C 0 FOSR[9:0] 0 RPEND Res. reset value Res. DFSDM_ FLT0FCR 0x114 0x118 0 FORD[2:0] reset value 0 JCHG[7:0] Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 DFSDM_ FLT0JCHGR Res. Res. reset value Res. CLRCKABF[7:0] Res. 0x110 CLRSCDF[7:0] Res. DFSDM_ FLT0ICR 0x10C Res. Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 237. DFSDM register map and reset values (continued) RM0433 Digital filter for sigma delta modulators (DFSDM) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM_ FLT1AWSR 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 RDATA CH[2:0] 0 0 0 BKAWH[3:0] 0 0 0 0 BKAWL[3:0] 0 0 0 0 0 0 0 0 AWLTF[7:0] 0 0 0 0 CLRAWHTF[7:0] 0 DocID029587 Rev 3 0 0 0 AWHTF[7:0] 0 Res. Res. 0 AWLT[23:0] Res. Res. Res. Res. Res. Res. Res. 0 AWHT[23:0] reset value 0x1AC 0 RDATA[23:0] DFSDM_ FLT1AWLTR DFSDM_ FLT1AWCFR 0 Res. 0 Res. 0 RPEND 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 JDATA[23:0] 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. Res. Res. 0 Res. 0x1A8 0 DFSDM_ FLT1AWHTR reset value 0x1A4 0 DFSDM_ FLT1RDATAR reset value 0x1A0 0 DFSDM_ FLT1JDATAR reset value 0x19C 0 0 IOSR[7:0] Res. 0x198 0 FOSR[9:0] Res. reset value Res. DFSDM_ FLT1FCR Res. 0x194 0 FORD[2:0] reset value DFEN JEOCIE JEOCF 0 Res. 0 JCHG[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x190 Res. 0 reset value DFSDM_ FLT1JCHGR JSW START JSYNC REOCIE JSCAN Res. JDMAEN Res. Res. REOCF Res. 0 Res. Res. 0 JDATACH[2:0] Res. JOVRIE Res. 0 JOVRF Res. 0 CLR JOVRF Res. AWDIE Res. Res. Res. 0 ROVRIE Res. Res. Res. Res. Res. Res. Res. 0 0 AWDF 0 0 ROVRF 0 0 Res. 0 0 CLR ROVRF 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 JCIP 0 Res. 0 RCIP 0 Res. 0 Res. EXCH[7:0] Res. 0 Res. 0 Res. 0 Res. 0 Res. AWDCH[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM_ FLT1ICR 0 Res. 0 reset value 0x18C JEXTEN[1:0] 0 Res. 0 Res. RCONT RSW START Res. RSYNC Res. RDMAEN Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. DFSDM_ FLT1ISR Res. 0x188 Res. reset value 0 Res. 0 Res. 0 JEXTSEL[4:0] Res. 0 Res. Res. RCH[2:0] Res. Res. 0 Res. FAST DFSDM_ FLT1CR2 0 Res. 0x184 Res. reset value Res. Res. DFSDM_ FLT1CR1 AWFSEL 0x180 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 237. DFSDM register map and reset values (continued) 0 0 0 0 CLRAWLTF[7:0] 0 0 0 0 0 0 0 0 1105/3178 1108 0x218 reset value reset value 1106/3178 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM_ FLT2JDATAR 0 0 0 0 0 0 0 0 JDATA[23:0] 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 Res. Res. Res. 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. reset value 0 0 reset value 0 0 0 0 0 0 0 0 Res. Res. Res. Res. DFEN 0 JSW START 0 JEOCIE - 0 REOCIE JEOCF - REOCF Res. Res. Res. 0 JOVRIE 0 JOVRF 0 0 0 0 0 0 CLR JOVRF Res. 0 ROVRF Res. 0 JSYNC CNVCNT[27:0] ROVRIE JEXTSEL[4:0] CLR ROVRF 1 Res. 1 JSCAN 1 AWDIE 1 AWDF 1 Res. 1 Res. 1 JDMAEN 1 EXMINCH[2:0] Res. Res. Res. Res. 1 Res. Res. 1 Res. 0 0 0 JCHG[7:0] 0 IOSR[7:0] Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. EXCH[7:0] Res. 0 JEXTEN[1:0] 0 Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 JDATACH[2:0] Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. Res. 0 0 0 Res. 0 0 Res. 0 JCIP 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 RCIP 0 RSW START Res. EXMIN[23:0] 0 Res. FOSR[9:0] 0 Res. 0 Res. AWDCH[7:0] Res. 0 Res. reset value 0 Res. 0 Res. 0 Res. DFSDM_ FLT2ISR 0 Res. 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 1 Res. 0 0 Res. 0 Res. 0 RCONT 0 Res. 0 RSYNC 1 Res. Res. 0 Res. DFSDM_ FLT1CNVTIMR 0 Res. 0 1 Res. 0 0 Res. 0 1 Res. 1 0 Res. Res. RDMAEN DFSDM_ FLT1EXMIN Res. 0 Res. Res. Res. 1 Res. reset value 0 Res. Res. Res. 1 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 1 Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 1 Res. Res. Res. Res. 0 Res. Res. FAST 0 Res. RCH[2:0] Res. 1 0 Res. DFSDM_ FLT2FCR Res. Res. EXMAXCH[2:0] Res. Res. Res. Res. Res. EXMAX[23:0] Res. 0x214 Res. DFSDM_ FLT1EXMAX Res. DFSDM_ FLT2JCHGR 1 Res. DFSDM_ FLT2ICR Res. DFSDM_ FLT2CR2 AWFSEL reset value 0 0 Res. 0x210 DFSDM_ FLT2CR1 1 0 Res. 0x20C Reserved 0 Res. 0x208 0 0 Res. 0x204 reset value 1 Res. 0x200 0 0 Res. 0x1BC 0x1FC Res. 0x1B8 Res. reset value 1 Res. 0x1B4 Res. reset value Res. 0x1B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset FORD[2:0] Digital filter for sigma delta modulators (DFSDM) RM0433 Table 237. DFSDM register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 RM0433 Digital filter for sigma delta modulators (DFSDM) 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 JEOCF Res. Res. 0 REOCF Res. Res. 0 0 0 0 0 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 JOVRF Res. Res. Res. Res. Res. 0 0 0 0 1 JCHG[7:0] 0 DocID029587 Rev 3 0 ROVRF Res. Res. Res. Res. Res. reset value 0 CLR JOVRF 0 0 CLR ROVRF 0 0 AWDF 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM_ FLT3JCHGR 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 reset value 0x290 0 EXMAX CH[2:0] JEOCIE Res. 0 0 0 0 REOCIE Res. 0 EXCH[7:0] 0 0 JOVRIE Res. Res. 0 0 ROVRIE Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. AWDCH[7:0] 0 0 AWDIE RSW START Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. 0 0 Res. 0 Res. 0 RCONT 0 Res. 0 RSYNC 0 Res. 0 Res. 0 Res. 0 RDMAEN 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 JEXTSEL[4:0] 0 0 0 0 0 0 0 0 0 0 0 RCH[2:0] 0 0 0 Res. 0 FAST 0 Res. Reserved 0 Res. 0 Res. RPEND Res. 0 CNVCNT[27:0] reset value 0 CLRAWLTF[7:0] EXMIN[23:0] DFSDM_ FLT2CNVTIMR 0 BKAWL[3:0] 0 Res. 0 0 AWLTF[7:0] 0 0 Res. 0 EXMAX[23:0] 1 0 Res. 0 DFSDM_ FLT2EXMIN DFSDM_ FLT3ICR 0 CLRAWHTF[7:0] reset value 0x28C 0 AWHTF[7:0] 0 DFSDM_ FLT2EXMAX DFSDM_ FLT3ISR 0 EXMINCH[2:0] 0 reset value 0x288 0 Res. 0 DFSDM_ FLT3CR2 0 Res. 0 reset value 0x284 0 Res. 0 DFSDM_ FLT3CR1 0 AWLT[23:0] Res. 0x280 0 Res. 0 DFEN 0 0 JSW START 0 Res. 0 Res. 0 Res. 0 Res. 0 0 BKAWH[3:0] Res. 0 0 Res. 0 0 Res. 0 Res. 0x23C 0x27C 0 JSYNC 0 AWFSEL 0x238 0 Res. 0 DFSDM_ FLT2AWSR reset value 0 Res. 0 Res. 0x234 0 Res. 0 reset value reset value 0 Res. 0 reset value 0x230 0 Res. 0 reset value 0x22C 0 AWHT[23:0] DFSDM_ FLT2AWLTR DFSDM_ FLT2AWCFR 0 JSCAN 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 JDMAEN 0 RDATA CH[2:0] Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0x228 0 JEXTEN[1:0] reset value 0x224 0 JCIP 0x220 0 DFSDM_ FLT2AWHTR RCIP reset value RDATA[23:0] Res. DFSDM_ FLT2RDATAR Res. 0x21C Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 237. DFSDM register map and reset values (continued) 0 0 0 0 0 1107/3178 1108 Digital filter for sigma delta modulators (DFSDM) RM0433 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM_ FLT3AWSR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM_ FLT3EXMIN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 CLRAWHTF[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Reserved 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 JDATACH[2:0] 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1108/3178 DocID029587 Rev 3 0 0 BKAWL[3:0] 0 CNVCNT[27:0] reset value 0 0 0 0 0 0 0 CLRAWLTF[7:0] EXMIN[23:0] DFSDM_ FLT3CNVTIMR 0 BKAWH[3:0] 0 Res. 0 0 AWLTF[7:0] EXMAX[23:0] 0 RDATA CH[2:0] 0 0 AWHTF[7:0] 0 1 Res. 0 AWLT[23:0] DFSDM_ FLT3EXMAX 0 Res. 0 Res. 0 AWHT[23:0] 0 Res. Res. Res. Res. Res. Res. 0 0 EXMAXCH[2:0] 0 0 0 0 EXMINCH[2:0] 0 0 0 0 Res. 0 0 0x2BC 0x3FC 0 Res. 0 Res. 0x2B8 0 Res. 0 0 reset value 0 Res. 0x2B4 0 Res. 0 reset value reset value 0 Res. 0 reset value 0x2B0 0 Res. 0 reset value 0x2AC 0 RDATA[23:0] DFSDM_ FLT3AWLTR DFSDM_ FLT3AWCFR 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 RPEND 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 JDATA[23:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 IOSR[7:0] Res. 0 Res. Res. Res. Res. 0 Res. 0x2A8 0 DFSDM_ FLT3AWHTR reset value 0x2A4 0 DFSDM_ FLT3RDATAR reset value 0x2A0 0 DFSDM_ FLT3JDATAR reset value 0x29C 0 FOSR[9:0] Res. reset value Res. DFSDM_ FLT3FCR 0x294 0x298 FORD[2:0] Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 237. DFSDM register map and reset values (continued) RM0433 Digital camera interface (DCMI) 31 Digital camera interface (DCMI) 31.1 DCMI introduction The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG). This interface is for use with black & white cameras, X24 and X5 cameras, and it is assumed that all preprocessing like resizing is performed in the camera module. 31.2 31.3 DCMI main features • 8-, 10-, 12- or 14-bit parallel interface • Embedded/external line and frame synchronization • Continuous or snapshot mode • Crop feature • Supports the following data formats: – 8/10/12/14- bit progressive video: either monochrome or raw bayer – YCbCr 4:2:2 progressive video – RGB 565 progressive video – Compressed data: JPEG DCMI clocks The digital camera interface uses two clock domains, DCMI_PIXCLK and HCLK. The signals generated with DCMI_PIXCLK are sampled on the rising edge of HCLK once they are stable. An enable signal is generated in the HCLK domain, to indicate that data coming from the camera are stable and can be sampled. The maximum DCMI_PIXCLK period must be higher than 2.5 HCLK periods. 31.4 DCMI functional overview The digital camera interface is a synchronous parallel interface that can receive high-speed data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock line (DCMI_PIXCLK). The pixel clock has a programmable polarity, so that data can be captured on either the rising or the falling edge of the pixel clock. The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a general-purpose DMA channel. The image buffer is managed by the DMA, not by the camera interface. The data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer modes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG bit (bit 3 of DCMI_CR register) must be set. DocID029587 Rev 3 1109/3178 1134 Digital camera interface (DCMI) RM0433 The data flow is synchronized either by hardware using the optional DCMI_HSYNC (horizontal synchronization) and DCMI_VSYNC (vertical synchronization) signals or by synchronization codes embedded in the data flow. 31.4.1 DCMI block diagram Figure 224 shows the DCMI block diagram. Figure 224. DCMI block diagram '&0, '0$ LQWHUIDFH ELW$+%%XV GFPLBGPD ),)2'DWD IRUPDWWHU &RQWURO6WDWXVUHJLVWHU 'DWD H[WUDFWLRQ 6\QFKURQL]HU '&0,B3,;&/. '&0,B'> @ '&0,B+6<1& '&0,B96<1& GFPLBLW GFPLBKFON 06Y9 Figure 225. Top-level block diagram GFPLBKFON ,QWHUUXSW FRQWUROOHU '&0,B'> @ GFPLBLW '&0, '&0,B3,;&/. '&0,B+6<1& '&0,B96<1& ([WHUQDO LQWHUIDFH GFPLBGPD 06Y9 1110/3178 DocID029587 Rev 3 RM0433 31.4.2 Digital camera interface (DCMI) DCMI internal signals Table 238 shows the DCMI internal signals. Table 238. DCMI internal signals 31.4.3 Name Signal type Description dcmi_dma Digital output DCMI DMA request dcmi_it Digital output DCMI interrupt request dcmi_hclk Digital input DCMI interface clock DMA interface The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA request is generated each time the camera interface receives a complete 32-bit data block in its register. 31.4.4 DCMI physical interface The interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported. The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the EDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused input pins must be connected to ground. Table 239 shows the DCMI pins. Table 239. DCMI external signals Signal name 8 bits 10 bits 12 bits 14 bits DCMI_D[0..7] DCMI_D[0..9] DCMI_D[0..11] DCMI_D[0..13] Signal type Signal description Digital inputs DCMI data DCMI_PIXCLK Digital input Pixel clock DCMI_HSYNC Digital input Horizontal synchronization / Data valid DCMI_VSYNC Digital input Vertical synchronization The data are synchronous with DCMI_PIXCLK and change on the rising/falling edge of the pixel clock depending on the polarity. The DCMI_HSYNC signal indicates the start/end of a line. The DCMI_VSYNC signal indicates the start/end of a frame DocID029587 Rev 3 1111/3178 1134 Digital camera interface (DCMI) RM0433 Figure 226. DCMI signal waveforms $#-)?0)8#,+ $#-)?$2;= $#-)?(39.# $#-)?639.# AIB 1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. 8-bit data When EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSBs at its input (DCMI_D[0:7]) and stores them as 8-bit data. The DCMI_D[13:8] inputs are ignored. In this case, to capture a 32-bit word, the camera interface takes four pixel clock cycles. The first captured data byte is placed in the LSB position in the 32-bit word and the 4th captured data byte is placed in the MSB position in the 32-bit word. Table 240 gives an example of the positioning of captured data bytes in two 32-bit words. Table 240. Positioning of captured data bytes in 32-bit words (8-bit width) Byte address 31:24 23:16 15:8 7:0 0 Dn+3[7:0] Dn+2[7:0] Dn+1[7:0] Dn[7:0] 4 Dn+7[7:0] Dn+6[7:0] Dn+5[7:0] Dn+4[7:0] 10-bit data When EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit data at its input DCMI_D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The remaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero. So, in this case, a 32-bit data word is made up every two pixel clock cycles. The first captured data are placed in the LSB position in the 32-bit word and the 2nd captured data are placed in the MSB position in the 32-bit word as shown in Table 241. Table 241. Positioning of captured data bytes in 32-bit words (10-bit width) 1112/3178 Byte address 31:26 25:16 15:10 9:0 0 0 Dn+1[9:0] 0 Dn[9:0] 4 0 Dn+3[9:0] 0 Dn+2[9:0] DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) 12-bit data When EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the 12-bit data at its input DCMI_D[0..11] and stores them as the 12 least significant bits of a 16bit word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles. The first captured data are placed in the LSB position in the 32-bit word and the 2nd captured data are placed in the MSB position in the 32-bit word as shown in Table 242. Table 242. Positioning of captured data bytes in 32-bit words (12-bit width) Byte address 31:28 27:16 15:12 11:0 0 0 Dn+1[11:0] 0 Dn[11:0] 4 0 Dn+3[11:0] 0 Dn+2[11:0] 14-bit data When EDM[1:0] in DCMI_CR are programmed to “11”, the camera interface captures the 14-bit data at its input DCMI_D[0..13] and stores them as the 14 least significant bits of a 16bit word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles. The first captured data are placed in the LSB position in the 32-bit word and the 2nd captured data are placed in the MSB position in the 32-bit word as shown in Table 243. Table 243. Positioning of captured data bytes in 32-bit words (14-bit width) 31.4.5 Byte address 31:30 29:16 15:14 13:0 0 0 Dn+1[13:0] 0 Dn[13:0] 4 0 Dn+3[13:0] 0 Dn+2[13:0] Synchronization The digital camera interface supports embedded or hardware (DCMI_HSYNC and DCMI_VSYNC) synchronization. When embedded synchronization is used, it is up to the digital camera module to make sure that the 0x00 and 0xFF values are used ONLY for synchronization (not in data). Embedded synchronization codes are supported only for the 8-bit parallel data interface width (that is, in the DCMI_CR register, the EDM[1:0] bits should be cleared to “00”). For compressed data, the DCMI supports only the hardware synchronization mode. In this case, DCMI_VSYNC is used as a start/end of the image, and DCMI_HSYNC is used as a Data Valid signal. Figure 227 shows the corresponding timing diagram. DocID029587 Rev 3 1113/3178 1134 Digital camera interface (DCMI) RM0433 Figure 227. Timing diagram 3DGGLQJGDWD DWWKHHQGRIWKH-3(*VWUHDP %HJLQQLQJRI-3(*VWUHDP 3URJUDPPDEOH -3(*SDFNHWVL]H -3(*GDWD (QGRI-3(*VWUHDP '&0,B+6<1& '&0,B96<1& 3DFNHWGLVSDWFKLQJGHSHQGVRQWKHLPDJHFRQWHQW 7KLVUHVXOWVLQDYDULDEOHEODQNLQJGXUDWLRQ -3(*SDFNHWGDWD DL E Hardware synchronization mode In hardware synchronization mode, the two synchronization signals (DCMI_HSYNC/DCMI_VSYNC) are used. Depending on the camera module/mode, data may be transmitted during horizontal/vertical synchronization periods. The DCMI_HSYNC/DCMI_VSYNC signals act like blanking signals since all the data received during DCMI_HSYNC/DCMI_VSYNC active periods are ignored. In order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized with the DCMI_VSYNC signal. When the hardware synchronization mode is selected, and capture is enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the deactivation of the DCMI_VSYNC signal (next start of frame). Transfer can then be continuous, with successive frames transferred by DMA to successive buffers or the same/circular buffer. To allow the DMA management of successive frames, a VSIF (Vertical synchronization interrupt flag) is activated at the end of each frame. Embedded data synchronization mode In this synchronization mode, the data flow is synchronized using 32-bit codes embedded in the data flow. These codes use the 0x00/0xFF values that are not used in data anymore. There are 4 types of codes, all with a 0xFF0000XY format. The embedded synchronization codes are supported only in 8-bit parallel data width capture (in the DCMI_CR register, the EDM[1:0] bits should be programmed to “00”). For other data widths, this mode generates unpredictable results and must not be used. 1114/3178 DocID029587 Rev 3 RM0433 Note: Digital camera interface (DCMI) Camera modules can have 8 such codes (in interleaved mode). For this reason, the interleaved mode is not supported by the camera interface (otherwise, every other halfframe would be discarded). • Mode 2 Four embedded codes signal the following events – Frame start (FS) – Frame end (FE) – Line start (LS) – Line end (LE) The XY values in the 0xFF0000XY format of the four codes are programmable (see Section 31.7.7: DCMI embedded synchronization code register (DCMI_ESCR)). A 0xFF value programmed as a “frame end” means that all the unused codes are interpreted as valid frame end codes. In this mode, once the camera interface has been enabled, the frame capture starts after the first occurrence of the frame end (FE) code followed by a frame start (FS) code. • Mode 1 An alternative coding is the camera mode 1. This mode is ITU656 compatible. The codes signal another set of events: – SAV (active line) - line start – EAV (active line) - line end – SAV (blanking) - end of line during interframe blanking period – EAV (blanking) - end of line during interframe blanking period This mode can be supported by programming the following codes: • FS ≤ 0xFF • FE ≤ 0xFF • LS ≤ SAV (active) • LE ≤ EAV (active) An embedded unmask code is also implemented for frame/line start and frame/line end codes. Using it, it is possible to compare only the selected unmasked bits with the programmed code. You can therefore select a bit to compare in the embedded code and detect a frame/line start or frame/line end. This means that there can be different codes for the frame/line start and frame/line end with the unmasked bit position remaining the same. Example FS = 0xA5 Unmask code for FS = 0x10 In this case the frame start code is embedded in the bit 4 of the frame start code. DocID029587 Rev 3 1115/3178 1134 Digital camera interface (DCMI) 31.4.6 RM0433 Capture modes This interface supports two types of capture: snapshot (single frame) and continuous grab. Snapshot mode (single frame) In this mode, a single frame is captured (CM = ‘1’ in the DCMI_CR register). After the CAPTURE bit is set in DCMI_CR, the interface waits for the detection of a start of frame before sampling the data. The camera interface is automatically disabled (CAPTURE bit cleared in DCMI_CR) after receiving the first complete frame. An interrupt is generated (IT_FRAME) if it is enabled. In case of an overrun, the frame is lost and the CAPTURE bit is cleared. Figure 228. Frame capture waveforms in snapshot mode '&0,B+6<1& '&0,B96<1& )UDPHFDSWXUHG )UDPH QRWFDSWXUHG DLE 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. Continuous grab mode In this mode (CM bit = ‘0’ in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR, the grabbing process starts on the next DCMI_VSYNC or embedded frame start depending on the mode. The process continues until the CAPTURE bit is cleared in DCMI_CR. Once the CAPTURE bit has been cleared, the grabbing process continues until the end of the current frame. 1116/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) Figure 229. Frame capture waveforms in continuous grab mode '&0,B+6<1& '&0,B96<1& )UDPHFDSWXUHG )UDPHFDSWXUHG DLE 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. In continuous grab mode, you can configure the FCRC bits in DCMI_CR to grab all pictures, every second picture or one out of four pictures to decrease the frame capture rate. Note: In the hardware synchronization mode (ESS = ‘0’ in DCMI_CR), the IT_VSYNC interrupt is generated (if enabled) even when CAPTURE = ‘0’ in DCMI_CR so, to reduce the frame capture rate even further, the IT_VSYNC interrupt can be used to count the number of frames between 2 captures in conjunction with the Snapshot mode. This is not allowed by embedded data synchronization mode. 31.4.7 Crop feature With the crop feature, the camera interface can select a rectangular window from the received image. The start (upper left corner) coordinates and size (horizontal dimension in number of pixel clocks and vertical dimension in number of lines) are specified using two 32bit registers (DCMI_CWSTRT and DCMI_CWSIZE). The size of the window is specified in number of pixel clocks (horizontal dimension) and in number of lines (vertical dimension). Figure 230. Coordinates and size of the window after cropping 967ELWLQ'&0,B&6757 9/,1(ELWLQ'&0,B&6,=( +2))&17ELWLQ'&0,B&6757 &$3&17ELWLQ'&0,B&6,=( -36 These registers specify the coordinates of the starting point of the capture window as a line number (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from 0), and the size of the window as a line number and a number of pixel clocks. The CAPCNT value can only be a multiple of 4 (two least significant bits are forced to 0) to allow the correct transfer of data through the DMA. DocID029587 Rev 3 1117/3178 1134 Digital camera interface (DCMI) RM0433 If the VSYNC signal goes active before the number of lines is specified in the DCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated when enabled. Figure 231. Data capture waveforms '&0,B+6<1& '&0,B96<1& +2))&17 &$3&17 'DWDQRWFDSWXUHGLQWKLVSKDVH 'DWDFDSWXUHGLQWKLVSKDVH 06 9 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. 31.4.8 JPEG format To allow JPEG image reception, it is necessary to set the JPEG bit in the DCMI_CR register. JPEG images are not stored as lines and frames, so the DCMI_VSYNC signal is used to start the capture while DCMI_HSYNC serves as a data enable signal. The number of bytes in a line may not be a multiple of 4, you should therefore be careful when handling this case since a DMA request is generated each time a complete 32-bit word has been constructed from the captured data. When an end of frame is detected and the 32-bit word to be transferred has not been completely received, the remaining data are padded with ‘0s’ and a DMA request is generated. The crop feature and embedded synchronization codes cannot be used in the JPEG format. 31.4.9 FIFO Input mode A four-word FIFO is implemented to manage data rate transfers on the AHB. The DCMI features a simple FIFO controller with a read pointer incremented each time the camera interface reads from the AHB, and a write pointer incremented each time the camera interface writes to the FIFO. There is no overrun protection to prevent the data from being overwritten if the AHB interface does not sustain the data transfer rate. In case of overrun or errors in the synchronization signals, the FIFO is reset and the DCMI interface waits for a new start of frame. 1118/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) 31.5 Data format description 31.5.1 Data formats Three types of data are supported: • 8-bit progressive video: either monochrome or raw Bayer format • YCbCr 4:2:2 progressive video • RGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits for green) takes two clock cycles to be transferred. Compressed data: JPEG For B&W, YCbCr or RGB data, the maximum input size is 2048 × 2048 pixels. No limit in JPEG compressed mode. For monochrome, RGB & YCbCr, the frame buffer is stored in raster mode. 32-bit words are used. Only the little endian format is supported. Figure 232. Pixel raster scan order 7ORD 7ORD 7ORD 0IXEL ROW 0IXEL RASTER SCAN ORDER INCREASING ADDRESSES 0IXEL ROW N n AI 31.5.2 Monochrome format Characteristics: • Raster format • 8 bits per pixel Table 244 shows how the data are stored. Table 244. Data storage in monochrome progressive video format Byte address 31:24 23:16 15:8 7:0 0 n+3 n+2 n+1 n 4 n+7 n+6 n+5 n+4 DocID029587 Rev 3 1119/3178 1134 Digital camera interface (DCMI) 31.5.3 RM0433 RGB format Characteristics: • Raster format • RGB • Interleaved: one buffer: R, G & B interleaved: BRGBRGBRG, etc. • Optimized for display output The RGB planar format is compatible with standard OS frame buffer display formats. Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported. The 24 BPP (palletized format) and grayscale formats are not supported. Pixels are stored in a raster scan order, that is from top to bottom for pixel rows, and from left to right within a pixel row. Pixel components are R (red), G (green) and B (blue). All components have the same spatial resolution (4:4:4 format). A frame is stored in a single part, with the components interleaved on a pixel basis. Table 245 shows how the data are stored. Table 245. Data storage in RGB progressive video format 31.5.4 Byte address 31:27 26:21 20:16 15:11 10:5 4:0 0 Red n + 1 Green n + 1 Blue n + 1 Red n Green n Blue n 4 Red n + 4 Green n + 3 Blue n + 3 Red n + 2 Green n + 2 Blue n + 2 YCbCr format Characteristics: • Raster format • YCbCr 4:2:2 • Interleaved: one Buffer: Y, Cb & Cr interleaved: CbYCrYCbYCr, etc. Pixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue and red). Each component is encoded in 8 bits. Luma and chroma are stored together (interleaved) as shown in Table 246. Table 246. Data storage in YCbCr progressive video format 31.5.5 Byte address 31:24 23:16 15:8 7:0 0 Yn+1 Cr n Yn Cb n 4 Yn+3 Cr n + 2 Yn+2 Cb n + 2 YCbCr format - Y only Characteristics: • Raster format • YCbCr 4:2:2 • The buffer only contains Y information - monochrome image Pixel components are Y (luminance or “luma”), Cb and Cr (chrominance or “chroma” blue and red). In this mode, the chroma information is dropped. Only Luma component of each 1120/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) pixel , encoded in 8 bits, is stored as shown in Table 247. The result is a monochrome image having the same resolution as the original YCbCr data. Table 247. Data storage in YCbCr progressive video format - Y extraction mode 31.5.6 Byte address 31:24 23:16 15:8 7:0 0 Yn+3 Yn+2 Yn+1 Yn 4 Yn+7 Yn+6 Yn+5 Yn+4 Half resolution image extraction This is a modification of the previous reception modes, being applicable to monochrome, RGB or Y extraction modes. This mode allows to only store a half resolution image. It is selected through OELS and LSM control bits. 31.6 DCMI interrupts Five interrupts are generated. All interrupts are maskable by software. The global interrupt (dcmi_it) is the OR of all the individual interrupts. Table 248 gives the list of all interrupts. Table 248. DCMI interrupts Interrupt name 31.7 Interrupt event IT_LINE Indicates the end of line IT_FRAME Indicates the end of frame capture IT_OVR indicates the overrun of data reception IT_VSYNC Indicates the synchronization frame IT_ERR Indicates the detection of an error in the embedded synchronization frame detection dcmi_it Logic OR of the previous interrupts DCMI register description All DCMI registers have to be accessed as 32-bit words, otherwise a bus error occurs. 31.7.1 DCMI control register (DCMI_CR) Address offset: 0x00 Reset value: 0x0000 0x0000 DocID029587 Rev 3 1121/3178 1134 Digital camera interface (DCMI) RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OELS LSM OEBS rw rw rw rw 4 3 2 1 0 ESS JPEG CROP CM CAPTURE rw rw rw rw rw 15 14 13 12 Res. ENABLE Res. Res. rw 11 10 EDM rw 9 8 FCRC rw rw rw 7 6 5 VSPOL HSPOL PCKPOL rw rw rw 17 16 BSM rw Bits 31:21 Reserved, must be kept at reset value. Bit 20 OELS: Odd/Even Line Select (Line Select Start) This bit works in conjunction with LSM field (LSM = 1) 0: Interface captures first line after the frame start, second one being dropped 1: Interface captures second line from the frame start, first one being dropped Bit 19 LSM: Line Select mode 0: Interface captures all received lines 1: Interface captures one line out of two. Bit 18 OEBS: Odd/Even Byte Select (Byte Select Start) This bit works in conjunction with BSM field (BSM <> 00) 0: Interface captures first data (byte or double byte) from the frame/line start, second one being dropped 1: Interface captures second data (byte or double byte) from the frame/line start, first one being dropped Bits 17:16 BSM[1:0]: Byte Select mode 00: Interface captures all received data 01: Interface captures every other byte from the received data 10: Interface captures one byte out of four 11: Interface captures two bytes out of four Note: This mode only work for EDM[1:0]=00. For all other EDM values, this bit field must be programmed to the reset value. Bit 15 Reserved, must be kept at reset value. Bit 14 ENABLE: DCMI enable 0: DCMI disabled 1: DCMI enabled Note: The DCMI configuration registers should be programmed correctly before enabling this Bit Bits 13:12 Reserved, must be kept at reset value. Bits 11:10 EDM[1:0]: Extended data mode 00: Interface captures 8-bit data on every pixel clock 01: Interface captures 10-bit data on every pixel clock 10: Interface captures 12-bit data on every pixel clock 11: Interface captures 14-bit data on every pixel clock Bits 9:8 FCRC[1:0]: Frame capture rate control These bits define the frequency of frame capture. They are meaningful only in Continuous grab mode. They are ignored in snapshot mode. 00: All frames are captured 01: Every alternate frame captured (50% bandwidth reduction) 10: One frame in 4 frames captured (75% bandwidth reduction) 11: reserved 1122/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) Bit 7 VSPOL: Vertical synchronization polarity This bit indicates the level on the DCMI_VSYNC pin when the data are not valid on the parallel interface. 0: DCMI_VSYNC active low 1: DCMI_VSYNC active high Bit 6 HSPOL: Horizontal synchronization polarity This bit indicates the level on the DCMI_HSYNC pin when the data are not valid on the parallel interface. 0: DCMI_HSYNC active low 1: DCMI_HSYNC active high Bit 5 PCKPOL: Pixel clock polarity This bit configures the capture edge of the pixel clock 0: Falling edge active. 1: Rising edge active. Bit 4 ESS: Embedded synchronization select 0: Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals. 1: Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. Note: Valid only for 8-bit parallel data. HSPOL/VSPOL are ignored when the ESS bit is set. This bit is disabled in JPEG mode. Bit 3 JPEG: JPEG format 0: Uncompressed video format 1: This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode. Bit 2 CROP: Crop feature 0: The full image is captured. In this case the total number of bytes in an image frame should be a multiple of 4 1: Only the data inside the window specified by the crop register will be captured. If the size of the crop window exceeds the picture size, then only the picture size is captured. Bit 1 CM: Capture mode 0: Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA. 1: Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset. DocID029587 Rev 3 1123/3178 1134 Digital camera interface (DCMI) RM0433 Bit 0 CAPTURE: Capture enable 0: Capture disabled. 1: Capture enabled. The camera interface waits for the first start of frame, then a DMA request is generated to transfer the received data into the destination memory. In snapshot mode, the CAPTURE bit is automatically cleared at the end of the 1st frame received. In continuous grab mode, if the software clears this bit while a capture is ongoing, the bit will be effectively cleared after the frame end. Note: The DMA controller and all DCMI configuration registers should be programmed correctly before enabling this bit. 1124/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) 31.7.2 DCMI status register (DCMI_SR) Address offset: 0x04 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FNE r VSYNC HSYNC r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 FNE: FIFO not empty This bit gives the status of the FIFO 1: FIFO contains valid data 0: FIFO empty Bit 1 VSYNC This bit gives the state of the DCMI_VSYNC pin with the correct programmed polarity. When embedded synchronization codes are used, the meaning of this bit is the following: 0: active frame 1: synchronization between frames In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in DCMI_CR is set. Bit 0 HSYNC This bit gives the state of the DCMI_HSYNC pin with the correct programmed polarity. When embedded synchronization codes are used, the meaning of this bit is the following: 0: active line 1: synchronization between lines In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in DCMI_CR is set. DocID029587 Rev 3 1125/3178 1134 Digital camera interface (DCMI) 31.7.3 RM0433 DCMI raw interrupt status register (DCMI_RIS) Address offset: 0x08 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE _RIS VSYNC _RIS ERR _RIS OVR _RIS FRAME _RIS r r r r r DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value. Bits 31:5 Reserved, must be kept at reset value. Bit 4 LINE_RIS: Line raw interrupt status This bit gets set when the DCMI_HSYNC signal changes from the inactive state to the active state. It goes high even if the line is not valid. In the case of embedded synchronization, this bit is set only if the CAPTURE bit in DCMI_CR is set. It is cleared by writing a ‘1’ to the LINE_ISC bit in DCMI_ICR. Bit 3 VSYNC_RIS: DCMI_VSYNC raw interrupt status This bit is set when the DCMI_VSYNC signal changes from the inactive state to the active state. In the case of embedded synchronization, this bit is set only if the CAPTURE bit is set in DCMI_CR. It is cleared by writing a ‘1’ to the VSYNC_ISC bit in DCMI_ICR. Bit 2 ERR_RIS: Synchronization error raw interrupt status 0: No synchronization error detected 1: Embedded synchronization characters are not received in the correct order. This bit is valid only in the embedded synchronization mode. It is cleared by writing a ‘1’ to the ERR_ISC bit in DCMI_ICR. Note: This bit is available only in embedded synchronization mode. Bit 1 OVR_RIS: Overrun raw interrupt status 0: No data buffer overrun occurred 1: A data buffer overrun occurred and the data FIFO is corrupted. This bit is cleared by writing a ‘1’ to the OVR_ISC bit in DCMI_ICR. Bit 0 FRAME_RIS: Capture complete raw interrupt status 0: No new capture 1: A frame has been captured. This bit is set when a frame or window has been captured. In case of a cropped window, this bit is set at the end of line of the last line in the crop. It is set even if the captured frame is empty (e.g. window cropped outside the frame). This bit is cleared by writing a ‘1’ to the FRAME_ISC bit in DCMI_ICR. 1126/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) 31.7.4 DCMI interrupt enable register (DCMI_IER) Address offset: 0x0C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE _IE VSYNC _IE ERR _IE OVR _IE FRAME _IE rw rw rw rw rw The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. Bits 31:5 Reserved, must be kept at reset value. Bit 4 LINE_IE: Line interrupt enable 0: No interrupt generation when the line is received 1: An Interrupt is generated when a line has been completely received Bit 3 VSYNC_IE: DCMI_VSYNC interrupt enable 0: No interrupt generation 1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state The active state of the DCMI_VSYNC signal is defined by the VSPOL bit. Bit 2 ERR_IE: Synchronization error interrupt enable 0: No interrupt generation 1: An interrupt is generated if the embedded synchronization codes are not received in the correct order. Note: This bit is available only in embedded synchronization mode. Bit 1 OVR_IE: Overrun interrupt enable 0: No interrupt generation 1: An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received. Bit 0 FRAME_IE: Capture complete interrupt enable 0: No interrupt generation 1: An interrupt is generated at the end of each received frame/crop window (in crop mode). DocID029587 Rev 3 1127/3178 1134 Digital camera interface (DCMI) 31.7.5 RM0433 DCMI masked interrupt status register (DCMI_MIS) This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set. Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LINE _MIS VSYNC _MIS ERR _MIS OVR _MIS FRAME _MIS r r r r r Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:5 Reserved, must be kept at reset value. Bit 4 LINE_MIS: Line masked interrupt status This bit gives the status of the masked line interrupt 0: No interrupt generation when the line is received 1: An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER. Bit 3 VSYNC_MIS: VSYNC masked interrupt status This bit gives the status of the masked VSYNC interrupt 0: No interrupt is generated on DCMI_VSYNC transitions 1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER. The active state of the DCMI_VSYNC signal is defined by the VSPOL bit. Bit 2 ERR_MIS: Synchronization error masked interrupt status This bit gives the status of the masked synchronization error interrupt 0: No interrupt is generated on a synchronization error 1: An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set. Note: This bit is available only in embedded synchronization mode. Bit 1 OVR_MIS: Overrun masked interrupt status This bit gives the status of the masked overflow interrupt 0: No interrupt is generated on overrun 1: An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER. Bit 0 FRAME_MIS: Capture complete masked interrupt status This bit gives the status of the masked capture complete interrupt 0: No interrupt is generated after a complete capture 1: An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER. 1128/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) 31.7.6 DCMI interrupt clear register (DCMI_ICR) Address offset: 0x14 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE _ISC VSYNC _ISC ERR _ISC OVR _ISC FRAME _ISC w w w w w The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect. Bits 15:5 Reserved, must be kept at reset value. Bit 4 LINE_ISC: line interrupt status clear Writing a ‘1’ into this bit clears LINE_RIS in the DCMI_RIS register Bit 3 VSYNC_ISC: Vertical Synchronization interrupt status clear Writing a ‘1’ into this bit clears the VSYNC_RIS bit in DCMI_RIS Bit 2 ERR_ISC: Synchronization error interrupt status clear Writing a ‘1’ into this bit clears the ERR_RIS bit in DCMI_RIS Note: This bit is available only in embedded synchronization mode. Bit 1 OVR_ISC: Overrun interrupt status clear Writing a ‘1’ into this bit clears the OVR_RIS bit in DCMI_RIS Bit 0 FRAME_ISC: Capture complete interrupt status clear Writing a ‘1’ into this bit clears the FRAME_RIS bit in DCMI_RIS DocID029587 Rev 3 1129/3178 1134 Digital camera interface (DCMI) 31.7.7 RM0433 DCMI embedded synchronization code register (DCMI_ESCR) Address offset: 0x18 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 FEC 19 18 17 16 LEC rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw LSC FSC Bits 31:24 FEC: Frame end delimiter code This byte specifies the code of the frame end delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, FEC. If FEC is programmed to 0xFF, all the unused codes (0xFF0000XY) are interpreted as frame end delimiters. Bits 23:16 LEC: Line end delimiter code This byte specifies the code of the line end delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, LEC. Bits 15:8 LSC: Line start delimiter code This byte specifies the code of the line start delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, LSC. Bits 7:0 FSC: Frame start delimiter code This byte specifies the code of the frame start delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, FSC. If FSC is programmed to 0xFF, no frame start delimiter is detected. But, the 1st occurrence of LSC after an FEC code will be interpreted as a start of frame delimiter. 1130/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) 31.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR) Address offset: 0x1C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 FEU 19 18 17 16 LEU rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw LSU FSU Bits 31:24 FEU: Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter. 0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data. 1: The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the frame end delimiter with the received data Bits 23:16 LEU: Line end delimiter unmask This byte specifies the mask to be applied to the code of the line end delimiter. 0: The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line end delimiter with the received data 1: The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the line end delimiter with the received data Bits 15:8 LSU: Line start delimiter unmask This byte specifies the mask to be applied to the code of the line start delimiter. 0: The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line start delimiter with the received data 1: The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the line start delimiter with the received data Bits 7:0 FSU: Frame start delimiter unmask This byte specifies the mask to be applied to the code of the frame start delimiter. 0: The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the frame start delimiter with the received data 1: The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the frame start delimiter with the received data DocID029587 Rev 3 1131/3178 1134 Digital camera interface (DCMI) 31.7.9 RM0433 DCMI crop window start (DCMI_CWSTRT) Address offset: 0x20 Reset value: 0x0000 0x0000 31 30 29 Res. Res. Res. 28 27 26 25 24 23 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 Res. Res. rw rw rw rw rw rw 22 21 20 19 18 17 16 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw VST[12:0 HOFFCNT[13:0] rw rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:16 VST[12:0]: Vertical start line count The image capture starts with this line number. Previous line data are ignored. 0x0000 => line 1 0x0001 => line 2 0x0002 => line 3 .... Bits 15:14 Reserved, must be kept at reset value. Bits 13:0 HOFFCNT[13:0]: Horizontal offset count This value gives the number of pixel clocks to count before starting a capture. 31.7.10 DCMI crop window size (DCMI_CWSIZE) Address offset: 0x24 Reset value: 0x0000 0x0000 31 30 Res. Res. 15 14 Res. Res. 29 28 27 26 25 24 23 rw rw rw rw rw rw rw 13 12 11 10 9 8 7 22 21 20 19 18 17 16 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw VLINE13:0] CAPCNT[13:0] rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:16 VLINE[13:0]: Vertical line count This value gives the number of lines to be captured from the starting point. 0x0000 => 1 line 0x0001 => 2 lines 0x0002 => 3 lines .... 1132/3178 DocID029587 Rev 3 RM0433 Digital camera interface (DCMI) Bits 15:14 Reserved, must be kept at reset value. Bits 13:0 CAPCNT[13:0]: Capture count This value gives the number of pixel clocks to be captured from the starting point on the same line. It value should corresponds to word-aligned data for different widths of parallel interfaces. 0x0000 => 1 pixel 0x0001 => 2 pixels 0x0002 => 3 pixels .... 31.7.11 DCMI data register (DCMI_DR) Address offset: 0x28 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 Byte3 r r r r 15 14 13 12 r r r r r r r r 11 10 9 8 7 6 5 4 Byte1 r r r r 19 18 17 16 r r r r 3 2 1 0 r r r r Byte2 Byte0 r r r r r r r r Bits 31:24 Data byte 3 Bits 23:16 Data byte 2 Bits 15:8 Data byte 1 Bits 7:0 Data byte 0 The digital camera Interface packages all the received data in 32-bit format before requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA transfers and avoid DMA overrun conditions. DocID029587 Rev 3 1133/3178 1134 0x24 DCMI_ESCR Reset value DCMI_CWSIZE 0x28 Reset value 1134/3178 FEC 0 0 0 Reset value 0 0 DCMI_ESUR Reset value 0 0 0 DCMI_CWSTRT Reset value 0 DCMI_DR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEU 0 0 0 Byte3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VST[12:0 VLINE13:0] 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 LEC 0 LEU 0 0 0 Byte2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 0 0 0 0 0 0 0 Byte1 0 FRAME_MIS 0 0 0 0 LSC FSC 0 LSU 0 0 0 FRAME_ISC ERR_MIS 0 ERR_ISC 0 OVR_ISC VSYNC_IE ERR_IE OVR_IE FRAME_IE Reset value LINE_IE Res. Res. Res. Res. Res. Res. VSYNC_RIS ERR_RIS OVR_RIS FRAME_RIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE_RIS Reset value VSYNC_ISC OVR_MIS Res. Res. VSYNC_MIS Reset value LINE_MIS Reset value LINE_ISC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CROP CM CAPTURE 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 HOFFCNT[13:0] CAPCNT[13:0] Byte0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. HSYNC ESS JPEG 0 FNE PCKPOL 0 VSYNC VSPOL HSPOL 0 Res. Res. Res. ENABLE 0 Res. Res. Res. Res. Res. Res. EDM FCRC Res. Res. Res. Res. Res. Res. Res. Res. LSM OEBS Res. 0 Res. Res. Res. Res. OELS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. DCMI_ICR Res. DCMI_MIS Res. DCMI_IER Res. 0x0C Res. DCMI_RIS Res. 0x08 Res. DCMI_SR Res. 0x04 Res. Reset value BSM Res. 0x20 DCMI_CR Res. 0x00 Res. 0x1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. 0x18 Res. 0x14 Res. 0x10 Res. Offset Res. 31.7.12 Res. Digital camera interface (DCMI) RM0433 DCMI register map Table 249 summarizes the DCMI registers. Table 249. DCMI register map and reset values 0 0 0 0 0 0 0 0 0 0 0 0 0 FSU RM0433 32 32.1 LCD-TFT Display Controller (LTDC) LCD-TFT Display Controller (LTDC) Introduction The LCD-TFT (Liquid Crystal Display - Thin Film Transistor) display controller provides a parallel digital RGB (Red, Green, Blue) and signals for horizontal, vertical synchronization, Pixel Clock and Data Enable as output to interface directly to a variety of LCD and TFT panels. 32.2 LTDC main features • 24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888) • 2 display layers with dedicated FIFO (64x64-bit) • Color Look-Up Table (CLUT) up to 256 color (256x24-bit) per layer • Programmable timings for different display panels • Programmable Background color • Programmable polarity for HSync, VSync and Data Enable • Up to 8 Input color formats selectable per layer • – ARGB8888 – RGB888 – RGB565 – ARGB1555 – ARGB4444 – L8 (8-bit Luminance or CLUT) – AL44 (4-bit alpha + 4-bit luminance) – AL88 (8-bit alpha + 8-bit luminance) Pseudo-random dithering output for low bits per channel – Dither width 2-bits for Red, Green, Blue • Flexible blending between two layers using alpha value (per pixel or constant) • Color Keying (transparency color) • Programmable Window position and size • Supports thin film transistor (TFT) color displays • AXI master interface with burst of 16 double-words • Up to 4 programmable interrupt events DocID029587 Rev 3 1135/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 32.3 LTDC functional description 32.3.1 LTDC block diagram The block diagram of the LTDC is shown in Figure 233: LTDC block diagram. Figure 233. LTDC block diagram 3L[HO&ORFNGRPDLQ ELW$;,EXV OWGFBDFON /D\HU ),)2 $;, LQWHUIDFH /&'B+6<1& %OHQGLQJ XQLW /D\HU ),)2 OWGFBSFON ELW$3%EXV 3)& 'LWKHULQJ XQLW /&'B96<1& /&'B'( /&'B&/. 3)& /&'B5> @ /&' 7)7 3DQHO /&'B*> @ &RQILJXUDWLRQ DQG6WDWXV UHJLVWHUV /&'B%> @ 7LPLQJ JHQHUDWRU OWFGBOLBLW OWGFBLW OWGFBHUUBLW OWGFBNHUBFN 06Y9 Layer FIFO: One FIFO 64x64 bit per layer. PFC: Pixel Format Convertor performing the pixel format conversion from the selected input pixel format of a layer to words. AXI interface: For data transfer from memories to the FIFO. Blending, Dithering unit and Timings Generator: Refer to Section 32.4.1 and Section 32.4.2. 32.3.2 LCD-TFT internal signals Table 250 gives the list of LCD-TFT internal signals. Table 250. LCD-TFT internal signals 1136/3178 Names Signal type Description ltdc_aclk Digital input Clock for LCD-TFT registers in AXI clock domain ltdc_pclk Digital input LCD-TFT register interface clock ltdc_ker_ck Digital input LCD-TFT kernel clock used for LCD_CLK (pixel clock) generation ltdc_li_it Digital output LCD-TFT line interrupt trigger for MDMA DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) Table 250. LCD-TFT internal signals (continued) 32.3.3 Names Signal type Description ltdc_it Digital output LCD-TFT global interrupt request ltdc_err_it Digital output LCD-TFT global error interrupt request LCD-TFT pins and external signal interface Table 251 summarizes the LTDC signal interface. Table 251. LCD-TFT pins and signal interface LCD-TFT signals I/O LCD_CLK O Clock Output LCD_HSYNC O Horizontal Synchronization LCD_VSYNC O Vertical Synchronization LCD_DE O Not Data Enable LCD_R[7:0] O Data: 8-bit Red data LCD_G[7:0] O Data: 8-bit Green data LCD_B[7:0] O Data: 8-bit Blue data Description The LTDC-TFT controller pins must be configured by the user application. The unused pins can be used for other purposes. For LTDC outputs up to 24-bit (RGB888), if less than 8bpp are used to output for example RGB565 or RGB666 to interface on 16b-bit or 18-bit displays, the RGB display data lines must be connected to the MSB of the LCD-TFT controller RGB data lines. As an example, in the case of an LCD-TFT controller interfacing with a RGB565 16-bit display, the LCD display R[4:0], G[5:0] and B[4:0] data lines pins must be connected to LCD-TFT controller LCD_R[7:3], LCD_G[7:2] and LCD_B[7:3]. 32.3.4 LTDC reset and clocks The LCD-TFT controller peripheral uses 3 clock domains: • AXI clock domain (ltdc_aclk) This domain contains the LCD-TFT AXI master interface for data transfer from the memories to the Layer FIFO and the frame buffer configuration register • APB clock domain (ltdc_pclk): This domain contains the global configuration registers and the interrupt register. • Pixel clock domain (LCD_CLK) This domain contains the pixel data generation, the layer configuration register as well as the LCD-TFT interface signal generator. The LCD_CLK output should be configured following the panel requirements. The LCD_CLK is generated from a specific PLL output (refer to the Reset and Clock control section). Table 252 summarizes the clock domain for each register. DocID029587 Rev 3 1137/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 Table 252. Clock domain for each register LTDC register Clock domain LTDC_LxCR LTDC_LxCFBAR ltdc_aclk LTDC_LxCFBLR LTDC_LxCFBLNR LTDC_SRCR LTDC_IER ltdc_pclk LTDC_ISR LTDC_ICR LTDC_SSCR LTDC_BPCR LTDC_AWCR LTDC_TWCR LTDC_GCR LTDC_BCCR LTDC_LIPCR LTDC_CPSR Pixel Clock (LCD_CLK) LTDC_CDSR LTDC_LxWHPCR LTDC_LxWVPCR LTDC_LxCKCR LTDC_LxPFCR LTDC_LxCACR LTDC_LxDCCR LTDC_LxBFCR LTDC_LxCLUTWR Care must be taken while accessing the LTDC registers, the APB bus is stalled during the access for a given time period (refer to Table 253). Table 253. LTDC register access and update durations Register clock domain AXI domain APB domain Pixel clock domain Register read access duration 7 x ltdc_pclk + 5 x ltdc_aclk 7 x ltdc_pclk 7 x ltdc_pclk + 5 x ltdc_ker_clk Register write access duration 6 x ltdc_pclk + 5 x ltdc_aclk 6 x ltdc_pclk 6 x ltdc_pclk + 5 x ltdc_ker_clk 1138/3178 DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) The LCD controller can be reset by setting the corresponding bit in the RCC_APBRSTR register. It resets the three clock domains. 32.4 LTDC programmable parameters The LCD-TFT controller provides flexible configurable parameters. It can be enabled or disabled through the LTDC_GCR register. 32.4.1 LTDC Global configuration parameters Synchronous Timings: Figure 234 presents the configurable timing parameters generated by the Synchronous Timings Generator block presented in the block diagram Figure 233. It generates the Horizontal and Vertical Synchronization timings panel signals, the Pixel Clock and the Data Enable signals. Figure 234. LCD-TFT synchronous timings +6<1& ZLGWK 7RWDOZLGWK +%3 +)3 $FWLYHZLGWK 96<1&ZLGWK 9%3 7RWDO+HLJKW 'DWD/LQH $FWLYH'LVSOD\$UHD $FWLYH+HLJKW 'DWD Q /LQH Q 9)3 06Y 9 Note: The HBP and HFP are respectively the Horizontal back porch and front porch period. The VBP and the VFP are respectively the Vertical back porch and front porch period. DocID029587 Rev 3 1139/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 The LCD-TFT programmable synchronous timings are: Note: – HSYNC and VSYNC Width: Horizontal and Vertical Synchronization width configured by programming a value of HSYNC Width - 1 and VSYNC Width - 1 in the LTDC_SSCR register. – HBP and VBP: Horizontal and Vertical Synchronization back porch width configured by programming the accumulated value HSYNC Width + HBP - 1 and the accumulated value VSYNC Width + VBP - 1 in the LTDC_BPCR register. – Active Width and Active Height: The Active Width and Active Height are configured by programming the accumulated value HSYNC Width + HBP + Active Width - 1 and the accumulated value VSYNC Width + VBP + Active Height - 1 in the LTDC_AWCR register (only up to 1024x768 is supported). – Total Width: The Total width is configured by programming the accumulated value HSYNC Width + HBP + Active Width + HFP - 1 in the LTDC_TWCR register. The HFP is the Horizontal front porch period. – Total Height: The Total Height is configured by programming the accumulated value VSYNC Height + VBP + Active Height + VFP - 1 in the LTDC_TWCR register. The VFP is the Vertical front porch period. When the LTDC is enabled, the timings generated start with X/Y=0/0 position as the first horizontal synchronization pixel in the vertical synchronization area and following the back porch, active data display area and the front porch. When the LTDC is disabled, the timing generator block is reset to X=Total Width - 1, Y=Total Height - 1 and held the last pixel before the vertical synchronization phase and the FIFO are flushed. Therefore only blanking data is output continuously. Example of Synchronous timings configuration: TFT-LCD timings (should be extracted from Panel datasheet): • Horizontal and Vertical Synchronization width: 0xA pixels and 0x2 lines • Horizontal and Vertical back porch: 0x14 pixels and 0x2 lines • Active Width and Active Height: 0x140 pixels, 0xF0 lines (320x240) • Horizontal front porch: 0xA pixels • Vertical front porch: 0x4 lines The programmed values in the LTDC Timings registers will be: • LTDC_SSCR register: to be programmed to 0x00090001. (HSW[11:0] is 0x9 and VSH[10:0] is 0x1) • LTDC_BPCR register: to be programmed to 0x001D0003. (AHBP[11:0] is 0x1D(0xA+ 0x13) and AVBP[10:0] is 0x3(0x2 + 0x1)) • LTDC_AWCR register: to be programmed to 0x015D00F3. (AAW[11:0] is 0x15D(0xA +0x14 +0x13F) and AAH[10:0] is 0xF3(0x2 +0x2 + 0xEF) • LTDC_TWCR register: to be programmed to 0x00000167. (TOTALW[11:0] is 0x167(0xA +0x14 +0x140 + 0x9) • LTDC_THCR register: to be programmed to 0x000000F7. (TOTALH[10:0] is 0xF7(0x2 +0x2 + 0xF0 + 3) Programmable polarity The Horizontal and Vertical Synchronization, Data Enable and Pixel Clock output signals polarity can be programmed to active high or active low through the LTDC_GCR register. 1140/3178 DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) Background Color A constant background color (RGB888) can programmed through the LTDC_BCCR register. It is used for blending with the bottom layer. Dithering The Dithering pseudo-random technique using an LFSR is used to add a small random value (threshold) to each pixel color channel (R, G or B) value, thus rounding up the MSB in some cases when displaying a 24-bit data on 18-bit display. Thus the Dithering technique is used to round data which is different from one frame to the other. The Dither pseudo-random technique is the same as comparing LSBs against a threshold value and adding a 1 to the MSB part only, if the LSB part is >= the threshold. The LSBs are typically dropped once dithering was applied. The width of the added pseudo-random value is 2 bits for each color channel; 2 bits for Red, 2 bits for Green and 2 bits for Blue. Once the LCD-TFT controller is enabled, the LFSR starts running with the first active pixel and it is kept running even during blanking periods and when dithering is switched off. If the LTDC is disabled, the LFSR is reset. The Dithering can be switched On and Off on the fly through the LTDC_GCR register. Reload Shadow registers Some configuration registers are shadowed. The shadow registers values can be reloaded immediately to the active registers when writing to these registers or at the beginning of the vertical blanking period following the configuration in the LTDC_SRCR register. If the immediate reload configuration is selected, the reload should be only activated when all new registers have been written. The shadow registers should not be modified again before the reload has been done. Reading from the shadow registers returns the actual active value. The new written value can only be read after the reload has taken place. A register reload interrupt can be generated if enabled in the LTDC_IER register. The shadowed registers are all the Layer 1 and Layer 2 registers except the LTDC_LxCLUTWR register. Interrupt generation event Refer to Section 32.5: LTDC interrupts for interrupt configuration. 32.4.2 Layer programmable parameters Up to two layers can be enabled, disabled and configured separately. The layer display order is fixed and it is bottom up. If two layers are enabled, the Layer2 is the top displayed window. Windowing Every layer can be positioned and resized and it must be inside the Active Display area. The window position and size are configured through the top-left and bottom-right X/Y positions and the Internal timing generator which includes the synchronous, back porch size and the active data area. Refer to LTDC_LxWHPCR and LTDC_WVPCR registers. DocID029587 Rev 3 1141/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 The programmable layer position and size defines the first/last visible pixel of a line and the first/last visible line in the window. It allows to display either the full image frame or only a part of the image frame. Refer to Figure 235 • The first and the last visible pixel in the layer are set by configuring the WHSTPOS[11:0] and WHSPPOS[11:0] in the LTDC_LxWHPCR register. • The first and the last visible lines in the layer are set by configuring the WVSTPOS[10:0] and WVSPPOS[10:0] in the LTDC_LxWVPCR register. Figure 235. Layer window programmable parameters $FWLYH'DWD$UHD :967326ELWVLQ /7'&B/[:+3&5 :967326ELWVLQ /7'&B/[:93&5 :963326ELWVLQ /7'&B/[:93&5 :LQGRZ :+63326ELWVLQ /7'&B/[:+3&5 06Y 9 Pixel input Format The programmable pixel format is used for the data stored in the frame buffer of a layer. Up to 8 input pixel formats can be configured for every layer through the LTDC_LxPFCR register The pixel data is read from the frame buffer and then transformed to the internal 8888 (ARGB) format as follows: • Components which have a width of less than 8 bits get expanded to 8 bits by bit replication. The selected bit range is concatenated multiple times until it is longer than 8 bits. Of the resulting vector, the 8 MSB bits are chosen. Example: 5 bits of an RGB565 red channel become (bit positions): 43210432 (the 3 LSBs are filled with the 3 MSBs of the 5 bits) The figure below describes the pixel data mapping depending on the selected format. Table 254. Pixel Data mapping versus Color Format ARGB8888 @+3 Ax[7:0] @+2 Rx[7:0] @+1 Gx[7:0] @ Bx[7:0] @+7 Ax+1[7:0] @+6 Rx+1[7:0] @+5 Gx+1[7:0] @+4 Bx+1[7:0] RGB888 1142/3178 DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) Table 254. Pixel Data mapping versus Color Format (continued) ARGB8888 @+3 Bx+1[7:0] @+2 Rx[7:0] @+1 Gx[7:0] @ Bx[7:0] @+7 Gx+2[7:0] @+6 Bx+2[7:0] @+5 Rx+1[7:0] @+4 Gx+1[7:0] RGB565 @+3 Rx+1[4:0] Gx+1[5:3] @+2 Gx+1[2:0] Bx+1[4:0] @+1 Rx[4:0] Gx[5:3] @ Gx[2:0] Bx[4:0] @+7 Rx+3[4:0] Gx+3[5:3] @+6 Gx+3[2:0] Bx+3[4:0] @+5 Rx+2[4:0] Gx+2[5:3] @+4 Gx+2[2:0] Bx+2[4:0] ARGB1555 @+3 Ax+1[0]Rx+1[4:0] Gx+1[4:3] @+2 Gx+1[2:0] Bx+1[4:0] @+1 Ax[0] Rx[4:0] Gx[4:3] @ Gx[2:0] Bx[4:0] @+7 Ax+3[0]Rx+3[4:0] Gx+3[4:3] @+6 Gx+3[2:0] Bx+3[4:0] @+5 Ax+2[0]Rx+2[4:0]Gx+2[4: 3] @+4 Gx+2[2:0] Bx+2[4:0] ARGB4444 @+3 Ax+1[3:0]Rx+1[3:0] @+2 Gx+1[3:0] Bx+1[3:0] @+1 Ax[3:0] Rx[3:0] @ Gx[3:0] Bx[3:0] @+7 Ax+3[3:0]Rx+3[3:0] @+6 Gx+3[3:0] Bx+3[3:0] @+5 Ax+2[3:0]Rx+2[3:0] @+4 Gx+2[3:0] Bx+2[3:0] L8 @+3 Lx+3[7:0] @+2 Lx+2[7:0] @+1 Lx+1[7:0] @ Lx[7:0] @+7 Lx+7[7:0] @+6 Lx+6[7:0] @+5 Lx+5[7:0] @+4 Lx+4[7:0] AL44 @+3 Ax+3[3:0] Lx+3[3:0] @+2 Ax+2[3:0] Lx+2[3:0] @+1 Ax+1[3:0] Lx+1[3:0] @ Ax[3:0] Lx[3:0] @+7 Ax+7[3:0] Lx+7[3:0] @+6 Ax+6[3:0] Lx+6[3:0] @+5 Ax+5[3:0] Lx+5[3:0] @+4 Ax+4[3:0] Lx+4[3:0] AL88 @+3 Ax+1[7:0] @+2 Lx+1[7:0] @+1 Ax[7:0] @ Lx[7:0] @+7 Ax+3[7:0] @+6 Lx+3[7:0] @+5 Ax+2[7:0] @+4 Lx+2[7:0] DocID029587 Rev 3 1143/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 Color Look-Up Table (CLUT) The CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and it is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel format. First, the CLUT has to be loaded with the R, G and B values that will replace the original R, G, B values of that pixel (indexed color). Each color (RGB value) has its own address which is the position within the CLUT. The R, G and B values and their own respective address are programmed through the LTDC_LxCLUTWR register. • In case of L8 and AL88 input pixel format, the CLUT has to be loaded by 256 colors. The address of each color is configured in the CLUTADD bits in the LTDC_LxCLUTWR register. • In case of AL44 input pixel format, the CLUT has to be only loaded by 16 colors. The address of each color must be filled by replicating the 4-bit L channel to 8-bit as follows: – L0 (indexed color 0), at address 0x00 – L1, at address 0x11 – L2, at address 0x22 – ..... – L15, at address 0xFF Color Frame Buffer Address Every Layer has a start address for the color frame buffer configured through the LTDC_LxCFBAR register. When a layer is enabled, the data is fetched from the Color Frame Buffer. Color Frame Buffer Length Every layer has a total line length setting for the color frame buffer in bytes and a number of lines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR register respectively. The line length and the number of lines settings are used to stop the prefetching of data to the layer FIFO at the end of the frame buffer. • If it is set to less bytes than required, a FIFO underrun interrupt is generated if it has been previously enabled. • If it is set to more bytes than actually required, the useless data read from the FIFO is discarded. The useless data is not displayed. Color Frame Buffer Pitch Every layer has a configurable pitch for the color frame buffer, which is the distance between the start of one line and the beginning of the next line in bytes. It is configured through the LTDC_LxCFBLR register. Layer Blending The blending is always active and the two layers can be blended following the blending factors configured through the LTDC_LxBFCR register. 1144/3178 DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) The blending order is fixed and it is bottom up. If two layers are enabled, first the Layer1 is blended with the Background color, then the Layer2 is blended with the result of blended color of Layer1 and the background. Refer to Figure 236. Figure 236. Blending two layers with background /D\HU /D\HU /D\HU %* /D\HU%* /D\HU /D\HU%* 06 9 Default color Every layer can have a default color in the format ARGB which is used outside the defined layer window or when a layer is disabled. The default color is configured through the LTDC_LxDCCR register. The blending is always performed between the two layers even when a layer is disabled. To avoid displaying the default color when a layer is disabled, keep the blending factors of this layer in the LTDC_LxBFCR register to their reset value. Color Keying A color key (RGB) can be configured to be representative for a transparent pixel. If the Color Keying is enabled, the current pixels (after format conversion and before CLUT respectively blending) are compared to the color key. If they match for the programmed RGB value, all channels (ARGB) of that pixel are set to 0. The Color Key value can be configured and used at run-time to replace the pixel RGB value. The Color Keying is enabled through the LTDC_LxCKCR register. The Color Keying is configured through the LTDC_LxCKCR register. The programmed value depends on the pixel format as it is compared to current pixel after pixel format conversion to ARGB888. Example: if the a mid-yellow color (50% red + 50% green) is used as the transparent color key: 32.5 • In RGB565, the mid yellow color is 0x8400. Set the LTDC_LxCKCR to 0x848200. • In ARGB8888, the mid yellow color is 0x808000, set LTDC_LxCKCR to 0x808000. • In all CLUT-based color modes (L8, AL88, AL44), set one of the palette entry to the mid yellow color 0x808000 and set the LTDC_LxCKCR to 0x808000. LTDC interrupts The LTDC provides four maskable interrupts logically ORed to two interrupt vectors. DocID029587 Rev 3 1145/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 The interrupt sources can be enabled or disabled separately through the LTDC_IER register. Setting the appropriate mask bit to 1 enables the corresponding interrupt. The two interrupts are generated on the following events: • Line interrupt: generated when a programmed line is reached. The line interrupt position is programmed in the LTDC_LIPCR register • Register Reload interrupt: generated when the shadow registers reload was performed during the vertical blanking period • FIFO Underrun interrupt: generated when a pixel is requested from an empty layer FIFO • Transfer Error interrupt: generated when an AXI bus error occurs during data transfer Those interrupts events are connected to the NVIC controller as described in the figure below. Figure 237. Interrupt events /LQH /7'&JOREDOLQWHUUXSW 5HJLVWHU5HORDG ),)28QGHUUXQ /7'&JOREDO(UURULQWHUUXSW 7UDQVIHUHUURU 06 9 Table 255. LTDC interrupt requests Interrupt event Event flag Enable Control bit LIF LIE Register Reload RRIF RRIEN FIFO Underrun FUDERRIF FUDERRIE Transfer Error TERRIF TERRIE Line 1146/3178 DocID029587 Rev 3 RM0433 32.6 Note: LCD-TFT Display Controller (LTDC) LTDC programming procedure • Enable the LTDC clock in the RCC register • Configure the required Pixel clock following the panel datasheet • Configure the Synchronous timings: VSYNC, HSYNC, Vertical and Horizontal back porch, active data area and the front porch timings following the panel datasheet as described in the Section 32.4.1: LTDC Global configuration parameters • Configure the synchronous signals and clock polarity in the LTDC_GCR register • If needed, configure the background color in the LTDC_BCCR register • Configure the needed interrupts in the LTDC_IER and LTDC_LIPCR register • Configure the Layer1/2 parameters by programming: – The Layer window horizontal and vertical position in the LTDC_LxWHPCR and LTDC_WVPCR registers. The layer window must be in the active data area. – The pixel input format in the LTDC_LxPFCR register – The color frame buffer start address in the LTDC_LxCFBAR register – The line length and pitch of the color frame buffer in the LTDC_LxCFBLR register – The number of lines of the color frame buffer in the LTDC_LxCFBLNR register – if needed, load the CLUT with the RGB values and its address in the LTDC_LxCLUTWR register – If needed, configure the default color and the blending factors respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers • Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register • If needed, dithering and color keying can be enabled respectively in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled on the fly. • Reload the shadow registers to active register through the LTDC_SRCR register. • Enable the LCD-TFT controller in the LTDC_GCR register. • All layer parameters can be modified on the fly except the CLUT. The new configuration has to be either reloaded immediately or during vertical blanking period by configuring the LTDC_SRCR register. All layer’s registers are shadowed. Once a register is written, it should not be modified again before the reload has been done. Thus, a new write to the same register will override the previous configuration if not yet reloaded. DocID029587 Rev 3 1147/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 32.7 LTDC registers 32.7.1 LTDC Synchronization Size Configuration Register (LTDC_SSCR) This register defines the number of Horizontal Synchronization pixels minus 1 and the number of Vertical Synchronization lines minus 1. Refer to Figure 234 and Section 32.4: LTDC programmable parameters for an example of configuration. Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw rw HSW[11:0] VSH[10:0] rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HSW[11:0]: Horizontal Synchronization Width (in units of pixel clock period) These bits define the number of Horizontal Synchronization pixel minus 1. Bits 15:11 Reserved, must be kept at reset value. Bits 10:0 VSH[10:0]: Vertical Synchronization Height (in units of horizontal scan line) These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. 32.7.2 LTDC Back Porch Configuration Register (LTDC_BPCR) This register defines the accumulated number of Horizontal Synchronization and back porch pixels minus 1 (HSYNC Width + HBP- 1) and the accumulated number of Vertical Synchronization and back porch lines minus 1 (VSYNC Height + VBP - 1). Refer to Figure 234 and Section 32.4: LTDC programmable parameters for an example of configuration. Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 Res. Res. Res. Res. rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw rw AHBP[11:0] AVBP[10:0] rw 1148/3178 25 rw rw rw rw DocID029587 Rev 3 rw RM0433 LCD-TFT Display Controller (LTDC) Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 AHBP[11:0]: Accumulated Horizontal back porch (in units of pixel clock period) These bits define the Accumulated Horizontal back porch width which includes the Horizontal Synchronization and Horizontal back porch pixels minus 1. The Horizontal back porch is the period between Horizontal Synchronization going inactive and the start of the active display part of the next scan line. Bits 15:11 Reserved, must be kept at reset value. Bits 10:0 AVBP[10:0]: Accumulated Vertical back porch (in units of horizontal scan line) These bits define the accumulated Vertical back porch width which includes the Vertical Synchronization and Vertical back porch lines minus 1. The Vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. 32.7.3 LTDC Active Width Configuration Register (LTDC_AWCR) This register defines the accumulated number of Horizontal Synchronization, back porch and Active pixels minus 1 (HSYNC width + HBP + Active Width - 1) and the accumulated number of Vertical Synchronization, back porch lines and Active lines minus 1 (VSYNC Height+ BVBP + Active Height - 1). Refer to Figure 234 and Section 32.4: LTDC programmable parameters for an example of configuration. Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw rw AAW[11:0] AAH[10:0] rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 AAW[11:0]: Accumulated Active Width (in units of pixel clock period) These bits define the Accumulated Active Width which includes the Horizontal Synchronization, Horizontal back porch and Active pixels minus 1. The Active Width is the number of pixels in active display area of the panel scan line. Refer to device datasheet for maximum Active Width supported following maximum pixel clock. Bits 15:11 Reserved, must be kept at reset value. Bits 10:0 AAH[10:0]: Accumulated Active Height (in units of horizontal scan line) These bits define the Accumulated Height which includes the Vertical Synchronization, Vertical back porch and the Active Height lines minus 1. The Active Height is the number of active lines in the panel. Refer to device datasheet for maximum Active Height supported following maximum pixel clock. DocID029587 Rev 3 1149/3178 1169 LCD-TFT Display Controller (LTDC) 32.7.4 RM0433 LTDC Total Width Configuration Register (LTDC_TWCR) This register defines the accumulated number of Horizontal Synchronization, back porch, Active and front porch pixels minus 1 (HSYNC Width + HBP + Active Width + HFP - 1) and the accumulated number of Vertical Synchronization, back porch lines, Active and Front lines minus 1 (VSYNC Height+ BVBP + Active Height + VFP - 1). Refer to Figure 234 and Section 32.4: LTDC programmable parameters for an example of configuration. Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. rw rw rw rw rw rw 16 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw rw TOTALW[11:0] TOTALH[10:0] rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 TOTALW[11:0]: Total Width (in units of pixel clock period) These bits defines the accumulated Total Width which includes the Horizontal Synchronization, Horizontal back porch, Active Width and Horizontal front porch pixels minus 1. Bits 15:11 Reserved, must be kept at reset value. Bits 10:0 TOTALH[10:0]: Total Height (in units of horizontal scan line) These bits defines the accumulated Height which includes the Vertical Synchronization, Vertical back porch, the Active Height and Vertical front porch Height lines minus 1. 32.7.5 LTDC Global Control Register (LTDC_GCR) This register defines the global configuration of the LCD-TFT controller. Address offset: 0x18 Reset value: 0x0000 2220 31 30 29 28 HSPOL VSPOL DEPOL PCPOL rw rw rw rw 15 14 13 12 Res. DRW[2:0] r 1150/3178 r 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DEN 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. LTDCEN rw Res. r DGW[2:0] r r Res. r DBW[2:0] r DocID029587 Rev 3 r r rw RM0433 LCD-TFT Display Controller (LTDC) Bit 31 HSPOL: Horizontal Synchronization Polarity This bit is set and cleared by software. 0: Horizontal Synchronization polarity is active low 1: Horizontal Synchronization polarity is active high Bit 30 VSPOL: Vertical Synchronization Polarity This bit is set and cleared by software. 0: Vertical Synchronization is active low 1: Vertical Synchronization is active high Bit 29 DEPOL: Not Data Enable Polarity This bit is set and cleared by software. 0: Not Data Enable polarity is active low 1: Not Data Enable polarity is active high Bit 28 PCPOL: Pixel Clock Polarity This bit is set and cleared by software. 0: Pixel clock polarity is active low 1: Pixel clock is active high Bits 27:17 Reserved, must be kept at reset value. Bit 16 DEN: Dither Enable This bit is set and cleared by software. 0: Dither disable 1: Dither enable Bit 15 Reserved, must be kept at reset value. Bits 14:12 DRW[2:0]: Dither Red Width These bits return the Dither Red Bits Bit 11 Reserved, must be kept at reset value. Bits 10:8 DGW[2:0]: Dither Green Width These bits return the Dither Green Bits Bit 7 Reserved, must be kept at reset value. Bits 6:4 DBW[2:0]: Dither Blue Width These bits return the Dither Blue Bits Bits 3:1 Reserved, must be kept at reset value. Bit 0 LTDCEN: LCD-TFT controller enable bit This bit is set and cleared by software. 0: LTDC disable 1: LTDC enable DocID029587 Rev 3 1151/3178 1169 LCD-TFT Display Controller (LTDC) 32.7.6 RM0433 LTDC Shadow Reload Configuration Register (LTDC_SRCR) This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VBR IMR rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 VBR: Vertical Blanking Reload This bit is set by software and cleared only by hardware after reload. (it cannot be cleared through register write once it is set) 0: No effect 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the Active Display Area) Bit 0 IMR: Immediate Reload This bit is set by software and cleared only by hardware after reload. 0: No effect 1: The shadow registers are reloaded immediately Note: The shadow registers read back the active values. Until the reload has been done, the 'old' value will be read. 32.7.7 LTDC Background Color Configuration Register (LTDC_BCCR) This register defines the background color (RGB888). Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 1152/3178 19 18 17 16 BCRED[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw BCGREEN[7:0] rw 20 BCBLUE[7:0] rw rw DocID029587 Rev 3 rw rw rw RM0433 LCD-TFT Display Controller (LTDC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 BCRED[7:0]: Background Color Red value These bits configure the background red value Bits 15:8 BCGREEN[7:0]: Background Color Green value These bits configure the background green value Bits 7:0 BCBLUE[7:0]: Background Color Blue value These bits configure the background blue value 32.7.8 LTDC Interrupt Enable Register (LTDC_IER) This register determines which status flags generate an interrupt request by setting the corresponding bit to 1. Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RRIE TERRIE FUIE LIE rw rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 RRIE: Register Reload interrupt enable This bit is set and cleared by software 0: Register Reload interrupt disable 1: Register Reload interrupt enable Bit 2 TERRIE: Transfer Error Interrupt Enable This bit is set and cleared by software 0: Transfer Error interrupt disable 1: Transfer Error interrupt enable Bit 1 FUIE: FIFO Underrun Interrupt Enable This bit is set and cleared by software 0: FIFO Underrun interrupt disable 1: FIFO Underrun Interrupt enable Bit 0 LIE: Line Interrupt Enable This bit is set and cleared by software 0: Line interrupt disable 1: Line Interrupt enable DocID029587 Rev 3 1153/3178 1169 LCD-TFT Display Controller (LTDC) 32.7.9 RM0433 LTDC Interrupt Status Register (LTDC_ISR) This register returns the interrupt status flag Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RRIF TERRIF FUIF LIF r r r r Bits 31:4 Reserved, must be kept at reset value. Bit 3 RRIF: Register Reload Interrupt Flag 0: No Register Reload interrupt generated 1: Register Reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) Bit 2 TERRIF: Transfer Error interrupt flag 0: No Transfer Error interrupt generated 1: Transfer Error interrupt generated when a Bus error occurs Bit 1 FUIF: FIFO Underrun Interrupt flag 0: NO FIFO Underrun interrupt generated. 1: A FIFO underrun interrupt is generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO Bit 0 LIF: Line Interrupt flag 0: No Line interrupt generated 1: A Line interrupt is generated, when a programmed line is reached 32.7.10 LTDC Interrupt Clear Register (LTDC_ICR) Address offset: 0x3C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CFUIF CLIF w w CRRIF CTERRIF w 1154/3178 DocID029587 Rev 3 w RM0433 LCD-TFT Display Controller (LTDC) Bits 31:4 Reserved, must be kept at reset value. Bit 3 CRRIF: Clears Register Reload Interrupt Flag 0: No effect 1: Clears the RRIF flag in the LTDC_ISR register Bit 2 CTERRIF: Clears the Transfer Error Interrupt Flag 0: No effect 1: Clears the TERRIF flag in the LTDC_ISR register. Bit 1 CFUIF: Clears the FIFO Underrun Interrupt flag 0: No effect 1: Clears the FUDERRIF flag in the LTDC_ISR register. Bit 0 CLIF: Clears the Line Interrupt Flag 0: No effect 1: Clears the LIF flag in the LTDC_ISR register. 32.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR) This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure 234. Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. rw rw rw rw rw LIPOS[10:0] rw rw rw rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:0 LIPOS[10:0]: Line Interrupt Position These bits configure the line interrupt position 32.7.12 LTDC Current Position Status Register (LTDC_CPSR) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CXPOS[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CYPOS[15:0] r r r r r r r r r DocID029587 Rev 3 1155/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 Bits 31:16: CXPOS[15:0]: Current X Position These bits return the current X position Bits 15:0 CYPOS[15:0]: Current Y Position These bits return the current Y position 32.7.13 LTDC Current Display Status Register (LTDC_CDSR) This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and Horizontal/Vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high. Address offset: 0x48 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HDES VDES r r HSYNC VSYNC S S r r Bits 31:4 Reserved, must be kept at reset value. Bit 3 HSYNCS: Horizontal Synchronization display Status 0: Active low 1: Active high Bit 2 VSYNCS: Vertical Synchronization display Status 0: Active low 1: Active high Bit 1 HDES: Horizontal Data Enable display Status 0: Active low 1: Active high Bit 0 VDES: Vertical Data Enable display Status 0: Active low 1: Active high Note: 1156/3178 The returned status does not depend on the configured polarity in the LTDC_GCR register, instead it returns the current active display phase. DocID029587 Rev 3 RM0433 32.7.14 LCD-TFT Display Controller (LTDC) LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) Address offset: 0x84 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLUTEN Res. Res. COLKEN LEN rw rw rw Bits 31:5 Reserved, must be kept at reset value. Bit 4 CLUTEN: Color Look-Up Table Enable This bit is set and cleared by software. 0: Color Look-Up Table disable 1: Color Look-Up Table enable The CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color Look-Up Table (CLUT) on page 1144 Bit 3 Reserved, must be kept at reset value. Bit 2 Reserved, must be kept at reset value. Bit 1 COLKEN: Color Keying Enable This bit is set and cleared by software. 0: Color Keying disable 1: Color Keying enable Bit 0 LEN: Layer Enable This bit is set and cleared by software. 0: Layer disable 1: Layer enable 32.7.15 LTDC Layerx Window Horizontal Position Configuration Register (LTDC_LxWHPCR) (where x=1..2) This register defines the Horizontal Position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[10:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[10:0] bits in the LTDC_AWCR register. DocID029587 Rev 3 1157/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 Address offset: 0x88 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 WHSPPOS[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw WHSTPOS[11:0] rw rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 WHSPPOS[11:0]: Window Horizontal Stop Position These bits configure the last visible pixel of a line of the layer window. WHSPPOS[11:0] must be >= AHBP[10:0] bits + 1 (programmed in LTDC_BPCR register). Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 WHSTPOS[11:0]: Window Horizontal Start Position These bits configure the first visible pixel of a line of the layer window. WHSTPOS[11:0] must be <= AAW[10:0] bits (programmed in LTDC_AWCR register). Example: The LTDC_BPCR register is configured to 0x000E0005(AHBP[11:0] is 0xE) and the LTDC_AWCR register is configured to 0x028E01E5(AAW[11:0] is 0x28E). To configure the horizontal position of a window size of 630x460, with horizontal start offset of 5 pixels in the Active data area. 1158/3178 1. Layer window first pixel: WHSTPOS[11:0] should be programmed to 0x14 (0xE+1+0x5) 2. Layer window last pixel: WHSPPOS[11:0] should be programmed to 0x28A DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) 32.7.16 LTDC Layerx Window Vertical Position Configuration Register (LTDC_LxWVPCR) (where x=1..2) This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[10:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[10:0] bits in the LTDC_AWCR register. Address offset: 0x8C + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 Res. Res. Res. Res. Res. 15 14 13 12 11 Res. Res. Res. Res. Res. 26 25 24 23 22 21 20 19 18 17 16 WVSPPOS[10:0] rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw WVSTPOS[10:0] rw rw rw rw rw rw rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:16 WVSPPOS[10:0]: Window Vertical Stop Position These bits configures the last visible line of the layer window. WVSPPOS[10:0] must be >= AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register). Bits 15:11 Reserved, must be kept at reset value. Bits 10:0 WVSTPOS[10:0]: Window Vertical Start Position These bits configure the first visible line of the layer window. WVSTPOS[10:0] must be <= AAH[10:0] bits (programmed in LTDC_AWCR register). Example: The LTDC_BPCR register is configured to 0x000E0005 (AVBP[10:0] is 0x5) and the LTDC_AWCR register is configured to 0x028E01E5 (AAH[10:0] is 0x1E5). To configure the vertical position of a window size of 630x460, with vertical start offset of 8 lines in the Active data area: 32.7.17 1. Layer window first line: WVSTPOS[10:0] should be programmed to 0xE (0x5 + 1 + 0x8) 2. Layer window last line: WVSPPOS[10:0] should be programmed to 0x1DA LTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR) (where x=1..2) This register defines the color key value (RGB), which is used by the Color Keying. Address offset: 0x90 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 DocID029587 Rev 3 1159/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 CKRED[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw CKGREEN[7:0] CKBLUE[7:0] rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 CKRED[7:0]: Color Key Red value Bits 15:8 CKGREEN[7:0]: Color Key Green value Bits 7:0 CKBLUE[7:0]: Color Key Blue value 32.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2) This register defines the pixel format which is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). Address offset: 0x94 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PF[2:0] rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PF[2:0]: Pixel Format These bits configures the Pixel format 000: ARGB8888 001: RGB888 010: RGB565 011: ARGB1555 100: ARGB4444 101: L8 (8-Bit Luminance) 110: AL44 (4-Bit Alpha, 4-Bit Luminance) 111: AL88 (8-Bit Alpha, 8-Bit Luminance) 1160/3178 DocID029587 Rev 3 rw rw RM0433 LCD-TFT Display Controller (LTDC) 32.7.19 LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR) (where x=1..2) This register defines the constant alpha value (divided by 255 by Hardware), which is used in the alpha blending. Refer to LTDC_LxBFCR register. Address offset: 0x98 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: (Layerx -1) 0x0000 00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw CONSTA[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 CONSTA[7:0]: Constant Alpha These bits configure the Constant Alpha used for blending. The Constant Alpha is divided by 255 by hardware. Example: if the programmed Constant Alpha is 0xFF, the Constant Alpha value is 255/255=1 32.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2) This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. Address offset: 0x9C + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 DCALPHA[7:0] 14 13 12 11 10 9 8 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw DCGREEN[7:0] rw 19 DCRED[7:0] rw 15 20 DCBLUE[7:0] rw rw rw rw rw Bits 31:24 DCALPHA[7:0]: Default Color Alpha These bits configure the default alpha value DocID029587 Rev 3 1161/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 Bits 23:16 DCRED[7:0]: Default Color Red These bits configure the default red value Bits 15:8 DCGREEN[7:0]: Default Color Green These bits configure the default green value Bits 7:0 DCBLUE[7:0]: Default Color Blue These bits configure the default blue value 1162/3178 DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) 32.7.21 LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2) This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs • BC = Blended color • BF1 = Blend Factor 1 • C = Current layer color • BF2 = Blend Factor 2 • Cs = subjacent layers blended color Address offset: 0xA0 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0607 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BF1[2:0] rw rw rw BF2[2:0] rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:8 BF1[2:0]: Blending Factor 1 These bits select the blending factor F1 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: Constant Alpha 101: Reserved 110: Pixel Alpha x Constant Alpha 111:Reserved Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 BF2[2:0]: Blending Factor 2 These bits select the blending factor F2 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: Reserved 101: 1 - Constant Alpha 110: Reserved 111: 1 - (Pixel Alpha x Constant Alpha) DocID029587 Rev 3 1163/3178 1169 LCD-TFT Display Controller (LTDC) Note: RM0433 The Constant Alpha value, is the programmed value in the LxCACR register divided by 255 by hardware. Example: Only layer1 is enabled, BF1 configured to Constant Alpha BF2 configured to 1 - Constant Alpha Constant Alpha: The Constant Alpha programmed in the LxCACR register is 240 (0xF0). Thus, the Constant Alpha value is 240/255 = 0.94 C: Current Layer Color is 128 Cs: Background color is 48 Layer1 is blended with the background color. BC = Constant Alpha x C + (1 - Constant Alpha) x Cs = 0.94 x 128 + (1- 0.94) x 48 = 123. 32.7.22 LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2) This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. Address offset: 0xAC + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFBADD[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CFBADD[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 CFBADD[31:0]: Color Frame Buffer Start Address These bits defines the color frame buffer start address. 32.7.23 LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2) This register defines the color frame buffer line length and pitch. Address offset: 0xB0 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 Res. Res. Res. 28 26 25 24 23 22 21 20 19 18 17 16 CFBP[17:0] rw rw rw rw rw rw rw rw rw rw rw rw rw 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw CFBLL[12:0] rw 1164/3178 27 rw rw rw rw rw rw DocID029587 Rev 3 RM0433 LCD-TFT Display Controller (LTDC) Bits 31:29 Reserved, must be kept at reset value.r Bits 28:16 CFBP[12:0]: Color Frame Buffer Pitch in bytes These bits define the pitch which is the increment from the start of one line of pixels to the start of the next line in bytes. Bits 15:13 Reserved, must be kept at reset value. Bits 12:0 CFBLL[12:0]: Color Frame Buffer Line Length These bits define the length of one line of pixels in bytes + 7. The line length is computed as follows: Active high width x number of bytes per pixel + 7. Example: 32.7.24 • A frame buffer having the format RGB565 (2 bytes per pixel) and a width of 256 pixels (total number of bytes per line is 256x2=512 bytes), where pitch = line length requires a value of 0x02000207 to be written into this register. • A frame buffer having the format RGB888 (3 bytes per pixel) and a width of 320 pixels (total number of bytes per line is 320x3=960), where pitch = line length requires a value of 0x03C003C7 to be written into this register. LTDC Layerx ColorFrame Buffer Line Number Register (LTDC_LxCFBLNR) (where x=1..2) This register defines the number of lines in the color frame buffer. Address offset: 0xB4 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. rw rw rw rw rw CFBLNBR[10:0] rw rw rw rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:0 CFBLNBR[10:0]: Frame Buffer Line Number These bits define the number of lines in the frame buffer which corresponds to the Active high width. Note: The number of lines and line length settings define how much data is fetched per frame for every layer. If it is configured to less bytes than required, a FIFO underrun interrupt will be generated if enabled. The start address and pitch settings on the other hand define the correct start of every line in memory. DocID029587 Rev 3 1165/3178 1169 LCD-TFT Display Controller (LTDC) 32.7.25 RM0433 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2) This register defines the CLUT address and the RGB value. Address offset: 0xC4 + 0x80 x (Layerx -1), Layerx = 1 or 2 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 CLUTADD[7:0] 19 18 17 16 RED[7:0] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w GREEN[7:0] w w w w w BLUE[7:0] w w w w w w w w Bits 31:24 CLUTADD[7:0]: CLUT Address These bits configure the CLUT address (color position within the CLUT) of each RGB value Bits 23:16 RED[7:0]: Red value These bits configure the red value Bits 15:8 GREEN[7:0]: Green value These bits configure the green value Bits 7:0 BLUE[7:0]: Blue value These bits configure the blue value Note: The CLUT write register should only be configured during blanking period or if the layer is disabled. The CLUT can be enabled or disabled in the LTDC_LxCR register. The CLUT is only meaningful for L8, AL44 and AL88 pixel format. 1166/3178 DocID029587 Rev 3 0x0038 LTDC_ISR DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. LTDCEN 0 0 Res. 0 0 Reset value Reset value IMR 0 0 0 0 0 LIE 0 0 0 0 0 LIF AVBP[10:0] 0 0 VBR AAH[10:0] 0 FUIE TOTALH[10:0] 0 Res. DBW[2:0] Res. Res. Res. 0 FUIF 1 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 0 TERRIE BCBLUE[7:0] 0 Res. DGW[2:0] Res. DRW[2:0] Res. 0 TERRIF 0 Res. 1 Res. 0 Res. Res. DEN 0 RRIE 0 Res. 0 0 Res. 0 Res. 1 0 RRIF Reset value 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. BCGREEN[7:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. BCRED[7:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. AHBP[11:0] 0 Res. AAV[11:0] 0 Res. TOTALW[11:0] 0 0 Res. 0 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Reset value Res. Res. Res. LTDC_SRCR Res. 0 Res. 0 Res. 0 0 Res. PCPOL 0 Res. Reset value Res. DEPOL Reset value Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. VSPOL Reset value Res. LTDC_IER Res. LTDC_BCCR Res. 0x0034 LTDC_TWCR Res. 0x002C HSPOL 0x0024 LTDC_GCR Res. 0x0018 Res. 0x0014 LTDC_AWCR Res. 0x0010 LTDC_BPCR Res. 0x000C VSH[10:0] Res. Res. Res. Res. Res. HSW[11:0] Res. Res. Res. Res. LTDC_SSCR Res. 0x0008 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 32.7.26 Res. RM0433 LCD-TFT Display Controller (LTDC) LTDC register map The following table summarizes the LTDC registers. Refer to the register boundary addresses table for the LTDC register base address. Table 256. LTDC register map and reset values 0 0 0 0 0 0 0 1167/3178 1169 LCD-TFT Display Controller (LTDC) RM0433 CTERRIF CFUIF CLIF Res. CRRIF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDC_ICR 0x003C Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 256. LTDC register map and reset values (continued) 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDC_LIPCR Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDC_CDSR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDC_L1BFCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDC_L1CFBLR Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBP[17:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 Res. 0 Res. 0 Res. 0 1168/3178 0 0 0 0 PF[2:0] 0 0 0 1 1 1 0 0 0 0 0 0 BF1[2:0] 1 1 0 0 0 0 0 0 0 BF2[2:0] 1 1 1 CFBADD[31:0] Reset value Reset value 0 Res. 0 Res. 0x00B0 0 DCBLUE[7:0] Res. 0 1 Res. 0 1 Res. 0 1 Res. Reset value LTDC_L1CFBAR 1 DCGREEN[7:0] Res. DCRED[7:0] Res. DCALPHA[7:0] Res. LTDC_L1DCCR Reset value 0x00AC 0 CONSTA[7:0] 1 Res. 0x00A0 0 CKBLUE[7:0] Res. CKGREEN[7:0] Reset value 0x009C 0 0 Res. LTDC_L1CACR 0 WVSTPOS[10:0] 0 CKRED[7:0] 0 Res. Res. Res. 0 0 Res. Res. Res. 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Reset value 0x0098 0 WHSTPOS[11:0] Res. 0 Res. Res. Res. Res. Res. Res. LTDC_L1PFCR 0 WVSPPOS[10:0] Reset value 0x0094 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. LTDC_L1CKCR Res. Reset value 0x0090 0 Res. Res. Res. LTDC_L1WVPCR Res. 0x008C WHSPPOS[11:0] 0 Res. Reset value Res. Res. Res. LTDC_L1WHPCR Res. 0x0088 0 0 Res. Reset value Res. CLUTEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDC_L1CR Res. 0x0084 LEN 1 Reset value COLKEN VDES 0 HDES 0 VSYNCS 0 Res. Reset value Res. CYPOS[15:0] Res. CXPOS[15:0] 0 Res. LTDC_CPSR 0 Res. 0x0048 0 Res. 0x0044 BCRED[10:0] HSYNCS 0x0040 Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLL[12:0] 0 0 0 0 0 0 0 0 RM0433 LCD-TFT Display Controller (LTDC) Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDC_L2CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDC_L2BFCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 BF1[2:0] 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF[2:0] 0 0 1 1 1 0 0 0 BF2[2:0] 1 1 1 CLUTADD[7:0] 0 0 0 0 0 0 RED[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLNBR[10:0] 0 0 0 0 GREEN[7:0] 0 0 CFBLL[12:0] 0 LTDC_L2CLUTWR Reset value 0 1 Reset value 0x0144 0 Res. 0 0 0 0 0 Re Re Re s. s. s. 0 0 Res. 0 CFBP[12:0] 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. Res. Reset value 0 Res. LTDC_L2CFBLR 0 Res. 0 Res. 0 Res. 0 Res. Reset value LTDC_L2CFBLNR 0 CFBADD[31:0] Res. 0x0134 0 Res. 0 1 Res. 0 1 Res. 0 1 Res. 0 Res. 0x0130 0 DCBLUE[7:0] Res. Reset value LTDC_L2CFBAR 1 DCGREEN[7:0] Res. DCRED[7:0] Res. DCALPHA[7:0] Reset value 0x012C 0 CONSTA[7:0] 1 LTDC_L2DCCR Res. 0x0120 0 CKBLUE[7:0] Res. CKGREEN[7:0] Reset value 0x011C 0 0 Res. LTDC_L2CACR 0 WVSTPOS[10:0] 0 CKRED[7:0] 0 Res. Res. Res. 0 0 Res. Res. Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. 0 Reset value 0x0118 0 WHSTPOS[11:0] Res. 0 Res. 0 Res. 0 Res. 0 WVSPPOS[10:0] Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. LTDC_L2PFCR Res. 0x0114 0 Reset value Res. 0x0110 Res. Reset value LTDC_L2CKCR Res. Res. Res. Res. Res. WHSPPOS[11:0] 0 Res. LTDC_L2WVPCR 0 0 Reset value 0x010C 0 LEN 0 LTDC_L2WHPCR 0 COLKEN 0 Res. Reset value Reset value 0x0108 0 BLUE[7:0] Res. GREEN[7:0] 0 Res. 0 Res. RED[7:0] 0 Res. CLUTADD[7:0] 0 Res. 0x0104 LTDC_L1CLUTWR 0 Res. 0x00C4 0 Res. Reset value CFBLNBR[10:0] CLUTEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LTDC_L1CFBLNR Res. 0x00B4 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 256. LTDC register map and reset values (continued) 0 0 0 0 BLUE[7:0] 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 1169/3178 1169 JPEG codec (JPEG) RM0433 33 JPEG codec (JPEG) 33.1 Introduction The hardware 8-bit JPEG codec encodes uncompressed image data stream or decodes JPEG-compressed image data stream. It also fully manages JPEG headers. 33.2 1170/3178 JPEG codec main features • High-speed fully-synchronous operation • Configurable as encoder or decoder • Single-clock-per-pixel encode/decode • RGB, YCbCr, YCMK and BW (grayscale) image color space support • 8-bit depth per image component at encode/decode • JPEG header generator/parser with enable/disable • Four programmable quantization tables • Single-clock Huffman coding and decoding • Fully-programmable Huffman tables (two AC and two DC) • Fully-programmable minimum coded unit (MCU) • Concurrent input and output data stream interfaces DocID029587 Rev 3 RM0433 JPEG codec (JPEG) 33.3 JPEG codec block functional description 33.3.1 General description The block diagram of the JPEG codec is shown in Figure 238: JPEG codec block diagram. Figure 238. JPEG codec block diagram ELW$+%EXV 'DWDVWUHDP,1 'DWDVWUHDP287 ^ƚĂƚƵƐ͕ĐŽŶƚƌŽůĂŶĚ ĐŽŶĨŝŐƵƌĂƚŝŽŶ ZĞŐŝƐƚĞƌƐ /ŶƉƵƚ&/&K ,ƵĨĨ ŶĐ ZD KƵƚƉƵƚ&/&K ,dDĞŵ ZD ŶĐŽĚĞƌ YƵĂŶƚŝĨŝĞƌ YDĞŵ ZD ĞĐŽĚĞƌ ,ƵĨĨDŝŶ ZD -3(* MSHJBLW MSHJBKFON ,ƵĨĨĂƐĞ ZD MSHJBLIQIBWUJ MSHJBLIWBWUJ ,ƵĨĨ^LJŵď ZD MSHJBRIQHBWUJ MSHJBRIWBWUJ MSHJBRHFBWUJ 06Y9 33.3.2 JPEG internal signals Table 257 lists the JPEG internal signals. Table 257. JPEG internal signals Signal name Signal type Description jpeg_hclk Digital input jpeg_it Digital output JPEG global interrupt jpeg_ift_trg Digital output JPEG input FIFO threshold for MDMA jpeg_ifnf_trg Digital output JPEG input FIFO not full for MDMA jpeg_oft_trg Digital output JPEG output FIFO threshold for MDMA JPEG kernel and register interface clock DocID029587 Rev 3 1171/3178 1184 JPEG codec (JPEG) RM0433 Table 257. JPEG internal signals (continued) 33.3.3 Signal name Signal type Description jpeg_ofne_trg Digital output JPEG output FIFO not empty for MDMA jpeg_oec_trg Digital output JPEG end of conversion for MDMA JPEG decoding procedure The JPEG codec can decode a JPEG stream as defined in the ISO/IEC 10918-1 specification. It can optionally parse the JPEG header and update accordingly the JPEG codec registers, the quantization tables and the Huffman tables. The JPEG codec is configured in decode mode setting the DE bit (decode enable) of the JPEG_CONFR1 register. The JPEG decode starts by setting the START bit of the JPEG_CONFR0 register. The JPEG codec requests data for its input FIFO through generating one of: • MDMA trigger • interrupts Interrupt or MDMA trigger generation for input FIFO Input FIFO can be managed using interrupts or MDMA triggers through two flags according to the FIFO state: • Input FIFO not full flag: a 32-bit value can be written in. • Input FIFO threshold flag: 8 words (32 bytes) can be written in. The interrupt or MDMA trigger generation is independent of the START bit of the JPEG_CONFR0 register. The input FIFO flags are generated regardless of the state of the JPEG codec kernel. Writes are ignored if the input FIFO is full. At the end of the decoding process, extra bytes may remain in the input FIFO and/or an interrupt request / MDMA trigger may be pending. The FIFO can be flushed by setting the IFF bit (Input FIFO Flush) of the JPEG_CR register. Prior to flushing the FIFO: • The interrupts for the input FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO. • The MDMA channel must be stopped to prevent unwanted MDMA trigger. The consequence of not flushing the FIFO at the end of the decoding process is that any remaining data is taken into the next JPEG decoding. Header parsing The header parsing can be activated setting the HDR bit of the JPEG_CONFR1 register. The JPEG header parser supports all markers relevant to the JPEG baseline algorithm indicated in Annex B of the ISO/IEC 10918-1. 1172/3178 DocID029587 Rev 3 RM0433 JPEG codec (JPEG) When parsing a supported marker, the JPEG header parser extracts the required parameters and stores them in shadow registers. At the end of the parsing the JPEG codec registers are updated. If a DQT marker segment is located, quantization data associated with it is written into the quantization table memory. If a DHT marker segment is located, the Huffman table data associated with it is converted into three different table formats (HuffMin, HuffBase and HuffSymb) and stored in their respective memories. Once the parsing operation is completed, the HPDF (header parsing done flag) bit of the JPEG_SR register is set. An interrupt is generated if the EHPIE (end of header parsing interrupt enable) bit of the JPEG_CR register is set. JPEG decoding Once the JPEG header is parsed or JPEG codec registers and memories are properly programmed, the incoming data stream is decoded and the resulting MCUs are sent to the output FIFO. When decoding two images successively, the START bit of the JPEG_CONFR0 register must be set again (even if already 1) after the header processing of the second image is completed. Interrupt or MDMA trigger generation for output FIFO The output FIFO can be managed using interrupts or MDMA triggers through two flags according to the FIFO state: • Output FIFO not empty flag: a 32-bit value can be read out. • Output FIFO Threshold flag: 8 words (32 bytes) can be read out. Reads return 0 if the output FIFO is empty. In case of abort of the JPEG codec operations by reseting the START bit of the JPEG_CONFR0 register, the output FIFO can be flushed. If the FIFO needs to be flushed, it shall be done by software setting the FF bit (FIFO flush) of the JPEG_CR register. Prior to flushing the FIFO: • The interrupts for the output FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO. • The MDMA channel must be stopped to prevent unwanted MDMA trigger. The output FIFO must be flushed at the end of processing before any JPEG configuration change. 33.3.4 JPEG encoding procedure The JPEG codec can encode a JPEG stream as defined in the ISO/IEC 10918-1 specification. It can optionally generate the JPEG Header. The JPEG codec is configured in encode mode resetting the DE bit (decode enable) of the JPEG_CONFR1 register. DocID029587 Rev 3 1173/3178 1184 JPEG codec (JPEG) RM0433 The configuration used for encoding the JPEG must be loaded in the JPEG codec: • JPEG codec configuration registers • quantization tables • Huffman tables The JPEG codec is started setting the START bit of the JPEG_CONFR0 register. Once the JPEG codec has been started, it request data for its input FIFO generating one of: • MDMA trigger • interrupts Interrupt or MDMA trigger generation for input FIFO Input FIFO can be managed using interrupts or MDMA triggers through two flags according to the FIFO state: • Input FIFO not full flag: a 32-bit value can be written in. • Input FIFO threshold flag: 8 words (32 bytes) can be written in. The interrupt or MDMA trigger generation is independent of the START bit of the JPEG_CONFR0 register. The input FIFO flags are generated regardless of the state of the JPEG codec kernel. Writes are ignored if the input FIFO is full. At the end of the encoding process, extra bytes may remain in the input FIFO and/or an interrupt request / MDMA trigger may be pending. The FIFO can be flushed by setting the IFF bit (input FIFO flush) of the JPEG_CR register. Prior to flushing the FIFO: • The interrupts for the input FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO. • The MDMA channel must be stopped to prevent unwanted MDMA trigger. The consequence of not flushing the FIFO at the end of the encoding process is that any remaining data is taken into the next JPEG encoding. JPEG encoding Once the JPEG header generated, the incoming MCUs are encoded and the resulting data stream sent to the output FIFO. Interrupt or MDMA trigger generation for output FIFO Output FIFO can be managed using interrupts or MDMA triggers through two flags according to the FIFO state: • Output FIFO not empty flag: a 32-bit value can be read out. • Output FIFO threshold flag: 8 words (32 bytes) can be read out. Reads return 0 if the output FIFO is empty. In case of abort of the JPEG codec operations by reseting the START bit of the JPEG_CONFR0 register, the output FIFO can be flushed. The FIFO can be flushed by setting the FF bit (FIFO flush) of the JPEG_CR register. 1174/3178 DocID029587 Rev 3 RM0433 JPEG codec (JPEG) Prior to flushing the FIFO: • The interrupts for the output FIFO must be disabled to prevent unwanted interrupt request upon flushing the FIFO. • The MDMA channel must be stopped to prevent unwanted MDMA trigger. The output FIFO must be flushed at the end of processing before any JPEG configuration change. The EOCF bit (end of conversion flag) of the JPEG_SR register can only be cleared when the output FIFO is empty. Clearing either of the HDR bit (header processing) of the JPEG_CONFR1 register and the JCEN bit (JPEG codec enable) of the JPEG_CR register is allowed only when the EOCF bit of the JPEG_SR register is cleared. 33.4 JPEG codec interrupts An interrupt can be produced on the following events: • input FIFO threshold reached • input FIFO not full • output FIFO threshold reached • output FIFO not empty • end of conversion • header parsing done Separate interrupt enable bits are available for flexibility. Table 258. JPEG codec interrupt requests Interrupt event Event flag Enable Control bit IFTF IFTIE Input FIFO not full IFNFF IFNFIE Output FIFO threshold reached OFTF OFTIE Output FIFO not empty OFNEF OFNEIE End of conversion EOCF EOCIE Header parsing done HPDF HPDIE Input FIFO threshold reached DocID029587 Rev 3 1175/3178 1184 JPEG codec (JPEG) RM0433 33.5 JPEG codec registers 33.5.1 JPEG codec control register (JPEG_CONFR0) Address offset: 0x0000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. START w Bits 31: 1 Reserved Bit 0 START: Start This bit start or stop the encoding or decoding process. 0: Stop/abort 1: Start Reads always return 0. 33.5.2 JPEG codec configuration register 1 (JPEG_CONFR1) Address offset: 0x0004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DE Res. YSIZE[15:0] rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. HDR 7 NS[1:0] COLSPACE[1:0] NF[1:0] Bits 31: 16 YSIZE[15:0]: Y Size This field defines the number of lines in source image. Bits 15: 9 Reserved Bit 8 HDR: Header processing This bit enables the header processing (generation/parsing). 0: Disable 1: Enable Bits 7: 6 NS[1:0]: Number of components for scan This field defines the number of components minus 1 for scan header marker segment. 1176/3178 DocID029587 Rev 3 RM0433 JPEG codec (JPEG) Bits 5: 4 COLORSPACE[1:0]: Color space This filed defines the number of quantization tables minus 1 to insert in the output stream. 00: Grayscale (1 quantization table) 01: YUV (2 quantization tables) 10: RGB (3 quantization tables) 11: CMYK (4 quantization tables) Bit 3 DE: Codec operation as coder or decoder This bit selects the code or decode process 0: Code 1: Decode Bit 2 Reserved Bits 1: 0 NF[1:0]: Number of color components This field defines the number of color components minus 1. 00: Grayscale (1 color component) 01: - (2 color components) 10: YUV or RGB (3 color components) 11: CMYK (4 color components) 33.5.3 JPEG codec configuration register 2 (JPEG_CONFR2) Address offset: 0x0008 Reset value: 0x0000 0000 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 25 24 23 22 21 20 19 18 17 16 3 2 1 0 NMCU[25:16] rw 9 8 7 6 5 4 NMCU[15:0] rw Bits 31: 26 Reserved Bits 25: 0 NMCU[25:0]: Number of MCUs For encoding: this field defines the number of MCU units minus 1 to encode. For decoding: this field indicates the number of complete MCU units minus 1 to be decoded (this field is updated after the JPEG header parsing). If the decoded image size has not a X or Y size multiple of 8 or 16 (depending on the sub-sampling process), the resulting incomplete or empty MCU must be added to this value to get the total number of MCUs generated. DocID029587 Rev 3 1177/3178 1184 JPEG codec (JPEG) 33.5.4 RM0433 JPEG codec configuration register 3 (JPEG_CONFR3) Address offset: 0x000C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XSIZE[15:0] rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31: 16 XSIZE[15:0]: X size This field defines the number of pixels per line. Bits 15: 0 Reserved 33.5.5 JPEG codec configuration register 4-7 (JPEG_CONFR4-7) Address offset: 0x0010 + 0x4 * i, where “i” is image component from 0 to 3 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSF[3:0] VSF[3:0] NB[3:0] QT[1:0] HA HD rw rw rw rw rw rw Bits 31: 16 Reserved Bits 15: 12 HSF[3:0]: Horizontal sampling factor Horizontal sampling factor for component i. Bits 11: 8 VSF[3:0]: Vertical sampling factor Vertical sampling factor for component i. Bits 7: 4 NB[3:0]: Number of blocks Number of data units minus 1 that belong to a particular color in the MCU. 1178/3178 DocID029587 Rev 3 RM0433 JPEG codec (JPEG) Bits 3: 2 QT[1:0]: Quantization table Selects quantization table used for component i. 00: Quantization table 0 01: Quantization table 1 10: Quantization table 2 11: Quantization table 3 Bit 1 HA: Huffman AC Selects the Huffman table for encoding AC coefficients. 0: Not selected 1: Selected Bit 0 HD: Huffman DC Selects the Huffman table for encoding DC coefficients. 0: Not selected 1: Selected 33.5.6 JPEG control register (JPEG_CR) Address offset: 0x0030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. OFF IFF Res. Res. Res. Res. Res. Res. HPDIE EOCIE OFNEIE OFTIE IFNFIE IFTIE JCEN r0 r0 rw rw rw rw rw rw rw Bits 31: 15 Reserved Bit 14 OFF: Output FIFO flush This bit flushes the output FIFO. 0: No effect 1: Output FIFO is flushed Reads always return 0. Bit 13 IFF: Input FIFO flush This bit flushes the input FIFO. 0: No effect 1: Input FIFO is flushed Reads always return 0. Bits 12: 7 Reserved Bit 6 HPDIE: Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation. 0: Disabled 1: Enabled DocID029587 Rev 3 1179/3178 1184 JPEG codec (JPEG) RM0433 Bit 5 EOCIE: End of conversion interrupt enable This bit enables interrupt generation at the end of conversion. 0: Disabled 1: Enabled Bit 4 OFNEIE: Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty. 0: Disabled 1: Enabled Bit 3 OFTIE: Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold. 0: Disabled 1: Enabled Bit 2 IFNFIE: Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty. 0: Disabled 1: Enabled Bit 1 IFTIE: Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold. 0: Disabled 1: Enabled Bit 0 JCEN: JPEG core enable This bit enables the JPEG codec core. 0: Disabled (internal registers are reset). 1: Enabled (internal registers are accessible). 33.5.7 JPEG status register (JPEG_SR) Address offset: 0x0034 Reset value: 0x0000 0006 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. COF HPDF EOCF OFNEF OFTF IFNFF IFTF Res. ro ro ro ro ro ro ro 1180/3178 DocID029587 Rev 3 RM0433 JPEG codec (JPEG) Bits 31: 8 Reserved Bit 7 COF: Codec operation flag This bit flags code/decode operation in progress. 0: Not in progress 1: In progress Bit 6 HPDF: Header parsing done flag In decode mode, this bit flags the completion of header parsing and updating internal registers. 0: Not completed 1: Completed Bit 5 EOCF: End of conversion flag This bit flags the completion of encode/decode process and data transfer to the output FIFO. 0: Not completed 1: Completed Bit 4 OFNEF: Output FIFO not empty flag This bit flags that data is available in the output FIFO. 0: Empty (data not available) 1: Not empty (data available) Bit 4 OFTF: Output FIFO threshold flag This bit flags that the amount of data in the output FIFO reaches or exceeds a threshold. 0: Below threshold 1: At or above threshold Bit 2 IFNFF: Input FIFO not full flag This bit flags that the input FIFO is not full (data can be written). 0: Full 1: Not full Bit 1 IFTF: Input FIFO threshold flag This bit flags that the amount of data in the input FIFO is below a threshold. 0: At or above threshold 1: Below threshold. Bit 0 Reserved 33.5.8 JPEG clear flag register (JPEG_CFR) Address offset: 0x0038 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHPDF CEOCF w1c DocID029587 Rev 3 w1c 1181/3178 1184 JPEG codec (JPEG) RM0433 Bits 31: 7 Reserved Bit 6 CHPDF: Clear header parsing done flag Writing 1 clears the HPDF bit of the JPEG_SR register. 0: No effect 1: Clear Bit 5 CEOCF: Clear end of conversion flag Writing 1 clears the ECF bit of the JPEG_SR register. 0: No effect 1: Clear Bits 4: 0 Reserved 33.5.9 JPEG data input register (JPEG_DIR) Address offset: 0x0040 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DATAIN[31:16] wo 15 14 13 12 11 10 9 8 7 DATAIN[15:0] wo Bits 31: 0 DATAIN[31:0]: Data input FIFO Input FIFO data register. 33.5.10 JPEG data output register (JPEG_DOR) Address offset: 0x0044 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 DATAOUT[31:16] ro 15 14 13 12 11 10 9 8 7 DATAOUT[15:0] ro Bits 31: 0 DATAOUT[31:0]: Data output FIFO Output FIFO data register. 1182/3178 DocID029587 Rev 3 0x0038 0x0040 JPEG_CFR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 JPEG_DIR 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Res. VSF[3:0] 0 0 0 0 0 0 0 NB[3:0] 0 0 0 0 0 Res. 0 JCEN 0 Res. 0 IFTIE 0 0 NB[3:0] 0 0 0 0 0 QT[1:0] NB[3:0] QT[1:0] NB[3:0] QT[1:0] 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 HD HD 0 HA 0 Res. 0 HD 0 Res. 0 HA 0 HA 0 Res. Res. 0 Res. 0 QT[1:0] VSF[3:0] 0 IFNFIE Res. 0 OFTIE VSF[3:0] 0 OFNEIE Res. 0 Res. Res. Res. Res. Res. NMCU[25:0] 0 Res. IFTF 0 Res. 0 IFNFF DATAIN[31:0] 0 Res. Reset value OFTF Reset value Res. 0 OFNEF 0 0 0 EOCIE Res. 0 Res. 0 0 EOCF VSF[3:0] CEOCF 0 0 HD Res. Res. HSF[3:0] 0 0 HPDF 0 0 0 CHPDF 0 0 HA Res. Res. HSF[3:0] 0 0 COF 0 0 0 Res. 0 0 0 Res. Res. 0 Res. Res. Res. HSF[3:0] 0 Res. 0 0 0 Res. Res. Res. HSF[3:0] Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Reset value Res. 0 Res. Reset value 0 0 Res. 0 0 0 Res. Reset value Res. 0 Res. Reset value 0 Res. 0 Res. Reset value Res. JPEG_CONFR4 IFF 0 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 OFF Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. XSIZE[15:0] Res. Res. Res. Res. Res. 0 Res. NF[1:0] Res. DE COLSPACE[1:0] NS[1:0] HDR Res. Res. Res. Res. Res. Res. Res. YSIZE[15:0] Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Reset value Res. 0 Res. JPEG_CONFR3 Res. Res. 0 Res. JPEG_CONFR2 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. JPEG_CR Res. Reset value Res. 0 Res. Reserved Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. JPEG_CONFR1 Res. Res. JPEG_SR Res. 0x0034 Res. 0x0030 Res. 0x00200x002C JPEG_CONFR7 Res. 0x001C JPEG_CONFR6 Res. 0x0018 JPEG_CONFR5 Res. 0x0014 Res. 0x0010 Res. 0x000C Res. 0x0008 Res. 0x0004 START Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JPEG_CONFR0 Res. 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 33.5.11 Res. RM0433 JPEG codec (JPEG) JPEG codec register map The following table summarizes the JPEG codec registers. Refer to the register boundary addresses table for the JPEG codec register base address. Table 259. JPEG codec register map and reset values Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1183/3178 1184 JPEG codec (JPEG) RM0433 DATAOUT[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X 0x01900x020C HUFFBASE Res. Res. Res. Res. Res. 0x02100x035C HUFFSYMB 0x03600x04FC DHTMEM Reset value X X X X X X X X X X X X X X X X X X HuffBase RAM X X X X X X X X X X X Res. X Res. X Res. X Res. X Res. X Res. X X X X X X HuffBase RAM X X X X X X X X X X X X X X X X X X X X X X X X X X X X X HuffSymb RAM X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Res. Res. Res. X X X X X X X X X X X X HuffEnc RAM X X X X X X X X X X X X X X X X Res. X HUFFENC Res. DHTMem RAM Reset value Reset value 0 HuffMin RAM Res. HUFFMIN Reset value 0 Res. Reset value 0 QMem RAM Reset value 0x05000x07FC 0 QMEM Res. 0x01500x018C Reset value Res. 0x00500x014C JPEG_DOR Res. 0x0044 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 259. JPEG codec register map and reset values (continued) HuffEnc RAM X X X X X Refer to Section 2.2.2 on page 105 for the register boundary addresses. 1184/3178 DocID029587 Rev 3 X X X RM0433 True random number generator (RNG) 34 True random number generator (RNG) 34.1 Introduction The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. The RNG can be used to construct a NIST compliant Deterministic Random Bit Generator (DRBG), acting as a live entropy source. The RNG true random number generator has been validated according to the German AIS-31 standard. 34.2 RNG main features • The RNG delivers 32-bit true random numbers, produced by an analog entropy source conditioned with block cipher AES-CBC. • It is validated according to the AIS-31 pre-defined class PTG.2 evaluation methodology, which is part of the German Common Criteria (CC) scheme. • It produces four 32-bit random samples every 4x54 AHB clock cycles. • It allows embedded continuous basic health tests with associated error management – Includes too low sampling clock detection and repetition count tests. • It can be disabled to reduce power consumption. • It has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only (else for write accesses an AHB bus error is generated), Warning! any write not equal to 32 bits might corrupt the register content. DocID029587 Rev 3 1185/3178 1198 True random number generator (RNG) RM0433 34.3 RNG functional description 34.3.1 RNG block diagram Figure 239 shows the RNG block diagram. Figure 239. RNG block diagram 751*Y UQJBLW %<3 &RQGLWLRQLQJORJLF 51*B'5 VWDWXV 51*B65 $ODUPV GDWD )DXOWGHWHFWLRQ &ORFNFKHFNHU $+%FORFNGRPDLQ ELWGDWDRXWSXW ELW$+%%XV $+% LQWHUIDFH [ELW ),)2 51*B&5 FRQWURO ELW %DQNHG5HJLVWHUV $(6 &%& ELWGDWDLQSXW ELW 5DZGDWDVKLIWUHJ ELW UQJBFON 6DPSOLQJ 1RUPDOL]DWLRQ [ 51*FORFNGRPDLQ HQBRVF $QDORJ $QDORJ QRLVH QRLVH VRXUFH VRXUFH $QDORJQRLVHVRXUFH 06Y 9 34.3.2 RNG internal signals Table 260 describes a list of useful-to-know internal signals available at the RNG level, not at the STM32 product level (on pads). Table 260. RNG internal input/output signals 1186/3178 Signal name Signal type Description rng_it digital output rng_hclk2 digital input AHB2 clock rng_clk digital input RNG dedicated clock, asynchronous to rng_hclk2 RNG global interrupt request DocID029587 Rev 3 RM0433 34.3.3 True random number generator (RNG) Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. The RNG implements the entropy source model pictured on Figure 240, and provides three main functions to the application: • Collects the bitstring output of the entropy source box • Obtains samples of the noise source for validation purpose • Collects error messages from continuous health tests Figure 240. Entropy source model (UURU PHVVDJH +HDWK WHVWV 2XWSXW &RQGLWLRQLQJ RSWLRQDO 5DZGDWD 3RVWSURFHVVLQJ RSWLRQDO 2XWSXW 'LJLWL]DWLRQ UDZGDWDRUGLJLWL]HG QRLVHVRXUFH 1RLVH6RXUFH (QWURS\VRXUFH 06Y 9 The main components of the RNG are: • A source of physical randomness (analog noise sources) • A digitization stage for those analog noise sources • A stage delivering a cryptographically conditioned noise source • Output buffers, for both entropy source output (buffered) and noise source samples (also buffered) • A health monitoring block performing tests on the whole entropy source All those components are detailed below. Noise source The noise source is the component that contains the non-deterministic, entropy-providing activity that is ultimately responsible for the uncertainty associated with the bitstring output by the entropy source. It is composed of: • Two analog noise sources, each based on three XORed free-running ring oscillator outputs. It is possible to disable those analog oscillators to save power, as described in Section 34.4: RNG low-power usage. • A sampling stage of these outputs clocked by a dedicated clock input (rng_clk), delivering a 2-bit raw data output. DocID029587 Rev 3 1187/3178 1198 True random number generator (RNG) RM0433 The noise source sampling stage solves a metastability problem that may occurs due to the asynchronism between the noise source output signals and the dedicated rng_clk input. This noise source sampling is also independent to the AHB interface clock frequency (rng_hclk). Note: In Section 34.7: Entropy source validation recommended RNG clock frequencies are given. Post processing The sample values obtained from a true random noise source consist of 2-bit bitstrings. Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level. More specifically, for each of the two noise source bits the RNG takes half of the bits from the sampled noise source, and half of the bits from inverted sampled noise source. Thus, if the source generates more ‘1’ than ‘0’ (or the opposite), it is filtered Conditioning The conditioning component in the RNG is a deterministic function that increases the entropy rate of the resulting fixed-length bitstrings output (128-bit). The conditioning algorithm used is a block cipher based on AES CBC with a key length of 128 bits, generating 128 bits of random samples every 54x4 AHB clock cycles, as shown on Figure 241. Note: The latency during the RNG initialization is described in Section 34.6: RNG processing time. The raw data coming from the two digitized noise sources are interleaved together at the input of AES post-processing stage (raw bit1 + raw bit2 + raw bit1 + raw bit2 …). Also note that AES computations are triggered when at least 32 bits of raw data has been received and when output FIFO needs a refill. Thus the RNG output entropy is maximum when the RNG 128-bit FIFO is emptied by application after 64 RNG clock cycles. 1188/3178 DocID029587 Rev 3 RM0433 True random number generator (RNG) Figure 241. Random samples conditioning process $(6SRVWSURFHVVLQJ 5DZ GDWD 5DZ GDWD 5DZ GDWD 5DZ GDWD 5DZ GDWD 5DZ GDWD 5DZ GDWD 5DZ GDWD [ QHZELWV [ QHZELWV )URP [WR [ QHZELWV )URP [WR [ QHZELWV ,QSXWUHJ ,QSXWUHJ ,QSXWUHJ ,QSXWUHJ ELW ELW ELW ELW $(6 (QF $(6 (QF $(6 (QF ELW [[+&/. FORFNF\FOHV $(6 (QF ELW ELW 2XWSXWUHJ 2XWSXWUHJ 2XWSXWUHJ 2XWSXW),)2 2XWSXW),)2 2XWSXW),)2 ELWZRUGV ELWZRUGV ELWZRUGV [+&/. FORFNF\FOHV [+&/. FORFNF\FOHV 06Y9 The conditioning component is clocked by the faster AHB clock. Note: Two noise source bits can be loaded into the AES input buffer per RNG clock cycle. Output buffer A data output buffer can store up to four 32-bit words which have been output from the conditioning component (AES-CBC). When four words have been read from the output FIFO through the RNG_DR register, the content of the 128-bit conditioning output register is pushed into the output FIFO, and a new AES calculation is automatically started. Four new words are added to the conditioning output register 213 AHB clock cycles later (time to perform the AES computation). Whenever a random number is available through the RNG_DR register the DRDY flag transitions from “0” to “1”. This flag remains high until output buffer becomes empty after reading four words from the RNG_DR register. Note: When interrupts are enabled an interrupt is generated when this data ready flag transitions from “0” to “1”. Interrupt is then cleared automatically by the RNG as explained above. DocID029587 Rev 3 1189/3178 1198 True random number generator (RNG) RM0433 Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features: 1. 2. Behavior tests, applied to the entropy source at run-time – Repetition count test, flagging an error when: a) One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”) b) Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bits patterns (“01” or “10”) Vendor specific continuous test – Real-time “too slow” sampling clock detector, flagging an error when one RNG clock cycle (after divider) is smaller than AHB clock cycle divided by 32. The CECS and SECS status bits in the RNG_SR register indicate when an error condition is detected, as detailed in Section 34.3.7: Error management. Note: An interrupt can be generated when an error is detected. 34.3.4 RNG initialization The RNG simplified state machine is pictured on Figure 242 When a hardware reset occurs the following chain of events occurs: 1190/3178 1. The analog noise source is enabled, and logic immediately starts sampling the analog output, filling 128-bit conditioning shift register 2. The conditioning logic is enabled and AES-CBC post-processing context is initialized using two 128 noise source bits (128 bits are for the key). 3. The AES internal input data buffer is filled again with 128-bit and one AES postprocessing loop is performed. The output buffer is then filled with AES post processing result. 4. The output buffer is refilled automatically according to the RNG usage. DocID029587 Rev 3 RM0433 True random number generator (RNG) The associated initialization time can be found in Section 34.6: RNG processing time. Figure 242. RNG initialization overview >KDUGZDUHUHVHW@ 1RLVHVRXUFH HQDEOH (QWURS\VRXUFH JOREDOUHVHW &RQGLWLRQLQJ KDUGZDUHLQLW 'URSVDPSOHVWKHQ FKHFNDJDLQ *HQHUDWHVDPSOHV &RQWLQXRXVWHVW V QRW2. (UURUVWDWH 06Y9 34.3.5 RNG operation Normal operations To run the RNG using interrupts the following steps are recommended: 1. Enable the interrupts by setting the IE bit in the RNG_CR register. At the same time enable the RNG by setting the bit RNGEN=1. 2. An interrupt is now generated when a random number is ready or when an error occurs. Therefore at each interrupt, check that: – No error occurred. The SEIS and CEIS bits should be set to ‘0’ in the RNG_SR register. – A random number is ready. The DRDY bit must be set to ‘1’ in the RNG_SR register. – If above two conditions are true the content of the RNG_DR register can be read up to four consecutive times. If valid data is available in the AES output buffer, four additional words can be read by the application (in this case the DRDY bit will still be high). If one or both of above conditions are false, the RNG_DR register must not be read. If an error occurred error recovery sequence described in Section 34.3.7 shall be used. DocID029587 Rev 3 1191/3178 1198 True random number generator (RNG) RM0433 To run the RNG in polling mode following steps are recommended: 1. Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. 2. Read the RNG_SR register and check that: 3. Note: – No error occurred (the SEIS and CEIS bits should be set to ‘0’) – A random number is ready (the DRDY bit should be set to ‘1’) If above conditions are true read the content of the RNG_DR register up to four consecutive times. If valid data is available in the AES output buffer four additional words can be read by the application (in this case the DRDY bit will still be high). If one or both of above conditions are false, the RNG_DR register must not be read. If an error occurred error recovery sequence described in Section 34.3.7 shall be used. When data is not ready (DRDY=”0”) RNG_DR returns zero. Low-power operations If the power consumption is a concern to the application, low-power strategies can be used, as described in Section 34.4: RNG low-power usage on page 1193. Software post-processing No specific software post-processing/conditioning is required to meet AIS-31 approvals. If a NIST approved DRBG with 128 bits of security strength is required an approved random generator software must be built around the RNG true random number generator. Built-in health check functions are described in Section 34.3.3: Random number generation. 34.3.6 RNG clocking The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock. The AHB clock is used to clock the AHB banked registers and conditioning component. The RNG clock is used for noise source sampling. Recommended clock configurations are detailed in Section 34.7: Entropy source validation. Caution: When the CED bit in the RNG_CR register is set to “0”, the RNG clock frequency must be higher than AHB clock frequency divided by 32, otherwise the clock checker will flag a clock error (CECS or CEIS in the RNG_SR register) and the RNG will stop producing random numbers. See Section 34.3.1: RNG block diagram for details (AHB and RNG clock domains). 34.3.7 Error management In parallel to random number generation an health check block verifies the correct noise source behavior and the frequency of the RNG source clock as detailed in this section. Associated error state is also described. Clock error detection When the clock error detection is enabled (CED = 0) and If the RNG clock frequency is too low, the RNG stops generating random numbers and sets to “1” both the CEIS and CECS bits to indicate that a clock error occurred. In this case, the application should check that the RNG clock is configured correctly (see Section 34.3.6: RNG clocking) and then it must clear 1192/3178 DocID029587 Rev 3 RM0433 True random number generator (RNG) the CEIS bit interrupt flag. As soon as the RNG clock operates correctly, the CECS bit will be automatically cleared. The RNG operates only when the CECS flag is set to “0”. However note that the clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can still be used. Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy. If the error was detected during the initialization phase the whole initialization sequence will be automatically restarted by the RNG. The following sequence shall be used to fully recover from a seed error after the RNG initialization: 34.4 1. Clear the SEIS bit by writing it to “0”. 2. Read out 12 words from the RNG_DR register, and discard each of them in order to clean the pipeline. 3. Confirm that SEIS is still cleared. Random number generation is back to normal. RNG low-power usage If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set to “1” by setting the RNGEN bit to “0” in the RNG_CR register. As the AES post-processing logic and the output buffer remain operational while RNGEN=’0’ following features are available to software: • If there are valid words in the output buffer four random numbers can still be read from the RNG_DR register. • If there are valid bits in the AES output internal register four additional random numbers can be still be read from the RNG_DR register. If it is not the case the RNG must be reenabled by the application until at least 32 new bits have been collected from the noise source and a complete AES computation has been done. It corresponds to 16 RNG clock cycles to sample new bits, and 216 AHB clock cycles to run an AES round. When disabling the RNG the user deactivates all the analog seed generators, whose power consumption is given in the datasheet electrical characteristics section. The user also gates all the logic clocked by the RNG clock. Note that this strategy is adding latency before a random sample is available on the RNG_DR register, because of the RNG initialization time. If the RNG block is disabled during initialization (i.e. well before the DRDY bit rises for the first time), the initialization sequence will resume from where it was stopped when RNGEN bit is set to “1”. DocID029587 Rev 3 1193/3178 1198 True random number generator (RNG) 34.5 RM0433 RNG interrupts In the RNG an interrupt can be produced on the following events: • Data ready flag • Seed error, see Section 34.3.7: Error management • Clock error, see Section 34.3.7: Error management Dedicated interrupt enable control bits are available as shown in Table 261 Table 261. RNG interrupt requests Interrupt event Event flag Enable control bit Data ready flag DRDY IE Seed error flag SEIS IE Clock error flag CEIS IE The user can enable or disable the above interrupt sources individually by changing the mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the individual interrupt sources can be read from the RNG_SR register. Note: Interrupts are generated only when RNG is enabled. 34.6 RNG processing time The AES can produce four 32-bit random numbers every 4x54 AHB clock cycles, though more time is needed for the first set of random numbers after the device exits reset (see Section 34.3.4: RNG initialization). After enabling the RNG for the first time, random data is first available after either: • 128 RNG clock cycles + 426 AHB cycles, if fAHB < 160 MHz and fRNG = 48 MHz • 192 RNG clock cycles + 213 AHB cycles, if fAHB ≥ 160 MHz and fRNG = 48 MHz 34.7 Entropy source validation 34.7.1 Introduction In order to assess of the amount of entropy available from the RNG, STMicroelectronics has tested the RNG against AIS-31 PTG.2 set of tests. The results can be provided on demand or the customer can reproduce the measurements using the AIS reference software. The customer could also test the RNG against an older NIST SP800-22 set of tests. 34.7.2 Validation conditions STMicroelectronics has validated the RNG true random number generator in the following conditions: 1194/3178 • RNG clock rng_clk= 48 MHz (CED bit = ’0’ in RNG_CR register) and rng_clk = 400 kHz (CED bit = ‘1’ in RNG_CR register). • AHB clock rng_hclk= 216 MHz DocID029587 Rev 3 RM0433 34.7.3 True random number generator (RNG) Data collection In order to run statistical tests it is required to collect samples from the entropy source at raw data level as well as at the output of the entropy source. The RNG strategy is to use the same 32-bit buffer to output both samples, using the BYP bit in the RNG_CR register to bypass or not the conditioning stage. In other words if raw data needs to be captured by the application the following sequence is recommended: 1. Write in the RNG_CR register the bit RNGEN to “0” and the bit BYP to “1”. 2. Write in the RNG_CR register the bit RNGEN to “1” and the bit BYP to “1”. The raw samples are captured the same way as normal output samples. DocID029587 Rev 3 1195/3178 1198 True random number generator (RNG) 34.8 RM0433 RNG registers The RNG is associated with a control register, a data register and a status register. 34.8.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. BYP CED Res. IE RNGEN Res. Res. rw rw rw rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 BYP: Bypass mode enable This bit enables or disables the bypass of post-processing/conditioning logic. This feature is used for RNG validation. 0: Bypass mode is disabled. The noise source samples are post-processed and conditioned. 1: Bypass mode is enabled. The noise source samples are not post-processed nor conditioned and directly readable by the application. Writing this bit is taken into account only if RNGEN=0. Bit 5 CED: Clock error detection 0: Clock error detection is enable 1: Clock error detection is disable The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled. Bit 4 Reserved, must be kept at reset value. Bit 3 IE: Interrupt Enable 0: RNG Interrupt is disabled 1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=’1’, SEIS=’1’ or CEIS=’1’ in the RNG_SR register. Bit 2 RNGEN: True random number generator enable 0: True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. 1: True random number generator is enabled. Bits 1:0 Reserved, must be kept at reset value. 1196/3178 DocID029587 Rev 3 RM0433 True random number generator (RNG) 34.8.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. SEIS CEIS Res. Res. SECS CECS DRDY rc_w0 rc_w0 r r r Bits 31:7 Reserved, must be kept at reset value. Bit 6 SEIS: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to ‘0’. 0: No faulty sequence detected 1: At least one faulty sequence has been detected. See SECS bit description for details. An interrupt is pending if IE = ‘1’ in the RNG_CR register. Bit 5 CEIS: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to ‘0’. 0: The RNG clock is correct (fRNGCLK> fHCLK/32) 1: The RNG clock has been detected too slow (fRNGCLK< fHCLK/32) An interrupt is pending if IE = ‘1’ in the RNG_CR register. Bits 4:3 Reserved, must be kept at reset value. Bit 2 SECS: Seed error current status 0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: At least one of the following faulty sequence has been detected: – One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bit patterns (“01” or “10”) – Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bit patterns (“01” or “10”) Bit 1 CECS: Clock error current status 0: The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. 1: The RNG clock is too slow (fRNGCLK< fHCLK/32). Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to “0”. Bit 0 DRDY: Data Ready 0: The RNG_DR register is not yet valid, no random data is available. 1: The RNG_DR register contains valid random data. Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to ‘0’ until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=’0’ in the RNG_CR register). If IE=’1’ in the RNG_CR register, an interrupt is generated when DRDY=’1’. DocID029587 Rev 3 1197/3178 1198 True random number generator (RNG) 34.8.3 RM0433 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty. The content of this register is valid when DRDY=’1’, even if RNGEN=’0’. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RNDATA[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r RNDATA[15:0] r r Bits 31:0 RNDATA[31:0]: Random data 32-bit random data which are valid when DRDY=’1’. When DRDY=’0’ RNDATA value is zero. 34.8.4 RNG register map Table 262 gives the RNG register map and reset values. 0x000 RNG_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BYP CED Res. IE RNGEN Res. Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 262. RNG register map and reset map 0x004 0x008 1198/3178 0 0 0 0 RNG_SR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SEIS CEIS Res. Res. SECS CECS DRDY Reset value Reset value RNG_DR Reset value 0 0 0 0 0 RNDATA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 35 Cryptographic processor (CRYP) 35.1 Introduction The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES or AES algorithms. It is a fully compliant implementation of the following standards: • The data encryption standard (DES) and Triple-DES (TDES) as defined by Federal Information Processing Standards Publication (FIPS PUB 46-3, Oct 1999), and the American National Standards Institute (ANSI X9.52) • The advanced encryption standard (AES) as defined by Federal Information Processing Standards Publication (FIPS PUB 197, Nov 2001) Multiple key sizes and chaining modes are supported: • DES/TDES chaining modes ECB and CBC, supporting standard 56-bit keys with 8-bit parity per key • AES chaining modes ECB, CBC, CTR, GCM, GMAC, CCM for key sizes of 128, 192 or 256 bits The CRYP is a 32-bit AHB peripheral. It supports DMA transfers for incoming and outgoing data (two DMA channels are required). The peripheral also includes input and output FIFOs (each 8 words deep) for better performance. The CRYP peripheral provides hardware acceleration to AES and DES cryptographic algorithms packaged in STM32 cryptographic library. 35.2 CRYP main features • • • Compliant implementation of the following standards: – NIST FIPS publication 46-3, Data Encryption Standard (DES) – ANSI X9.52, Triple Data Encryption Algorithm Modes of Operation – NIST FIPS publication 197, Advanced Encryption Standard (AES) AES symmetric block cipher implementation – 128-bit data block processing – Support for 128-, 192- and 256-bit cipher key lengths – Encryption and decryption with multiple chaining modes: Electronic Code Book (ECB), Cipher Block Chaining (CBC), Counter mode (CTR), Galois Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Counter with CBC-MAC (CCM). – 14 (respectively 18) clock cycles for processing one 128-bit block of data with a 128-bit (respectively 256-bit) key in AES-ECB mode – Integrated key scheduler with its key derivation stage (ECB or CBC decryption only) DES/TDES encryption/decryption implementation – 64-bit data block processing – Support for 64-, 128- and 192-bit cipher key lengths (including parity) – Encryption and decryption with support of ECB and CBC chaining modes DocID029587 Rev 3 1199/3178 1268 Cryptographic processor (CRYP) • 1200/3178 RM0433 – Direct implementation of simple DES algorithms (a single key K1 is used) – 16 (respectively 64) clock cycles for processing one 64-bit block of data in DES (respectively TDES) ECB mode – Software implementation of ciphertext stealing Features common to DES/TDES and AES – AMBA AHB slave peripheral, accessible through 32-bit word single accesses only (otherwise an AHB bus error is generated, and write accesses are ignored) – 256-bit register for storing the cryptographic key (8x 32-bit registers) – 128-bit registers for storing initialization vectors (4× 32-bit) – 1x32-bit INPUT buffer associated with an internal IN FIFO of eight 32- bit words, corresponding to four incoming DES blocks or two AES blocks – 1x32-bit OUTPUT buffer associated with an internal OUT FIFO of eight 32-bit words, corresponding to four processed DES blocks or two AES blocks – Automatic data flow control supporting direct memory access (DMA) using two channels (one for incoming data, one for processed data). Single and burst transfers are supported. – Data swapping logic to support 1-, 8-, 16- or 32-bit data – Possibility for software to suspend a message if the cryptographic processor needs to process another message with higher priority (suspend/resume operation) DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 35.3 CRYP functional description 35.3.1 CRYP block diagram Figure 243 shows the block diagram of the cryptographic processor. VWDWXV FRQWURO $+% LQWHUIDFH &5<3B'287 &5<3B65 VZDSSLQJ GDWDRXW &5<3B',1 VZDSSLQJ ELW$+%EXV GDWDLQ [ELW ,1),)2 %DQNHG5HJLVWHUV PDLQ [ELW 287),)2 Figure 243. CRYP block diagram &5<3B&5 NH\ &5<3B.[ .H\ LY &5<3B,9[ ,9 $(6 &RUH $($ '(6 7'(6 &RUH '($ %DQNHG5HJLVWHUV VXVSHQGUHVXPH &5<3B*&0[ FU\SBKFON &6*&0&0[ 6DYH5HVWRUH %DQNHG5HJLVWHUV ,54 '0$ &5<3B,06&5 &5<3B5,6 &5<3B0,6 &5<3B'0$&5 FU\SBLQBGPD FU\SBRXWBGPD FU\SBLW '0$ LQWHUIDFH &RQWURO/RJLF ,54 LQWHUIDFH 06Y 9 35.3.2 CRYP internal signals Table 263 provides a list of useful-to-know internal signals available at cryptographic processor level and not at STM32 product level (on pads). DocID029587 Rev 3 1201/3178 1268 Cryptographic processor (CRYP) RM0433 Table 263. CRYP internal input/output signals 35.3.3 Signal name Signal type Description cryp_hclk digital input cryp_it digital output Cryptographic processor global interrupt request cryp_in_dma digital input/output IN FIFO DMA burst request/ acknowledge cryp_out_dma digital input/output OUT FIFO DMA burst request/ acknowledge (with single request for DES) AHB bus clock CRYP DES/TDES cryptographic core Overview The DES/Triple-DES cryptographic core consists of three components: • The DES Algorithm (DEA core) • Multiple keys (one for the DES algorithm, one to three for the TDES algorithm) • The initialization vector, which is used only in CBC mode The DES/Triple-DES cryptographic core provides two operating modes: • ALGODIR=0: Plaintext encryption using the key stored in the CRYP_Kx registers. • ALGODIR=1: Ciphertext decryption using the key stored in the CRYP_Kx registers. The operating mode is selected by programming the ALGODIR bit in the CRYP_CR register. Typical data processing Typical usage of the cryptographic processor in DES modes can be found inSection 35.3.10: CRYP DES/TDES basic chaining modes (ECB, CBC). Note: The outputs of the intermediate DEA stages are never revealed outside the cryptographic boundary, with the exclusion of the IV registers in CBC mode. DES keying and chaining modes The TDES allows three different keying options: • Three independent keys The first option specifies that all the keys are independent, that is, K1, K2 and K3 are independent. FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to this option as the Keying Option 1 and, to the TDES as 3-key TDES. • Two independent keys The second option specifies that K1 and K2 are independent and K3 is equal to K1, that is, K1 and K2 are independent, K3 = K1. FIPS PUB 46-3 – 1999 (and ANSI X9.52 1202/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) – 1998) refers to this second option as the Keying Option 2 and, to the TDES as 2-key TDES. • Three equal keys The third option specifies that K1, K2 and K3 are equal, that is: K1 = K2 = K3 FIPS PUB 46-3 – 1999 (and ANSI X9.52 – 1998) refers to the third option as the Keying Option 3. This “1-key” TDES is equivalent to single DES. The following chaining algorithms are supported by the DES hardware and can be selected through the ALGOMODE bits in the CRYP_CR register: • Electronic Code Book (ECB) • Cipher Block Chaining (CBC) These modes are described in details in Section 35.3.10: CRYP DES/TDES basic chaining modes (ECB, CBC). 35.3.4 CRYP AES cryptographic core Overview The AES cryptographic core consists of the following components: • The AES Algorithm (AEA core) • The Multiplier over a binary Galois field (GF2mul) • The key information • The initialization vector (IV) or Nonce information • Chaining algorithms logic (XOR, feedback/counter, mask) The AES core works on 128-bit data blocks of (four words) with 128-, 192- or 256-bit key lengths. Depending on the chaining mode, the peripheral requires zero or one 128-bit initialization vector (IV). The cryptographic peripheral features two operating modes: • ALGODIR=0: Plaintext encryption using the key stored in the CRYP_Kx registers. • ALGODIR=1: Ciphertext decryption using the key stored in the CRYP_Kx registers. When ECB and CBC chaining modes are selected, an initial key derivation process is automatically performed by the cryptographic peripheral. The operating mode is selected by programming the ALGODIR bit in the CRYP_CR register. Typical data processing A description of cryptographic processor typical usage in AES mode can be found in Section 35.3.11: CRYP AES basic chaining modes (ECB, CBC). Note: The outputs of the intermediate AEA stages is never revealed outside the cryptographic boundary, with the exclusion of the IV registers. DocID029587 Rev 3 1203/3178 1268 Cryptographic processor (CRYP) RM0433 AES chaining modes The following chaining algorithms are supported by the cryptographic processor and can be selected through the ALGOMODE bits in the CRYP_CR register: • Electronic Code Book (ECB) • Cipher Block Chaining (CBC) • Counter Mode (CTR) • Galois/Counter Mode (GCM) • Galois Message Authentication Code mode (GMAC) • Counter with CBC-MAC (CCM) A quick introduction on these chaining modes can be found in the following subsections. For detailed instructions, refer to Section 35.3.11: CRYP AES basic chaining modes (ECB, CBC) and onward. AES Electronic CodeBook (ECB) Figure 244. AES-ECB mode overview ECB is the simplest operating mode. There are no chaining operations, and no special initialization stage. The message is divided into blocks and each block is encrypted or decrypted separately. Note: 1204/3178 For decryption, a special key scheduling is required before processing the first block. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) AES Cipher block chaining (CBC) Figure 245. AES-CBC mode overview CBC operating mode chains the output of each block with the input of the following block. To make each message unique, an initialization vector is used during the first block processing. Note: For decryption,a special key scheduling is required before processing the first block. DocID029587 Rev 3 1205/3178 1268 Cryptographic processor (CRYP) RM0433 AES Counter mode (CTR) Figure 246. AES-CTR mode overview The CTR mode uses the AES core to generate a key stream; these keys are then XORed with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation. Note: 1206/3178 Unlike ECB and CBC modes, no key scheduling is required for the CTR decryption, since in this chaining scheme the AES core is always used in encryption mode for producing the counter blocks. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) AES Galois/Counter mode (GCM) Figure 247. AES-GCM mode overview In Galois/Counter mode (GCM), the plaintext message is encrypted, while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation Galois/Counter Mode (GCM) and GMAC. GCM mode is based on AES in counter mode for confidentiality. It uses a multiplier over a fixed finite field for computing the message authentication code. It requires an initial value and a particular 128-bit block at the end of the message. AES Galois Message Authentication Code (GMAC) Figure 248. AES-GMAC mode overview DocID029587 Rev 3 1207/3178 1268 Cryptographic processor (CRYP) RM0433 Galois Message Authentication Code (GMAC) allows authenticating a message and generating the corresponding message authentication code (MAC). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation Galois/Counter Mode (GCM) and GMAC. GMAC is similar to Galois/Counter mode (GCM), except that it is applied on a message composed only by clear-text authenticated data (i.e. only header, no payload). AES Counter with CBC-MAC (CCM) Figure 249. AES-CCM mode overview In Counter with Cipher Block Chaining-Message Authentication Code (CCM), the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and the corresponding MAC (also known as tag). It is described by NIST in Special Publication 800-38C, Recommendation for Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality. CCM mode is based on AES in counter mode for confidentiality and it uses CBC for computing the message authentication code. It requires an initial value. Like GCM CCM chaining mode, AES-CCM mode can be applied on a message composed only by cleartext authenticated data (i.e. only header, no payload). Note that this way of using CCM is not called CMAC (it is not similar to GCM/GMAC), and its usage is not recommended by NIST. 1208/3178 DocID029587 Rev 3 RM0433 35.3.5 Cryptographic processor (CRYP) CRYP procedure to perform a cipher operation Introduction To understand how the cryptographic peripheral operates, a typical cipher operation is described below. For the detailed peripheral usage according to the cipher mode, refer to the specific section, e.g. Section 35.3.11: CRYP AES basic chaining modes (ECB, CBC). The flowcharts shown in Figure 250 and Figure 251 describe the way STM32 cryptographic library implements DES (respectively AES) algorithm. The cryptographic processor accelerates the execution of the following cryptographic algorithms: Note: • AES-128, AES-192, AES-256 bit in the following modes: ECB, CBC, CTR, CCM, GCM • DES, TripleDES in the following modes: ECB, CBC For more details on the cryptographic library, refer to use manual UM1924 “STM32 crypto library” available from www.st.com Figure 250. STM32 cryptolib DES/TDES flowcharts (QFU\SWLRQ 'HFU\SWLRQ %HJLQ %HJLQ '(6B[HQFU\SWLQLW '(6B[GHFU\SWLQLW (UURUVWDWXV (UURUVWDWXV VXFFHVV VXFFHVV '(6B[HQFU\SW DSSHQG $(6B[GHFU\SW DSSHQG GDWDWRDSSHQG (UURUVWDWXV GDWDWRDSSHQG (UURUVWDWXV VXFFHVV VXFFHVV '(6B[HQFU\SW ILQLVK '(6B[GHFU\SW ILQLVK (UURUVWDWXV (UURUVWDWXV VXFFHVV VXFFHVV (QG (QG 06Y9 DocID029587 Rev 3 1209/3178 1268 Cryptographic processor (CRYP) RM0433 Figure 251. STM32 cryptolib AES flowchart examples (QFU\SWLRQ $XWKHQWLFDWHG'HFU\SWLRQ %HJLQ %HJLQ $(6B[HQFU\SWLQLW $(6B[GHFU\SWLQLW (UURUVWDWXV (UURUVWDWXV VXFFHVV VXFFHVV $(6B[HQFU\SW DSSHQG $(6B[KHDGHU DSSHQG GDWDWRDSSHQG (UURUVWDWXV GDWDWRDSSHQG (UURUVWDWXV VXFFHVV $(6B[GHFU\SW DSSHQG GDWDWRDSSHQG (UURUVWDWXV VXFFHVV VXFFHVV $(6B[HQFU\SW ILQLVKILQDO $(6B[GHFU\SW ILQLVKILQDO (UURUVWDWXV (UURUVWDWXV VXFFHVV VXFFHVV (QG 0$&7DJ FRPSDULVRQ (QG 06Y9 CRYP initialization 1. 1210/3178 Initialize the cryptographic processor. The order of operations is not important except for AES-ECB and AES-CBC decryption, where the key preparation requires a specific sequence. a) Disable the cryptographic processor by setting to 0 the CRYPEN bit in the CRYP_CR register. b) Configure the key size (128-, 192- or 256-bit, in the AES only) with the KEYSIZE bits in the CRYP_CR register. c) Write the symmetric key into the CRYP_KxL/R registers (2 to 8 registers to be written depending on the algorithm). d) Configure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE bits in the CRYP_CR register. e) In case of decryption in AES-ECB or AES-CBC mode, prepare the key that has been written. First configure the key preparation mode by setting the ALGOMODE bits to 0b111 in the CRYP_CR register. Then write the CRYPEN bit to 1: the BUSY DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) bit is set automatically. Wait until BUSY returns to 0 (CRYPEN is automatically cleared as well): the key is prepared for decryption. 2. f) Configure the algorithm and chaining with the ALGOMODE bits in the CRYP_CR register. g) Configure the direction (encryption/decryption) through the ALGODIR bit in the CRYP_CR register. h) When it is required (e.g. CBC or CTR chaining modes), write the initialization vectors into the CRYP_IVxL/R register. Flush the IN and OUT FIFOs by writing the FFLUSH bit to 1 in the CRYP_CR register. Preliminary warning for all cases If the ECB or CBC mode is selected and data are not a multiple of 64 bits (for DES) or 128 bits (for AES), the second and the last block management is more complex than the sequences below. Refer to Section 35.3.8: CRYP stealing and data padding for more details. Appending data using the CPU in polling mode 1. Enable the cryptographic processor by setting to 1 the CRYPEN bit in the CRYP_CR register. 2. Write data in the IN FIFO (one block or until the FIFO is full). 3. Repeat the following sequence until the second last block of data has been processed: a) Wait until the not-empty-flag OFNE is set to 1, then read the OUT FIFO (one block or until the FIFO is empty). b) Wait until the not-full-flag IFNF is set to 1, then write the IN FIFO (one block or until the FIFO is full) except if it is the last block. 4. The BUSY bit is set automatically by the cryptographic processor. At the end of the processing, the BUSY bit returns to 0 and both FIFOs are empty (IN FIFO empty flag IFEM=1 and OUT FIFO not empty flag OFNE=0). 5. If the next processing block is the last block, the CPU must pad (when applicable) the data with zeroes to obtain a complete block 6. When the operation is complete, the cryptographic processor can be disabled by clearing the CRYPEN bit in CRYP_CR register. Appending data using the CPU in interrupt mode 1. Enable the interrupts by setting the INIM and OUTIM bits in the CRYP_IMSCR register. 2. Enable the cryptographic processor by setting to 1 the CRYPEN bit in the CRYP_CR register. 3. 4. In the interrupt service routine that manages the input data: a) If the last block is being loaded, the CPU must pad (when applicable) the data with zeroes to have a complete block. Then load the block into the IN FIFO. b) If it is not the last block, load the data into the IN FIFO. You can load only one block (2 words for DES, 4 words for AES), or load data until the FIFO is full. c) In all cases, after the last word of data has been written, disable the interrupt by clearing the INIM interrupt mask. In the interrupt service routine that manages the input data: DocID029587 Rev 3 1211/3178 1268 Cryptographic processor (CRYP) RM0433 a) Read the output data from the OUT FIFO. You can read only one block (2 words for DES, 4 words for AES), or read data until the FIFO is empty. b) When the last word has been read, INIM and BUSY bits are set to 0 and both FIFOs are empty (IFEM=1 and OFNE=0). You can disable the interrupt by clearing the OUTIM bit, and disable the peripheral by clearing the CRYPEN bit. c) If you read the last block of cleartext data (i.e. decryption), optionally discard the data that is not part of message/payload. Appending data using the DMA 1. Prepare the last block of data by optionally padding it with zeroes to have a complete block. 2. Configure the DMA controller to transfer the input data from the memory and transfer the output data from the peripheral to the memory, as described in Section 35.3.19: CRYP DMA interface. The DMA should be configured to set an interrupt on transfer completion to indicate that the processing is complete. 3. Enable the cryptographic processor by setting to 1 the CRYPEN bit in CRYP_CR register, then enable the DMA IN and OUT requests by setting to 1 the DIEN and DOEN bits in the CRYP_DMACR register. 4. All the transfers and processing are managed by the DMA and the cryptographic processor. The DMA interrupt indicates that the processing is complete. Both FIFOs are normally empty and BUSY flag is set 0. Caution: It is important that DMA controller empties the cryptographic processor output FIFO before filling up the cryptographic processor input FIFO. To achieve this, the DMA controller should be configured so that the transfer from the cryptographic peripheral to the memory has a higher priority than the transfer from the memory to the cryptographic peripheral. 35.3.6 CRYP busy state The cryptographic processor is busy and processing data (BUSY set to 1 in CRYP_SR register) when all the conditions below are met: • CRYPEN = 1 in CRYP_CR register. • There are enough data in the input FIFO (at least two words for the DES or TDES algorithm mode, four words for the AES algorithm mode). • There is enough free-space in the output FIFO (at least two word locations for DES, four for AES). Write operations to the CRYP_Kx(L/R)R key registers, to the CRYP_IVx(L/R)R initialization registers, or to bits [9:2] of the CRYP_CR register, are ignored when cryptographic processor is busy (i.e. the registers are not modified). It is thus not possible to modify the configuration of the cryptographic processor while it is processing a data block. It is possible to clear the CRYPEN bit while BUSY bit is set to 1. In this case the ongoing DES/TDES or AES processing first completes (i.e. the word results are written to the output FIFO) before the BUSY bit is cleared by hardware. Note: If the application needs to suspend a message to process another one with a higher priority, refer to Section 35.3.9: CRYP suspend/resume operations When a block is being processed in DES or TDES mode, if the output FIFO becomes full and the input FIFO contains at least one new block, then the new block is popped off the 1212/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) input FIFO and the BUSY bit remains high until there is enough space to store this new block into the output FIFO. 35.3.7 Preparing the CRYP AES key for decryption When performing an AES ECB or CBC decryption, the AES key has to be prepared, i.e. a complete key schedule of encryption is required before performing the decryption. In other words, the key in the last round of encryption must be used as the first round key for decryption. This preparation is not required in any other AES modes than AES ECB or CBC decryption. If the application software stores somehow the initial key prepared for decryption, the key scheduling operation can be performed only once for all the data to be decrypted with a given cipher key. Note: The latency of the key preparation operation is 14, 16 or 18 clock cycles depending on the key size (128-, 192- or 256-bit). The CRYP key preparation process is performed as follow: 1. Write the encryption key to K0...K3 key registers. 2. Program ALGOMODE bits to 0b111 in CRYP_CR. Writing this value when CRYPEN is et to 1 immediately starts an AES round for key preparation. The BUSY bit in the CRYP_SR register is set to 1. 3. When the key processing is complete, the resulting key is copied back into the K0...K3 key registers, and the BUSY bit is cleared. Note: As the CRYPEN bitfield is reset by hardware at the end of the key preparation, the application software must set it again for the next operation. 35.3.8 CRYP stealing and data padding When using DES or AES algorithm in ECB or CBC modes to manage messages that are not multiple of the block size (64 bits for DES, 128 bits for AES), use ciphertext stealing techniques such as those described in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation: Three Variants of Ciphertext Stealing for CBC Mode. Since the cryptographic processor does not implement such techniques, the last two blocks must be handled in a special way by the application. Note: Ciphertext stealing techniques are not documented in this reference manual. Similarly, when the AES algorithm is used in other modes than ECB or CBC, incomplete input data blocks (i.e. block shorter than 128 bits) have to be padded with zeroes by the application prior to encryption (i.e. extra bits should be appended to the trailing end of the data string). After decryption, the extra bits have to be discarded. The cryptographic processor does not implement automatic data padding operation to the last block, so the application should follow the recommendation given in Section 35.3.5: CRYP procedure to perform a cipher operation to manage messages that are not multiple of 128 bits. Note: Padding data are swapped in a similar way as normal data, according to the DATATYPE field in CRYP_CR register (see Section 35.3.16: CRYP data registers and data swapping for details). DocID029587 Rev 3 1213/3178 1268 Cryptographic processor (CRYP) RM0433 With this version of cryptographic processor, a special workaround is required in order to properly compute authentication tags while doing a GCM encryption or a CCM decryption with the last block of payload size inferior to 128 bits. This workaround is described below: • • 1214/3178 During GCM encryption payload phase and before inserting a last plaintext block smaller than 128 bits, the application has to follow the below sequence: a) Disable the peripheral by setting the CRYPEN bit to 0 in CRYP_CR. b) Load CRYP_IV1R register content in a temporary variable. Decrement the value by 1 and reinsert the result in CRYP_IV1R register. c) Change the AES mode to CTR mode by writing the ALGOMODE bitfield to 0b0110 in the CRYP_CR register. a) Set the CRYPEN bit to 1 in CRYP_CR to enable again the peripheral. b) Pad the last block (smaller than 128 bits) with zeros to have a complete block of 128 bits, then write it into CRYP_DIN register. c) Upon encryption completion, read the 128-bit generated ciphertext from the CRYP_DOUT register and store it as intermediate data. d) Change again the AES mode to GCM mode by writing the ALGOMODE bitfield to 0b1000 in the CRYP_CR register. e) Select Final phase by writing the GCM_CCMPH bitfield to 0b11 in the CRYP_CR register. f) In the intermediate data, set to 0 the bits corresponding to the padded bits of the last payload block then insert the resulting data to CRYP_DIN register. g) When the operation is complete, read data from CRYP_DOUT. These data have to be discarded. h) Apply the normal Final phase as described in Section 35.3.13: CRYP AES Galois/counter mode (GCM). During CCM decryption payload phase and before inserting a last ciphertext block smaller than 128 bits, the application has to follow the below sequence: a) To disable the peripheral, set the CRYPEN bit to 0 in CRYP_CR. b) Load CRYP_IV1R in a temporary variable (named here IV1temp). c) Load CRYP_CSGCMCCM0R, CRYP_CSGCMCCM1R, CRYP_CSGCMCCM2R, and CRYP_CSGCMCCM3R registers content from LSB to MSB in 128-bit temporary variable (named here temp1). d) Load in CRYP_IV1R the content previously stored in IV1temp. e) Change the AES mode to CTR mode by writing the ALGOMODE bitfield to 0b0110 in the CRYP_CR register. a) Set the CRYPEN bit to 1 in CRYP_CR to enable again the peripheral. b) Pad the last block (smaller than 128 bits) with zeros to have a complete block of 128 bits, then write it to CRYP_DIN register. c) Upon decryption completion, read the 128-bit generated data from DOUT register, and store them as intermediate data (here named intdata_o). d) Save again CRYP_CSGCMCCM0R, CRYP_CSGCMCCM1R, CRYP_CSGCMCCM2R, and CRYP_CSGCMCCM3R registers content, from LSB to MSB, in a new 128-bit temporary variable (named here temp2). e) Change again the AES mode to CCM mode by writing the ALGOMODE bitfield to 0b1001 in the CRYP_CR register. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) f) Select the header phase by writing the GCM_CCMPH bitfield to 0b01 in the CRYP_CR register. g) In the intermediate data (intdata_o which was generated with CTR), set to 0 the bits corresponding to the padded bits of the last payload block, XOR with temp1, XOR with temp2, and insert the resulting data into CRYP_DIN register. In other words: CRYP_DIN=(intdata_o AND mask) XOR temp1 XOR temp2. 35.3.9 h) Wait for operation completion. i) Apply the normal Final phase as described in Section 35.3.15: CRYP AES Counter with CBC-MAC (CCM). CRYP suspend/resume operations A message can be suspended if another message with a higher priority has to be processed. When this highest priority message has been sent, the suspended message can be resumed in both encryption or decryption mode. Suspend/resume operations do not break the chaining operation and the message processing can be resumed as soon as cryptographic processor is enabled again to receive the next data block. Figure 252 gives an example of suspend.resume operation: message 1 is suspended in order to send a higher priority message (message 2), which is shorter than message 1 (AES algorithm). Figure 252. Example of suspend mode management 0HVVDJH 0HVVDJH ELWEORFN ELWEORFN 1HZKLJKHU SULRULW\PHVVDJH WREHSURFHVVHG ELWEORFN &5<3VXVSHQG VHTXHQFH ELWEORFN ELWEORFN ELWEORFN ELWEORFN &5<3UHVXPH VHTXHQFH ELWEORFN 06Y9 A detailed description of suspend/resume operations can be found in each AES mode section. DocID029587 Rev 3 1215/3178 1268 Cryptographic processor (CRYP) 35.3.10 RM0433 CRYP DES/TDES basic chaining modes (ECB, CBC) Overview FIPS PUB 46-3 – 1999 (and ANSI X9.52-1998) provides a thorough explanation of the processing involved in the four operation modes supplied by the DES computing core: TDES-ECB encryption, TDES-ECB decryption, TDES-CBC encryption and TDES-CBC decryption. This section only gives a brief explanation of each mode. DES/TDES-ECB encryption Figure 253 illustrates the encryption in DES and TDES Electronic CodeBook (DES/TDESECB) mode. This mode is selected by writing in ALGOMODE to 0b000 and ALGODIR to 0 in CRYP_CR. Figure 253. DES/TDES-ECB mode encryption ). &)&/ PLAINTEXT 0 0 BITS $!4!490% SWAPPING $%! ENCRYPT + $%! DECRYPT + + $%! ENCRYPT / BITS $!4!490% SWAPPING # BITS /54 &)&/ CIPHERTEXT # AIB 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. A 64-bit plaintext data block (P) is used after bit/byte/half-word as the input block (I). The input block is processed through the DEA in the encrypt state using K1. The output of this process is fed back directly to the input of the DEA where the DES is performed in the decrypt state using K2. The output of this process is fed back directly to the input of the DEA where the DES is performed in the encrypt state using K3. The resultant 64-bit output block (O) is used, after bit/byte/half-word swapping, as ciphertext (C) and it is pushed into the OUT FIFO. Note: For more information on data swapping, refer to Section 35.3.16: CRYP data registers and data swapping. Detailed DES/TDES encryption sequence can be found in Section 35.3.5: CRYP procedure to perform a cipher operation. 1216/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) DES/TDES-ECB mode decryption Figure 254 illustrates the decryption in DES and TDES Electronic CodeBook (DES/TDESECB) mode. This mode is selected by writing ALGOMODE to 0b000 and ALGODIR to 1 in CRYP_CR. Figure 254. DES/TDES-ECB mode decryption ). &)&/ CIPHERTEXT # # BITS $!4!490% SWAPPING ) BITS $%! DECRYPT + $%! ENCRYPT + + $%! DECRYPT / BITS $!4!490% SWAPPING 0 BITS /54 &)&/ PLAINTEXT 0 -36 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. A 64-bit ciphertext block (C) is used, after bit/byte/half-word swapping, as the input block (I). The keying sequence is reversed compared to that used in the encryption process. The input block is processed through the DEA in the decrypt state using K3. The output of this process is fed back directly to the input of the DEA where the DES is performed in the encrypt state using K2. The new result is directly fed to the input of the DEA where the DES is performed in the decrypt state using K1. The resultant 64-bit output block (O), after bit/byte/half-word swapping, produces the plaintext (P). Note: For more information on data swapping refer to Section 35.3.16: CRYP data registers and data swapping. Detailed DES/TDES encryption sequence can be found in Section 35.3.5: CRYP procedure to perform a cipher operation. DocID029587 Rev 3 1217/3178 1268 Cryptographic processor (CRYP) RM0433 DES/TDES-CBC encryption Figure 255 illustrates the encryption in DES and TDES Cipher Block Chaining (DES/TDESECB) mode. This mode is selected by writing in ALGOMODE to 0b001 and ALGODIR to 0 in CRYP_CR. Figure 255. DES/TDES-CBC mode encryption ). &)&/ PLAINTEXT 0 0 BITS $!4!490% !(" DATA WRITE BEFORE #290 IS ENABLED SWAPPING 0S BITS )6,2 ) BITS $%! ENCRYPT + / IS WRITTEN BACK INTO )6 AT THE SAME TIME AS IT IS PUSHED INTO THE /54 &)&/ $%! DECRYPT + + $%! ENCRYPT / BITS $!4!490% SWAPPING # BITS /54 &)&/ CIPHERTEXT # AIB K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: initialization vectors. This mode begins by dividing a plaintext message into 64-bit data blocks. In TCBC encryption, the first input block (I1), obtained after bit/byte/half-word swapping, is formed by exclusive-ORing the first plaintext data block (P1) with a 64-bit initialization vector IV (I1 = IV ⊕ P1). The input block is processed through the DEA in the encrypt state using K1. The output of this process is fed back directly to the input of the DEA, which performs the DES in the decrypt state using K2. The output of this process is fed directly to the input of the DEA, which performs the DES in the encrypt state using K3. The resultant 64-bit output block (O1) is used directly as the ciphertext (C1), that is, C1 = O1. This first ciphertext block is then exclusive-ORed with the second plaintext data block to produce the second input block, (I2) = (C1 ⊕ P2). Note that I2 and P2 now refer to the second block. The second input block is processed through the TDEA to produce the second ciphertext block. This encryption process continues to “chain” successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted. If the message does not consist of an integral number of data blocks, then the final partial data block should be encrypted in a manner specified for the application. 1218/3178 DocID029587 Rev 3 RM0433 Note: Cryptographic processor (CRYP) For more information on data swapping refer to Section 35.3.16: CRYP data registers and data swapping. Detailed DES/TDES encryption sequence can be found in Section 35.3.5: CRYP procedure to perform a cipher operation. DES/TDES-CBC decryption Figure 255 illustrates the decryption in DES and TDES Cipher Block Chaining (DES/TDESECB) mode. This mode is selected by writing ALGOMODE to 0b001 and ALGODIR to 1 in CRYP_CR. Figure 256. DES/TDES-CBC mode decryption ). &)&/ CIPHERTEXT # # BITS $!4!490% SWAPPING ) BITS ) IS WRITTEN BACK INTO )6 AT THE SAME TIME AS 0 IS PUSHED INTO THE /54 &)&/ $%! DECRYPT + $%! ENCRYPT + + !(" DATA WRITE BEFORE #290 IS ENABLED $%! DECRYPT / BITS )6,2 0S BITS $!4!490% SWAPPING 0 BITS /54 &)&/ PLAINTEXT 0 -36 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: initialization vectors. In this mode the first ciphertext block (C1) is used directly as the input block (I1). The keying sequence is reversed compared to that used for the encrypt process. The input block is processed through the DEA in the decrypt state using K3. The output of this process is fed directly to the input of the DEA where the DES is processed in the encrypt state using K2. This resulting value is directly fed to the input of the DEA where the DES is processed in the decrypt state using K1. The resulting output block is exclusive-ORed with the IV (which must be the same as that used during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV). The second ciphertext block is then used as the next input block and is processed through the TDEA. The resulting output block is exclusive-ORed with the first ciphertext block to produce the second plaintext data block (P2 = O2 ⊕ C1). Note that P2 and O2 refer to the second block of data. DocID029587 Rev 3 1219/3178 1268 Cryptographic processor (CRYP) RM0433 The DES/TDES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted. Ciphertext representing a partial data block must be decrypted in a manner specified for the application. Note: For more information on data swapping refer to Section 35.3.16: CRYP data registers and data swapping. Detailed DES/TDES encryption sequence can be found in Section 35.3.5: CRYP procedure to perform a cipher operation. DES/TDES suspend/resume operations in ECB/CBC modes Before interrupting the current message, the user application must respect the following steps: Note: 1. If DMA is used, stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in the CRYP_DMACR register. 2. Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR) and the BUSY bit is cleared. Alternatively, as the input FIFO can contain up to four unprocessed DES blocks, the application could decide for real-time reason to interrupt the cryptographic processing without waiting for the IN FIFO to be empty. In this case, the alternative is: a) Wait until OUT FIFO is empty (OFNE=0). b) Read back the data loaded in the IN FIFO that have not been processed and save them in the memory until the IN FIFO is empty. 3. If DMA is used stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN bit in the CRYP_DMACR register. 4. Disable the cryptographic processor by setting the CRYPEN bit to 0 in CRYP_CR, then save the current configuration (bits [9:2] in the CRYP_CR register). If CBC mode is selected, save the initialization vector registers, since CRYP_IVx registers have changed from initial values during the data processing. Key registers do not need to be saved as the original key value is known by the application. 5. If DMA is used, save the DMA controller status (such as the pointers to IN and OUT data transfers, number of remaining bytes). To resume message processing, the user application must respect the following sequence: 1220/3178 1. If DMA is used, reconfigure the DMA controller to complete the rest of the FIFO IN and FIFO OUT transfers. 2. Make sure the cryptographic processor is disabled by reading the CRYPEN bit in CRYP_CR (it must be 0). 3. Configure again the cryptographic processor with the initial setting in CRYP_CR, as well as the key registers using the saved configuration. 4. If the CBC mode is selected, restore CRYP_IVx registers using the saved configuration. 5. Optionally, write the data that were saved during context saving into the IN FIFO. 6. Enable the cryptographic processor by setting the CRYPEN bit to 1. 7. If DMA is used, enable again DMA requests for the cryptographic processor, by setting to 1 the DIEN and DOEN bits in the CRYP_DMACR register. DocID029587 Rev 3 RM0433 35.3.11 Cryptographic processor (CRYP) CRYP AES basic chaining modes (ECB, CBC) Overview FIPS PUB 197 (November 26, 2001) provides a thorough explanation of the processing involved in the four basic operation modes supplied by the AES computing core: AES-ECB encryption, AES-ECB decryption, AES-CBC encryption and AES-CBC decryption. This section only gives a brief explanation of each mode. AES ECB encryption Figure 257 illustrates the AES Electronic codebook (AES-ECB) mode encryption. This mode is selected by writing ALGOMODE to 0b100 and ALGODIR to 0 in CRYP_CR. Figure 257. AES-ECB mode encryption ). &)&/ PLAINTEXT 0 0 BITS $!4!490% SWAPPING ) BITS OR + !%! ENCRYPT $!4!490% SWAPPING # BITS /54 &)&/ CIPHERTEXT # AIB 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. 2. If Key size = 128: Key = [K3 K2]. If Key size = 192: Key = [K3 K2 K1] If Key size = 256: Key = [K3 K2 K1 K0]. In this mode a 128- bit plaintext data block (P) is used after bit/byte/half-word swapping as the input block (I). The input block is processed through the AEA in the encrypt state using the 128, 192 or 256-bit key. The resultant 128-bit output block (O) is used after bit/byte/halfword swapping as ciphertext (C). It is then pushed into the OUT FIFO. For more information on data swapping refer to Section 35.3.16: CRYP data registers and data swapping. DocID029587 Rev 3 1221/3178 1268 Cryptographic processor (CRYP) RM0433 AES ECB decryption Figure 258 illustrates the AES Electronic codebook (AES-ECB) mode decryption. This mode is selected by writing in ALGOMODE to 0b100 and ALGODIR to 1 in CRYP_CR. Figure 258. AES-ECB mode decryption ). &)&/ CIPHERTEXT # # BITS $!4!490% OR + SWAPPING ) BITS !%! DECRYPT / BITS $!4!490% SWAPPING 0 BITS /54 &)&/ PLAINTEXT 0 -36 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. 2. If Key size = 128 => Key = [K3 K2]. If Key size = 192 => Key = [K3 K2 K1] If Key size = 256 => Key = [K3 K2 K1 K0]. To perform an AES decryption in ECB mode, the secret key has to be prepared (it is necessary to execute the complete key schedule for encryption) by collecting the last round key, and using it as the first round key for the decryption of the ciphertext. This preparation phase is computed by the AES core. Refer to Section 35.3.7: Preparing the CRYP AES key for decryption for more details on how to prepare the key. When the key preparation is complete, the decryption proceed as follow: a 128-bit ciphertext block (C) is used after bit/byte/half-word swapping as the input block (I). The keying sequence is reversed compared to that of the encryption process. The resultant 128-bit output block (O), after bit/byte or half-word swapping, produces the plaintext (P). The AESCBC decryption process continues in this manner until the last complete ciphertext block has been decrypted. For more information on data swapping refer to Section 35.3.16: CRYP data registers and data swapping. 1222/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) AES CBC encryption Figure 259 illustrates the AES Cipher block chaining (AES-CBC) mode encryption. This mode is selected by writing ALGOMODE to 0b101 and ALGODIR to 0 in CRYP_CR. Figure 259. AES-CBC mode encryption ). &)&/ PLAINTEXT 0 0 BITS $!4!490% !(" DATA WRITE BEFORE #290 IS ENABLED SWAPPING 0S BITS )6 ;)6 )6= + ) BITS OR !%! ENCRYPT / IS WRITTEN BACK INTO )6 AT THE SAME TIME AS IT IS PUSHED INTO THE /54 &)&/ / BITS $!4!490% SWAPPING # BITS /54 &)&/ CIPHERTEXT # AIB 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: Initialization vectors. 2. IVx=[IVxR IVxL], R=right, L=left. 3. If Key size = 128 => Key = [K3 K2]. If Key size = 192 => Key = [K3 K2 K1] If Key size = 256 => Key = [K3 K2 K1 K0]. In this mode the first input block (I1) obtained after bit/byte/half-word swapping is formed by exclusive-ORing the first plaintext data block (P1) with a 128-bit initialization vector IV (I1 = IV ⊕ P1). The input block is processed through the AEA in the encrypt state using the 128-, 192- or 256-bit key (K0...K3). The resultant 128-bit output block (O1) is used directly as ciphertext (C1), that is, C1 = O1. This first ciphertext block is then exclusive-ORed with the second plaintext data block to produce the second input block, (I2) = (C1 ⊕ P2). Note that I2 and P2 now refer to the second block. The second input block is processed through the AEA to produce the second ciphertext block. This encryption process continues to “chain” successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted. If the message does not consist of an integral number of data blocks, then the final partial data block should be encrypted in a manner specified for the application, as explained in Section 35.3.8: CRYP stealing and data padding. For more information on data swapping, refer to Section 35.3.16: CRYP data registers and data swapping. DocID029587 Rev 3 1223/3178 1268 Cryptographic processor (CRYP) RM0433 AES CBC decryption Figure 260 illustrates the AES Cipher block chaining (AES-CBC) mode decryption. This mode is selected by writing ALGOMODE to 0b101 and ALGODIR to 1 in CRYP_CR. Figure 260. AES-CBC mode decryption ). &)&/ CIPHERTEXT # # BITS $!4!490% + SWAPPING ) BITS OR !%! DECRYPT ) IS WRITTEN BACK INTO )6 AT THE SAME TIME AS 0 IS PUSHED INTO THE /54 &)&/ !(" DATA WRITE BEFORE #290 IS ENABLED )6 ;)6 )6= $!4!490% / BITS 0S BITS SWAPPING 0 BITS /54 &)&/ PLAINTEXT 0 -36 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: Initialization vectors. 2. IVx=[IVxR IVxL], R=right, L=left. 3. If Key size = 128 => Key = [K3 K2]. If Key size = 192 => Key = [K3 K2 K1] If Key size = 256 => Key = [K3 K2 K1 K0]. In CBC mode, like in ECB mode, the secret key must be prepared to perform an AES decryption. Refer to Section 35.3.7: Preparing the CRYP AES key for decryption for more details on how to prepare the key. When the key preparation process is complete, the decryption proceeds as follow: the first 128-bit ciphertext block (C1) is used directly as the input block (I1). The input block is processed through the AEA in the decrypt state using the 128-, 192- or 256-bit key. The resulting output block is exclusive-ORed with the 128-bit initialization vector IV (which must be the same as that used during encryption) to produce the first plaintext block (P1 = O1 ⊕ IV). The second ciphertext block is then used as the next input block and is processed through the AEA. The resulting output block is exclusive-ORed with the first ciphertext block to produce the second plaintext data block (P2 = O2 ⊕ C1). Note that P2 and O2 refer to the second block of data. The AES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted. 1224/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Ciphertext representing a partial data block must be decrypted in a manner specified for the application, as explained in Section 35.3.8: CRYP stealing and data padding. For more information on data swapping, refer to Section 35.3.16: CRYP data registers and data swapping. AES suspend/resume operations in ECB/CBC modes Before interrupting the current message, the user application must respect the following sequence: Note: 1. If DMA is used, stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in the CRYP_DMACR register. 2. Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR) and the BUSY bit is cleared. 3. If DMA is used, stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN bit in the CRYP_DMACR register. 4. Disable the CRYP by setting the CRYPEN bit to 0 in CRYP_CR, then save the current configuration (bits [9:2] in the CRYP_CR register). If ECB mode is not selected, save the initialization vector registers, because CRYP_IVx registers have changed from initial values during the data processing. Key registers do not need to be saved as the original key value is known by the application. 5. If DMA is used, save the DMA controller status (such as pointers to IN and OUT data transfers, number of remaining bytes). To resume message processing, the user application must respect the following sequence: 1. If DMA is used, reconfigure the DMA controller to complete the rest of the FIFO IN and FIFO OUT transfers. 2. Make sure the cryptographic processor is disabled by reading the CRYPEN bit in CRYP_CR (it must be set to 0). 3. Configure the cryptographic processor again with the initial setting in CRYP_CR, as well as the key registers using the saved configuration. 4. For AES-ECB or AES-CBC decryption, the key must be prepared again, as described in Section 35.3.7: Preparing the CRYP AES key for decryption. 5. If ECB mode is not selected, restore CRYP_IVx registers using the saved configuration. 6. Enable the cryptographic processor by setting the CRYPEN bit to 1. 7. If DMA is used, enable again the DMA requests from the cryptographic processor, by setting DIEN and DOEN bits to 1 in the CRYP_DMACR register. DocID029587 Rev 3 1225/3178 1268 Cryptographic processor (CRYP) 35.3.12 RM0433 CRYP AES counter mode (AES-CTR) Overview The AES counter mode (CTR) uses the AES block as a key stream generator. The generated keys are then XORed with the plaintext to obtain the ciphertext. CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation. A typical message construction in CTR mode is given in Figure 261. Figure 261. Message construction for the Counter mode %\WHVERXQGDULHV &75PRGH (QFU\SWHG&LSKHUWH[W & 3DG GLQJ GHFU\SW ,&% %\WHVERXQGDULHV 1RQFH 3ODLQWH[W 3 ,QLWLDOL]DWLRQ YHFWRU ,9 &RXQWHU [ 06Y9 The structure of this message is as below: • • 1226/3178 A 16-byte Initial Counter Block (ICB), composed of three distinct fields: – A nonce: a 32-bit, single-use value (i.e. a new nonce should be assigned to each new communication). – The initialization vector (IV): a 64-bit value that must be unique for each execution of the mode under a given key. – The counter: a 32-bit big-endian integer that is incremented each time a block has been processed. The initial value of the counter should be set to 1. The plaintext (P) is both authenticated and encrypted as ciphertext C, with a known length. This length can be non-multiple of 16 bytes, in which case a plaintext padding is required. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) AES CTR processing Figure 262 (respectively Figure 263) describes the AES-CTR encryption (respectively decryption) process implemented within this peripheral. This mode is selected by writing in ALGOMODE bitfield to 0b110 in CRYP_CR. Figure 262. AES-CTR mode encryption ). &)&/ PLAINTEXT 0 3ELWV $+%GDWDZULWH EHIRUH&5<3 LVHQDEOHG '$7$7<3( SWAPPING )6,2 3VELWV + ,ELWV OR , LVZULWWHQ EDFNLQWR,9 DWVDPHWLPH WKDQ&LVSXVKHG LQ287),)2 !%! ENCRYPT 2ELWV &VELW '$7$7<3( SWAPPING &ELWV /54 &)&/ CIPHERTEXT # AIB 1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when encoding); P: plain text; IV: Initialization vectors. DocID029587 Rev 3 1227/3178 1268 Cryptographic processor (CRYP) RM0433 Figure 263. AES-CTR mode decryption ). &)&/ CIPHERTEXT 0 &ELWV $+%GDWDZULWH EHIRUH&5<3 LVHQDEOHG '$7$7<3( SWAPPING )6,2 &VELWV + ,ELWV RU , LVZULWWHQ EDFNLQWR,9 DWVDPHWLPH WKDQ3LVSXVKHG LQ287),)2 !%! ENCRYPT 2ELWV 3VELWV '$7$7<3( SWAPPING 3ELWV /54 &)&/ PLAINTEXT # -36 1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when encoding); P: plain text; IV: Initialization vectors. In CTR mode, the output block is XORed with the subsequent input block before it is input to the algorithm. Initialization vectors in the peripheral must be initialized as shown on Table 264. Table 264. Counter mode initialization vector CRYP_IV1R[31:0] CRYP_IV1L[31:0] CRYP_IV0R[31:0] CRYP_IV0L[31:0] nonce IV[63:32] IV[31:0] 32-bit counter= 0x1 Unlike in CBC mode, which uses the CRYP_IVx registers only once when processing the first data block, in CTR mode IV registers are used for processing each data block, and the peripheral increments the least significant 32 bits (leaving the other most significant 96 bits unchanged). CTR decryption does not differ from CTR encryption, since the core always encrypts the current counter block to produce the key stream that will be XORed with the plaintext or cipher as input. Thus when ALGOMODE is set to 0b110, ALGODIR is don’t care. Note: 1228/3178 In this mode the key must NOT be prepared for decryption. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) The following sequence must be used to perform an encryption or a decryption in CTR chaining mode: 1. Make sure the cryptographic processor is disabled by clearing the CRYPEN bit in the CRYP_CR register. 2. Configure CRYP_CR as follows: a) Program ALGOMODE bits to 0b110 to select CTR mode. b) Configure the data type (1, 8, 16 or 32 bits) through the DATATYPE bits. 3. Initialize the key registers (128,192 and 256 bits) in CRYP_KEYRx as well as the initialization vector (IV) as described in Table 264. 4. Flush the IN and OUT FIFOs by writing the FFLUSH bit to 1 in the CRYP_CR register. 5. If it is the last block, optionally pad the data with zeros to have a complete block. 6. Append data in the cryptographic processor and read the result. The three possible scenarios are described in Section 35.3.5: CRYP procedure to perform a cipher operation. 7. Repeat the previous step until the second last block is processed. For the last block, execute the two previous steps. For this last block, the driver must discard the data that is not part of the data when the last block size is less than 16 bytes. Suspend/resume operations in CTR mode Like for the CBC mode, it is possible to interrupt a message to send a higher priority message, and resume the message which was interrupted. Detailed CBC sequence can be found in Section 35.3.11: CRYP AES basic chaining modes (ECB, CBC). Note: Like for CBC mode, IV registers must be reloaded during the resume operation. DocID029587 Rev 3 1229/3178 1268 Cryptographic processor (CRYP) 35.3.13 RM0433 CRYP AES Galois/counter mode (GCM) Overview The AES Galois/counter mode (GCM) allows encrypting and authenticating the plaintext, and generating the correspondent ciphertext and tag (also known as message authentication code). To ensure confidentiality, GCM algorithm is based on AES counter mode. It uses a multiplier over a fixed finite field to generate the tag. GCM chaining is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC. A typical message construction in GCM mode is given in Figure 264. Figure 264. Message construction for the Galois/Counter mode >/HQ $ @ /HQ $ %\WHVERXQGDULHV /HQ 3 /HQ & $GGLWLRQDO$XWKHQWLFDWHG'DWD 3DGGLQJ $$' µ¶ 3DGGL QJµ¶ 3ODLQWH[W 3 /DVW %ORFN &RXQWHU [ DXWKHQWLFDWLRQ ,QLWLDOL]DWLRQYHFWRU ,9 =HURH GELWV $XWKHQWLFDWHG (QFU\SWHG&LSKHUWH[W & DXWKHQWL FDWLRQ %\WHVERXQGDULHV DXWKHQWLFDWLRQ HQFU\ SW ,&% >/HQ & @ $XWK7DJ 7 06Y9 The structure of this message is defined as below: • Note: 1230/3178 A 16-byte Initial Counter Block (ICB), composed of two distinct fields: – The initialization vector (IV): a 96-bit value that must be unique for each execution of the mode under a given key. Note that the GCM standard supports IV that are shorter than 96-bit, but in this case strict rules apply. – The counter: a 32-bit big-endian integer that is incremented each time a block has been processed. According to NIST specification, the counter value is 0x2 when processing the first block of payload. • The authenticated header A (also knows as Additional Authentication Data) has a known length Len(A) that can be non-multiple of 16 bytes and cannot exceed 264-1 bits. This part of the message is only authenticated, not encrypted. • The plaintext message (P) is both authenticated and encrypted as ciphertext C, with a known length Len(P) that can be non-multiple of 16 bytes, and cannot exceed 232 -2 blocks of 128-bits. GCM standard specifies that ciphertext C has same bit length as the plaintext P. • When a part of the message (AAD or P) has a length which is non-multiple of 16 bytes, a special padding scheme is required. • The last block is composed of the length of A (on 64 bits) and the length of ciphertext C (on 64 bits) as shown inTable 265. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Table 265. GCM last block definition Endianness Input data Bit[0] Bit[32] 0x0 Bit[64] Header length[31:0] Bit[96] 0x0 Payload length[31:0] AES GCM processing This mode is selected by writing ALGOMODE bitfield to 0b110 in CRYP_CR. The mechanism for the confidentiality of the plaintext in GCM mode is a variation of the Counter mode, with a particular 32-bit incrementing function that generates the necessary sequence of counter blocks. CRYP_IV registers are used for processing each data block. The cryptographic processor automatically increments the 32 least signification bits of the counter block. The first counter block (CB1) written by the application is equal to the Initial Counter Block incremented by one (see Table 266). Table 266. GCM mode IV registers initialization Note: Register CRYP_IV1R[31:0] CRYP_IV1L[31:0] CRYP_IV0R[31:0] CRYP_IV0L[31:0] Input data ICB[127:96] ICB[95:64] ICB[63:32] ICB[31:0] 32-bit counter= 0x2 In this mode the key must NOT be prepared for decryption. The authentication mechanism in GCM mode is based on a hash function, called GF2mul, that performs multiplication by a fixed parameter, called the hash subkey (H), within a binary Galois field. To process a GCM message, the driver must go through four phases, which are described in the following subsections. • The Init phase: the peripheral prepares the GCM hash subkey (H) and performs the IV processing • The Header phase: the peripheral processes the Additional Authenticated Data (AAD), with hash computation only. • The Payload phase: the peripheral processes the plaintext (P) with hash computation, keystream encryption and data XORing. It operates in a similar way for ciphertext (C). • The Final phase: the peripheral generates the authenticated tag (T) using the data last block. DocID029587 Rev 3 1231/3178 1268 Cryptographic processor (CRYP) 1. RM0433 GCM init phase During this first step, the GCM hash subkey (H) is calculated and saved internally to be used for processing all the blocks. It is recommended to follow the sequence below: 2. a) Make sure the cryptographic processor is disabled by clearing the CRYPEN bit in the CRYP_CR register. b) Select the GCM chaining mode by programming ALGOMODE bits to 0b01000 in CRYP_CR. c) Configure GCM_CCMPH bits to 0b00 in CRYP_CR to indicate that the init phase is ongoing. d) Initialize the key registers (128, 192 and 256 bits) in CRYP_KEYRx as well as the initialization vector (IV) as defined in Table 266. e) Set CRYPEN bit to 1 to start the calculation of the hash key. f) Wait for the CRYPEN bit to be cleared to 0 by the cryptographic processor, before moving on to the next phase. GCM header phase The below sequence shall be performed after the GCM init phase. It must be complete before jumping to the payload phase. The sequence is identical for encryption and decryption. Note: g) Set the GCM_CCMPH bits to 0b01 in CRYP_CR to indicate that the header phase is ongoing. h) Set the CRYPEN bit to 1 to start accepting data. i) If it is the last block of additional authenticated data, optionally pad the data with zeros to have a complete block. j) Append additional authenticated data in the cryptographic processor. The three possible scenarios are described in Section 35.3.5: CRYP procedure to perform a cipher operation. k) Repeat the previous step until the second last additional authenticated data block is processed. For the last block, execute the two previous steps. Once all the additional authenticated data have been supplied, wait until the BUSY flag is cleared before moving on to the next phase. This phase can be skipped if there is no additional authenticated data, i.e. Len(A)=0. In header and payload phases, CRYPEN bit is not automatically cleared by the cryptographic processor. 1232/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 3. GCM payload phase (encryption or decryption) When the payload size is not null, this sequence must be executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the CRYP_DOUT register. l) Set the CRYPEN bit to 0. m) Configure GCM_CCMPH to 0b10 in the CRYP_CR register to indicate that the payload phase is ongoing. Note: n) Select the algorithm direction (0 for encryption, 1 for decryption) through the ALGODIR bit in CRYP_CR. o) Set the CRYPEN bit to 1 to start accepting data. p) If it is the last block of cleartext or plaintext, optionally pad the data with zeros to have a complete block. For encryption, refer to Section 35.3.8: CRYP stealing and data padding for more details. q) Append payload data in the cryptographic processor, and read the result. The three possible scenarios are described in Section 35.3.5: CRYP procedure to perform a cipher operation. r) Repeat the previous step until the second last plaintext block is encrypted or until the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), execute the two previous steps. For the last block, the driver must discard the bits that are not part of the cleartext or the ciphertext when the last block size is less than 16 bytes. Once all payload data have been supplied, wait until the BUSY flag is cleared. This phase can be skipped if there is no payload data, i.e. Len(C)=0 (see GMAC mode). 4. GCM final phase In this last step, the cryptographic processor generates the GCM authentication tag and stores it in CRYP_DOUT register. Note: s) Configure GCM_CCMPH[1:0] to 0b11 in CRYP_CR to indicate that the Final phase is ongoing. Set the ALGODIR bit to 0 in the same register. t) Write the input to the CRYP_DIN register four times. The input must be composed of the length in bits of the additional authenticated data (coded on 64 bits) concatenated with the length in bits of the payload (coded of 64 bits), as show in Table 265. In this final phase data have to be swapped according to the DATATYPE programmed in CRYP_CR register. u) Wait until the OFNE flag (FIFO output not empty) is set to 1 in the CRYP_SR register. v) Read the CRYP_DOUT register 4four times: the output corresponds to the authentication tag. w) Disable the cryptographic processor (CRYPEN bit = 0 in CRYP_CR) x) If an authenticated decryption is being performed, compare the generated tag with the expected tag passed with the message. Suspend/resume operations in GCM mode Before interrupting the current message in header or payload phase, the user application must respect the following sequence: DocID029587 Rev 3 1233/3178 1268 Cryptographic processor (CRYP) Note: RM0433 1. If DMA is used, stop DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in the CRYP_DMACR register. 2. Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR register) and the BUSY bit is cleared. 3. If DMA is used, stop DMA transfers from the OUT FIFO by clearing to 0 the DOEN bit in the CRYP_DMACR register. 4. Disable the cryptographic processor by setting the CRYPEN bit to 0 in CRYP_CR, then save the current configuration (bits [9:2], bits [17:16] and bits 19 of the CRYP_CR register). In addition, save the initialization vector registers, since CRYP_IVx registers have changed from their initial values during data processing. Key registers do not need to be saved as original their key value is known by the application. 5. Save context swap registers: CRYP_CSGCMCCM0..7 and CRYP_CSGCM0..7 6. If DMA is used, save the DMA controller status (pointers to IN and OUT data transfers, number of remaining bytes, etc.). To resume message processing, the user must respect the following sequence: Note: 1234/3178 1. If DMA is used, reconfigure the DMA controller to complete the rest of the FIFO IN and FIFO OUT transfers. 2. Make sure the cryptographic processor is disabled by reading the CRYPEN bit in CRYP_CR (it must be 0). 3. Configure again the cryptographic processor with the initial setting in CRYP_CR, as well as the key registers using the saved configuration. 4. Restore context swap registers: CRYP_CSGCMCCM0..7 and CRYP_CSGCM0..7 5. Restore CRYP_IVx registers using the saved configuration. 6. Enable the cryptographic processor by setting the CRYPEN bit to 1. 7. If DMA is used, enable again cryptographic processor DMA requests by setting to 1 the DIEN and DOEN bits in the CRYP_DMACR register. In Header phase, DMA OUT FIFO transfer is not used. DocID029587 Rev 3 RM0433 CRYP AES Galois message authentication code (GMAC) Overview The Galois message authentication code (GMAC) allows authenticating a plaintext and generating the corresponding tag information (also known as message authentication code). It is based on GCM algorithm, as defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC. A typical message construction in GMAC mode is given in Figure 265. Figure 265. Message construction for the Galois Message Authentication Code mode >/HQ $ @ %\WHVERXQGDULHV /HQ $ ,&% $XWKHQWLFDWHG'DWD %\WHVERXQGDULHV ,QLWLDOL]DWLRQYHFWRU ,9 3DGGLQJ /DVW µ¶ %ORFN DXWKHQ WLFDWLRQ 35.3.14 Cryptographic processor (CRYP) $XWK7DJ 7 &RXQWHU [ 06Y9 AES GMAC processing This mode is selected by writing ALGOMODE bitfield to 0b110 in CRYP_CR. GMAC algorithm corresponds to the GCM algorithm applied on a message composed only of an header. As a consequence, all steps and settings are the same as in GCM mode, except that the payload phase (3) is not used. Suspend/resume operations in GMAC GMAC is exactly the same as GCM algorithm except that only header phase (2) can be interrupted. DocID029587 Rev 3 1235/3178 1268 Cryptographic processor (CRYP) 35.3.15 RM0433 CRYP AES Counter with CBC-MAC (CCM) Overview The AES Counter with Cipher Block Chaining-Message Authentication Code (CCM) algorithm allows encrypting and authenticating the plaintext, and generating the correspondent ciphertext and tag (also known as message authentication code). To ensure confidentiality, CCM algorithm is based on AES counter mode. It uses Cipher Block Chaining technique to generate the message authentication code. This is commonly called CBC-MAC Note: NIST does not approve this CBC-MAC as an authentication mode outside of the context of the CCM specification. CCM chaining is specified in NIST Special Publication 800-38C, Recommendation for Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality. A typical message construction in CCM mode is given in Figure 266 Figure 266. Message construction for the Counter with CBC-MAC mode $OHQ %\WHVERXQGDULHV >D@ >D@ $VVRFLDWHG'DWD $ 3DGGLQJ ³´ 3ODLQWH[W 3 7OHQ 3DGGLQ J³´ (QF 7 IODJV $XWKHQWLFDWHG (QFU\SWHG&LSKHUWH[W & 1RQFH 1 4 GHFU\S FRPSDUH %\WHVERXQGDULHV DXWKHQ WLFDWLRQ (QFU\SW % &OHQ 3OHQ 0$& 7 1OHQ 06Y 9 The structure of this message is as below: • Note: 1236/3178 One 16-byte first authentication block (called B0 by the standard), composed of three distinct fields: – Q: a bit string representation of the byte length of P (Plen) – A nonce (N): single-use value (i.e. a new nonce should be assigned to each new communication). Size of nonce Nlen + size of Plen shall be equal to 15 bytes. – Flags: most significant byte containing four flags for control information, as specified by the standard. It contains two 3-bit strings to encode the values t (MAC length expressed in bytes) and q (plaintext length such as Plen<28q bytes). Note that the counter blocks range associated to q is equal to 28q-4, i.e. if q maximum value is 8, the counter blocks used in cipher shall be on 60 bits. The cryptographic peripheral can only manage padded plaintext/ciphertext messages of length Plen < 236 +1 bytes. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) • 16-bytes blocks (B) associated to the Associated Data (A). This part of the message is only authenticated, not encrypted. This section has a known length, ALen, that can be a non-multiple of 16 bytes (see Figure 266). The standard also states that, on the MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as defined below: – – – Note: If 0 < a < 216-28, then it is encoded as [a]16, i.e. two bytes. If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six bytes. If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten bytes. • 16-byte blocks (B) associated to the plaintext message (P), which is both authenticated and encrypted as ciphertext C, with a known length of Plen. This length can be a nonmultiple of 16 bytes (see Figure 266) but cannot exceed 232 blocks of 128-bit. • The encrypted MAC (T) of length Tlen appended to the ciphertext C of overall length Clen. • When a part of the message (A or P) has a length which is a non-multiple of 16 bytes, a special padding scheme is required. CCM chaining mode can also be used with associated data only (i.e. no payload). As an example, the C.1 section in NIST Special Publication 800-38C gives the following: N: 10111213 141516 (Nlen= 56 bits or 0x7 bytes) A: 00010203 04050607 (Alen= 64 bits or 0x8 bytes) P: 20212223 (Plen= 32 bits i.e. Q= 0x4 bytes) T: 6084341b (Tlen= 32 bits or t= 4) B0: 4f101112 13141516 00000000 00000004 B1: 00080001 02030405 06070000 00000000 B2: 20212223 00000000 00000000 00000000 CTR0: 0710111213 141516 00000000 00000000 CTR1: 0710111213 141516 00000000 00000001 The usage of control blocks CTRx is explained in the following section. The generation of CTR0 from the first block (B0) must be managed by software. DocID029587 Rev 3 1237/3178 1268 Cryptographic processor (CRYP) RM0433 AES CCM processing This mode is selected by writing ALGOMODE bitfield to 0b1001 in CRYP_CR. The data input to the generation-encryption process are a valid nonce, a valid payload string, and a valid associated data string, all properly formatted. The CBC chaining mechanism is applied to the formatted data to generate a MAC, whose length is known. Counter mode encryption, which requires a sufficiently long sequence of counter blocks as input, is applied to the payload string and separately to the MAC. The resulting data, called the ciphertext C, is the output of the generation-encryption process on plaintext P. CRYP_IV registers are used for processing each data block. The cryptographic processor automatically increments the CTR counter with a bit length defined by the first block (B0). The first counter written by application, CTR1, is equal to B0 with the first 5 bits zeroed and the most significant bits containing P byte length also zeroed, then incremented by one (see Table 267). Table 267. CCM mode IV registers initialization Register CRYP_IV0L[31:0] CRYP_IV0R[31:0] CRYP_IV1L[31:0] CRYP_IV1R[31:0] Endianness IV[0:31] IV[32:63] IV[64:95] IV[96:127] Input data B0[31:0], where the 5 most significant bits are set to 0 (flag bits) B0[63:32] B0[95:64] B0[127:96], where Q length bits are set to 0, except for bit 0 that is set to 1 Note: In this mode, the key must NOT be prepared for decryption. To process a CCM message, the driver must go through four phases, which are described below. 1238/3178 • The Init phase: the peripheral processes the first block and prepares the first counter block. • The Header phase: the peripheral processes the Associated data (A), with hash computation only. • The Payload phase: the peripheral processes the plaintext (P), with hash computation, counter block encryption and data XORing. It operates in a similar way for ciphertext (C). • The Final phase: the peripheral generates the message authentication code (MAC). DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 1. CCM init phase In this first step, the first block (B0) of the CCM message is programmed into the CRYP_DIN register. During this phase, the CRYP_DOUT register does not contain any output data. It is recommended to follow the sequence below: Note: a) Make sure that the cryptographic processor is disabled by clearing the CRYPEN bit in the CRYP_CR register. b) Select the CCM chaining mode by programming the ALGOMODE bits to 0b01001 in the CRYP_CR register. c) Configure the GCM_CCMPH bits to 0b00 in CRYP_CR to indicate that we are in the init phase. d) Initialize the key registers (128, 192 and 256 bits) in CRYP_KEYRx as well as the initialization vector (IV) with CTR1 information, as defined in Table 267. e) Set the CRYPEN bit to 1 in CRYP_CR to start accepting data. f) Write the B0 packet into CRYP_DIN register, then wait for the CRYPEN bit to be cleared to 0 by the cryptographic processor before moving on to the next phase. In this init phase data have to be swapped according to the DATATYPE programmed in CRYP_CR register. 2. CCM header phase The below sequence shall be performed after the CCM Init phase. It must be complete before jumping to the payload phase. The sequence is identical for encryption and decryption. During this phase, the CRYP_DOUT register does not contain any output data. g) Set the GCM_CCMPH bit to 0b01 in CRYP_CR to indicate that the header phase is ongoing. h) Set the CRYPEN bit to 1 to start accepting data. i) If it is the last block of associated data, optionally pad the data with zeros to have a complete block. j) Append the associated data in the cryptographic processor. The three possible scenarios are described in Section 35.3.5: CRYP procedure to perform a cipher operation. k) Repeat the previous step until the second last associated data block is processed. For the last block, execute the two previous steps. Once all the additional authenticated data have been supplied, wait until the BUSY flag is cleared. Note: This phase can be skipped if there is no associated data (Alen=0). Note: The first block of the associated data B1 must be formatted with the associated data length. This task must be managed by the driver. DocID029587 Rev 3 1239/3178 1268 Cryptographic processor (CRYP) 3. RM0433 CCM payload phase (encryption or decryption) When the payload size is not null, this sequence must be performed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the CRYP_DOUT register. l) Set the CRYPEN bit to 0. m) Configure GCM_CCMPH bits to 0b10 in CRYP_CR to indicate that the payload phase is ongoing. n) Select the algorithm direction (0 for encryption, 1 for decryption) through the ALGODIR bit in CRYP_CR. o) Set the CRYPEN bit to 1 to start accepting data. p) If it is the last block of cleartext, optionally pad the data with zeros to have a complete block (encryption only). For decryption, refer to Section 35.3.8: CRYP stealing and data padding for more details. q) Append payload data in the cryptographic processor, and read the result. The three possible scenarios are described in Section 35.3.5: CRYP procedure to perform a cipher operation. r) Repeat the previous step until the second last plaintext block is encrypted or until the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), execute the two previous steps. For the last block of ciphertext (decryption only), the driver must discard the data that is not part of the cleartext when the last block size is less than 16 bytes. Once all payload data have been supplied, wait until the BUSY flag is cleared Note: This phase can be skipped if there is no payload data, i.e. Plen=0 or Clen=Tlen Note: Do not forget to remove LSBTlen(C) encrypted tag information when decrypting ciphertext C. 4. CCM final phase In this last step, the cryptographic processor generates the CCM authentication tag and stores it in the CRYP_DOUT register. Note: 1240/3178 s) Configure GCM_CCMPH[1:0] bits to 0b11 in CRYP_CR to indicate that the final phase is ongoing and set the ALGODIR bit to 0 in the same register. t) Load in CRYP_DIN, the CTR0 information which is described in Table 267 with bit[0] set to 0. In this final phase, data have to be swapped according to the DATATYPE programmed in CRYP_CR register. u) Wait until the OFNE flag (FIFO output not empty) is set to 1 in the CRYP_SR register. v) Read the CRYP_DOUT register four times: the output corresponds to the encrypted CCM tag. w) Disable the cryptographic processor (CRYPEN bit set to 0 in CRYP_CR) x) If an authenticated decryption is being performed, compare the generated encrypted tag with the encrypted tag padded in the ciphertext, i.e. LSBTlen(C)= MSBTlen(CRYP_DOUT data). DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Suspend/resume operations in CCM mode Before interrupting the current message in payload phase, the user application must respect the following sequence: Note: 1. If DMA is used, stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in the CRYP_DMACR register. 2. Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR register) and the BUSY bit is cleared. 3. If DMA is used, stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN bit in the CRYP_DMACR register. 4. Disable the cryptographic processor by setting the CRYPEN bit to 0 in CRYP_CR, then save the current configuration (bits [9:2], bits [17:16] and bits 19 in the CRYP_CR register). In addition, save the initialization vector registers, since CRYP_IVx registers have changed from their initial values during the data processing. Key registers do not need to be saved as their original key value is known by the application. 5. Save context swap registers: CRYP_CSGCMCCM0..7 6. If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers, number of remaining bytes, etc.). To resume message processing, the user application must respect the following sequence: Note: 1. If DMA is used, reconfigure the DMA controller to complete the rest of the FIFO IN and FIFO OUT transfers. 2. Make sure the cryptographic processor is disabled by reading the CRYPEN bit in CRYP_CR (must be 0). 3. Configure the cryptographic processor again with the initial setting in CRYP_CR and key registers using the saved configuration. 4. Restore context swap registers: CRYP_CSGCMCCM0..7 5. Restore CRYP_IVx registers using the saved configuration. 6. Enable the cryptographic processor by setting the CRYPEN bit to 1. 7. If DMA is used, enable again cryptographic processor DMA requests by setting to 1 the DIEN and DOEN bits in the CRYP_DMACR register. In Header phase DMA OUT FIFO transfer is not used. DocID029587 Rev 3 1241/3178 1268 Cryptographic processor (CRYP) 35.3.16 RM0433 CRYP data registers and data swapping Introduction The CRYP_DIN register is the 32-bit wide data input register of the peripheral. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. The first word written into the FIFO is the LSB of the input block. The MSB of the input block is written at the end. CRYP_DIN data endianness can be described as below when DATATYPE=”00” (no data swapping): • In the DES/TDES modes Bit 1 (leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word entered into the FIFO, bit 64 (rightmost bit) corresponds to the LSB (bit 0) of the second word entered into the FIFO. • In the AES mode Bit 0 (leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word written into the FIFO, bit 127 (rightmost bit) corresponds to the LSB (bit 0) of the 4th word written into the FIFO. Similarly CRYP_DOUT register is the 32-bit wide data out register of the peripheral. It is a read-only register that is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. Like for the input data, the LSB of the output block is the first word read from the output FIFO. The MSB of the output block is read at the end. CRYP_DOUT data endianness can be described as below when DATATYPE=”00” (no data swapping): • In the DES/TDES modes Bit 1 (leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word read from the FIFO, bit 64 (rightmost bit) corresponds to the LSB (bit 0) of the second word read from the FIFO. • In the AES mode Bit 0 (leftmost bit) of the data block corresponds to the MSB (bit 31) of the first word read from the FIFO, bit 127 (rightmost bit) corresponds to the LSB (bit 0) of the 4th word read from the FIFO. 1242/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) DES/TDES data swapping feature Depending on the type of data to be processed (e.g. byte swapping when data are ASCII text stream), a bit, byte, half-word or no swapping operation must be done on the data read from the input FIFO before entering the little-endian DES processing core. The same swapping must be performed on the data produced by the little-endian DES processing core before they are written to the output FIFO. Figure 267 shows how the DES processing core 64-bit data block M1...64 is constructed from two consecutive 32-bit words popped into IN FIFO by the driver. This is done according to the DATATYPE bitfield in the CRYP_CR register. Note: The same swapping is performed between the IN FIFO and the CRYP data block, and between the CRYP data block and the OUT FIFO. Figure 267. 64-bit block construction according to the data type (IN FIFO) '$7$7<3( E QRVZDSSLQJ /6% ZULWWHQILUVW :RUG ELW '$7$7<3( E ELWRUKDOIZRUGVZDSSLQJ 6\VWHPLQWHUIDFH ELW ELW ZULWWHQILUVW :RUG ELW ELW ELW ELW 0 0 '(6FRUHLQWHUIDFH 0 /6% /6% 06% :RUG 0 06% 0 /6% ELW ELW ELW 0 /6% 6\VWHPLQWHUIDFH 06% /6% ELW 0 0 '(6FRUHLQWHUIDFH 0 6\VWHPLQWHUIDFH ZULWWHQILUVW :RUG :RUG ELW 0 ELW 06% :RUG ELW ELW 0 ELW 0 06% '$7$7<3( E ELWVZDSSLQJ '$7$7<3( E ELWRUE\WHVZDSSLQJ /6% ZULWWHQILUVW :RUG 0 6\VWHPLQWHUIDFH ELW ELW ELW ELW 0 0 0 0 0 0 0 '(6FRUHLQWHUIDFH 06% 06% :RUG ELWELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW 0 0 0 /6% 0 0 0 0 0 0 '(6FRUHLQWHUIDFH 0 0 0 06% 06Y9 Note: The CRYP Key registers (CRYP_Kx(L/R)) and initialization registers (CRYP_IVx(L/R)) are not sensitive to the swap mode selected. They have a fixed little-endian configuration (refer to Section 35.3.17 and Section 35.3.18, respectively). A typical example of data swapping is given in Table 268. DocID029587 Rev 3 1243/3178 1268 Cryptographic processor (CRYP) RM0433 Table 268. DES/TDES data swapping feature DATATYPE in CRYP_CR Data block representation (64-bit) 0xABCD7720 6973FE01 Swapping performed System memory data (plaintext or cypher) Address @: 0xABCD7720 (LSB, written first) Address @+4: 0x6973FE01 0b00 No swapping 7'(6EORFNVL]H ELW [ELW [$%&' )( V\VWHPPHPRU\ [$%&' [ )( # # Address @: 0x7720ABCD (swapped LSB, written first) Address @+4: 0xFE016973 0b01 Half-word (16-bit) swapping V\VWHPPHPRU\ 7'(6EORFNVL]H ELW [ELW [$%&' )( [$%&' [)( # # Address @: 0x2077CDAB (swapped LSB, written first) Address @+4: 0x01FE7369 0b10 Byte (8-bit) swapping V\VWHPPHPRU\ 7'(6EORFNVL]H ELW [ELW [$%&' )( 0b11 Bit swapping [&'$% [)( LSB data word: 0xABCD7720 0b1010 1011 1100 1101 0111 0111 0010 0000 MSB data word: 0x6973FE01 0b0110 1001 0111 0011 1111 1110 0000 0001 Address @: 0x04EEB3D5 (swapped LSB, written first) Address @+4: 0x807FCE96 1244/3178 DocID029587 Rev 3 # # RM0433 Cryptographic processor (CRYP) AES data swapping feature Depending on the type of data to be processed (e.g. byte swapping when data are ASCII text stream), a bit, byte, half-word or no swapping operation must be done on data read from the input FIFO before entering the little-endian AES processing core. The same swapping must be performed on the data produced by the little-endian AES processing core before they are written to the output FIFO. Figure 268 shows how the AES processing core 128-bit data block P0..127 is constructed from four consecutive 32-bit words written by the driver to the CRYP_DIN register. This is done according to the DATATYPE bitfield in the CRYP control register (CRYP_CR). Note: The same swapping is performed between the CRYP_DIN and the CRYP data block, and between the CRYP data block and the CRYP_DOUT. Figure 268. 128-bit block construction according to the data type '$7$7<3(³´ QRVZDSSLQJ /6% 06% 6\VWHPLQWHUIDFH ZULWWHQILUVW :RUG :RUG :RUG ELW ELW ELW 3 3 3 ELW ELW 3 3 $(6FRUHLQWHUIDFH /6% :RUG ELW ELW 3 3 ELW 3 06% '$7$7<3(³´ ELWRUKDOIZRUGVZDSSLQJ ZULWWHQILUVW /6% ELW 3 /6% :RUG ELW ELW 3 3 ELW ELW 3 06% 6\VWHPLQWHUIDFH :RUG ELW ELW 3 3 3 ELW ELW :RUG ELW ELW ELW 3 $(6FRUHLQWHUIDFH ELW 3 :RUG ELW ELW 3 3 ELW 3 06% '$7$7<3(³´ ELWRUE\WHVZDSSLQJ ZULWWHQILUVW /6% 3 /6% 3 :RUG :RUG ELW ELW ELW 3 ELW 06% 6\VWHPLQWHUIDFH :RUG ELW ELW ELW 3 ELW ELW ELW ELW $(6FRUHLQWHUIDFH :RUG ELW ELW ELW ELW 3 3 ELW 3 06% '$7$7<3(³´ ELWVZDSSLQJ 3 3 /6% 6\VWHPLQWHUIDFH ZULWWHQILUVW /6% :RUG ELW ELW ELW 3 ELW ELW ELW 3 3 3 :RUG ELW ELW ELW 3 3 3 :RUG ELW ELW ELW 3 3 3 $(6FRUHLQWHUIDFH 06% :RUG ELW ELW ELW 3 3 3 ELW ELW ELW 3 3 3 06% 06Y9 DocID029587 Rev 3 1245/3178 1268 Cryptographic processor (CRYP) Note: RM0433 The swapping operation concerns only the CRYP_DOUT and CRYP_DIN registers. The CRYP_KxL/KxR and CRYP_IVxL/IVxR registers are not sensitive to the swap mode selected.They have a fixed little-endian configuration (refer to Section 35.3.17 and Section 35.3.18). Typical examples of data swapping are given in Table 269. Table 269. AES data swapping feature DATATYPE in CRYP_CR Data block representation (64-bit) 0x4E6F7720 69732074 Swapping performed System memory data (little-endian) Address @: 0x4E6F7720 (LSB, written first) Address @+4: 0x69732074 0b00 No swapping 0b01 Half-word (16-bit) swapping Address @: 0x77204E6F (swapped LSB, written first) Address @+4: 0x20746973 0b10 Byte (8-bit) swapping Address @: 0x20776F4E (swapped LSB, written first) Address @+4: 0x74207369 0b11 Bit swapping LSB data word: 0x4E6F7720 0b0100 1110 0110 1111 0111 0111 0010 0000 MSB data word: 0x69732074 0b0110 1001 0111 0011 0010 0000 0111 0100 Address @: 0x4EEF672 (swapped LSB, written first) Address @+4: 0x2E04CE96 35.3.17 CRYP key registers The CRYP_Kx registers are used to store the encryption or decryption keys. They are organized as eight registers in a little-endian configuration, as shown in Table 270. Table 270. Key registers CRYP_KxR/LR endianness (TDES K1/2/3 and AES 128/192/256-bit keys) K0LR[31:0] K0RR[31:0] K1LR[31:0] K1RR[31:0] K2LR[31:0] K2RR[31:0] K3LR[31:0] K3RR[31:0] - - K1[1:32] K1[33:64] K2[1:32] K2[33:64] K2[1:32] K2[33:64] K0LR[31:0] K0RR[31:0] K1LR[31:0] K1RR[31:0] K2LR[31:0] K2RR[31:0] K3LR[31:0] K3RR[31:0] - - - - k[0:31] k[32:63] k[64:95] k[96:127] K0LR[31:0] K0RR[31:0] K1LR[31:0] K1RR[31:0] K2LR[31:0] K2RR[31:0] K3LR[31:0] K3RR[31:0] - - k[0:31] k[32:63] k[64:95] k[96:127] k[128:159] k[160:191] K0LR[31:0] K0RR[31:0] K1LR[31:0] K1RR[31:0] K2LR[31:0] K2RR[31:0] K3LR[31:0] K3RR[31:0] k[0:31] k[32:63] k[64:95] k[96:127] k[128:159] k[160:191] k[192:223] k[224:255] Note: 1246/3178 DES/TDES keys include 8-bit parity information that are not used by the cryptographic processor. In other words, bits 8, 16, 24, 32, 40, 48, 56 and 64 of each 64-bit key value Kx[1:64] are not used. DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Keys are considered as four 64-bit data items. They therefore do not have the same data format and representation in system memory as plaintext or ciphertext data. Any write operation to the CRYP_Kx(L/R) registers when the BUSY bit is set to 1 in the CRYP_SR register is disregarded (i.e. register content not modified). Thus, the software must check that the BUSY equals 0 before modifying key registers. Key registers are not affected by the data swapping feature controlled by DATATYPE value in CRYP_CR register. Refer to Section 35.6: CRYP registers for a detailed description of CRYP_Kx(L/R) registers. 35.3.18 CRYP initialization vector registers The CRYP_IVxL/IVxR registers are used to store the initialization vector or the nonce, depending on the chaining mode selected. When used, these registers are updated by the core after each computation round of the TDES or AES core. They are organized as four registers in a little-endian configuration, as shown in Table 271. Table 271. Initialization vector registers CRYP_IVxR endianness CRYP_IV1R[31:0] CRYP_IV1L[31:0] CRYP_IV0R[31:0] CRYP_IV0L[31:0] IV[96:127] IV[64:95] IV[32:63] IV[0:31] Initialization vector registers are considered as two 64-bit data items. They therefore do not have the same data format and representation in system memory as plaintext or ciphertext data. Any write operation to the CRYP_IV0...1(L/R) registers when the BUSY bit is set to 1 in the CRYP_SR register is disregarded (i.e. register content not modified). Therefore, the software must check that the BUSY equals 0 in the CRYP_SR register before modifying initialization vectors. Reading the CRYP_IV0...1(L/R) register returns the latest counter value (useful for managing suspend mode) except for CCM/GCM. Note: In DES/TDES mode, only CRYP_IV0x are used. Initialization vector registers are not affected by the data swapping feature controlled by DATATYPE value in CRYP_CR register. Refer to Section 35.6: CRYP registers for a detailed description of CRYP_IVxL/IVxR registers. DocID029587 Rev 3 1247/3178 1268 Cryptographic processor (CRYP) 35.3.19 RM0433 CRYP DMA interface The cryptographic processor provides an interface to connect to the DMA (Direct Memory Access) controller. The DMA operation is controlled through the CRYP DMA control register (CRYP_DMACR). Data input using DMA DMA can be enabled for writing data into the cryptographic peripheral by setting the DIEN bit in the CRYP_DMACR register. When this bit is set, the cryptographic processor initiates a DMA request during the INPUT phase each time it requires a word to be written to the CRYP_DIN register. Table 272 shows the recommended configuration to transfer data from memory to cryptographic processor through the DMA controller. Table 272. Cryptographic processor configuration for memory-to-peripheral DMA transfers DMA channel control register field Programming recommendation Transfer size Message length, multiple of 128-bit. This 128-bit granularity corresponds to two blocks for DES, one block for AES. According to the algorithm and the mode selected, special padding/ ciphertext stealing might be required. Refer to Section 35.3.8: CRYP stealing and data padding for details. Source burst size (memory) CRYP FIFO_size /2 /transfer_width = 4 Destination burst size (peripheral) CRYP FIFO_size /2 /transfer_width = 4 (FIFO_size= 8x32-bit, transfer_width= 32-bit) DMA FIFO size CRYP FIFO_size /2 = 16 bytes Source transfer width (memory) 32-bit words Destination transfer width (peripheral) 32-bit words Source address increment (memory) Yes, after each 32-bit transfer. Destination address Fixed address of CRYP_DIN shall be used (no increment). increment (peripheral) Data output using DMA To enable the DMA for reading data from AES peripheral, set the DOEN bit in the CRYP_DMACR register. When this bit is set, the cryptographic processor initiates a DMA request during the OUTPUT phase each time it requires a word to be read from the CRYP_DOUT register. Table 273 shows the recommended configuration to transfer data from cryptographic processor to memory through the DMA controller. 1248/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Table 273. Cryptographic processor configuration for peripheral to memory DMA transfers DMA channel control register field Programming recommendation Transfer size Message length, multiple of 128-bit. This 128-bit granularity corresponds to two blocks for DES, one block for AES. Depending on the algorithm used, extra bits have to be discarded. Source burst size (peripheral) When DES is used: Single transfer (burst size=1) When AES is used: CRYP FIFO_size /2 /transfer_width = 4 (FIFO_size= 8x32-bit, transfer_width= 32-bit) Destination burst size (memory) CRYP FIFO_size /2 /transfer_width = 4 DMA FIFO size CRYP FIFO_size /2 = 16 bytes Source transfer width (peripheral) 32-bit words memory transfer width 32-bit words (memory) Source address Fixed address of CRYP_DOUT shall be used (no increment). increment (peripheral) Destination address increment (memory) Yes, after each 32-bit transfer. DMA mode When AES is used, the cryptographic processor manages two DMA transfer requests through cryp_in_dma and cryp_out_dma internal input/output signals, which are asserted: • for IN FIFO: every time a block has been read from FIFO by CRYP, • for OUT FIFO: every time a block has been written into the FIFO by the cryptographic processor. When DES is used, the cryptographic processor manages two DMA transfer requests through cryp_in_dma and cryp_out_dma internal input/output signals, which are asserted: • for IN FIFO: every time two blocks have been read from FIFO by the cryptographic processor • for OUT FIFO: every time a word has been written into the FIFO by the cryptographic processor (single transfer). Note that a burst transfer is also triggered when two blocks have been written into the FIFO. All request signals are de-asserted if the cryptographic peripheral is disabled or the DMA enable bit is cleared (DIEN bit for the IN FIFO and DOEN bit for the OUT FIFO in the CRYP_DMACR register). Caution: It is important that DMA controller empties the cryptographic peripheral output FIFO before filling up the CRYP input FIFO. To achieve it, the DMA controller should be configured so DocID029587 Rev 3 1249/3178 1268 Cryptographic processor (CRYP) RM0433 that the transfer from the peripheral to the memory has a higher priority than the transfer from the memory to the peripheral. For more detailed information on DMA operations, refer to Section 35.3.5: CRYP procedure to perform a cipher operation. 35.3.20 CRYP error management No error flags are generated by the cryptographic processor. 35.4 CRYP interrupts Overview There are two individual maskable interrupt sources generated by the cryptographic processor to signal the following events: • Input FIFO empty or not full • Output FIFO full or not empty These two sources are combined into a single interrupt signal which is the only interrupt signal from the CRYP peripheral that drives the NVIC (nested vectored interrupt controller). The interrupt logic is summarized on Figure 269. Figure 269. CRYP interrupt mapping diagram &5<3B&5&5<3(1 ,10,6 &5<3B5,65,15,6 &5<3B,06&5,1,0 &5<3B5,652875,6 &5<3B,06&5287,0 FU\SBLW ,3JOREDOLQWHUUXSW UHTXHVWVLJQDO 2870,6 06Y9 You can enable or disable CRYP interrupt sources individually by changing the mask bits in the CRYP_IMSCR register. Setting the appropriate mask bit to 1 enables the interrupt. The status of the individual maskable interrupt sources can be read either from the CRYP_RISR register, for raw interrupt status, or from the CRYP_MISR register for masked interrupt status. The status of the individual source of event flags can be read from the CRYP_SR register. Table 274 gives a summary of the available features. 1250/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Table 274. CRYP interrupt requests Interrupt event Output FIFO full Output FIFO not empty Input FIFO not full Input FIFO empty Event flag (interrupt status) Enable control bit OUTRIS, OUTMIS OUTIM and CRYPEN OUTRIS, OUTMIS INIM and CRYPEN Event flag (source) OFFU OFNE IFNF IFEM Output FIFO service interrupt - OUTMIS The output FIFO service interrupt is asserted when there is one or more (32-bit word) data items in the output FIFO. This interrupt is cleared by reading data from the output FIFO until there is no valid (32-bit) word left (that is when the interrupt follows the state of the output FIFO not empty flag OFNE). The output FIFO service interrupt OUTMIS is NOT enabled with the CRYP enable bit. Consequently, disabling the CRYP will not force the OUTMIS signal low if the output FIFO is not empty. Input FIFO service interrupt - INMIS The input FIFO service interrupt is asserted when there are less than four words in the input FIFO. It is cleared by performing write operations to the input FIFO until it holds four or more words. The input FIFO service interrupt INMIS is enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the INMIS signal is low even if the input FIFO is empty. DocID029587 Rev 3 1251/3178 1268 Cryptographic processor (CRYP) 35.5 RM0433 CRYP processing time The time required to process a 128-bit block for each mode of operation is summarized below. Table 275. Processing time (in clock cycle) for ECB, CBC and CTR per 128-bit block Algorithm/ Key size ECB CBC CTR 128b 14 14 14 192b 16 16 16 256b 18 18 18 Table 276. Processing time (in clock cycle) for GCM and CCM per 128-bit block Algorithm/ Key size GCM Init Header Payload CCM Tag Total Init Header Payload Tag Total 128b 24 10 14 14 62 12 14 25 14 65 192b 28 10 16 16 70 14 16 29 16 75 256b 32 10 18 18 78 16 18 33 18 85 1252/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 35.6 CRYP registers The cryptographic core is associated with several control and status registers, eight key registers and four initialization vectors registers. 35.6.1 CRYP control register (CRYP_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 23 22 Res. 21 20 Res. 19 18 ALGOM ODE[3] Res. rw 15 14 CRYPEN FFLUSH rw w 13 12 11 10 Res. Res. Res. Res. 9 8 KEYSIZE rw rw 7 6 DATATYPE rw rw 5 4 3 ALGOMODE[2:0] rw rw rw 17 16 GCM_CCMPH rw rw 2 1 0 ALGODIR Res. Res. rw Bits 31:20 Reserved, must be kept at reset value. Bit 19 ALGOMODE[3]: refer to bit [5:3] description Bit 18 Reserved, must be kept at reset value. Bits 17:16 GCM_CCMPH: GCM or CCM Phase selection This bitfield has no effect if GCM, GMAC or CCM algorithm is not selected in ALGOMODE field. 00: Init phase 01: Header phase 10: Payload phase 11: Final phase Bit 15 CRYPEN: CRYP processor Enable 0: Cryptographic processor peripheral is disabled 1: Cryptographic processor peripheral is enabled This bit is automatically cleared by hardware when the key preparation process ends (ALGOMODE= 0b111) or after GCM/GMAC or CCM init phase. Bit 14 FFLUSH: CRYP FIFO Flush 0: No FIFO flush 1: FIFO flush enabled When CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (i.e. read and write pointers of the FIFOs are reset). Writing this bit to 0 has no effect. When CRYPEN = 1, writing this bit to 0 or 1 has no effect. Reading this bit always returns 0. FFLUSH bit has to be set only when BUSY=0. If not, the FIFO is flushed, but the block being processed may be pushed into the output FIFO just after the flush operation, resulting in a non-empty FIFO condition. Bits 13:10 Reserved, must be kept at reset value. DocID029587 Rev 3 1253/3178 1268 Cryptographic processor (CRYP) RM0433 Bits 9:8 KEYSIZE: Key Size selection (AES mode only) This bitfield defines the bit-length of the key used for the AES cryptographic core. This bitfield is ‘don’t care’ in the DES or TDES modes. 00: 128-bit key length 01: 192-bit key length 10: 256-bit key length 11: Reserved, do not use this value Writing KEYSIZE bits while BUSY=1 has no effect. These bits can only be configured when BUSY=0. Bits 7:6 DATATYPE: Data Type selection This bitfield defines the format of data written in CRYP_DIN or read from CRYP_DOUT registers. For more details refer to Section 35.3.16: CRYP data registers and data swapping). 00: 32-bit data. No swapping for each word. First word pushed into the IN FIFO (or popped off the OUT FIFO) forms bits 1...32 of the data block, the second word forms bits 33...64 etc. 01: 16-bit data, or half-word. Each word pushed into the IN FIFO (or popped off the OUT FIFO) is considered as 2 half-words, which are swapped with each other. 10: 8-bit data, or bytes. Each word pushed into the IN FIFO (or popped off the OUT FIFO) is considered as 4 bytes, which are swapped with each other. 11: bit data, or bit-string. Each word pushed into the IN FIFO (or popped off the OUT FIFO) is considered as 32 bits (1st bit of the string at position 0), which are swapped with each other. Writing DATATYPE bits while BUSY=1 has no effect. These bits can only be configured when BUSY=0. Bits 5:3 ALGOMODE[2:0]: Algorithm mode Below definition includes the bit 19: 0000: TDES-ECB (triple-DES Electronic Codebook). 0001: TDES-CBC (triple-DES Cipher Block Chaining). 0010: DES-ECB (simple DES Electronic Codebook). 0011: DES-CBC (simple DES Cipher Block Chaining). 0100: AES-ECB (AES Electronic Codebook). 0101: AES-CBC (AES Cipher Block Chaining). 0110: AES-CTR (AES Counter Mode). 0111: AES key preparation for ECB or CBC decryption. 1000: AES-GCM (Galois Counter Mode) and AES-GMAC (Galois Message Authentication Code mode). 1001: AES-CCM (Counter with CBC-MAC). Writing ALGOMODE bits while BUSY=1 has no effect. These bits can only be configured when BUSY=0. Bit 2 ALGODIR: Algorithm Direction 0: Encrypt 1: Decrypt Writing ALGODIR bit while BUSY=1 has no effect. It can only be configured when BUSY=0. Bits 1:0 Reserved, must be kept at reset value. 1254/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 35.6.2 CRYP status register (CRYP_SR) Address offset: 0x04 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY OFFU OFNE IFNF IFEM r r r r r Bits 31:5 Reserved, must be kept at reset value. Bit 4 BUSY: Busy bit 0: The CRYP core is not processing any data. The reason is: – either that the CRYP core is disabled (CRYPEN=0 in the CRYP_CR register) and the last processing has completed, – or the CRYP core is waiting for enough data in the input FIFO or enough free space in the output FIFO (that is in each case at least 2 words in the DES, 4 words in the AES). 1: The CRYP core is currently processing a block of data or a key preparation is ongoing (AES ECB or CBC decryption only). Bit 3 OFFU: Output FIFO full flag 0: Output FIFO is not full 1: Output FIFO is full Bit 2 OFNE: Output FIFO not empty flag 0: Output FIFO is empty 1: Output FIFO is not empty Bit 1 IFNF: Input FIFO not full flag 0: Input FIFO is full 1: Input FIFO is not full Bit 0 IFEM: Input FIFO empty flag 0: Input FIFO is not empty 1: Input FIFO is empty 35.6.3 CRYP data input register (CRYP_DIN) Address offset: 0x08 Reset value: 0x0000 0000 The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section 35.3.16: CRYP data registers and data swapping for more details. DocID029587 Rev 3 1255/3178 1268 Cryptographic processor (CRYP) RM0433 When CRYP_DIN register is written to the data are pushed into the input FIFO. • If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: Note: 31 • If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. • if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATAIN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DATAIN rw rw rw rw rw rw rw rw Bits 31:0 DATAIN: Data Input On read FIFO is popped (last written value is returned), and its value is returned if CRYPEN=0. If CRYPEN=1 DATAIN register returns an undefined value. On write current register content is pushed inside the FIFO. 35.6.4 CRYP data output register (CRYP_DOUT) Address offset: 0x0C Reset value: 0x0000 0000 The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section 35.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATAOUT r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r DATAOUT 1256/3178 r r DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) Bits 31:0 DATAOUT: Data Output On read returns output FIFO content (pointed to by read pointer), else returns an undefined value. On write, no effect. 35.6.5 CRYP DMA control register (CRYP_DMACR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOEN DIEN rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 DOEN: DMA Output Enable When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. 0: DMA for outgoing data transfer is disabled 1: DMA for outgoing data transfer is enabled Bit 0 DIEN: DMA Input Enable When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. 0: DMA for incoming data transfer is disabled 1: DMA for incoming data transfer is enabled 35.6.6 CRYP interrupt mask set/clear register (CRYP_IMSCR) Address offset: 0x14 Reset value: 0x0000 0000 The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OUTIM INIM rw rw DocID029587 Rev 3 1257/3178 1268 Cryptographic processor (CRYP) RM0433 Bits 31:2 Reserved, must be kept at reset value. Bit 1 OUTIM: Output FIFO service interrupt mask 0: Output FIFO service interrupt is masked 1: Output FIFO service interrupt is not masked Bit 0 INIM: Input FIFO service interrupt mask 0: Input FIFO service interrupt is masked 1: Input FIFO service interrupt is not masked 35.6.7 CRYP raw interrupt status register (CRYP_RISR) Address offset: 0x18 Reset value: 0x0000 0001 The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OUTRIS INRIS r r Bits 31:2 Reserved, must be kept at reset value. Bit 1 OUTRIS: Output FIFO service raw interrupt status This bit gives the output FIFO interrupt information without taking CRYP_IMSCR corresponding mask into account. 0: Raw interrupt not pending 1: Raw interrupt pending Bit 0 INRIS: Input FIFO service raw interrupt status This bit gives the input FIFO interrupt information without taking CRYP_IMSCR corresponding mask into account. 0: Raw interrupt not pending 1: Raw interrupt pending 35.6.8 CRYP masked interrupt status register (CRYP_MISR) Address offset: 0x1C Reset value: 0x0000 0000 The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. 1258/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OUTMIS INMIS r r r r r r r r r r r r r r r r Bits 31:2 Reserved, must be kept at reset value. Bit 1 OUTMIS: Output FIFO service masked interrupt status This bit gives the output FIFO interrupt information without taking into account the corresponding CRYP_IMSCR mask. 0: Interrupt not pending 1: Interrupt pending Bit 0 INMIS: Input FIFO service masked interrupt status This bit gives the input FIFO interrupt information without taking into account the corresponding CRYP_IMSCR mask. 0: Interrupt not pending 1: Interrupt pending when CRYPEN= 1 35.6.9 CRYP key register 0L (CRYP_K0LR) Address offset: 0x20 Reset value: 0x0000 0000 CRYP key registers contain the cryptographic keys. • In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. • In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: – for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), – for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), – for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section 35.3.17: CRYP key registers. Note: Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K255 K254 K253 K252 K251 K250 K249 K248 K247 K246 K245 K244 K243 K242 K241 K240 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K239 K238 K237 K236 K235 K234 K233 K232 K231 K230 K229 K228 K227 K226 K225 K224 w w w w w w w w w w w w w w w w DocID029587 Rev 3 1259/3178 1268 Cryptographic processor (CRYP) RM0433 Bit x - 224 Kx: AES key bit x (x= 224 to 255) Note: This register is not used in DES mode 35.6.10 CRYP key register 0R (CRYP_K0RR) Address offset: 0x24 Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K223 K222 K221 K220 K219 K218 K217 K216 K215 K214 K213 K212 K211 K210 K209 K208 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K207 K206 K205 K204 K203 K202 K201 K200 K199 K198 K197 K196 K195 K194 K193 K192 w w w w w w w w w w w w w w w w Bit x - 192 Kx: AES key bit x (x= 192 to 223) Note: This register is not used in DES mode 35.6.11 CRYP key register 1L (CRYP_K1LR) Address offset: 0x28 Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K191 K190 K189 K188 K187 K186 K185 K184 K183 K182 K181 K180 K179 K178 K177 K176 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K175 K174 K173 K172 K171 K170 K169 K168 K167 K166 K165 K164 K163 K162 K161 K160 w w w w w w w w w w w w w w w w Bit x - 160 Kx: AES key bit x (x= 160 to 191) In DES mode, K192 corresponds to key K1 bit 1 and K160 corresponds to key K1 bit 32. 35.6.12 CRYP key register 1R (CRYP_K1RR) Address offset: 0x2C Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 1260/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K159 K158 K157 K156 K155 K154 K153 K152 K151 K150 K149 K148 K147 K146 K145 K144 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K143 K142 K141 K140 K139 K138 K137 K136 K135 K134 K133 K132 K131 K130 K129 K128 w w w w w w w w w w w w w w w w Bit x - 128 Kx: AES key bit x (x= 128 to 159) In DES mode K159 corresponds to key K1 bit 33 and K128 corresponds to key K1 bit 64. 35.6.13 CRYP key register 2L (CRYP_K2LR) Address offset: 0x30 Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K127 K126 K125 K124 K123 K122 K121 K120 K119 K118 K117 K116 K115 K114 K113 K112 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K111 K110 K109 K108 K107 K106 K105 K104 K103 K102 K101 K100 K99 K98 K97 K96 w w w w w w w w w w w w w w w w Bit x - 96 Kx: AES key bit x (x= 96 to 127) In DES mode K127 corresponds to key K2 bit 1 and K96 corresponds to key K2 bit 32. 35.6.14 CRYP key register 2R (CRYP_K2RR) Address offset: 0x34 Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K95 K95 K93 K92 K91 K90 K89 K88 K87 K86 K85 K84 K83 K82 K81 K80 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K79 K78 K77 K76 K75 K74 K73 K72 K71 K70 K69 K68 K67 K66 K65 K64 w w w w w w w w w w w w w w w w Bit x - 64 Kx: AES key bit x (x= 64 to 95) In DES mode K95 corresponds to key K2 bit 33 and K64 corresponds to key K2 bit 64. DocID029587 Rev 3 1261/3178 1268 Cryptographic processor (CRYP) 35.6.15 RM0433 CRYP key register 3L (CRYP_K3LR) Address offset: 0x38 Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K63 K62 K61 K60 K59 K58 K57 K56 K55 K54 K53 K52 K51 K50 K49 K48 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K47 K46 K45 K44 K43 K42 K41 K40 K39 K38 K37 K36 K35 K34 K33 K32 w w w w w w w w w w w w w w w w Bit x - 32 Kx: AES key bit x (x= 32 to 63) In DES mode K63 corresponds to key K3 bit 1 and K32 corresponds to key K3 bit 32. 35.6.16 CRYP key register 3R (CRYP_K3RR) Address offset: 0x3C Reset value: 0x0000 0000 Refer to Section 35.6.9: CRYP key register 0L (CRYP_K0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 K31 K30 K29 K28 K27 K26 K25 K24 K23 K22 K21 K20 K19 K18 K17 K16 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0 w w w w w w w w w w w w w w w w Bit x Kx: AES key bit x (x= 0 to 31) In DES mode K31 corresponds to key K3 bit 33 and K0 corresponds to key K3 bit 64. 35.6.17 CRYP initialization vector register 0L (CRYP_IV0LR) Address offset: 0x40 Reset value: 0x0000 0000 The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section 35.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Note: 1262/3178 Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV0 IV1 IV2 IV3 IV4 IV5 IV6 IV7 IV8 IV9 IV10 IV11 IV12 IV13 IV14 IV15 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV16 IV17 IV18 IV19 IV20 IV21 IV22 IV23 IV24 IV25 IV26 IV27 IV28 IV29 IV30 IV31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 - x IVx: Initialization vector bit x (x= 0 to 31) 35.6.18 CRYP initialization vector register 0R (CRYP_IV0RR) Address offset: 0x44 Reset value: 0x0000 0000 Refer to Section 35.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV32 IV33 IV34 IV35 IV36 IV37 IV38 IV39 IV40 IV41 IV42 IV43 IV44 IV45 IV46 IV47 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV48 IV49 IV50 IV51 IV52 IV53 IV54 IV55 IV56 IV57 IV58 IV59 IV60 IV61 IV62 IV63 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 63 - x IVx: Initialization vector bit x (x= 32 to 63) 35.6.19 CRYP initialization vector register 1L (CRYP_IV1LR) Address offset: 0x48 Reset value: 0x0000 0000 Refer to Section 35.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV64 IV65 IV66 IV67 IV68 IV69 IV70 IV71 IV72 IV73 IV74 IV75 IV76 IV77 IV78 IV79 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV80 IV81 IV82 IV83 IV84 IV85 IV86 IV87 IV88 IV89 IV90 IV91 IV92 IV93 IV94 IV95 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 95 - x IVx: Initialization vector bit x (x= 64 to 95) Note: This register is not used in DES mode 35.6.20 CRYP initialization vector register 1R (CRYP_IV1RR) Address offset: 0x4C Reset value: 0x0000 0000 Refer to Section 35.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. DocID029587 Rev 3 1263/3178 1268 Cryptographic processor (CRYP) RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV96 IV97 IV98 IV99 IV100 IV101 IV102 IV103 IV104 IV105 IV106 IV107 IV108 IV109 IV110 IV111 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV112 IV113 IV114 IV115 IV116 IV117 IV118 IV119 IV120 IV121 IV122 IV123 IV124 IV125 IV126 IV127 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 127- x IVx: Initialization vector bit x (x= 96 to 127) Note: This register is not used in DES mode 35.6.21 CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) Address offset: 0x050 + x* 0x4 (x=0 to 7) Reset value: 0x0000 0000 These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRYP_CSGCMCCMxR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRYP_CSGCMCCMxR rw rw rw rw rw rw rw rw rw Bits 31:0 CRYP_CSGCMCCMxR: CRYP internal state registers for GCM, GMAC and CCM modes. Note: This register is not used in DES/TDES or other AES modes than the ones indicated 35.6.22 CRYP context swap GCM registers (CRYP_CSGCMxR) Address offset: 0x070 + x* 0x4 (x=0 to 7) Reset value: 0x0000 0000 Please refer to Section 35.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 1264/3178 DocID029587 Rev 3 RM0433 Cryptographic processor (CRYP) 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRYP_CSGCMxR CRYP_CSGCMxR rw rw rw rw rw rw rw rw rw Bits 31:0 CRYP_CSGCMxR: CRYP internal state registers for GCM and GMAC modes. Note: This register is not used in DES/TDES or other AES modes than the ones indicated DocID029587 Rev 3 1265/3178 1268 0x20 0x24 0x38 0x3C 0x40 1266/3178 0x1C CRYP_MISR Reset value Reset value Reset value Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_K0LR CRYP_K0RR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_K3LR CRYP_K3RR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_IV0LR 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_DMACR Reset value Reset value Reset value Reset value Res. DIEN 0 Res. IFEM Res. IFNF Res. OFNE Res. OFFU Res. BUSY 0 INIM 0 Res. 0 INRIS 0 Res. 0 INMIS 0 Res. 0 DOEN 0 Res. 0 Res. 1 0 Res. 2 3 4 5 6 7 8 9 ALGODIR Res. ALGOMODE[2:0] DATATYPE KEYSIZE 11 10 Res. Res. 0 OUTIM Res. Res. 0 Res. 12 Res. Res. 0 OUTRIS Res. Res. Res. Res. Res. Res. 0 Res. 13 Res. Res. 0 OUTMIS Res. Res. Res. Res. Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. 0 Res. 14 Res. 15 FFLUSH Res. Res. 16 CRYPEN Res. 17 Res. GCM_CCMPH Res. 18 19 20 0 Res. 0 Res. Res. Res. Res. ALGOMODE[3] Res. 22 Res. 21 23 Res. 0 Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. 24 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. CRYP_DOUT 0 Res. CRYP_DIN Res. 0 Res. 0 Res. 0 Res. 25 Res. 0 Res. 0 Res. 26 Res. 0 Res. 0 Res. 27 Res. 0 Res. Res. 0 Res. 28 Res. Res. 29 Res. 0 Res. Res. 30 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 31 CRYP_CR Res. 0 Res. Res. Res. Register name Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Reset value Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. CRYP_RISR 0 Res. 0x18 0 Res. CRYP_IMSCR 0 Res. 0x14 0 Res. Reset value Res. 0x10 Reset value Res. 0x0C Res. 0x08 Res. CRYP_SR Res. 0x04 Res. 0x00 0x00 Res. Offset Res. 35.6.23 Res. Cryptographic processor (CRYP) RM0433 CRYP register map Table 277. CRYP register map and reset values 0 0 0 1 1 DATAIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAOUT 0 0 0 0 0 1 0 0 CRYP_K0LR CRYP_K0RR ... ... CRYP_K3LR CRYP_K3RR CRYP_IV0LR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Cryptographic processor (CRYP) 0x7C 0x80 0x84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 16 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM0R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM1R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM2R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM3R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM4R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM5R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM6R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCMCCM7R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM0R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM1R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM2R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM3R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM4R 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM5R Reset value 0 CRYP_IV1RR CRYP_CSGCM4R Reset value 0 CRYP_IV1LR CRYP_CSGCM3R Reset value 17 18 19 21 22 23 24 25 26 27 28 29 20 0 CRYP_CSGCM2R Reset value 0 0x78 0 CRYP_CSGCM1R Reset value 1 0x74 0 CRYP_CSGCM0R Reset value 2 0x70 0 CRYP_ CSGCMCCM7R Reset value 3 0x6C 0 CRYP_ CSGCMCCM6R Reset value 4 0x68 0 CRYP_ CSGCMCCM5R Reset value 5 0x64 0 CRYP_ CSGCMCCM4R Reset value 6 0x60 0 CRYP_ CSGCMCCM3R Reset value 7 0x5C 0 CRYP_ CSGCMCCM2R Reset value 8 0x58 0 CRYP_ CSGCMCCM1R Reset value 9 0x54 0 CRYP_ CSGCMCCM0R Reset value 11 0x50 0 CRYP_IV1RR Reset value 0 CRYP_IV0RR CRYP_IV1LR Reset value 10 0x4C Reset value 12 0x48 CRYP_IV0RR 13 0x44 Register name 30 Offset 31 Table 277. CRYP register map and reset values (continued) 0 0 0 0 0 0 CRYP_CSGCM5R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 1267/3178 1268 Cryptographic processor (CRYP) RM0433 1268/3178 9 8 7 6 5 4 3 2 1 0 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM6R 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM7R Reset value 11 Reset value 10 0x8C CRYP_CSGCM6R 12 0x88 30 Register name Offset 31 Table 277. CRYP register map and reset values (continued) 0 0 0 0 0 0 CRYP_CSGCM7R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 RM0433 Hash processor (HASH) 36 Hash processor (HASH) 36.1 Introduction The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications. HMAC algorithms provide a way of authenticating messages by means of hash functions. It consist in calling the SHA-1, SHA-224, SHA-256 or MD5 hash function twice. The hash processor computes message digests (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for messages of up to (264 – 1) bits. 36.2 HASH main features • • Suitable for data authentication applications, compliant with: – FIPS PUB 180-1 (Federal Information Processing Standards Publication 180-1) Secure Hash Standard specifications (SHA-1) – FIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2) Secure Hash Standard specifications (SHA-224 and SHA-256) – Internet Engineering Task Force (IETF) Request For Comments RFC 1321 MD5 Message-Digest Algorithm – Internet Engineering Task Force (IETF) Request For Comments RFC 2104 HMAC: Keyed-Hashing for Message Authentication Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message – Automatic 32-bit words swapping to comply with the internal little-endian representation of the input bit-string – Word swapping supported: bits, bytes, half-words and 32-bit words • Automatic padding to complete the input bit string to fit digest minimum block size of 512 bits (16 × 32 bits) • Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words, corresponding to one block size • Fast computation of SHA-1, SHA-224, SHA-256, and MD5 – 82 (respectively 66) clock cycles for processing one 512-bit block of data using SHA-1 (respectively SHA-256) algorithm – 66 clock cycles for processing one 512-bit block of data using MD5 algorithm • AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB error is generated) • 8 × 32-bit words (H0 to H7) for output message digest • Automatic data flow control with support of direct memory access (DMA) using one channel. Fixed burst of 4 supported. • Interruptible message digest computation, on a per-32-bit word basis – Re-loadable digest registers – Hashing computation suspend/resume mechanism, including using DMA DocID029587 Rev 3 1269/3178 1291 Hash processor (HASH) RM0433 36.3 HASH functional description 36.3.1 HASH block diagram Figure 270 shows the block diagram of the hash processor. ELW$+%EXV GDWDNH\ UHVXOW +$6+B+[ VWDWXV +$6+B65 FRQWURO $+% LQWHUIDFH +$6+B',1 VWDUW VZDSSLQJ %DQNHG5HJLVWHUV PDLQ [ELW ,1),)2 Figure 270. HASH block diagram GLJHVW +$6+ &RUH 6+$ 6+$ 6+$ 0' +$6+B&5 +$6+B675 %DQNHG5HJLVWHUV FRQWH[WVZDSSLQJ +$6+B&65[ KDVKBKFON +0$& ORJLF &RQWH[WVZDS %DQNHG5HJLVWHUV ,54 &5<3B,05 KDVKBLQBGPD KDVKBLW '0$ LQWHUIDFH ,54 LQWHUIDFH &RQWURO/RJLF 06Y 9 36.3.2 HASH internal signals Table 278 describes a list of useful to know internal signals available at HASH level, not at product level (on pads). Table 278. HASH internal input/output signals 36.3.3 Signal name Signal type hash_hclk2 digital input hash_it digital output hash_in_dma digital input/output Description AHB2 bus clock Hash processor global interrupt request DMA burst request/ acknowledge About secure hash algorithms The hash processor is a fully compliant implementation of the secure hash algorithm defined by FIPS PUB 180-1 standard (SHA1), FIPS PUB 180-2 standard (SHA-224, SHA256) and the IETF RFC1321 publication (MD5). With each algorithm, the HASH computes a condensed representation of a message or data file. More specifically, when a message of any length below 264 bits is provided on input, the 1270/3178 DocID029587 Rev 3 RM0433 Hash processor (HASH) SHA-1, SHA-224, SHA-256 and MD5 processing core produces respectively a 160-bit, 224 bit, 256 bit and 128-bit output string called a message digest. The message digest can then be processed with a digital signature algorithm in order to generate or verify the signature for the message. Signing the message digest rather than the message often improves the efficiency of the process because the message digest is usually much smaller in size than the message. The verifier of a digital signature has to use the same hash algorithm as the one used by the creator of the digital signature. The SHA-1, SHA-224, SHA-256 and MD5 are qualified as “secure” because it is computationally infeasible to find a message that corresponds to a given message digest, or to find two different messages that produce the same message digest. Any change to a message in transit will, with very high probability, result in a different message digest, and the signature will fail to verify. 36.3.4 Message data feeding The message (or data file) to be processed by the HASH should be considered as a bit string. Per FIPS PUB 180-1 and 180-2 standards this message bit string grows from left to right, with hexadecimal words expressed in “big-endian” convention, so that within each word, the most significant bit is stored in the left-most bit position. For example message string “abc” with a bit string representation of “01100001 01100010 01100011” is represented by a 32-bit word 0x00636261, and 8-bit words 0x61626300. Data are entered into the HASH one 32-bit word at a time, by writing them into the HASH_DIN register. The current contents of the HASH_DIN register are transferred to the 16 words input FIFO (IN FIFO) each time the register is written with new data. Hence HASH_DIN and the input FIFO form a seventeen 32-bit words length FIFO (named the IN buffer). In accordance to the kind of data to be processed (e.g. byte swapping when data are ASCII text stream) there must be a bit, byte, half-word or no swapping operation to be performed on data from the input FIFO before entering the little-endian hash processing core. Figure 271 shows how the hash processing core 32-bit data block M0...31 is constructed from one 32-bit words popped into IN FIFO by the driver, according to the DATATYPE bitfield in the HASH control register (HASH_CR). HASH_DIN data endianness when bit swapping is disabled (DATATYPE=”00”) can be described as following: the least significant bit of the message has to be at MSB position in the first word entered into the hash processor, the 32nd bit of the bit string has to be at MSB position in the second word entered into the hash processor and so on. DocID029587 Rev 3 1271/3178 1291 Hash processor (HASH) RM0433 Figure 271. Message data swapping feature '$7$7<3(³´ QRVZDSSLQJ ZULWWHQILUVW /6% 06% 6\VWHPLQWHUIDFH :RUG :RUG :RUG ELW ELW ELW 0 0 0 ELW ELW ELW ELW 0 0 0 ELW 0 0 +$6+FRUHLQWHUIDFH /6% :RUG 06% '$7$7<3(³´ ELWRUKDOIZRUGVZDSSLQJ ZULWWHQILUVW /6% ELW 0 /6% :RUG ELW ELW 0 0 06% 6\VWHPLQWHUIDFH ELW ELW :RUG ELW ELW 0 0 0 0 ELW ELW :RUG ELW ELW ELW 0 +$6+FRUHLQWHUIDFH ELW 0 :RUG ELW ELW 0 0 ELW 0 06% '$7$7<3(³´ ELWRUE\WHVZDSSLQJ ZULWWHQILUVW /6% 0 /6% 0 :RUG :RUG ELW ELW ELW ELW 06% 6\VWHPLQWHUIDFH :RUG ELW ELW ELW ELW ELW ELW ELW :RUG ELW ELW ELW ELW 0 0 0 +$6+FRUHLQWHUIDFH ELW 0 0 06% '$7$7<3(³´ ELWVZDSSLQJ /6% :RUG ELW ELW ELW 0 0 0 /6% 6\VWHPLQWHUIDFH ZULWWHQILUVW ELW ELW ELW :RUG ELW ELW ELW 0 0 0 0 0 0 :RUG ELW ELW ELW 0 0 0 +$6+FRUHLQWHUIDFH 06% :RUG ELW ELW ELW 0 0 0 ELW ELW ELW 0 0 0 06% 06Y 9 1272/3178 DocID029587 Rev 3 RM0433 36.3.5 Hash processor (HASH) Message digest computing The hash processor sequentially processes 512-bit blocks when computing the message digest. Thus, each time 16 × 32-bit words (= 512 bits) have been written to the hash processor by the DMA or the CPU, the HASH automatically starts computing the message digest. This operation is known as ‘partial digest computation’. As described in Section 36.3.4: Message data feeding, the message to be processed is entered into the HASH 32-bit word at a time, writing to the HASH_DIN register to fill the input FIFO. In order to perform the hash computation on this data below sequence shall be used by the application. 1. 2. Caution: Initialize the hash processor using the HASH_CR register: – Select the right algorithm using ALGO field. If needed program the correct swapping operation on the message input words using DATATYPE bitfield in HASH_CR. – Set MODE=1 and select the key length using LKEY if HMAC mode has been selected. – Update NBLW to define the number of valid bits in last word if it is different from 32 bits. If it is the case automatic padding could be applied by the HASH. Complete the initialization by setting to 1 the INIT bit in HASH_CR. Also set the bit DMAE to 1 if data are transferred via DMA. When programming step 2, it is important to set up before or at the same time the correct configuration values (ALGO, DATATYPE, HMAC mode, key length, NBLW). 3. Start filling data by writing to HASH_DIN register, unless data are automatically: transferred via DMA. Note that the processing of a block can start only once the last value of the block has entered the IN FIFO. The way the partial or final digest computation is managed depends on the way data are fed into the processor: a) When data are filled by software: – The partial digest computation is triggered when the software writes an additional word to the HASH_DIN register (actually the first word of the next block). Once the processor is ready again (DINIS=1 in HASH_SR), the software can write new data to HASH_DIN. This mechanism avoids the introduction of wait states by the HASH. – The final digest computation is triggered when the last block is entered and the software writes the DCAL bit to 1. If the message length is not an exact multiple of 512 bits, the NBLW field in HASH_STR register must be written prior to writing DCAL bit (see Section 36.3.6 for details). b) When data are filled by DMA as a single DMA transfer (MDMAT bit=”0”): – The partial digest computation is triggered automatically each time the FIFO is full. – The final digest computation is triggered automatically when the last block has been transferred to the HASH_DIN register (DCAL bit is set to 1 by hardware). If the message length is not an exact multiple of 512 bits, the NBLW field in HASH_STR register must be written prior to enabling the DMA (see Section 36.3.6 for details). c) When data are filled using multiple DMA transfers (MDMAT bit=”1”) : – The partial digest computations are triggered as for single DMA transfers. However the final digest computation is not triggered automatically when the last block has been transferred to the HASH_DIN register (DCAL bit is not set to 1 by hardware). It allows the hash processor to receive a new DMA transfer as part of DocID029587 Rev 3 1273/3178 1291 Hash processor (HASH) RM0433 this digest computation. To launch the final digest computation, the software must set MDMAT bit to 0 before the last DMA transfer in order to trigger the final digest computation as it is done for single DMA transfers (see description before). 4. Once computed, the digest can be read from the output registers as described in Table 279. Table 279. Hash processor outputs Algorithm Valid output registers Most significant bit Digest size (in bits) MD5 HASH_H0 to HASH_H3 HASH_H0[31] 128 SHA-1 HASH_H0 to HASH_H4 HASH_H0[31] 160 SHA-224 HASH_H0 to HASH_H6 HASH_H0[31] 224 SHA-256 HASH_H0 to HASH_H7 HASH_H0[31] 256 For more information about HMAC detailed instructions, refer to Section 36.3.7: HMAC operation. 36.3.6 Message padding Overview When computing a condensed representation of a message, the process of feeding data into the hash processor (with automatic partial digest computation every 512-bit block) loops until the last bits of the original message are written to the HASH_DIN register. As the length (number of bits) of a message can be any integer value, the last word written to the hash processor may have a valid number of bits between 1 and 32. This number of valid bits in the last word, NBLW, has to be written to the HASH_STR register, so that message padding is correctly performed before the final message digest computation. Padding processing Detailed padding sequences with DMA is enabled or disabled are described in Section 36.3.5: Message digest computing. Padding example As specified by Federal Information Processing Standards PUB 180-1 and PUB 180-2, message padding consists in appending a “1” followed by k “0”s, itself followed by a 64-bit integer that is equal to the length L in bits of the message. These three padding operations generate a padded message of length L + 1 + k + 64, which by construction is a multiple of 512 bits. For the hash processor, the “1” is added to the last word written to the HASH_DIN register at the bit position defined by the NBLW bitfield, and the remaining upper bits are cleared (“0”s). 1274/3178 DocID029587 Rev 3 RM0433 Hash processor (HASH) Example from FIPS PUB180-2 Let us assume that the original message is the ASCII binary-coded form of “abc”, of length L = 24: byte 0 byte 1 byte 2 byte 3 01100001 01100010 01100011 UUUUUUUU <-- 1st word written to HASH_DIN --> NBLW has to be loaded with the value 24: a “1” is appended at bit location 24 in the bit string (starting counting from left to right in the above bit string), which corresponds to bit 31 in the HASH_DIN register (little-endian convention): 01100001 01100010 01100011 1UUUUUUU Since L = 24, the number of bits in the above bit string is 25, and 423 “0” bits are appended, making now 448 bits. This gives in hexadecimal (byte words in big-endian format): 61626380 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 The message length value, L, in two-word format (that is 00000000 00000018) is appended. Hence the final padded message in hexadecimal (byte words in big-endian format): 61626380 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000018 If the hash processor is programmed to swap byte within HASH_DIN input register (DATATYPE=10 in HASH_CR), the above message has to be entered by following below the sequence: 1. 0xUU636261 is written to the HASH_DIN register (where ‘U’ means don’t care). 2. 0x18 is written to the HASH_STR register (the number of valid bits in the last word written to the HASH_DIN register is 24, as the original message length is 24 bits). 3. 0x10 is written to the HASH_STR register to start the message padding (described above) and then perform the digest computation. 4. The hash computing is complete with the message digest available in the HASH_Hx registers (x = 0...4) for the SHA-1 algorithm. For this FIPS example, the expected value is as follows: HASH_H0 HASH_H1 HASH_H2 HASH_H3 HASH_H4 36.3.7 = = = = = 0xA9993E36 0x4706816A 0xBA3E2571 0x7850C26C 0x9CD0D89D HMAC operation Overview As specified by Internet Engineering Task Force RFC2104, HMAC: keyed-hashing for message authentication, the HMAC algorithm is used for message authentication by irreversibly binding the message being processed to a key chosen by the user. The algorithm consists of two nested hash operations: DocID029587 Rev 3 1275/3178 1291 Hash processor (HASH) RM0433 HMAC(message) = Hash((key | pad) XOR [0x5C]n | Hash((key | pad) XOR [0x36]n | message)) where: • [X]n represents a repetition of X n times, where n equal to the size of the underlying hash function data block that is 512 bits for SHA-1, SHA224, SHA-256, MD5 hash algorithms (i.e. n=64). • pad is a sequence of zeroes needed to extend the key to the length n defined above. If the key length is greater than n, the application shall first hash the key using Hash() function and then use the resultant byte string as the actual key to HMAC. • | represents the concatenation operator. HMAC processing Four different steps are required to compute the HMAC: 1. 2. The block is initialized by writing the INIT bit to 1 with the MODE bit at 1 and the ALGO bits set to the value corresponding to the desired algorithm. The LKEY bit must also be set to 1 if the key being used is longer than 64 bytes. In this case, as required by HMAC specifications, the hash processor will use the hash of the key instead of the real key. The key to be used for the inner hash function must be provided to the hash processor: The key loading operation follows the same mechanism as the message bit string loading, i.e. write key data into HASH_DIN and complete the transfer by writing to HASH_STR register. Note: Note: Endianness details can be found in Section 36.3.4: Message data feeding. 3. Once the last key word has been entered and computation has started, the hash processor elaborates the inner key material. Once this operation has completed, it is ready to accept the message bit string as described in Section 36.3.4: Message data feeding. 4. After the final hash round, the hash processor returns “ready” to indicate that it is ready to receive the key to be used for the outer hash function (normally, this key is the same as the one used for the inner hash function). When the last word of the key is entered and computation starts, the HMAC result can be found in the HASH_H0...HASH_H7 registers. The computation latency of the HMAC primitive depends on the lengths of the keys and message, as described in Section 36.5: HASH processing time. HMAC example Below is an example of HMAC SHA-1 algorithm (ALGO=”00” and MODE=”1” in HASH_CR) as specified by NIST. Let us assume that the original message is the ASCII binary-coded form of “Sample message for keylen=blocklen”, of length L = 34 bytes. If the HASH is programmed in no swapping mode (DATATYPE=00 in HASH_CR), the following data must be loaded sequentially into HASH_DIN register: 1. Inner hash key input (lenght=64, i.e. no padding), specified by NIST. As key lenght=64, LKEY bit is set to 0 in HASH_CR register 00010203 04050607 08090A0B 0C0D0E0F 10111213 14151617 18191A1B 1C1D1E1F 20212223 24252627 28292A2B 2C2D2E2F 1276/3178 DocID029587 Rev 3 RM0433 Hash processor (HASH) 30313233 34353637 38393A3B 3C3D3E3F 2. Message input (lenght=34, i.e. padding required). HASH_STR must be set to 0x20 to start message padding and inner hash computation (see ‘U’ as don’t care) 53616D70 6C65206D 65737361 67652066 6F72206B 65796C65 6E3D626C 6F636B6C 656EUUUU 3. Outer hash key input (lenght=64, i.e. no padding). A key identical to the inner hash key is entered here. 4. Final outer hash computing is then performed by the HASH. The HMAC-SHA1 is available in the HASH_Hx registers (x = 0...4), as shown below: HASH_H0 HASH_H1 HASH_H2 HASH_H3 HASH_H4 36.3.8 = = = = = 0x5FD596EE 0x78D5553C 0x8FF4E72D 0x266DFD19 0x2366DA29 Context swapping Overview It is possible to interrupt a hash/HMAC operation to perform another processing with a higher priority. The interrupted process completes later when the higher-priority task has been processed, as shown in Figure 272. Figure 272. HASH save/restore mechanism 0HVVDJH 0HVVDJH ELWEORFN ELWEORFN 1HZKLJKHU SULRULW\PHVVDJH WREHSURFHVVHG ELWEORFN +$6+VXVSHQG VHTXHQFH ELWEORFN ELWEORFN ODVWEORFN ELWEORFN ELWEORFN +$6+UHVXPH VHTXHQFH ELWEORFN 06Y 9 To do so, the context of the interrupted task must be saved from the HASH registers to memory, and then be restored from memory to the HASH registers. The procedures where the data flow is controlled by software or by DMA are described below. DocID029587 Rev 3 1277/3178 1291 Hash processor (HASH) RM0433 Data loaded by software When the DMA is not used to load the message into the hash processor, the context can be saved only when no block processing is ongoing. This means that the user application must wait until DINIS = 1 (last block processed and input FIFO empty) or NBW ≠ 0 (FIFO not full and no processing ongoing). The detailed procedure is described below. • Current context saving Before interrupting the current message digest calculation, the application must store the contents of the following registers into memory: • – HASH_IMR – HASH_STR – HASH_CR – HASH_CSR0 to HASH_CSR53 Current context restoring To resume processing the interrupted message, the application must respect the following steps: a) Write the following registers with the values saved in memory: HASH_IMR, HASH_STR and HASH_CR. b) Initialize the hash processor by setting the INIT bit in the HASH_CR register. c) Write the HASH_CSR0 to HASH_CSR53 registers with the values saved in memory. d) Restart the processing from the point where it has been interrupted. Data loaded by DMA When the DMA is used to load the message into the hash processor, it is not possible to predict if a DMA transfer is ongoing. The user application must thus stop DMA transfers, then wait until the hash processor is ready before interrupting the current message digest calculation. The detailed procedure is described below. • Current context saving Before interrupting the current message digest calculation using DMA, the application must respect the following steps: • a) Clear the DMAE bit to disable the DMA interface. b) Wait until the current DMA transfer is complete (wait for DMAS = 0 in the HASH_SR register). Note that the block may or may not have been totally transferred to the HASH. c) Disable the corresponding channel in the DMA controller. d) Wait until the hash processor is ready (no block is being processed), that is wait for DINIS = 1 Current context restoring To resume processing the interrupted message using DMA, the application must respect the following steps: 1278/3178 a) Reconfigure the DMA controller so that it proceeds with the transfer of the message up to the end if it is not interrupted again. b) Restart the processing from the point where it was interrupted by setting the DMAE bit. DocID029587 Rev 3 RM0433 Note: Hash processor (HASH) If the context swapping does not involve HMAC operations, the HASH_CSR38 to HASH_CSR53 registers do not need to be saved and restored. If the context swapping occurs between two blocks (the last block was completely processed and the next block has not yet been pushed into the IN FIFO, NBW = 000 in the HASH_CR register), the HASH_CSR22 to HASH_CSR37 registers do not need to be saved and restored. 36.3.9 HASH DMA interface The hash processor provides an interface to connect to the DMA controller. This DMA can be used to write data to the HASH by setting the DMAE bit in the HASH_CR register. When this bit is set, the HASH asserts the burst request signal to the DMA controller when there is enough free words in the FIFO to support a burst of four words. Once four 32-bit words have been received, the HASH automatically restarts this process, checks the FIFO size, and asserts a new request if the FIFO status allow a burst reception. For more information refer to Section 36.3.5: Message digest computing. Before starting the DMA transfer, the software must program the number of valid bits in the last word that will be copied into HASH_DIN register. This is done by writing in HASH_STR register the following value: NBLW = Len(Message)% 32 where “x%32” gives the remainder of x divided by 32. DMAS bit in HASH_SR register provides information on the DMA interface activity. This bit is set with DMAE and cleared when DMAE is cleared to 0 and no DMA transfer is ongoing. Note: No interrupt is associated to DMAS bit. 36.3.10 HASH error management No error flags are generated by the HASH hardware. 36.4 HASH interrupts Two individual maskable interrupt sources are generated by the hash processor to signal following events: • Digest calculation completion (DCIS) • Data input buffer ready (DINIS) Both interrupt sources are connected to the same global interrupt request signal, as shown on Figure 273. Figure 273. HASH interrupt mapping diagram +$6+B65'&,6 +$6+B,05'&,( +$6+B65',1,6 +$6+B,05',1,( KDVKBLW ,3JOREDOLQWHUUXSW UHTXHVWVLJQDO 06Y 9 DocID029587 Rev 3 1279/3178 1291 Hash processor (HASH) RM0433 The above interrupt sources can be enabled or disabled individually by changing the mask bits in the HASH_IMR register. Setting the appropriate mask bit to 1 enables the interrupt. The status of the individual interrupt events can be read from the HASH_SR register. Table 280 gives a summary of the available features. Table 280. HASH interrupt requests Interrupt event 36.5 Event flag Enable control bit Digest computation completed flag DCIS DCIE Data input buffer ready to get a new block flag DINIS DINIE HASH processing time Table 281 summarizes the time required to process a 512-bit intermediate block for each mode of operation. Table 281. Processing time (in clock cycle) Mode of operation FIFO load(1) Computation phase Total MD5 16 50 66 SHA-1 16 66 82 SHA-224 16 50 66 SHA-256 16 50 66 1. The time required to load the 16 words of the block into the processor must be added to this value. The time required to process the last block of a message (or of a key in HMAC) can be longer. This time depends on the length of the last block and the size of the key (in HMAC mode). Compared to the processing of an intermediate block, it can be increased by the factor below: 1280/3178 • 1 to 2.5 for a hash message • ~2.5 for an HMAC input-key • 1 to 2.5 for an HMAC message • ~2.5 for an HMAC output key in case of a short key • 3.5 to 5 for an HMAC output key in case of a long key DocID029587 Rev 3 RM0433 Hash processor (HASH) 36.6 HASH registers The HASH core is associated with several control and status registers and five message digest registers. All these registers are accessible through 32-bit word accesses only, else an AHB2 error is generated. 36.6.1 HASH control register (HASH_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALGO[1] Res. LKEY rw 15 14 Res. Res. 13 12 11 10 MDMAT DINNE rw r 9 8 NBW r r 7 6 ALGO[0] MODE r r rw rw 5 4 DATATYPE rw rw rw 3 2 1 0 DMAE INIT Res. Res. rw w Bits 31:19 Reserved, must be kept at reset value. Bit 18 ALGO[1]: refer to bit 7 description Bit 17 Reserved, must be kept at reset value. Bit 16 LKEY: Long key selection This bit selects between short key (≤64 bytes) or long key (> 64 bytes) in HMAC mode. 0: Short key (≤64 bytes) 1: Long key (> 64 bytes) Note: This selection is only taken into account when the INIT bit is set and MODE= 1. Changing this bit during a computation has no effect. Bit 15 Reserved, must be kept at reset value. Bit 14 Reserved, must be kept at reset value. Bit 13 MDMAT: Multiple DMA Transfers This bit is set when hashing large files when multiple DMA transfers are needed. 0: DCAL is automatically set at the end of a DMA transfer. 1: DCAL is not automatically set at the end of a DMA transfer. Bit 12 DINNE: DIN not empty This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. 0: No data are present in the data input buffer 1: The input buffer contains at least one word of data DocID029587 Rev 3 1281/3178 1291 Hash processor (HASH) RM0433 Bits 11:8 NBW: Number of words already pushed This bitfield reflects the number of words in the message that have already been pushed into the IN FIFO. NBW increments (+1) when a write access is performed to the HASH_DIN register while DINNE = 1. It goes to zero when the INIT bit is written to 1 or when a digest calculation starts (DCAL written to 1 or DMA end of transfer). If the DMA is not used 0000 and DINNE=0: no word has been pushed into the DIN buffer, i.e. both HASH_DIN register and IN FIFO are empty. 0000 and DINNE=1: one word has been pushed into the DIN buffer, i.e. HASH_DIN register contains one word and IN FIFO is empty. 0001: two words have been pushed into the DIN buffer, i.e. HASH_DIN register and the IN FIFO contain one word each. ... 1111: 16 words have been pushed into the DIN buffer. If the DMA is used NBW is the exact number of words that have been pushed into the IN FIFO by the DMA. Bit 18 and bit 7 ALGO[1:0]: Algorithm selection These bits selects the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: SHA-1 algorithm selected 01: MD5 algorithm selected 10: SHA224 algorithm selected 11: SHA256 algorithm selected Note: This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. Bit 6 MODE: Mode selection This bit selects the HASH or HMAC mode for the selected algorithm: 0: Hash mode selected 1: HMAC mode selected. LKEY must be set if the key being used is longer than 64 bytes. Note: This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. Bits 5:4 DATATYPE: Data type selection These bits define the format of the data entered into the HASH_DIN register: 00: 32-bit data. The data written to HASH_DIN are directly used by the hash processing, without reordering. 01: 16-bit data or half-word. The data written to HASH_DIN are considered as two half-words, and are swapped before being used by the hash processing. 10: 8-bit data or bytes. The data written to HASH_DIN are considered as four bytes, and are swapped before being used by the hash processing. 11: bit data or bit-string. The data written to HASH_DIN are considered as 32 bits (1st bit of the string at position 0), and are swapped before being used by the hash processing (first bit of the string at position 31). 1282/3178 DocID029587 Rev 3 RM0433 Hash processor (HASH) Bit 3 DMAE: DMA enable 0: DMA transfers disabled 1: DMA transfers enabled. A DMA request is sent as soon as the hash core is ready to receive data. After this bit is set it is cleared by hardware while the last data of the message is written to the hash processor. Setting this bit to 0 while a DMA transfer is on-going is not aborting this current transfer. Instead, the DMA interface of the HASH remains internally enabled until the transfer is complete or INIT is written to 1. Setting INIT bit to 1 does not clear DMAE bit. Bit 2 INIT: Initialize message digest calculation Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. Writing this bit to 0 has no effect. Reading this bit always return 0. Bits 1:0 Reserved, must be kept at reset value. DocID029587 Rev 3 1283/3178 1291 Hash processor (HASH) 36.6.2 RM0433 HASH data input register (HASH_DIN) Address offset: 0x04 Reset value: 0x0000 0000 HASH_DIN is the data input register. It is 32-bit wide. This register is used to enter the message by blocks of 512 bits. When the HASH_DIN register is programmed, the value presented on the AHB databus is ‘pushed’ into the hash core and the register takes the new value presented on the AHB databus. To get a correct message format, the DATATYPE bits must have been previously configured in the HASH_CR register. When a block of 16 words has been written to the HASH_DIN register, an intermediate digest calculation is launched: • by writing new data into the HASH_DIN register (the first word of the next block) if the DMA is not used (intermediate digest calculation), • automatically if the DMA is used. When the last block has been written to the HASH_DIN register, the final digest calculation (including padding) is launched: • by writing the DCAL bit to 1 in the HASH_STR register (final digest calculation), • automatically if the DMA is used and MDMAT bit is set to 0. When a digest calculation (intermediate or final) is ongoing and a new write access to the HASH_DIN register is performed, wait-states are inserted on the AHB2 bus until the hash calculation completes. When the HASH_DIN register is read, the last word written to this location is accessed (zero after reset). . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATAIN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DATAIN rw rw rw rw rw rw rw rw Bits 31:0 DATAIN: Data input Reading this register returns the current register content. Writing this register pushes the current register content into the IN FIFO, and the register takes the new value presented on the AHB databus. 1284/3178 DocID029587 Rev 3 RM0433 Hash processor (HASH) 36.6.3 HASH start register (HASH_STR) Address offset: 0x08 Reset value: 0x0000 0000 The HASH_STR register has two functions: • It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) • It is used to start the processing of the last block in the message by writing the DCAL bit to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. DCAL Res. Res. Res. rw rw rw rw w NBLW rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 DCAL: Digest calculation Writing this bit to 1 starts the message padding, using the previously written value of NBLW, and starts the calculation of the final message digest with all data words written to the IN FIFO since the INIT bit was last written to 1. Reading this bit returns 0. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 NBLW: Number of valid bits in the last word When the last word of the message bit string is written in HASH_DIN register, the hash processor takes only the valid bits specified as below, after internal data swapping: 0x00: All 32 bits of the last data written are valid message bits i.e. M[31:0] 0x01: Only one bit of the last data written (after swapping) is valid i.e. M[0] 0x02: Only two bits of the last data written (after swapping) are valid i.e. M[1:0] 0x03: Only three bits of the last data written (after swapping) are valid i.e. M[2:0] ... 0x1F: Only 31 bits of the last data written (after swapping) are valid i.e. M[30:0] The above mechanism is valid only if DCAL=0. If NBLW bits are written while DCAL is set to 1, the NBLW bitfield remains unchanged. In other words it is not possible to configure NBLW and set DCAL at the same time. Reading NBLW bits returns the last value written to NBLW. DocID029587 Rev 3 1285/3178 1291 Hash processor (HASH) 36.6.4 RM0433 HASH digest registers (HASH_HR0..7) These registers contain the message digest result named as follows: 1. H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description In this case, the HASH_H5 to HASH_H7 register is not used, and it is read as zero. 2. A, B, C and D, respectively, in the MD5 algorithm description 3. H0 to H6, respectively, in the SHA224 algorithm description, In this case, the HASH_H4 to HASH_H7 register is not used, and it is read as zero. In this case, the HASH_H7 register is not used, and it is read as zero. 4. H0 to H7, respectively, in the SHA256 algorithm description, In all cases, the digest most significant bit is stored in HASH_H0[31]. If a read access to one of these registers is performed while the hash core is calculating an intermediate digest or a final message digest (that is when the DCAL bit has been written to 1), then the read operation is stalled until the hash calculation completes. Note: H0, H1, H2, H3 and H4 mapping are duplicated in two memory regions. HASH_HR0 Address offset: 0x0C and 0x310 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r 23 22 21 20 19 18 17 16 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r H0 r r r r r r r r 15 14 13 12 11 10 9 8 H0 r r r r r r r r HASH_HR1 Address offset: 0x10 and 0x314 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 H1 r r r r r r r r 15 14 13 12 11 10 9 8 H1 r r 1286/3178 r r r r r r DocID029587 Rev 3 RM0433 Hash processor (HASH) HASH_HR2 Address offset: 0x14 and 0x318 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r 23 22 21 20 19 18 17 16 H2 H2 r r r r r r r HASH_HR3 Address offset: 0x18 and 0x31C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r 23 22 21 20 19 18 17 16 H3 H3 r r r r r r r HASH_HR4 Address offset: 0x1C and 0x320 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H4 H4 r r r r r r r r r r r r r r r r 23 22 21 20 19 18 17 16 HASH_HR5 Address offset: 0x324 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r H5 H5 r r r r r r r r DocID029587 Rev 3 1287/3178 1291 Hash processor (HASH) RM0433 HASH_HR6 Address offset: 0x328 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H6 H6 r r r r r r r r r r r r r r r r 23 22 21 20 19 18 17 16 HASH_HR7 Address offset: 0x32C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r H7 H7 r r r r r r r r Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these registers are forced to their reset values. 36.6.5 HASH interrupt enable register (HASH_IMR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCIE DINIE rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 DCIE: Digest calculation completion interrupt enable 0: Digest calculation completion interrupt disabled 1: Digest calculation completion interrupt enabled. Bit 0 DINIE: Data input interrupt enable 0: Data input interrupt disabled 1: Data input interrupt enabled 1288/3178 DocID029587 Rev 3 RM0433 Hash processor (HASH) 36.6.6 HASH status register (HASH_SR) Address offset: 0x24 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY DMAS DCIS DINIS r r rc_w0 rc_w0 Bits 31:4 Reserved, must be kept at reset value. Bit 3 BUSY: Busy bit 0: No block is currently being processed 1: The hash core is processing a block of data Bit 2 DMAS: DMA Status This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE=0 and no DMA transfer is ongoing. No interrupt is associated with this bit. 0: DMA interface is disabled (DMAE=0) and no transfer is ongoing 1: DMA interface is enabled (DMAE=1) or a transfer is ongoing Bit 1 DCIS: Digest calculation completion interrupt status This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. 0: No digest available in the HASH_Hx registers 1: Digest calculation complete, a digest is available in the HASH_Hx registers. An interrupt is generated if the DCIE bit is set in the HASH_IMR register. Bit 0 DINIS: Data input interrupt status This bit is set by hardware when the input buffer is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. 0: Less than 16 locations are free in the input buffer 1: A new block can be entered into the input buffer. An interrupt is generated if the DINIE bit is set in the HASH_IMR register. DocID029587 Rev 3 1289/3178 1291 Hash processor (HASH) 36.6.7 RM0433 HASH context swap registers (HASH_CSRx) These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. HASH_CSR0 Address offset: 0x0F8 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CS0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 23 22 21 20 19 18 17 16 CS0 HASH_CSRx (x=1 to 53) Address offset: 0x0F8 + x * 0x4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 CSx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw CSx 1290/3178 DocID029587 Rev 3 RM0433 36.6.8 Hash processor (HASH) HASH register map Table 9 gives the summary HASH register map and reset values. 0 0 0 0 0 0 0 0 0 0 0 DCAL Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_STR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xF8 0xFC 0x1CC 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C HASH_CSR53 Reset value HASH_HR0 Reset value HASH_HR1 Reset value HASH_HR2 Reset value HASH_HR3 Reset value HASH_HR4 Reset value HASH_HR5 Reset value HASH_HR6 Reset value HASH_HR7 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 BUSY DCIS DINIS Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSR53 0 0 0 H0 0 0 H1 0 0 H2 0 0 H3 0 0 H4 0 0 H5 0 0 H6 0 0 H7 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSR0 0 0 0 0 CSR1 0 0 0 0 0 DMAS Reset value HASH_CSR0 Reset value HASH_CSR1 Reset value Res. 0x24 HASH_SR Res. Reset value DINIE 0 0 DCIE 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 NBLW Res. 0 0 Res. 0 0 Res. 0 Res. 0 H0 0 0 H1 0 0 H2 0 0 H3 0 0 H4 0 0 Res. 0 Res. 0 Res. HASH_IMR Res. 0 INIT Res. MODE 0 DMAE ALGO[0] 0 0 Reset value HASH_HR0 Reset value HASH_HR1 Reset value HASH_HR2 Reset value HASH_HR3 Reset value HASH_HR4 Reset value DATATYPE DINNE Res. .MDMAT Res. 0 0 Res. 0x20 0 0 Res. 0x1C 0 0 Res. 0x18 0 0 Res. 0x14 0 Reset value Res. 0x10 0 NBW DATAIN Res. 0x0C HASH_DIN Res. 0x08 0 Res. 0x04 0 LKEY Res. Res. Reset value ALGO[1] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HASH_CR Res. 0x00 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 282. HASH register map and reset values 1291/3178 1291 High-Resolution Timer (HRTIM) RM0433 37 High-Resolution Timer (HRTIM) 37.1 Introduction The high-resolution timer can generate up to 10 digital signals with highly accurate timings. It is primarily intended to drive power conversion systems such as switch mode power supplies or lighting systems, but can be of general purpose usage, whenever a very fine timing resolution is expected. Its modular architecture allows to generate either independent or coupled waveforms. The wave-shape is defined by self-contained timings (using counters and compare units) and a broad range of external events, such as analog or digital feedbacks and synchronization signals. This allows to produce a large variety of control signal (PWM, phase-shifted, constant Ton,...) and address most of conversion topologies. For control and monitoring purposes, the timer has also timing measure capabilities and links to built-in ADC and DAC converters. Last, it features light-load management mode and is able to handle various fault schemes for safe shut-down purposes. 1292/3178 DocID029587 Rev 3 www.st.com RM0433 37.2 High-Resolution Timer (HRTIM) Main features • • • • Multiple timing units – Full-resolution available on all outputs, possibility to adjust duty-cycle, frequency and pulse width in triggered one-pulse mode – 6 16-bit timing units (each one with an independent counter and 4 compare units) – 10 outputs that can be controlled by any timing unit, up to 32 set/reset sources per channel – Modular architecture to address either multiple independent converters with 1 or 2 switches or few large multi-switch topologies Up to 10 external events, available for any timing unit – Programmable polarity and edge sensitivity – 5 events with a fast asynchronous mode – 5 events with a programmable digital filter – Spurious events filtering with blanking and windowing modes Multiple links to built-in analog peripherals – 4 triggers to ADC converters – 3 triggers to DAC converters – 3 comparators for analog signal conditioning Versatile protection scheme – 5 fault inputs can be combined and associated to any timing unit – Programmable polarity, edge sensitivity, and programmable digital filter – dedicated delayed protections for resonant converters • Multiple HRTIM instances can be synchronized with external synchronization inputs/outputs • Versatile output stage – Full-resolution Deadtime insertion – Programmable output polarity – Chopper mode • Burst mode controller to handle light-load operation synchronously on multiple converters • 7 interrupt vectors, each one with up to 14 sources • 6 DMA requests with up to 14 sources, with a burst mode for multiple registers update DocID029587 Rev 3 1293/3178 1466 High-Resolution Timer (HRTIM) RM0433 37.3 Functional description 37.3.1 General description The HRTIM can be partitioned into several sub entities: • The master timer • The timing units (Timer A to Timer E) • The output stage • The burst mode controller • An external event and fault signal conditioning logic that is shared by all timers • The system interface The master timer is based on a 16-bit up counter. It can set/reset any of the 10 outputs via 4 compare units and it provides synchronization signals to the 5 timer units. Its main purpose is to have the timer units controlled by a unique source. An interleaved buck converter is a typical application example where the master timer manages the phase-shifts between the multiple units. The timer units are working either independently or coupled with the other timers including the master timer. Each timer contains the controls for two outputs. The outputs set/reset events are triggered either by the timing units compare registers or by events coming from the master timer, from the other timers or from external events. The output stage has several duties • Addition of deadtime when the 2 outputs are configured in complementary PWM mode • Addition of a carrier frequency on top of the modulating signal • Management of fault events, by asynchronously asserting the outputs to a predefined safe level The burst mode controller can take over the control of one or multiple timers in case of lightload operation. The burst length and period can be programmed, as well as the idle state of the outputs. The external event and fault signal conditioning logic includes: • The input selection MUXes (for instance for selecting a digital input or an on-chip source for a given external event channel) • Polarity and edge-sensitivity programming • Digital filtering (for 5 channels out of 10) The system interface allows the HRTIM to interact with the rest of the MCU: • Interrupt requests to the CPU • DMA controller for automatic accesses to/from the memories, including an HRTIM specific burst mode • Triggers for the ADC and DAC converters The HRTIM registers are split into 7 groups: 1294/3178 • Master timer registers • Timer A to Timer E registers • Common registers for features shared by all timer units DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Note: As a writing convention, references to the 5 timing units in the text and in registers are generalized using the “x” letter, where x can be any value from A to E. The block diagram of the timer is shown in Figure 274. Figure 274. High-resolution timer block diagram KUWLPBXSGBHQ > @ KUWLPBLQBV\QF> @ KUWLPBRXWBV\QF> @ 0DVWHU7LPHU 5HVHW KUWLPBGDFBWUJ> @ $3%DQG SHULSKHUDO LQWHUIDFH KUWLPBPVWBLW> @ KUWLPBGPD> @ $3%EXV '0$EXUVW FRQWUROOHU 7,0(5$ KUWLPBNHUBFN 5HVHW 7,0(5% (YHQWV 5HVHW 7,0(5& (YHQWV 5HVHW 7,0(5' (YHQWV KUWLPBEP BFN %XUVWPRGH FRQWUROOHU (YHQWV &URVVWLPHUFRXQWHUUHVHWEXV KUWLPBDGFBWUJ> @ KUWLPBEP BWUJ 6HW5HVHW FURVVEDU DWLPHUFRQWUROV RXWSXWV 5XQ,GOH +57,0B&+$ +57,0B&+$ 5XQ,GOH +57,0B&+% +57,0B&+% 5XQ,GOH 2XWSXW VWDJH +57,0B&+& +57,0B&+& 5XQ,GOH +57,0B&+' +57,0B&+' 5XQ,GOH +57,0B&+( +57,0B&+( KUWLPBSFON 5HVHW KUWLPBHYW> @ «« +57,0B)/7> @ KUWLPBLQBIOW> @ KUWLPBV\VBIOW [&03 (YHQW EODQNLQJ ZLQGRZ ([WHUQDO(YHQWV FRQGLWLRQLQJ KUWLPBHYW> @ 7,0(5( [&37 )DXOWFRQGLWLRQLQJ 06Y 9 DocID029587 Rev 3 1295/3178 1466 High-Resolution Timer (HRTIM) 37.3.2 RM0433 HRTIM pins and internal signals The table here below summarizes the HRTIM inputs and outputs, both on-chip and off-chip. Table 283. HRTIM Input/output summary Signal name Signal type HRTIM_CHA1, HRTIM_CHA2, HRTIM_CHB1, HRTIM_CHB2, HRTIM_CHC1, HRTIM_CHC2, HRTIM_CHD1, HRTIM_CHD2, HRTIM_CHE1, HRTIM_CHE2 Outputs HRTIM_FLT[5:1], hrtim_in_flt[5:1] Digital input Fault inputs: immediately disable the HRTIM outputs when asserted (5 on-chip inputs and 5 off-chip HRTIM_FLTx inputs). hrtim_sys_flt Digital input System fault gathering MCU internal fault events (Clock security system, SRAM parity error, Cortex®-M7 lockup (HardFault), PVD output). hrtim_in_sync[3:1] hrtim_out_sync[2:1] Description Main HRTIM timer outputs. They can be coupled by pairs (HRTIM_CHx1 & HRTIM_CHx2) with deadtime insertion or work independently. Synchronization inputs to synchronize the whole HRTIM with other internal or external timer resources: hrtim_in_sync1: reserved Digital Input hrtim_in_sync2: the source is a regular TIMx timer (via on-chip interconnect) hrtim_in_sync3: the source is an external HRTIM (via the HRTIM_SCIN input pins) Digital output The purpose of this output is to cascade or synchronize several HRTIM instances, either on-chip or off-chip: hrtim_out_sync1: reserved hrtim_out_sync2: the destination is an off-chip HRTIM or peripheral (via HRTIM_SCOUT output pins) hrtim_evt1[4:1] hrtim_evt2[4:1] hrtim_evt3[4:1] hrtim_evt4[4:1] hrtim_evt5[4:1] hrtim_evt6[4:1] External events. Each of the 10 events can be selected among 4 sources, Digital input either on-chip (from other built-in peripherals: comparator, ADC analog watchdog, TIMx timers, trigger outputs) or off-chip (HRTIM_EEVx input pins) hrtim_evt7[4:1] hrtim_evt8[4:1] hrtim_evt9[4:1] hrtim_evt10[4:1] hrtim_upd_en[3:1] 1296/3178 Digital input HRTIM register update enable inputs (on-chip interconnect) trigger the transfer from shadow to active registers DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Table 283. HRTIM Input/output summary (continued) Signal name Signal type hrtim_bm_trg Digital input Burst mode trigger event (on-chip interconnect) hrtim_bm_ck[4:1] Description Digital input Burst mode clock (on-chip interconnect) hrtim_adc_trg[4:1] Digital output ADC start of conversion triggers hrtim_dac_trg[3:1] Digital output DAC conversion update triggers hrtim_mst_it[7:1] Digital output Interrupt requests hrtim_dma[6:1] Digital output DMA requests hrtim_pclk Digital input APB clock Digital input HRTIM kernel clock (hereafter mentioned as fHRTIM). hrtim_ker_ck 37.3.3 Clocks The HRTIM must be supplied by the tHRTIM system clock to offer a full resolution. All clocks present in the HRTIM are derived from this reference clock. Definition of terms fHRTIM: main HRTIM clock (hrtim_ker_ck). All subsequent clocks are derived and synchronous with this source. fDTG: deadtime generator clock. For convenience, only the tDTG period (tDTG = 1/fDTG) is used in this document. fCHPFRQ: chopper stage clock source. f1STPW: clock source defining the length of the initial pulse in chopper mode. For convenience, only the t1STPW period (t1STPW = 1/f1STPW) is used in this document. fBRST: burst mode controller counter clock. fSAMPLING: clock needed to sample the fault or the external events inputs. fFLTS: clock derived from fHRTIM which is used as a source for fSAMPLING to filter fault events. fEEVS: clock derived from fHRTIM which is used as a source for fSAMPLING to filter external events. fpclk (hrtim_pclk): APB bus clock, needed for register read/write accesses DocID029587 Rev 3 1297/3178 1466 High-Resolution Timer (HRTIM) RM0433 Timer clock and prescaler Each timer in the HRTIM has its own individual clock prescaler, which allows you to adjust the timer resolution. (See Table 284). Table 284. Timer resolution and min. PWM frequency for fHRTIM = 400 MHz CKPSC[2:0](1) Prescaling ratio 101 1 400 MHz 110 2 111 4 fCOUNTER Resolution Min PWM frequency 2.5 ns 6.1 kHz 400/2 MHz = 200 MHz 5 ns 3.05 kHz 400/4 MHz = 100MHz 10 ns 1.5 kHz 1. CKPSC[2:0] values from 000 to 100 are reserved. The Full-resolution is available for edge positioning, PWM period adjustment and externally triggered pulse duration. Initialization At start-up, it is mandatory to initialize first the prescaler bitfields before writing the compare and period registers. Once the timer is enabled (MCEN or TxCEN bit set in the HRTIM_MCR register), the prescaler cannot be modified. When multiple timers are enabled, the prescalers are synchronized with the prescaler of the timer that was started first. Warning: It is possible to have different prescaling ratios in the master and TIMA..E timers only if the counter and output behavior does not depend on other timers’ information and signals. It is mandatory to configure identical prescaling ratios in these timers when one of the following events is propagated from one timing unit (or master timer) to another: output set/reset event, counter reset event, update event, external event filter or capture triggers. Prescaler factors not equal will yield to unpredictable results. Deadtime generator clock The deadtime prescaler is supplied by fHRTIM / 8 / 2(DTPRSC[2:0]), programmed with DTPRSC[2:0] bits in the HRTIM_DTxR register. tDTG ranges from 2.5 ns to 20 ns for fHRTIM = 400 MHz. 1298/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Chopper stage clock The chopper stage clock source fCHPFRQ is derived from fHRTIM with a division factor ranging from 16 to 256, so that 1.56 MHz <= fCHPFRQ <= 25 MHz for fHRTIM = 400 MHz. t1STPW is the length of the initial pulse in chopper mode, programmed with the STRPW[3:0] bits in the HRTIM_CHPxR register, as follows: t1STPW = (STRPW[3:0]+1) x 16 x tHRTIM. It uses fHRTIM / 16 as clock source (25 MHz for fHRTIM= 400 MHz). Burst Mode Prescaler The burst mode controller counter clock fBRST can be supplied by several sources, among which one is derived from fHRTIM. In this case, fBRST ranges from fHRTIM to fHRTIM / 32768 (12.2 kHz for fHRTIM = 400 MHz). Fault input sampling clock The fault input noise rejection filter has a time constant defined with fSAMPLING which can be either fHRTIM or fFLTS. fFLTS is derived from fHRTIM and ranges from 400 MHz to 50 MHz for fHRTIM = 400 MHz. External Event input sampling clock The fault input noise rejection filter has a time constant defined with fSAMPLING which can be either fHRTIM or fEEVS. fEEVS is derived from fHRTIM and ranges from 400 MHz to 50 MHz for fHRTIM = 400 MHz. DocID029587 Rev 3 1299/3178 1466 High-Resolution Timer (HRTIM) 37.3.4 RM0433 Timer A..E timing units The HRTIM embeds 5 identical timing units made of a 16-bit up-counter with an auto-reload mechanism to define the counting period, 4 compare and 2 capture units, as per Figure 275. Each unit includes all control features for 2 outputs, so that it can operate as a standalone timer. Figure 275. Timer A..E overview &37 5(3 &DSWXUH &37 5HSHWLWLRQ &DSWXUH 0DVWHU WLPHU &RXQWHU I+57,0 3UHVFDOHU 3HULRG &RXQWHU 567 5HVHW 0DQDJHPHQW &03 &RPSDUH +DOI &03 &RPSDUH 5(3 &03 &03 &03 &03 8SGDWH 2WKHU 0DVWHU 0DVWHU 0DVWHU WLPLQJXQLWV WLPHU WLPHU WLPHU 6HWUHVHW FURVVEDU RXWSXWV 3XVKSXOO DQGGHDGWLPH PDQDJHPHQW 2XW 7RWKH RXWSXW 2XW VWDJH $XWRGHOD\ &03 (YHQWV %ODQNLQJDQG ZLQGRZLQJ &RPSDUH &03 &RPSDUH 5HJLVWHU $XWRGHOD\ )URPH[WHUQDOHYHQWV FRQGLWLRQLQJ 'HQRWHVDUHJLVWHUZLWKSUHORDG ,QWHUUXSW'0$UHTXHVW 069 The period and compare values must be within a lower and an upper limit related to the high-resolution implementation and listed in Table 285: • The minimum value must be greater than or equal to 3 periods of the fHRTIM clock • The maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock Table 285. Period and Compare registers min and max values CKPSC[2:0] value(1) Min Max ≥5 0x0003 0xFFFD 1. CKPSC[2:0] values < 5 are reserved. Note: 1300/3178 A compare value greater than the period register value will not generate a compare match event. DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Counter operating mode Timer A..E can operate in continuous (free-running) mode or in single-shot manner where counting is started by a reset event, using the CONT bit in the HRTIM_TIMxCR control register. An additional RETRIG bit allows you to select whether the single-shot operation is retriggerable or non-retriggerable. Details of operation are summarized on Table 286 and on Figure 276 and Figure 277. Table 286. Timer operating modes CONT RETRIG Operating mode 0 0 0 1 1 X Start / Stop conditions Clocking and event generation Setting the TxEN bit enables the timer but does not start the counter. A first reset event starts the counting and any subsequent reset is ignored Single-shot until the counter reaches the PER value. Non-retriggerable The PER event is then generated and the counter is stopped. A reset event re-starts the counting operation from 0x0000. Single-shot Retriggerable Continuous mode Setting the TxEN bit enables the timer but does not start the counter. A reset event starts the counting if the counter is stopped, otherwise it clears the counter. When the counter reaches the PER value, the PER event is generated and the counter is stopped. A reset event re-starts the counting operation from 0x0000. Setting the TxEN bit enables the timer and starts the counter simultaneously. When the counter reaches the PER value, it rolls-over to 0x0000 and resumes counting. The counter can be reset at any time. The TxEN bit can be cleared at any time to disable the timer and stop the counting. Figure 276. Continuous timer operation 3(5 &RXQWHU 5HVHW (QDEOH &RQWLQXRXVPRGH &217 5(75,* ; 06 9 DocID029587 Rev 3 1301/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 277. Single-shot timer operation 3(5HYHQW 3(5HYHQW 3(5 &RXQWHU 5HVHW (QDEOH 6LQJOHVKRWPRGHQRQUHWULJJHUDEOH &217 5(75,* 3(5HYHQW 3(5HYHQW 3(5 &RXQWHU 5HVHW (QDEOH 6LQJOHVKRWPRGHUHWULJJHUDEOH &217 5(75,* /HJHQG 5HVHWDFWLYH 5HVHWLJQRUHG 069 Roll-over event A counter roll-over event is generated when the counter goes back to 0 after having reached the period value set in the HRTIM_PERxR register in continuous mode. This event is used for multiple purposes in the HRTIM: – To set/reset the outputs – To trigger the register content update (transfer from preload to active) – To trigger an IRQ or a DMA request – To serve as a burst mode clock source or a burst start trigger – as an ADC trigger – To decrement the repetition counter If the initial counter value is above the period value when the timer is started, or if a new period is set while the counter is already above this value, the counter is not reset: it will overflow at the maximum period value and the repetition counter will not decrement. 1302/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Timer reset The reset of the timing unit counter can be triggered by up to 30 events that can be selected simultaneously in the HRTIM_RSTxR register, among the following sources: • The timing unit: Compare 2, Compare 4 and Update (3 events) • The master timer: Reset and Compare 1..4 (5 events) • The external events EXTEVNT1..10 (10 events) • All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events) Several events can be selected simultaneously to handle multiple reset sources. In this case, the multiple reset requests are ORed. When 2 counter reset events are generated within the same fHRTIM clock cycle, the last counter reset is taken into account. Additionally, it is possible to do a software reset of the counter using the TxRST bits in the HRTIM_CR2 register. These control bits are grouped into a single register to allow the simultaneous reset of several counters. The reset requests are taken into account only once the related counters are enabled (TxCEN bit set). When the fHRTIM clock prescaling ratio is above 1, the counter reset event is delayed to the next active edge of the prescaled clock. This allows to maintain a jitterless waveform generation when an output transition is synchronized to the reset event (typically a constant Ton time converter). Figure 278 shows how the reset is handled for a clock prescaling ratio of 4 (fHRTIM divided by 4). Figure 278. Timer reset resynchronization (prescaling ratio above 32) Ĩ,Zd/D WƌĞƐĐĂůĞĚ ĐůŽĐŬ ZĞƐĞƚ ĞǀĞŶƚ ŽƵŶƚĞƌ ϱ ϭ Ϯ Ϭ ϭ ŽƵŶƚĞƌ ;W ZсϱͿ dϭ dϭ͗^ĞƚŽŶdŝŵĞƌƌĞƐĞƚĞǀĞŶƚ͕ZĞƐĞƚŽŶŽŵƉĂƌĞϭсϮ DocID029587 Rev 3 D^ϯϮϮϲϭsϭ 1303/3178 1466 High-Resolution Timer (HRTIM) RM0433 Repetition counter A common software practice is to have an interrupt generated when the period value is reached, so that the maximum amount of time is left for processing before the next period begins. The main purpose of the repetition counter is to adjust the period interrupt rate and off-load the CPU by decoupling the switching frequency and the interrupt frequency. The timing units have a repetition counter. This counter cannot be read, but solely programmed with an auto-reload value in the HRTIM_REPxR register. The repetition counter is initialized with the content of the HRTIM_REPxR register when the timer is enabled (TXCEN bit set). Once the timer has been enabled, any time the counter is cleared, either due to a reset event or due to a counter roll-over, the repetition counter is decreased. When it reaches zero, a REP interrupt or a DMA request is issued if enabled (REPIE and REPDE bits in the HRTIM_DIER register). If the HRTIM_REPxR register is set to 0, an interrupt is generated for each and every period. For any value above 0, a REP interrupt is generated after (HRTIM_REPxR + 1) periods. Figure 279 presents the repetition counter operation for various values, in continuous mode. Figure 279. Repetition rate vs HRTIM_REPxR content in continuous mode W Z ŽƵŶƚĞƌ ,Zd/DͺZ WdžZсϬ ϬΎ ϬΎ Z WĞǀĞŶƚ ,Zd/DͺZ WdžZсϭ ϬΎ Z W ϭΎ ϬΎ Z W ϬΎ Z W ,Zd/DͺZ WdžZсϮ ϭΎ ϬΎ ϬΎ Z W Z W ϭΎ Z W ϮΎ ϬΎ Z W ΎĚĞŶŽƚĞƐƌĞƉĞƚŝƚŝŽŶĐŽƵŶƚĞƌŝŶƚĞƌŶĂůǀĂůƵĞƐ;ŶŽƚƌĞĂĚĂďůĞ͕ĨŽƌĞdžƉůĂŶĂƚŝŽŶƉƵƌƉŽƐĞŽŶůLJͿ D^ϯϮϮϲϮsϭ The repetition counter can also be used when the counter is reset before reaching the period value (variable frequency operation) either in continuous or in single-shot mode (Figure 280 here-below). The reset causes the repetition counter to be decremented, at the exception of the very first start following counter enable (TxCEN bit set). 1304/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 280. Repetition counter behavior in single-shot mode W Z ŽƵŶƚĞƌ ZĞƐĞƚ ϬΎ ϭΎ ϮΎ ϮΎ ϭΎ ϬΎ Z WĞǀĞŶƚ ΎĚĞŶŽƚĞƐƌĞƉĞƚŝƚŝŽŶĐŽƵŶƚĞƌŝŶƚĞƌŶĂůǀĂůƵĞƐ;ŶŽƚƌĞĂĚĂďůĞ͕ĨŽƌĞdžƉůĂŶĂƚŝŽŶƉƵƌƉŽƐĞŽŶůLJͿ D^ϯϮϮϲϯsϭ A reset or start event from the hrtim_in_sync[3:1] source causes the repetition to be decremented as any other reset. However, in SYNCIN-started single-shot mode (SYNCSTRTx bit set in the HRTIM_TIMxCR register), the repetition counter will be decremented only on the 1st reset event following the period. Any subsequent reset will not alter the repetition counter until the counter is re-started by a new request on hrtim_in_sync[3:1] inputs. Set / reset crossbar A “set” event correspond to a transition to the output active state, while a “reset” event corresponds to a transition to the output inactive state. The polarity of the waveform is defined in the output stage to accommodate positive or negative logic external components: an active level corresponds to a logic level 1 for a positive polarity (POLx = 0), and to a logic level 0 for a negative polarity (POLx = 1). Each of the timing units handles the set/reset crossbar for two outputs. These 2 outputs can be set, reset or toggled by up to 32 events that can be selected among the following sources: – The timing unit: Period, Compare 1..4, register update (6 events) – The master timer: Period, Compare 1..4, HRTIM synchronization (6 events) – All other timing units (e.g. Timer B..E for timer A): TIMEVNT1..9 (9 events described in Table 287) – The external events EXTEVNT1..10 (10 events) – A software forcing (1 event) The event sources are ORed and multiple events can be simultaneously selected. Each output is controlled by two 32-bit registers, one coding for the set (HRTIM_SETxyR) and another one for the reset (HRTIM_RSTxyR), where x stands for the timing unit: A..E and y stands for the output 1or 2 (e.g. HRTIM_SETA1R, HRTIM_RSTC2R,...). If the same event is selected for both set and reset, it will toggle the output. It is not possible to toggle the output state more than one time per tHRTIM period: in case of two consecutive toggling events within the same cycle, only the first one is considered. The set and reset requests are taken into account only once the counter is enabled (TxCEN bit set), except if the software is forcing a request to allow the prepositioning of the outputs at timer start-up. DocID029587 Rev 3 1305/3178 1466 High-Resolution Timer (HRTIM) RM0433 Table 287 summarizes the events from other timing units that can be used to set and reset the outputs. The number corresponds to the timer events (such as TIMEVNTx) listed in the register, and empty locations are indicating non-available events. For instance, Timer A outputs can be set or reset by the following events: Timer B Compare1, 2 and 4, Timer C Compare 2 and 3,... and Timer E Compare 3 will be listed as TIMEVNT8 in HRTIM_SETA1R. Table 287. Events mapping across Timer A to E Timer A CMP4 CMP1 CMP2 CMP3 CMP4 CMP1 CMP2 CMP3 CMP4 CMP1 CMP2 CMP3 CMP4 CMP1 CMP2 CMP3 CMP4 Timer E CMP3 Timer D CMP2 Timer C CMP1 Destination Source Timer B Timer A - - - - 1 2 - 3 - 4 5 - 6 7 - - - - 8 9 Timer B 1 2 - 3 - - - - - - 4 5 - - 6 7 8 9 - - Timer C - 1 2 - - 3 4 - - - - - - 5 - 6 - 7 8 9 Timer D 1 - - 2 - 3 - 4 5 - 6 7 - - - - 8 - - 9 Timer E - - 1 2 - - 3 4 5 6 - - 7 8 - 9 - - - - Figure 281 represents how a PWM signal is generated using two compare events. Figure 281. Compare events action on outputs: set on compare 1, reset on compare 2 I+57,0 &ORFN &RXQWHU &03UHJLVWHUV YDOXHLVXSGDWHG ZKHQFRXQWHU UROOVRYHU +57,0B&03$5 [ +57,0B&03$5 [ 7$ 2XWSXW 5HJLVWHUVHWWLQJ +57,0B6(7$5 [+57,0B567$5 [ 06Y 9 1306/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Set/Reset on Update events Half mode This mode aims at generating square signal with fixed 50% duty cycle and variable frequency (typically for converters using resonant topologies). It allows to have the duty cycle automatically forced to half of the period value when a new period is programmed. This mode is enabled by writing HALF bit to 1 in the HRTIM_TIMxCR register. When the HRTIM_PERxR register is written, it causes an automatic update of the Compare 1 value with HRTIM_PERxR/2 value. The output on which a square wave is generated must be programmed to have one transition on CMP1 event, and one transition on the period event, as follows: – HRTIM_SETxyR = 0x0000 0008, HRTIM_RSTxyR = 0x0000 0004, or – HRTIM_SETxyR = 0x0000 0004, HRTIM_RSTxyR = 0x0000 0008 The HALF mode overrides the content of the HRTIM_CMP1xR register. The access to the HRTIM_PERxR register only causes Compare 1 internal register to be updated. The useraccessible HRTIM_CMP1xR register is not updated with the HRTIM_PERxR / 2 value. When the preload is enabled (PREEN = 1, MUDIS, TxUDIS), Compare 1 active register is refreshed on the Update event. If the preload is disabled (PREEN= 0), Compare 1 active register is updated as soon as HRTIM_PERxR is written. The period must be greater than or equal to 6 periods of the fHRTIM clock when the HALF mode is enabled. Capture The timing unit has the capability to capture the counter value, triggered by internal and external events. The purpose is to: • measure events arrival timings or occurrence intervals • update Compare 2 and Compare 4 values in auto-delayed mode (see Auto-delayed mode). The capture is done with fHRTIM resolution. The timer has 2 capture registers: HRTIM_CPT1xR and HRTIM_CPT2xR. The capture triggers are programmed in the HRTIM_CPT1xCR and HRTIM_CPT2xCR registers. The capture of the timing unit counter can be triggered by up to 28 events that can be selected simultaneously in the HRTIM_CPT1xCR and HRTIM_CPT2xCR registers, among the following sources: • The external events, EXTEVNT1..10 (10 events) • All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and output 1 set/reset events (16 events) • The timing unit: Update (1 event) • A software capture (1 event) Several events can be selected simultaneously to handle multiple capture triggers. In this case, the concurrent trigger requests are ORed. The capture can generate an interrupt or a DMA request when CPTxIE and CPTxDE bits are set in the HRTIM_TIMxDIER register. Over-capture is not prevented by the circuitry: a new capture is triggered even if the previous value was not read, or if the capture flag was not cleared. DocID029587 Rev 3 1307/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 282. Timing unit capture circuitry DWϭ DWϮ dϭƐĞƚ dϭƌĞƐĞƚ dŝŵĞƌ dŝŵĞƌ dŝŵĞƌ dŝŵĞƌ ϰ ϰ ϰ ĂƉƚƵƌĞϭ dƌŝŐŐĞƌ ƐĞůĞĐƚŝŽŶ ;KZͿ ĂƉƚƵƌĞϭƌĞŐŝƐƚĞƌ džƚĞƌŶĂůĞǀĞŶƚƐϭ͘͘ϭϬ dŝŵĞƌhƉĚĂƚĞ ϭϬ Wdϭ ;/ZYΘDͿ ^ŽĨƚǁĂƌĞ ĂƉƚƵƌĞ Ĩ,Zd/D WƌĞƐĐĂůĞƌ dŝŵĞƌĐŽƵŶƚĞƌ D^ϯϮϮϲϱsϭ Auto-delayed mode This mode allows to have compare events generated relatively to capture events, so that for instance an output change can happen with a programmed timing following a capture. In this case, the compare match occurs independently from the timer counter value. It enables the generation of waveforms with timings synchronized to external events without the need of software computation and interrupt servicing. As long as no capture is triggered, the content of the HRTIM_CMPxR register is ignored (no compare event is generated when the counter value matches the Compare value. Once the capture is triggered, the compare value programmed in HRTIM_CMPxR is summed with the captured counter value in HRTIM_CPTxyR, and it updates the internal auto-delayed compare register, as seen on Figure 283. The auto-delayed compare register is internal to the timing unit and cannot be read. The HRTIM_CMPxR preload register is not modified after the calculation. This feature is available only for Compare 2 and Compare 4 registers. Compare 2 is associated with capture 1, while Compare 4 is associated with capture 2. HRTIM_CMP2xR and HRTIM_CMP4xR Compares cannot be programmed with a value below 3 fHRTIM clock periods, as in the regular mode. 1308/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 283. Auto-delayed overview (Compare 2 only) ĂƉƚƵƌĞϭ ŽƵŶƚĞƌ ͊ϬϬ dƌŝŐŐĞƌ͗Wdϭ͕ DWϭŽƌDWϯ >DWϮϭ͘͘Ϭ ƵƚŽĚĞůĂLJĞĚ ŽŵƉĂƌĞϮ ĚĚ ŽŵƉĂƌĞϮ >DWϮϭ͘͘Ϭ ŽŵƉĂƌĞϭ ŽŵƉĂƌĞϯ ϭϬ dŝŵĞŽƵƚĨĞĂƚƵƌĞŝĨ >DWϮϭ͘͘Ϭсϭdž ϬϬ ϭϭ D^ϯϮϮϲϲsϭ The auto-delayed Compare is only valid from the capture up to the period event: once the counter has reached the period value, the system is re-armed with Compare disabled until a capture occurs. DELCMP2[1:0] and DELCMP4[1:0] bits in HRTIM_TIMxCR register allow to configure the auto-delayed mode as follows: • 00 Regular compare mode: HRTIM_CMP2xR and HRTIM_CMP4xR register contents are directly compared with the counter value. • 01 Auto-delayed mode: Compare 2 and Compare 4 values are recomputed and used for comparison with the counter after a capture 1/2 event. DocID029587 Rev 3 1309/3178 1466 High-Resolution Timer (HRTIM) • RM0433 1X Auto-delayed mode with timeout: Compare 2 and Compare 4 values are recomputed and used for comparison with the counter after a capture 1/2 event or after a Compare 1 match (DELCMPx[1:0]= 10) or a Compare 3 match (DELCMPx[1:0]= 11) to have a timeout function if capture 1/2 event is missing. When the capture occurs, the comparison is done with the (HRTIM_CMP2/4xR + HRTIM_CPT1/2xR) value. If no capture is triggered within the period, the behavior depends on the DELCMPx[1:0] value: • DELCMPx[1:0] = 01: the compare event is not generated • DELCMPx[1:0] = 10 or 11: the comparison is done with the sum of the 2 compares (for instance HRTIM_CMP2xR + HRTIM_CMP1xR). The captures are not taken into account if they are triggered after CMPx + CMP1 (resp. CMPx + CMP3). The captures are enabled again at the beginning of the next PWM period. If the result of the auto-delayed summation is above 0xFFFF (overflow), the value is ignored and no compare event will be generated until a new period is started. Note: DELCMPx[1:0] bitfield must be reset when reprogrammed from one value to the other to reinitialize properly the auto-delayed mechanism, for instance: • DELCMPx[1:0] = 10 • DELCMPx[1:0] = 00 • DELCMPx[1:0] = 11 As an example, Figure 284 shows how the following signal can be generated: Note: • Output set when the counter is equal to Compare 1 value • Output reset 4 cycles after a falling edge on a given external event To simplify the figure, the external event signal is shown without any resynchronization delay: practically, there is a delay of 1 to 2 fHRTIM clock periods between the falling edge and the capture event due to an internal resynchronization stage which is necessary to process external input signals. Figure 284. Auto-delayed compare 8SGDWH &RXQWHU +57,0B&37[5 3UHYLRXV 0DWFK +57,0B&03[5 3UHORDG DFWLYH 3UHORDG DFWLYH 3UHORDG DFWLYH 0DWFK +57,0B&03[5 &DSWXUH ([WHUQDOHYHQW 2XWSXW F\FOHV 06Y9 A regular compare channel (e.g. Compare 1) is used for the output set: as soon as the counter matches the content of the compare register, the output goes to its active state. 1310/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) A delayed compare is used for the output reset: the compare event can be generated only if a capture event has occurred. No event is generated when the counter matches the delayed compare value (counter = 4). Once the capture event has been triggered by the external event, the content of the capture register is summed to the delayed compare value to have the new compare value. In the example, the auto-delayed value 4 is summed to the capture equal to 7 to give a value of 12 in the auto-delayed compare register. From this time on, the compare event can be generated and will happen when the counter is equal to 12, causing the output to be reset. Overcapture management in auto-delayed mode Overcapture is prevented when the auto-delayed mode is enabled (DELCMPx[1:0] = 01, 10, 11). When multiple capture requests occur within the same counting period, only the first capture is taken into account to compute the auto-delayed compare value. A new capture is possible only: • Once the auto-delayed compare has matched the counter value (compare event) • Once the counter has rolled over (period) • Once the timer has been reset Changing auto-delayed compare values When the auto-delayed compare value is preloaded (PREEN bit set), the new compare value is taken into account on the next coming update event (for instance on the period event), regardless of when the compare register was written and if the capture occurred (see Figure 284, where the delay is changed when the counter rolls over). When the preload is disabled (PREEN bit reset), the new compare value is taken into account immediately, even if it is modified after the capture event has occurred, as per the example below: 1. At t1, DELCMP2 = 1. 2. At t2, CMP2_act = 0x40 => comparison disabled 3. At t3, a capture event occurs capturing the value CPTR1 = 0x20. => comparison enabled, compare value = 0x60 4. At t4, CMP2_act = 0x100 (before the counter reached value CPTR1 + 0x40) => comparison still enabled, new compare value = 0x120 5. At t5, the counter reaches the period value => comparison disabled, cmp2_act = 0x100 Similarly, if the CMP1(CMP3) value changes while DELCMPx = 10 or 11, and preload is disabled: 1. At t1, DELCMP2 = 2. 2. At t2, CMP2_act = 0x40 => comparison disabled 3. At t3, CMP3 event occurs - CMP3_act = 0x50 before capture 1 event occurs => comparison enabled, compare value = 0x90 4. At t4, CMP3_act = 0x100 (before the counter reached value 0x90) => comparison still enabled, Compare 2 event will occur at = 0x140 DocID029587 Rev 3 1311/3178 1466 High-Resolution Timer (HRTIM) RM0433 Push-pull mode This mode primarily aims at driving converters using push-pull topologies. It also needs to be enabled when the delayed idle protection is required, typically for resonant converters (refer to Section 37.3.9: Delayed Protection). The push-pull mode is enabled by setting PSHPLL bit in the HRTIM_TIMxCR register. It applies the signals generated by the crossbar to output 1 and output 2 alternatively, on the period basis, maintaining the other output to its inactive state. The redirection rate (push-pull frequency) is defined by the timer’s period event, as shown on Figure 285. The push-pull period is twice the timer counting period. Figure 285. Push-pull mode block diagram KƵƚϭ;ĨƌŽŵĐƌŽƐƐƐďĂƌͿ Ϭ /ŶĂĐƚŝǀĞ Ϭ KƵƚϭ ϭ ϭ WƵƐŚͲWƵůů ůŽŐŝĐ ZŽůůͲŽǀĞƌ ĞǀĞŶƚƐ W^,W>> Ϭ /ŶĂĐƚŝǀĞ KƵƚϮ;ĨƌŽŵĐƌŽƐƐƐďĂƌͿ ϭ dŽƚŚĞ ŽƵƚƉƵƚ ƐƚĂŐĞ ϭ KƵƚϮ Ϭ D^ϯϮϮϲϴsϭ The push-pull mode is only available when the timer operates in continuous mode: the counter must not be reset once it has been enabled (TxCEN bit set). It is necessary to disable the timer to stop a push-pull operation and to reset the counter before re-enabling it. The signal shape is defined using HRTIM_SETxyR and HRTIM_RSTxyR for both outputs. It is necessary to have HRTIM_SETx1R = HRTIM_SETx2R and HRTIM_RSTx1R = HRTIM_RSTx2R to have both outputs with identical waveforms and to achieve a balanced operation. Still, it is possible to have different programming on both outputs for other uses. Note: The push-pull operation cannot be used when a deadtime is enabled (mutually exclusive functions). The CPPSAT status bit in HRTIM_TIMxISR indicates on which output the signal is currently active. CPPSTAT is reset when the push-pull mode is disabled. In the example given on Figure 286, the timer internal waveform is defined as follows: 1312/3178 • Output set on period event • Output reset on Compare 1 match event DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 286. Push-pull mode example WĞƌŝŽĚ ŽƵŶƚĞƌ ŽŵƉĂƌĞϭ ZŽůůͲŽǀĞƌĞǀĞŶƚƐ WƵƐŚͲWƵůůůŽŐŝĐ ƌŽƐƐďĂƌŽƵƚƉƵƚ ^ĞƚŽŶ ƉĞƌŝŽĚ ZĞƐĞƚŽŶ ĐŽŵƉĂƌĞϭ KƵƚƉƵƚϭ KƵƚƉƵƚϮ D^ϯϮϮϲϵsϭ Deadtime A deadtime insertion unit allows to generate a couple of complementary signals from a single reference waveform, with programmable delays between active state transitions. This is commonly used for topologies using half-bridges or full bridges. It simplifies the software: only 1 waveform is programmed and controlled to drive two outputs. The Dead time insertion is enabled by setting DTEN bit in HRTIM_OUTxR register. The complementary signals are built based on the reference waveform defined for output 1, using HRTIM_SETx1R and HRTIM_RSTx1R registers: HRTIM_SETx2R and HRTIM_RSTx2R registers are not significant when DTEN bit is set. Note: The deadtime cannot be used simultaneously with the push-pull mode. Two deadtimes can be defined in relationship with the rising edge and the falling edge of the reference waveform, as in Figure 287. Figure 287. Complementary outputs with deadtime insertion &RXQWHU &RPSDUH &URVVEDURXWSXW 'HDGWLPHULVLQJ 'HDGWLPHIDOOLQJ 2XWSXW 2XWSXW 069 DocID029587 Rev 3 1313/3178 1466 High-Resolution Timer (HRTIM) RM0433 Negative deadtime values can be defined when some control overlap is required. This is done using the deadtime sign bits (SDTFx and SDTRx bits in HRTIM_DTxR register). Figure 288 shows complementary signal waveforms depending on respective signs. Figure 288. Deadtime insertion vs deadtime sign (1 indicates negative deadtime) KƵƚϭ;ĨƌŽŵĐƌŽƐƐďĂƌͿ ĞĂĚƚŝŵĞƌŝƐŝŶŐ ĞĂĚƚŝŵĞĨĂůůŝŶŐ ^dZdžсϬ ^d&džсϬ ^dZdžсϭ ^d&džсϭ ^dZdžсϬ ^d&džсϭ ^dZdžсϭ ^d&džсϬ D^ϯϮϮϳϭsϭ The deadtime values are defined with DTFx[8:0] and DTRx[8:0] bitfields and based on a specific clock prescaled according to DTPRSC[2:0] bits, as follows: tDTx = +/- DTx[8:0] x tDTG where x is either R or F and tDTG = (2(DTPRSC[2:0])) x tHRTIM. Table 288 gives the resolution and maximum absolute values depending on the prescaler value. Table 288. Deadtime resolution and max absolute values DTPRSC[2:0](1) tDTG tDTx max tDTG (ns) |tDTx| max (µs) 011 tHRTIM 2.5 1.28 100 2 * tHRTIM 5 2.56 101 4 * tHRTIM 10 5.11 110 8 * tHRTIM 20 10.22 111 16 * tHRTIM 40 20.44 511 * tDTG 1. DTPRSC[2:0] values 000, 001, 010 are reserved. 1314/3178 fHRTIM= 400 MHz DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 289 to Figure 292 present how the deadtime generator behaves for reference waveforms with pulsewidth below the deadtime values, for all deadtime configurations. Figure 289. Complementary outputs for low pulse width (SDTRx = SDTFx = 0) ZĞĨ͘ d& dZ dϭ dϮ ĞĂĚƚŝŵĞƌŝƐŝŶŐ ƐŬŝƉƉĞĚ ĞĂĚƚŝŵĞĨĂůůŝŶŐ ƐŬŝƉƉĞĚ D^ϯϮϮϳϮsϭ Figure 290. Complementary outputs for low pulse width (SDTRx = SDTFx = 1) ZĞĨ͘ d& dϭ dZ dϮ ĞĂĚƚŝŵĞƌŝƐŝŶŐ ƐŬŝƉƉĞĚ ĞĂĚƚŝŵĞĨĂůůŝŶŐ ƐŬŝƉƉĞĚ D^ϯϮϮϳϯsϭ Figure 291. Complementary outputs for low pulse width (SDTRx = 0, SDTFx = 1) ZĞĨ͘ dϭ dϮ ĞĂĚƚŝŵĞĨĂůůŝŶŐ ĂŶĚƌŝƐŝŶŐƐŬŝƉƉĞĚ ĞĂĚƚŝŵĞĨĂůůŝŶŐ ĂŶĚƌŝƐŝŶŐƐŬŝƉƉĞĚ D^ϯϮϮϳϰsϭ DocID029587 Rev 3 1315/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 292. Complementary outputs for low pulse width (SDTRx = 1, SDTFx=0) 5HI 7$ 7$ 'HDGWLPH)DOOLQJ DQGULVLQJVNLSSHG 'HDGWLPH)DOOLQJ DQGULVLQJVNLSSHG 069 For safety purposes, it is possible to prevent any spurious write into the deadtime registers by locking the sign and/or the value of the deadtime using DTFLKx, DTRLKx, DTFSLKx and DTRSLKx. Once these bits are set, the related bits and bitfields are becoming read only until the next system reset. Caution: DTEN bit must not be changed in the following cases: - When the timer is enabled (TxEN bit set) - When the timer outputs are set/reset by another timer (while TxEN is reset) Otherwise, an unpredictable behavior would result. It is therefore necessary to disable the timer (TxCEN bit reset) and have the corresponding outputs disabled. For the particular case where DTEN must be set while the burst mode is enabled with a deadtime upon entry (BME = 1, DIDL = 1, IDLEM = 1), it is necessary to force the two outputs in their IDLES state by software commands (SST, RST bits) before setting DTEN bit. This is to avoid any side effect resulting from a burst mode entry that would happen immediately before a deadtime enable. 1316/3178 DocID029587 Rev 3 RM0433 37.3.5 High-Resolution Timer (HRTIM) Master timer The main purpose of the master timer is to provide common signals to the 5 timing units, either for synchronization purpose or to set/reset outputs. It does not have direct control over any outputs, but still can be used indirectly by the set/reset crossbars. Figure 293 provides an overview of the master timer. Figure 293. Master timer overview 5(3 ([WHUQDO 6\QFKURQL]DWLRQ 8QLW 5HSHWLWLRQ 6<1& &RXQWHU I+57,0 3UHVFDOHU 6WDUW FN 5HVHW &RXQWHU 3HULRG 5(3 &03 &03 &03 &03 &RPSDUH +DOI 7R7LPHU $( FURVVEDUV &03 6<1& &03 &RPSDUH &03 &RPSDUH &03 5HJLVWHU 'HQRWHVDUHJLVWHUZLWKSUHORDG ,QWHUUXSW'0$UHTXHVW &RPSDUH 069 The master timer is based on the very same architecture as the timing units, with the following differences: • It does not have outputs associated with, nor output related control • It does not have its own crossbar unit, nor push-pull or deadtime mode • It can only be reset by the external synchronization circuitry • It does not have a capture unit, nor the auto-delayed mode • It does not include external event blanking and windowing circuitry • It has a limited set of interrupt / DMA requests: Compare 1..4, repetition, register update and external synchronization event. The master timer control register includes all the timer enable bits, for the master and Timer A..E timing units. This allows to have all timer synchronously started with a single write access. It also handles the external synchronization for the whole HRTIM timer (see Section 37.3.17: Synchronizing the HRTIM with other timers or HRTIM instances), with both MCU internal and external (inputs/outputs) resources. DocID029587 Rev 3 1317/3178 1466 High-Resolution Timer (HRTIM) RM0433 Master timer control registers are mapped with the same offset as the timing units’ registers. 37.3.6 Set/reset events priorities and narrow pulses management This section describes how the output waveform is generated when several set and/or reset requests are occurring within 3 consecutive tHRTIM periods. An arbitration is performed during each tHRTIM period, in 2 steps: 1. For each active event, the desired output transition is determined (set, reset or toggle). 2. A predefined arbitration is performed among the active events (from highest to lowest priority CMP4 → CMP3 → CMP2 → CMP1 → PER, see Concurrent set request / Concurrent reset requests. When set and reset requests from two different sources are simultaneous, the reset action has the highest priority. Concurrent set request / Concurrent reset requests When multiple sources are selected for a set event, an arbitration is performed when the set requests occur within the same fHRTIM clock period. In case of multiple requests from adjacent timers (TIMEVNT1..9), the request which occurs first is taken into account. The arbitration is done in 2 steps, depending on the source (from the highest to the lowest priority): CMP4 → CMP3 → CMP2 → CMP1. If multiple requests from the master timer occur within the same fHRTIM clock period, a predefined arbitration is applied and a single request will be taken into account (from the highest to the lowest priority): MSTCMP4 → MSTCMP3 → MSTCMP2 → MSTCMP1 → MSTCMPER When multiple requests internal to the timer occur within the same fHRTIM clock period, a predefined arbitration is applied and the requests are taken with the following priority, whatever the effective timing (from highest to lowest): CMP4 → CMP3 → CMP2 → CMP1 → PER Note: Practically, this is of a primary importance only when using auto-delayed Compare 2 and Compare 4 simultaneously (i.e. when the effective set/reset cannot be determined a priori because it is related to an external event). In this case, the highest priority signal must be affected to the CMP4 event. Last, the highest priority is given to non timing-related: EXTEVNT1..10, RESYNC (coming from SYNC event if SYNCRSTx or SYNCSTRTx is set or from a software reset), update and software set (SST). As a summary, in case of simultaneous events, the effective set (reset) event will be arbitrated between: • Any TIMEVNT1..9 event • A single source from the master (as per the fixed arbitration given above) • A single source from the timer • The “non timing-related events”. The same arbitration principle applies for concurrent reset requests. In this case, the reset request has the highest priority. 1318/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) A set or reset event occurring within the prescaler clock cycle is delayed to the next active edge of the prescaled clock (as for a counter reset), even if the arbitration is still performed every tHRTIM cycle. If a reset event is followed by a set event within the same prescaler clock cycle, the latest event will be considered. 37.3.7 External events global conditioning The HRTIM timer can handle events not generated within the timer, referred to as “external event”. These external events come from multiple sources, either on-chip or off-chip: • built-in comparators, • digital input pins (typically connected to off-chip comparators and zero-crossing detectors), • on-chip events for other peripheral (ADC’s analog watchdogs and general purpose timer trigger outputs). The external events conditioning circuitry allows to select the signal source for a given channel (with a 4:1 multiplexer) and to convert it into an information that can be processed by the crossbar unit (for instance, to have an output reset triggered by a falling edge detection on an external event channel). Up to 10 external event channels can be conditioned and are available simultaneously for any of the 5 timers. This conditioning is common to all timers, since this is usually dictated by external components (such as a zero-crossing detector) and environmental conditions (typically the filter set-up will be related to the applications noise level and signature). Figure 294 presents an overview of the conditioning logic for a single channel. DocID029587 Rev 3 1319/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 294. External event conditioning overview (1 channel represented) 2XWSXW 2XWSXW VWDJH 2XWSXW VWDJH 2XWSXW VWDJH 2XWSXW VWDJH VWDJH 7LPHU$( 7LPHU$( 7LPHU$( 7LPHU$( 7LPHU$( KUWLPBHYW[VLJQDOV 6\QFKURQRXV SDWK (([)$67 (([32/ KUWLPBHYW[>@ KUWLPBHYW[>@ KUWLPBHYW[>@ KUWLPBHYW[>@ 'LJLWDO )LOWHU )DVWDV\QFKURQRXVSDWK (([)$67 (([)> @ (([65&> @ 3UHVFDOHU ((96'> @ (([616> @ 6RXUFH VHOHFWLRQ (GJHDQG SRODULW\ )LOWHULQJ KUWLPBHYWRQO\ )DVWSDWK KUWLPBHYWRQO\ 069 The 10 external events are initialized using the HRTIM_EECR1 and HRTIM EECR2 registers: Note: • to select up to 4 sources with the EExSRC[1:0] bits, • to select the sensitivity with EExSNS[1:0] bits, to be either level-sensitive or edgesensitive (rising, falling or both), • to select the polarity, in case of a level sensitivity, with EExPOL bit, • to have a low latency mode, with EExFAST bits (see Latency to external events), for external events 1 to 5. The external events used as triggers for reset, capture, burst mode, ADC triggers and delayed protection are edge-sensitive even if EESNS bit is reset (level-sensitive selection): if POL = 0 the trigger is active on external event rising edge, while if POL = 1 the trigger is active on external event falling edge. The external events are discarded as long as the counters are disabled (TxCEN bit reset) to prevent any output state change and counter reset, except if they are used as ADC triggers. Additionally, it is possible to enable digital noise filters, for external events 6 to 10, using EExF[3:0] bits in the HRTIM_EECR3 register. A digital filter is made of a counter in which a number N of valid samples is needed to validate a transition on the output. If the input value changes before the counter has 1320/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) reached the value N, the counter is reset and the transition is discarded (considered as a spurious event). If the counter reaches N, the transition is considered as valid and transmitted as a correct external event. Consequently, the digital filter adds a latency to the external events being filtered, depending on the sampling clock and on the filter length (number of valid samples expected). The sampling clock is either the fHRTIM clock or a specific prescaled clock fEEVS derived from fHRTIM, defined with EEVSD[1:0] bits in HRTIM_EECR3 register. Table 289 summarizes the available sources and features associated with each of the 10 external events channels. Table 289. External events mapping and associated features External event channel Fast mode Digital filter 1 Yes - - 2 Yes - 3 Yes 4 Balanced Balanced fault timer fault timer A,B,C D,E Src1 Src 2 Src3 Src4 - PC10 COMP1 TIM1_TRGO ADC1_AWD1 - - PC12 COMP2 TIM2_TRGO ADC1_AWD2 - - - PD5 - TIM3_TRGO ADC1_AWD3 Yes - - - PG11 OPAMP1(1) TIM7_TRGO ADC2_AWD1 5 Yes - - - PG12 - LPTIM1 OUT ADC2_AWD2 6 - Yes Yes - PB4 COMP1 TIM6_TRGO ADC2_AWD3 7 - Yes Yes - PB5 COMP2 TIM7_TRGO - 8 - Yes - Yes PB6 - TIM6_TRGO TTCAN_TMP TIM15_TRGO TTCAN_RTP LPTIM2 OUT TTCAN_SOC 9 - Yes - Yes PB7 10 - Yes - - PG13 (1) OPAMP1 - 1. OPAMP1_VOUT can be used as High-resolution timer internal event source. In this case, OPAMP1_VOUT (PC4) pin must be configured in input mode. The data from the GPIO pin is redirect to the HRTIM external events through the pin Schmitt trigger. If OPAMP1 is disabled, PC4 pin, configured in input mode, can be used as HRTIM external events. Latency to external events The external event conditioning gives the possibility to adjust the external event processing time (and associated latency) depending on performance expectations: • A regular operating mode, in which the external event is resampled with the clock before acting on the output crossbar. This adds some latency but gives access to all crossbar functionalities. It enables the generation of an externally triggered highresolution pulse. • A fast operating mode, in which the latency between the external event and the action on the output is minimized. This mode is convenient for ultra-fast over-current protections, for instance. EExFAST bits in the HRTIM_EECR1 register allow to define the operating for channels 1 to 5. This influences the latency and the jitter present on the output pulses, as summarized in the table below. DocID029587 Rev 3 1321/3178 1466 High-Resolution Timer (HRTIM) RM0433 Table 290. Output set/reset latency and jitter vs external event operating mode EExFAST Response time latency Response time jitter 0 5 to 6 cycles of fHRTIM clock 1 cycles of fHRTIM clock 1 Minimal latency (depends whether the comparator or digital input is used) Minimal jitter Jitter on output pulse (counter reset by ext. event) No jitter, pulse width maintained with high-resolution 1 cycle of fHRTIM clock jitter pulse width resolution down to tHRTIM The EExFAST mode is only available with level-sensitive programming (EExSNS[1:0] = 00); the edge-sensitivity cannot be programmed. It is possible to apply event filtering to external events (both blanking and windowing with EExFLTR[3:0] != 0000, see Section 37.3.8). In this case, EExLTCHx bit must be reset: the postponed mode is not supported, neither the windowing timeout feature. Note: The external event configuration (source and polarity) must not be modified once the related EExFAST bit is set. A fast external event cannot be used to toggle an output: if must be enabled either in HRTIM_SETxyR or HRTIM_RSTxyR registers, not in both. When a set and a reset event - from 2 independent fast external events - occur simultaneously, the reset has the highest priority in the crossbar and the output becomes inactive. When EExFAST bit is set, the output cannot be changed during the 11 fHRTIM clock periods following the external event. Figure 295 and Figure 296 give practical examples of the reaction time to external events, for output set/reset and counter reset. 1322/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 295. Latency to external events falling edge (counter reset and output set) I+57,0FORFN ([WHUQDO(YHQW F\FOHVGHOD\ ([WHUQDO(YHQW DIWHULQWHUQDO UHV\QFKURQLVDWLRQ +57,0(5 FRXQWHU &RXQWHUUHVHW F\FOHVGHOD\ +57,0(5 RXWSXW (([)$67 -LWWHUOHVVSXOVH 6HWDWFRXQWHUUHVHWDQGUHVHWDW F\FOHVGHOD\ WRWDOODWHQF\ +57,0(5 RXWSXW (([)$67 F\FOHSXOVHOHQJWKMLWWHU 0LQLPDOODWHQF\ DV\QFKURQRXVSDWK 6HWDWFRXQWHUUHVHWDQGUHVHWDW 06Y 9 Figure 296. Latency to external events (output reset on external event) Ĩ,Zd/DĐůŽĐŬ džƚĞƌŶĂů ǀĞŶƚ ϮͲϯĐLJĐůĞƐĚĞůĂLJ džƚĞƌŶĂů ǀĞŶƚ ĂĨƚĞƌŝŶƚĞƌŶĂů ƌĞͲƐLJŶĐŚƌŽŶŝƐĂƚŝŽŶ ,Zd/D Z ŽƵƚƉƵƚ dž&^dсϬ ϱͲϲĐLJĐůĞƐĚĞůĂLJƚŽƚĂů ,Zd/D Z ŽƵƚƉƵƚ dž&^dсϭ DŝŶŝŵĂůůĂƚĞŶĐLJ ;ĂƐLJŶĐŚƌŽŶŽƵƐƉĂƚŚͿ D^ϯϮϮϵϯsϭ DocID029587 Rev 3 1323/3178 1466 High-Resolution Timer (HRTIM) 37.3.8 RM0433 External event filtering in timing units Once conditioned, the 10 external events are available for all timing units. They can be used directly and are active as soon as the timing unit counter is enabled (TxCEN bit set). They can also be filtered to have an action limited in time, usually related to the counting period. Two operations can be performed: • blanking, to mask external events during a defined time period, • windowing, to enable external events only during a defined time period. These modes are enabled using HRTIM_EExFLTR[3:0] bits in the HRTIM_EEFxR1 and HRTIM_EEFxR2 registers. Each of the 5 TimerA..E timing units has its own programmable filter settings for the 10 external events. Blanking mode In event blanking mode (see Figure 297), the external event is ignored if it happens during a given blanking period. This is convenient, for instance, to avoid a current limit to trip on switching noise at the beginning of a PWM period. This mode is active for EExFLTR[3:0] bitfield values ranging from 0001 to 1100. Figure 297. Event blanking mode džƚĞƌŶĂůĞǀĞŶƚ džƚͬ͘ŝŶƚ͘ĞǀĞŶƚ ůĂŶŬŝŶŐ ůĂŶŬŝŶŐƐŽƵƌĐĞ ZĞƐƵůƚŝŶŐĞǀĞŶƚ D^ϯϮϮϵϰsϭ In event postpone mode, the external event is not taken into account immediately but is memorized (latched) and generated as soon as the blanking period is completed, as shown on Figure 298. This mode is enabled by setting EExLTCH bit in HRTIM_EEFxR1 and HRTIM_EEFxR2 registers. Figure 298. Event postpone mode džƚĞƌŶĂůĞǀĞŶƚ džƚͬ͘ŝŶƚ͘ĞǀĞŶƚ >ĂƚĐŚ ůĂŶŬŝŶŐƐŽƵƌĐĞ ůĂŶŬŝŶŐ ZĞƐƵůƚŝŶŐĞǀĞŶƚ D^ϯϮϮϵϱsϭ 1324/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) The blanking signal comes from several sources: • the timer itself: the blanking lasts from the counter reset to the compare match (EExFLTR[3:0] = 0001 to 0100 for Compare 1 to Compare 4) • from other timing units (EExFLTR[3:0] = 0101 to 1100): the blanking lasts from the selected timing unit counter reset to one of its compare match, or can be fully programmed as a waveform on Tx2 output. In this case, events are masked as long as the Tx2 signal is inactive (it is not necessary to have the output enabled, the signal is taken prior to the output stage). The EEXFLTR[3:0] configurations from 0101 to 1100 are referred to as TIMFLTR1 to TIMFLTR8 in the bit description, and differ from one timing unit to the other. Table 291 gives the 8 available options per timer: CMPx refers to blanking from counter reset to compare match, Tx2 refers to the timing unit TIMx output 2 waveform defined with HRTIM_SETx2 and HRTIM_RSTx2 registers. For instance, Timer B (TIMFLTR6) is Timer C output 2 waveform. Table 291. Filtering signals mapping per time r Timer A Destination Source Timer B Timer C CMP CMP CMP CMP CMP CMP CMP CMP CMP TA2 TB2 1 2 4 1 2 4 1 2 4 TC2 Timer D Timer E CMP CMP CMP TD2 1 2 4 CMP CMP CMP TE2 1 2 4 Timer A - - - - 1 - 2 3 4 - 5 6 7 - - - - 8 - - Timer B 1 - 2 3 - - - - 4 5 - 6 - 7 - - 8 - - - Timer C - 1 - - 2 - 3 4 - - - - 5 - 6 7 - - 8 - Timer D 1 - - - - 2 - - 3 4 - 5 - - - - 6 - 7 8 Timer E - 1 - - 2 - - - 3 - 4 5 6 - 7 8 - - - - Figure 299 and Figure 300 give an example of external event blanking for all edge and level sensitivities, in regular and postponed modes. DocID029587 Rev 3 1325/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 299. External trigger blanking with edge-sensitive trigger &RXQWHU &RPSDUH %ODQNLQJZLQGRZ ([WHUQDOHYHQW (([/7&+ (([/7&+ (([616> @ (([616> @ (([616> @ ,QWHUQDOHYHQWJHQHUDWHGDIWHUEODQNLQJ 06 9 Figure 300. External trigger blanking, level sensitive triggering ŽƵŶƚĞƌ ŽŵƉĂƌĞϭ ůĂŶŬŝŶŐǁŝŶĚŽǁ džƚĞƌŶĂůĞǀĞŶƚ WK>сϬ;,Ϳ͕>d,сϬ WK>сϭ;>Ϳ͕>d,сϬ WK>сϬ;,Ϳ͕>d,сϭ ůĂƚĐŚĞĚ WK>сϭ;>Ϳ͕>d,сϭ WK>с džWK> >d,с dž>d, ΎŚŝŐŚůĞǀĞůĚĞŶŽƚĞƐĂĐŽŶƚŝŶƵŽƵƐĞǀĞŶƚŐĞŶĞƌĂƚŝŽŶĂĨƚĞƌďůĂŶŬŝŶŐ D^ϯϮϮϵϳsϭ 1326/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Windowing mode In event windowing mode, the event is taken into account only if it occurs within a given time window, otherwise it is ignored. This mode is active for EExFLTR[3:0] ranging from 1101 to 1111. Figure 301. Event windowing mode ([WHUQDOHYHQW ([WLQWHYHQW 2XWSXW %ODQNLQJVRXUFH :LQGRZLQJ 5HVXOWLQJHYHQW 06 9 EExLTCH bit in EEFxR1 and EEFxR2 registers allows to latch the signal, if set to 1: in this case, an event is accepted if it occurs during the window but is delayed at the end of it. • If EExLTCH bit is reset and the signal occurs during the window, it is passed through directly. • If EExLTCH bit is reset and no signal occurs, a timeout event is generated at the end of the window. A use case of the windowing mode is to filter synchronization signals. The timeout generation allows to force a default synchronization event, when the expected synchronization event is lacking (for instance during a converter start-up). There are 3 sources for each external event windowing, coded as follows: • 1101 and 1110: the windowing lasts from the counter reset to the compare match (respectively Compare 2 and Compare 3) • 1111: the windowing is related to another timing unit and lasts from its counter reset to its Compare 2 match. The source is described as TIMWIN in the bit description and is given in Table 292. As an example, the external events in timer B can be filtered by a window starting from timer A counter reset to timer A Compare 2. Table 292. Windowing signals mapping per timer (EEFLTR[3:0] = 1111) Note: Destination Timer A Timer B Timer C Timer D Timer E TIMWIN (source) Timer B CMP2 Timer A CMP2 Timer D CMP2 Timer C CMP2 Timer D CMP2 The timeout event generation is not supported if the external event is programmed in fast mode. Figure 302 and Figure 303 present how the events are generated for the various edge and level sensitivities, as well as depending on EExLTCH bit setting. Timeout events are specifically mentioned for clarity reasons. DocID029587 Rev 3 1327/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 302. External trigger windowing with edge-sensitive trigger ŽƵŶƚĞƌ ŽŵƉĂƌĞϭ tŝŶĚŽǁ džƚĞƌŶĂůĞǀĞŶƚ ;dŝŵĞŽƵƚͿ dž>d,сϬ ;dŝŵĞŽƵƚͿ ;dŝŵĞŽƵƚͿ dž>d,сϭ dž^E^ϭ͗ϬсϬϭ dž^E^ϭ͗ϬсϭϬ dž^E^ϭ͗Ϭсϭϭ /ŶƚĞƌŶĂůĞǀĞŶƚŐĞŶĞƌĂƚĞĚĂĨƚĞƌǁŝŶĚŽǁŝŶŐ D^ϯϮϮϵϵsϭ Figure 303. External trigger windowing, level sensitive triggering ŽƵŶƚĞƌ ŽŵƉĂƌĞϭ ǁŝŶĚŽǁ džƚĞƌŶĂůĞǀĞŶƚ ;dŝŵĞŽƵƚͿ WK>сϬ;,Ϳ͕>d,сϬ WK>сϭ;>Ϳ͕>d,сϬ WK>сϬ;,Ϳ͕>d,сϭ WK>сϭ;>Ϳ͕>d,сϭ WK>с džWK> >d,с dž>d, ΎŚŝŐŚůĞǀĞůĚĞŶŽƚĞƐĐŽŶƚŝŶƵŽƵƐĞǀĞŶƚŐĞŶĞƌĂƚŝŽŶĂĨƚĞƌǁŝŶĚŽǁŝŶŐ D^ϯϮϯϯϬsϭ 1328/3178 DocID029587 Rev 3 RM0433 37.3.9 High-Resolution Timer (HRTIM) Delayed Protection The HRTIM features specific protection schemes, typically for resonant converters when it is necessary to shut down the PWM outputs in a delayed manner, either once the active pulse is completed or once a push-pull period is completed. These features are enabled with DLYPRTEN bit in the HRTIM_OUTxR register, and are using specific external event channels. Delayed Idle In this mode, the active pulse is completed before the protection is activated. The selected external event causes the output to enter in idle mode at the end of the active pulse (defined by an output reset event in HRTIM_RSTx1R or HRTIM_RSTx2R). Once the protection is triggered, the idle mode is permanently maintained but the counter continues to run, until the output is re-enabled. Tx1OEN and Tx2OEN bits are not affected by the delayed idle entry. To exit from delayed idle and resume operation, it is necessary to overwrite Tx1OEN and Tx2OEN bits to 1. The output state will change on the first transition to an active state following the output enable command. Note: The delayed idle mode cannot be exited immediately after having been entered, before the active pulse is completed: it is mandatory to make sure that the outputs are in idle state before resuming the run mode. This can be done by waiting up to the next period, for instance, or by polling the O1CPY and/or O2CPY status bits in the TIMxISR register. The delayed idle mode can be applied to a single output (DLYPRT[2:0] = x00 or x01) or to both outputs (DLYPRT[2:0] = x10). An interrupt or a DMA request can be generated in response to a Delayed Idle mode entry. The DLYPRT flag in HRTIM_TIMxISR is set as soon as the external event arrives, independently from the end of the active pulse on output. When the Delayed Idle mode is triggered, the output states can be determined using O1STAT and O2STAT in HRTIM_TIMxISR. Both status bits are updated even if the delayed idle is applied to a single output. When the push-pull mode is enabled, the IPPSTAT flag in HRTIM_TIMxISR indicates during which period the delayed protection request occurred. This mode is available whatever the timer operating mode (regular, push-pull, deadtime). It is available with 2 external events only: • hrtim_evt6 and hrtim_evt7 for Timer A, B and C • hrtim_evt8 and hrtim_evt9 for Timer D and E The delayed protection mode can be triggered only when the counter is enabled (TxCEN bit set). It remains active even if the TxEN bit is reset, until the TxyOEN bits are set. DocID029587 Rev 3 1329/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 304. Delayed Idle mode entry ĞůĂLJĞĚ/ĚůĞŵŽĚĞĨŽƌďŽƚŚŽƵƚƉƵƚƐ džƚĞƌŶĂů ǀĞŶƚ ϭ >zWZd Ϯ ZƵŶŵŽĚĞ /ĚůĞŵŽĚĞ ;Kϭ^ddсϭ͕KϮ^ddсϬͿ džƚĞƌŶĂů ǀĞŶƚ ϭ >zWZd Ϯ ϭZƵŶŵŽĚĞ ϭ/ĚůĞŵŽĚĞ ϮZƵŶŵŽĚĞ Ϯ/ĚůĞŵŽĚĞ ;Kϭ^ddсϭ͕KϮ^ddсϭͿ ĞůĂLJĞĚ/ĚůĞŵŽĚĞĨŽƌϮŽƵƚƉƵƚŽŶůLJ džƚĞƌŶĂů ǀĞŶƚ ϭ Ϯ >zWZd ϮZƵŶŵŽĚĞ Ϯ/ĚůĞŵŽĚĞ D^ϯϮϯϯϭsϭ The delayed idle mode has a higher priority than the burst mode: any burst mode exit request is discarded once the delayed idle protection has been triggered. On the contrary, If the delayed protection is exited while the burst mode is active, the burst mode will be resumed normally and the output will be maintained in the idle state until the burst mode exits. Figure 305 gives an overview of these different scenarios. 1330/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 305. Burst mode and delayed protection priorities (DIDL = 0) ĞůĂLJĞĚƉƌŽƚĞĐƚŝŽŶ ŶƚƌLJ;ĚŝƐĐĂƌĚĞĚ͕ďƵƌƐƚ ŚĂƐƉƌŝŽƌŝƚLJͿ ĞůĂLJĞĚƉƌŽƚĞĐƚŝŽŶ Ğdžŝƚ;ĚŝƐĐĂƌĚĞĚ͕ďƵƌƐƚ ŚĂƐƉƌŝŽƌŝƚLJͿ ƵƌƐƚĞdžŝƚ ƵƌƐƚĞŶƚƌLJ KƵƚƉƵƚ ^ƚĂƚĞ ZhE /> ZhE ƵƌƐƚĞdžŝƚ;ĚŝƐĐĂƌĚĞĚ͕ ĚĞůĂLJĞĚƉƌŽƚĞĐƚŝŽŶŚĂƐ ƉƌŝŽƌŝƚLJͿ ƵƌƐƚĞŶƚƌLJ ĞůĂLJĞĚ ƉƌŽƚĞĐƚŝŽŶ Ğdžŝƚ ĞůĂLJĞĚ ƉƌŽƚĞĐƚŝŽŶ ŶƚƌLJ KƵƚƉƵƚ ^ƚĂƚĞ ZhE /> ZhE D^ϯϮϮϴϬsϭ The same priorities are applied when the delayed burst mode entry is enabled (DIDL bit set), as shown on Figure 306 below. DocID029587 Rev 3 1331/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 306. Burst mode and delayed protection priorities (DIDL = 1) %XUVWH[LW 'HOD\HG SURWHFWLRQ 'HOD\HG SURWHFWLRQ H[LW %XUVWHQWU\ &URVVEDU RXWSXW ,'/(6OHYHO 2XWSXW 'HDGWLPH %XUVWH[LW %XUVWHQWU\ 'HOD\HG SURWHFWLRQ H[LW 'HOD\HG SURWHFWLRQ &URVVEDU RXWSXW ,'/(6OHYHO 2XWSXW 'HDGWLPH 069 Balanced Idle Only available in push-pull mode, it allows to have balanced pulsewidth on the two outputs when one of the active pulse is shortened due to a protection. The pulsewidth, which was terminated earlier than programmed, is copied on the alternate output and the two outputs are then put in idle state, until the normal operation is resumed by software. This mode is enabled by writing x11 in DLYPRT[2:0] bitfield in HRTIM_OUTxR. This mode is available with 2 external events only: 1332/3178 • hrtim_evt6 and hrtim_evt7 for Timer A, B and C • hrtim_evt8 and hrtim_evt9 for Timer D and E DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 307. Balanced Idle protection example 3(5 FRXQWHU &03 7DUHI LQWHUQDO 7$ 7$ &3367$7 &3367$7 &3367$7 &3367$7 ((9 7$ 3XOVHOHQJWK FRSLHG 7$ ,3367$7 7$ ((9 3XOVHOHQJWK FRSLHG 7$ ,3367$7 UHVHWYDOXH ,3367$7 '/<357 $DQG$5XQPRGH $DQG$,GOHPRGH 069 When the balanced Idle mode is enabled, the selected external event triggers a capture of the counter value into the Compare 4 active register (this value is not user-accessible). The push-pull is maintained for one additional period so that the shorten pulse can be repeated: a new output reset event is generated while the regular output set event is maintained. DocID029587 Rev 3 1333/3178 1466 High-Resolution Timer (HRTIM) RM0433 The Idle mode is then entered and the output takes the level defined by IDLESx bits in the HRTIM_OUTxR register. The balanced idle mode entry is indicated by the DLYPRT flag, while the IPPSTAT flag indicates during which period the external event occurred, to determine the sequence of shorten pulses (HRTIM_CHA1 then HRTIM_CHA2 or vice versa). The timer operation is not interrupted (the counter continues to run). To enable the balanced idle mode, it is necessary to have the following initialization: Note: – timer operating in continuous mode (CONT = 1) – Push-pull mode enabled – HRTIM_CMP4xR must be set to 0 and the content transferred into the active register (for instance by forcing a software update) – DELCMP4[1:0] bit field must be set to 00 (auto-delayed mode disabled) – DLYPRT[2:0] = x11 (delayed protection enable) The HRTIM_CMP4xR register must not be written during a balanced idle operation. The CMP4 event is reserved and cannot be used for another purpose. In balanced idle mode, it is recommended to avoid multiple external events or softwarebased reset events causing an output reset. If such an event arrives before a balanced idle request within the same period, it will cause the output pulses to be unbalanced (1st pulse length defined by the external event or software reset, while the 2nd pulse is defined by the balanced idle mode entry). The minimum pulsewidth that can be handled in balanced idle mode is 4 fHRTIM clock periods. If the capture occurs before the counter has reached this minimum value, the current pulse is extended up to 4 fHRTIM clock periods before being copied into the secondary output. In any case, the pulsewidths are always balanced. Tx1OEN and Tx2OEN bits are not affected by the balanced idle entry. To exit from balanced idle and resume the operation, it is necessary to overwrite Tx1OEN and Tx2OEN bits to 1 simultaneously. The output state will change on the first active transition following the output enable. It is possible to resume operation similarly to the delayed idle entry. For instance, if the external event arrives while output 1 is active (delayed idle effective after output 2 pulse), the re-start sequence can be initiated for output 1 first. To do so, it is necessary to poll CPPSTAT bit in the HRTIM_TIMxISR register. Using the above example (IPPSTAT flag equal to 0), the operation will be resumed when CPPSTAT bit is 0. In order to have a specific re-start sequence, it is possible to poll the CPPSTAT to know which output will be active first. This allows, for instance, to re-start with the same sequence as the idle entry sequence: if EEV arrives during output 1 active, the re-start sequence will be initiated when the output 1 is active (CPPSTAT = 0). Note: The balanced idle mode must not be disabled while a pulse balancing sequence is ongoing. It is necessary to wait until the CMP4 flag is set, thus indicating that the sequence is completed, to reset the DLYPRTEN bit. The balanced idle protection mode can be triggered only when the counter is enabled (TxCEN bit set). It remains active even if the TxCEN bit is reset, until TxyOEN bits are set. 1334/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Balanced idle can be used together with the burst mode under the following conditions: • TxBM bit must be reset (counter clock maintained during the burst, see Section 37.3.13), • No balanced idle protection must be triggered while the outputs are in a burst idle state. The balanced idle mode has a higher priority than the burst mode: any burst mode exit request is discarded once the balanced idle protection has been triggered. On the contrary, if the delayed protection is exited while the burst mode is active, the burst mode will be resumed normally. Note: Although the output state is frozen in idle mode, a number of events are still generated on the auxiliary outputs (see Section 37.3.16) during the idle period following the delayed protection: - Output set/reset interrupt or DMA requests - External event filtering based on output signal - Capture events triggered by set/reset 37.3.10 Register preload and update management Most of HRTIM registers are buffered and can be preloaded if needed. Typically, this allows to prevent the waveforms from being altered by a register update not synchronized with the active events (set/reset). When the preload mode is enabled, accessed registers are shadow registers. Their content is transferred into the active register after an update request, either software or synchronized with an event. By default, PREEN bits in HRTIM_MCR and HRTIM_TIMxCR registers are reset and the registers are not preloaded: any write directly updates the active registers. If PREEN bit is reset while the timer is running and preload was enabled, the content of the preload registers is directly transferred into the active registers. Each timing unit and the master timer have their own PREEN bit. If PRREN is set, the preload registers are enabled and transferred to the active register only upon an update event. There are two options to initialize the timer when the preload feature is needed: • Enable PREEN bit at the very end of the timer initialization to have the preload registers transferred into the active registers before the timer is enabled (by setting MCEN and TxCEN bits). • enable PREEN bit at any time during the initialization and force a software update immediately before starting. Table 293 lists the registers which can be preloaded, together with a summary of available update events. DocID029587 Rev 3 1335/3178 1466 High-Resolution Timer (HRTIM) RM0433 Table 293. HRTIM preloadable control registers and associated update sources Timer Preloadable registers HRTIM_DIER HRTIM_MPER HRTIM_MREP HRTIM_MCMP1R HRTIM_MCMP2R HRTIM_MCMP3R HRTIM_MCMP4R Preload enable Update sources PREEN bit in HRTIM_MCR Software Repetition event Burst DMA event Repetition event following a burst DMA event Timer x x = A..E HRTIM_TIMxDIER HRTIM_TIMxPER HRTIM_TIMxREP HRTIM_TIMxCMP1R HRTIM_TIMxCMP1CR HRTIM_TIMxCMP2R HRTIM_TIMxCMP3R HRTIM_TIMxCMP4R HRTIM_DTxR HRTIM_SETx1R HRTIM_RSTx1R HRTIM_SETx2R HRTIM_RSTx2R HRTIM_RSTxR PREEN bit in HRTIM_TIMxCR Software TIMx Repetition event TIMx Reset Event Burst DMA event Update event from other timers (TIMy, Master) Update event following a burst DMA event Update enable input 1..3 Update event following an update enable input 1..3 HRTIM Common HRTIM_ADC1R HRTIM_ADC2R HRTIM_ADC3R HRTIM_ADC4R TIMx or Master timer Update, depending on ADxUSRC[2:0] bits in HRTIM_CR1, if PREEN = 1 in the selected timer Master Timer The master timer has 4 update options: 1. Software: writing 1 into MSWU bit in HRTIM_CR2 forces an immediate update of the registers. In this case, any pending hardware update request is cancelled. 2. Update done when the master counter rolls over and the master repetition counter is equal to 0. This is enabled when MREPU bit is set in HRTIM_MCR. 3. Update done once Burst DMA is completed (see Section 37.3.21 for details). This is enabled when BRSTDMA[1:0] = 01 in HRTIM_MCR. It is possible to have both MREPU=1 and BRSTDMA=01. Note: The update can take place immediately after the end of the burst sequence if SWU bit is set (i.e. forced update mode). If SWU bit is reset, the update will be done on the next update event following the end of the burst sequence. 4. Update done when the master counter rolls over following a Burst DMA completion. This is enabled when BRSTDMA[1:0] = 10 in HRTIM_MCR. An interrupt or a DMA request can be generated by the master update event. 1336/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Each timer (TIMA..E) can also have the update done as follows: • By software: writing 1 into TxSWU bit in HRTIM_CR2 forces an immediate update of the registers. In this case, any pending hardware update request is canceled. • Update done when the counter rolls over and the repetition counter is equal to 0. This is enabled when TxREPU bit is set in HRTIM_TIMxCR. • Update done when the counter is reset or rolls over in continuous mode. This is enabled when TxRSTU bit is set in HRTIM_TIMxCR. This is used for a timer operating in single-shot mode, for instance. • Update done once a Burst DMA is completed. This is enabled when UPDGAT[3:0] = 0001 in HRTIM_TIMxCR. • Update done on the update event following a Burst DMA completion (the event can be enabled with TxREPU, MSTU or TxU). This is enabled when UPDGAT[3:0] = 0010 in HRTIM_TIMxCR. • Update done when receiving a request on the update enable input 1..3. This is enabled when UPDGAT[3:0] = 0011, 0100, 0101 in HRTIM_TIMxCR. • Update done on the update event following a request on the update enable input 1..3 (the event can be enabled with TxREPU, MSTU or TxU). This is enabled when UPDGAT[3:0] = 0110, 0111, 1000 in HRTIM_TIMxCR • Update done synchronously with any other timer or master update (for instance TIMA can be updated simultaneously with TIMB). This is used for converters requiring several timers, and is enabled by setting bits MSTU and TxU in HRTIM_TIMxCR register. The update enable inputs 1..3 allow to have an update event synchronized with on-chip events coming from the general-purpose timers. These inputs are rising-edge sensitive. Table 294 lists the connections between update enable inputs and the on-chip sources. Table 294. Update enable inputs and sources Update enable input Update source Update enable input 1 TIM16_OC Update enable input 2 TIM17_OC Update enable input 3 TIM6_TRGO This allows to synchronize low frequency update requests with high-frequency signals (for instance an update on the counter roll-over of a 100 kHz PWM that has to be done at a 100 Hz rate). Note: The update events are synchronized to the prescaler clock when CKPSC[2:0] > 5. An interrupt or a DMA request can be generated by the Timx update event. MUDIS and TxUDIS bits in the HRTIM_CR1 register allow to temporarily disable the transfer from preload to active registers, whatever the selected update event. This allows to modify several registers in multiple timers. The regular update event takes place once these bits are reset. MUDIS and TxUDIS bits are all grouped in the same register. This allows the update of multiple timers (not necessarily synchronized) to be disabled and resumed simultaneously. DocID029587 Rev 3 1337/3178 1466 High-Resolution Timer (HRTIM) RM0433 The following example is a practical use case. A first power converter is controlled with the master, TIMB and TIMC. TIMB and TIMC must be updated simultaneously with the master timer repetition event. A second converter works in parallel with TIMA, TIMD and TIME, and TIMD, TIME must be updated with TIMA repetition event. First converter In HRTIM_MCR, MREPU bit is set: the update will occur at the end of the master timer counter repetition period. In HRTIM_TIMBCR and HRTIM_TIMCCR, MSTU bits are set to have TIMB and TIMC timers updated simultaneously with the master timer. When the power converter set-point has to be adjusted by software, MUDIS, TBUDIS and TCUDIS bits of the HRTIM_CR register must be set prior to write accessing registers to update the values (for instance the compare values). From this time on, any hardware update request is ignored and the preload registers can be accessed without any risk to have them transferred into the active registers. Once the software processing is over, MUDIS, TBUDIS and TCUDIS bits must be reset. The transfer from preload to active registers will be done as soon as the master repetition event occurs. Second converter In HRTIM_TIMACR, TAREPU bit is set: the update will occur at the end of the Timer A counter repetition period. In HRTIM_TIMDCR and HRTIM_TIMECR, TAU bits are set to have TIMD and TIME timers updated simultaneously with Timer A. When the power converter set-point has to be adjusted by software, TAUDIS, TDUDIS and TEUDIS bits of the HRTIM_CR register must be set prior to write accessing the registers to update the values (for instance the compare values). From this time on, any hardware update request is ignored and the preload registers can be accessed without any risk to have them transferred into the active registers. Once the software processing is over, TAUDIS, TDUDIS and TEUDIS bits can be reset: the transfer from preload to active registers will be done as soon as the Timer A repetition event occurs. 37.3.11 Events propagation within or across multiple timers The HRTIM offers many possibilities for cascading events or sharing them across multiple timing units, including the master timer, to get full benefits from its modular architecture. These are key features for converters requiring multiple synchronized outputs. This section summarizes the various options and specifies whether and how an event is propagated within the HRTIM. TIMx update triggered by the Master timer update The sources listed in Table 295 are generating a master timer update. The table indicates if the source event can be used to trigger a simultaneous update in any of TIMx timing units. Operating condition: MSTU bit is set in HRTIM_TIMxCR register. 1338/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Table 295. Master timer update event propagation Source Condition Propagation Burst DMA end BRSTDMA[1:0] = 01 No Roll-over event following a Burst DMA end BRSTDMA[1:0] = 10 Yes - Yes - No - Repetition event caused by a counter roll-over Repetition event caused by a counter reset (from HRTIM_SCIN or software) MREPU = 1 Software update MSWU = 1 No Comment Must be done in TIMxCR (UPDGAT[3:0] = 0001) All software update bits (TxSWU) are grouped in the HRTIM_CR2 register and can be used for a simultaneous update TIMx update triggered by the TIMy update The sources listed in Table 296 are generating a TIMy update. The table indicates if the given event can be used to trigger a simultaneous update in another or multiple TIMx timers. Operating condition: TyU bit set in HRTIM_TIMxCR register (source = TIMy and destination = TIMx). Table 296. TIMx update event propagation Source Condition Propagation UPDGAT[3:0] = 0001 No Must be done directly in HRTIM_TIMxCR (UPDGAT[3:0] = 0001) Update caused by the update enable input UPDGAT[3:0] = 0011, 0100, 0101 No Must be done directly in HRTIM_TIMxCR (UPDGAT[3:0] = 0011, 0100, 0101 Master update MSTU = 1 in HRTIM_TIMyCR No Another TIMx update (TIMz>TIMy>TIMx) TzU=1 in HRTIM_TIMyCR TyU=1 in TIMxCR No Repetition event caused by a counter roll-over TyREPU = 1 Yes Repetition event caused by a counter reset TyREPU = 1 - Counter roll-over TyRSTU = 1 Yes Counter software reset TyRST=1 in HRTIM_CR2 No Can be done simultaneously with update in HRTIM_CR2 register Counter reset caused by a TIMz compare TIMzCMPn in HRTIM_RSTyR No Must be done using TIMzCMPn in HRTIM_RSTxR Counter reset caused by external events EXTEVNTn in HRTIM_RSTyR Yes Burst DMA end Comment Must be done with MSTU = 1 in HRTIM_TIMxCR Must be done with TzU=1 in HRTIM_TIMxCR TzU=1 in HRTIM_TIMyCR Refer to counter reset cases below - DocID029587 Rev 3 - 1339/3178 1466 High-Resolution Timer (HRTIM) RM0433 Table 296. TIMx update event propagation (continued) Source Condition Propagation Comment Counter reset caused by a master compare or a master period MSTCMPn or MSTPER in HRTIM_RSTyR No - Counter reset caused by a TIMy compare CMPn in HRTIM_RSTyR Yes - Counter reset caused by an update UPDT in HRTIM_RSTyR No Counter reset caused by HRTIM_SCIN SYNCRSTy in HRTIM_TIMyCR No TySWU = 1 No Software update Propagation would result in a lock-up situation (update causing reset causing update) All software update bits (TxSWU) are grouped in the HRTIM_CR2 register and can be used for a simultaneous update TIMx Counter reset causing a TIMx update Table 297 lists the counter reset sources and indicates whether they can be used to generate an update. Operating condition: TxRSTU bit in HRTIM_TIMxCR register. Table 297. Reset events able to generate an update Source Condition Counter roll-over 1340/3178 Propagation Comment Yes Propagation would result in a lock-up situation (update causing a reset causing an update) Update event UPDT in HRTIM_RSTxR No External Event EXTEVNTn in HRTIM_RSTxR Yes - TIMy compare TIMyCMPn in HRTIM_RSTxR Yes - Master compare MSTCMPn in HRTIM_RSTxR Yes - Master period MSTPER in HRTIM_RSTxR Yes - Compare 2 and 4 CMPn in HRTIM_RSTxR Yes - Software TxRST=1 in HRTIM_CR2 Yes - HRTIM_SCIN SYNCRSTx in HRTIM_TIMxCR Yes - DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) TIMx update causing a TIMx counter reset Table 298 lists the update event sources and indicates whether they can be used to generate a counter reset. Operating condition: UPDT bit set in HRTIM_RSTxR. Table 298. Update event propagation for a timer reset Source Condition Propagation Comment Burst DMA end UPDGAT[3:0] = 0001 Yes - Update caused by the update enable input UPDGAT[3:0] = 0011, 0100, 0101 Yes - Master update caused by a roll-over after a Burst DMA MSTU = 1 in HRTIM_TIMxCR BRSTDMA[1:0] = 10 in HRTIM_MCR Yes - Yes - No - Master update caused by a repetition event following a roll-over Master update caused by a repetition event following a counter reset (software or due to HRTIM_SCIN) MSTU = 1 in HRTIM_TIMxCR MREPU = 1 in HRTIM_MCR All software update bits (TxSWU) are grouped in the HRTIM_CR2 register and can be used for a simultaneous update Software triggered master timer update MSTU = 1 in HRTIM_TIMxCR MSWU = 1 in HRTIM_CR2 No TIMy update caused by a TIMy counter roll-over TyU = 1 in HRTIM_TIMxCR TyRSTU = 1 in HRTIM_TIMyCR Yes - TIMy update caused by a TIMy repetition event TyU = 1 in HRTIM_TIMxCR TyREPU = 1 in HRTIM_TIMyCR Yes - TIMy update caused by an external event or a TIMy compare (through a TIMy reset) TyU = 1 in HRTIM_TIMxCR TyRSTU = 1 in HRTIM_TIMyCR EXTEVNTn or CMP4/2 in HRTIM_RSTyCR Yes - TIMy update caused by sources other than those listed above TyU = 1 in HRTIM_TIMxCR No - DocID029587 Rev 3 1341/3178 1466 High-Resolution Timer (HRTIM) RM0433 Table 298. Update event propagation for a timer reset (continued) Source Repetition event following a roll-over Repetition event following a counter reset 37.3.12 Condition TxREPU = 1 in HRTIM_TIMxCR Propagation Comment Yes - No - Timer reset TxRSTU = 1 in HRTIM_TIMxCR No Propagation would result in a lock-up situation (reset causing an update causing a reset) Software TxSWU in HRTIM_CR2 No - Output management Each timing unit controls a pair of outputs. The outputs have three operating states: • RUN: this is the main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit. • IDLE: this state is the default operating state after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation (where outputs are temporary disabled during a normal operating mode; refer to Section 37.3.13 for more details). It is either permanently active or inactive. • FAULT: this is the safety state, entered in case of a shut-down request on FAULTx inputs. It can be permanently active, inactive or Hi-Z. The output status is indicated by TxyOEN bit in HRTIM_OENR register and TxyODS bit in HRTIM_ODSR register, as in Table 299. Table 299. Output state programming, x= A..E, y = 1 or 2 TxyOEN (control/status) (set by software, cleared by hardware) TxyODS (status) Output operating state 1 x RUN 0 0 IDLE 0 1 FAULT TxyOEN bit is both a control and a status bit: it must be set by software to have the output in RUN mode. It is cleared by hardware when the output goes back in IDLE or FAULT mode. When TxyOEN bit is cleared, TxyODS bit indicates whether the output is in the IDLE or FAULT state. A third bit in the HRTIM_ODISR register allows to disable the output by software. 1342/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 308. Output management overview ^ƚĂƚƵƐ͗K EͬK^ 7LPLQJ8QLW ZhE &KRSSHU ϭdž /> &3+[ +57,0B&+[\ Ϭϭ &h>d ϬϬ 32/[ ,'/(6WDWH $FWLYH,QDFWLYH 581HQWU\ 6RIWZDUH 2(1ELWVHW ,'/(6[ ,'/(HQWU\ 6RIWZDUH 2',6ELWVHW RU +DUGZDUH %XUVW'HOD\HGSURWHFWLRQ &h>d^ƚĂƚĞ ĐƚŝǀĞͬ/ŶĂĐƚŝǀĞͬ,ŝͲ )$8/7HQWU\ +DUGZDUH )$8/7[LQSXWV RUEUHDNSRLQW &h>ddžϭ͗Ϭ 069 Figure 309 summarizes the bit values for the three states and how the transitions are triggered. Faults can be triggered by any external or internal fault source, as listed in Section 37.3.15, while the Idle state can be entered when the burst mode or delayed protections are active. Figure 309. HRTIM output states and transitions /> ^ƚĂƚĞ K EсϬ K^сϬ K/^ ďŝƚƐĞƚ K E ďŝƚƐĞƚ K/^ ďŝƚƐĞƚ ;&ĂƵůƚŽƌďƌĞĂŬƉŽŝŶƚΎͿ Θ;&h>ddžϭ͗ϬхϬͿ ΘK Eсϭ K E ďŝƚƐĞƚ ZhE^ƚĂƚĞ K Eсϭ K ^сy &h>d^ƚĂƚĞ K EсϬ K^сϭ &ĂƵůƚ;ŝĨ&h>ddžхϬͿ ŽƌďƌĞĂŬƉŽŝŶƚΎ ƌĞĂŬƉŽŝŶƚΎ͗ƚŚŝƐĐŽŶĚŝƚŝŽŶŝƐǀĂůŝĚŽŶůLJŝĨ'ͺ,Zd/Dͺ^dKWсϭ ddžLJƉƌĞĨŝdžŝƐŽŵŝƚƚĞĚĨŽƌĐůĂƌŝƚLJ͗;K EсddžLJK E͕K/^сddžLJK/^͕K^сddžLJK^Ϳ D^ϯϮϯϯϯsϭ The FAULT and IDLE levels are defined as active or inactive. Active (or inactive) refers to the level on the timer output that causes a power switch to be closed (or opened for an inactive state). The IDLE state has the highest priority: the transition FAULT → IDLE is possible even if the FAULT condition is still valid, triggered by ODIS bit set. The FAULT state has priority over the RUN state: if TxyOEN bit is set simultaneously with a Fault event, the FAULT state will be entered. The condition is given on the transition IDLE → DocID029587 Rev 3 1343/3178 1466 High-Resolution Timer (HRTIM) RM0433 FAULT, as in Figure 309: fault protection needs to be enabled (FAULTx[1:0] bits = 01, 10, 11) and the Txy OEN bit set with a fault active (or during a breakpoint if DBG_HRTIM_STOP = 1). The output polarity is programmed using POLx bits in HRTIM_OUTxR. When POLx = 0, the polarity is positive (output active high), while it is active low in case of a negative polarity (POLx = 1). Practically, the polarity is defined depending on the power switch to be driven (PMOS vs. NMOS) or on a gate driver polarity. The output level in the FAULT state is configured using FAULTx[1:0] bits in HRTIM_OUTxR, for each output, as follows: Note: • 00: output never enters the fault state and stays in RUN or IDLE state • 01: output at active level when in FAULT • 10: output at inactive level when in FAULT • 11: output is tri-stated when in FAULT. The safe state must be forced externally with pull-up or pull-down resistors, for instance. FAULTx[1:0] bits must not be changed as long as the outputs are in FAULT state. The level of the output in IDLE state is configured using IDLESx bit in HRTIM_OUTxR, as follows: • 0: output at inactive level when in IDLE • 1: output at active level when in IDLE When TxyOEN bit is set to enter the RUN state, the output is immediately connected to the crossbar output. If the timer clock is stopped, the level will either be inactive (after an HRTIM reset) or correspond to the RUN level (when the timer was stopped and the output disabled). During the HRTIM initialization, the output level can be prepositioned prior to have it in RUN mode, using the software forced output set and reset in the HRTIM_SETx1R and HRTIM_RSTx1R registers. 37.3.13 Burst mode controller The burst mode controller allows to have the outputs alternatively in IDLE and RUN state, by hardware, so as to skip some switching periods with a programmable periodicity and duty cycle. Burst mode operation is of common use in power converters when operating under light loads. It can significantly increase the efficiency of the converter by reducing the number of transitions on the outputs and the associated switching losses. When operating in burst mode, one or a few pulses are outputs followed by an idle period equal to several counting periods, typically, where no output pulses are produced, as shown in the example on Figure 310. 1344/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 310. Burst mode operation example ƵƌƐƚdƌŝŐŐĞƌ ŽƵŶƚĞƌ KƵƚƉƵƚ KƵƚƉƵƚ ƐƚĂƚĞ ZhE /> ZhE /> ƵƌƐƚ ĐůŽĐŬ ƵƌƐƚ ĐŽƵŶƚĞƌ Ϭ Ϭ ϭ Ϯ ϯ ϰ ϱ ϲ ϳ Ϭ ϭ Ϯ ϯ ϰ ϱ ,Zd/DͺDDWсϰ ,Zd/DͺDW Zсϳ D^ϯϮϮϴϯsϭ The burst mode controller consists of: • A counter that can be clocked by various sources, either within or outside the HRTIM (typically the end of a PWM period). • A compare register to define the number of idle periods: HRTIM_BMCMP. • A period register to define the burst repetition rate (corresponding to the sum of the idle and run periods): HRTIM_BMPER. The burst mode controller is able to take over the control of any of the 10 PWM outputs. The state of each output during a burst mode operation is programmed using IDLESx and IDLEMx bits in the HRTIM_OUTxR register, as in Table 300. Table 300. Timer output programming for burst mode Note: IDLEMx IDLESx 0 X No action: the output is not affected by the burst mode operation. 1 0 Output inactive during the burst 1 1 Output active during the burst Output state during burst mode IDLEMx bit must not be changed while the burst mode is active. The burst mode controller only acts on the output stage. A number of events are still generated during the idle period: • Output set/reset interrupt or DMA requests • External event filtering based on Tx2 output signal • Capture events triggered by output set/reset During the burst mode, neither start not reset events are generated on the HRTIM_SCOUT output, even if TxBM bit is set. DocID029587 Rev 3 1345/3178 1466 High-Resolution Timer (HRTIM) RM0433 Operating mode It is necessary to have the counter enabled (TxCEN bit set) before using the burst mode on a given timing unit.The burst mode is enabled with BME bit in the HRTIM_BMCR register. It can operate in continuous or single-shot mode, using BMOM bit in the HRTIM_BMCR register. The continuous mode is enabled when BMOM = 1. The Burst operation is maintained until BMSTAT bit in HRTIM_BMCR is reset to terminate it. In single-shot mode (BMOM = 0), the idle sequence is executed once, following the burst mode trigger, and the normal timer operation is resumed immediately after. The duration of the idle and run periods is defined with a burst mode counter and 2 registers. The HRTIM_BMCMPR register defines the number of counts during which the selected timer(s) are in an idle state (idle period). HRTIM_BMPER defines the overall burst mode period (sum of the idle and run periods). Once the initial burst mode trigger has occurred, the idle period length is HRTIM_BMCMPR+1, the overall burst period is HRTIM_BMPER+1. Note: The burst mode period must not be less than or equal to the deadtime duration defined with DTRx[8:0] and DTFx[8:0] bitfields. The counters of the timing units and the master timer can be stopped and reset during the burst mode operation. HRTIM_BMCR holds 6 control bits for this purpose: MTBM (master) and TABM..TEBM for Timer A..E. When MTBM or TxBM bit is reset, the counter clock is maintained. This allows to keep a phase relationship with other timers in multiphase systems, for instance. When MTBM or TxBM bit is set, the corresponding counter is stopped and maintained in reset state during the burst idle period. This allows to have the timer restarting a full period when exiting from idle. If SYNCSRC[1:0] = 00 or 10 (synchronization output on the master start or timer A start), a pulse is sent on the HRTIM_SCOUT output when exiting the burst mode. Note: TxBM bit must not be set when the balanced idle mode is active (DLYPRT[1:0] = 0x11). Burst mode clock The burst mode controller counter can be clocked by several sources, selected with BMCLK[3:0] bits in the HRTIM_BMCR register: 1346/3178 • BMCLK[3:0] = 0000 to 0101: Master timer and TIMA..E reset/roll-over events. This allows to have burst mode idle and run periods aligned with the timing unit counting period (both in free-running and counter reset mode). • BMCLK[3:0] = 0110 to 1001: The clocking is provided by the general purpose timers, as in Table 301. In this case, the burst mode idle and run periods are not necessarily aligned with timing unit counting period (a pulse on the output may be interrupted, resulting a waveform with modified duty cycle for instance. • BMCLK[3:0] = 1010: The fHRTIM clock prescaled by a factor defined with BMPRSC[3:0] bits in HRTIM_BMCR register. In this case, the burst mode idle and run periods are not necessarily aligned with the timing unit counting period (a pulse on the output may be interrupted, resulting in a waveform with a modified duty cycle, for instance. DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Table 301. Burst mode clock sources from general purpose timer BMCLK[3:0] Clock source 0110 hrtim_bm_ck1: TIM16 OC 0111 hrtim_bm_ck2: TIM17 OC 1000 hrtim_bm_ck3: TIM7 TRGO 1001 hrtim_bm_ck4: Reserved The pulsewidth on TIMxx OC output must be at least N fHRTIM clock cycles long to be detected by the HRTIM burst mode controller. Burst mode triggers To trigger the burst operation, 32 sources are available and are selected using the HRTIM_BMTRGR register: • Software trigger (set by software and reset by hardware) • 6 Master timer events: repetition, reset/roll-over, Compare 1 to 4 • 5 x 4 events from timers A..E: repetition, reset/roll-over, Compare 1 and 2 • hrtim_evt7 (including TIMA event filtering) and hrtim_evt8 (including TIMD event filtering) • Timer A period following hrtim_evt7 (including TIMA event filtering) • Timer D period following hrtim_evt8 (including TIMD event filtering) • On-chip events coming from other general purpose timer (hrtim_bm_trg output:TIM7_TRGO output) These sources can be combined to have multiple concurrent triggers. Burst mode is not re-triggerable. In continuous mode, new triggers are ignored until the burst mode is terminated, while in single-shot mode, the triggers are ignored until the current burst completion including run periods (HRTIM_BMPER+1 cycles). This is also valid for software trigger (the software bit is reset by hardware even if it is discarded). Figure 311 shows how the burst mode is started in response to an external event, either immediately or on the timer period following the event. Figure 311. Burst mode trigger on external event džƚĞƌŶĂůĞǀĞŶƚ ŽƵŶƚĞƌ KƵƚƉƵƚ dƌŝŐŐĞƌŽŶ ĞdžƚĞƌŶĂůĞǀĞŶƚ dƌŝŐŐĞƌŽŶƚŝŵĞƌ ƉĞƌŝŽĚĨŽůůŽǁŝŶŐ ĞdžƚĞƌŶĂůĞǀĞŶƚ KƵƚƉƵƚ ƐƚĂƚĞ ZhE /> ZhE KƵƚƉƵƚ KƵƚƉƵƚ ƐƚĂƚĞ ZhE /> ZhE D^ϯϮϮϴϰsϭ DocID029587 Rev 3 1347/3178 1466 High-Resolution Timer (HRTIM) RM0433 For TAEEV7 and TDEEV8 combined triggers (trigger on a Timer period following an external event), the external event detection is always active, regardless of the burst mode programming and the on-going burst operation: Note: • When the burst mode is enabled (BME=1) or the trigger is enabled (TAEEV7 or TDEEV8 bit set in the BMTRG register) in between the external event and the timer period event, the burst is triggered. • The single-shot burst mode is re-triggered even if the external event occurs before the burst end (as long as the corresponding period happens after the burst). TAEEV7 and TDEEV8 triggers are valid only after a period event. If the counter is reset before the period event, the pending hrtim_evt7/8 event is discarded. Burst mode delayed entry By default, the outputs are taking their idle level (as per IDLES1 and IDLES2 setting) immediately after the burst mode trigger. It is also possible to delay the burst mode entry and force the output to an inactive state during a programmable period before the output takes its idle state. This is useful when driving two complementary outputs, one of them having an active idle state, to avoid a deadtime violation as shown on Figure 312. This prevents any risk of shoot through current in half-bridges, but causes a delayed response to the burst mode entry. 1348/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 312. Delayed burst mode entry with deadtime enabled and IDLESx = 1 ƵƌƐƚdƌŝŐŐĞƌ KƵƚƉƵƚ^ƚĂƚĞ ZhE /> KƵƚƉƵƚϭ /> ^ϭсϭ />ϭсϬ />ϮсϬ ĞĂĚƚŝŵĞ ǀŝŽůĂƚŝŽŶ KƵƚƉƵƚϮ /> ^ϮсϬ KƵƚƉƵƚϭ /> ^ϭсϭ />ϭсϭ />Ϯсϭ ĞůĂLJĞĚŝĚůĞ ƐƚĂƚĞ KƵƚƉƵƚϮ /> ^ϮсϬ D^ϯϮϮϴϱsϭ The delayed burst entry mode is enabled with DIDLx bit in the HRTIM_OUTxR register (one enable bit per output). It forces a deadtime insertion before the output takes its idle state. Each TIMx output has its own deadtime value: – DTRx[8:0] on output 1 when DIDL1 = 1 – DTFx[8:0] on output 2 when DIDL2 = 1 DIDLx bits can be set only if one of the outputs has an active idle level during the burst mode (IDLES = 1) and only when positive deadtimes are used (SDTR/SDTF set to 0). Note: The delayed burst entry mode uses deadtime generator resources. Consequently, when any of the 2 DIDLx bits is set and the corresponding timing unit uses the deadtime insertion (DTEN bit set in HRTIM_OUTxR), it is not possible to use the timerx output 2 as a filter for external events (Tx2 filtering signal is not available). When durations defined by DTRx[8:0] and DTFx[8:0] are lower than 3 fHRTIM clock cycle periods, the limitations related to the narrow pulse management listed in Section 37.3.6 must be applied. When the burst mode entry arrives during the regular deadtime, it is aborted and a new deadtime is re-started corresponding to the inactive period, as on Figure 313. DocID029587 Rev 3 1349/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 313. Delayed Burst mode entry during deadtime ƵƌƐƚŵŽĚĞĞŶƚƌLJ /> ^ ddžϭ ddžϮ /> ^ ZĞŐƵůĂƌĚĞĂĚƚŝŵĞ ;ĂďŽƌƚĞĚǁŚĞŶďƵƌƐƚŝƐƚƌŝŐŐĞƌĞĚͿ d d ĞůĂLJĞĚƵƌƐƚŵŽĚĞĞŶƚƌLJĚĞĂĚƚŝŵĞ D^ϯϮϮϴϲsϭ Burst mode exit The burst mode exit is either forced by software (in continuous mode) or once the idle period is elapsed (in single-shot mode). In both cases, the counter is re-started immediately (if it was hold in a reset state with MTBM or TxBM bit = 1), but the effective output state transition from the idle to active mode only happens after the programmed set/reset event. A burst period interrupt is generated in single-shot and continuous modes when BMPERIE enable bit is set in the HRTIM_IER register. This interrupt can be used to synchronize the burst mode exit with a burst period in continuous burst mode. Figure 314 shows how a normal operation is resumed when the deadtime is enabled. Although the burst mode exit is immediate, this is only effective on the first set event on any of the complementary outputs. Two different cases are presented: 1350/3178 1. The burst mode ends while the signal is inactive on the crossbar output waveform. The active state is resumed on Tx1 and Tx2 on the set event for the Tx1 output, and the Tx2 output does not take the complementary level on burst exit. 2. The burst mode ends while the crossbar output waveform is active: the activity is resumed on the set event of Tx2 output, and Tx1 does not take the active level immediately on burst exit. DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 314. Burst mode exit when the deadtime generator is enabled dŝŵdž ĐŽƵŶƚĞƌ KƵƚϭ ĐƌŽƐƐďĂƌ ǁĂǀĞĨŽƌŵ ƵƌƐƚƐƚĂƚĞ /> ZhE ddžϭ ddžϮ ƵƌƐƚƐƚĂƚĞ /> ZhE ddžϭ ddžϮ D^ϯϮϮϴϳsϭ The behavior described above is slightly different when the push-pull mode is enabled. The push-pull mode forces an output reset at the beginning of the period if the output is inactive, or symmetrically forces an active level if the output was high during the preceding period. Consequently, an output with an active idle state can be reset at the time the burst mode is exited even if no transition is explicitly programmed. For symmetrical reasons, an output can be set at the time the burst mode is exited even if no transition is explicitly programmed, in case it was active when it entered in idle state. Burst mode registers preloading and update BMPREN bit (Burst mode Preload Enable) allows to have the burst mode compare and period registers preloaded (HRTIM_BMCMP and HRTIM_BMPER). When BMPREN is set, the transfer from preload to active register happens: • when the burst mode is enabled (BME = 1), • at the end of the burst mode period. A write into the HRTIM_BMPER period register disables the update temporarily, until the HRTIM_BMCMP compare register is written, to ensure the consistency of the two registers when they are modified. DocID029587 Rev 3 1351/3178 1466 High-Resolution Timer (HRTIM) RM0433 If the compare register only needs to be changed, a single write is necessary. If the period only needs to be changed, it is also necessary to re-write the compare to have the new values taken into account. When BMPREN bits is reset, the write access into BMCMPR and BMPER directly updates the active register. In this case, it is necessary to consider when the update is done during the overall burst period, for the 2 cases below: a) Compare register update If the new compare value is above the current burst mode counter value, the new compare is taken into account in the current period. If the new compare value is below the current burst mode counter value, the new compare is taken into account in the next burst period in continuous mode, and ignored in single-shot mode (no compare match will occur and the idle state will last until the end of the idle period). b) Period register update If the new period value is above the current burst mode counter value, the change is taken into account in the current period. Note: If the new period value is below the current burst mode counter value, the new period will not be taken into account, the burst mode counter will overflow (at 0xFFFF) and the change will be effective in the next period. In single-shot mode, the counter will roll over at 0xFFFF and the burst mode will re-start for another period up to the new programmed value. Burst mode emulation using a compound register The burst mode controller only controls one or a set of timers for a single converter. When the burst mode is necessary for multiple independent timers, it is possible to emulate a simple burst mode controller using the DMA and the HRTIM_CMP1CxR compound register, which holds aliases of both the repetition and the Compare 1 registers. This is applicable to a converter which only requires a simple PWM (typically a buck converter), where the duty cycle only needs to be updated. In this case, the CMP1 register is used to reset the output (and define the duty cycle), while it is set on the period event. In this case, a single 32-bit write access in CMP1CxR is sufficient to define the duty cycle (with the CMP1 value) and the number of periods during which this duty cycle is maintained (with the repetition value). To implement a burst mode, it is then only necessary to transfer by DMA (upon repetition event) two 32-bit data in continuous mode, organized as follows: CMPC1xR = {REP_Run; CMP1 = Duty_Cycle}, {REP_Idle; CMP1 = 0} For instance, the values: {0x0003 0000}: CMP1 = 0 for 3 periods {0x0001 0800}: CMP1 = 0x0800 for 1 period will provide a burst mode with 2 periods active every 6 PWM periods, as shown on Figure 315. 1352/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 315. Burst mode emulation example ŽƵŶƚĞƌ Z W D ƌĞƋƵĞƐƚ DWϭdžZ Z W D ƌĞƋƵĞƐƚ ϬdžϬϬϬϭϬϴϬϬ Z W D ƌĞƋƵĞƐƚ ϬdžϬϬϬϯϬϬϬϬ Z W D ƌĞƋƵĞƐƚ ϬdžϬϬϬϭϬϴϬϬ KƵƚƉƵƚ Z WdžZсϭ DWϭdžZсϬdžϬϴϬϬ Z WdžZсϯ DWϭdžZсϬdžϬϬϬϬ Z WdžZсϭ DWϭdžZсϬdžϬϴϬϬ ZhE /> ;ĞŵƵůĂƚĞĚͿ ZhE D^ϯϮϮϴϴsϭ 37.3.14 Chopper A high-frequency carrier can be added on top of the timing unit output signals to drive isolation transformers. This is done in the output stage before the polarity insertion, as shown on Figure 316, using CHP1 and CHP2 bits in the HRTIM_OUTxR register, to enable chopper on outputs 1 and 2, respectively. Figure 316. Carrier frequency signal insertion &KRSSHU I+57,0 &DUULHU JHQHUDWLRQ 3RODULW\ &+3 6\QF +57,0B&+[ [ )DXOW ,GOH &DUULHU JHQHUDWLRQ &+3 6\QF +57,0B&+[ [ )DXOW,GOHVRXUFHV 069 DocID029587 Rev 3 1353/3178 1466 High-Resolution Timer (HRTIM) RM0433 The chopper parameters can be adjusted using the HRIM_CHPxR register, with the possibility to define a specific pulsewidth at the beginning of the pulse, to be followed by a carrier frequency with programmable frequency and duty cycle, as in Figure 317. CARFRQ[3:0] bits define the frequency, ranging from 156 MHz to 25 MHz (for fHRTIM = 400 MHz) following the formula FCHPFRQ = fHRTIM / (16 x (CARFRQ[3:0]+1)). The duty cycle can be adjusted by 1/8 step with CARDTY[2:0], from 0/8 up to 7/8 duty cycle. When CARDTY[2:0] = 000 (duty cycle = 0/8), the output waveform only contains the starting pulse following the rising edge of the reference waveform, without any added carrier. The pulsewidth of the initial pulse is defined using the STRPW[3:0] bitfield as follows: t1STPW = (STRPW[3:0]+1) x 16 x tHRTIM and ranges from 40 ns to 0.63 µs (for fHRTIM=400 MHz). The carrier frequency parameters are defined based on the fHRTIM frequency, and are not dependent from the CKPSC[2:0] setting. In chopper mode, the carrier frequency and the initial pulsewidth are combined with the reference waveform using an AND function. A synchronization is performed at the end of the initial pulse to have a repetitive signal shape. The chopping signal is stopped at the end of the output waveform active state, without waiting for the current carrier period to be completed. It can thus contain shorter pulses than programmed. Figure 317. HRTIM outputs with Chopper mode enabled ϭ ĂƌƌŝĞƌ ^ƚĂƌƚ dϭ ^ƚĂƌƚƉƵůƐĞǁŝĚƚŚ ĂƌƌŝĞƌƉĞƌŝŽĚ D^ϯϮϯϯϱsϭ Note: CHP1 and CHP2 bits must be set prior to the output enable done with TxyOEN bits in the HRTIM_OENR register. CARFRQ[2:0], CARDTY[2:0] and STRPW[3:0] bitfields cannot be modified while the chopper mode is active (at least one of the two CHPx bits is set). 37.3.15 Fault protection The HRTIMER has a versatile fault protection circuitry to disable the outputs in case of an abnormal operation. Once a fault has been triggered, the outputs take a predefined safe state. This state is maintained until the output is re-enabled by software. In case of a permanent fault request, the output will remain in its fault state, even if the software attempts to re-enable them, until the fault source disappears. The HRTIM has 5 FAULT input channels; all of them are available and can be combined for each of the 5 timing units, as shown on Figure 318. 1354/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 318. Fault protection circuitry (FAULT1 fully represented, FAULT2..5 partially) )$8/7> @ )$8/7> @ +57,0B &+[ 7LPHU[ +57,0B &+[ I)/76FORFNVRXUFH )/765& )/73 )/7)> @ )/7 +57,0B)/7>@ )DXOW )DXOW )LOWHU KUWLPBLQBIOW>@ 3RODULW\ )/7( )DXOW )DXOW &203LQ )/7(1 )/7(1 )/7(1 5HI 6<6)/7 $YDLODEOHIRUVRPH)$8/7 FKDQQHOVRQO\ KUWLPBV\VBIOW 06Y9 Each fault channel is fully configurable using HRTIM_FLTINR1 and HRTIM_FLTINR2 registers before being routed to the timing units. FLTxSRC bit selects the source of the Fault signal, that can be either a digital input or an internal event (built-in comparator output). Table 302 summarizes the available sources for each of the 10 faults channels: Table 302. Fault inputs Fault channel External Input (FLTxSRC = 0) On-chip source (FLTxSRC = 1) FAULT 1 PA15 COMP1 FAULT 2 PC11 COMP2 FAULT 3 PD4 NC FAULT 4 PB3 NC FAULT 5 PG10 NC The polarity of the signal can be selected to define the active level, using the FLTxP polarity bit in HRTIM_FLTINRx registers. If FLTxP = 0, the signal is active at low level; if FLTxP = 1, it is active when high. The fault information can be filtered after the polarity setting. If FLTxF[3:0] bitfield is set to 0000, the signal is not filtered and will act asynchronously, independently from the fHRTIM clock. For all other FLTxF[3:0] bitfield values, the signal is digitally filtered. The digital filter is made of a counter in which a number N of valid samples is needed to validate a transition on the output. If the input value changes before the counter has reached the value N, the counter is reset and the transition is discarded (considered as a spurious event). If the counter reaches N, the transition is considered as valid and transmitted as a correct external DocID029587 Rev 3 1355/3178 1466 High-Resolution Timer (HRTIM) RM0433 event. Consequently, the digital filter adds a latency to the external events being filtered, depending on the sampling clock and on the filter length (number of valid samples expected). Figure 319 shows how a spurious fault signal is filtered. Figure 319. Fault signal filtering (FLTxF[3:0]= 0010: fSAMPLING = fHRTIM, N = 4) Ĩ,Zd/D &ĂƵůƚŝŶƉƵƚ &ŝůƚĞƌĐŽƵŶƚĞƌ Ϭ Ϭ ϭ Ϯ ϯ ϰ Ϭ Ϭ Ϭ Ϭ Ϭ Ϭ ϭ Ϯ Ϭ ϭ Ϯ ϯ ϰ Ϭ &ŝůƚĞƌĞĚƐŝŐŶĂů &ĂƵůƚŝŶƉƵƚ &ŝůƚĞƌĐŽƵŶƚĞƌ &ŝůƚĞƌĞĚƐŝŐŶĂů D^ϯϮϮϴϵsϭ The filtering period ranges from 2 cycles of the fHRTIM clock up to 8 cycles of the fFLTS clock divided by 32. fFLTS is defined using FLTSD[1:0] bits in the HRTIM_FLTINR2 register. Table 303 summarizes the sampling rate and the filter length. A jitter of 1 sampling clock period must be subtracted from the filter length to take into account the uncertainty due to the sampling and have the effective filtering. Table 303. Sampling rate and filter length vs FLTFxF[3:0] and clock setting fFLTS vs FLTSD[1:0] Filter length for fHRTIM = 400 MHz FLTFxF[3:0] 00 01 10 11 Min Max 0001,0010,0011 fHRTIM fHRTIM fHRTIM fHRTIM fHRTIM, N =2 5 ns fHRTIM, N =8 20 ns 0100, 0101 fHRTIM /2 fHRTIM /4 fHRTIM /8 fHRTIM /16 fHRTIM /2, N = 6 30 ns fHRTIM /16, N = 8 320 ns 0110, 0111 fHRTIM /4 fHRTIM /8 fHRTIM /16 fHRTIM /32 fHRTIM /4, N = 6 60 ns fHRTIM /32, N = 8 640 ns 1000, 1001 fHRTIM /8 fHRTIM /16 fHRTIM /32 fHRTIM /64 fHRTIM /8, N = 6 120 ns fHRTIM /64, N = 8 1.28 µs 1356/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Table 303. Sampling rate and filter length vs FLTFxF[3:0] and clock setting (continued) fFLTS vs FLTSD[1:0] Filter length for fHRTIM = 400 MHz FLTFxF[3:0] 00 01 10 11 Min Max 1010, 1011, 1100 fHRTIM /16 fHRTIM /32 fHRTIM /64 fHRTIM /128 fHRTIM /16, N = 5 200 ns fHRTIM /128, N = 8 2.56 µs 1101, 1110, 1111 fHRTIM /32 fHRTIM /64 fHRTIM /128 fHRTIM /256 fHRTIM /32, N = 5 400 ns fHRTIM /256, N = 8 5.12 µs System fault input (hrtim_sys_flt) This fault is provided by the MCU Class B circuitry (see the System configuration controller (SYSCFG) section for details) and corresponds to a system fault coming from: • the Clock Security System • the SRAM parity checker • the Cortex®-M7-lockup signal • the PVD detector This input overrides the FAULT inputs and disables all outputs having FAULTy[1:0] = 01, 10, 11. For each FAULT channel, a write-once FLTxLCK bit in the HRTIM_FLTxR register allows to lock FLTxE, FLTxP, FLTxSRC, FLTxF[3:0] bits (it renders them read-only), for functional safety purpose. If enabled, the fault conditioning set-up is frozen until the next HRTIM or system reset. Once the fault signal is conditioned as explained above, it is routed to the timing units. For any of them, the 5 fault channels are enabled using bits FLT1EN to FLT5EN in the HRTIM_FLTxR register, and they can be selected simultaneously (the sysfault is automatically enabled as long as the output is protected by the fault mechanism). This allows to have, for instance: • One fault channel simultaneously disabling several timing units • Multiple fault channels being ORed to disable a single timing unit A write-once FLTLCK bit in the HRTIM_FLTxR register allows to lock FLTxEN bits (it renders them read-only) until the next reset, for functional safety purpose. If enabled, the timing unit fault-related set-up is frozen until the next HRTIM or system reset. For each of the timers, the output state during a fault is defined with FAULT1[1:0] and FAULT2[1:0] bits in the HRTIM_OUTxR register (see Section 37.3.12). 37.3.16 Auxiliary outputs Timer A to E have auxiliary outputs in parallel with the regular outputs going to the output stage. They provide the following internal status, events and signals: • SETxy and RSTxy status flags, together with the corresponding interrupts and DMA requests • Capture triggers upon output set/reset • External event filters following a Tx2 output copy (see details in Section 37.3.8) DocID029587 Rev 3 1357/3178 1466 High-Resolution Timer (HRTIM) RM0433 The auxiliary outputs are taken either before or after the burst mode controller, depending on the HRTIM operating mode. An overview is given on Figure 320. Figure 320. Auxiliary outputs KƵƚϭ KƵƚϭ WƵƐŚͲƉƵůů Žƌ ĚĞĂĚƚŝŵĞ ŝŶƐĞƌƚŝŽŶ ^ĞƚͬƌĞƐĞƚ ĐƌŽƐƐďĂƌǁŝƚŚ ĞǀĞŶƚƐKZŝŶŐ dŽƚŚĞ ŽƵƚƉƵƚ ƐƚĂŐĞ ƵƌƐƚŵŽĚĞ ĐŽŶƚƌŽůůĞƌ KƵƚϮ KƵƚϮ ƵdžŝůŝĂƌLJŽƵƚƉƵƚĐŝƌĐƵŝƚƌLJ ^ ddžLJͬZ^ddžLJĨůĂŐƐ /ŶƚĞƌƌƵƉƚƐĂŶĚDƌĞƋƵĞƐƚƐ ĂƉƚƵƌĞƚƌŝŐŐĞƌƐ džƚĞƌŶĂůĞǀĞŶƚĨŝůƚĞƌŝŶŐ ;KƵƚϮĐŚĂŶŶĞůŽŶůLJͿ D^ϯϮϮϵϬsϭ By default, the auxiliary outputs are copies of outputs Tx1 and Tx2. The exceptions are: 1358/3178 • The delayed idle and the balanced idle protections, when the deadtime is disabled (DTEN = 0). When the protection is triggered, the auxiliary outputs are maintained and follow the signal coming out of the crossbar. On the contrary, if the deadtime is enabled (DTEN = 1), both main and auxiliary outputs are forced to an inactive level. • The burst mode (TCEN=1, IDLEMx=1); there are 2 cases: a) If DTEN=0 or DIDLx=0, the auxiliary outputs are not affected by the burst mode entry and continue to follow the reference signal coming out of the crossbar (see Figure 321). b) If the deadtime is enabled (DTEN=1) together with the delayed burst mode entry (DIDLx=1), the auxiliary outputs have the same behavior as the main outputs. They are forced to the IDLES level after a deadtime duration, then they keep this level during all the burst period. When the burst mode is terminated, the IDLES level is maintained until a transition occurs to the opposite level, similarly to the main output. DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 321. Auxiliary and main outputs during burst mode (DIDLx = 0) ƵƌƐƚŵŽĚĞ ĞŶƚƌLJ ƵƌƐƚŵŽĚĞ Ğdžŝƚ ƵdžŝůŝĂƌLJ ŽƵƚƉƵƚϭ ƵdžŝůŝĂƌLJ ŽƵƚƉƵƚϮ KƵƚƉƵƚ ddžϭ /> ^ůĞǀĞů KƵƚƉƵƚ ddžϮ /> ^ůĞǀĞů /> ^ůĞǀĞůĐŽŶƚŝŶƵĞĚƵƉ ƚŽƚŚĞƚƌĂŶƐŝƚŝŽŶƚŽƚŚĞ ŽƉƉŽƐŝƚĞůĞǀĞů D^ϯϮϮϵϭsϭ The signal on the auxiliary output can be slightly distorted when exiting from the burst mode or when re-enabling the outputs after a delayed protection, if this happens during a deadtime. In this case, the deadtime applied to the auxiliary outputs is extended so that the deadtime on the main outputs is respected. Figure 322 gives some examples. Figure 322. Deadtime distortion on auxiliary output when exiting burst mode KƵƚϭƌĞƐĞƚƌĞƋƵĞƐƚ ƵƌƐƚĞdžŝƚ ƵdžŝůŝĂƌLJ ŽƵƚƉƵƚϭ ƵdžŝůŝĂƌLJ ŽƵƚƉƵƚϮ WƌŽŐƌĂŵŵĞĚ ĚĞĂĚƚŝŵĞ KƵƚƉƵƚ ddžϭ /> ^сϬ KƵƚƉƵƚ ddžϮ /> ^сϬ džƚĞŶĚĞĚ ĚĞĂĚƚŝŵĞ ƵdžŝůŝĂƌLJ ŽƵƚƉƵƚϭ ƵdžŝůŝĂƌLJ ŽƵƚƉƵƚϮ KƵƚƉƵƚ ddžϭ KƵƚƉƵƚ ddžϮ ĂƐĞϭ͗ƚƌĂŶƐŝƚŝŽŶƌĞƋƵĞƐƚƚŽ ƚŚĞƐĂŵĞůĞǀĞůĂƐ/> ^ ^ĂŵĞĚĞĂĚƚŝŵĞĨŽƌŵĂŝŶĂŶĚ ĂƵdžŝůŝĂƌLJŽƵƚƉƵƚƐ ĂƐĞϮ͗ƚƌĂŶƐŝƚŝŽŶƌĞƋƵĞƐƚƚŽ ĂůĞǀĞůŽƉƉŽƐŝƚĞƚŽ/> ^ ĞĂĚƚŝŵĞŽŶĂƵdžŝůŝĂƌLJŽƵƚƉƵƚ ŝƐĞdžƚĞŶĚĞĚ /> ^сϭ /> ^сϬ WƌŽŐƌĂŵŵĞĚ ĚĞĂĚƚŝŵĞ D^ϯϮϮϵϮsϭ DocID029587 Rev 3 1359/3178 1466 High-Resolution Timer (HRTIM) 37.3.17 RM0433 Synchronizing the HRTIM with other timers or HRTIM instances The HRTIM provides options for synchronizing multiple HRTIM instances, as a master unit (generating a synchronization signal) or as a slave (waiting for a trigger to be synchronized). This feature can also be used to synchronize the HRTIM with other timers, either external or on-chip. The synchronization circuitry is controlled inside the master timer. Synchronization output This section explains how the HRTIM must be configured to synchronize external resources and act as a master unit. Four events can be selected as the source to be sent to the synchronization output. This is done using SYNCSRC[1:0] bits in the HRTIM_MCR register, as follows: • 00: Master timer Start This event is generated when MCEN bit is set or when the timer is re-started after having reached the period value in single-shot mode. It is also generated on a reset which occurs during the counting (when CONT or RETRIG bits are set). • 01: Master timer Compare 1 event • 10: Timer A start This event is generated when TACEN bit is set or when the counter is reset and restarts counting in response to this reset. The following counter reset events are not propagated to the synchronization output: counter roll-over in continuous mode, and discarded reset request in single-shot non-retriggerable mode. The reset is only taken into account when it occurs during the counting (CONT or RETRIG bits are set). • 11: Timer A Compare 1 event SYNCOUT[1:0] bits in the HRTIM_MCR register specify how the synchronization event is generated. The synchronization pulses are generated on the HRTIM_SCOUT output pin, with SYNCOUT[1:0] = 1x. SYNCOUT[0] bit specifies the polarity of the synchronization signal. If SYNCOUT[0] = 0, the HRTIM_SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization). If SYNCOUT[0] = 1, the idle level is high and a negative pulse is generated. Note: The synchronization pulse is followed by an idle level of 16 fHRTIM clock cycles during which any new synchronization request is discarded. Consequently, the maximum synchronization frequency is fHRTIM/32. The idle level on the HRTIM_SCOUT pin is applied as soon as the SYNCOUT[1:0] bits are enabled (i.e. the bitfield value is different from 00). The synchronization output initialization procedure must be done prior to the configuration of the MCU outputs and counter enable, in the following order: 1. SYNCOUT[1:0] and SYNCSRC[1:0] bitfield configuration in HRTIM_MCR 2. HRTIM_SCOUT pin configuration (see the General-purpose I/Os section) 3. Master or Timer A counter enable (MCEN or TACEN bit set) When the synchronization input mode is enabled and starts the counter (using SYNCSTRTM/SYNCSTRTx bits) simultaneously with the synchronization output mode (SYNCSRC[1:0] = 00 or 10), the output pulse is generated only when the counter is starting or is reset while running. Any reset request clearing the counter without causing it to start will not affect the synchronization output. 1360/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Synchronization input The HRTIM can be synchronized by external sources, as per the programming of the SYNCIN[1:0] bits in the HRTIM_MCR register: • 00: synchronization input is disabled • 01: reserved configuration • 10: the on-chip TIM1 general purpose timer (TIM1 TRGO output) • 11: a positive pulse on the HRTIM_SCIN input pin This bitfield cannot be changed once the destination timer (master timer or timing unit) is enabled (MCEN and/or TxCEN bit set). The HRTIM_SCIN input is rising-edge sensitive. The timer behavior is defined with the following bits present in HRTIM_MCR and HRTIM_TIMxCR registers (see Table 304 for details): • Synchronous start: the incoming signal starts the timer’s counter (SYNCSTRTM and/or SYNCSTRTx bits set). TxCEN (MCEN) bits must be set to have the timer enabled and the counter ready to start. In continuous mode, the counter will not start until the synchronization signal is received. • Synchronous reset: the incoming signal resets the counter (SYNCRSTM and/or SYNCRSTx bits set). This event decrements the repetition counter as any other reset event. The synchronization events are taken into account only once the related counters are enabled (MCEN or TxCEN bit set). A synchronization request triggers a SYNC interrupt. Note: A synchronized start event resets the counter if the current counter value is above the active period value. The effect of the synchronization event depends on the timer operating mode, as summarized in Table 304. . Operating mode Table 304. Effect of sync event vs timer operating modes SYNC SYNC RSTx STRTx 0 1 Start events are taken into account when the counter is stopped and: – once the MCEN or TxCEN bits are set – once the period has been reached. A start occurring when the counter is stopped at the period value resets the counter. A reset request clears the counter but does not start it (the counter can solely be re-started with the synchronization). Any reset occurring during the counting is ignored (as during regular nonretriggerable mode). X Reset events are starting the timer counting. They are taken into account only if the counter is stopped and: – once the MCEN or TxCEN bits are set – once the period has been reached. When multiple reset requests are selected (from HRTIM_SCIN and from internal events), only the first arriving request is taken into account. Single-shot non-retriggerable 1 Behavior following a SYNC reset or start event DocID029587 Rev 3 1361/3178 1466 High-Resolution Timer (HRTIM) RM0433 Table 304. Effect of sync event vs timer operating modes (continued) Operating mode SYNC SYNC RSTx STRTx 0 1 The counter start is effective only if the counter is not started or period is elapsed. Any synchronization event occurring after counter start has no effect. A start occurring when the counter is stopped at the period value resets the counter. A reset request clears the counter but does not start it (the counter can solely be started by the synchronization). A reset occurring during counting is taken into account (as during regular retriggerable mode). X The reset from HRTIM_SCIN is taken into account as any HRTIM counter reset from internal events and is starting or re-starting the timer counting. When multiple reset requests are selected, the first arriving request is taken into account. 1 The timer is enabled (MCEN or TxCEN bit set) and is waiting for the synchronization event to start the counter. Any synchronization event occurring after the counter start has no effect (the counter can solely be started by the synchronization). A reset request clears the counter but does not start it. X The reset from HRTIM_SCIN is taken into account as any HRTIM counter reset from internal events and is starting or re-starting the timer counting. When multiple reset requests are selected, the first arriving request is taken into account. Single-shot retriggerable 1 0 Continuous mode 1 Behavior following a SYNC reset or start event Figure 323 presents how the synchronized start is done in single-shot mode. 1362/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 323. Counter behavior in synchronized start mode &RXQWHULQLWLDOL]HGE\VRIWZDUH 3(5 &RXQWHU KUWLPBLQBV\QF>[@ ,QWHUQDOUHVHW UHTXHVW 6<1&67576LQJOHVKRWPRGHQRQUHWULJJHUDEOH &RXQWHULQLWLDOL]HGE\VRIWZDUH 3(5 &RXQWHU KUWLPBLQBV\QF>[@ ,QWHUQDOUHVHW UHTXHVW 6<1&67576LQJOHVKRWPRGHUHWULJJHUDEOH 06Y9 37.3.18 ADC triggers The ADCs can be triggered by the master and the 5 timing units. 4 independent triggers are available to start both the regular and the injected sequencers of the 2 ADCs. Up to 32 events can be combined (ORed) for each trigger output, in registers HRTIM_ADC1R to HRTIM_ADC4R, as shown on Figure 324. Triggers 1/3 and 2/4 are using the same source set. The external events can be used as a trigger. They are taken right after the conditioning defined in HRTIM_EECRx registers, and are not depending on EEFxR1 and EEFxR2 register settings. Multiple triggering is possible within a single switching period by selecting several sources simultaneously. A typical use case is for a non-overlapping multiphase converter, where all phases can be sampled in a row using a single ADC trigger output. DocID029587 Rev 3 1363/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 324. ADC trigger selection overview 7ULJJHU 7ULJJHU 7ULJJHU 7ULJJHU 0DVWHU&PS3(5 0DVWHU&PS3(5 ϱ ϱ ([WHUQDO(YHQWV ([WHUQDO(YHQWV ϱ $'& 7LPHU$&PS3(5567 ϱ $'& ϰ 7ULJJHU 7LPHU$&PS3(5 7ULJJHU ϱ 7LPHU%&PS3(5567 7ULJJHU 7LPHU%&PS3(5 ϱ 7LPHU&&PS3(5 ϰ 7ULJJHU ϰ 2ULQJRIVDPH VRXUFHV 7LPHU&&PS3(5567 ϱ 2ULQJRIVDPH VRXUFHV 7LPHU'&PS3(5567 7LPHU'&PS3(5 ϰ 7LPHU(&PS3(5 ϰ ϱ 7ULJJHU 7ULJJHU 8SGDWH 8SGDWH 7LPHU(&PS567 ϰ $'865&> @ $'865&> @ $'865&> @ 7ULJJHU 7ULJJHU 8SGDWH 8SGDWH $'865&> @ 0DVWHUXSGDWH 7LPHU$XSGDWH 7LPHU%XSGDWH 7LPHU&XSGDWH 7LPHU'XSGDWH 7LPHU(XSGDWH 069 HRTIM_ADC1R to HRTIM_ADC4R registers are preloaded and can be updated synchronously with the timer they are related to. The update source is defined with ADxUSRC[2:0] bits in the HRTIM_CR1 register. For instance, if ADC trigger 1 outputs Timer A CMP2 events (HRTIM_ADC1R = 0x0000 0400), HRTIM_ADC1R will be typically updated simultaneously with Timer A (AD1USRC[2:0] = 001). When the preload is disabled (PREEN bit reset) in the source timer, the HRTIM_ADCxR registers are not preloaded either: a write access will result in an immediate update of the trigger source. 37.3.19 DAC triggers The HRTIMER allows to have the embedded DACs updated synchronously with the timer updates. The update events from the master timer and the timer units can generate DAC update triggers on any of the 3 hrtim_dac_trgx outputs. Note: Each timer has its own DAC-related control register. DACSYNC[1:0] bits of the HRTIM_MCR and HRTIM_TIMxCR registers are programmed as follows: • 00: No update generated • 01: Update generated on hrtim_dac_trg1 • 10: Update generated on hrtim_dac_trg2 • 11: Update generated on hrtim_dac_trg3 An output pulse of 1 fHRTIM clock periods is generated on the hrtim_dac_trgx output. 1364/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) When DACSYNC[1:0] bits are enabled in multiple timers, the hrtim_dac_trgx output will consist of an OR of all timers’ update events. For instance, if DACSYNC = 1 in timer A and in timer B, the update event in timer A will be ORed with the update event in timer B to generate a DAC update trigger on the corresponding hrtim_dac_trgx output, as shown on Figure 325. Figure 325. Combining several updates on a single hrtim_dac_trgx output 7LPHU$ FRXQWHU 7LPHU% FRXQWHU 7$XSGDWH 7LPHU$ &RPSDUH UHJLVWHU [ [ 7%XSGDWH 7LPHU% &RPSDUH UHJLVWHU 7$XSGDWH [ 7%XSGDWH [ 7$XSGDWH [ 7%XSGDWH [ KUWLPBGDFB WUJ[ 06Y 9 hrtim_dac_trgx pins are connected to the DACs as follows: • hrtim_dac_trg1: DAC1_CH1 trigger input 9 (TSEL1[2:0] = 1001 in DAC_CR of DAC1 peripheral) • hrtim_dac_trg2: DAC1_CH2 trigger input 10 (TSEL1[2:0] = 1010 in DAC_CR of DAC1 peripheral) • hrtim_dac_trg3: not connected DocID029587 Rev 3 1365/3178 1466 High-Resolution Timer (HRTIM) 37.3.20 RM0433 HRTIM Interrupts 7 interrupts can be generated by the master timer: • Master timer registers update • Synchronization event received • Master timer repetition event • Master Compare 1 to 4 event 14 interrupts can be generated by each timing unit: • Delayed protection triggered • Counter reset or roll-over event • Output 1 and output 2 reset (transition active to inactive) • Output 1 and output 2 set (transition inactive to active) • Capture 1 and 2 events • Timing unit registers update • Repetition event • Compare 1 to 4 event 8 global interrupts are generated for the whole HRTIM: • System fault and Fault 1 to 5 (regardless of the timing unit attribution) • Burst mode period completed The interrupt requests are grouped in 7 vectors as follows: • hrtim_mst_it: Master timer interrupts (Master Update, Sync Input, Repetition, MCMP1..4) and global interrupt except faults (Burst mode period) • hrtim_tima_it: TIMA interrupts • hrtim_timb_it: TIMB interrupts • hrtim_timc_it: TIMC interrupts • hrtim_timd_it: TIMD interrupts • hrtim_time_it: TIME interrupts • hrtim_fault_it: Dedicated vector all fault interrupts to allow high-priority interrupt handling Table 305 is a summary of the interrupt requests, their mapping and associated control, and status bits. 1366/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Table 305. HRTIM interrupt summary Interrupt vector Event flag Enable control bit Flag clearing bit Burst mode period completed BMPER BMPERIE BMPERC Master timer registers update MUPD MUPDIE MUPDC Synchronization event received SYNC SYNCIE SYNCC Master timer repetition event MREP MREPIE MREPC MCMP1 MCMP1IE MCP1C MCMP2 MCMP2IE MCP2C MCMP3 MCMP3IE MCP3C MCMP4 MCMP4IE MCP4C DLYPRT DLYPRTIE DLYPRTC RST RSTIE RSTC Output 1 and output 2 reset (transition active to inactive) RSTx1 RSTx1IE RSTx1C RSTx2 RSTx2IE RSTx2C Output 1 and output 2 set (transition inactive to active) SETx1 SETx1IE SETx1C SETx2 SETx2IE SETx2C CPT1 CPT1IE CPT1C CPT2 CPT2IE CPT2C Timing unit registers update UPD UPDIE UPDC Repetition event REP REPIE REPC CMP1 CMP1IE CMP1C CMP2 CMP2IE CMP2C CMP3 CMP3IE CMP3C CMP4 CMP4IE CMP4C SYSFLT SYSFLTIE SYSFLTC FLT1 FLT1IE FLT1C FLT2 FLT2IE FLT2C FLT3 FLT3IE FLT3C FLT4 FLT4IE FLT4C FLT5 FLT5IE FLT5C Interrupt event hrtim_mst_it Master Compare 1 to 4 event Delayed protection triggered Counter reset or roll-over event hrtim_tima_it hrtim_timb_it hrtim_timc_it hrtim_timd_it hrtim_time_it Capture 1 and 2 events Compare 1 to 4 event System fault hrtim_fault_it Fault 1 to 5 DocID029587 Rev 3 1367/3178 1466 High-Resolution Timer (HRTIM) 37.3.21 RM0433 DMA Most of the events able to generate an interrupt can also generate a DMA request, even both simultaneously. Each timer (master, TIMA...E) has its own DMA enable register. The individual DMA requests are ORed into 6 channels as follows: Note: • 1 channel for the master timer • 1 channel per timing unit Before disabling a DMA channel (DMA enable bit reset in TIMxDIER), it is necessary to disable first the DMA controller. Table 306 is a summary of the events with their associated DMA enable bits. Table 306. HRTIM DMA request summary DMA capable DMA enable bit Burst mode period completed No N/A Master timer registers update Yes MUPDDE Synchronization event received Yes SYNCDE Master timer repetition event Yes MREPDE Yes MCMP1DE Yes MCMP2DE Yes MCMP3DE Yes MCMP4DE Delayed protection triggered Yes DLYPRTDE Counter reset or roll-over event Yes RSTDE Output 1 and output 2 reset (transition active to inactive) Yes RSTx1DE Yes RSTx2DE Output 1 and output 2 set (transition inactive to active) Yes SETx1DE Yes SETx2DE Yes CPT1DE Yes CPT2DE Timing unit registers update Yes UPDDE Repetition event Yes REPDE Yes CMP1DE Yes CMP2DE Yes CMP3DE Yes CMP4DE System fault No N/A Fault 1 to 5 No N/A Burst mode period completed No N/A DMA Channel Event hrtim_dma1 (Master timer) Master Compare 1 to 4 event hrtim_dma2 (Timer A) hrtim_dma3 (Timer B) hrtim_dma4 (Timer C) hrtim_dma5 (Timer D) hrtim_dma6 (Timer E) Capture 1 and 2 events Compare 1 to 4 event N/A 1368/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Burst DMA transfers In addition to the standard DMA requests, the HRTIM features a DMA burst controller to have multiple registers updated with a single DMA request. This allows to: • update multiple data registers with one DMA channel only, • reprogram dynamically one or several timing units, for converters using multiple timer outputs. The burst DMA feature is only available for one DMA channel, but any of the 6 channels can be selected for burst DMA transfers. The principle is to program which registers are to be written by DMA. The master timer and TIMA..E have the burst DMA update register, where most of their control and data registers are associated with a selection bit: HRTIM_BDMUPR, HRTIM_BDTAUPR to HRTIM_BDTEUPR (this is applicable only for registers with write accesses). A redirection mechanism allows to forward the DMA write accesses to the HRTIM registers automatically, as shown on Figure 326. Figure 326. DMA burst overview +57,0B3(5%5 +57,0B5(3%5 +57,0B&03%5 5HGLUHFWLRQ GHPXOWLSOH[HU +57,0B&03%&5 +57,0B&03%5 +57,0B&03%5 +57,0B&03%5 '0$EXUVWFRQWUROOHU '0$UHTXHVWV 5HJLVWHUVSDUVLQJ '0$EXUVW XSGDWH UHJLVWHUV UHJLVWHUV +57,0B%'7&835 +57,0B%'7%835 +57,0B%'7$835 '0$FRQWUROOHU +57,0B%'0$'5 '0$XQLTXH GHVWLQDWLRQ 069 When the DMA trigger occurs, the HRTIM generates multiple 32-bit DMA requests and parses the update register. If the control bit is set, the write access is redirected to the associated register. If the bit is reset, the register update is skipped and the register parsing is resumed until a new bit set is detected, to trigger a new request. Once the 6 update registers (HRTIM_BDMUPR, 5x HRTIM_BDTxUPR) are parsed, the burst is completed and the system is ready for another DMA trigger (see the flowchart on Figure 327). Note: Any trigger occurring while the burst is on-going is discarded, except if it occurs during the very last data transfer. The burst DMA mode is permanently enabled (there is no enable bit). A burst DMA operation is started by the first write access into the HRTIM_BDMADR register. DocID029587 Rev 3 1369/3178 1466 High-Resolution Timer (HRTIM) RM0433 It is only necessary to have the DMA controller pointing to the HRTIM_BDMADR register as the destination, in the memory, to the peripheral configuration with the peripheral increment mode disabled (the HRTIM handles internally the data re-routing to the final destination register). To re-initialize the burst DMA mode if it was interrupted during a transaction, it is necessary to write at least to one of the 6 update registers. Figure 327. Burst DMA operation flowchart :ULWHDFFHVVWR +57,0B%'0$'5 3DUVH +57,0B%'0835 3DUVH +57,0B%'7$835 3DUVH +57,0B%'7(835 0&5ELWVHW" :ULWHGDWDLQWR +57,0B0&5 7,0$&5ELW VHW" :ULWHGDWDLQWR +57,0B7,0$&5 7,0(&5ELW VHW" :ULWHGDWDLQWR +57,0B7,0(&5 0&,5ELWVHW" :ULWHGDWDLQWR +57,0B0,&5 7,0$,&5 ELWVHW" :ULWHGDWDLQWR +57,0B7,0$,&5 7,0(,&5 ELWVHW" :ULWHGDWDLQWR +57,0B7,0(,&5 0&03ELW VHW" :ULWHGDWDLQWR +57,0B0&03 7,0$)/75 ELWVHW" :ULWHGDWDLQWR +57,0B)/7$5 7,0()/75 ELWVHW" :ULWHGDWDLQWR +57,0B)/7(5 (QGRI'0$EXUVW 069 Several options are available once the DMA burst is completed, depending on the register update strategy. If the PREEN bit is reset (preload disabled), the value written by the DMA is immediately transferred into the active register and the registers are updated sequentially, following the DMA transaction pace. When the preload is enabled (PREEN bit set), there are 3 use cases: 1370/3178 1. The update is done independently from DMA burst transfers (UPDGAT[3:0] = 0000 in HRTIM_TIMxCR and BRSTDMA[1:0] = 00 in HRTIM_MCR). In this case, and if it is necessary to have all transferred data taken into account simultaneously, the user must check that the DMA burst is completed before the update event takes place. On the contrary, if the update event happens while the DMA transfer is on-going, only part of the registers will be loaded and the complete register update will require 2 consecutive update events. 2. The update is done when the DMA burst transfer is completed (UPDGAT[3:0] = 0000 in HRTIM_TIMxCR and BRSTDMA[1:0] = 01 in HRTIM_MCR). This mode guarantees that all new register values are transferred simultaneously. This is done independently DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) from the counter value and can be combined with regular update events, if necessary (for instance, an update on a counter reset when TxRSTU is set). 3. The update is done on the update event following the DMA burst transfer completion (UPDGAT[3:0] = 0010 in HRTIM_TIMxCR and BRSTDMA[1:0] = 10 in HRTIM_MCR). This mode guarantees both a coherent update of all transferred data and the synchronization with regular update events, with the timer counter. In this case, if a regular update request occurs while the transfer is on-going, it will be discarded and the effective update will happen on the next coming update request. The chronogram on Figure 328 presents the active register content for 3 cases: PREEN=0, UPDGAT[3:0] = 0001 and UPDGAT[3:0] = 0001 (when PREEN = 1). Figure 328. Registers update following DMA burst transfer DƌĞƋƵĞƐƚŽŶDWϭĞǀĞŶƚ ƐƚĂƌƚƐDďƵƌƐƚ dŝŵĞƌ ŽƵŶƚĞƌ ZĞƉĞƚŝƚŝŽŶ ĞǀĞŶƚ DƌĞƋƵĞƐƚƐ DĐŽŶƚƌŽůůĞƌǁƌŝƚĞ ĂĐĐĞƐƐĞƐƚŽDZ W Z DWϭ DWϯ W Z;ƉƌĞǀŝŽƵƐͿ W Z;ŶĞǁͿ DWϭ;ƉƌĞǀŝŽƵƐͿ DWϭ;ŶĞǁͿ DWϯ;ƉƌĞǀŝŽƵƐͿ DWϯ;ŶĞǁͿ DWϯ;ƉƌĞǀŝŽƵƐͿ DWϯ;ŶĞǁͿ DWϯ;ƉƌĞǀŝŽƵƐͿ DWϯ;ŶĞǁͿ ZĞŐŝƐƚĞƌĐŽŶƚĞŶƚ WZ EсϬ ZĞŐŝƐƚĞƌĐŽŶƚĞŶƚ WZ Eсϭ ;DWϯƐŚŽǁĞĚŽŶůLJͿ KƉƚŝŽŶϭ͗ƵƉĚĂƚĞĚŽŶĞĂƚƚŚĞĞŶĚŽĨƚŚĞDďƵƌƐƚ ƚƌĂŶƐĨĞƌ;hW'dϯ͗Ϭ@сϬϬϬϭͿ KƉƚŝŽŶϮ͗ƵƉĚĂƚĞĚŽŶĞĂƚƚŚĞĞŶĚŽĨƚŚĞDďƵƌƐƚ ƚƌĂŶƐĨĞƌ;hW'dϯ͗Ϭ@сϬϬϭϬĂŶĚddžZ Whсϭ D^ϯϮϯϰϮsϭ 37.3.22 HRTIM initialization This section describes the recommended HRTIM initialization procedure, including other related MCU peripherals. The HRTIM clock source must be enabled in the Reset and Clock control unit (RCC). The HRTIM control registers can be initialized as per the power converter topology and the timing units use case. All inputs have to be configured (source, polarity, edge-sensitivity). DocID029587 Rev 3 1371/3178 1466 High-Resolution Timer (HRTIM) RM0433 The HRTIM outputs must be set up eventually, with the following sequence: • the polarity must be defined using POLx bits in HRTIM_OUTxR • the FAULT and IDLE states must be configured using FAULTx[1:0] and IDLESx bits in HRTIM_OUTxR The HRTIM outputs are ready to be connected to the MCU I/Os. In the GPIO controller, the selected HRTIM I/Os have to be configured as per the alternate function mapping table in the product datasheet. From this point on, the HRTIM controls the outputs, which are in the IDLE state. The outputs are configured in RUN mode by setting TxyOEN bits in the HRTIM_OENR register. The 2 outputs are in the inactive state until the first valid set/reset event in RUN mode. Any output set/reset event (except software requests using SST, SRT) are ignored as long as TxCEN bit is reset, as well as burst mode requests (IDLEM bit value is ignored). Similarly, any counter reset request coming from the burst mode controller is ignored (if TxBM bit is set). Note: When the deadtime insertion is enabled (DTEN bit set), it is necessary to force the output state by software, using SST and RST bits, to have the outputs in a complementary state as soon as the RUN mode is entered. The HRTIM operation can eventually be started by setting TxCEN or MCEN bits in HRTIM_MCR. If the HRTIM peripheral is reset with the Reset and Clock Controller, the HRTIM outputs are put in IDLE mode with a low level. It is recommended to first disconnect the HRTIMER from the outputs (using the GPIO controller) before performing a peripheral reset. 37.3.23 Debug When a microcontroller enters the debug mode (Cortex®-M7 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_HRTIM_STOP configuration bit in DBG module: • DBG_HRTIM_STOP = 0: no behavior change, the HRTIM continues to operate. • DBG_HRTIM_STOP = 1: all HRTIM timers, including the master, are stopped. The outputs in RUN mode enter the FAULT state if FAULTx[1:0] = 01,10,11, or keep their current state if FAULTx[1:0] = 00. The outputs in idle state are maintained in this state. This is permanently maintained even if the MCU exits the halt mode. This allows to maintain a safe state during the execution stepping. The outputs can be enabled again by settings TxyOEN bit (requires the use of the debugger). Timer behavior during MCU halt when DBG_HRTIM_STOP = 1 The set/reset crossbar, the dead-time and push-pull unit, the idle/balanced fault detection and all the logic driving the normal output in RUN mode are not affected by debug. The output will keep on toggling internally, so as to retrieve regular signals of the outputs when TxyOEN will be set again (during or after the MCU halt). Associated triggers and filters are also following internal waveforms when the outputs are disabled. FAULT inputs and events (any source) are enabled during the MCU halt. Fault status bits can be set and TxyOEN bits reset during the MCU halt if a fault occurs at that time (TxyOEN and TxyODS are not affected by DBG_HRTIM_STOP bit state). 1372/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Synchronization, counter reset, start and reset-start events are discarded in debug mode, as well as capture events. This is to keep all related registers stable as long as the MCU is halted. The counter stops counting when a breakpoint is reached. However, the counter enable signal is not reset; consequently no start event will be emitted when exiting from debug. All counter reset and capture triggers are disabled, as well as external events (ignored as long as the MCU is halted). The outputs SET and RST flags are frozen, except in case of forced software set/reset. A level-sensitive event is masked during the debug but will be active again as soon as the debug will be exited. For edge-sensitive events, if the signal is maintained active during the MCU halt, a new edge is not generated when exiting from debug. The update events are discarded. This prevents any update trigger on hrtim_upd_en[3:1] inputs. DMA triggers are disabled. The burst mode circuit is frozen: the triggers are ignored and the burst mode counter stopped. 37.4 Application use cases 37.4.1 Buck converter Buck converters are of common use as step-down converters. The HRTIM can control up to 10 buck converters with 6 independent switching frequencies. The converter usually operates at a fixed frequency and the Vin/Vout ratio depends on the duty cycle D applied to the power switch:. V out = D × V in The topology is given on Figure 329 with the connection to the ADC for voltage reading. Figure 329. Buck converter topology 9,1 +57,0B &+$ 9287 $'& 069 Figure 330 presents the management of two converters with identical frequency PWM signals. The outputs are defined as follows: • HRTIM_CHA1 set on period, reset on CMP1 • HRTIM_CHA2 set on CMP3, reset on PER The ADC is triggered twice per period, precisely in the middle of the ON time, using CMP2 and CMP4 events. DocID029587 Rev 3 1373/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 330. Dual Buck converter management $'& 7,0$ FRXQWHU $'& $'& $'& $'& $'& 3(5 &03 &03 &03 &03 7,0$ RXWSXWV +57,0B&+$ %8&. +57,0B&+$ %8&. 069 Timers A..E provide either 10 buck converters coupled by pairs (both with identical switching frequencies) or 6 completely independent converters (each of them having a different switching frequency), using the master timer as the 6th time base. 37.4.2 Buck converter with synchronous rectification Synchronous rectification allows to minimize losses in buck converters, by means of a FET replacing the freewheeling diode. Synchronous rectification can be turned on or off on the fly depending on the output current level, as shown on Figure 331. Figure 331. Synchronous rectification depending on output current 9,1 +57,0B &+$ +57,0B &+$ 9287 $'& 069 The main difference vs. a single-switch buck converter is the addition of a deadtime for an almost complementary waveform generation on HRTIM_CHA2, based on the reference waveform on HRTIM_CHA1 (see Figure 332). 1374/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 332. Buck with synchronous rectification $'& $'& $'& 3(5 7,0$ FRXQWHU &03 &03 7,0$ RXWSXWV +57,0B&+$ +57,0B&+$ 6\QFKURQRXV5HFWLILFDWLRQ 65 DFWLYH 65GLVDEOHG 069 37.4.3 Multiphase converters Multiphase techniques can be applied to multiple power conversion topologies (buck, flyback). Their main benefits are: • Reduction of the current ripple on the input and output capacitors • Reduced EMI • Higher efficiency at light load by dynamically changing the number of phases (phase shedding) The HRTIM is able to manage multiple converters. The number of converters that can be controlled depends on the topologies and resources used (including the ADC triggers): • 5 buck converters with synchronous rectification (SR), using the master timer and the 5 timers • 4 buck converters (without SR), using the master timer and 2 timers • ... Figure 334 presents the topology of a 3-phase interleaved buck converter. DocID029587 Rev 3 1375/3178 1466 High-Resolution Timer (HRTIM) RM0433 Figure 333. 3-phase interleaved buck converter +57,0 B&+$ 9,1 +57,0 B&+% 9287 +57,0 B&+& 069 The master timer is responsible for the phase management: it defines the phase relationship between the converters by resetting the timers periodically. The phase-shift is 360° divided by the number of phases, 120° in the given example. The duty cycle is then programmed into each of the timers. The outputs are defined as follows: • HRTIM_CHA1 set on master timer period, reset on TACMP1 • HRTIM_CHB1 set on master timer MCMP1, reset on TBCMP1 • HRTIM_CHC1 set on master timer MCMP2, reset on TCCMP1 The ADC trigger can be generated on TxCMP2 compare event. Since all ADC trigger sources are phase-shifted because of the converter topology, it is possible to have all of them combined into a single ADC trigger to save ADC resources (for instance 1 ADC regular channel for the full multi-phase converter). 1376/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Figure 334. 3-phase interleaved buck converter control 0DVWHU &03 FRXQWHU &03 5HVHW 5HVHW 5HVHW 5HVHW 5HVHW 5HVHW 7,0$ FRXQWHU &03 7,0% FRXQWHU &03 7,0& FRXQWHU &03 +57,0B&+$ +57,0B&+% +57,0B&+& 069 37.4.4 Transition mode Power Factor Correction The basic operating principle is to build up current into an inductor during a fixed Ton time. This current will then decay during the Toff time, and the period will be re-started when it becomes null. This is detected using a Zero Crossing Detection circuitry (ZCD), as shown on Figure 335. With a constant Ton time, the peak current value in the inductor is proportional to the rectified AC input voltage, which provides the power factor correction. Figure 335. Transition mode PFC 9,1 =&' +57,0B &+$ 9287 $'& 2& 06 9 DocID029587 Rev 3 1377/3178 1466 High-Resolution Timer (HRTIM) RM0433 This converter is operating with a constant Ton time and a variable frequency due the Toff time variation (depending on the input voltage). It must also include some features to operate when no zero-crossing is detected, or to limit the Ton time in case of over-current (OC). The OC feedback is usually conditioned with the built-in comparator and routed onto an external event input. Figure 336 presents the waveform during the various operating modes, with the following parameters defined: • Ton Min: masks spurious overcurrent (freewheeling diode recovery current), represented as OC blanking • Ton Max: practically, the converter set-point. It is defined by CMP1 • Toff Min: limits the frequency when the current limit is close to zero (demagnetization is very fast). It is defined with CMP2. • Toff Max: prevents the system to be stuck if no ZCD occurs. It is defined with CMP4 in auto-delayed mode. Both Toff values are auto-delayed since the value must be relative to the output falling edge. Figure 336. Transition mode PFC waveforms &03 &03 =HUR&XUUHQW 'HWHFWLRQ =&' & & & & & =&'EODQNLQJ 2YHU&XUUHQW 2& 2&EODQNLQJ +57,0B &+$ 1RUPDORSHUDWLRQ & 2YHU&XUUHQW 7RII0LQ 7RII0D[ 1RUPDORSHUDWLRQ &DSWXUHHYHQW 069 1378/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5 HRTIM registers 37.5.1 HRTIM Master Timer Control Register (HRTIM_MCR) Address offset: 0x0000h Reset value: 0x0000 0000 31 30 BRSTDMA[1:0] 29 28 27 MREPU Res. PREEN rw rw rw 15 14 13 SYNCSRC[1:0] rw rw 12 SYNCOUT[1:0] rw rw 26 25 DACSYNC[1:0] rw rw rw 11 10 9 SYNCS SYNCR TRTM STM rw rw 24 23 22 Res. Res. Res. rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 Res. Res. HALF RETRI G CONT rw rw rw SYNCIN[1:0] rw rw 21 20 19 18 17 16 TECEN TDCEN TCCEN TBCEN TACEN MCEN CKPSC[2:0] rw rw rw Bits 31:30 BRSTDMA[1:0]: Burst DMA Update These bits define how the update occurs relatively to a burst DMA transaction. 00: Update done independently from the DMA burst transfer completion 01: Update done when the DMA burst transfer is completed 10: Update done on master timer roll-over following a DMA burst transfer completion. This mode only works in continuous mode. 11: reserved Bit 29 MREPU: Master Timer Repetition update This bit defines whether an update occurs when the master timer repetition period is completed (either due to roll-over or reset events). MREPU can be set only if BRSTDMA[1:0] = 00 or 01. 0: Update on repetition disabled 1: Update on repetition enabled Bit 28 Reserved, must be kept at reset value. Bit 27 PREEN: Preload enable This bit enables the registers preload mechanism and defines whether the write accesses to the memory mapped registers are done into HRTIM active or preload registers. 0: Preload disabled: the write access is directly done into the active register 1: Preload enabled: the write access is done into the preload register Bits 26:25 DACSYNC[1:0] DAC Synchronization A DAC synchronization event can be enabled and generated when the master timer update occurs. These bits are defining on which output the DAC synchronization is sent (refer to Section 37.3.19: DAC triggers for connections details). 00: No DAC trigger generated 01: Trigger generated on hrtim_dac_trg1 10: Trigger generated on hrtim_dac_trg2 11: Trigger generated on hrtim_dac_trg3 Bits 24:22 Reserved, must be kept at reset value. Bit 21 TECEN: Timer E counter enable This bit starts the Timer E counter. 0: Timer E counter disabled 1: Timer E counter enabled Note: This bit must not be changed within a minimum of 8 cycles of fHRTIM clock. DocID029587 Rev 3 1379/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 20 TDCEN: Timer D counter enable This bit starts the Timer D counter. 0: Timer D counter disabled 1: Timer D counter enabled Note: This bit must not be changed within a minimum of 8 cycles of fHRTIM clock. Bit 19 TCCEN: Timer C counter enable This bit starts the Timer C counter. 0: Timer C counter disabled 1: Timer C counter enabled Note: This bit must not be changed within a minimum of 8 cycles of fHRTIM clock. Bit 18 TBCEN: Timer B counter enable This bit starts the Timer B counter. 0: Timer B counter disabled 1: Timer B counter enabled Note: This bit must not be changed within a minimum of 8 cycles of fHRTIM clock. Bit 17 TACEN: Timer A counter enable This bit starts the Timer A counter. 0: Timer A counter disabled 1: Timer A counter enabled Note: This bit must not be changed within a minimum of 8 cycles of fHRTIM clock. Bit 16 MCEN: Master timer counter enable This bit starts the Master timer counter. 0: Master counter disabled 1: Master counter enabled Note: This bit must not be changed within a minimum of 8 cycles of fHRTIM clock. Bits 15:14 SYNCSRC[1:0]: Synchronization source These bits define the source and event to be sent on the synchronization outputs SYNCOUT[2:1] 00: Master timer Start 01: Master timer Compare 1 event 10: Timer A start/reset 11: Timer A Compare 1 event Bits 13:12 SYNCOUT[1:0]: Synchronization output These bits define the routing and conditioning of the synchronization output event. 00: disabled 01: Reserved. 10: Positive pulse on HRTIM_SCOUT output (16x fHRTIM clock cycles) 11: Negative pulse on HRTIM_SCOUT output (16x fHRTIM clock cycles) Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set) Bit 11 SYNCSTRTM: Synchronization Starts Master This bit enables the Master timer start when receiving a synchronization input event: 0: No effect on the Master timer 1: A synchronization input event starts the Master timer Bit 10 SYNCRSTM: Synchronization Resets Master This bit enables the Master timer reset when receiving a synchronization input event: 0: No effect on the Master timer 1: A synchronization input event resets the Master timer 1380/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bits 9:8 SYNCIN[1:0] Synchronization input These bits are defining the synchronization input source. 00: disabled. HRTIM is not synchronized and runs in standalone mode. 01: Reserved. 10: Internal event: the HRTIM is synchronized with the on-chip timer (see Synchronization input). 11: External event (input pin). A positive pulse on HRTIM_SCIN input triggers the HRTIM. Note: This parameter cannot be changed once the impacted timers are enabled. Bits 7:6 Reserved, must be kept at reset value. Bit 5 HALF: Half mode This bit enables the half duty-cycle mode: the HRTIM_MCMP1xR active register is automatically updated with HRTIM_MPER/2 value when HRTIM_MPER register is written. 0: Half mode disabled 1: Half mode enabled Bit 4 RETRIG: Re-triggerable mode This bit defines the behavior of the master timer counter in single-shot mode. 0: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped (period elapsed) 1: The timer is re-triggerable: a counter reset is done whatever the counter state (running or stopped) Bit 3 CONT: Continuous mode 0: The timer operates in single-shot mode and stops when it reaches the MPER value 1: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value Bits 2:0 CKPSC[2:0]: Clock prescaler These bits define the master timer clock prescaler ratio. The counter clock equivalent frequency (fCOUNTER) is equal to fHRCK / 2(CKPSC[2:0]-5). The prescaling ratio cannot be modified once the timer is enabled. 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: Reserved 101: fCOUNTER = fHRTIM 110: fCOUNTER = fHRTIM / 2 111: fCOUNTER = fHRTIM / 4 DocID029587 Rev 3 1381/3178 1466 High-Resolution Timer (HRTIM) 37.5.2 RM0433 HRTIM Master Timer Interrupt Status Register (HRTIM_MISR) Address offset: 0x0004h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. MUPD SYNC MREP r r r MCMP4 MCMP3 MCMP2 MCMP1 r r r r Bits 31:7 Reserved, must be kept at reset value. Bit 6 MUPD: Master Update Interrupt Flag This bit is set by hardware when the Master timer registers are updated. 0: No Master Update interrupt occurred 1: Master Update interrupt occurred Bit 5 SYNC: Sync Input Interrupt Flag This bit is set by hardware when a synchronization input event is received. 0: No Sync input interrupt occurred 1: Sync input interrupt occurred Bit 4 MREP: Master Repetition Interrupt Flag This bit is set by hardware when the Master timer repetition period has elapsed. 0: No Master Repetition interrupt occurred 1: Master Repetition interrupt occurred Bit 3 MCMP4: Master Compare 4 Interrupt Flag Refer to MCMP1 description Bit 2 MCMP3: Master Compare 3 Interrupt Flag Refer to MCMP1 description Bit 1 MCMP2: Master Compare 2 Interrupt Flag Refer to MCMP1 description Bit 0 MCMP1: Master Compare 1 Interrupt Flag This bit is set by hardware when the Master timer counter matches the value programmed in the master Compare 1 register. 0: No Master Compare 1 interrupt occurred 1: Master Compare 1 interrupt occurred 1382/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.3 HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR) Address offset: 0x0008h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. MCMP 4C MCMP 3C MCMP 2C MCMP 1C w w w w MREP MUPD SYNCC C C w w w Bits 31:7 Reserved, must be kept at reset value. Bit 6 MUPDC: Master update Interrupt flag clear Writing 1 to this bit clears the MUPDC flag in HRTIM_MISR register Bit 5 SYNCC: Sync Input Interrupt flag clear Writing 1 to this bit clears the SYNC flag in HRTIM_MISR register Bit 4 MREPC: Repetition Interrupt flag clear Writing 1 to this bit clears the MREP flag in HRTIM_MISR register Bit 3 MCMP4C: Master Compare 4 Interrupt flag clear Writing 1 to this bit clears the MCMP4 flag in HRTIM_MISR register Bit 2 MCMP3C: Master Compare 3 Interrupt flag clear Writing 1 to this bit clears the MCMP3 flag in HRTIM_MISR register Bit 1 MCMP2C: Master Compare 2 Interrupt flag clear Writing 1 to this bit clears the MCMP2 flag in HRTIM_MISR register Bit 0 MCMP1C: Master Compare 1 Interrupt flag clear Writing 1 to this bit clears the MCMP1 flag in HRTIM_MISR register DocID029587 Rev 3 1383/3178 1466 High-Resolution Timer (HRTIM) 37.5.4 RM0433 HRTIM Master Timer DMA / Interrupt Enable Register (HRTIM_MDIER) Address offset: 0x000Ch Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 22 21 20 MUPD SYNCD MREP E DE DE 19 18 17 16 MCMP 4DE MCMP 3DE MCMP 2DE MCMP 1DE rw rw rw rw rw rw rw 6 5 4 3 2 1 0 MREPI E MCMP 4IE MCMP 3IE MCMP 2IE MCMP 1IE rw rw rw rw rw MUPDI SYNCI E E rw rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 MUPDDE: Master Update DMA request Enable This bit is set and cleared by software to enable/disable the Master update DMA requests. 0: Master update DMA request disabled 1: Master update DMA request enabled Bit 21 SYNCDE: Sync Input DMA request Enable This bit is set and cleared by software to enable/disable the Sync input DMA requests. 0: Sync input DMA request disabled 1: Sync input DMA request enabled Bit 20 MREPDE: Master Repetition DMA request Enable This bit is set and cleared by software to enable/disable the Master timer repetition DMA requests. 0: Repetition DMA request disabled 1: Repetition DMA request enabled Bit 19 MCMP4DE: Master Compare 4 DMA request Enable Refer to MCMP1DE description Bit 18 MCMP3DE: Master Compare 3 DMA request Enable Refer to MCMP1DE description Bit 17 MCMP2DE: Master Compare 2 DMA request Enable Refer to MCMP1DE description Bit 16 MCMP1DE: Master Compare 1 DMA request Enable This bit is set and cleared by software to enable/disable the Master timer Compare 1 DMA requests. 0: Compare 1 DMA request disabled 1: Compare 1 DMA request enabled Bits 15:6 Reserved, must be kept at reset value. Bit 6 MUPDIE: Master Update Interrupt Enable This bit is set and cleared by software to enable/disable the Master timer registers update interrupts 0: Master update interrupts disabled 1: Master update interrupts enabled 1384/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 5 SYNCIE: Sync Input Interrupt Enable This bit is set and cleared by software to enable/disable the Sync input interrupts 0: Sync input interrupts disabled 1: Sync input interrupts enabled Bit 4 MREPIE: Master Repetition Interrupt Enable This bit is set and cleared by software to enable/disable the Master timer repetition interrupts 0: Master repetition interrupt disabled 1: Master repetition interrupt enabled Bit 3 MCMP4IE: Master Compare 4 Interrupt Enable Refer to MCMP1IE description Bit 2 MCMP3IE: Master Compare 3 Interrupt Enable Refer to MCMP1IE description Bit 1 MCMP2IE: MAster Compare 2 Interrupt Enable Refer to MCMP1IE description Bit 0 MCMP1IE: Master Compare 1 Interrupt Enable This bit is set and cleared by software to enable/disable the Master timer Compare 1 interrupt 0: Compare 1 interrupt disabled 1: Compare 1 interrupt enabled DocID029587 Rev 3 1385/3178 1466 High-Resolution Timer (HRTIM) 37.5.5 RM0433 HRTIM Master Timer Counter Register (HRTIM_MCNTR) Address offset: 0x0010h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MCNT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCNT[15:0]: Counter value Holds the master timer counter value. This register can only be written when the master timer is stopped (MCEN = 0 in HRTIM_MCR). Note: The timer behavior is not guaranteed if the counter value is set above the HRTIM_MPER register value. 37.5.6 HRTIM Master Timer Period Register (HRTIM_MPER) Address offset: 0x0014h Reset value: 0x0000 FFDF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MPER[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MPER[15:0]: Master Timer Period value This register defines the counter overflow value. The period value must be above or equal to 3 periods of the fHRTIM clock. The maximum value is 0x0000 FFDF. 1386/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.7 HRTIM Master Timer Repetition Register (HRTIM_MREP) Address offset: 0x0018h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw MREP[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 MREP[7:0]: Master Timer Repetition period value This register holds the repetition period value for the master counter. It is either the preload register or the active register if preload is disabled. 37.5.8 HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R) Address offset: 0x001Ch Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MCMP1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCMP1[15:0]: Master Timer Compare 1 value This register holds the master timer Compare 1 value. It is either the preload register or the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. DocID029587 Rev 3 1387/3178 1466 High-Resolution Timer (HRTIM) 37.5.9 RM0433 HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R) Address offset: 0x0024h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MCMP2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCMP2[15:0]: Master Timer Compare 2 value This register holds the master timer Compare 2 value. It is either the preload register or the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. 37.5.10 HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R) Address offset: 0x0028h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MCMP3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCMP3[15:0]: Master Timer Compare 3 value This register holds the master timer Compare 3 value. It is either the preload register or the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. 1388/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.11 HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R) Address offset: 0x002Ch Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MCMP4[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 MCMP4[15:0]: Master Timer Compare 4 value This register holds the master timer Compare 4 value. It is either the preload register or the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. DocID029587 Rev 3 1389/3178 1466 High-Resolution Timer (HRTIM) 37.5.12 RM0433 HRTIM Timerx Control Register (HRTIM_TIMxCR) Address offset: 0x0000h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 UPDGAT[3:0] 27 PREEN 26 25 DACSYNC[1:0] 24 23 22 21 20 19 MSTU TEU TDU TCU TBU Res. rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. PSHPL L HALF RETRI G CONT rw rw rw rw DELCMP4[1:0] rw rw DELCMP2[1:0] rw rw SYNCS SYNCR STx TRTx rw rw 18 17 TxRST TxREP U U rw rw 2 1 16 Res. 0 CKPSCx[2:0] rw rw rw Bits 31:28 UPDGAT[3:0]: Update Gating These bits define how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3 (see Table 294: Update enable inputs and sources) The update events, as mentioned below, can be: MSTU, TEU, TDU, TCU, TBU, TAU, TxRSTU, TxREPU. 0000: the update occurs independently from the DMA burst transfer 0001: the update occurs when the DMA burst transfer is completed 0010: the update occurs on the update event following the DMA burst transfer completion 0011: the update occurs on a rising edge of HRTIM update enable input 1 (hrtim_upd_en1) 0100: the update occurs on a rising edge of HRTIM update enable input 2 (hrtim_upd_en2) 0101: the update occurs on a rising edge of HRTIM update enable input 3 (hrtim_upd_en3) 0110: the update occurs on the update event following a rising edge of HRTIM update enable input 1 (hrtim_upd_en1) 0111: the update occurs on the update event following a rising edge of HRTIM update enable input 2 (hrtim_upd_en2) 1000: the update occurs on the update event following a rising edge of HRTIM update enable input 3 (hrtim_upd_en3) Other codes: reserved Note: This bitfield must be reset before programming a new value. For UPDGAT[3:0] values equal to 0001, 0011, 0100, 0101, it is possible to have multiple concurrent update source (for instance RSTU and DMA burst). Bit 27 PREEN: Preload enable This bit enables the registers preload mechanism and defines whether a write access into a preloadable register is done into the active or the preload register. 0: Preload disabled: the write access is directly done into the active register 1: Preload enabled: the write access is done into the preload register Bits 26:25 DACSYNC[1:0] DAC Synchronization A DAC synchronization event is generated when the timer update occurs. These bits are defining on which output the DAC synchronization is sent (refer to Section 37.3.19: DAC triggers for connections details). 00: No DAC trigger generated 01: Trigger generated on hrtim_dac_trg1 10: Trigger generated on hrtim_dac_trg2 11: Trigger generated on hrtim_dac_trg3 1390/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 24 MSTU: Master Timer update Register update is triggered by the master timer update. 0: Update by master timer disabled 1: Update by master timer enabled Bit 23 In HRTIM_TIMACR, HRTIM_TIMBCR, HRTIM_TIMCCR, HRTIM_TIMDCR: TEU: Timer E update Register update is triggered by the timer E update 0: Update by timer E disabled 1: Update by timer E enabled In HRTIM_TIMECR: Reserved, must be kept at reset value Bit 22 In HRTIM_TIMACR, HRTIM_TIMBCR, HRTIM_TIMCCR, HRTIM_TIMECR: TDU: Timer D update Register update is triggered by the timer D update 0: Update by timer D disabled 1: Update by timer D enabled In HRTIM_TIMDCR: Reserved, must be kept at reset value Bit 21 In HRTIM_TIMACR, HRTIM_TIMBCR, HRTIM_TIMDCR, HRTIM_TIMECR: TCU: Timer C update Register update is triggered by the timer C update 0: Update by timer C disabled 1: Update by timer C enabled In HRTIM_TIMCCR: Reserved, must be kept at reset value Bit 20 In HRTIM_TIMACR, HRTIM_TIMCCR, HRTIM_TIMDCR, HRTIM_TIMECR: TBU: Timer B update Register update is triggered by the timer B update 0: Update by timer B disabled 1: Update by timer B enabled In HRTIM_TIMBCR: Reserved, must be kept at reset value Bit 19 In HRTIM_TIMBCR, HRTIM_TIMCCR, HRTIM_TIMDCR, HRTIM_TIMECR: TAU: Timer A update Register update is triggered by the timer A update 0: Update by timer A disabled 1: Update by timer A enabled In HRTIM_TIMACR: Reserved, must be kept at reset value DocID029587 Rev 3 1391/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 18 TxRSTU: Timerx reset update Register update is triggered by Timerx counter reset or roll-over to 0 after reaching the period value in continuous mode. 0: Update by timer x reset / roll-over disabled 1: Update by timer x reset / roll-over enabled Bit 17 TxREPU: Timer x Repetition update Register update is triggered when the counter rolls over and HRTIM_REPx = 0 0: Update on repetition disabled 1: Update on repetition enabled Bit 16 Reserved, must be kept at reset value. Bits 15:14 DELCMP4[1:0]: CMP4 auto-delayed mode This bitfield defines whether the compare register is behaving in standard mode (compare match issued as soon as counter equal compare), or in auto-delayed mode (see Auto-delayed mode). 00: CMP4 register is always active (standard compare mode) 01: CMP4 value is recomputed and is active following a capture 2 event 10: CMP4 value is recomputed and is active following a capture 2 event, or is recomputed and active after Compare 1 match (timeout function if capture 2 event is missing) 11: CMP4 value is recomputed and is active following a capture event, or is recomputed and active after Compare 3 match (timeout function if capture event is missing) Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set) Bits 13:12 DELCMP2[1:0]: CMP2 auto-delayed mode This bitfield defines whether the compare register is behaving in standard mode (compare match issued as soon as counter equal compare), or in auto-delayed mode (see Auto-delayed mode). 00: CMP2 register is always active (standard compare mode) 01: CMP2 value is recomputed and is active following a capture 1 event 10: CMP2 value is recomputed and is active following a capture 1 event, or is recomputed and active after Compare 1 match (timeout function if capture event is missing) 11: CMP2 value is recomputed and is active following a capture 1 event, or is recomputed and active after Compare 3 match (timeout function if capture event is missing) Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set) Bit 11 SYNCSTRTx: Synchronization Starts Timer x This bit defines the Timer x behavior following the synchronization event: 0: No effect on Timer x 1: A synchronization input event starts the Timer x Bit 10 SYNCRSTx: Synchronization Resets Timer x This bit defines the Timer x behavior following the synchronization event: 0: No effect on Timer x 1: A synchronization input event resets the Timer x Bits 9:7 Reserved, must be kept at reset value. Bit 6 PSHPLL: Push-Pull mode enable This bit enables the push-pull mode. 0: Push-Pull mode disabled 1: Push-Pull mode enabled Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set) 1392/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 5 HALF: Half mode enable This bit enables the half duty-cycle mode: the HRTIM_CMP1xR active register is automatically updated with HRTIM_PERxR/2 value when HRTIM_PERxR register is written. 0: Half mode disabled 1: Half mode enabled Bit 4 RETRIG: Re-triggerable mode This bit defines the counter behavior in single shot mode. 0: The timer is not re-triggerable: a counter reset is done if the counter is stopped (period elapsed in single-shot mode or counter stopped in continuous mode) 1: The timer is re-triggerable: a counter reset is done whatever the counter state. Bit 3 CONT: Continuous mode This bit defines the timer operating mode. 0: The timer operates in single-shot mode and stops when it reaches TIMxPER value 1: The timer operates in continuous mode and rolls over to zero when it reaches TIMxPER value Bits 2:0 CKPSCx[2:0]: HRTIM Timer x Clock prescaler These bits define the master timer clock prescaler ratio. The counter clock equivalent frequency (fCOUNTER) is equal to fHRCK / 2(CKPSC[2:0]-5). The prescaling ratio cannot be modified once the timer is enabled. 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: Reserved 101: fCOUNTER = fHRTIM 110: fCOUNTER = fHRTIM / 2 111: fCOUNTER = fHRTIM / 4 DocID029587 Rev 3 1393/3178 1466 High-Resolution Timer (HRTIM) 37.5.13 RM0433 HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR) Address offset: 0x0004h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 O2CPY O1CPY 19 18 17 16 O2STA O1STA IPPSTA CPPST T T AT T r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DLYPR T RST RSTx2 SETx2 RSTx1 SETx1 CPT2 CPT1 UPD Res. REP CMP4 CMP3 CMP2 CMP1 r r r r r r r r r r r r r r Bits 31:22 Reserved, must be kept at reset value. Bit 21 O2CPY: Output 2 Copy This status bit is a raw copy of the output 2 state, before the output stage (chopper, polarity). It allows to check the current output state before re-enabling the output after a delayed protection. 0: Output 2 is inactive 1: Output 2 is active Bit 20 O1CPY: Output 1 Copy This status bit is a raw copy of the output 1 state, before the output stage (chopper, polarity). It allows to check the current output state before re-enabling the output after a delayed protection. 0: Output 1 is inactive 1: Output 1 is active Bit 19 O2STAT: Output 2 Status This status bit indicates the output 2 state when the delayed idle protection was triggered. This bit is updated upon any new delayed protection entry. This bit is not updated in balanced idle. 0: Output 2 was inactive 1: Output 2 was active Bit 18 O1STAT: Output 1 Status This status bit indicates the output 1 state when the delayed idle protection was triggered. This bit is updated upon any new delayed protection entry. This bit is not updated in balanced idle. 0: Output 1 was inactive 1: Output 1 was active Bit 17 IPPSTAT: Idle Push Pull Status This status bit indicates on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered (whatever the output state, active or inactive). 0: Protection occurred when the output 1 was active and output 2 forced inactive 1: Protection occurred when the output 2 was active and output 1 forced inactive Bit 16 CPPSTAT: Current Push Pull Status This status bit indicates on which output the signal is currently applied, in push-pull mode. It is only significant in this configuration. 0: Signal applied on output 1 and output 2 forced inactive 1: Signal applied on output 2 and output 1 forced inactive Bit 15 Reserved Bit 14 DLYPRT: Delayed Protection Flag This bit indicates delayed idle or the balanced idle mode entry. 1394/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 13 RST: Reset and/or roll-over Interrupt Flag This bit is set by hardware when the timer x counter is reset or rolls over in continuous mode. 0: No TIMx counter reset/roll-over interrupt occurred 1: TIMX counter reset/roll-over interrupt occurred Bit 12 RSTx2: Output 2 Reset Interrupt Flag Refer to RSTx1 description Bit 11 SETx2: Output 2 Set Interrupt Flag Refer to SETx1 description Bit 10 RSTx1: Output 1 Reset Interrupt Flag This bit is set by hardware when the Tx1 output is reset (goes from active to inactive mode). 0: No Tx1 output reset interrupt occurred 1: Tx1 output reset interrupt occurred Bit 9 SETx1: Output 1 Set Interrupt Flag This bit is set by hardware when the Tx1 output is set (goes from inactive to active mode). 0: No Tx1 output set interrupt occurred 1: Tx1 output set interrupt occurred Bit 8 CPT2: Capture2 Interrupt Flag Refer to CPT1 description Bit 7 CPT1: Capture1 Interrupt Flag This bit is set by hardware when the timer x capture 1 event occurs. 0: No timer x Capture 1 reset interrupt occurred 1: Timer x output 1 reset interrupt occurred Bit 6 UPD: Update Interrupt Flag This bit is set by hardware when the timer x update event occurs. 0: No timer x update interrupt occurred 1: Timer x update interrupt occurred Bit 5 Reserved, must be kept at reset value. Bit 4 REP: Repetition Interrupt Flag This bit is set by hardware when the timer x repetition period has elapsed. 0: No timer x repetition interrupt occurred 1: Timer x repetition interrupt occurred Bit 3 CMP4: Compare 4 Interrupt Flag Refer to CMP1 description Bit 2 CMP3: Compare 3 Interrupt Flag Refer to CMP1 description Bit 1 CMP2: Compare 2 Interrupt Flag Refer to CMP1 description Bit 0 CMP1: Compare 1 Interrupt Flag This bit is set by hardware when the timer x counter matches the value programmed in the Compare 1 register. 0: No Compare 1 interrupt occurred 1: Compare 1 interrupt occurred DocID029587 Rev 3 1395/3178 1466 High-Resolution Timer (HRTIM) 37.5.14 RM0433 HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR) Address offset: 0x0008h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DLYPR TC RSTC RSTx2 C SET2x C RSTx1 C UPDC Res. w w w w w w w SET1x CPT2C CPT1C C w w w REPC CMP4C CMP3C CMP2C CMP1C w Bits 31:15 Reserved, must be kept at reset value. Bit 14 DLYPRTC: Delayed Protection Flag Clear Writing 1 to this bit clears the DLYPRT flag in HRTIM_TIMxISR register Bit 13 RSTC: Reset Interrupt flag Clear Writing 1 to this bit clears the RST flag in HRTIM_TIMxISR register Bit 12 RSTx2C: Output 2 Reset flag Clear Writing 1 to this bit clears the RSTx2 flag in HRTIM_TIMxISR register Bit 11 SETx2C: Output 2 Set flag Clear Writing 1 to this bit clears the SETx2 flag in HRTIM_TIMxISR register Bit 10 RSTx1C: Output 1 Reset flag Clear Writing 1 to this bit clears the RSTx1 flag in HRTIM_TIMxISR register Bit 9 SETx1C: Output 1 Set flag Clear Writing 1 to this bit clears the SETx1 flag in HRTIM_TIMxISR register Bit 8 CPT2C: Capture2 Interrupt flag Clear Writing 1 to this bit clears the CPT2 flag in HRTIM_TIMxISR register Bit 7 CPT1C: Capture1 Interrupt flag Clear Writing 1 to this bit clears the CPT1 flag in HRTIM_TIMxISR register Bit 6 UPDC: Update Interrupt flag Clear Writing 1 to this bit clears the UPD flag in HRTIM_TIMxISR register Bit 5 Reserved, must be kept at reset value. Bit 4 REPC: Repetition Interrupt flag Clear Writing 1 to this bit clears the REP flag in HRTIM_TIMxISR register Bit 3 CMP4C: Compare 4 Interrupt flag Clear Writing 1 to this bit clears the CMP4 flag in HRTIM_TIMxISR register Bit 2 CMP3C: Compare 3 Interrupt flag Clear Writing 1 to this bit clears the CMP3 flag in HRTIM_TIMxISR register Bit 1 CMP2C: Compare 2 Interrupt flag Clear Writing 1 to this bit clears the CMP2 flag in HRTIM_TIMxISR register Bit 0 CMP1C: Compare 1 Interrupt flag Clear Writing 1 to this bit clears the CMP1 flag in HRTIM_TIMxISR register 1396/3178 DocID029587 Rev 3 w w w w RM0433 High-Resolution Timer (HRTIM) 37.5.15 HRTIM Timerx DMA / Interrupt Enable Register (HRTIM_TIMxDIER) Address offset: 0x000Ch (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 Res. 30 29 28 DLYPR RSTx2 RSTDE TDE DE 27 26 SETx2 DE RSTx1 DE 25 24 23 22 SETx1 CPT2D CPT1D UPDDE DE E E rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 Res. DLYPR TIE RSTIE rw rw RSTx2I SETx2I RSTx1I SET1xI CPT2IE CPT1IE UPDIE E E E E rw rw rw rw rw rw rw 21 20 Res. REPDE 19 18 17 16 CMP4D CMP3D CMP2D CMP1D E E E E rw rw rw rw rw 5 4 3 2 1 0 Res. REPIE CMP4I E CMP3I E CMP2I E CMP1I E rw rw rw rw rw Bit 31 Reserved Bit 30 DLYPRTDE: Delayed Protection DMA request Enable This bit is set and cleared by software to enable/disable DMA requests on delayed protection. 0: Delayed protection DMA request disabled 1: Delayed protection DMA request enabled Bit 29 RSTDE: Reset/roll-over DMA request Enable This bit is set and cleared by software to enable/disable DMA requests on timer x counter reset or roll-over in continuous mode. 0: Timer x counter reset/roll-over DMA request disabled 1: Timer x counter reset/roll-over DMA request enabled Bit 28 RSTx2DE: Output 2 Reset DMA request Enable Refer to RSTx1DE description Bit 27 SETx2DE: Output 2 Set DMA request Enable Refer to SETx1DE description Bit 26 RSTx1DE: Output 1 Reset DMA request Enable This bit is set and cleared by software to enable/disable Tx1 output reset DMA requests. 0: Tx1 output reset DMA request disabled 1: Tx1 output reset DMA request enabled Bit 25 SETx1DE: Output 1 Set DMA request Enable This bit is set and cleared by software to enable/disable Tx1 output set DMA requests. 0: Tx1 output set DMA request disabled 1: Tx1 output set DMA request enabled Bit 24 CPT2DE: Capture 2 DMA request Enable Refer to CPT1DE description Bit 23 CPT1DE: Capture 1 DMA request Enable This bit is set and cleared by software to enable/disable Capture 1 DMA requests. 0: Capture 1 DMA request disabled 1: Capture 1 DMA request enabled Bit 22 UPDDE: Update DMA request Enable This bit is set and cleared by software to enable/disable DMA requests on update event. 0: Update DMA request disabled 1: Update DMA request enabled DocID029587 Rev 3 1397/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 21 Reserved, must be kept at reset value. Bit 20 REPDE: Repetition DMA request Enable This bit is set and cleared by software to enable/disable DMA requests on repetition event. 0: Repetition DMA request disabled 1: Repetition DMA request enabled Bit 19 CMP4DE: Compare 4 DMA request Enable Refer to CMP1DE description Bit 18 CMP3DE: Compare 3 DMA request Enable Refer to CMP1DE description Bit 17 CMP2DE: Compare 2 DMA request Enable Refer to CMP1DE description Bit 16 CMP1DE: Compare 1 DMA request Enable This bit is set and cleared by software to enable/disable the Compare 1 DMA requests. 0: Compare 1 DMA request disabled 1: Compare 1 DMA request enabled Bit 15 Reserved Bit 14 DLYPRTIE: Delayed Protection Interrupt Enable This bit is set and cleared by software to enable/disable interrupts on delayed protection. 0: Delayed protection interrupts disabled 1: Delayed protection interrupts enabled Bit 13 RSTIE: Reset/roll-over Interrupt Enable This bit is set and cleared by software to enable/disable interrupts on timer x counter reset or rollover in continuous mode. 0: Timer x counter reset/roll-over interrupt disabled 1: Timer x counter reset/roll-over interrupt enabled Bit 12 RSTx2IE: Output 2 Reset Interrupt Enable Refer to RSTx1IE description Bit 11 SETx2IE: Output 2 Set Interrupt Enable Refer to SETx1IE description Bit 10 RSTx1IE: Output 1 Reset Interrupt Enable This bit is set and cleared by software to enable/disable Tx1 output reset interrupts. 0: Tx1 output reset interrupts disabled 1: Tx1 output reset interrupts enabled Bit 9 SETx1IE: Output 1 Set Interrupt Enable This bit is set and cleared by software to enable/disable Tx1 output set interrupts. 0: Tx1 output set interrupts disabled 1: Tx1 output set interrupts enabled Bit 8 CPT2IE: Capture Interrupt Enable Refer to CPT1IE description Bit 7 CPT1IE: Capture Interrupt Enable This bit is set and cleared by software to enable/disable Capture 1 interrupts. 0: Capture 1 interrupts disabled 1: Capture 1 interrupts enabled 1398/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 6 UPDIE: Update Interrupt Enable This bit is set and cleared by software to enable/disable update event interrupts. 0: Update interrupts disabled 1: Update interrupts enabled Bit 5 Reserved, must be kept at reset value. Bit 4 REPIE: Repetition Interrupt Enable This bit is set and cleared by software to enable/disable repetition event interrupts. 0: Repetition interrupts disabled 1: Repetition interrupts enabled Bit 3 CMP4IE: Compare 4 Interrupt Enable Refer to CMP1IE description Bit 2 CMP3IE: Compare 3 Interrupt Enable Refer to CMP1IE description Bit 1 CMP2IE: Compare 2 Interrupt Enable Refer to CMP1IE description Bit 0 CMP1IE: Compare 1 Interrupt Enable This bit is set and cleared by software to enable/disable the Compare 1 interrupts. 0: Compare 1 interrupt disabled 1: Compare 1 interrupt enabled DocID029587 Rev 3 1399/3178 1466 High-Resolution Timer (HRTIM) 37.5.16 RM0433 HRTIM Timerx Counter Register (HRTIM_CNTxR) Address offset: 0x0010h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNTx[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNTx[15:0]: Timerx Counter value This register holds the Timerx counter value. It can only be written when the timer is stopped (TxCEN = 0 in HRTIM_TIMxCR). Note: The timer behavior is not guaranteed if the counter value is above the HRTIM_PERxR register value. 37.5.17 HRTIM Timerx Period Register (HRTIM_PERxR) Address offset: 0x14h (this offset address is relative to timer x base address) Reset value: 0x0000 FFDF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PERx[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PERx[15:0]: Timerx Period value This register holds timer x period value. This register holds either the content of the preload register or the content of the active register if preload is disabled. The period value must be above or equal to 3 periods of the fHRTIM clock. The maximum value is 0x0000 FFDF. 1400/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.18 HRTIM Timerx Repetition Register (HRTIM_REPxR) Address offset: 0x18h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw REPx[7:0] rw rw rw rw rw Bits31:8 Reserved, must be kept at reset value. Bits 7:0 REPx[7:0]: Timerx Repetition period value This register holds the repetition period value. This register holds either the content of the preload register or the content of the active register if preload is disabled. 37.5.19 HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR) Address offset: 0x1Ch (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMP1x[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP1x[15:0]: Timerx Compare 1 value This register holds the compare 1 value. This register holds either the content of the preload register or the content of the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. DocID029587 Rev 3 1401/3178 1466 High-Resolution Timer (HRTIM) 37.5.20 RM0433 HRTIM Timerx Compare 1 Compound Register (HRTIM_CMP1CxR) Address offset: 0x20h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 REPx[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMP1x[15:0] rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 REPx[7:0]: Timerx Repetition value (aliased from HRTIM_REPx register) This bitfield is an alias from the REPx[7:0] bitfield in the HRTIMx_REPxR register. Bits 15:0 CMP1x[15:0]: Timerx Compare 1 value This bitfield is an alias from the CMP1x[15:0] bitfield in the HRTIMx_CMP1xR register. 37.5.21 HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR) Address offset: 0x24h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMP2x[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP2x[15:0]: Timerx Compare 2 value This register holds the Compare 2 value. This register holds either the content of the preload register or the content of the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. This register can behave as an auto-delayed compare register, if enabled with DELCMP2[1:0] bits in HRTIM_TIMxCR. 1402/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.22 HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR) Address offset: 0x28h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMP3x[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP3x[15:0]: Timerx Compare 3 value This register holds the Compare 3 value. This register holds either the content of the preload register or the content of the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. 37.5.23 HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR) Address offset: 0x2Ch (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMP4x[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP4x[15:0]: Timerx Compare 4 value This register holds the Compare 4 value. This register holds either the content of the preload register or the content of the active register if preload is disabled. The compare value must be above or equal to 3 periods of the fHRTIM clock. This register can behave as an auto-delayed compare register, if enabled with DELCMP4[1:0] bits in HRTIM_TIMxCR. DocID029587 Rev 3 1403/3178 1466 High-Resolution Timer (HRTIM) 37.5.24 RM0433 HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR) Address offset: 0x30h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CPT1x[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CPT1x[15:0]: Timerx Capture 1 value This register holds the counter value when the capture 1 event occurred. 37.5.25 HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR) Address offset: 0x34h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CPT2x[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CPT2x[15:0]: Timerx Capture 2 value This register holds the counter value when the capture 2 event occurred. 1404/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.26 HRTIM Timerx Deadtime Register (HRTIM_DTxR) Address offset: 0x38h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 DTFLK DTFSL x Kx rwo rwo 15 14 DTRLK DTRSL x Kx rwo rwo 29 28 27 26 25 Res. Res. Res. Res. SDTFx 13 12 11 10 Res. DTPRSC[1:0] rw rw 24 23 22 21 19 18 17 16 DTFx[8:0] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw SDTRx rw 20 rw DTRx[8:0] rw rw rw rw rw Bit 31 DTFLKx: Deadtime Falling Lock This write-once bit prevents the deadtime (sign and value) to be modified, if enabled. 0: Deadtime falling value and sign is writable 1: Deadtime falling value and sign is read-only Note: This bit is not preloaded Bit 30 DTFSLKx: Deadtime Falling Sign Lock This write-once bit prevents the sign of falling deadtime to be modified, if enabled. 0: Deadtime falling sign is writable 1: Deadtime falling sign is read-only Note: This bit is not preloaded Bits 29:26 Reserved, must be kept at reset value. Bit 25 SDTFx: Sign Deadtime Falling value This register determines whether the deadtime is positive (signals not overlapping) or negative (signals overlapping). 0: Positive deadtime on falling edge 1: Negative deadtime on falling edge Bits 24:16 DTFx[8:0]: Deadtime Falling value This register holds the value of the deadtime following a falling edge of reference PWM signal. tDTF = DTFx[8:0] x tDTG Bit 15 DTRLKx: Deadtime Rising Lock This write-once bit prevents the deadtime (sign and value) to be modified, if enabled 0: Deadtime rising value and sign is writable 1: Deadtime rising value and sign is read-only Note: This bit is not preloaded Bit 14 DTRSLKx: Deadtime Rising Sign Lock This write-once bit prevents the sign of deadtime to be modified, if enabled 0: Deadtime rising sign is writable 1: Deadtime rising sign is read-only Note: This bit is not preloaded Bit 13 Reserved, must be kept at reset value. DocID029587 Rev 3 1405/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bits 12:10 DTPRSC[2:0]: Deadtime Prescaler This register holds the value of the deadtime clock prescaler. tDTG = (2(DTPRSC[2:0]-3)) x tHRTIM 000: Reserved 001: Reserved 010: Reserved 011: tDTG= tHRTIM 100: tDTG= tHRTIM x 2 101: tDTG= tHRTIM x 4 110: tDTG= tHRTIM x 8 111: tDTG= tHRTIM x 16 This bitfield is read-only as soon as any of the lock bit is enabled (DTFLKs, DTFSLKx, DTRLKx, DTRSLKx). Bit 9 SDTRx: Sign Deadtime Rising value This register determines whether the deadtime is positive or negative (overlapping signals) 0: Positive deadtime on rising edge 1: Negative deadtime on rising edge Bits 8:0 DTRx[8:0]: Deadtime Rising value This register holds the value of the deadtime following a rising edge of reference PWM signal. tDTR = DTRx[8:0] x tDTG 1406/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.27 HRTIM Timerx Output1 Set Register (HRTIM_SETx1R) Address offset: 0x3Ch (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 EXT EXT EXT EXT TIM EXT EXT EXT EXT EXT EXT TIM TIM UPDAT EVNT1 E EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 EVNT4 EVNT3 EVNT2 EVNT1 EVNT9 EVNT8 EVNT7 0 17 16 TIM EVNT6 TIM EVNT5 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST CMP4 MST CMP3 MST CMP2 MST CMP1 MST PER CMP4 CMP3 CMP2 CMP1 PER RESYNC SST rw rw rw rw rw rw rw rw rw rw rw rw TIM TIM TIM TIM EVNT4 EVNT3 EVNT2 EVNT1 rw rw rw rw Bit 31 UPDATE: Registers update (transfer preload to active) Register update event forces the output to its active state. Bit 30 EXTEVNT10: External Event 10 Refer to EXTEVNT1 description Bit 29 EXTEVNT9: External Event 9 Refer to EXTEVNT1 description Bit 28 EXTEVNT8: External Event 8 Refer to EXTEVNT1 description Bit 27 EXTEVNT7: External Event 7 Refer to EXTEVNT1 description Bit 26 EXTEVNT6: External Event 6 Refer to EXTEVNT1 description Bit 25 EXTEVNT5: External Event 5 Refer to EXTEVNT1 description Bit 24 EXTEVNT4: External Event 4 Refer to EXTEVNT1 description Bit 23 EXTEVNT3: External Event 3 Refer to EXTEVNT1 description Bit 22 EXTEVNT2: External Event 2 Refer to EXTEVNT1 description Bit 21 EXTEVNT1: External Event 1 External event 1 forces the output to its active state. Bit 20 TIMEVNT9: Timer Event 9 Refer to TIMEVNT1 description Bit 19 TIMEVNT8: Timer Event 8 Refer to TIMEVNT1 description Bit 18 TIMEVNT7: Timer Event 7 Refer to TIMEVNT1 description Bit 17 TIMEVNT6: Timer Event 6 Refer to TIMEVNT1 description DocID029587 Rev 3 1407/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 16 TIMEVNT5: Timer Event 5 Refer to TIMEVNT1 description Bit 15 TIMEVNT4: Timer Event 4 Refer to TIMEVNT1 description Bit 14 TIMEVNT3: Timer Event 3 Refer to TIMEVNT1 description Bit 13 TIMEVNT2: Timer Event 2 Refer to TIMEVNT1 description Bit 12 TIMEVNT1:Timer Event 1 Timers event 1 forces the output to its active state (refer to Table 287 for Timer Events assignments) Bit 11 MSTCMP4: Master Compare 4 Master Timer Compare 4 event forces the output to its active state. Bit 10 MSTCMP3: Master Compare 3 Master Timer Compare 3 event forces the output to its active state. Bit 9 MSTCMP2: Master Compare 2 Master Timer Compare 2 event forces the output to its active state. Bit 8 MSTCMP1: Master Compare 1 Master Timer compare 1 event forces the output to its active state. Bit 7 MSTPER: Master Period The master timer counter roll-over in continuous mode, or to the master timer reset in single-shot mode forces the output to its active state. Bit 6 CMP4: Timer x Compare 4 Timer A compare 4 event forces the output to its active state. Bit 5 CMP3: Timer x Compare 3 Timer A compare 3 event forces the output to its active state. Bit 4 CMP2: Timer x Compare 2 Timer A compare 2 event forces the output to its active state. Bit 3 CMP1: Timer x Compare 1 Timer A compare 1 event forces the output to its active state. Bit 2 PER: Timer x Period Timer A Period event forces the output to its active state. Bit 1 RESYNC: Timer A resynchronization Timer A reset event coming solely from software or SYNC input forces the output to its active state. Note: Other timer reset are not affecting the output when RESYNC=1 Bit 0 SST: Software Set trigger This bit forces the output to its active state. This bit can only be set by software and is reset by hardware. Note: This bit is not preloaded 1408/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.28 HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R) Address offset: 0x40h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXT EXT EXT EXT TIM EXT EXT EXT EXT EXT EXT TIM TIM TIM TIM UPDAT EVNT1 E EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 EVNT4 EVNT3 EVNT2 EVNT1 EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST CMP4 MST CMP3 MST CMP2 MST CMP1 MST PER CMP4 CMP3 CMP2 CMP1 PER RESYN C SRT rw rw rw rw rw rw rw rw rw rw rw rw 17 16 TIM TIM TIM TIM EVNT4 EVNT3 EVNT2 EVNT1 rw rw rw rw Bits 31:0 Refer to HRTIM_SETx1R bits description. These bits are defining the source which can force the Tx1 output to its inactive state. 37.5.29 HRTIM Timerx Output2 Set Register (HRTIM_SETx2R) Address offset: 0x44h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 EXT EXT EXT EXT TIM EXT EXT EXT EXT EXT EXT TIM TIM TIM TIM UPDAT EVNT1 E EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 EVNT4 EVNT3 EVNT2 EVNT1 EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST CMP4 MST CMP3 MST CMP2 MST CMP1 MST PER CMP4 CMP3 CMP2 CMP1 PER RESYN C SST rw rw rw rw rw rw rw rw rw rw rw rw TIM TIM TIM TIM EVNT4 EVNT3 EVNT2 EVNT1 rw rw rw rw Bits 31:0 Refer to HRTIM_SETx1R bits description. These bits are defining the source which can force the Tx2 output to its active state. DocID029587 Rev 3 1409/3178 1466 High-Resolution Timer (HRTIM) 37.5.30 RM0433 HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R) Address offset: 0x48h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXT EXT EXT EXT TIM EXT EXT EXT EXT EXT EXT TIM TIM TIM TIM UPDAT EVNT1 E EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 EVNT4 EVNT3 EVNT2 EVNT1 EVNT9 EVNT8 EVNT7 EVNT6 EVNT5 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST CMP4 MST CMP3 MST CMP2 MST CMP1 MST PER CMP4 CMP3 CMP2 CMP1 PER RESYN C SRT rw rw rw rw rw rw rw rw rw rw rw rw TIM TIM TIM TIM EVNT4 EVNT3 EVNT2 EVNT1 rw rw rw rw Bits 31:0 Refer to HRTIM_SETx1R bits description. These bits are defining the source which can force the Tx2 output to its inactive state. 1410/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.31 HRTIM Timerx External Event Filtering Register 1 (HRTIM_EEFxR1) Address offset: 0x4Ch (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 27 26 25 24 EE5LT CH EE5FLTR[3:0] rw rw rw rw rw 12 11 10 9 8 EE3LT CH EE3FLTR[2:0] rw 28 rw Res. 23 Res. rw rw 20 19 18 EE4LT CH rw rw rw rw rw 6 5 4 3 2 EE2LT CH rw 21 EE4FLTR[3:0] 7 EE2FLTR[3:0] rw 22 rw Res. 17 16 Res. EE3FL TR[3] rw 1 EE1FLTR[3:0] rw rw rw 0 EE1LT CH rw rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:25 EE5FLTR[3:0]: External Event 5 filter Refer to EE1FLTR[3:0] description Bit 24 EE5LTCH: External Event 5 latch Refer to EE1LTCH description Bit 23 Reserved, must be kept at reset value. Bits 22:19 EE4FLTR[3:0]: External Event 4 filter Refer to EE1FLTR[3:0] description Bit 18 EE4LTCH: External Event 4 latch Refer to EE1LTCH description Bit 17 Reserved, must be kept at reset value. Bits 16:13 EE3FLTR[3:0]: External Event 3 filter Refer to EE1FLTR[3:0] description Bit 12 EE3LTCH: External Event 3 latch Refer to EE1LTCH description Bit 11 Reserved, must be kept at reset value. Bits 10:7 EE2FLTR[3:0]: External Event 2 filter Refer to EE1FLTR[3:0] description Bit 6 EE2LTCH: External Event 2 latch Refer to EE1LTCH description DocID029587 Rev 3 1411/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 5 Reserved, must be kept at reset value. Bits 4:1 EE1FLTR[3:0]: External Event 1 filter 0000: No filtering 0001: Blanking from counter reset/roll-over to Compare 1 0010: Blanking from counter reset/roll-over to Compare 2 0011: Blanking from counter reset/roll-over to Compare 3 0100: Blanking from counter reset/roll-over to Compare 4 0101: Blanking from another timing unit: TIMFLTR1 source (see Table 291 for details) 0110: Blanking from another timing unit: TIMFLTR2 source (see Table 291 for details) 0111: Blanking from another timing unit: TIMFLTR3 source (see Table 291 for details) 1000: Blanking from another timing unit: TIMFLTR4 source (see Table 291 for details) 1001: Blanking from another timing unit: TIMFLTR5 source (see Table 291 for details) 1010: Blanking from another timing unit: TIMFLTR6 source (see Table 291 for details) 1011: Blanking from another timing unit: TIMFLTR7 source (see Table 291 for details) 1100: Blanking from another timing unit: TIMFLTR8 source (see Table 291 for details) 1101: Windowing from counter reset/roll-over to Compare 2 1110: Windowing from counter reset/roll-over to Compare 3 1111: Windowing from another timing unit: TIMWIN source (see Table 292 for details) Note: Whenever a compare register is used for filtering, the value must be strictly above 0. This bitfield must not be modified once the counter is enabled (TxCEN bit set) Bit 0 EE1LTCH: External Event 1 latch 0: Event 1 is ignored if it happens during a blank, or passed through during a window. 1: Event 1 is latched and delayed till the end of the blanking or windowing period. Note: A timeout event is generated in window mode (EE1FLTR[3:0]=1101, 1110, 1111) if EE1LTCH = 0, except if the External event is programmed in fast mode (EExFAST = 1). This bitfield must not be modified once the counter is enabled (TxCEN bit set) 1412/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.32 HRTIM Timerx External Event Filtering Register 2 (HRTIM_EEFxR2) Address offset: 0x50h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 27 26 25 24 EE10LT CH EE10FLTR[3:0] rw rw rw rw rw 12 11 10 9 8 EE8LT CH EE8FLTR[2:0] rw 28 rw Res. 23 Res. rw rw 20 19 18 EE9LT CH rw rw rw rw rw 6 5 4 3 2 EE7LT CH rw 21 EE9FLTR[3:0] 7 EE7FLTR[3:0] rw 22 rw Res. 17 16 Res. EE8FL TR[3] rw 1 EE6FLTR[3:0] rw rw rw 0 EE6LT CH rw rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:25 EE10FLTR[3:0]: External Event 10 filter Refer to EE1FLTR[3:0] description Bit 24 EE10LTCH: External Event 10 latch Refer to EE1LTCH description Bit 23 Reserved, must be kept at reset value. Bits 22:19 EE9FLTR[3:0]: External Event 9 filter Refer to EE1FLTR[3:0] description Bit 18 EE9LTCH: External Event 9 latch Refer to EE1LTCH description Bit 17 Reserved, must be kept at reset value. Bits 16:13 EE8FLTR[3:0]: External Event 8 filter Refer to EE1FLTR[3:0] description Bit 12 EE8LTCH: External Event 8 latch Refer to EE1LTCH description Bit 11 Reserved, must be kept at reset value. Bits 10:7 EE7FLTR[3:0]: External Event 7 filter Refer to EE1FLTR[3:0] description Bit 6 EE7LTCH: External Event 7 latch Refer to EE1LTCH description Bit 5 Reserved, must be kept at reset value. Bits 4:1 EE6FLTR[3:0]: External Event 6 filter Refer to EE1FLTR[3:0] description Bit 0 EE6LTCH: External Event 6 latch Refer to EE1LTCH description DocID029587 Rev 3 1413/3178 1466 High-Resolution Timer (HRTIM) 37.5.33 RM0433 HRTIM Timerx Reset Register (HRTIM_RSTxR) HRTIM TimerA Reset Register (HRTIM_RSTAR) Address offset: 0xD4h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. TIME CMP4 TIME CMP2 TIME CMP1 TIMD CMP4 TIMD CMP2 TIMD CMP1 TIMC CMP4 TIMC CMP2 TIMC CMP1 TIMB CMP4 TIMB CMP2 TIMB CMP1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSTC MP4 MSTC MP3 MSTC MP2 CMP4 CMP2 UPDT Res. rw rw rw rw rw rw EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV NT7 NT5 NT4 NT3 NT2 NT1 NT6 rw rw rw rw rw rw rw MSTC MSTPE MP1 R rw Bit 31 Reserved, must be kept at reset value. Bit 30 TECPM4: Timer E Compare 4 The timer A counter is reset upon timer E Compare 4 event. Bit 29 TECMP2: Timer E Compare 2 The timer A counter is reset upon timer E Compare 2 event. Bit 28 TECMP1: Timer E Compare 1 The timer A counter is reset upon timer E Compare 1 event. Bit 27 TDCMP4: Timer D Compare 4 The timer A counter is reset upon timer D Compare 4 event. Bit 26 TDCMP2: Timer D Compare 2 The timer A counter is reset upon timer D Compare 2 event. Bit 25 TDCMP1: Timer D Compare 1 The timer A counter is reset upon timer D Compare 1 event. Bit 24 TCCMP4: Timer C Compare 4 The timer A counter is reset upon timer C Compare 4 event. Bit 23 TCCMP2: Timer C Compare 2 The timer A counter is reset upon timer C Compare 2 event. Bit 22 TCCMP1: Timer C Compare 1 The timer A counter is reset upon timer C Compare 1 event. Bit 21 TBCMP4: Timer B Compare 4 The timer A counter is reset upon timer B Compare 4 event. Bit 20 TBCMP2: Timer B Compare 2 The timer A counter is reset upon timer B Compare 2 event. Bit 19 TBCMP1: Timer B Compare 1 The timer A counter is reset upon timer B Compare 1 event. Bit 18 EXTEVNT10: External Event The timer A counter is reset upon external event 10. Bit 17 EXTEVNT9: External Event 9 The timer A counter is reset upon external event 9. 1414/3178 DocID029587 Rev 3 rw 18 17 16 EXTEV EXTEV EXTEV NT10 NT9 NT8 RM0433 High-Resolution Timer (HRTIM) Bit 16 EXTEVNT8: External Event 8 The timer A counter is reset upon external event 8. Bit 15 EXTEVNT7: External Event 7 The timer A counter is reset upon external event 7. Bit 14 EXTEVNT6: External Event 6 The timer A counter is reset upon external event 6. Bit 13 EXTEVNT5: External Event 5 The timer A counter is reset upon external event 5. Bit 12 EXTEVNT4: External Event 4 The timer A counter is reset upon external event 4. Bit 11 EXTEVNT3: External Event 3 The timer A counter is reset upon external event 3. Bit 10 EXTEVNT2: External Event 2 The timer A counter is reset upon external event 2. Bit 9 EXTEVNT1: External Event 1 The timer A counter is reset upon external event 1. Bit 8 MSTCMP4: Master compare 4 The timer A counter is reset upon master timer Compare 4 event. Bit 7 MSTCMP3: Master compare 3 The timer A counter is reset upon master timer Compare 3 event. Bit 6 MSTCMP2: Master compare 2 The timer A counter is reset upon master timer Compare 2 event. Bit 5 MSTCMP1: Master compare 1 The timer A counter is reset upon master timer Compare 1 event. Bit 4 MSTPER Master timer Period The timer A counter is reset upon master timer period event. Bit 3 CMP4: Timer A compare 4 reset The timer A counter is reset upon Timer A Compare 4 event. Bit 2 CMP2: Timer A compare 2 reset The timer A counter is reset upon Timer A Compare 2 event. Bit 1 UPDT: Timer A Update reset The timer A counter is reset upon update event. Bit 0 Reserved, must be kept at reset value. DocID029587 Rev 3 1415/3178 1466 High-Resolution Timer (HRTIM) RM0433 HRTIM TimerB Reset Register (HRTIM_RSTBR) Address offset: 0x154h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. TIME CMP4 TIME CMP2 TIME CMP1 TIMD CMP4 TIMD CMP2 TIMD CMP1 TIMC CMP4 TIMC CMP2 TIMC CMP1 TIMA CMP4 TIMA CMP2 TIMA CMP1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSTC MP4 MSTC MP3 MSTC MP2 CMP4 CMP2 UPDT Res. rw rw rw rw rw rw 18 17 EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV NT7 NT5 NT4 NT3 NT2 NT1 NT6 rw rw rw rw rw rw rw MSTC MSTPE MP1 R rw rw 18 17 16 EXTEV EXTEV EXTEV NT10 NT9 NT8 Bits 30:1 Refer to HRTIM_RSTAR bits description. Bits 30:19 differ (reset signals come from TIMA, TIMC, TIMD and TIME) HRTIM TimerC Reset Register (HRTIM_RSTCR) Address offset: 0x1D4h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. TIME CMP4 TIME CMP2 TIME CMP1 TIMD CMP4 TIMD CMP2 TIMD CMP1 TIMB CMP4 TIMB CMP2 TIMB CMP1 TIMA CMP4 TIMA CMP2 TIMA CMP1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSTC MP4 MSTC MP3 MSTC MP2 CMP4 CMP2 UPDT Res. rw rw rw rw rw rw 18 17 EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV NT7 NT5 NT4 NT3 NT2 NT1 NT6 rw rw rw rw rw rw rw MSTC MSTPE MP1 R rw rw 16 EXTEV EXTEV EXTEV NT10 NT9 NT8 Bits 30:1 Refer to HRTIM_RSTAR bits description. Bits 30:19 differ (reset signals come from TIMA, TIMB, TIMD and TIME) HRTIM TimerD Reset Register (HRTIM_RSTDR) Address offset: 0x254h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. TIME CMP4 TIME CMP2 TIME CMP1 TIMC CMP4 TIMC CMP2 TIMC CMP1 TIMB CMP4 TIMB CMP2 TIMB CMP1 TIMA CMP4 TIMA CMP2 TIMA CMP1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSTC MP4 MSTC MP3 MSTC MP2 CMP4 CMP2 UPDT Res. rw rw rw rw rw rw EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV NT7 NT5 NT4 NT3 NT2 NT1 NT6 rw rw rw rw rw rw rw MSTC MSTPE MP1 R rw rw Bits 30:1 Refer to HRTIM_RSTAR bits description. Bits 30:19 differ (reset signals come from TIMA, TIMB, TIMC and TIME) 1416/3178 DocID029587 Rev 3 16 EXTEV EXTEV EXTEV NT10 NT9 NT8 RM0433 High-Resolution Timer (HRTIM) HRTIM Timerx Reset Register (HRTIM_RSTER) Address offset: 0x2D4h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. TIMD CMP4 TIMD CMP2 TIMD CMP1 TIMC CMP4 TIMC CMP2 TIMC CMP1 TIMB CMP4 TIMB CMP2 TIMB CMP1 TIMA CMP4 TIMA CMP2 TIMA CMP1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSTC MP4 MSTC MP3 MSTC MP2 CMP4 CMP2 UPDT Res. rw rw rw rw rw rw EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV EXTEV NT7 NT5 NT4 NT3 NT2 NT1 NT6 rw rw rw rw rw rw rw MSTC MSTPE MP1 R rw rw 18 17 16 EXTEV EXTEV EXTEV NT10 NT9 NT8 Bits 30:1 Refer to HRTIM_RSTAR bits description. Bits 30:19 differ (reset signals come from TIMA, TIMB, TIMC and TIMD) 37.5.34 HRTIM Timerx Chopper Register (HRTIM_CHPxR) Address offset: 0x58h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. STRTPW[3:0] rw rw rw CARDTY[2:0 ) rw rw rw CARFRQ[3:0] rw rw rw rw rw Bits 31:11 Reserved, must be kept at reset value. DocID029587 Rev 3 1417/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bits 10:7 STRPW[3:0]: Timerx start pulsewidth This register defines the initial pulsewidth following a rising edge on output signal. This bitfield cannot be modified when one of the CHPx bits is set. t1STPW = (STRPW[3:0]+1) x 16 x tHRTIM. 0000: 40 ns (1/25 MHz) ... 1111: 640 ns (16/25 MHz) Bits 6:4 CARDTY[2:0]: Timerx chopper duty cycle value This register defines the duty cycle of the carrier signal. This bitfield cannot be modified when one of the CHPx bits is set. 000: 0/8 (i.e. only 1st pulse is present) ... 111: 7/8 Bits 3:0 CARFRQ[3:0]: Timerx carrier frequency value This register defines the carrier frequency FCHPFRQ = fHRTIM / (16 x (CARFRQ[3:0]+1)). This bitfield cannot be modified when one of the CHPx bits is set. 0000: 25 MHz (fHRTIM/ 16) ... 1111: 1.56 MHz (fHRTIM / 256) 1418/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.35 HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR) Address offset: 0x5Ch (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 Reserved (for TIME only) 26 25 24 23 Reserved (for TIMD only) TECMP TECMP TE1RS TE1SE 2 1 T T TDCM P2 TDCM P1 22 21 20 19 Reserved (for TIMC only) TD1RS TD1SE T T TCCM P2 TCCM P1 18 17 16 Reserved (for TIMB only) TC1RS TC1SE TBCMP TBCMP TB1RS TB1SE 2 1 T T T T rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved (for TIMA only) TACMP TACMP TA1RS TA1SE 2 1 T T rw rw rw rw EXEV1 EXEV9 EXEV8 EXEV7 EXEV6 EXEV5 EXEV4 EXEV3 EXEV2 EXEV1 UPDCP SWCP T 0CPT CPT CPT CPT CPT CPT CPT CPT CPT CPT T rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Refer to HRTIM_CPT2xCR bit description DocID029587 Rev 3 1419/3178 1466 High-Resolution Timer (HRTIM) 37.5.36 RM0433 HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR) Address offset: 0x60h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 Reserved (for TIME only) 26 25 24 23 Reserved (for TIMD only) TECMP TECMP TE1RS TE1SE 2 1 T T TDCM P2 TDCM P1 22 21 20 19 Reserved (for TIMC only) TD1RS TD1SE T T TCCM P2 TCCM P1 18 17 16 Reserved (for TIMB only) TC1RS TC1SE TBCMP TBCMP TB1RS TB1SE 2 1 T T T T rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved (for TIMA only) TACMP TACMP TA1RS TA1SE 2 1 T T rw rw rw rw EXEV1 EXEV9 EXEV8 EXEV7 EXEV6 EXEV5 EXEV4 EXEV3 EXEV2 EXEV1 UPDCP SWCP T 0CPT CPT CPT CPT CPT CPT CPT CPT CPT CPT T rw rw rw rw rw rw Bit 31 TECMP2: Timer E Compare 2 Refer to TACMP1 description Note: This bit is reserved for Timer E Bit 30 TECMP1: Timer E Compare 1 Refer to TACMP1 description Note: This bit is reserved for Timer E Bit 29 TE1RST: Timer E output 1 Reset Refer to TA1RST description Note: This bit is reserved for Timer E Bit 28 TE1SET: Timer E output 1 Set Refer to TA1SET description Note: This bit is reserved for Timer E Bit 27 TDCMP2: Timer D Compare 2 Refer to TACMP1 description Note: This bit is reserved for Timer D Bit 26 TDCMP1:Timer D Compare 1 Refer to TACMP1 description Note: This bit is reserved for Timer D Bit 25 TD1RST: Timer D output 1 Reset Refer to TA1RST description Note: This bit is reserved for Timer D Bit 24 TD1SET: Timer D output 1 Set Refer to TA1SET description Note: This bit is reserved for Timer D Bit 23 TCCMP2: Timer C Compare 2 Refer to TACMP1 description Note: This bit is reserved for Timer C 1420/3178 DocID029587 Rev 3 rw rw rw rw rw rw RM0433 High-Resolution Timer (HRTIM) Bit 22 TCCMP1:Timer C Compare 1 Refer to TACMP1 description Note: This bit is reserved for Timer C Bit 21 TC1RST: Timer C output 1 Reset Refer to TA1RST description Note: This bit is reserved for Timer C Bit 20 TC1SET: Timer C output 1 Set Refer to TA1SET description Note: This bit is reserved for Timer C Bit 19 TBCMP2: Timer B Compare 2 Refer to TACMP1 description Note: This bit is reserved for Timer B Bit 18 TBCMP1: Timer B Compare 1 Refer to TACMP1 description Note: This bit is reserved for Timer B Bit 17 TB1RST: Timer B output 1 Reset Refer to TA1RST description Note: This bit is reserved for Timer B Bit 16 TB1SET: Timer B output 1 Set Refer to TA1SET description Note: This bit is reserved for Timer B Bit 15 TACMP2: Timer A Compare 2 Timer A Compare 2 triggers Capture 2. Note: This bit is reserved for Timer A Bit 14 TACMP1: Timer A Compare 1 Timer A Compare 1 triggers Capture 2. Note: This bit is reserved for Timer A Bit 13 TA1RST: Timer B output 1 Reset Capture 2 is triggered by HRTIM_CHA1 output active to inactive transition. Note: This bit is reserved for Timer A Bit 12 TA1SET: Timer B output 1 Set Capture 2 is triggered by HRTIM_CHA1 output inactive to active transition. Note: This bit is reserved for Timer A Bit 11 EXEV10CPT: External Event 10 Capture Refer to EXEV1CPT description Bit 10 EXEV9CPT: External Event 9 Capture Refer to EXEV1CPT description Bit 9 EXEV8CPT: External Event 8 Capture Refer to EXEV1CPT description Bit 8 EXEV7CPT: External Event 7 Capture Refer to EXEV1CPT description Bit 7 EXEV6CPT: External Event 6 Capture Refer to EXEV1CPT description DocID029587 Rev 3 1421/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 6 EXEV5CPT: External Event 5 Capture Refer to EXEV1CPT description Bit 5 EXEV4CPT: External Event 4 Capture Refer to EXEV1CPT description Bit 4 EXEV3CPT: External Event 3 Capture Refer to EXEV1CPT description Bit 3 EXEV2CPT: External Event 2 Capture Refer to EXEV1CPT description Bit 2 EXEV1CPT: External Event 1 Capture The External event 1 triggers the Capture 2. Bit 1 UPDCPT: Update Capture The update event triggers the Capture 2. Bit 0 SWCPT: Software Capture This bit forces the Capture 2 by software. This bit is set only, reset by hardware 1422/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.37 HRTIM Timerx Output Register (HRTIM_OUTxR) Address offset: 0x64h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. DLYPR TEN rw DLYPRT[2:0] rw rw rw 23 22 21 20 FAULT2[1:0 ] 19 18 IDLEM IDLES2 2 17 16 POL2 Res. DIDL2 CHP2 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DTEN DIDL1 CHP1 IDLES1 IDLEM 1 POL1 Res. rw rw rw rw rw rw FAULT1[1:0 ] rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 DIDL2: Output 2 Deadtime upon burst mode Idle entry This bit can delay the idle mode entry by forcing a deadtime insertion before switching the outputs to their idle state. This setting only applies when entering in idle state during a burst mode operation. 0: The programmed Idle state is applied immediately to the Output 2 1: Deadtime (inactive level) is inserted on output 2 before entering the idle mode. The deadtime value is set by DTFx[8:0]. Note: This parameter cannot be changed once the timer x is enabled. DIDL=1 can be set only if one of the outputs is active during the burst mode (IDLES=1), and with positive deadtimes (SDTR/SDTF set to 0). Bit 22 CHP2: Output 2 Chopper enable This bit enables the chopper on output 2 0: Output signal is not altered 1: Output signal is chopped by a carrier signal Note: This parameter cannot be changed once the timer x is enabled. Bits 21:20 FAULT2[1:0]: Output 2 Fault state These bits select the output 2 state after a fault event 00: No action: the output is not affected by the fault input and stays in run mode. 01: Active 10: Inactive 11: High-Z Note: This parameter cannot be changed once the timer x is enabled (TxCEN bit set), if FLTENx bit is set or if the output is in FAULT state. Bit 19 IDLES2: Output 2 Idle State This bit selects the output 2 idle state 0: Inactive 1: Active Note: This parameter must be set prior to have the HRTIM controlling the outputs. Bit 18 IDLEM2: Output 2 Idle mode This bit selects the output 2 idle mode 0: No action: the output is not affected by the burst mode operation 1: The output is in idle state when requested by the burst mode controller. Note: This bit is preloaded and can be changed during run-time, but must not be changed while the burst mode is active. DocID029587 Rev 3 1423/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 17 POL2: Output 2 polarity This bit selects the output 2 polarity 0: positive polarity (output active high) 1: negative polarity (output active low) Note: This parameter cannot be changed once the timer x is enabled. Bits 16:12 Reserved, must be kept at reset value. Bits 12:10 DLYPRT[2:0]: Delayed Protection These bits define the source and outputs on which the delayed protection schemes are applied. In HRTIM_OUTAR, HRTIM_OUTBR, HRTIM_OUTCR: 000: Output 1 delayed Idle on external Event 6 001: Output 2 delayed Idle on external Event 6 010: Output 1 and output 2 delayed Idle on external Event 6 011: Balanced Idle on external Event 6 100: Output 1 delayed Idle on external Event 7 101: Output 2 delayed Idle on external Event 7 110: Output 1 and output 2 delayed Idle on external Event 7 111: Balanced Idle on external Event 7 In HRTIM_OUTDR, HRTIM_OUTER: 000: Output 1 delayed Idle on external Event 8 001: Output 2 delayed Idle on external Event 8 010: Output 1 and output 2 delayed Idle on external Event 8 011: Balanced Idle on external Event 8 100: Output 1 delayed Idle on external Event 9 101: Output 2 delayed Idle on external Event 9 110: Output 1 and output 2 delayed Idle on external Event 9 111: Balanced Idle on external Event 9 Note: This bitfield must not be modified once the delayed protection is enabled (DLYPRTEN bit set) Bit 9 DLYPRTEN: Delayed Protection Enable This bit enables the delayed protection scheme 0: No action 1: Delayed protection is enabled, as per DLYPRT[2:0] bits Note: This parameter cannot be changed once the timer x is enabled (TxEN bit set). Bit 8 DTEN: Deadtime enable This bit enables the deadtime insertion on output 1 and output 2 0: Output 1 and output 2 signals are independent. 1: Deadtime is inserted between output 1 and output 2 (reference signal is output 1 signal generator) Note: This parameter cannot be changed once the timer is operating (TxEN bit set) or if its outputs are enabled and set/reset by another timer. Bit 7 DIDL1: Output 1 Deadtime upon burst mode Idle entry This bit can delay the idle mode entry by forcing a deadtime insertion before switching the outputs to their idle state. This setting only applies when entering the idle state during a burst mode operation. 0: The programmed Idle state is applied immediately to the Output 1 1: Deadtime (inactive level) is inserted on output 1 before entering the idle mode. The deadtime value is set by DTRx[8:0]. Note: This parameter cannot be changed once the timer x is enabled. DIDL=1 can be set only if one of the outputs is active during the burst mode (IDLES=1), and with positive deadtimes (SDTR/SDTF set to 0). 1424/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 6 CHP1: Output 1 Chopper enable This bit enables the chopper on output 1 0: Output signal is not altered 1: Output signal is chopped by a carrier signal Note: This parameter cannot be changed once the timer x is enabled. Bits 5:4 FAULT1[1:0]: Output 1 Fault state These bits select the output 1 state after a fault event 00: No action: the output is not affected by the fault input and stays in run mode. 01: Active 10: Inactive 11: High-Z Note: This parameter cannot be changed once the timer x is enabled (TxCEN bit set), if FLTENx bit is set or if the output is in FAULT state. Bit 3 IDLES1: Output 1 Idle State This bit selects the output 1 idle state 0: Inactive 1: Active Note: This parameter must be set prior to HRTIM controlling the outputs. Bit 2 IDLEM1: Output 1 Idle mode This bit selects the output 1 idle mode 0: No action: the output is not affected by the burst mode operation 1: The output is in idle state when requested by the burst mode controller. Note: This bit is preloaded and can be changed during runtime, but must not be changed while burst mode is active. Bit 1 POL1: Output 1 polarity This bit selects the output 1 polarity 0: positive polarity (output active high) 1: negative polarity (output active low) Note: This parameter cannot be changed once the timer x is enabled. Bit 0 Reserved DocID029587 Rev 3 1425/3178 1466 High-Resolution Timer (HRTIM) 37.5.38 RM0433 HRTIM Timerx Fault Register (HRTIM_FLTxR) Address offset: 0x68h (this offset address is relative to timer x base address) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FLTLC K Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLT5E N FLT4E N FLT3E N FLT2E N FLT1E N rw rw rw rw rw rwo Bit 31 FLTLCK: Fault sources Lock 0: FLT1EN..FLT5EN bits are read/write 1: FLT1EN..FLT5EN bits are read only The FLTLCK bit is write-once. Once it has been set, it cannot be modified till the next system reset. Bits 30:5 Reserved, must be kept at reset value. Bit 4 FLT5EN: Fault 5 enable 0: Fault 5 input ignored 1: Fault 5 input is active and can disable HRTIM outputs. Bit 3 FLT4EN: Fault 4 enable 0: Fault 4 input ignored 1: Fault 4 input is active and can disable HRTIM outputs. Bit 2 FLT3EN: Fault 3 enable 0: Fault 3 input ignored 1: Fault 3 input is active and can disable HRTIM outputs. Bit 1 FLT2EN: Fault 2 enable 0: Fault 2 input ignored 1: Fault 2 input is active and can disable HRTIM outputs. Bit 0 FLT1EN: Fault 1 enable 0: Fault 1 input ignored 1: Fault 1 input is active and can disable HRTIM outputs. 1426/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.39 HRTIM Control Register 1 (HRTIM_CR1) Address offset: 0x380h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TEUDI S TDUDI S TCUDI S TBUDI S TAUDI S MUDIS rw rw rw rw rw rw AD4USRC[2:0] 23 22 21 AD3USRC[2:0] 20 19 18 AD2USRC[2:0] 17 16 AD1USRC[2:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:25 AD4USRC[2:0]: ADC Trigger 4 Update Source Refer to AD1USRC[2:0] description Bits 24:22 AD3USRC[2:0]: ADC Trigger 3 Update Source Refer to AD1USRC[2:0] description Bits 21:19 AD2USRC[2:0]: ADC Trigger 2 Update Source Refer to AD1USRC[2:0] description Bits 18:16 AD1USRC[2:0]: ADC Trigger 1 Update Source These bits define the source which will trigger the update of the HRTIM_ADC1R register (transfer from preload to active register). It only defines the source timer. The precise condition is defined within the timer itself, in HRTIM_MCR or HRTIM_TIMxCR. 000: Master Timer 001: Timer A 010: Timer B 011: Timer C 100: Timer D 101: Timer E 110, 111: Reserved Bits 15:6 Reserved, must be kept at reset value. Bit 5 TEUDIS: Timer E Update Disable Refer to TAUDIS description Bit 4 TDUDIS: Timer D Update Disable Refer to TAUDIS description Bit 3 TCUDIS: Timer C Update Disable Refer to TAUDIS description DocID029587 Rev 3 1427/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 2 TBUDIS: Timer B Update Disable Refer to TAUDIS description Bit 1 TAUDIS: Timer A Update Disable This bit is set and cleared by software to enable/disable an update event generation temporarily on Timer A. 0: update enabled. The update occurs upon generation of the selected source. 1: update disabled. The updates are temporarily disabled to allow the software to write multiple registers that have to be simultaneously taken into account. Bit 0 MUDIS: Master Update Disable This bit is set and cleared by software to enable/disable an update event generation temporarily. 0: update enabled. 1: update disabled. The updates are temporarily disabled to allow the software to write multiple registers that have to be simultaneously taken into account. 1428/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.40 HRTIM Control Register 2 (HRTIM_CR2) Address offset: 0x384h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. MRST Res. Res. TESW U TDSW U TCSW U rw rw rw TERST TDRST TCRST TBRST TARST rw rw rw rw rw rw TBSW TASWU MSWU U rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bit 13 TERST: Timer E counter software reset Refer to TARST description Bit 12 TDRST: Timer D counter software reset Refer to TARST description Bit 11 TCRST: Timer C counter software reset Refer to TARST description Bit 10 TBRST: Timer B counter software reset Refer to TARST description Bit 9 TARST: Timer A counter software reset Setting this bit resets the TimerA counter. The bit is automatically reset by hardware. Bit 8 MRST: Master Counter software reset Setting this bit resets the Master timer counter. The bit is automatically reset by hardware. Bits 7:6 Reserved, must be kept at reset value. Bit 5 TESWU: Timer E Software Update Refer to TASWU description Bit 4 TDSWU: Timer D Software Update Refer to TASWU description Bit 3 TCSWU: Timer C Software Update Refer to TASWU description Bit 2 TBSWU: Timer B Software Update Refer to TASWU description Bit 1 TASWU: Timer A Software update This bit is set by software and automatically reset by hardware. It forces an immediate transfer from the preload to the active register and any pending update request is cancelled. Bit 0 MSWU: Master Timer Software update This bit is set by software and automatically reset by hardware. It forces an immediate transfer from the preload to the active register in the master timer and any pending update request is cancelled. DocID029587 Rev 3 1429/3178 1466 High-Resolution Timer (HRTIM) 37.5.41 RM0433 HRTIM Interrupt Status Register (HRTIM_ISR) Address offset: 0x388h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BMPER Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSFLT FLT5 FLT4 FLT3 FLT2 FLT1 r r r r r r Bits 31:18 Reserved, must be kept at reset value. Bit 17 BMPER: Burst mode Period Interrupt Flag This bit is set by hardware when a single-shot burst mode operation is completed or at the end of a burst mode period in continuous mode. It is cleared by software writing it at 1. 0: No Burst mode period interrupt occurred 1: Burst mode period interrupt occurred Bits 16:6 Reserved, must be kept at reset value. Bit 5 SYSFLT: System Fault Interrupt Flag Refer to FLT1 description Bit 4 FLT5: Fault 5 Interrupt Flag Refer to FLT1 description Bit 3 FLT4: Fault 4 Interrupt Flag Refer to FLT1 description Bit 2 FLT3: Fault 3 Interrupt Flag Refer to FLT1 description Bit 1 FLT2: Fault 2 Interrupt Flag Refer to FLT1 description Bit 0 FLT1: Fault 1 Interrupt Flag This bit is set by hardware when Fault 1 event occurs. It is cleared by software writing it at 1. 0: No Fault 1 interrupt occurred 1: Fault 1 interrupt occurred 1430/3178 DocID029587 Rev 3 RM0433 37.5.42 High-Resolution Timer (HRTIM) HRTIM Interrupt Clear Register (HRTIM_ICR) Address offset: 0x38Ch Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BMPERC Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLT4C FLT3C FLT2C FLT1C w w w w w SYSFLTC FLT5C w Bits 31:18 Reserved, must be kept at reset value. Bit 17 BMPERC: Burst mode period flag Clear Writing 1 to this bit clears the BMPER flag in HRTIM_ISR register. Bits 16:6 Reserved, must be kept at reset value. Bit 5 SYSFLTC: System Fault Interrupt Flag Clear Writing 1 to this bit clears the SYSFLT flag in HRTIM_ISR register. Bit 4 FLT5C: Fault 5 Interrupt Flag Clear Writing 1 to this bit clears the FLT5 flag in HRTIM_ISR register. Bit 3 FLT4C: Fault 4 Interrupt Flag Clear Writing 1 to this bit clears the FLT4 flag in HRTIM_ISR register. Bit 2 FLT3C: Fault 3 Interrupt Flag Clear Writing 1 to this bit clears the FLT3 flag in HRTIM_ISR register. Bit 1 FLT2C: Fault 2 Interrupt Flag Clear Writing 1 to this bit clears the FLT2 flag in HRTIM_ISR register. Bit 0 FLT1C: Fault 1 Interrupt Flag Clear Writing 1 to this bit clears the FLT1 flag in HRTIM_ISR register. DocID029587 Rev 3 1431/3178 1466 High-Resolution Timer (HRTIM) 37.5.43 RM0433 HRTIM Interrupt Enable Register (HRTIM_IER) Address offset: 0x390h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BMPERIE Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw SYSFLTIE FLT5IE FLT4IE FLT3IE rw rw rw 1 0 FLT2IE FLT1IE rw rw Bits 31:18 Reserved, must be kept at reset value. Bit 17 BMPERIE: Burst mode period Interrupt Enable This bit is set and cleared by software to enable/disable the Burst mode period interrupt. 0: Burst mode period interrupt disabled 1: Burst mode period interrupt enabled Bits 16:6 Reserved, must be kept at reset value. Bit 5 SYSFLTIE: System Fault Interrupt Enable Refer to FLT1IE description Bit 4 FLT5IE: Fault 5 Interrupt Enable Refer to FLT1IE description Bit 3 FLT4IE: Fault 4 Interrupt Enable Refer to FLT1IE description Bit 2 FLT3IE: Fault 3 Interrupt Enable Refer to FLT1IE description Bit 1 FLT2IE: Fault 2 Interrupt Enable Refer to FLT1IE description Bit 0 FLT1IE: Fault 1 Interrupt Enable This bit is set and cleared by software to enable/disable the Fault 1 interrupt. 0: Fault 1 interrupt disabled 1: Fault 1 interrupt enabled 1432/3178 DocID029587 Rev 3 RM0433 37.5.44 High-Resolution Timer (HRTIM) HRTIM Output Enable Register (HRTIM_OENR) Address offset: 0x394h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. TE2O EN TE1O EN TD2O EN TD1O EN TC2O EN TC1O EN TB2O EN TB1O EN TA2O EN TA1O EN rs rs rs rs rs rs rs rs rs rs Bits 31:10 Reserved, must be kept at reset value. Bit 9 TE2OEN: Timer E Output 2 Enable Refer to TA1OEN description Bit 8 TE1OEN: Timer E Output 1 Enable Refer to TA1OEN description Bit 7 TD2OEN: Timer D Output 2 Enable Refer to TA1OEN description Bit 6 TD1OEN: Timer D Output 1 Enable Refer to TA1OEN description Bit 5 TC2OEN: Timer C Output 2 Enable Refer to TA1OEN description Bit 4 TC1OEN: Timer C Output 1 Enable Refer to TA1OEN description Bit 3 TB2OEN: Timer B Output 2 Enable Refer to TA1OEN description Bit 2 TB1OEN: Timer B Output 1 Enable Refer to TA1OEN description Bit 1 TA2OEN: Timer A Output 2 Enable Refer to TA1OEN description Bit 0 TA1OEN: Timer A Output 1 (HRTIM_CHA1) Enable Setting this bit enables the Timer A output 1. Writing “0” has no effect. Reading the bit returns the output enable/disable status. This bit is cleared asynchronously by hardware as soon as the timer-related fault input(s) is (are) active. 0: output HRTIM_CHA1 disabled. The output is either in Fault or Idle state. 1: output HRTIM_CHA1 enabled Note: The disable status corresponds to both idle and fault states. The output disable status is given by TA1ODS bit in the HRTIM_ODSR register. DocID029587 Rev 3 1433/3178 1466 High-Resolution Timer (HRTIM) 37.5.45 RM0433 HRTIM Output Disable Register (HRTIM_ODISR) Address offset: 0x398h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. TE2OD TE1OD TD2OD TD1OD TC2OD TC1OD TB2OD TB1OD TA2OD TA1OD IS IS IS IS IS IS IS IS IS IS w w w w w w w w w w Bits 31:10 Reserved, must be kept at reset value. Bit 9 TE2ODIS: Timer E Output 2 disable Refer to TA1ODIS description Bit 8 TE1ODIS: Timer E Output 1 disable Refer to TA1ODIS description Bit 7 TD2ODIS: Timer D Output 2 disable Refer to TA1ODIS description Bit 6 TD1ODIS: Timer D Output 1 disable Refer to TA1ODIS description Bit 5 TC2ODIS: Timer C Output 2 disable Refer to TA1ODIS description Bit 4 TC1ODIS: Timer C Output 1 disable Refer to TA1ODIS description Bit 3 TB2ODIS: Timer B Output 2 disable Refer to TA1ODIS description Bit 2 TB1ODIS: Timer B Output 1 disable Refer to TA1ODIS description Bit 1 TA2ODIS: Timer A Output 2 disable Refer to TA1ODIS description Bit 0 TA1ODIS: Timer A Output 1 (HRTIM_CHA1) disable Setting this bit disables the Timer A output 1. The output enters the idle state, either from the run state or from the fault state. Writing “0” has no effect. 1434/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.46 HRTIM Output Disable Status Register (HRTIM_ODSR) Address offset: 0x39Ch Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. TE2OD TE1OD TD2OD TD1OD TC2OD TC1OD TB2OD TB1OD TA2OD TA1OD S S S S S S S S S S r r r r r r r r r r Bits 31:10 Reserved, must be kept at reset value. Bit 9 TE2ODS: Timer E Output 2 disable status Refer to TA1ODS description Bit 8 TE1ODS: Timer E Output 1 disable status Refer to TA1ODS description Bit 7 TD2ODS: Timer D Output 2 disable status Refer to TA1ODS description Bit 6 TD1ODS: Timer D Output 1 disable status Refer to TA1ODS description Bit 5 TC2ODS: Timer C Output 2 disable status Refer to TA1ODS description Bit 4 TC1ODS: Timer C Output 1 disable status Refer to TA1ODS description Bit 3 TB2ODS: Timer B Output 2 disable status Refer to TA1ODS description Bit 2 TB1ODS: Timer B Output 1 disable status Refer to TA1ODS description Bit 1 TA2ODS: Timer A Output 2 disable status Refer to TA1ODS description Bit 0 TA1ODS: Timer A Output 1 disable status Reading the bit returns the output disable status. It is not significant when the output is active (Tx1OEN or Tx2OEN = 1). 0: output HRTIM_CHA1 disabled, in Idle state. 1: output HRTIM_CHA1 disabled, in Fault state. DocID029587 Rev 3 1435/3178 1466 High-Resolution Timer (HRTIM) 37.5.47 RM0433 HRTIM Burst Mode Control Register (HRTIM_BMCR) Address offset: 0x3A0h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BMSTAT Res. Res. Res. Res. Res. Res. Res. Res. Res. TEBM TDBM TCBM TBBM TABM MTBM rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. BMPR EN BMOM BME rw rw rc_w0 rw BMPRSC[3:0] rw rw rw BMCLK[3:0] rw rw rw rw rw Bit 31 BMSTAT: Burst Mode Status This bit gives the current operating state. 0: Normal operation 1: Burst operation on-going. Writing this bit to 0 causes a burst mode early termination. Bits 30:22 Reserved, must be kept at reset value. Bit 21 TEBM: Timer E Burst Mode Refer to TABM description Bit 20 TDBM: Timer D Burst Mode Refer to TABM description Bit 19 TCBM: Timer C Burst Mode Refer to TABM description Bit 18 TBBM: Timer B Burst Mode Refer to TABM description Bit 17 TABM: Timer A Burst Mode This bit defines how the timer behaves during a burst mode operation. This bitfield cannot be changed while the burst mode is enabled. 0: Timer A counter clock is maintained and the timer operates normally 1: Timer A counter clock is stopped and the counter is reset Note: This bit must not be set when the balanced idle mode is active (DLYPRT[2:0] = 0x11) Bit 16 MTBM: Master Timer Burst Mode This bit defines how the timer behaves during a burst mode operation. This bitfield cannot be changed while the burst mode is enabled. 0: Master Timer counter clock is maintained and the timer operates normally 1: Master Timer counter clock is stopped and the counter is reset Bits 15:11 Reserved, must be kept at reset value. Bit 10 BMPREN: Burst Mode Preload Enable This bit enables the registers preload mechanism and defines whether a write access into a preloadable register (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register. 0: Preload disabled: the write access is directly done into active registers 1: Preload enabled: the write access is done into preload registers 1436/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bits 9:6 BMPRSC[3:0]: Burst Mode Prescaler Defines the prescaling ratio of the fHRTIM clock for the burst mode controller. This bitfield cannot be changed while the burst mode is enabled. 0000: Clock not divided 0001: Division by 2 0010: Division by 4 0011: Division by 8 0100: Division by 16 0101: Division by 32 0110: Division by 64 0111: Division by 128 1000: Division by 256 1001: Division by 512 1010: Division by 1024 1011: Division by 2048 1100: Division by 4096 1101:Division by 8192 1110: Division by 16384 1111: Division by 32768 Bits 5:2 BMCLK[3:0]: Burst Mode Clock source This bitfield defines the clock source for the burst mode counter. It cannot be changed while the burst mode is enabled (refer to Table 301 for on-chip events 1..4 connections details). 0000: Master timer counter reset/roll-over 0001: Timer A counter reset/roll-over 0010: Timer B counter reset/roll-over 0011: Timer C counter reset/roll-over 0100: Timer D counter reset/roll-over 0101: Timer E counter reset/roll-over 0110: On-chip Event 1 (hrtim_bm_ck1), acting as a burst mode counter clock 0111: On-chip Event 2 (hrtim_bm_ck2) acting as a burst mode counter clock 1000: On-chip Event 3 (hrtim_bm_ck3) acting as a burst mode counter clock 1001: On-chip Event 4 (hrtim_bm_ck4) acting as a burst mode counter clock 1010: Prescaled fHRTIM clock (as per BMPRSC[3:0] setting) Other codes reserved Bit 1 BMOM: Burst Mode operating mode This bit defines if the burst mode is entered once or if it is continuously operating. 0: Single-shot mode 1: Continuous operation Bit 0 BME: Burst Mode enable This bit starts the burst mode controller which becomes ready to receive the start trigger. Writing this bit to 0 causes a burst mode early termination. 0: Burst mode disabled 1: Burst mode enabled DocID029587 Rev 3 1437/3178 1466 High-Resolution Timer (HRTIM) 37.5.48 RM0433 HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR) Address offset: 0x3A4h Reset value: 0x0000 0000 31 30 OCHP EV EEV8 29 EEV7 28 27 26 25 24 23 TDEEV TAEEV TECMP TECMP TEREP TERST 8 7 2 1 22 TDCM P2 21 20 19 TDCM TDREP TDRST P1 18 TCCM P2 17 16 TCCM TCREP P1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSTC MP4 MSTC MP3 MSTC MP2 rw rw rw TCRST rw TBCMP TBCMP TACMP TACMP TBREP TBRST TAREP TARST 2 1 2 1 rw rw rw rw rw rw rw rw MSTC MSTRE MSTRS MP1 P T rw rw rw SW rw Bit 31 OCHPEV: On-chip Event A rising edge on an on-chip Event (see Section : Burst mode triggers) triggers a burst mode entry. Bit 30 EEV8: External Event 8 (TIMD filters applied) The external event 8 conditioned by TIMD filters is starting the burst mode operation. Bit 29 EEV7: External Event 7 (TIMA filters applied) The external event 7 conditioned by TIMA filters is starting the burst mode operation. Bit 28 TDEEV8: Timer D period following External Event 8 The timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation. Bit 27 TAEEV7: Timer A period following External Event 7 The timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation. Bit 26 TECMP2: Timer E Compare 2 event Refer to TACMP1 description Bit 25 TECMP1: Timer E Compare 1 event Refer to TACMP1 description Bit 24 TEREP: Timer E repetition Refer to TAREP description Bit 23 TERST: Timer E counter reset or roll-over Refer to TARST description Bit 22 TDCMP2: Timer D Compare 2 event Refer to TACMP1 description Bit 21 TDCMP1: Timer D Compare 1 event Refer to TACMP1 description Bit 20 TDREP: Timer D repetition Refer to TAREP description Bit 19 TDRST: Timer D reset or roll-over Refer to TARST description Bit 18 TCCMP2: Timer C Compare 2 event Refer to TACMP1 description 1438/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) Bit 17 TCCMP1: Timer C Compare 1 event Refer to TACMP1 description Bit 16 TCREP: Timer C repetition Refer to TAREP description Bit 15 TCRST: Timer C reset or roll-over Refer to TARST description Bit 14 TBCMP2: Timer B Compare 2 event Refer to TACMP1 description Bit 13 TBCMP1: Timer B Compare 1 event Refer to TACMP1 description Bit 12 TBREP: Timer B repetition Refer to TAREP description Bit 11 TBRST: Timer B reset or roll-over Refer to TARST description Bit 10 TACMP2: Timer A Compare 2 event Refer to TACMP1 description Bit 9 TACMP1: Timer A Compare 1 event The timer A compare 1 event is starting the burst mode operation. Bit 8 TAREP: Timer A repetition The Timer A repetition event is starting the burst mode operation. Bit 7 TARST: Timer A reset or roll-over The Timer A reset or roll-over event is starting the burst mode operation. Bit 6 MSTCMP4: Master Compare 4 Refer to MSTCMP1 description Bit 5 MSTCMP3: Master Compare 3 Refer to MSTCMP1 description Bit 4 MSTCMP2: Master Compare 2 Refer to MSTCMP1 description Bit 3 MSTCMP1: Master Compare 1 The master timer Compare 1 event is starting the burst mode operation. Bit 2 MSTREP: Master repetition The master timer repetition event is starting the burst mode operation. Bit 1 MSTRST: Master reset or roll-over The master timer reset and roll-over event is starting the burst mode operation. Bit 0 SW: Software start This bit is set by software and automatically reset by hardware. When set, It starts the burst mode operation immediately. This bit is not active if the burst mode is not enabled (BME bit is reset). DocID029587 Rev 3 1439/3178 1466 High-Resolution Timer (HRTIM) 37.5.49 RM0433 HRTIM Burst Mode Compare Register (HRTIM_BMCMPR) Address offset: 0x3A8h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BMCMP[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 BMCMP[15:0]: Burst mode compare value Defines the number of periods during which the selected timers are in idle state. This register holds either the content of the preload register or the content of the active register if the preload is disabled. Note: BMCMP[15:0] cannot be set to 0x0000 when using the fHRTIM clock without a prescaler as the burst mode clock source (BMCLK[3:0] = 1010 and BMPRESC[3:0] = 0000). 37.5.50 HRTIM Burst Mode Period Register (HRTIM_BMPER) Address offset: 0x3ACh Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BMPER[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 BMPER[15:0]: Burst mode Period Defines the burst mode repetition period. This register holds either the content of the preload register or the content of the active register if preload is disabled. Note: The BMPER[15:0] must not be null when the burst mode is enabled. 1440/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.51 HRTIM Timer External Event Control Register 1 (HRTIM_EECR1) Address offset: 0x3B0h Reset value: 0x0000 0000 31 30 29 Res. Res. EE5FA ST rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EE3SN EE3PO S[0] L rw rw 28 EE5SNS[1:0] EE3SRC[1:0] rw 27 rw EE2FA ST rw 26 EE5PO L 25 EE5SRC[1:0] EE2SNS[1:0] rw 24 EE2PO L rw rw 23 EE4FA ST 22 EE4SNS[1:0] EE2SRC[1:0] rw 21 rw EE1FA ST rw 20 EE4PO L 19 EE4SRC[1:0] EE1SNS[1:0] rw 18 rw EE1PO L rw 17 16 EE3FA EE3SN ST S[1] EE1SRC[1:0] rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 EE5FAST: External Event 5 Fast mode Refer to EE1FAST description Bits 28:27 EE5SNS[1:0]: External Event 5 Sensitivity Refer to EE1SNS[1:0] description Bit 26 EE5POL: External Event 5 Polarity Refer to EE1POL description Bits 25:24 EE5SRC[1:0]: External Event 5 Source Refer to EE1SRC[1:0] description Bit 23 EE4FAST: External Event 4 Fast mode Refer to EE1FAST description Bits 22:21 EE4SNS[1:0]: External Event 4 Sensitivity Refer to EE1SNS[1:0] description Bit 20 EE4POL: External Event 4 Polarity Refer to EE1POL description Bits 19:18 EE4SRC[1:0]: External Event 4 Source Refer to EE1SRC[1:0] description Bit 17 EE3FAST: External Event 3 Fast mode Refer to EE1FAST description Bits 16:15 EE3SNS[1:0]: External Event 3 Sensitivity Refer to EE1SNS[1:0] description Bit 14 EE3POL: External Event 3 Polarity Refer to EE1POL description Bits 13:12 EE3SRC[1:0]: External Event 3 Source Refer to EE1SRC[1:0] description Bit 11 EE2FAST: External Event 2 Fast mode Refer to EE1FAST description Bits 10:9 EE2SNS[1:0]: External Event 2 Sensitivity Refer to EE1SNS[1:0] description Bit 8 EE2POL: External Event 2 Polarity Refer to EE1POL description DocID029587 Rev 3 1441/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bits 7:6 EE2SRC[1:0]: External Event 2 Source Refer to EE1SRC[1:0] description Bit 5 EE1FAST: External Event 1 Fast mode 0: External Event 1 is re-synchronized by the HRTIM logic before acting on outputs, which adds a fHRTIM clock-related latency 1: External Event 1 is acting asynchronously on outputs (low latency mode) Note: This bit must not be modified once the counter in which the event is used is enabled (TxCEN bit set) Bits 4:3 EE1SNS[1:0]: External Event 1 Sensitivity 00: On active level defined by EE1POL bit 01: Rising edge, whatever EE1POL bit value 10: Falling edge, whatever EE1POL bit value 11: Both edges, whatever EE1POL bit value Bit 2 EE1POL: External Event 1 Polarity This bit is only significant if EE1SNS[1:0] = 00. 0: External event is active high 1: External event is active low Note: This parameter cannot be changed once the timer x is enabled. It must be configured prior to setting EE1FAST bit. Bits 1:0 EE1SRC[1:0]: External Event 1 Source 00: hrtim_evt11 01: hrtim_evt12 10: hrtim_evt13 11: hrtim_evt14 Note: This parameter cannot be changed once the timer x is enabled. It must be configured prior to setting EE1FAST bit. 1442/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.52 HRTIM Timer External Event Control Register 2 (HRTIM_EECR2) Address offset: 0x3B4h Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 EE8SN EE8PO S[0] L rw rw 28 EE10SNS[1:0] 26 EE10P OL 25 24 EE10SRC[1:0] rw rw rw rw rw 12 11 10 9 8 EE8SRC[1:0] rw 27 rw Res. EE7SNS[1:0] rw EE7PO L rw rw 23 Res. 22 EE9SNS[1:0] 20 EE9PO L 19 18 EE9SRC[1:0] rw rw rw rw rw 6 5 4 3 2 7 EE7SRC[1:0] rw 21 rw Res. EE6SNS[1:0] rw rw EE6PO L rw 17 16 Res. EE8SN S[1] rw 1 0 EE6SRC[1:0] rw rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:27 EE10SNS[1:0]: External Event 10 Sensitivity Refer to EE1SNS[1:0] description Bit 26 EE10POL: External Event 10 Polarity Refer to EE1POL description Bits 25:24 EE10SRC[1:0]: External Event 10 Source Refer to EE1SRC[1:0] description Bit 23 Reserved, must be kept at reset value. Bits 22:21 EE9SNS[1:0]: External Event 9 Sensitivity Refer to EE1SNS[1:0] description Bit 20 EE9POL: External Event 9 Polarity Refer to EE1POL description Bits 19:18 EE9SRC[1:0]: External Event 9 Source Refer to EE1SRC[1:0] description Bit 17 Reserved, must be kept at reset value. Bits 16:15 EE8SNS[1:0]: External Event 8 Sensitivity Refer to EE1SNS[1:0] description Bit 14 EE8POL: External Event 8 Polarity Refer to EE1POL description Bits 13:12 EE8SRC[1:0]: External Event 8 Source Refer to EE1SRC[1:0] description Bit 11 Reserved, must be kept at reset value. Bits 10:9 EE7SNS[1:0]: External Event 7 Sensitivity Refer to EE1SNS[1:0] description Bit 8 EE7POL: External Event 7 Polarity Refer to EE1POL description Bits 7:6 EE7SRC[1:0]: External Event 7 Source Refer to EE1SRC[1:0] description Bit 5 Reserved, must be kept at reset value. DocID029587 Rev 3 1443/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bits 4:3 EE6SNS[1:0]: External Event 6 Sensitivity Refer to EE1SNS[1:0] description Bit 2 EE6POL: External Event 6 Polarity Refer to EE1POL description Bits 1:0 EE6SRC[1:0]: External Event 6 Source Refer to EE1SRC[1:0] description 37.5.53 HRTIM Timer External Event Control Register 3 (HRTIM_EECR3) Address offset: 0x3B8h Reset value: 0x0000 0000 31 30 EEVSD[1:0] rw rw 15 14 29 28 Res. Res. 13 12 EE8F[3:0] rw rw rw rw 27 26 25 24 EE10F[3:0] rw rw rw rw 11 10 9 8 Res. Res. 23 22 Res. Res. 7 6 EE7F[3:0] rw rw rw rw 21 20 19 18 EE9F[3:0] rw rw rw rw 5 4 3 2 Res. Res. 17 16 Res. Res. 1 0 EE6F[3:0] rw rw rw Bits 31:30 EEVSD[1:0]: External Event Sampling clock division This bitfield indicates the division ratio between the timer clock frequency (fHRTIM) and the External Event signal sampling clock (fEEVS) used by the digital filters. 00: fEEVS=fHRTIM 01: fEEVS=fHRTIM / 2 10: fEEVS=fHRTIM / 4 11: fEEVS=fHRTIM / 8 Bits 29:28 Reserved, must be kept at reset value. Bits 27:24 EE10F[3:0]: External Event 10 filter Refer to EE6F[3:0] description Bits 23:22 Reserved, must be kept at reset value. Bits 21:18 EE9F[3:0]: External Event 9 filter Refer to EE6F[3:0] description Bits 17:16 Reserved, must be kept at reset value. Bits 15:12 EE8F[3:0]: External Event 8 filter Refer to EE6F[3:0] description Bits 11:10 Reserved, must be kept at reset value. 1444/3178 DocID029587 Rev 3 rw RM0433 High-Resolution Timer (HRTIM) Bits 9:6 EE7F[3:0]: External Event 7 filter Refer to EE6F[3:0] description Bits 4:5 Reserved, must be kept at reset value. Bits 3:0 EE6F[3:0]: External Event 6 filter This bitfield defines the frequency used to sample External Event 6 input and the length of the digital filter applied to hrtim_evt6. The digital filter is made of a counter in which N valid samples are needed to validate a transition on the output. 0000: Filter disabled 0001: fSAMPLING= fHRTIM, N=2 0010: fSAMPLING= fHRTIM, N=4 0011: fSAMPLING= fHRTIM, N=8 0100: fSAMPLING= fEEVS/2, N=6 0101: fSAMPLING= fEEVS/2, N=8 0110: fSAMPLING= fEEVS/4, N=6 0111: fSAMPLING= fEEVS/4, N=8 1000: fSAMPLING= fEEVS/8, N=6 1001: fSAMPLING= fEEVS/8, N=8 1010: fSAMPLING= fEEVS/16, N=5 1011: fSAMPLING= fEEVS/16, N=6 1100: fSAMPLING= fEEVS/16, N=8 1101: fSAMPLING= fEEVS/32, N=5 1110: fSAMPLING= fEEVS/32, N=6 1111: fSAMPLING= fEEVS/32, N=8 37.5.54 HRTIM ADC Trigger 1 Register (HRTIM_ADC1R) Address offset: 0x3BCh Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AD1TE AD1TE AD1TE AD1TE AD1TD AD1TD AD1TD AD1TD AD1TC AD1TC AD1TC AD1TC AD1TB AD1TB AD1TB AD1TB PER C4 C3 PER C3 C2 PER C2 RST PER C2 C4 C4 C3 C4 C3 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD1TB AD1TA AD1TA AD1TA AD1TA AD1TA AD1EE AD1EE AD1EE AD1EE AD1EE AD1MP AD1MC AD1MC AD1MC AD1MC C2 RST PER C3 C2 V5 V4 V3 4 3 2 1 C4 V2 V1 ER rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 These bits select the trigger source for th ADC Trigger 1 output (hrtim_adc_trg1). Refer to HRTIM_ADC3R bits description for details DocID029587 Rev 3 1445/3178 1466 High-Resolution Timer (HRTIM) 37.5.55 RM0433 HRTIM ADC Trigger 2 Register (HRTIM_ADC2R) Address offset: 0x3C0h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AD2TE AD2TE AD2TE AD2TE AD2TD AD2TD AD2TD AD2TD AD2TD AD2TC AD2TC AD2TC AD2TC AD2TC AD2TB AD2TB RST C4 C3 RST PER C3 C2 RST PER C2 PER C2 C4 C4 C3 C4 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD2TB AD2TB AD2TA AD2TA AD2TA AD2TA AD2EE AD2EE AD2EE AD2EE AD2EE AD2MP AD2MC AD2MC AD2MC AD2MC C2 PER C3 C2 V10 V9 V8 4 3 2 1 C3 C4 V7 V6 ER rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 These bits select the trigger source for th ADC Trigger 2 output (hrtim_adc_trg2). Refer to HRTIM_ADC4R bits description for details 1446/3178 DocID029587 Rev 3 rw rw RM0433 High-Resolution Timer (HRTIM) 37.5.56 HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) Address offset: 0x3C4h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC3 ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T TEPER EC4 EC3 DPER DC3 DC2 CPER CC2 BRST BPER EC2 DC4 CC4 CC3 BC4 BC3 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC3T ADC3T ADC3T ADC3T ADC3T ADC3T ADC3E ADC3E ADC3E ADC3E ADC3E ADC3M ADC3M ADC3M ADC3M ADC3M BC2 ARST APER AC3 AC2 EV5 EV4 EV3 C4 C3 C2 C1 AC4 EV2 EV1 PER rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 ADC3TEPER: ADC trigger 3 on Timer E Period Refer to ADC3TAPER description Bit 30 ADC3TEC4: ADC trigger 3 on Timer E Compare 4 Refer to ADC3TAC2 description Bit 29 ADC3TEC3: ADC trigger 3 on Timer E Compare 3 Refer to ADC3TAC2 description Bit 28 ADC3TEC2: ADC trigger 3 on Timer E Compare 2 Refer to ADC3TAC2 description Bit 27 ADC3TDPER: ADC trigger 3 on Timer D Period Refer to ADC3TAPER description Bit 26 ADC3TDC4: ADC trigger 3 on Timer D Compare 4 Refer to ADC3TAC2 description Bit 25 ADC3TDC3: ADC trigger 3 on Timer D Compare 3 Refer to ADC3TAC2 description Bit 24 ADC3TDC2: ADC trigger 3 on Timer D Compare 2 Refer to ADC3TAC2 description Bit 23 ADC3TCPER: ADC trigger 3 on Timer C Period Refer to ADC3TAPER description Bit 22 ADC3TCC4: ADC trigger 3 on Timer C Compare 4 Refer to ADC3TAC2 description Bit 21 ADC3TCC3: ADC trigger 3 on Timer C Compare 3 Refer to ADC3TAC2 description Bit 20 ADC3TCC2: ADC trigger 3 on Timer C Compare 2 Refer to ADC3TAC2 description Bit 19 ADC3TBRST: ADC trigger 3 on Timer B Reset and counter roll-over Refer to ADC3TBRST description Bit 18 ADC3TBPER: ADC trigger 3 on Timer B Period Refer to ADC3TAPER description Bit 17 ADC3TBC4: ADC trigger 3 on Timer B Compare 4 Refer to ADC3TAC2 description DocID029587 Rev 3 1447/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 16 ADC3TBC3: ADC trigger 3 on Timer B Compare 3 Refer to ADC3TAC2 description Bit 15 ADC3TBC2: ADC trigger 3 on Timer B Compare 2 Refer to ADC3TAC2 description Bit 14 ADC3TARST: ADC trigger 3 on Timer A Reset and counter roll-over This bit enables the generation of an ADC Trigger upon Timer A reset and roll-over event, on ADC Trigger 1 output. Bit 13 ADC3TAPER: ADC trigger 3 on Timer A Period This bit enables the generation of an ADC Trigger upon Timer A period event, on ADC Trigger 3 output (hrtim_adc_trg3). Bit 12 ADC3TAC4: ADC trigger 3 on Timer A Compare 4 Refer to ADC3TAC2 description Bit 11 ADC3TAC3: ADC trigger 3 on Timer A Compare 3 Refer to ADC3TAC2 description Bit 10 ADC3TAC2: ADC trigger 3 on Timer A Compare 2 This bit enables the generation of an ADC Trigger upon Timer A Compare 2 event, on ADC Trigger 3 output (hrtim_adc_trg3). Bit 9 ADC3EEV5: ADC trigger 3 on External Event 5 Refer to ADC3EEV1 description Bit 8 ADC3EEV4: ADC trigger 3 on External Event 4 Refer to ADC3EEV1 description Bit 7 ADC3EEV3: ADC trigger 3 on External Event 3 Refer to ADC3EEV1 description Bit 6 ADC3EEV2: ADC trigger 3 on External Event 2 Refer to ADC3EEV1 description Bit 5 ADC3EEV1: ADC trigger 3 on External Event 1 This bit enables the generation of an ADC Trigger upon External event 1, on ADC Trigger 3 output (hrtim_adc_trg3). Bit 4 ADC3MPER: ADC trigger 3 on Master Period This bit enables the generation of an ADC Trigger upon Master timer period event, on ADC Trigger 3 output (hrtim_adc_trg3). Bit 3 ADC3MC4: ADC trigger 3 on Master Compare 4 Refer to ADC3MC1 description Bit 2 ADC3MC3: ADC trigger 3 on Master Compare 3 Refer to ADC3MC1 description Bit 1 ADC3MC2: ADC trigger 3 on Master Compare 2 Refer to ADC3MC1 description Bit 0 ADC3MC1: ADC trigger 3 on Master Compare 1 This bit enables the generation of an ADC Trigger upon Master Compare 1 event, on ADC Trigger 3 output (hrtim_adc_trg3). 1448/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.57 HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) Address offset: 0x3C8h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ERST EC4 EC3 DRST DPER DC3 DC2 CRST CPER CC2 BPER EC2 DC4 CC4 CC3 BC4 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC4T ADC4T ADC4T ADC4T ADC4T ADC4T ADC4E ADC4E ADC4E ADC4E ADC4E ADC4M ADC4M ADC4M ADC4M ADC4M BC2 APER AC3 AC2 EV10 EV9 EV8 C4 C3 C2 C1 BC3 AC4 EV7 EV6 PER rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 ADC4TERST: ADC trigger 4 on Timer E Reset and counter roll-over (1) Refer to ADC4TCRST description Bit 30 ADC4TEC4: ADC trigger 4 on Timer E Compare 4 Refer to ADC4TAC2 description Bit 29 ADC4TEC3: ADC trigger 4 on Timer E Compare 3 Refer to ADC4TAC2 description Bit 28 ADC4TEC2: ADC trigger 4 on Timer E Compare 2 Refer to ADC4TAC2 description Bit 27 ADC4TDRST: ADC trigger 4 on Timer D Reset and counter roll-over (1) Refer to ADC4TCRST description Bit 26 ADC4TDPER: ADC trigger 4 on Timer D Period Refer to ADC4TAPER description Bit 25 ADC4TDC4: ADC trigger 4 on Timer D Compare 4 Refer to ADC4TAC2 description Bit 24 ADC4TDC3: ADC trigger 4 on Timer D Compare 3 Refer to ADC4TAC2 description Bit 23 ADC4TDC2: ADC trigger 2 on Timer D Compare 2 Refer to ADC4TAC2 description Bit 22 ADC4TCRST: ADC trigger 4 on Timer C Reset and counter roll-over (1) This bit enables the generation of an ADC Trigger upon Timer C reset and roll-over event, on ADC Trigger 4 output (hrtim_adc_trg4). Bit 21 ADC4TCPER: ADC trigger 4 on Timer C Period Refer to ADC4TAPER description Bit 20 ADC4TCC4: ADC trigger 4 on Timer C Compare 4 Refer to ADC4TAC2 description Bit 19 ADC4TCC3: ADC trigger 4 on Timer C Compare 3 Refer to ADC4TAC2 description Bit 18 ADC4TCC2: ADC trigger 4 on Timer C Compare 2 Refer to ADC4TAC2 description DocID029587 Rev 3 1449/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 17 ADC4TBPER: ADC trigger 4 on Timer B Period Refer to ADC4TAPER description Bit 16 ADC4TBC4: ADC trigger 4 on Timer B Compare 4 Refer to ADC4TAC2 description Bit 15 ADC4TBC3: ADC trigger 4 on Timer B Compare 3 Refer to ADC4TAC2 description Bit 14 ADC4TBC2: ADC trigger 4 on Timer B Compare 2 Refer to ADC4TAC2 description Bit 13 ADC4TAPER: ADC trigger 4 on Timer A Period This bit enables the generation of an ADC Trigger upon Timer A event, on ADC Trigger 4 output (hrtim_adc_trg4). Bit 12 ADC4TAC4: ADC trigger 4 on Timer A Compare 4 Refer to ADC4TAC2 description Bit 11 ADC4TAC3: ADC trigger 4 on Timer A Compare 3 Refer to ADC4TAC2 description Bit 10 ADC4TAC2: ADC trigger 4 on Timer A Compare 2 This bit enables the generation of an ADC Trigger upon Timer A Compare 2, on ADC Trigger 4 output (hrtim_adc_trg4). Bit 9 ADC4EEV10: ADC trigger 4 on External Event 10 (1) Refer to ADC4EEV6 description Bit 8 ADC4EEV9: ADC trigger 4 on External Event 9 (1) Refer to ADC4EEV6 description Bit 7 ADC4EEV8: ADC trigger 4 on External Event 8 (1) Refer to ADC4EEV6 description Bit 6 ADC4EEV7: ADC trigger 4 on External Event 7 (1) Refer to ADC4EEV6 description Bit 5 ADC4EEV6: ADC trigger 4 on External Event 6 (1) This bit enables the generation of an ADC Trigger upon external event 6, on ADC Trigger 4 output (hrtim_adc_trg4). Bit 4 ADC4MPER: ADC trigger 4 on Master Period This bit enables the generation of an ADC Trigger upon Master period event, on ADC Trigger 4 output (hrtim_adc_trg4). Bit 3 ADC4MC4: ADC trigger 4 on Master Compare 4 Refer to ADC4MC1 description Bit 2 ADC4MC3: ADC trigger 4 on Master Compare 3 Refer to ADC4MC1 description Bit 1 ADC4MC2: ADC trigger 4 on Master Compare 2 Refer to ADC4MC1 description Bit 0 ADC4MC1: ADC trigger 4 on Master Compare 1 This bit enables the generation of an ADC Trigger upon Master Compare 1 event, on ADC Trigger 4 output (hrtim_adc_trg4). 1. These triggers are differing from HRTIM_ADC1R/HRTIM_ADC3R to HRTIM_ADC2R/HRTIM_ADC4R. 1450/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.58 HRTIM Fault Input Register 1 (HRTIM_FLTINR1) Address offset: 0x3D0h Reset value: 0x0000 0000 31 30 FLT4L CK 29 28 27 FLT4F[3:0] 26 25 24 23 FLT4S RC FLT4P FLT4E FLT3L CK 22 21 20 19 FLT3F[3:0] 18 17 16 FLT3S RC FLT3P FLT3E rwo rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLT2S RC FLT2P FLT2E FLT1L CK FLT1S RC FLT1P FLT1E rw rw rw rw rw rw rw FLT2L CK rwo FLT2F[3:0] rw rw rw rw FLT1F[3:0] rw rw rw rw Bit 31 FLT4LCK: Fault 4 Lock Refer to FLT5LCK description in HRTIM_FLTINR2 register Bits 30:27 FLT4F[3:0]: Fault 4 filter Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register Bit 26 FLT4SRC: Fault 4 source Refer to FLT5SRC description in HRTIM_FLTINR2 register Bit 25 FLT4P: Fault 4 polarity Refer to FLT5P description in HRTIM_FLTINR2 register Bit 24 FLT4E: Fault 4 enable Refer to FLT5E description in HRTIM_FLTINR2 register Bit 23 FLT3LCK: Fault 3 Lock Refer to FLT5LCK description in HRTIM_FLTINR2 register Bits 22:19 FLT3F[3:0]: Fault 3 filter Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register Bit 18 FLT3SRC: Fault 3 source Refer to FLT5SRC description in HRTIM_FLTINR2 register Bit 17 FLT3P: Fault 3 polarity Refer to FLT5P description in HRTIM_FLTINR2 register Bit 16 FLT3E: Fault 3 enable Refer to FLT5E description in HRTIM_FLTINR2 register Bit 15 FLT2LCK: Fault 2 Lock Refer to FLT5LCK description in HRTIM_FLTINR2 register Bits 14:11 FLT2F[3:0]: Fault 2 filter Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register Bit 10 FLT2SRC: Fault 2 source Refer to FLT5SRC description in HRTIM_FLTINR2 register Bit 9 FLT2P: Fault 2 polarity Refer to FLT2P description in HRTIM_FLTINR2 register Bit 8 FLT2E: Fault 2 enable Refer to FLT5E description in HRTIM_FLTINR2 register DocID029587 Rev 3 1451/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bit 7 FLT1LCK: Fault 1 Lock Refer to FLT5LCK description in HRTIM_FLTINR2 register Bits 6:3 FLT1F[3:0]: Fault 1 filter Refer to FLT5F[3:0] description in HRTIM_FLTINR2 register Bit 2 FLT1SRC: Fault 1 source Refer to FLT5SRC description in HRTIM_FLTINR2 register Bit 1 FLT1P: Fault 1 polarity Refer to FLT5P description in HRTIM_FLTINR2 register Bit 0 FLT1E: Fault 1 enable Refer to FLT5E description in HRTIM_FLTINR2 register 1452/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.59 HRTIM Fault Input Register 2 (HRTIM_FLTINR2) Address offset: 0x3D4h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. FLT5L CK FLT5S RC FLT5P FLT5E rw rw rw FLTSD[1:0] rwo FLT5F[3:0] rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:24 FLTSD[1:0]: Fault Sampling clock division This bitfield indicates the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters. 00: fFLTS=fHRTIM 01: fFLTS=fHRTIM / 2 10: fFLTS=fHRTIM / 4 11: fFLTS=fHRTIM / 8 Note: This bitfield must be written prior to any of the FLTxE enable bits. Bits 23:8 Reserved, must be kept at reset value. Bit 7 FLT5LCK: Fault 5 Lock The FLT5LCK bit modifies the write attributes of the fault programming bit, so that they can be protected against spurious write accesses. This bit is write-once. Once it has been set, it cannot be modified till the next system reset. 0: FLT5E, FLT5P, FLT5SRC, FLT5F[3:0] bits are read/write. 1: FLT5E, FLT5P, FLT5SRC, FLT5F[3:0] bits can no longer be written (read-only mode) DocID029587 Rev 3 1453/3178 1466 High-Resolution Timer (HRTIM) RM0433 Bits 6:3 FLT5F[3:0]: Fault 5 filter This bitfield defines the frequency used to sample FLT5 input and the length of the digital filter applied to FLT5. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, FLT5 acts asynchronously 0001: fSAMPLING = fHRTIM, N = 2 0010: fSAMPLING = fHRTIM, N = 4 0011: fSAMPLING = fHRTIM, N = 8 0100: fSAMPLING = fFLTS/2, N = 6 0101: fSAMPLING = fFLTS/2, N = 8 0110: fSAMPLING = fFLTS/4, N = 6 0111: fSAMPLING = fFLTS/4, N = 8 1000: fSAMPLING = fFLTS/8, N = 6 1001: fSAMPLING = fFLTS/8, N = 8 1010: fSAMPLING = fFLTS/16, N = 5 1011: fSAMPLING = fFLTS/16, N = 6 1100: fSAMPLING = fFLTS/16, N = 8 1101: fSAMPLING = fFLTS/32, N = 5 1110: fSAMPLING = fFLTS/32, N = 6 1111: fSAMPLING = fFLTS/32, N = 8 Note: This bitfield can be written only when FLT5E enable bit is reset. This bitfield cannot be modified when FLT5LOCK has been programmed. Bit 2 FLT5SRC: Fault 5 source This bit selects the FAULT5 input source (refer to Table 302 for connection details). 0: Fault 1 input is HRTIM_FLT5 input pin 1: Fault 1 input is hrtim_in_flt5 signal Note: This bitfield can be written only when FLT5E enable bit is reset Bit 1 FLT5P: Fault 5 polarity This bit selects the FAULT5 input polarity. 0: Fault 5 input is active low 1: Fault 5 input is active high Note: This bitfield can be written only when FLT5E enable bit is reset Bit 0 FLT5E: Fault 5 enable This bit enables the global FAULT5 input circuitry. 0: Fault 5 input disabled 1: Fault 5 input enabled 1454/3178 DocID029587 Rev 3 RM0433 High-Resolution Timer (HRTIM) 37.5.60 HRTIM Burst DMA Master timer update Register (HRTIM_BDMUPR) Address offset: 0x3D8h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. MPER MCNT MDIER MICR MCR rw rw rw rw rw MCMP4 MCMP3 MCMP2 MCMP1 MREP rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 MCMP4: MCMP4R register update enable Refer to MCR description Bit 8 MCMP3: MCMP3R register update enable Refer to MCR description Bit 7 MCMP2: MCMP2R register update enable Refer to MCR description Bit 6 MCMP1: MCMP1R register update enable Refer to MCR description Bit 5 MREP: MREP register update enable Refer to MCR description Bit 4 MPER: MPER register update enable Refer to MCR description Bit 3 MCNT: MCNTR register update enable Refer to MCR description Bit 2 MDIER: MDIER register update enable Refer to MCR description Bit 1 MICR: MICR register update enable Refer to MCR description Bit 0 MCR: MCR register update enable This bit defines if the master timer MCR register is part of the list of registers to be updated by the Burst DMA. 0: MCR register is not updated by Burst DMA accesses 1: MCR register is updated by Burst DMA accesses DocID029587 Rev 3 1455/3178 1466 High-Resolution Timer (HRTIM) 37.5.61 RM0433 HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR) Address offset: 0x3DCh-0x3ECh Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20 19 TIMxFL TIMxO UTR TR 2 1 0 10 9 8 7 6 5 4 3 TIMxE EFR1 TIMxR ST2R TIMxS ET2R TIMxR ST1R TIMxS ET1R TIMxD TxR TIMxC MP4 TIMxC MP3 TIMxC MP2 TIMxC MP1 TIMxR EP TIMxP ER TIMxC NT rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 16 TIMxEEFR2: HRTIM_EEFxR2 register update enable Refer to TIMxCR description Bit 15 TIMxEEFR1: HRTIM_EEFxR1 register update enable Refer to TIMxCR description Bit 14 TIMxRST2R: HRTIM_RST2xR register update enable Refer to TIMxCR description Bit 13 TIMxSET2R: HRTIM_SET2xR register update enable Refer to TIMxCR description Bit 12 TIMxRST1R: HRTIM_RST1xR register update enable Refer to TIMxCR description Bit 11 TIMxSET1R: HRTIM_SET1xR register update enable Refer to TIMxCR description Bit 10 TIMxDTR: HRTIM_DTxR register update enable Refer to TIMxCR description Bit 9 TIMxCMP4: HRTIM_CMP4xR register update enable Refer to TIMxCR description Bit 8 TIMxCMP3: HRTIM_CMP3xR register update enable Refer to TIMxCR description Bit 7 TIMxCMP2: HRTIM_CMP2xR register update enable Refer to TIMxCR description 1456/3178 DocID029587 Rev 3 TIMxE EFR2 rw 11 Bit 17 TIMxRSTR: HRTIM_RSTxR register update enable Refer to TIMxCR description TIMxR STR rw 12 Bit 18 TIMxCHPR: HRTIM_CHPxR register update enable Refer to TIMxCR description TIMxC HPR rw 13 Bit 19 TIMxOUTR: HRTIM_OUTxR register update enable Refer to TIMxCR description 16 rw 14 Bit 20 TIMxFLTR: HRTIM_FLTxR register update enable Refer to TIMxCR description 17 rw 15 Bits 31:21 Reserved, must be kept at reset value. 18 TIMxDI TIMxIC ER R rw rw TIMxC R rw RM0433 High-Resolution Timer (HRTIM) Bit 6 TIMxCMP1: HRTIM_CMP1xR register update enable Refer to TIMxCR description Bit 5 TIMxREP: HRTIM_REPxR register update enable Refer to TIMxCR description Bit 4 TIMxPER: HRTIM_PERxR register update enable Refer to TIMxCR description Bit 3 TIMxCNT: HRTIM_CNTxR register update enable Refer to TIMxCR description Bit 2 TIMxDIER: HRTIM_TIMxDIER register update enable Refer to TIMxCR description Bit 1 TIMxICR: HRTIM_TIMxICR register update enable Refer to TIMxCR description Bit 0 TIMxCR: HRTIM_TIMxCR register update enable This bit defines if the master timer MCR register is part of the list of registers to be updated by the Burst DMA. 0: HRTIM_TIMxCR register is not updated by Burst DMA accesses 1: HRTIM_TIMxCR register is updated by Burst DMA accesses 37.5.62 HRTIM Burst DMA Data Register (HRTIM_BDMADR) Address offset: 0x3F0h Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMADR[31:16] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wo wo wo wo wo wo wo BDMADR[15:0] wo wo wo wo wo wo wo wo wo Bits 31:0 BDMADR[31:0]: Burst DMA Data register Write accesses to this register triggers: – the copy of the data value into the registers enabled in BDTxUPR and BDMUPR register bits – the increment of the register pointer to the next location to be filled DocID029587 Rev 3 1457/3178 1466 High-Resolution Timer (HRTIM) 37.5.63 RM0433 HRTIM register map The tables below summarize the HRTIM registers mapping. The address offsets in Table 308 and Table 309 are referred to in the base address offsets given in Table 307. Table 307. RTIM global register map Base address offset Register 0x000 - 0x07F Master timer 0x080 - 0x0FF Timer A 0x100 - 0x17F Timer B 0x180 - 0x1FF Timer C 0x200 - 0x27F Timer D 0x280 - 0x2FF Timer E 0x300 - 0x37F Reserved 0x380 - 0x3FF Common registers 1458/3178 CKPSC[2:0] MCMP2 MCMP1 0 0 0 MCMP1C Res. Res. Res. Res. 0 MCMP2C Res. Res. Res. Res. 0 0 0 0 0 0 0 0 MCMP1IE Res. Res. Res. Res. Res. Res. Res. Res. 0 MCMP2IE Res. Res. CONT Res. Res. Res. Res. Res. Res. MCMP3 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCNT[15:0] 0 DocID029587 Rev 3 0 MCMP3C Res. Res. Reset value Res. 0 Res. 0 0 MCMP3IE Res. MCMP1DE 0 Res. MCMP2DE 0 RETRIG Res. MCMP3DE 0 Res. MREPDE MCMP4DE 0 0 MREP Res. Res. SYNCDE 0 0 MCMP4 Res. Res. MUPDDE Res. Res. Res. Res. Res. Res. Res. HRTIM_MCNT R Res. 0x0010 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. HRTIM_ MDIER(1) 0x000C Res. Reset value 0 MREPC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HRTIM_MICR Res. 0x0008 Res. Reset value 0 MCMP4C 0 MREPIE 0 MCMP4IE 0 Res. 0 HALF 0 SYNC 0 SYNCC SYNCRSTM 0 SYNCIE SYNCSTRTM 0 MUPD MCEN 0 MUPDC TACEN 0 MUPDIE TBCEN 0 SYNCIN[1:0] TCCEN 0 Res. SYNCOUT[1:0] SYNCSRC[1:0] TDCEN 0 Res. Res. TECEN Res. 0 Res. Res. Res. Res. 0 Res. DACSYNC[1:0] Res. PREEN 0 Res. HRTIM_MISR 0 Res. 0 Res. 0 Res. MREPU 0 Res. Reset value Res. 0x0004 HRTIM_MCR Res. 0x0000 BRSTDMA[1:0] Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 308. HRTIM Register map and reset values: Master timer 0 0 0 0 0 0 0 0 0 0x002C HRTIM_ MCMP4R(1) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HRTIM_ MCMP3R(1) Res. 0x0028 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset value 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 MCMP2[15:0] 0 MCMP3[15:0] 0 MCMP4[15:0] 0 Res. 1 Res. 1 Res. 1 Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. Reset value Res. HRTIM_ MCMP2R(1) Res. 0x0024 Reserved Res. 0x0020 HRTIM_ MCMP1R(1) Res. 0x001C HRTIM_MREP( 1) Res. 0x0018 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1) Res. HRTIM_MPER( Res. 0x0014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. RM0433 High-Resolution Timer (HRTIM) Table 308. HRTIM Register map and reset values: Master timer (continued) MPER[15:0] 0 1 1 1 1 1 MREP[7:0] 0 0 0 0 0 0 MCMP1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. This register can be preloaded (see Table 293 on page 1336). 1459/3178 1466 0x0030 HRTIM_CPT1xR 1460/3178 Res. 0 0 0 Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value Reset value Reset value DocID029587 Rev 3 1 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Reset value Res. Reset value 0 0 0 0 0 0 0 SET1xC CPT2C CPT1C UPDC REPC CMP4C CMP3C CMP2C CMP1C 0 0 0 0 0 0 0 0 0 0 0 0 0 SETx2IE RSTx1IE SET1xIE CPT2IE CPT1IE UPDIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REPx[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP1IE 1 CMP2IE PERx[15:0] CMP3IE 0 CMP4IE CNTx[15:0] REPIE CMP3 CMP2 CMP1 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. 0 0 0 0 0 0 CKPSCx[2:0] CONT CMP4 0 HALF REP 0 RETRIG UPD 0 0 Res. CPT1 0 PSHPLL CPT2 SYNCRSTx SETx1 SYNCSTRTx SETx2 RSTx1 DELCMP2[1:0] 0 RST 0 RSTx2 0 Res. SET2xC RSTx1C 0 RSTIE 0 Res. RSTC RSTx2C 0 RSTx2IE 0 DLYPRT DELCMP4[1:0] Res. TxRSTU TxREPU Res. DACSYNC[1:0] PREEN 0 Res. CPPSTAT Res. DLYPRTC Reset value DLYPRTIE CMP1DE 0 Res. O1STAT IPPSTAT Res. Res. Res. 0 Res. Res. 0 Res. CMP2DE 0 Res. Res. 0 Res. CMP3DE 0 Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. TBU Res. O2STAT Res. 0 Res. HRTIM_ TIMxISR Res. CMP4DE 0 Res. TCU 0 O1CPY 0 O2CPY 0 Res. 0 Res. TEU TDU 0 Res. REPDE 0 Res. Res. MSTU 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. UPDDE Res. Res. 0 Res. Res. Res. CPT1DE Res. Res. 0 Res. 0 Res. Res. Res. CPT2DE Res. Res. Res. 0 Res. Res. SET1xDE 0 Res. RSTx1DE 0 Res. 0 Res. 0 Res. SETx2DE 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. RSTDE RSTx2DE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. DLYPRTDE 0 Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. 0x002C HRTIM_ CMP4xR(1) Res. Reset value UPDGAT [3:0] Res. 0x0028 HRTIM_ CMP3xR(1) Res. 0x0024 HRTIM_ CMP2xR(1) Res. HRTIM_ CMP1CxR(1) Res. 0x001C HRTIM_ CMP1xR(1) Res. 0x0018 HRTIM_ REPxR(1) Res. 0x0014 HRTIM_ PERxR(1) Res. HRTIM_CNTxR Res. Reset value Res. 0x0020 HRTIM_ TIMxDIER(1) Res. 0x0010 HRTIM_ TIMxICR Res. 0x0008 Res. 0x0004 Res. 0x000C HRTIM_TIMxCR Res. 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. ) Res. High-Resolution Timer (HRTIM) RM0433 Table 309. HRTIM Register map and reset values: TIMx (x= A..E) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 REPx[7:0] CMP1x[15:0] CMP1x[15:0] CMP2x[15:0] CMP3x[15:0] CMP4x[15:0] CPT1x[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0054 HRTIM_ RSTAR(1) TIMDCMP1 TIMCCMP4 TIMCCMP2 TIMCCMP1 TIMBCMP4 TIMBCMP2 TIMBCMP1 EXTEVNT10 EXTEVNT9 EXTEVNT8 EXTEVNT7 EXTEVNT6 EXTEVNT5 EXTEVNT4 EXTEVNT3 EXTEVNT2 EXTEVNT1 MSTCMP4 MSTCMP3 MSTCMP2 MSTCMP1 MSTPER CMP4 CMP2 UPDT Reset value 0 Reset value 0 EE10FLTR[3 :0] 0 0 0 0 0 0 0 0 EXTEVNT6 EXTEVNT5 EXTEVNT4 EXTEVNT3 EXTEVNT2 EXTEVNT1 TIMEVNT9 TIMEVNT8 TIMEVNT7 TIMEVNT6 TIMEVNT5 TIMEVNT4 TIMEVNT3 TIMEVNT2 TIMEVNT1 MSTCMP4 MSTCMP3 MSTCMP2 MSTCMP1 MSTPER CMP4 CMP3 CMP2 CMP1 PER RESYNC SRT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ SETx2R(1) UPDATE EXTEVNT9 EXTEVNT8 EXTEVNT7 EXTEVNT6 EXTEVNT5 EXTEVNT4 EXTEVNT3 EXTEVNT2 EXTEVNT1 TIMEVNT9 TIMEVNT8 TIMEVNT7 TIMEVNT6 TIMEVNT5 TIMEVNT4 TIMEVNT3 TIMEVNT2 TIMEVNT1 MSTCMP4 MSTCMP3 MSTCMP2 MSTCMP1 MSTPER CMP4 CMP3 CMP2 CMP1 PER RESYNC SST Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ RSTx2R(1) EXTEVNT9 EXTEVNT8 EXTEVNT7 Reset value 0 0 0 0 0 0 0 0 0 EE5FLTR[3: 0] TIMEVNT8 TIMEVNT7 TIMEVNT6 TIMEVNT5 TIMEVNT4 0 0 0 0 0 0 EE4FLTR[3: 0] 0 EE9FLTR[3: 0] 0 0 0 0 0 0 0 EE4LTCH TIMEVNT2 TIMEVNT1 MSTCMP4 MSTCMP3 MSTCMP2 0 0 0 0 0 0 EE3FLTR[3: 0] EE3LTCH 0 0 0 EE8FLTR[3: 0] DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 EE7FLTR[3: 0] 0 0 0 0 0 0 SST 0 0 0 0 0 0 0 0 0 0 0 0 0 EE2FLTR[3: 0] SRT 0 PER 0 0 0 0 EE1FLTR[3: 0] EE1LTCH 0 RESYNC 0 RESYNC 0 CMP1 SDTRx DTPRSC[2:0] Res. 0 PER 0 CMP2 0 CMP1 0 0 CMP3 TIMEVNT3 0 CMP2 TIMEVNT4 0 0 CMP4 TIMEVNT5 0 CMP3 TIMEVNT6 0 0 Res. TIMEVNT7 0 0 MSTPER TIMEVNT8 0 CMP4 TIMEVNT9 0 MSTPER EXTEVNT1 0 EE2LTCH EXTEVNT2 0 0 MSTCMP1 EXTEVNT3 0 0 MSTCMP2 EXTEVNT4 0 0 MSTCMP1 0 MSTCMP3 0 MSTCMP4 0 TIMEVNT1 DTRSLKx 0 TIMEVNT2 DTRLKx 0 Res. TIMEVNT3 Res. TIMEVNT9 Res. 0 SDTFx 0 EXTEVNT5 Res. 0 EXTEVNT6 Res. Res. 0 0 0 0 0 EE6FLTR[3: 0] EE6LTCH EXTEVNT7 0 0 0 Res. EXTEVNT8 0 0 0 EE7LTCH EXTEVNT9 0 0 DTFx[8:0] 0 Res. UPDATE EXTEVNT10 Reset value 0 EE8LTCH HRTIM_ RSTx1R(1) EXTEVNT1 0 EXTEVNT2 0 EXTEVNT3 EXTEVNT7 0 EXTEVNT4 EXTEVNT8 0 EE5LTCH EXTEVNT9 0 EXTEVNT5 UPDATE EXTEVNT10 Reset value Res. HRTIM_ SETx1R(1) EXTEVNT6 Res. 0 0 Res. 0 EE9LTCH Res. 0 EE10LTCH Res. DTFLKx DTFSLKx 0 EXTEVNT10 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. TIMDCMP2 Reset value TIMDCMP4 HRTIM_EEFxR2 TIMECMP1 0x0050 HRTIM_EEFxR1 TIMECMP2 0x004C Reset value UPDATE 0x0048 HRTIM_DTxR(1) EXTEVNT10 0x0044 Res. 0x0040 Res. 0x003C Res. 0x0038 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HRTIM_CPT2xR Res. 0x0034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset TIMECMP4 RM0433 High-Resolution Timer (HRTIM) Table 309. HRTIM Register map and reset values: TIMx (x= A..E) (continued) CPT2x[15:0] 0 0 0 0 0 0 DTRx[8:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1461/3178 1466 1462/3178 EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT EXEV3CPT DocID029587 Rev 3 EXEV2CPT EXEV1CPT UPDCPT SWCPT EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT 0 EXEV4CPT Res. 0 EXEV4CPT Res. 0 EXEV4CPT Res. 0 EXEV5CPT Res. Reset value EXEV5CPT HRTIM_ CPT1DCR EXEV5CPT Res. 0 EXEV6CPT Res. 0 EXEV6CPT Res. 0 EXEV6CPT Res. 0 EXEV7CPT TD1SET 0 EXEV7CPT TD1RST 0 EXEV7CPT TDCMP1 0 EXEV8CPT TDCMP2 0 EXEV8CPT TE1SET Reset value EXEV8CPT Res. HRTIM_ CPT1CCR EXEV9CPT Res. 0 EXEV9CPT Res. 0 EXEV9CPT Res. 0 EXEV10CPT TC1SET 0 EXEV10CPT TC1RST 0 EXEV10CPT TCCMP1 0 TA1SET TCCMP2 0 TA1SET TD1SET 0 TA1SET TD1RST 0 TA1RST TDCMP1 0 TA1RST TDCMP2 0 TA1RST TE1SET 0 TACMP1 TE1RST Reset value TACMP1 HRTIM_ CPT1BCR TACMP1 0 EXEV10CPT EXEV9CPT EXEV8CPT EXEV7CPT EXEV6CPT EXEV5CPT EXEV4CPT EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT Res. Res. Res. Res. TB1SET 0 TACMP2 TB1RST 0 TACMP2 TBCMP1 0 TACMP2 TBCMP2 0 TB1SET TC1SET 0 TB1RST TC1RST 0 TB1SET TCCMP1 0 TB1RST TCCMP2 0 TBCMP1 TD1SET 0 TBCMP1 TD1RST 0 TBCMP2 TDCMP1 0 TBCMP2 TDCMP2 0 TE1RST HRTIM_CHPxR TC1SET TE1SET 0 TE1SET Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UPDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ RSTCR(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ RSTDR(1) 0 HRTIM_ RSTER(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value STRTPW [3:0] CARDTY [2:0] Res. 0 Res. CMP2 UPDT UPDT 0 UPDT CMP4 CMP2 CMP2 0 CMP2 MSTPER CMP4 CMP4 0 CMP4 MSTCMP1 MSTPER MSTPER 0 MSTPER MSTCMP2 MSTCMP1 MSTCMP1 0 MSTCMP1 MSTCMP3 MSTCMP2 MSTCMP2 0 MSTCMP2 MSTCMP4 MSTCMP3 MSTCMP3 0 MSTCMP3 EXTEVNT1 MSTCMP4 MSTCMP4 0 MSTCMP4 EXTEVNT2 EXTEVNT1 EXTEVNT1 0 EXTEVNT1 EXTEVNT3 EXTEVNT2 EXTEVNT2 0 EXTEVNT2 EXTEVNT4 EXTEVNT3 EXTEVNT3 0 EXTEVNT3 EXTEVNT5 EXTEVNT4 EXTEVNT4 0 EXTEVNT4 EXTEVNT6 EXTEVNT5 EXTEVNT5 0 EXTEVNT5 EXTEVNT7 EXTEVNT6 EXTEVNT6 0 EXTEVNT6 EXTEVNT8 EXTEVNT7 EXTEVNT7 0 EXTEVNT7 EXTEVNT9 EXTEVNT8 EXTEVNT8 0 EXTEVNT8 EXTEVNT9 EXTEVNT9 0 EXTEVNT9 TIMACMP1 EXTEVNT10 EXTEVNT10 EXTEVNT10 0 EXTEVNT10 TIMACMP2 TIMACMP1 TIMACMP1 0 TIMACMP1 TIMACMP4 TIMACMP2 TIMACMP2 0 TIMACMP2 TIMCCMP1 TIMACMP4 TIMACMP4 0 TIMACMP4 TIMCCMP2 TIMBCMP1 TIMBCMP1 0 TIMBCMP1 TIMCCMP4 TIMBCMP2 TIMBCMP2 0 TIMBCMP2 TIMDCMP1 TIMBCMP4 TIMBCMP4 0 TIMBCMP4 TIMDCMP2 TIMDCMP1 TIMCCMP1 0 TIMCCMP1 TIMDCMP2 TIMCCMP2 0 TIMCCMP2 TIMECMP1 TIMDCMP4 TIMDCMP4 TIMCCMP4 0 TIMCCMP4 TIMECMP2 TIMECMP1 TIMECMP1 TIMECMP2 TIMECMP2 0 TIMDCMP1 0 Res. Res. Res. TIMECMP4 Reset value Res. TIMECMP4 Reset value Res. 0 Res. Reset value TIMDCMP2 Reset value TC1RST TE1RST 0 TE1RST 0x0054 TIMECMP4 0x0054 TIMDCMP4 0x0054 Res. HRTIM_ RSTBR(1) Res. 0x0054 TCCMP1 TECMP1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name TCCMP2 TECMP2 0x005C 0 TECMP1 0x005C Reset value TECMP2 0x005C HRTIM_ CPT1ACR TECMP1 0x005C TECMP2 0x0058 TECMP1 Offset TECMP2 High-Resolution Timer (HRTIM) RM0433 Table 309. HRTIM Register map and reset values: TIMx (x= A..E) (continued) CARFRQ [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0068 1. HRTIM_FLTxR Reset value 0 IDLES2 IDLEM2 POL2 0 0 0 0 0 0 Res. Res. Res. DocID029587 Rev 3 TB1RST TB1SET TACMP2 TACMP1 TA1RST TA1SET EXEV10CPT 0 0 0 0 0 0 0 0 Res. Res. Res. Res. IDLES1 IDLEM1 POL1 0 0 0 0 0 0 FLT4EN FLT3EN FLT2EN FLT1EN 0 0 0 0 0 Res. FAULT1[1:0 ] 0 FLT5EN EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT EXEV4CPT DLYPRTEN 0 Res. EXEV5CPT 0 CHP1 0 Res. EXEV6CPT 0 DIDL1 EXEV7CPT 0 Res. EXEV8CPT 0 DTEN EXEV9CPT 0 Res. Res. TBCMP1 0 DLYPRT[2:0] TBCMP2 0 Res. Res. Res. TC1SET FAULT2[1:0 ] 0 Res. 0 CHP2 0 Res. 0 Res. TA1RST TA1SET EXEV10CPT EXEV9CPT EXEV8CPT EXEV7CPT EXEV6CPT EXEV5CPT EXEV4CPT EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT TACMP1 TA1RST TA1SET EXEV10CPT EXEV9CPT EXEV8CPT EXEV7CPT EXEV6CPT EXEV5CPT EXEV4CPT EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT TACMP1 TA1RST TA1SET EXEV10CPT EXEV9CPT EXEV8CPT EXEV7CPT EXEV6CPT EXEV5CPT EXEV4CPT EXEV3CPT EXEV2CPT EXEV1CPT UPDCPT SWCPT UPDCPT SWCPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. SWCPT EXEV1CPT 0 UPDCPT EXEV2CPT 0 EXEV1CPT EXEV3CPT 0 EXEV2CPT EXEV4CPT 0 EXEV3CPT EXEV5CPT 0 EXEV4CPT EXEV6CPT 0 EXEV5CPT EXEV7CPT 0 EXEV6CPT EXEV8CPT 0 EXEV7CPT EXEV9CPT 0 EXEV8CPT TA1SET EXEV10CPT 0 EXEV9CPT TA1RST 0 EXEV10CPT TACMP1 0 Res. Res. Res. Res. Res. 0 Res. Res. 0 DIDL2 Reset value TACMP1 Res. 0 Res. Res. HRTIM_ CPT2ECR Res. Res. 0 TB1SET Res. 0 TACMP2 Res. 0 0 Res. TE1SET 0 TACMP2 Res. TE1RST Reset value TACMP2 Res. HRTIM_ CPT2DCR TACMP2 Res. 0 Res. Res. 0 TB1RST TB1SET Res. TD1SET 0 TB1SET TD1RST 0 TB1SET TDCMP1 0 0 Res. TB1RST Res. TDCMP2 0 TBCMP1 TBCMP1 Res. TE1SET 0 TB1RST TE1RST 0 TBCMP1 TECMP1 Reset value TB1RST HRTIM_ CPT2CCR TBCMP1 Res. 0 TC1SET TC1SET 0 TBCMP2 TBCMP2 TC1RST 0 TBCMP2 TCCMP1 0 TBCMP2 TCCMP2 0 TC1RST TC1SET TD1SET 0 TC1SET TC1RST TD1RST 0 TCCMP1 TCCMP1 TDCMP1 0 TC1RST TDCMP2 0 TCCMP1 TE1SET 0 TC1RST TE1RST 0 TCCMP1 TECMP1 0 TD1SET TECMP2 Reset value TCCMP2 TCCMP2 HRTIM_ CPT2BCR TCCMP2 0 TCCMP2 0 TD1RST TD1SET 0 TD1SET 0 Res. TD1RST 0 TDCMP1 TDCMP1 0 TD1RST 0 TDCMP1 0 Res. 0 Res. TDCMP2 0 0 Res. Res. Res. Reset value Res. TE1SET 0 TDCMP2 TE1RST 0 TDCMP2 TECMP1 0 Res. Res. Res. TECMP2 0 TECMP2 Reset value Res. Res. HRTIM_OUTxR Res. 0x0064 0 TECMP1 0x0060 0 TECMP2 0x0060 Reset value Res. 0x0060 HRTIM_ CPT2ACR Res. 0x0060 Res. 0x0060 HRTIM_ CPT1ECR Res. 0x005C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset FLTLCK RM0433 High-Resolution Timer (HRTIM) Table 309. HRTIM Register map and reset values: TIMx (x= A..E) (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register can be preloaded (see Table 293 on page 1336). 1463/3178 1466 0x0020 0x0024 0x0028 Reset value 0 HRTIM_BMTRG Reset value 0 HRTIM_ BMCMPR(1) 1464/3178 0 0 Reset value DocID029587 Rev 3 SW 0 MSTRST 0 MSTREP 0 MSTCMP1 0 MSTCMP2 MTBM 0 0 0 0 0 BMOM BME BMPREN Res. Res. 0 0 TC2ODIS TC1ODIS TB2ODIS TB1ODIS TA2ODIS TA1ODIS 0 0 0 0 0 0 0 TC2ODS TC1ODS TB2ODS TD2OEN TD1OEN 0 0 TC2OEN TC1OEN TB2OEN 0 TB1OEN TA2OEN TA1OEN FLT4IE FLT3IE FLT2IE FLT1IE 0 FLT5IE FLT5C FLT4C FLT3C FLT2C FLT1C 0 SYSFLTC Res. TBRST TARST MRST Res. Res. Res. FLT5 FLT4 FLT3 FLT2 FLT1 Res. TESWU TDSWU TCSWU TBSWU TASWU MSWU Res. Res. TCRST Res. Res. TDRST Res. Res. MUDIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AD1USRC[2:0] TAUDIS Res. TBUDIS Res. TCUDIS Res. TDUDIS Res. AD2USRC[2:0] AD3USRC[2:0] AD4USRC[2:0] Res. Res. Res. Res. TEUDIS Res. TERST SYSFLT 0 SYSFLTIE Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 TA1ODS TD1ODIS 0 TD1ODS TE1OEN Res. Res. Res. Res. Res. Res. Res. Res. BMPER Res. 0 TA2ODS TD2ODIS 0 TD2ODS TE2OEN Res. Res. Res. Res. Res. Res. Res. BMPERC Res. Res. Res. 0 TB1ODS TE1ODIS Reset value 0 TE1ODS Reset value TE2ODIS Res. Res. Res. Res. Res. Res. Reset value TE2ODS Res. Res. Res. Res. Res. Res. Res. BMPERIE Res. Res. Res. Res. Reset value Res. Res. Res. Reset value Res. Res. Res. Reset value Res. Res. Res. Reset value Res. Res. Res. Res. Res. 0 Res. TABM Res. Res. Res. Res. Res. 0 MSTCMP3 0 Res. TBBM Res. Res. Res. Res. Res. 0 MSTCMP4 TCREP 0 Res. TCBM Res. Res. Res. Res. Res. 0 TARST TCCMP1 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 TAREP TDRST TCCMP2 0 Res. TEBM TDBM Res. Res. Res. Res. Res. Res. 0 TACMP1 TDREP 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TACMP2 TDCMP1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TBRST TDCMP2 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 TBREP TERST 0 Res. Res. Res. Res. Res. Res. 0 TBCMP1 TEREP 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 TCRST TECMP1 0 Res. Res. Res. Res. Res. Res. 0 TBCMP2 TECMP2 0 Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. HRTIM_ODSR Res. HRTIM_DISR Res. HRTIM_OENR Res. HRTIM_IER Res. 0x0010 Res. HRTIM_ICR Res. 0x000C Res. HRTIM_ISR Res. 0x008 Res. HRTIM_CR2 Res. 0x0004 Res. HRTIM_CR1 Res. 0x0000 Res. HRTIM_BMCR BMSTAT 0x001C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. 0x0018 OCHPEV Offset Res. 0x0014 Res. High-Resolution Timer (HRTIM) RM0433 Table 310. HRTIM Register map and reset values: Common functions 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMPRSC[3:0] BMCLK[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMCMP[15:0] 0 0 0 0 0 0 0x0050 AD1TEC3 AD1TEC2 AD1TDPER AD1TDC4 AD1TDC3 AD1TDC2 AD1TCPER AD1TCC4 AD1TCC3 AD1TCC2 AD1TBRST AD1TBPER AD1TBC4 AD1TBC3 AD1TBC2 AD1TARST AD1TAPER AD1TAC4 AD1TAC3 AD1TAC2 AD1EEV5 AD1EEV4 AD1EEV3 AD1EEV2 AD1EEV1 AD1MPER AD1MC4 AD1MC3 AD1MC2 AD1MC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ADC2R(1) AD2TEC3 AD2TEC2 AD2TDRST AD2TDPER AD2TDC4 AD2TDC3 AD2TDC2 AD2TCRST AD2TCPER AD2TCC4 AD2TCC3 AD2TCC2 AD2TBPER AD2TBC4 AD2TBC3 AD2TBC2 AD2TAPER AD2TAC4 AD2TAC3 AD2TAC2 AD2EEV10 AD2EEV9 AD2EEV8 AD2EEV7 AD2EEV6 AD2MPER AD2MC4 AD2MC3 AD2MC2 AD2MC1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ADC3R(1) AD1TEC3 AD1TEC2 AD1TDPER AD1TDC4 AD1TDC3 AD1TDC2 AD1TCPER AD1TCC4 AD1TCC3 AD1TCC2 AD1TBRST AD1TBPER AD1TBC4 AD1TBC3 AD1TBC2 AD1TARST AD1TAPER AD1TAC4 AD1TAC3 AD1TAC2 AD1EEV5 AD1EEV4 AD1EEV3 AD1EEV2 AD1EEV1 AD1MPER AD1MC4 AD1MC3 AD1MC2 AD1MC1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRTIM_ADC4R(1) AD2TEC3 AD2TEC2 AD2TDRST AD2TDPER AD2TDC4 AD2TDC3 AD2TDC2 AD2TCRST AD2TCPER AD2TCC4 AD2TCC3 AD2TCC2 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. FLT4SRC Res. Res. Res. Res. Res. Res. FLT4E FLT3LCK Res. Res. FLT4P FLT3SRC Res. HRTIM_FLTINxR1 0 Res. 0x004C AD1TEC4 0x0048 AD1TEPER 0x0044 Reset value AD2TEC4 0x0040 HRTIM_ADC1R(1) AD2TERST 0x003C AD1TEC4 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 FLT4F[3:0] 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 FLT2F[3:0] 0 0 0 0 0 0 0 AD2EEV6 AD2MPER AD2MC4 AD2MC3 AD2MC2 AD2MC1 0 0 0 0 0 0 0 0 0 Res. Res. FLT1SRC Res. Res. Res. FLT1P FLT1E 0 0 Res. 0 AD2EEV7 0 Res. 0 AD2EEV8 0 AD2EEV9 0 Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT1F[3:0] 0 0 0 0 0 0 EE1SRC[1:0] EE1POL 0 EE6SRC[1:0] 0 EE6POL EE1SNS[1:0] 0 0 0 0 0 0 EE6SRC[1:0] 0 0 Res. 0 0 EE6SNS[1:0] EE1FAST 0 Res. 0 Res. 0 0 Res. 0 0 EE2SRC[1:0] EE2POL EE2SNS[1:0] 0 EE7SRC[1:0] 0 EE7POL EE7SNS[1:0] EE2FAST 0 Res. Res. 0 FLT2E 0 FLT1LCK Res. 0 Res. 0 AD2EEV10 0 0 Res. 0 0 FLT2P 0 Res. EE3SRC[1:0] 0 Res. EE8SRC[1:0] EE3POL 0 Res. Res. EE8POL 0 AD2TAC2 Res. 0 AD2TAC3 Res. 0 0 Res. 0 EE3SNS[1:0] 0 FLT2SRC Res. 0 EE8SNS[1:0] EE3FAST EE4SRC[1:0] EE4POL EE4SNS[1:0] EE4FAST EE5SRC[1:0] EE5POL EE5SNS[1:0] EE5FAST Res. Res. Reset value AD2TAC4 0 Res. 0 AD2TBC2 0 AD2TAPER 0 Res. 0 Res. 0 Res. 0 0 Res. 0 AD2TBC3 0 0 FLT2LCK Res. FLT3F[3:0] Res. 0 Res. EE9SRC[1:0] EE9POL EE9SNS[1:0] Res. EE10SRC[1:0] EE10POL EE10SNS[1:0] 0 AD2TBC4 0 0 Res. 0 0 FLT3E 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 EE10SRC[1:0] 0 0 AD2TBPER Reset value 0 EE10POL Reset value EE10SNS[1:0] Res. 0 Res. HRTIM_EECR3 Res. Reset value Res. HRTIM_EECR2 Res. HRTIM_EECR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HRTIM_BMPER(1) Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name FLT3P 0x0038 ADC3TEPER 0x0034 AD2TEC4 0x0030 AD2TERST 0x002C Res. Offset FLT4LCK Res. RM0433 High-Resolution Timer (HRTIM) Table 310. HRTIM Register map and reset values: Common functions (continued) BMPER[15:0] 0 0 0 0 0 0 1465/3178 1466 0x0070 1. 0x006C HRTIM_ BDTEUPR 1466/3178 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMDDIER TIMDICR TIMDCR 0 0 0 0 HRTIM_BDMADR BDMADR[31:0] TIMEEEFR1 TIMERST2R 0 0 0 0 0 0 0 This register can be preloaded (see Table 293 on page 1336). DocID029587 Rev 3 0 0 TIMECR TIMDCNT 0 TIMEICR TIMDPER 0 TIMEDIER TIMDREP 0 TIMECNT TIMDCMP1 0 TIMEPER TIMDCMP2 0 TIMEREP TIMDCMP3 0 TIMECMP1 TIMDCMP4 0 TIMECMP2 TIMDDTxR 0 TIMECMP3 TIMDSET1R 0 TIMECMP4 TIMDRST1R 0 TIMEDTxR TIMDSET2R 0 TIMESET1R TIMDRST2R 0 TIMERST1R TIMDEEFR1 0 TIMESET2R TIMDEEFR2 0 0 TIMEEEFR2 0 TIMDRSTR 0 0 TIMERSTR 0 TIMDCHPR 0 TIMECHPR Reset value TIMDOUTR Reset value TIMEOUTR TIMCOUTR TIMCCHPR TIMCRSTR TIMCEEFR2 TIMCEEFR1 TIMCRST2R TIMCSET2R TIMCRST1R TIMCSET1R TIMCDTxR TIMCCMP4 TIMCCMP3 TIMCCMP2 TIMCCMP1 TIMCREP TIMCPER TIMCCNT TIMCDIER TIMCICR TIMCCR Reset value TIMCFLTR Res. TIMBOUTR TIMBCHPR TIMBRSTR TIMBEEFR2 TIMBEEFR1 TIMBRST2R TIMBSET2R TIMBRST1R TIMBSET1R TIMBDTxR TIMBCMP4 TIMBCMP3 TIMBCMP2 TIMBCMP1 TIMBREP TIMBPER TIMBCNT TIMBDIER TIMBICR TIMBCR Res. Res. Res. TIMBFLTR Reset value TIMDFLTR Res. Res. Res. Res. TIMAOUTR TIMACHPR TIMARSTR TIMAEEFR2 TIMAEEFR1 TIMARST2R TIMASET2R TIMARST1R TIMASET1R TIMADTxR TIMACMP4 TIMACMP3 TIMACMP2 TIMACMP1 TIMAREP TIMAPER TIMACNT TIMADIER TIMAICR TIMACR Res. Res. Res. Res. Res. Res. Res. TIMAFLTR Reset value TIMEFLTR Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCMP3 MCMP2 MCMP1 MREP MPER MCNT MDIER MICR MCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCMP4 Reset value FLT5P FLT5E FLT5LCK Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLTSD[1:0] Res. Res. Res. Res. Res. Res. FLT5SRC Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. HRTIM_ BDTDUPR Res. 0x0068 Res. HRTIM_ BDTCUPR Res. 0x0064 Res. HRTIM_ BDTBUPR Res. 0x0060 Res. HRTIM_BDTAUPR Res. HRTIM_ BDMUPDR Res. 0x0058 Res. 0x005C HRTIM_FLTINxR2 Res. 0x0054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. High-Resolution Timer (HRTIM) RM0433 Table 310. HRTIM Register map and reset values: Common functions (continued) 0 0 0 0 0 0 0 0 FLT5F[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Advanced-control timers (TIM1/TIM8) 38 Advanced-control timers (TIM1/TIM8) 38.1 TIM1/TIM8 introduction The advanced-control timers (TIM1/TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The advanced-control (TIM1/TIM8) and general-purpose (TIMy) timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 38.3.26: Timer synchronization. 38.2 TIM1/TIM8 main features TIM1/TIM8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. • Up to 6 independent channels for: – Input Capture (but channels 5 and 6) – Output Compare – PWM generation (Edge and Center-aligned Mode) – One-pulse mode output • Complementary outputs with programmable dead-time • Synchronization circuit to control the timer with external signals and to interconnect several timers together. • Repetition counter to update the timer registers only after a given number of cycles of the counter. • 2 break inputs to put the timer’s output signals in a safe user selectable configuration. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare • Supports incremental (quadrature) encoder and Hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management DocID029587 Rev 3 1467/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 337. Advanced-control timer block diagram &.B7,0IURP5&& ,QWHUQDOFORFN &.B,17 (75) 7,0[B(75 (75 2QFKLS(75 VRXUFHV (753 3RODULW\VHOHFWLRQ HGJHGHWHFWRU SUHVFDOHU ,75>@ 7ULJJHU FRQWUROOHU 75*2 WRRWKHUWLPHUV WR'$&$'& ,QSXW ILOWHU 7*, ,75 75& 75*, 7,)B(' 6ODYH 5HVHWHQDEOHXSGRZQFRXQW FRQWUROOHU PRGH (QFRGHU ,QWHUIDFH 7,)3 7,)3 5(3UHJLVWHU 8 8, $XWRUHORDGUHJLVWHU 5HSHWLWLRQ FRXQWHU 6WRSFOHDURUXSGRZQ &.B36& ;25 7,0[B&+ 7,>@ 7, 7,>@ 7,0[B&+ 7,>@ 7,>@ 7,0[B&+ 7,>@ 7,>@ 7,0[B&+ 7,>@ 7,>@ ,QSXW 7,)3 ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QSXW 7,)3 7, ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QSXW 7,)3 7, ILOWHU HGJH 7,)3 GHWHFWRU 75& ,QSXW 7,)3 7, ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QWHUQDO VRXUFHV 36& &.B&17 SUHVFDOHU &&, 8 ,& 3UHVFDOHU ,&36 &&, ,& 3UHVFDOHU &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU '7*UHJLVWHUV 2&5() '7* 2XWSXW FRQWURO &DSWXUH&RPSDUHUHJLVWHU 2&5() 7,0[B&+ 2& 7,0[B&+1 2&1 &&, 8 ,&36 8 7,0[B&+ '7* 2XWSXW FRQWURO 2& 7,0[B&+1 2&1 &&, 8 ,& 3UHVFDOHU ,&36 &&, ,& 3UHVFDOHU ,&36 &&, &DSWXUH&RPSDUHUHJLVWHU 7,0[B%.,1 2XWSXW FRQWURO 2& 7,0[B&+1 2&1 &DSWXUH&RPSDUHUHJLVWHU 2&5() 2XWSXW 2& FRQWURO &DSWXUH&RPSDUHUHJLVWHU 2&5() 2XWSXW 2& FRQWURO &DSWXUH&RPSDUHUHJLVWHU 2&5() 2XWSXW 2& FRQWURO 6%, ) %,) '7* &&, 8 7,0[B&+ 2&5() 7,0[B&+ (75) %5.UHTXHVW %UHDNDQG%UHDNFLUFXLWU\ %, ) %5.UHTXHVW 7,0[B%.,1 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 06Y9 1. See Figure 380: Break and Break2 circuitry overview for details 1468/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) 38.3 TIM1/TIM8 functional description 38.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) • Repetition counter register (TIMx_RCR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 338 and Figure 339 give some examples of the counter behavior when the prescaler ratio is changed on the fly: DocID029587 Rev 3 1469/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 338. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 339. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 1470/3178 DocID029587 Rev 3 RM0433 38.3.2 Advanced-control timers (TIM1/TIM8) Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1. Else the update event is generated at each counter overflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register, • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. DocID029587 Rev 3 1471/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 340. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 341. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 1472/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 342. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 343. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1473/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 344. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) <ͺW^ E dŝŵĞƌĐůŽĐŬс<ͺEd ŽƵŶƚĞƌƌĞŐŝƐƚĞƌ ϯϭ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϬϬ Ϭϭ ϬϮ Ϭϯ Ϭϰ Ϭϱ Ϭϲ Ϭϳ ŽƵŶƚĞƌŽǀĞƌĨůŽǁ hƉĚĂƚĞĞǀĞŶƚ;h sͿ hƉĚĂƚĞŝŶƚĞƌƌƵƉƚĨůĂŐ;h/&Ϳ ƵƚŽͲƌĞůŽĂĚƉƌĞůŽĂĚƌĞŐŝƐƚĞƌ && ϯϲ tƌŝƚĞĂŶĞǁǀĂůƵĞŝŶd/DdžͺZZ 069 Figure 345. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 1474/3178 DocID029587 Rev 3 069 RM0433 Advanced-control timers (TIM1/TIM8) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1. Else the update event is generated at each counter underflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register. • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. DocID029587 Rev 3 1475/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 346. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ FQWBXGI 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 347. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1476/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 348. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 349. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1477/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 350. Counter timing diagram, update event when repetition counter is not used &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or 1478/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 351. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 1. Here, center-aligned mode 1 is used (for more details refer to Section 38.4: TIM1/TIM8 registers). DocID029587 Rev 3 1479/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 352. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 353. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 1RWH +HUHFHQWHUBDOLJQHGPRGHRULVXSGDWHGZLWKDQ8,)RQRYHUIORZ 06 9 1480/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 354. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 355. Counter timing diagram, update event with ARPE=1 (counter underflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH UHJLVWHU )' 06 9 DocID029587 Rev 3 1481/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 356. Counter timing diagram, Update event with ARPE=1 (counter overflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH )' UHJLVWHU 06 9 38.3.3 Repetition counter Section 38.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register. The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 32768 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is 2xTck, due to the symmetry of the pattern. The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 357). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register. 1482/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the overflow. If the RCR was written after launching the counter, the UEV occurs on the underflow. For example, for RCR = 3, the UEV is generated each 4th overflow or underflow event depending on when the RCR was written. Figure 357. Update rate examples depending on mode and TIMx_RCR register settings (GJHDOLJQHGPRGH &RXQWHUDOLJQHGPRGH 8SFRXQWLQJ &RXQWHU 7,0[B&17 7,0[B5&5 7,0[B5&5 7,0[B5&5 7,0[B5&5 7,0[B5&5 DQG UHV\QFKURQL]DWLRQ 8(9 8(9 8(9 8(9 8(9 E\6: 8(9 'RZQFRXQWLQJ E\6: E\6: 8SGDWHHYHQW 3UHORDGUHJLVWHUVWUDQVIHUUHGWRDFWLYHUHJLVWHUVDQGXSGDWHLQWHUUXSWJHQHUDWHG 8SGDWH(YHQWLIWKHUHSHWLWLRQFRXQWHUXQGHUIORZRFFXUVZKHQWKHFRXQWHULVHTXDOWRWKHDXWRUHORDGYDOXH 06Y 9 DocID029587 Rev 3 1483/3178 1571 Advanced-control timers (TIM1/TIM8) 38.3.4 RM0433 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 38.3.5) • trigger for the slave mode (see Section 38.3.26) • PWM reset input for cycle-by-cycle current regulation (see Section 38.3.7) Figure 358 below describes the ETR input conditioning. The input polarity is defined with the ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield. Figure 358. External trigger input block (75LQSXW (75 'LYLGHU (73 7,0[B60&5 (736> @ 7,0[B60&5 (753 I'76 )LOWHU GRZQFRXQWHU 7RWKH2XWSXWPRGHFRQWUROOHU 7RWKH&.B36&FLUFXLWU\ 7RWKH6ODYHPRGHFRQWUROOHU (7)> @ 7,0[B60&5 069 The ETR input comes from multiple sources: input pins (default configuration), comparator outputs and analog watchdogs. The selection is done with the ETRSEL[3:0] bitfield. Figure 359. TIM1/TIM8 ETR input circuitry 7,0B$)> @ (75LQSXWVIURP$)FRQWUROOHU &203RXWSXW &203RXWSXW $'&$:' $'&$:' $'&$:' $'&$:' $'&$:' $'&$:' 7,0B$)> @ (75LQSXWVIURP$)FRQWUROOHU &203RXWSXW &203RXWSXW $'&$:' $'&$:' $'&$:' $'&$:' $'&$:' (75LQSXW $'&$:' 1& (75LQSXW 1& 06Y9 1484/3178 DocID029587 Rev 3 RM0433 38.3.5 Advanced-control timers (TIM1/TIM8) Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 360 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 360. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. DocID029587 Rev 3 1485/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 361. TI2 external clock connection example 7,0[B60&5 76> @ RU 7,) 7,) 7,0[B&+ 7,>@ 7, 7,>@ )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ ,75[ [[ 7,B(' 7,)3 7,)3 (75) ,&)> @ &&3 7,0[B&&05 7,0[B&&(5 RU RU (QFRGHU PRGH 75*, ([WHUQDOFORFN PRGH (75) ([WHUQDOFORFN PRGH &.B,17 LQWHUQDOFORFN ,QWHUQDOFORFN PRGH (&( &.B36& 606> @ 7,0[B60&5 06Y9 1. Codes ranging from 01000 to 11111 are reserved For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Note: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=00110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so the user does not need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. 1486/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 362. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The Figure 363 gives an overview of the external trigger input block. Figure 363. External trigger input block RU 7,) 7,) RU RU 7,0[B$)> @ 75*, (75 (75SLQ (753 'LYLGHU )LOWHU I GRZQFRXQWHU '76 (75) &.B,17 (73 (736> @ 7,0[B60&5 7,0[B60&5 (7)> @ LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH 7,0[B60&5 (&( 606> @ 7,0[B60&5 06Y9 1. Refer to Figure 359: TIM1/TIM8 ETR input circuitry. For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: DocID029587 Rev 3 1487/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 364. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 1488/3178 DocID029587 Rev 3 RM0433 38.3.6 Advanced-control timers (TIM1/TIM8) Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 365 to Figure 368 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 365. Capture/compare channel (example: channel 1 input stage) 7,0[B7,6(/> @ 7,0[B&+ 7,)B(' 7,>@ 7RWKHVODYHPRGHFRQWUROOHU 7,>@ )LOWHU GRZQFRXQWHU I'76 7,)B5LVLQJ 7,) (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 ,&)> @ 7,0[B&&05 &&3&&13 75& 7,0[B&&(5 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& 'LYLGHU ,&36 IURPVODYHPRGH FRQWUROOHU &&6> @ ,&36> @ 7,0[B&&05 &&( 7,0[B&&(5 06Y9 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. DocID029587 Rev 3 1489/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 366. Capture/compare channel 1 main circuit $3%%XV LIELW 0&8SHULSKHUDOLQWHUIDFH 5HDG&&5/ UHDGBLQBSURJUHVV ORZ 5HDG&&5+ 6 KLJK &DSWXUHFRPSDUHSUHORDGUHJLVWHU &&6>@ 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ,QSXW PRGH 6 ZULWH&&5+ ZULWHBLQBSURJUHVV 2XWSXW PRGH &&6>@ &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU 8(9 &RPSDUDWRU &DSWXUH ,&36 ZULWH&&5/ &&( &17!&&5 &RXQWHU IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 &&* 7,0B(*5 06 9 Figure 367. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) 7RWKHPDVWHUPRGH FRQWUROOHU (75) µ¶ 2&5() &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&[5() 2&5() 2&5()& 2&B'7 2XWSXW VHOHFWRU 'HDGWLPH JHQHUDWRU [ 2XWSXW HQDEOH FLUFXLW 2& 2XWSXW HQDEOH FLUFXLW 2&1 &&3 7,0B&&(5 2&1B'7 µ¶ [ &&1( &&( 7,0B&&(5 2&&( 2&0> @ '7*> @ &&1( &&( &&13 02( 266, 2665 7,0B&&05 7,0B%'75 7,0B&&(5 7,0B&&(5 7,0B%'75 06 9 1. OCxREF, where x is the rank of the complementary channel 1490/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 368. Output stage of capture/compare channel (channel 4) 7RWKHPDVWHU PRGHFRQWUROOHU (75) 2&5()& 2&5() µ¶ &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU &&( &&3 2XWSXW VHOHFWRU 2&5() 7,0B&&(5 2XWSXW HQDEOH FLUFXLW &&( 7,0B&&(5 7,0B&&(5 02( 2&&( 2&0> @ 2& 7,0B&&05 266, 7,0B%'75 2,6 7,0B&5 06 9 Figure 369. Output stage of capture/compare channel (channel 5, idem ch. 6) 7RWKHPDVWHU PRGHFRQWUROOHU (75) &17!&&5 2XWSXW &17 &&5 PRGH FRQWUROOHU µ¶ 2&5() &&( &&3 7,0B&&(5 7,0B&&(5 2&&( 2&0> @ 2XWSXW HQDEOH FLUFXLW 2& &&( 7,0B&&(5 02( 266, 7,0B%'75 7,0B&&05 2,6 7,0B&5 06 9 1. Not available externally. The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. DocID029587 Rev 3 1491/3178 1571 Advanced-control timers (TIM1/TIM8) 38.3.7 RM0433 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. • Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). • Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). • Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. • If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: 1492/3178 IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID029587 Rev 3 RM0433 38.3.8 Advanced-control timers (TIM1/TIM8) PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). • Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to CC2P/CC2NP=’10’ (active on falling edge). • Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register (TI1FP1 selected). • Configure the slave mode controller in reset mode: write the SMS bits to 0100 in the TIMx_SMCR register. • Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 370. PWM input mode timing 38.3.9 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, user just needs to write 0101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is DocID029587 Rev 3 1493/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 38.3.10 Output compare mode This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the microcontroller (for instance, for compound waveform generation or for ADC triggering). When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=0000), be set active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode). Procedure 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: 5. – Write OCxM = 0011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx 1494/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) shadow register is updated only at the next update event UEV). An example is given in Figure 371. Figure 371. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 06 9 38.3.11 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. DocID029587 Rev 3 1495/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 1471. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 372 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. Figure 372. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 06 9 • Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the Downcounting mode on page 1475 In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the 1496/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the Center-aligned mode (up/down counting) on page 1478. Figure 373 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 373. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E Hints on using center-aligned mode • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit DocID029587 Rev 3 1497/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • • 38.3.12 Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx register. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle: – OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 – OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Asymmetric PWM mode can be selected independently on two channel (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’ (Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. When a given channel is used as asymmetric PWM channel, its complementary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 1. Figure 374 represents an example of signals that can be generated using Asymmetric PWM mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Together with the deadtime generator, this allows a full-bridge phase-shifted DC to DC converter to be controlled. 1498/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 374. Generation of 2 phase-shifted PWM signals with 50% duty cycle &RXQWHUUHJLVWHU &&5 &&5 &&5 &&5 2&5()& 2&5()& 069 38.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: – OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 – OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. When a given channel is used as combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 375 represents an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration: – Channel 1 is configured in Combined PWM mode 2, – Channel 2 is configured in PWM mode 1, – Channel 3 is configured in Combined PWM mode 2, – Channel 4 is configured in PWM mode 1. DocID029587 Rev 3 1499/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 375. Combined PWM mode on channel 1 and 3 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 06 9 38.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal. The 3-bits GC5C[3:1] in the TIMx_CCR5 allow selection on which reference signal the OC5REF is combined. The resulting signals, OCxREFC, are made of an AND logical combination of two reference PWMs: – If GC5C1 is set, OC1REFC is controlled by TIMx_CCR1 and TIMx_CCR5 – If GC5C2 is set, OC2REFC is controlled by TIMx_CCR2 and TIMx_CCR5 – If GC5C3 is set, OC3REFC is controlled by TIMx_CCR3 and TIMx_CCR5 Combined 3-phase PWM mode can be selected independently on channels 1 to 3 by setting at least one of the 3-bits GC5C[3:1]. 1500/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 376. 3-phase combined PWM signals with multiple trigger pulses per period 2& $55 2& 2& 2& 2& 2& &RXQWHU 2&UHI 2&UHI& *&&> @ 2&UHI& 2&UHI& 3UHORDG $FWLYH [[[ [[[ 2&UHI 2&UHI 75*2 069 The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. Please refer to Section 38.3.27: ADC synchronization for more details. 38.3.15 Complementary outputs and dead-time insertion The advanced-control timers (TIM1/TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 314: Output control bits for complementary OCx and OCxN channels with break feature on page 1546 for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0). DocID029587 Rev 3 1501/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 377. Complementary output with dead-time insertion 2&[5() 2&[ GHOD\ 2&[1 GHOD\ 06 9 Figure 378. Dead-time waveforms with delay greater than the negative pulse 2&[5() 2&[ GHOD\ 2&[1 06 9 1502/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 379. Dead-time waveforms with delay greater than the positive pulse 2&[5() 2&[ 2&[1 GHOD\ 06 9 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 38.4.18: TIM1/TIM8 break and deadtime register (TIMx_BDTR) for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. 38.3.16 Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM1 and TIM8 timers. The two break inputs are usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state. A number of internal MCU events can also be selected to trigger an output shut-down. The break features two channels. A break channel which gathers both system-level fault (clock failure, parity error,...) and application fault (from input pins and built-in comparator), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration. A break2 channel which only includes application faults and is able to force the outputs to an inactive state. DocID029587 Rev 3 1503/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. – the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode) – the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shut-down level, either active or inactive. The OCx and OCxN outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values. Refer to Table 314: Output control bits for complementary OCx and OCxN channels with break feature on page 1546 for more details. When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break functions by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break input polarities can be selected by configuring the BKP and BKP2 bits in the same register. BKEx and BKPx can be modified at the same time. When the BKEx and BKPx bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. The sources for break (BRK) channel are: • An external source connected to one of the BKIN pin (as per selection done in the AFIO controller), with polarity selection and optional digital filtering • An internal source: – the output from a comparator, with polarity selection and optional digital filtering – the analog watchdog output of the DFSDM1 peripheral – A system break: - the Cortex®-M7 LOCKUP output - the PVD output - the SRAM parity error signal - a Flash ECC error - a clock failure event generated by the CSS detector The sources for break2 (BRK2) are: • An external source connected to one of the BKIN pin (as per selection done in the AFIO controller), with polarity selection and optional digital filtering • An internal source coming from a comparator output. Break events can also be generated by software using BG and B2G bits in the TIMx_EGR register. All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 380 below. 1504/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 380. Break and Break2 circuitry overview &RUH/RFNXS 39' /RFNXS/2&. 39'/2&. 6\VWHPEUHDNUHTXHVWV 5$0SDULW\(UURU (&&(UURU 6%,)IODJ 3DULW\/2&. (&&/2&. &66 %.,13 %.,1LQSXWV IURP$) FRQWUROOHU %.,1( 6RIWZDUHEUHDNUHTXHVWV %* %.&033 %.&03( &203RXWSXW %.)> @ %.( %,)IODJ %.3 %5.UHTXHVW )LOWHU %.&033 %.&03( &203RXWSXW $SSOLFDWLRQEUHDNUHTXHVWV %.')%.[( ')6'0 %5($.RXWSXW %.,13 %.,1LQSXWV IURP$) FRQWUROOHU %.,1( 6RIWZDUHEUHDNUHTXHVWV %* %.&033 %.&03( &203RXWSXW %.)> @ %.( %,)IODJ %.3 %5.UHTXHVW )LOWHU %.&033 &203RXWSXW ')6'0 %5($.RXWSXW %.&03( $SSOLFDWLRQEUHDNUHTXHVWV %.')%.[( 069 Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or the CSS) must be used to guarantee that break events are handled. DocID029587 Rev 3 1505/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 When one of the breaks occurs (selected level on one of the break inputs): Note: • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off. • Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the GPIO controller), otherwise the enable output remains high. • When complementary outputs are used: – The outputs are first put in inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is slightly longer than usual (around 2 ck_tim clock cycles). – If OSSI=0, the timer releases the output control (taken over by the GPIO controller which forces a Hi-Z state), otherwise the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. • The break status flag (SBIF, BIF and B2IF bits in the TIMx_SR register) is set. An interrupt is generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event (UEV). As an example, this can be used to perform a regulation. Otherwise, MOE remains low until the application sets it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. The break inputs are active on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF cannot be cleared. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The application can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 38.4.18: TIM1/TIM8 break and dead-time register (TIMx_BDTR). The LOCK bits can be written only once after an MCU reset. Figure 381 shows an example of behavior of the outputs in response to a break. 1506/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 381. Various output behavior in response to a break event on BRK (OSSI = 1) %5($. 02( 2&[5() 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 &&[1( &&[13 2,6[ 2,6[1 RU2,6[ 2,6[1 06 9 DocID029587 Rev 3 1507/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 311. Note: BRK2 must only be used with OSSR = OSSI = 1. Table 311. Behavior of timer outputs versus BRK/BRK2 inputs Typical use case BRK2 Timer outputs state Active Inactive BRK OCxN output (low side switches) OCx output (high side switches) X – Inactive then forced output state (after a deadtime) – Outputs disabled if OSSI = 0 (control taken over by GPIO logic) ON after deadtime insertion OFF Active Inactive OFF OFF Figure 382 gives an example of OCx and OCxN output behavior in case of active signals on BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP = CCxNP = 0 in TIMx_CCER register). Figure 382. PWM output state following BRK and BRK2 pins assertion (OSSI=1) Z<Ϯ Z< Kdž ĞĂĚƚŝŵĞ ĞĂĚƚŝŵĞ /ͬKƐƚĂƚĞ ĐƚŝǀĞ /ŶĂĐƚŝǀĞ /ĚůĞ D^ϯϰϭϬϲsϭ 1508/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 383. PWM output state following BRK assertion (OSSI=0) Z< /ͬKƐƚĂƚĞĚĞĨŝŶĞĚďLJƚŚĞ'W/KĐŽŶƚƌŽůůĞƌ;,/ͲͿ Kdž ĞĂĚƚŝŵĞ /ͬKƐƚĂƚĞĚĞĨŝŶĞĚďLJƚŚĞ'W/KĐŽŶƚƌŽůůĞƌ;,/ͲͿ /ͬKƐƚĂƚĞ ĐƚŝǀĞ /ŶĂĐƚŝǀĞ ŝƐĂďůĞĚ D^ϯϰϭϬϳsϭ 38.3.17 Bidirectional break inputs Beside regular digital break inputs and internal break events coming from the comparators, the timer 1 and 8 are featuring bidirectional break inputs/outputs combining the two sources, as represented on Figure 384. The TIMx_BKINy_COMPz pins are combining the COMPz output (to be configured in open drain) and the Timerx’s TIMx_BKINy input. They allow to have: - A global break information available for external MCUs or gate drivers shut down inputs, with a single-pin. - An internal comparator and multiple external open drain comparators outputs ORed together and triggering a break event, when the multiple internal and external break inputs must be merged. Figure 384. Output redirection %.,13 7RWKHWLPHUEUHDNLQSXW DFWLYHKLJK $), $)LQSXWHQDEOHG DFWLYHORZ 7,0[B%.,1\B&203] [ \ 1$ ] &203 $)2 $)RXWSXWFRQILJXUHGDVRSHQGUDLQ 069 38.3.18 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs. This function can only be DocID029587 Rev 3 1509/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 used in Output compare and PWM modes. It does not work in Forced mode. The ocref_clr_int is connected to the ETRF signal (ETR after filtering). When ETRF is chosen, ETR must be configured as follows: 1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’. 2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to ‘0’. 3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs. Figure 385 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode. Figure 385. Clearing TIMx OCxREF &&5[ &RXQWHU &17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ RFUHIBFOUBLQW EHFRPHVKLJK RFUHIBFOUBLQW VWLOOKLJK 069 Note: 1510/3178 In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow. DocID029587 Rev 3 RM0433 38.3.19 Advanced-control timers (TIM1/TIM8) 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on TRGI rising edge). A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the TIMx_DIER register). The Figure 386 describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations. Figure 386. 6-step generation, COM example (OSSR=1) DocID029587 Rev 3 1511/3178 1571 Advanced-control timers (TIM1/TIM8) 38.3.20 RM0433 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx) • In downcounting: CNT > CCRx Figure 387. Example of one pulse mode. 7, 2&5() 2& &RXQWHU 7,0B$55 7,0B&&5 W'(/$< W38/6( W 06 9 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: 1512/3178 • Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=00110 in the TIMx_SMCR register. • TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 38.3.21 Retriggerable one pulse mode (OPM) This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one pulse mode described in Section 38.3.20: – The pulse starts as soon as the trigger occurs (no programmable delay) – The pulse is extended if a new trigger occurs before the previous one is completed The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for Retrigerrable OPM mode 1 or 2. If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode, CCRx must be above or equal to ARR. Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit are not contiguous with the 3 least significant ones. This mode must not be used with center-aligned PWM modes. It is mandatory to have CMS[1:0] = 00 in TIMx_CR1. DocID029587 Rev 3 1513/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 388. Retriggerable one pulse mode 75*, &RXQWHU 2XWSXW 069 38.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. CC1NP and CC2NP must be kept low. The two inputs TI1 and TI2 are used to interface to an quadrature encoder. Refer to Table 312. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. Note: The prescaler must be set to zero when encoder mode is enabled In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. 1514/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Table 312. Counting direction versus encoder signals Active edge Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) TI1FP1 signal TI2FP2 signal Rising Falling Rising Falling Counting on TI1 only High Down Up No Count No Count Low Up Down No Count No Count Counting on TI2 only High No Count No Count Up Down Low No Count No Count Down Up Counting on TI1 and TI2 High Down Up Up Down Low Up Down Down Up A quadrature encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. The Figure 389 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: • CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1). • CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2). • CC1P=’0’ and CC1NP=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1). • CC2P=’0’ and CC2NP=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2). • SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges). • CEN=’1’ (TIMx_CR1 register, Counter enabled). Figure 389. Example of counter operation in encoder interface mode. IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU XS GRZQ XS 069 DocID029587 Rev 3 1515/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Figure 390 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 390. Example of encoder interface mode with TI1FP1 polarity inverted. IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU GRZQ XS GRZQ 069 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request. The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt). There is no latency between the UIF and UIFCPY flag assertions. In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only accessible in write mode). 38.3.23 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. In particular cases, it can ease the calculations by avoiding race conditions, caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the UIF and UIFCPY flags assertion. 1516/3178 DocID029587 Rev 3 RM0433 38.3.24 Advanced-control timers (TIM1/TIM8) Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. It is convenient to measure the interval between edges on two input signals, as per Figure 391 below. Figure 391. Measuring time interval between edges on 3 signals 7, 7, 7, ;25 7,0[ &RXQWHU 06 9 38.3.25 Interfacing with Hall sensors This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4) referred to as “interfacing timer” in Figure 392. The “interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register). The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs. On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (See Figure 365: Capture/compare channel (example: channel 1 input stage) on page 1489). The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed. The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-control timer (TIM1 or TIM8) through the TRGO output. DocID029587 Rev 3 1517/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, • Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors, • Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the TIMx_CCMR1 register to ‘01’. You can also program the digital filter if needed, • Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register, • Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’, In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). The Figure 392 describes this example. 1518/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Figure 392. Example of Hall sensor interface 7,+ ,QWHUIDFLQJWLPHU 7,+ 7,+ &RXQWHU &17 &&5 &&5 &$ &$ & &$ &$% & $GYDQFHGFRQWUROWLPHUV 7,0 7,0 75*2 2&5() &20 2& 2&1 2& 2&1 2& 2&1 :ULWH&&[(&&[1( DQG2&[0IRUQH[WVWHS DL DocID029587 Rev 3 1519/3178 1571 Advanced-control timers (TIM1/TIM8) 38.3.26 RM0433 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: • Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edges only). • Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=00101 in TIMx_SMCR register. • Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 393. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 1520/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=00101 in TIMx_SMCR register. • Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 394. Control circuit in Gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. DocID029587 Rev 3 1521/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 395. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: Combined reset + trigger mode In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter. This mode is used for one-pulse mode. Slave mode: external clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1522/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) 1. 2. 3. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source – CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=00101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. Figure 396. Control circuit in external clock mode 2 + trigger mode 7, &(1&17B(1 (75 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) 069 Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. DocID029587 Rev 3 1523/3178 1571 Advanced-control timers (TIM1/TIM8) 38.3.27 RM0433 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: – Rising and falling edges of OC4ref – Rising edge on OC5ref or falling edge on OC6ref The triggers are issued on the TRGO2 internal line which is redirected to the ADC. There is a total of 16 possible events, which can be selected using the MMS2[3:0] bits in the TIMx_CR2 register. An example of an application for 3-phase motor drives is given in Figure 376 on page 1501. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Note: The clock of the ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the timer. 38.3.28 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals. The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers. The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register: Example: 00000: TIMx_CR1 00001: TIMx_CR2 00010: TIMx_SMCR As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the CCRx registers. 1524/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) This is done in the following steps: 1. Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. Note: A null value can be written to the reserved registers. 38.3.29 Debug mode When the microcontroller enters debug mode (Cortex®-M7 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0), typically to force a Hi-Z. For more details, refer to Section 60.5.8: Microcontroller debug unit (DBGMCU). For safety purposes, when the counter is stopped (TIMx = 1 in DBGMCU_APB2FZ1), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force them to Hi-Z. DocID029587 Rev 3 1525/3178 1571 Advanced-control timers (TIM1/TIM8) 38.4 RM0433 TIM1/TIM8 registers Refer to for a list of abbreviations used in register descriptions. 38.4.1 TIM1/TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 11 10 Res. UIFRE MAP Res. rw 9 8 CKD[1:0] rw 7 6 ARPE rw rw 5 CMS[1:0] rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 1526/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 38.4.2 TIM1/TIM8 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 MMS2[3:0] rw rw 6 15 14 13 12 11 10 9 8 7 Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S rw rw rw rw rw rw rw rw rw rw 5 4 MMS[2:0] rw DocID029587 Rev 3 rw rw 19 18 17 16 Res. OIS6 Res. OIS5 rw rw 3 2 1 0 CCDS CCUS Res. CCPC rw rw rw 1527/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. 0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0010: Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. 0011: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). 0100: Compare - OC1REF signal is used as trigger output (TRGO2) 0101: Compare - OC2REF signal is used as trigger output (TRGO2) 0110: Compare - OC3REF signal is used as trigger output (TRGO2) 0111: Compare - OC4REF signal is used as trigger output (TRGO2) 1000: Compare - OC5REF signal is used as trigger output (TRGO2) 1001: Compare - OC6REF signal is used as trigger output (TRGO2) 1010: Compare Pulse - OC4REF rising or falling edges generate pulses on TRGO2 1011: Compare Pulse - OC6REF rising or falling edges generate pulses on TRGO2 1100: Compare Pulse - OC4REF or OC6REF rising edges generate pulses on TRGO2 1101: Compare Pulse - OC4REF rising or OC6REF falling edges generate pulses on TRGO2 1110: Compare Pulse - OC5REF or OC6REF rising edges generate pulses on TRGO2 1111: Compare Pulse - OC5REF rising or OC6REF falling edges generate pulses on TRGO2 Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bit 19 Reserved, must be kept at reset value. Bit 18 OIS6: Output Idle state 6 (OC6 output) Refer to OIS1 bit Bit 17 Reserved, must be kept at reset value. Bit 16 OIS5: Output Idle state 5 (OC5 output) Refer to OIS1 bit Bit 15 Reserved, must be kept at reset value. Bit 14 OIS4: Output Idle state 4 (OC4 output) Refer to OIS1 bit Bit 13 OIS3N: Output Idle state 3 (OC3N output) Refer to OIS1N bit Bit 12 OIS3: Output Idle state 3 (OC3 output) Refer to OIS1 bit 1528/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs DocID029587 Rev 3 1529/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). Note: This bit acts only on channels that have a complementary output. 38.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 ETP ECE rw rw 13 12 11 ETPS[1:0] rw rw 10 9 8 ETF[3:0] rw rw rw 7 6 MSM rw rw 21 20 TS[4:3] rw rw 5 4 TS[2:0] rw rw 19 18 17 16 Res. Res. Res. SMS[3] 3 2 1 rw Res. rw 0 SMS[2:0] rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 TS[4:3]: Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 Bits 19:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits 2:0 Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. 1530/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[2:0]: Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1) 00110: Filtered Timer Input 2 (TI2FP2) 00111: External Trigger input (ETRF) Others: Reserved See Table 313: TIMx internal trigger connection on page 1532 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. DocID029587 Rev 3 1531/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Table 313. TIMx internal trigger connection 38.4.4 Slave TIM ITR0 (TS = 00000) ITR1 (TS = 00001) ITR2 (TS = 00010) ITR3 (TS = 00011) TIM1 TIM15 TIM2 TIM3 TIM4 TIM8 TIM1 TIM2 TIM4 TIM5 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 Res. TDE rw 1532/3178 13 12 11 10 9 COMDE CC4DE CC3DE CC2DE CC1DE rw rw rw rw rw 8 7 6 5 4 3 2 1 0 UDE BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled 1: CC4 interrupt enabled Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled DocID029587 Rev 3 1533/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 38.4.5 TIM1/TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6IF CC5IF rc_w0 rc_w0 15 14 13 Res. Res. SBIF rc_w0 12 11 10 9 CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0 8 7 6 5 4 3 2 1 0 B2IF BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:18 Reserved, must be kept at reset value. Bit 17 CC6IF: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output) Bit 16 CC5IF: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output) Bits 15:14 Reserved, must be kept at reset value. Bit 13 SBIF: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. Bit 12 CC4OF: Capture/Compare 4 overcapture flag Refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag Refer to CC1OF description Bit 10 CC2OF: Capture/Compare 2 overcapture flag Refer to CC1OF description 1534/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 B2IF: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5 COMIF: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending. Bit 4 CC4IF: Capture/Compare 4 interrupt flag Refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag Refer to CC1IF description Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) DocID029587 Rev 3 1535/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 38.4.3: TIM1/TIM8 slave mode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 38.4.6 TIM1/TIM8 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. B2G BG TG COMG CC4G CC3G CC2G CC1G UG w w w w w w w w w Bits 15:9 Reserved, must be kept at reset value. Bit 8 B2G: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output. Bit 4 CC4G: Capture/Compare 4 generation Refer to CC1G description Bit 3 CC3G: Capture/Compare 3 generation Refer to CC1G description 1536/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 38.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. OC1M[3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 OC1 PE OC1 FE rw 15 14 OC2 CE 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE 9 8 CC2S[1:0] rw OC1 CE OC1M[2:0] IC2PSC[1:0] rw rw rw IC1F[3:0] rw rw rw rw DocID029587 Rev 3 rw 0 CC1S[1:0] IC1PSC[1:0] rw rw rw rw rw 1537/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC2M[3]: Output Compare 2 mode - bit 3 Refer to OC2M description on bits 14:12. Bits 23:17 Reserved, must be kept at reset value. Bits16 OC1M[3]: Output Compare 1 mode - bit 3 Refer to OC1M description on bits 6:4 Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 OC1CE: Output Compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 1538/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT TIMx_CCR1 else active (OC1REF=’1’). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT TIMx_CCR1 else inactive. 1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. DocID029587 Rev 3 1539/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). Input capture mode Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). 1540/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). 38.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 0000 Refer to the above CCMR1 register description. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Res. OC3M[3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 OC3 PE OC3 FE rw 15 14 OC4 CE 13 12 OC4M[2:0] IC4F[3:0] rw rw rw 11 10 OC4 PE OC4 FE 9 8 CC4S[1:0] rw OC3 CE. OC3M[2:0] IC4PSC[1:0] rw rw rw IC3F[3:0] rw rw rw rw DocID029587 Rev 3 rw 0 CC3S[1:0] IC3PSC[1:0] rw rw rw rw rw 1541/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC4M[3]: Output Compare 4 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC3M[3]: Output Compare 3 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). Input capture mode Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). 1542/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). 38.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6P CC6E Res. Res. CC5P CC5E rw rw rw rw 5 4 CC2P CC2E rw rw 15 14 13 12 CC4NP Res. CC4P CC4E rw rw rw 11 10 CC3NP CC3NE rw rw 9 8 CC3P CC3E rw rw 7 6 CC2NP CC2NE rw rw 3 2 CC1NP CC1NE rw rw 1 0 CC1P CC1E rw rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 CC6P: Capture/Compare 6 output polarity Refer to CC1P description Bit 20 CC6E: Capture/Compare 6 output enable Refer to CC1E description Bits 19:18 Reserved, must be kept at reset value. Bit 17 CC5P: Capture/Compare 5 output polarity Refer to CC1P description Bit 16 CC5E: Capture/Compare 5 output enable Refer to CC1E description Bit 15 CC4NP: Capture/Compare 4 complementary output polarity Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output polarity Refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable Refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity Refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable Refer to CC1NE description DocID029587 Rev 3 1543/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 9 CC3P: Capture/Compare 3 output polarity Refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 complementary output polarity Refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable Refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. 1544/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). 01: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). 10: reserved, do not use this configuration. 11: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. DocID029587 Rev 3 1545/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Table 314. Output control bits for complementary OCx and OCxN channels with break feature Output states(1) Control bits MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit 1 0 0 Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 0 0 1 Output disabled (not driven OCxREF + Polarity by the timer: Hi-Z) OCxN = OCxREF xor CCxNP OCx=0 0 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP Output Disabled (not driven by the timer: Hi-Z) OCxN=0 X 1 1 OCREF + Polarity + deadtime Complementary to OCREF (not OCREF) + Polarity + dead-time 1 0 1 Off-State (output enabled with inactive state) OCx=CCxP OCxREF + Polarity OCxN = OCxREF x or CCxNP 1 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP Off-State (output enabled with inactive state) OCxN=CCxNP X X 0 0 0 1 1 0 1 1 X 1 OCxN output state X 0 0 OCx output state X Output disabled (not driven by the timer anymore). The output state is defined by the GPIO controller and can be High, Low or Hi-Z. Off-State (output enabled with inactive state) Asynchronously: OCx=CCxP, OCxN=CCxNP (if BRK or BRK2 is triggered). Then (this is valid only if BRK is triggered), if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state (may cause a short circuit when driving switches in half-bridge configuration). Note: BRK2 can only be used if OSSI = OSSR = 1. 1. When both outputs of a channel are not used (control taken over by GPIO), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. Note: 1546/3178 The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) 38.4.10 TIM1/TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UIF CPY Res. Res. Res. Res. Res. Res. Res. Re s. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r CNT[15:0] rw Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 38.4.11 TIM1/TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 38.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 38.3.1: Time-base unit on page 1469 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID029587 Rev 3 1547/3178 1571 Advanced-control timers (TIM1/TIM8) 38.4.13 RM0433 TIM1/TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw REP[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 38.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR1[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output:: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input:: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. 1548/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) 38.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR2[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. 38.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR3[15:0] rw/r Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. DocID029587 Rev 3 1549/3178 1571 Advanced-control timers (TIM1/TIM8) 38.4.17 RM0433 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR4[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. 38.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 R e s. Res. Res. Res. Res. Res. BK2P BK2E rw rw 15 14 13 12 11 10 MOE AOE BKP BKE OSSR OSSI rw rw rw rw rw rw Note: 9 8 23 22 21 rw rw 19 18 17 16 BKF[3:0] rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw LOCK[1:0] rw 20 BK2F[3:0] DTG[7:0] rw As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. Bits 31:26 Reserved, must be kept at reset value. Bit 25 BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 1550/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 24 BK2E: Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 380: Break and Break2 circuitry overview). 0: Break2 function disabled 1: Break2 function enabled Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bits 23:20 BK2F[3:0]: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 19:16 BKF[3:0]: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID029587 Rev 3 1551/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). See OC/OCN enable description for more details (Section 38.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER)). Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 12 BKE: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 380: Break and Break2 circuitry overview). 0: Break function disabled 1: Break function enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 38.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 1552/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 38.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER)). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 38.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res. Res. Res. rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. DocID029587 Rev 3 1553/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer 00001: 2 transfers 00010: 3 transfers ... 10001: 18 transfers Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. – If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data will be copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: – If you configure the DMA Data Size in half-words, 16-bit data will be transferred to each of the 7 registers. – If you configure the DMA Data Size in bytes, the data will also be transferred to 7 registers: the first register will contain the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, you also have to specify the size of data transferred by DMA. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 38.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAB[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw DMAB[15:0] 1554/3178 rw rw DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 38.4.21 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3) Address offset: 0x54 Reset value: 0x0000 0000 Refer to the above CCMR1 register description. Channels 5 and 6 can only be configured in output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC6M[3] Res. Res. Res. Res. Res. Res. Res. OC5M[3] rw 15 14 OC6 CE rw 13 12 OC6M[2:0] rw rw rw 11 10 OC6 PE OC6FE rw rw 9 Res. rw 8 7 Res. OC5 CE. rw 6 5 4 OC5M[2:0] rw rw 3 2 OC5PE OC5FE rw rw 1 0 Res. Res. rw Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC6M[3]: Output Compare 6 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC5M[3]: Output Compare 5 mode - bit 3 Bit 15 OC6CE: Output compare 6 clear enable Bits 14:12 OC6M: Output compare 6 mode Bit 11 OC6PE: Output compare 6 preload enable Bit 10 OC6FE: Output compare 6 fast enable Bits 9:8 Reserved, must be kept at reset value. Bit 7 OC5CE: Output compare 5 clear enable Bits 6:4 OC5M: Output compare 5 mode Bit 3 OC5PE: Output compare 5 preload enable Bit 2 OC5FE: Output compare 5 fast enable Bits 1:0 Reserved, must be kept at reset value. DocID029587 Rev 3 1555/3178 1571 Advanced-control timers (TIM1/TIM8) 38.4.22 RM0433 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5) Address offset: 0x58 Reset value: 0x0000 0000 31 30 29 GC5C3 GC5C2 GC5C1 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw CCR5[15:0] rw rw Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. Bit 30 GC5C2: Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. Bit 29 GC5C1: Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. Bits 28:16 Reserved, must be kept at reset value. Bits 15:0 CCR5[15:0]: Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. 1556/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) 38.4.23 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6) Address offset: 0x5C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR6[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR6[15:0]: Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. 38.4.24 TIM1 alternate function option register 1 (TIM1_AF1) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ETRSEL[1:0] rw rw Res. Res. BK BK BKINP CMP2P CMP1P rw rw rw BKDF1 BK0E Res. Res. rw Res. Res. Res. 17 16 ETRSEL[3:2] rw rw 1 0 BK BK BKINE CMP2E CMP1E rw rw rw Bits 31:18 Reserved, must be kept at reset value Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source. 0000: ETR input is connected to I/O 0001: COMP1 output 0010: COMP2 output 0011: ADC1 AWD1 0100: ADC1 AWD2 0101: ADC1 AWD3 0110: ADC3 AWD1 0111: ADC3 AWD2 1000: ADC3 AWD3 Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:12 Reserved, must be kept at reset value DocID029587 Rev 3 1557/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active high 1: COMP2 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active high 1: COMP1 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDF1BK0E: BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer’s BRK input. dfsdm1_break[0] output is ‘ORed’ with the other BRK sources. 0: dfsdm1_break[0] input disabled 1: dfsdm1_break[0] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1558/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 359: TIM1/TIM8 ETR input circuitry and to Figure 380: Break and Break2 circuitry overview. 38.4.25 TIM1 Alternate function register 2 (TIM1_AF2) Address offset: 0x64 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BK2 CMP2 P BK2 CMP1 P BK2 INP BK2DF1 BK1E Res. Res. Res. Res. Res. BK2 CMP2E BK2 CMP1E BK2INE rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value Bit 11 BK2CMP2P: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BK2CMP1P: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BK2INP: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID029587 Rev 3 1559/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 8 BK2DF1BK1E: BRK2 dfsdm1_break[1] enable This bit enables the dfsdm1_break[1] for the timer’s BRK2 input. dfsdm1_break[1] output is ‘ORed’ with the other BRK2 sources. 0: dfsdm1_break[1] input disabled 1: dfsdm1_break[1] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BK2CMP2E: BRK2 COMP2 enable This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is ‘ORed’ with the other BRK2 sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BK2CMP1E: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is ‘ORed’ with the other BRK2 sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BK2INE: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 380: Break and Break2 circuitry overview. 38.4.26 TIM8 Alternate function option register 1 (TIM8_AF1) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. BK CMP2 P BKDF1 BK2E Res. Res. Res. Res. Res. BK CMP2E BK CMP1E BKINE rw rw rw ETRSEL[1:0] rw rw Res. rw BK CMP1 BKINP P rw rw rw Bits 31:18 Reserved, must be kept at reset value 1560/3178 DocID029587 Rev 3 17 16 ETRSEL[3:2] RM0433 Advanced-control timers (TIM1/TIM8) Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source. 0000: ETR input is connected to I/O 0001: COMP1 output 0010: COMP2 output 0011: ADC2 AWD1 0100: ADC2 AWD2 0101: ADC2 AWD3 0110: ADC3 AWD1 0111: ADC3 AWD2 1000: ADC3 AWD3 Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:12 Reserved, must be kept at reset value Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active high 1: COMP2 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active high 1: COMP1 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDF1BK2E: BRK dfsdm1_break[2] enable This bit enables the dfsdm1_break[2] for the timer’s BRK input. dfsdm1_break[2] output is ‘ORed’ with the other BRK sources. 0: dfsdm1_break[2] input disabled 1: dfsdm1_break[2] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value DocID029587 Rev 3 1561/3178 1571 Advanced-control timers (TIM1/TIM8) RM0433 Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 359: TIM1/TIM8 ETR input circuitry and to Figure 380: Break and Break2 circuitry overview. 38.4.27 TIM8 Alternate function option register 2 (TIM8_AF2) Address offset: 0x64 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BK2 CMP2 P BK2 CMP1 P BK2 INP BK2DF1 BK3E Res. Res. Res. Res. Res. BK2 CMP2E BK2 CMP1E BK2INE rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value Bit 11 BK2CMP2P: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1562/3178 DocID029587 Rev 3 RM0433 Advanced-control timers (TIM1/TIM8) Bit 10 BK2CMP1P: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BK2INP: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BK2DF1BK3E: BRK2 dfsdm1_break[3] enable This bit enables the dfsdm1_break[3] for the timer’s BRK2 input. dfsdm1_break[3] output is ‘ORed’ with the other BRK2 sources. 0: dfsdm1_break[3] input disabled 1: dfsdm1_break[3] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BK2CMP2E: BRK2 COMP2 enable This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is ‘ORed’ with the other BRK2 sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BK2CMP1E: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is ‘ORed’ with the other BRK2 sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BK2INE: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 380: Break and Break2 circuitry overview. DocID029587 Rev 3 1563/3178 1571 Advanced-control timers (TIM1/TIM8) 38.4.28 RM0433 TIM1 timer input selection register (TIM1_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 TI4SEL[3:0] 11 10 9 rw 22 21 20 Res. Res. Res. 7 6 5 4 Res. Res. Res. Res. 8 TI2SEL[3:0] rw 23 Res. rw 19 18 17 16 TI3SEL[3:0] 3 2 1 0 TI1SEL[3:0] rw rw rw rw 18 17 16 Bits 31:28 Reserved, must be kept at reset value Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input 0000: TIM1_CH4 input Others: Reserved Bits 23:20 Reserved, must be kept at reset value Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input 0000: TIM1_CH3 input Others: Reserved Bits 15:12 Reserved, must be kept at reset value Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input 0000: TIM1_CH2 input Others: Reserved Bits 7:4 Reserved, must be kept at reset value Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM1_CH1 input 0001: COMP1 output Others: Reserved 38.4.29 TIM8 timer input selection register (TIM8_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 TI4SEL[3:0] 11 10 9 rw 22 21 20 Res. Res. Res. Res. 8 TI2SEL[3:0] rw 23 rw 7 6 5 4 Res. Res. Res. Res. rw Bits 31:28 Reserved, must be kept at reset value Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input 0000: TIM8_CH4 input Others: Reserved 1564/3178 DocID029587 Rev 3 19 TI3SEL[3:0] 3 2 1 0 TI1SEL[3:0] rw rw rw RM0433 Advanced-control timers (TIM1/TIM8) Bits 23:20 Reserved, must be kept at reset value Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input 0000: TIM8_CH3 input Others: Reserved Bits 15:12 Reserved, must be kept at reset value Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input 0000: TIM8_CH2 input Others: Reserved Bits 7:4 Reserved, must be kept at reset value Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM8_CH1 input 0001: COMP2 output Others: Reserved DocID029587 Rev 3 1565/3178 1571 0x24 TIM1_CNT Reset value 0 1566/3178 0 DocID029587 Rev 3 0 0 0 0 IC2F[3:0] 0 0 OC4M [2:0] 0 0 IC4F[3:0] 0 0 0 IC2 PSC [1:0] 0 CC2 S [1:0] 0 0 0 0 0 0 0 0 0 0 0 IC4 PSC [1:0] CC4 S [1:0] 0 0 0 0 CC4 S [1:0] 0 0 UIE UIF 0 0 0 0 0 UG CC1IE CC1IF 0 CC1G CC2IE CC2IF 0 CC2G CC3IE TI1S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. UIFREMAP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARPE DIR OPM URS UDIS CEN 0 0 0 0 0 CCDS CCUS Res. CCPC 0 TS[2:0] 0 0 0 0 0 0 0 0 0 CC2 S [1:0] OC1M [2:0] 0 0 IC1F[3:0] 0 0 OC3M [2:0] 0 0 IC3F[3:0] Res. OIS1 MMS [2:0] OC1FE CC4IE CC3IF 0 CC3G COMIE 0 COM 0 CC4G ETF[3:0] MSM 0 0 OC1PE TIE 0 TG CC4IF BIE OIS2N OIS2 OIS3 OIS1N OIS3N 0 0 OC3FE 0 0 CMS [1:0] OC3PE 0 0 CC1E 0 COMIF Reset value TIF UDE 0 BIF 0 B2IF 0 CC1OF 0 CC2OF 0 Res. 0 Res. 0 CC3OF 0 Res. 0 CC4OF 0 Res. 0 SBIF 0 0 BG 0 0 0 B2G 0 0 0 OC1CE 0 0 Res. OIS4 Res. 0 OC3CE 0 CC1DE 0 CC2DE 0 Res. OIS5 Res. OIS6 0 CC1P 0 0 OC2FE 0 CC3DE 0 ETP S [1:0] 0 CC1NE 0 0 0 CC1NP 0 0 0 CC2E 0 CC3E 0 OC2M [2:0] OC2PE 0 CC4DE 0 COMDE ECE 0 TDE ETP 0 Res. Res. SMS[3] 0 Res. Res. Res. Res. 0 CC2P 0 CC2NP 0 Res. Res. Reset value OC4FE OC2CE CC5IF Res. Res. Res. Res. 0 OC4PE OC1M[3] CC6IF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CKD [1:0] CC2NE 0 CC3P 0 0 CC3NE Reset value CC3NP Reset value CC4E Res. Res. Res. 0 CC4P OC4CE 0 OC3M[3] Res. 0 Res. Res. Res. 0 Res. CC5E 0 Res. Res. Res. Res. Res. 0 Res. CC5P Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS [4:3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS2[3:0] Res. CC6E 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC6P Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. Res. TIM1_CCER Res. TIM1_CCMR2 Input Capture mode Res. TIM1_CCMR2 Output Compare mode Res. TIM1_CCMR1 Input Capture mode Res. TIM1_CCMR1 Output Compare mode Res. TIM1_EGR Res. 0x14 Res. TIM1_SR Res. 0x10 Res. TIM1_DIER Res. 0x20 TIM1_SMCR Res. 0x1C TIM1_CR2 Res. 0x04 Res. 0x18 TIM1_CR1 Res. 0x00 Res. 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 38.4.30 Res. 0x08 UIFCPY Advanced-control timers (TIM1/TIM8) RM0433 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 315. TIM1 register map and reset values 0 0 0 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 0 SMS[2:0] 0 0 0 CC1 S [1:0] 0 0 0 0 CC3 S [1:0] 0 IC3 PSC [1:0] CC3 S [1:0] 0x58 TIM1_CCR5 Reset value 0 0 0 OC6CE Res. OC5M[3] 0 Res. Res. Res. Res. Res. Res. Res. Res. OC6M[3] 0 0 0 0 Res. Res. Res. Res. Res. BKF[3:0] Reset value 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 OC6M [2:0] 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBL[4:0] 0 0 0 0 Res. 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Reset value 0 0 0 1 Res. 0 0 OSSI Reset value 0 BKE Res. Res. Res. 0 0 OSSR Res. Res. Res. Res. Reset value 0 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 LOC K [1:0] 0 0 DMAB[15:0] 0 0 0 0 OC5M [2:0] CCR5[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. Res. Res. Res. 0 0 1 0 Res. 0 Res. Res. Res. Res. Reset value 0 1 0 OC5FE 0 Res. Res. Res. Res. Res. 0 1 0 OC5PE BKP 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 1 0 Res. AOE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 OC5CE MOE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 Res. BK2E 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 OC6FE BK2P Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Reset value OC6PE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 BK2F[3:0] Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Reset value Res. Res. TIM1_CCMR3 Output Compare mode Res. TIM1_DMAR Res. 0x54 TIM1_DCR Res. 0x4C TIM1_BDTR Res. 0x48 GC5C1 0x44 TIM1_CCR4 Res. 0x40 TIM1_CCR3 Res. 0x3C TIM1_CCR2 Res. 0x38 TIM1_CCR1 Res. 0x34 TIM1_RCR Res. 0x30 TIM1_ARR Res. 0x2C Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM1_PSC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name Res. 0x28 GC5C2 Offset GC5C3 RM0433 Advanced-control timers (TIM1/TIM8) Table 315. TIM1 register map and reset values (continued) PSC[15:0] ARR[15:0] REP[15:0] CCR1[15:0] CCR2[15:0] CCR3[15:0] CCR4[15:0] DT[7:0] 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA[4:0] 0 0 1567/3178 1571 0x68 TIM1_TISEL Reset value 1568/3178 Res. TI4SEL[3:0] 0 0 0 0 Res. Res. Res. Res. 0 0 TI3SEL[3:0] 0 0 DocID029587 Rev 3 Res. Res. 0 0 0 TI2SEL[3:0] 0 0 0 0 0 BKCMP1E BKINE 0 0 1 BK2INE 0 BK2CMP1E 0 BKCMP2E 0 BK2CMP2E Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. 0 Res. Reset value BKINP 0 BKDF1BK0E 0 BK2DF1BK1E 0 BKCMP1P 0 BK2INP 0 BK2CMP1P 0 BKCMP2P 0 BK2CMP2P 0 Res. Res. 0 0 Res. 0 0 Res. Res ETRSEL [3:0] Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. TIM1_AF2 Res. 0x64 Res. 0x60 TIM1_AF1 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM1_CCR6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name Res. 0x5C Res. Offset Res. Advanced-control timers (TIM1/TIM8) RM0433 Table 315. TIM1 register map and reset values (continued) CCR6[15:0] 0 0 1 TI1SEL[3:0] 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 0 0 0x24 TIM8_CNT Reset value 0 0 DocID029587 Rev 3 0 0 0 IC2F[3:0] 0 0 OC4M [2:0] 0 0 IC4F[3:0] 0 0 0 0 IC2 PSC [1:0] CC2 S [1:0] 0 0 0 0 0 0 0 0 0 0 CC4 S [1:0] 0 IC4 PSC [1:0] CC4 S [1:0] 0 0 0 0 0 0 UIE UIF 0 0 0 0 0 UG CC1IE CC1IF 0 CC1G CC2IE CC2IF 0 CC2G CC3IE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. UIFREMAP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARPE DIR OPM URS UDIS CEN 0 0 0 0 0 CCDS CCUS Res. CCPC 0 TS[2:0] 0 0 0 0 0 0 0 0 0 CC2 S [1:0] OC1M [2:0] 0 0 IC1F[3:0] 0 0 OC3M [2:0] 0 0 IC3F[3:0] Res. TI1S MMS [2:0] OC1FE CC4IE CC3IF 0 CC3G OIS1 OIS2N 0 0 OC1PE COMIE 0 COM 0 CC4G CC4IF TIE 0 TG ETF[3:0] MSM OIS3 OIS2 OIS3N OIS1N OIS4 Res. 0 0 OC3FE 0 0 CC1E 0 0 0 CC1P 0 COMIF Reset value TIF BIE 0 BIF 0 B2IF 0 CC1OF 0 CC2OF 0 Res. 0 Res. 0 CC3OF 0 Res. 0 CC4OF 0 Res. 0 SBIF 0 Res. UDE 0 0 0 BG 0 0 0 B2G 0 0 0 OC1CE 0 CC1DE 0 CC2DE 0 ETP S [1:0] 0 CMS [1:0] OC3PE 0 OC2FE 0 CC3DE 0 Res. OIS5 Res. OIS6 0 CC1NE 0 0 0 CC1NP 0 0 0 OC3CE 0 0 0 CC2E 0 CC3E 0 OC2M [2:0] OC2PE 0 CC4DE 0 COMDE ECE 0 TDE ETP 0 Res. Res. SMS[3] 0 Res. Res. Res. Res. 0 CC2P 0 CC2NP 0 Res. Res. Reset value OC4FE OC2CE CC5IF Res. Res. Res. Res. 0 OC4PE OC1M[3] CC6IF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CKD [1:0] CC2NE 0 CC3P 0 0 CC3NE Reset value CC3NP Reset value CC4E Res. Res. Res. 0 CC4P OC4CE 0 OC3M[3] Res. 0 Res. Res. Res. 0 Res. CC5E 0 Res. Res. Res. Res. Res. 0 Res. CC5P Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS [4:3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS2[3:0] Res. CC6E 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC6P Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. TIM8_CCER Res. 0x20 Res. TIM8_CCMR2 Input Capture mode Res. 0x1C Res. TIM8_CCMR2 Output Compare mode Res. TIM8_CCMR1 Input Capture mode Res. TIM8_CCMR1 Output Compare mode Res. 0x18 TIM8_EGR Res. 0x14 TIM8_SR Res. 0x10 TIM8_DIER Res. 0x0C TIM8_SMCR Res. 0x08 TIM8_CR2 Res. 0x04 TIM8_CR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 38.4.31 UIFCPY RM0433 Advanced-control timers (TIM1/TIM8) TIM8 register map TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 316. TIM8 register map and reset values 0 0 0 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 0 SMS[2:0] 0 0 0 CC1 S [1:0] 0 0 0 CC3 S [1:0] 0 IC3 PSC [1:0] CC3 S [1:0] 0 1569/3178 1571 0x58 TIM8_CCR5 Reset value 0 0 0 1570/3178 OC6CE Res. OC5M[3] 0 Res. Res. Res. Res. Res. Res. Res. Res. OC6M[3] 0 0 0 0 Res. Res. Res. Res. Res. BKF[3:0] Reset value 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 OC6M [2:0] 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBL[4:0] 0 0 0 0 Res. 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Reset value 0 0 0 1 Res. 0 0 OSSI Reset value 0 BKE Res. Res. Res. 0 0 OSSR Res. Res. Res. Res. Reset value 0 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 LOC K [1:0] 0 0 DMAB[15:0] 0 0 0 0 OC5M [2:0] CCR5[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. Res. Res. Res. 0 0 1 0 Res. 0 Res. Res. Res. Res. Reset value 0 1 0 OC5FE 0 Res. Res. Res. Res. Res. 0 1 0 OC5PE BKP 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 1 0 Res. AOE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 OC5CE MOE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 Res. BK2E 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 OC6FE BK2P Res. 0 Res. Res. Res. Res. Res. Res. Reset value OC6PE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 BK2F[3:0] Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. TIM8_CCMR3 Output Compare mode Res. TIM8_DMAR Res. TIM8_DCR Res. 0x48 Res. TIM8_BDTR Res. TIM8_CCR4 Res. TIM8_CCR3 Res. 0x54 TIM8_CCR2 Res. 0x4C GC5C1 0x44 TIMx_CCR1 Res. 0x40 TIM8_RCR Res. 0x30 Res. 0x3C TIM8_ARR Res. 0x2C Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM8_PSC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name Res. 0x28 Res. Offset Res. 0x38 GC5C2 0x34 GC5C3 Advanced-control timers (TIM1/TIM8) RM0433 Table 316. TIM8 register map and reset values (continued) PSC[15:0] ARR[15:0] REP[15:0] CCR1[15:0] CCR2[15:0] CCR3[15:0] CCR4[15:0] DT[7:0] 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA[4:0] 0 0 0x68 TIM8_TISEL Reset value Res. TI4SEL[3:0] 0 0 0 0 Res. Res. Res. Res. 0 0 TI3SEL[3:0] 0 0 DocID029587 Rev 3 Res. Res. 0 0 0 TI2SEL[3:0] 0 0 0 0 0 BKCMP1E BKINE 0 0 1 BK2INE 0 BK2CMP1E 0 BKCMP2E 0 BK2CMP2E Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. 0 Res. Reset value BKINP 0 BKDF1BK2E 0 BK2DF1BK3E 0 BKCMP1P 0 BK2INP 0 BK2CMP1P 0 BKCMP2P 0 BK2CMP2P 0 Res. Res. 0 0 Res. 0 0 Res. Res ETRSEL [3:0] Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. TIM8_AF2 Res. 0x64 Res. 0x60 TIM8_AF1 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM8_CCR6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name Res. 0x5C Res. Offset Res. RM0433 Advanced-control timers (TIM1/TIM8) Table 316. TIM8 register map and reset values (continued) CCR6[15:0] 0 0 1 TI1SEL[3:0] 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 1571/3178 1571 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.1 TIM2/TIM3/TIM4/TIM5 introduction RM0433 The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 39.3.19: Timer synchronization. 39.2 TIM2/TIM3/TIM4/TIM5 main features General-purpose TIMx timer features include: 1572/3178 • 16-bit (TIM3, TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535. • Up to 4 independent channels for: – Input capture – Output compare – PWM generation (Edge- and Center-aligned modes) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare • Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 397. General-purpose timer block diagram ,QWHUQDOFORFN &.B,17 7,0[&/.IURP5&& (75) (75 7,0[B(75 3RODULW\VHOHFWLRQ HGJH GHWHFWRU SUHVFDOHU ,75>@ (753 7ULJJHU FRQWUROOHU 75*2 ,QSXWILOWHU WRRWKHUWLPHUV WR'$&$'& 7*, ,75 75& 75*, 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)B(' (QFRGHU LQWHUIDFH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 6WRSFOHDURUXSGRZQ &.B36& &.B&17 36& SUHVFDOHU &&, 8 ;25 7,>@ 7,0[B&+ 7,>@ 7,>@ 7,0[B&+ 7,>@ 7,>@ 7,0[B&+ 7,>@ 7,>@ 7,0[B&+ 7,>@ 7, ,QSXW 7,)3 ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QSXW 7,)3 7, ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QSXW 7,)3 7, ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QSXW 7,)3 7, ILOWHU 7,)3 HGJH GHWHFWRU 75& ,& 3UHVFDOHU ,&36 &&, ,& 3UHVFDOHU ,& 3UHVFDOHU &&, &DSWXUH&RPSDUHUHJLVWHU &DSWXUH&RPSDUHUHJLVWHU 3UHVFDOHU 7,0[B&+ 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ &&, 8 ,&36 2XWSXW 2& FRQWURO &&, 8 &&, ,& 2&5() &&, 8 ,&36 8 &17FRXQWHU &DSWXUH&RPSDUHUHJLVWHU ,&36 &&, 8, &DSWXUH&RPSDUHUHJLVWHU 2&5() (75) 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 06Y 9 DocID029587 Rev 3 1573/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.3 TIM2/TIM3/TIM4/TIM5 functional description 39.3.1 Time-base unit RM0433 The main block of the programmable timer is a 16-bit/32-bit counter with its related autoreload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 398 and Figure 399 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 1574/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 398. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 399. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID029587 Rev 3 1575/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.3.2 RM0433 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 400. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1576/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 401. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 402. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1577/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Figure 403. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 404. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 1578/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 405. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 069 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. DocID029587 Rev 3 1579/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 406. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ FQWBXGI 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 407. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1580/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 408. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 409. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1581/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Figure 410. Counter timing diagram, Update event when repetition counter is not used &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or 1582/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 411. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 1. Here, center-aligned mode 1 is used (for more details refer to Section 39.4.1: TIMx control register 1 (TIMx_CR1) on page 1616). DocID029587 Rev 3 1583/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Figure 412. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 413. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 1RWH +HUHFHQWHUBDOLJQHGPRGHRULVXSGDWHGZLWKDQ8,)RQRYHUIORZ 06 9 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. 1584/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 414. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 415. Counter timing diagram, Update event with ARPE=1 (counter underflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH UHJLVWHU )' 06 9 DocID029587 Rev 3 1585/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Figure 416. Counter timing diagram, Update event with ARPE=1 (counter overflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH )' UHJLVWHU 06 9 39.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 13 to act as a prescaler for Timer 2. Refer to : Using one timer as prescaler for another timer on page 1611 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 417 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 1586/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 417. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 418. TI2 external clock connection example 7,0[B60&5 76> @ RU 7,) 7,) 7,0[B&+ 7,>@ 7,>@ 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ ,75[ [[ 7,B(' 7,)3 7,)3 (75) ,&)> @ &&3 7,0[B&&05 7,0[B&&(5 RU RU 75*, (QFRGHU PRGH ([WHUQDOFORFN PRGH (75) ([WHUQDOFORFN PRGH &.B,17 LQWHUQDOFORFN ,QWHUQDOFORFN PRGH (&( &.B36& 606> @ 7,0[B60&5 06Y9 1. Codes ranging from 01000 to 11111: ITRy. For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: DocID029587 Rev 3 1587/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Note: RM0433 1. Select the proper TI1x source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. 2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. 3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. 4. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the TIMx_CCER register. 5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 6. Select TI2 as the input source by writing TS=00110 in the TIMx_SMCR register. 7. Enable the counter by writing CEN=1 in the TIMx_CR1 register. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 419. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 420 gives an overview of the external trigger input block. 1588/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 420. External trigger input block RU 7,) RU 7,) RU (QFRGHU (75LQSXWIURP$)FRQWUROOHU PRGH 75*, (75 (75LQSXWVIURP RQFKLSVRXUFHV ([WHUQDOFORFN PRGH 'LYLGHU (753 I'76 )LOWHU GRZQFRXQWHU (75) PRGH &.B,17 (73 7,0[B60&5 (736> @ 7,0[B60&5 (7)> @ &.B36& ([WHUQDOFORFN ,QWHUQDOFORFN PRGH LQWHUQDOFORFN 7,0[B60&5 (756(/> @ (&( 7,0[B$) 606> @ 7,0[B60&5 06Y 9 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. Select the proper ETR source (internal or external) with the ETRSEL[3:0] bits in the TIMx_AF1 register. 2. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 3. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 4. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 5. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 421. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 DocID029587 Rev 3 1589/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.3.4 RM0433 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 422. Capture/compare channel (example: channel 1 input stage) 7,0[B&+ 7,)B(' 7,>@ 7RWKHVODYHPRGHFRQWUROOHU 7,>@ )LOWHU GRZQFRXQWHU I'76 7,)B5LVLQJ 7,) (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 ,&)> @ 7,0[B&&05 &&3&&13 75& 7,0[B&&(5 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& 'LYLGHU ,&36 IURPVODYHPRGH FRQWUROOHU &&6> @ ,&36> @ 7,0[B&&05 &&( 7,0[B&&(5 06Y9 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. 1590/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 423. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ZULWHBLQBSURJUHVV 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH ,QSXW PRGH 2XWSXW PRGH &&6>@ &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU 8(9 &RPSDUDWRU &DSWXUH ,&36 ZULWH&&5/ &&( &17!&&5 &RXQWHU IURPWLPH EDVHXQLW 2&3( 7,0[B&&05 &17 &&5 &&* 7,0[B(*5 069 Figure 424. Output stage of capture/compare channel (channel 1) 7RWKHPDVWHU PRGHFRQWUROOHU (75) 2&5()& 2&5() µ¶ &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&5() 2XWSXW VHOHFWRU &&( 7,0[B&&(5 2&&( 2XWSXW HQDEOH FLUFXLW &&3 7,0[B&&(5 &&( 7,0[B&&(5 02( 2&0> @ 7,0[B&&05 2& 266, 7,0[B%'75 2,6 7,0[B&5 06Y 9 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. DocID029587 Rev 3 1591/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.3.5 RM0433 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. 2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 3. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 4. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case). 5. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register). 6. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 7. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: 1592/3178 IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID029587 Rev 3 RM0433 39.3.6 General-purpose timers (TIM2/TIM3/TIM4/TIM5) PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register. Figure 425. PWM input mode timing 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. DocID029587 Rev 3 1593/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.3.7 RM0433 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 39.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on ocxref and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure 1594/3178 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated. 4. Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 426. Figure 426. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 06 9 39.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be DocID029587 Rev 3 1595/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes (OCxM=‘110 or ‘111). This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 1576. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at 100%. PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 1582. Figure 428 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. DocID029587 Rev 3 1597/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Figure 428. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: • 1598/3178 – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. DocID029587 Rev 3 RM0433 39.3.10 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle: • OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 • OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Asymmetric PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’ (Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. When a given channel is used as asymmetric PWM channel, its secondary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 2. Figure 429 shows an example of signals that can be generated using Asymmetric PWM mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Figure 429. Generation of 2 phase-shifted PWM signals with 50% duty cycle &RXQWHUUHJLVWHU &&5 &&5 &&5 &&5 2&5()& 2&5()& 069 39.3.11 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: – OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 – OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. DocID029587 Rev 3 1599/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 430 shows an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration: • Channel 1 is configured in Combined PWM mode 2, • Channel 2 is configured in PWM mode 1, • Channel 3 is configured in Combined PWM mode 2, • Channel 4 is configured in PWM mode 1 Figure 430. Combined PWM mode on channels 1 and 3 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 06 9 39.3.12 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs. This function can only be used in Output compare and PWM modes. It does not work in Forced mode. The ocref_clr_int is connected to the ETRF signal (ETR after filtering). 1600/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs. This function can be used only in the output compare and PWM modes. It does not work in forced mode. For example, the OCxREF signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows: 1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. 2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs. Figure 431 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. Figure 431. Clearing TIMx OCxREF &&5[ &RXQWHU &17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ RFUHIBFOUBLQW EHFRPHVKLJK RFUHIBFOUBLQW VWLOOKLJK 069 Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow. DocID029587 Rev 3 1601/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.3.13 RM0433 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • CNT TIMx_CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT TIMx_CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. DocID029587 Rev 3 1627/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). Input capture mode Bits 31:16 Reserved, always read as 0. Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 1628/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 39.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 Res. OC4M [3] 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. OC3M [3] Res. Res. rw 15 14 OC4CE 13 12 OC4M[2:0] rw rw 10 OC4PE OC4FE IC4F[3:0] rw 11 IC4PSC[1:0] rw rw rw 9 8 CC4S[1:0] rw rw rw 7 6 OC3CE 5 4 OC3M[2:0] rw DocID029587 Rev 3 rw 2 OC3PE OC3FE IC3F[3:0] rw 3 IC3PSC[1:0] rw rw rw 1 0 CC3S[1:0] rw rw 1629/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Output compare mode Bits 31:25 Reserved, always read as 0. Bit 24 OC4M[3]: Output Compare 2 mode - bit 3 Bits 23:17 Reserved, always read as 0. Bit 16 OC3M[3]: Output Compare 1 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). Input capture mode Bits 31:16 Reserved, always read as 0. Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 1630/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 39.4.9 TIMx capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC4NP Res. CC4P CC4E CC3NP Res. CC3P CC3E CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output Polarity. Refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable. refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 output Polarity. Refer to CC1NP description Bit 10 Reserved, must be kept at reset value. Bit 9 CC3P: Capture/Compare 3 output Polarity. Refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable. Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. DocID029587 Rev 3 1631/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled Table 319. Output control bit for standard OCx channels CCxE bit OCx output state 0 Output Disabled (OCx=0, OCx_EN=0) 1 OCx=OCxREF + Polarity, OCx_EN=1 Note: The state of the external IO pins connected to the standard OCx channels depends on the OCx channel state and the GPIO and AFIO registers. 39.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 31 30 29 28 27 26 25 CNT[31] or UIFCPY 24 23 22 21 20 19 18 17 16 CNT[30:16] (depending on timers) rw or r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw CNT[15:0] 1632/3178 rw DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 31 Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 CNT[31]: Most significant bit of counter value (on TIM2 and TIM5) Reserved on other timers If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 and TIM5) Bits 15:0 CNT[15:0]: Least significant part of counter value 39.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 39.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ARR[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ARR[15:0] rw Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5) Bits 15:0 ARR[15:0]: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 39.3.1: Time-base unit on page 1574 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID029587 Rev 3 1633/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.4.13 RM0433 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR1[31:16] (depending on timers) rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR1[15:0] rw/r Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5) Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. 39.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR2[31:16] (depending on timers) rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR2[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5) Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. 1634/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR3[31:16] (depending on timers) rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR3[15:0] rw/r Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5) Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. 39.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r 15 14 13 12 11 10 9 8 7 22 21 20 19 18 17 16 rw/r rw/r rw/r rw/r rw/r rw/r rw/r 6 5 4 3 2 1 0 rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR4[31:16] (depending on timers) CCR4[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5) Bits 15:0 CCR4[15:0]: Low Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. DocID029587 Rev 3 1635/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.4.17 RM0433 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res. Res. Res. rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1 00001: TIMx_CR2 00010: TIMx_SMCR ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 39.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 1636/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.4.19 TIM2 alternate function option register 1 (TIM2_AF1) Address offset: 0x60 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[1:0] rw 17 16 ETRSEL[3:2] rw Bits 31:18 Reserved, must be kept at reset value. Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source. 0000: ETR input is connected to I/O 0001: COMP1 output 0010: COMP2 output 0011: LSE 0100: SAI1 FS_A 0101: SAI1 FS_B Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:0 Reserved, must be kept at reset value. 39.4.20 TIM3 alternate function option register 1 (TIM3_AF1) Address offset: 0x60 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] rw ETRSEL[1:0] rw 16 rw rw Bits 31:18 Reserved, must be kept at reset value. Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source. 0000: ETR input is connected to I/O 0001: COMP1 output Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:0 Reserved, must be kept at reset value. DocID029587 Rev 3 1637/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.4.21 RM0433 TIM5 alternate function option register 1 (TIM5_AF1) Address offset: 0x60 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[1:0] rw 17 16 ETRSEL[3:2] rw Bits 31:18 Reserved, must be kept at reset value. Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source. 0000: ETR input is connected to I/O 0001: SAI2 FS_A connected to ETR input 0010: SAI2 FS_B connected to ETR input Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:0 Reserved, must be kept at reset value. 39.4.22 TIM2 timer input selection register (TIM2_TISEL) Address offset: 0x68 Reset value: 0x0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 TI4SEL[3:0] rw rw rw rw 11 10 9 8 TI2SEL[3:0] rw rw rw 23 22 21 20 Res. Res. Res. Res. 7 6 5 4 Res. Res. Res. Res. rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 TI4SEL[3:0]: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. 0000: TIM2_CH4 input 0001: COMP1 output 0010: COMP2 output 0011: COMP1 output OR COMP2 output Others: Reserved Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 TI3SEL[3:0]: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. 0000: TIM2_CH3 input Others: Reserved Bits 15:12 Reserved, must be kept at reset value. 1638/3178 DocID029587 Rev 3 19 18 17 16 TI3SEL[3:0] rw rw rw rw 3 2 1 0 TI1SEL[3:0] rw rw rw rw RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. 0000: TIM2_CH2 input Others: Reserved Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. 0000: TIM2_CH1 input Others: Reserved 39.4.23 TIM3 timer input selection register (TIM3_TISEL) Address offset: 0x68 Reset value: 0x0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 TI4SEL[3:0] rw rw rw rw 11 10 9 8 TI2SEL[3:0] rw rw rw 23 22 21 20 Res. Res. Res. Res. 7 6 5 4 Res. Res. Res. Res. rw 19 18 17 16 TI3SEL[3:0] rw rw rw rw 3 2 1 0 TI1SEL[3:0] rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 TI4SEL[3:0]: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. 0000: TIM3_CH4 input Others: Reserved Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 TI3SEL[3:0]: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. 0000: TIM3_CH3 input Others: Reserved Bits 15:12 Reserved, must be kept at reset value. Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. 0000: TIM3_CH2 input Others: Reserved Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. 0000: TIM3_CH1 input 0001: COMP1 output 0010: COMP2 output 0011: COMP1 output OR COMP2 output Others: Reserved DocID029587 Rev 3 1639/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 39.4.24 RM0433 TIM5 timer input selection register (TIM5_TISEL) Address offset: 0x68 Reset value: 0x0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 TI4SEL[3:0] rw rw rw rw 11 10 9 8 TI2SEL[3:0] rw rw rw 23 22 21 20 Res. Res. Res. Res. 7 6 5 4 Res. Res. Res. Res. rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 TI4SEL[3:0]: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. 0000: TIM5_CH4 input Others: Reserved Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 TI3SEL[3:0]: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. 0000: TIM5_CH3 input Others: Reserved Bits 15:12 Reserved, must be kept at reset value. Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. 0000: TIM5_CH2 input Others: Reserved Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. 0000: TIM5_CH1 input 0001: fdcan1_tmp 0010: fdcan1_rtp Others: Reserved 1640/3178 DocID029587 Rev 3 19 18 17 16 TI3SEL[3:0] rw rw rw rw 3 2 1 0 TI1SEL[3:0] rw rw rw rw 0x20 TIMx_CCER Reset value DocID029587 Rev 3 IC4F[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 OC4M [2:0] CC4S [1:0] 0 0 0 0 0 0 0 Reset value 0 OC1M [2:0] 0 0 0 0 0 IC4 PSC [1:0] CC4S [1:0] 0 0 0 0 0 0 0 0 0 UG 0 CC1G UIE UIF 0 CC2G CC1IE CC1IF 0 0 0 0 0 0 OC1FE CC2IE CC2IF 0 CC3G CC3IE CC3IF 0 OC1PE 0 0 0 0 0 0 Res. CC4IE 0 Res. CC4IF 0 Res. DIR OPM URS UDIS CEN 0 0 0 0 MMS[2:0] CCDS Res. Res. Res. 0 0 0 0 0 0 TS[2:0] 0 IC1F[3:0] 0 0 OC3M [2:0] 0 IC3F[3:0] Res. 0 TI1S ARPE Res. Res. UIFREMAP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CC4G TIE 0 TIF 0 TG MSM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 IC1 PSC [1:0] CC1S [1:0] 0 0 0 OC3FE 0 CMS [1:0] OC3PE 0 Res. Res. UDE 0 Res. CC1OF Res. CC2OF 0 Res. 0 Res. 0 CC3OF 0 Res. 0 CC4OF 0 Res. 0 0 Res. 0 IC3 PSC [1:0] CC3S [1:0] 0 0 0 0 0 CC1E CC2S [1:0] 0 CC2S [1:0] OC1CE 0 CC1DE 0 CC2DE 0 ETF[3:0] Res. 0 IC2 PSC [1:0] 0 OC2FE 0 CC3DE 0 CC4DE 0 COMDE 0 Res. ECE 0 Res. Reset value CC1P 0 0 CC1NP 0 0 CC2E IC2F[3:0] OC3CE 0 Res. ETP 0 TDE SMS[3] Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETPS [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CKD [1:0] CC2P 0 0 0 Res. 0 OC2M [2:0] OC2PE 0 CC3E 0 Res. Res. Res. Res. Res. Reset value CC2NP 0 OC4FE OC2CE 0 OC4PE OC1M[3] Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 CC3NP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC3P 0 CC4E 0 0 CC4P Reset value Res. O24CE Reset value CC4NP Res. Res. OC3M[3] 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS [4:3] Res. Res. Res. Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. TIMx_CCMR2 Input Capture mode Res. 0x1C Res. TIMx_CCMR2 Output Compare mode Res. TIMx_CCMR1 Input Capture mode Res. TIMx_CCMR1 Output Compare mode Res. 0x18 TIMx_EGR Res. 0x14 TIMx_SR Res. 0x10 TIMx_DIER Res. 0x0C TIMx_SMCR Res. 0x08 TIMx_CR2 Res. 0x04 TIMx_CR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 39.4.25 Res. RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) TIMx register map TIMx registers are mapped as described in the table below: Table 320. TIM2/TIM3/TIM4/TIM5 register map and reset values SMS[2:0] 0 0 0 CC1S [1:0] 0 0 0 0 CC3S [1:0] 0 0 0 0 0 0 0 0 0 0 1641/3178 1643 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0433 CNT[31] or UIFCPY Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_PSC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[30:16] (TIM2 and TIM5 only, reserved on the other timers) Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[15:0] 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR4[15:0] Res. 0 0 CCR3[15:0] CCR4[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR4 0 CCR2[15:0] CCR3[31:16] (TIM2 and TIM5 only, reserved on the other timers) 0 0 0 0 0 0 0 0 0 0 Res. 0 Reset value 1642/3178 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 ETRSEL [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM5_AF1 0x60 0 Res. Reset value 0 ETRSEL [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM3_AF1 0x60 0 Res. Reset value 0 ETRSEL [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM2_AF1 0 DBA[4:0] DMAB[15:0] 0 Res. Reset value 0x60 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DMAR 0 Res. Reset value DBL[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DCR Res. Reserved Res. 0x44 0x4C 0 PSC[15:0] CCR2[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR3 Reset value 0x48 0 Res. 0 TIMx_CCR2 Reset value 0x40 0 CCR1[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR1 Reset value 0x3C 0 Reserved Reset value 0x38 0 Res. 0x30 0x34 0 ARR[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_ARR Reset value 0 0 Res. 0x2C CNT[15:0] Res. 0x28 TIMx_CNT Res. 0x24 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 320. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued) 0 RM0433 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Reset value 0 0 0 0 0 0 0 TI2SEL[3:0] 0 0 0 Res. Res. Res. Res. Res. 0 0 0 0 0 TI1SEL[3:0] 0 Res. 0 Res. 0 Res. TI2SEL[3:0] TI1SEL[3:0] 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. TI3SEL[3:0] 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. TI3SEL[3:0] TI2SEL[3:0] 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. TI4SEL[3:0] 0 Res. 0 0 Res. 0 Res. 0 TI3SEL[3:0] 0 Res. 0 Res. Res. Res. TIM5_TISEL Res. 0x68 0 TI4SEL[3:0] 0 Res. Reset value 0 Res. Res. Res. TIM3_TISEL Res. 0x68 0 Res. Reset value TI4SEL[3:0] Res. Res. Res. TIM2_TISEL Res. 0x68 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 320. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued) 0 0 0 TI1SEL[3:0] 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 1643/3178 1643 General-purpose timers (TIM12/TIM13/TIM14) 40 General-purpose timers (TIM12/TIM13/TIM14) 40.1 TIM12/TIM13/TIM14 introduction RM0433 The TIM12/TIM13/TIM14 general-purpose timers consist in a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The TIM12/TIM13/TIM14 timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 40.3.17: Timer synchronization (TIM12). 40.2 TIM12/TIM13/TIM14 main features 40.2.1 TIM12 main features The features of the TIM12 general-purpose timer include: 1644/3178 • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”) • Up to 2 independent channels for: – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers together • Interrupt generation on the following events: – Update: counter overflow, counter initialization (by software or internal trigger) – Trigger event (counter start, stop, initialization or count by internal trigger) – Input capture – Output compare DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Figure 446. General-purpose timer block diagram (TIM12) ,QWHUQDOFORFN &.B,17 ,75 ,75 ,75 ,75 7ULJJHU FRQWUROOHU 7*, ,75 75& 7,)B(' 75*, 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 6WRS&OHDU 8, 8 36& &.B&17 &17FRXQWHU SUHVFDOHU &&, 8 &&, &DSWXUH&RPSDUH 2&5() ,& 3UHVFDOHU ,&36 UHJLVWHU &.B36& 7,>@ 7,0[B&+ 7,>@ 7,>@ 7,0[B&+ 7,>@ 7,)3 ,QSXWILOWHU 7,)3 HGJHGHWHFWRU 75& &&, 7,)3 ,QSXWILOWHU 7,)3 HGJHGHWHFWRU 75& ,& 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ &&, 8 3UHVFDOHU ,&36 2XWSXW 2& FRQWURO &DSWXUH&RPSDUH UHJLVWHU 2&5() 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW 40.2.2 06Y 9 TIM13/TIM14 main features The features of general-purpose timers TIM13/TIM14 include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”) • independent channel for: • – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output Interrupt generation on the following events: – Update: counter overflow, counter initialization (by software) – Input capture – Output compare DocID029587 Rev 3 1645/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 447. General-purpose timer block diagram (TIM13/TIM14) ,QWHUQDOFORFN &.B,17 8 7ULJJHU &RQWUROOHU (QDEOH FRXQWHU $XWRUHORDGUHJLVWHU 8, 6WRSFOHDU 8 &.B36& 7,>@ 7,0[B&+ 7,>@ 1RWHV 5HJ ,QSXW 7,)3 ILOWHU HGJH VHOHFWRU 36& &.B&17 &17FRXQWHU SUHVFDOHU &, 8 ,& &DSWXUHFRPSDUH 3UHVFDOHU ,&36 UHJLVWHU &&, 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 1646/3178 06Y 9 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) 40.3 TIM12/TIM13/TIM14 functional description 40.3.1 Time-base unit The main block of the timer is a 16-bit up-counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in details for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 448 and Figure 449 give some examples of the counter behavior when the prescaler ratio is changed on the fly. DocID029587 Rev 3 1647/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 448. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 449. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 1648/3178 DocID029587 Rev 3 RM0433 40.3.2 General-purpose timers (TIM12/TIM13/TIM14) Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM12) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 450. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1649/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 451. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 452. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1650/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Figure 453. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 454. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 DocID029587 Rev 3 1651/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 455. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 40.3.3 069 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM12): connecting the trigger output from another timer. For instance, another timer can be configured as a prescaler for TIM12. Refer to Section : Using one timer as prescaler for another timer for more details. Internal clock source (CK_INT) The internal clock source is the default clock source for TIM13/TIM14. For TIM12, the internal clock source is selected when the slave mode controller is disabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software (except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is clocked by the internal clock CK_INT. Figure 456 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 1652/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Figure 456. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 UFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 (TIM12) This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 457. TI2 external clock connection example 7,0[B60&5 76> @ RU ,75[ 7,B(' 7,0[B&+ 7,)3 7,>@ 7,>@ 7,)B5LVLQJ )LOWHU (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,) 7,) [[ 75*, &&3 7,0[B&&05 7,0[B&&(5 (QFRGHU PRGH ([WHUQDOFORFN PRGH &.B36& &.B,17 ,&)> @ RU RU LQWHUQDOFORFN ,QWHUQDOFORFN PR GH 606> @ 7,0[B60&5 06Y 9 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: DocID029587 Rev 3 1653/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) Note: RM0433 1. Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. 2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=’0000’). 4. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 5. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR register. 6. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register. 7. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 458. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 40.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 459 to Figure 461 give an overview of one capture/compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 1654/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Figure 459. Capture/compare channel (example: channel 1 input stage 7,)B(' 7,>@ 7,0[B&+ 7RWKHVODYHPRGHFRQWUROOHU 7,>@ I'76 )LOWHU GRZQFRXQWHU 7,) 7,)B5LVLQJ (GJH GHWHFWRU 7,)3 7,)B)DOOLQJ 7,)3 ,&)> @ &&3&&13 75& 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& 'LYLGHU ,&36 IURPVODYHPRGH FRQWUROOHU &&6> @ ,&36> @ 7,0[B&&05 &&( 7,0[B&&(5 06Y 9 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 460. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5/ UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ 5HDG&&5+ 6 KLJK LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 7,0B(*5 06 9 DocID029587 Rev 3 1655/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 461. Output stage of capture/compare channel (channel 1) 7RWKHPDVWHUPRGH FRQWUROOHU 2&5() &17!&&5 &17 &&5 2&5()& µ¶ 2XWSXW PRGH FRQWUROOHU 2XWSXW VHOHFWRU 2&5() 2&&( 2XWSXW HQDEOH FLUFXLW &&( &&3 &&( 7,0B&&(5 7,0B&&(5 7,0B&&(5 2& 2&0> @ 7,0B&&05 06Y9 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 40.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1656/3178 1. Select the proper TI1[x] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. 2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, the channel is configured in input mode and the TIMx_CCR1 register becomes readonly. 3. Program the input filter duration you need with respect to the signal you connect to the timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) new level have been detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the TIMx_CCMR1 register. 4. Select the edge of the active transition on the TI1 channel by programming CC1P and CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case). 5. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 6. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 7. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 40.3.6 PWM input mode (only for TIM12) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): DocID029587 Rev 3 1657/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 1. Select the proper TI1[x] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. 2. Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). 3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). 4. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 register (TI1 selected). 5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the CC2P and CC2NP bits to ‘11’ (active on falling edge). 6. Select the valid trigger input: write the TS bits to ‘00101’ in the TIMx_SMCR register (TI1FP1 selected). 7. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the TIMx_SMCR register. 8. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 462. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH SHULRG PHDVXUHPHQW ,&FDSWXUH SXOVHZLGWK PHDVXUPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DLF 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 40.3.7 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write ‘0101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=’0’ (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to ‘0100’ in the TIMx_CCMRx register. 1658/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below. 40.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: 1. Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCxM=’0000’), be set active (OCxM=’0001’), be set inactive (OCxM=’0010’) or can toggle (OCxM=’0011’) on match. 2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). 3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: 5. – Write OCxM = ‘0011’ to toggle OCx output pin when CNT matches CCRx – Write OCxPE = ‘0’ to disable preload register – Write CCxP = ‘0’ to select active high polarity – Write CCxE = ‘1’ to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 463. DocID029587 Rev 3 1659/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 463. Output compare mode, toggle on OC1. :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 06 9 40.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. The OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CNT ≤ TIMx_CCRx. The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 464 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8. 1660/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Figure 464. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 06 9 40.3.10 Combined PWM mode (TIM12 only) Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: • OC1REFC (or OC2REFC) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. When a given channel is used as a combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 465 represents an example of signals that can be generated using combined PWM mode, obtained with the following configuration: • Channel 1 is configured in Combined PWM mode 2, • Channel 2 is configured in PWM mode 1, DocID029587 Rev 3 1661/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 465. Combined PWM mode on channel 1 and 2 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 06 9 40.3.11 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be as follows: CNT < CCRx ≤ ARR (in particular, 0 < CCRx) 1662/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Figure 466. Example of one pulse mode. 7, 2&5() 2& &RXQWHU 7,0B$55 7,0B&&5 W'(/$< W38/6( W 06 9 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Use TI2FP2 as trigger 1: 1. Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. 2. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 3. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’00110’ in the TIMx_SMCR register. 5. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=’0111’ in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. DocID029587 Rev 3 1663/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 40.3.12 Retriggerable one pulse mode (OPM) (TIM12 only) This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with non-retriggerable one pulse mode described in Section 40.3.11: One-pulse mode: • The pulse starts as soon as the trigger occurs (no programmable delay) • The pulse is extended if a new trigger occurs before the previous one is completed The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for retrigerrable OPM mode 1 or 2. If the timer is configured in up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in down-counting mode, CCRx must be above or equal to ARR. Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit are not contiguous with the 3 least significant ones. This mode must not be used with center-aligned PWM modes. It is mandatory to have CMS[1:0] = 00 in TIMx_CR1. Figure 467. Retriggerable one pulse mode 75*, &RXQWHU 2XWSXW 069 1664/3178 DocID029587 Rev 3 RM0433 40.3.13 General-purpose timers (TIM12/TIM13/TIM14) UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the assertions of the UIF and UIFCPY flags. 40.3.14 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture. It is useful for measuring the interval between the edges on two input signals, as shown in Figure 468. Figure 468. Measuring time interval between edges on 2 signals 7, 7, 7,;257, &RXQWHU 069 40.3.15 TIM12 external trigger synchronization The TIM12 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register. DocID029587 Rev 3 1665/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’00101’ in TIMx_SMCR register. 3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 469. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program CC1P=’1’ and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’00101’ in TIMx_SMCR register. 3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=’0’, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. 1666/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 470. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register. Select TI2 as the input source by writing TS=’00110’ in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. DocID029587 Rev 3 1667/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Figure 471. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 40.3.16 Slave mode – combined reset + trigger mode In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter. This mode is used for one-pulse mode. 1668/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) 40.3.17 Timer synchronization (TIM12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 39.3.19: Timer synchronization for details. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 40.3.18 Debug mode When the microcontroller enters debug mode (Cortex®-M7 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 60.5.8: Microcontroller debug unit (DBGMCU). 40.4 TIM12 registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 40.4.1 TIM12 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 11 10 Res. UIFRE MAP Res. rw 9 8 CKD[1:0] rw 7 6 5 4 3 2 1 0 ARPE Res. Res. Res. OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. DocID029587 Rev 3 1669/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Bit 3 OPM: One-pulse mode 0: Counter is not stopped on the update event 1: Counter stops counting on the next update event (clearing the CEN bit). Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable update event (UEV) generation. 0: UEV enabled. An UEV is generated by one of the following events: – Counter overflow – Setting the UG bit Buffered registers are then loaded with their preload values. 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled CEN is cleared automatically in one-pulse mode, when an update event occurs. Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 40.4.2 TIM12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. MSM rw 20 TS[4:3] rw rw 5 4 TS[2:0] rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 TS[4:3]: Trigger selection - bit 4:3 Refer to TS[4:0] description - bits 6:4 Bits 20:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits 2:0 Bits 15:8 Reserved, must be kept at reset value. 1670/3178 21 DocID029587 Rev 3 rw 19 18 17 16 Res. Res. Res. SMS[3] 3 2 1 rw Res. rw 0 SMS[2:0] rw rw rw RM0433 General-purpose timers (TIM12/TIM13/TIM14) Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful in order to synchronize several timers on a single external event. Bits 6:4 TS[4:0]: Trigger selection This TS[4:0] bitfield selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1) 00110: Filtered Timer Input 2 (TI2FP2) Others: Reserved See Table 321: TIMx internal trigger connection on page 1671 for more details on the meaning of ITRx for each timer. Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 0001: Reserved 0010: Reserved 0011: Reserved 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Table 321. TIMx internal trigger connection Slave TIM ITR0 (TS = ‘00000’) ITR1 (TS = ‘00001’) ITR2 (TS = ‘00010’) ITR3 (TS = ‘00011’) TIM12 TIM4 TIM5 TIM13 OC1 TIM14 OC1 DocID029587 Rev 3 1671/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) 40.4.3 RM0433 TIM12 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. TIE Res. Res. Res. CC2IE CC1IE UIE rw rw rw rw Bits 15:7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bits 5:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 40.4.4 TIM12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 Res. Res. Res. Res. Res. 10 rc_w0 Bits 15:11 9 CC2OF CC1OF 8 7 6 5 4 3 2 1 0 Res. Res. TIF Res. Res. Res. CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 1672/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 General-purpose timers (TIM12/TIM13/TIM14) Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bits 5:3 Reserved, must be kept at reset value. Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow and if UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. 40.4.5 TIM12 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. Res. Res. CC2G CC1G UG w w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled Bits 5:3 Reserved, must be kept at reset value. DocID029587 Rev 3 1673/3178 1694 General-purpose timers (TIM12/TIM13/TIM14) RM0433 Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled. If channel CC1 is configured as input: The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared. 40.4.6 TIM12 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is configured in output mode, ICxx describes its function when the channel is configured in input mode. So you must take care that the same bit can have different meanings for the input stage and the output stage. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC2M [3] Res. Res. Res. Res. Res. Res. Res. OC1M [3] Res. Res. rw 15 14 Res. 13 12 OC2M[2:0] rw rw 10 OC2PE OC2FE IC2F[3:0] rw 11 IC2PSC[1:0] rw rw rw 9 8 CC2S[1:0] rw rw rw 7 6 Res. OC1M[2:0] rw rw Bits 31:25 Reserved, always read as 0 Bit 24 OC2M[3]: Output Compare 2 mode - bit 3 Refer to OC2M description on bits 14:12 Bits 23:17 Reserved, always read as 0 Bit 16 OC1M[3]: Output Compare 1 mode - bit 3 Refer to OC1M description on bits 6:4 1674/3178 4 Reserved, must be kept at reset value. DocID029587 Rev 3 rw 3 2 OC1PE OC1FE IC1F[3:0] Output compare mode Bit 15 5 IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw RM0433 General-purpose timers (TIM12/TIM13/TIM14) Bits 14:12 OC2M[2:0]: Output compare 2 mode Refer to OC1M[3:0] for bit description. Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 Reserved, must be kept at reset value. Bits 6:4 OC1M[3:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas the active level of OC1 depends on the CC1P. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. The OC1REF signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1 0100: Force inactive level - OC1REF is forced low 0101: Force active level - OC1REF is forced high 0110: PWM mode 1 - channel 1 is active as long as TIMx_CNT @ 7,0[B&+ 7, 7,>@ ,QSXW ILOWHU HGJH GHWHFWRU 7,)3 7,)3 &.B&17 36& SUHVFDOHU &&, 8 ,& 3UHVFDOHU 75& 7,>@ 7,0[B&+ 7, 7,>@ ,QSXW 7,)3 ILOWHU 7,)3 HGJH GHWHFWRU 75& ,QWHUQDOVRXUFHV &&, ,& 3UHVFDOHU ,&36 &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU '7*UHJLVWHUV 2&5() '7* &&, 8 &DSWXUH&RPSDUHUHJLVWHU 2&5() 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+1 2&1 2XWSXW 2& 7,0[B&+ FRQWURO 6%,) %,) %UHDNFLUFXLWU\ 7,0[B%.,1 ,&36 8 %5.UHTXHVW 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 06Y 9 1. The internal break event source can be: - A clock failure event generated by CSS. For further information on the CSS, refer to Section 8.5.3: Clock Security System (CSS) - A PVD output - SRAM parity error signal - Cortex®-M7 with FPU LOCKUP (Hardfault) output - COMP output DocID029587 Rev 3 1697/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 473. TIM16/TIM17 block diagram ,QWHUQDOFORFN &.B,17 &RXQWHU(QDEOH &(1 5(3UHJLVWHU $XWRUHORDGUHJLVWHU 8 8, 5HSHWLWLRQ FRXQWHU 6WRSFOHDURUXSGRZQ &.B36& 7,>@ 7,0[B&+ 7,>@ ,QSXW 7,)3 ILOWHU HGJH GHWHFWRU ,& 36& &.B&17 SUHVFDOHU &, 8 ,&36 3UHVFDOHU &17FRXQWHU 8 '7*UHJLVWHUV &&, &DSWXUHFRPSDUHUHJLVWHU 7,0[B&+ 2&5() '7* 2XWSXW 2& FRQWURO 7,0[B&+1 2&1 ,QWHUQDOVRXUFHV 6%,) %,) %UHDNFLUFXLWU\ 7,0[B%.,1 %5.UHTXHVW 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 06Y 9 1. The internal break event source can be: - A clock failure event generated by CSS. For further information on the CSS, refer to Section 8.5.3: Clock Security System (CSS) - A PVD output - SRAM parity error signal - Cortex®-M7 with FPU LOCKUP (Hardfault) output - COMP output 1698/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) 41.4 TIM15/TIM16/TIM17 functional description 41.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) • Repetition counter register (TIMx_RCR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 474 and Figure 475 give some examples of the counter behavior when the prescaler ratio is changed on the fly: DocID029587 Rev 3 1699/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 474. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 475. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 1700/3178 DocID029587 Rev 3 RM0433 41.4.2 General-purpose timers (TIM15/TIM16/TIM17) Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter overflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register, • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. DocID029587 Rev 3 1701/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 476. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 477. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 1702/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Figure 478. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 479. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1703/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 480. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Figure 481. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 1704/3178 DocID029587 Rev 3 069 RM0433 41.4.3 General-purpose timers (TIM15/TIM16/TIM17) Repetition counter Section 41.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the value in the TIMx_RCR repetition counter register. The repetition counter is decremented at each counter overflow. The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 482). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register. DocID029587 Rev 3 1705/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 482. Update rate examples depending on mode and TIMx_RCR register settings (GJHDOLJQHGPRGH 8SFRXQWLQJ &RXQWHU 7,0[B&17 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 DQG UHV\QFKURQL]DWLRQ8(9 E\6: 8(9 8SGDWH(YHQW SUHORDGUHJLVWHUVWUDQVIHUUHGWRDFWLYHUHJLVWHUV DQGXSGDWHLQWHUUXSWJHQHUDWHG 069 41.4.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for another timer, for example, you can configure TIM1 to act as a prescaler for TIM15. Refer to Using one timer as prescaler for another timer on page 1611 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed 1706/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 483 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 483. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 484. TI2 external clock connection example 7,0[B60&5 76> @ ,75[ 7,B(' 7,)3 7,)B5LVLQJ 7,>@ 7,>@ )LOWHU (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 [[ 75*, 7,0[B&&05 &.B36& &.B,17 ,&)> @ ([WHUQDOFORFN PRGH &&3 LQWHUQDOFORFN ,QWHUQDOFORFN PRGH 7,0[B&&(5 606> @ 7,0[B60&5 06Y 9 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: DocID029587 Rev 3 1707/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) Note: RM0433 1. Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. 2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 4. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 6. Select TI2 as the trigger input source by writing TS=00110 in the TIMx_SMCR register. 7. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 485. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 41.4.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 486 to Figure 489 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 1708/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Figure 486. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7,>@ 7,)B5LVLQJ 7,>@ I'76 )LOWHU GRZQFRXQWHU (GJH GHWHFWRU 7,)3 7,)B)DOOLQJ 7,)3 ,&)> @ &&3 ,& ,&36 'LYLGHU 75& 7,0[B&&(5 7,0[B&&05 IURPVODYHPRGH FRQWUROOHU 7,)B5LVLQJ IURPFKDQQHO ,&36> @ &&6> @ 7,)B)DOOLQJ IURPFKDQQHO &&( 7,0[B&&(5 7,0[B&&05 06Y 9 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 487. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 7,0B(*5 06 9 DocID029587 Rev 3 1709/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 488. Output stage of capture/compare channel (channel 1) 7RWKHPDVWHUPRGH FRQWUROOHU µ¶ 2&5()& 2&5() &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&B'7 'HDGWLPH JHQHUDWRU 2XWSXW VHOHFWRU [ &&3 2XWSXW HQDEOH FLUFXLW 2& 2XWSXW HQDEOH FLUFXLW 2&1 7,0B&&(5 2&1B'7 µ¶ 2&5() [ &&1( &&( 7,0B&&(5 2&&( 2&0> @ '7*> @ &&1( &&( &&13 02( 266, 2665 7,0B&&05 7,0B%'75 7,0B&&(5 7,0B&&(5 7,0B%'75 06 9 Figure 489. Output stage of capture/compare channel (channel 2 for TIM15) 7RWKHPDVWHU PRGHFRQWUROOHU 2&5()& 2&5() µ¶ &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&5() 2XWSXW VHOHFWRU &&( &&3 7,0B&&(5 7,0B&&(5 2XWSXW HQDEOH FLUFXLW 2& &&( 7,0B&&(5 2&&( 2&0> @ 7,0B&&05 06 9 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 1710/3178 DocID029587 Rev 3 RM0433 41.4.6 General-purpose timers (TIM15/TIM16/TIM17) Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. 2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 3. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at least 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 4. Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). 5. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 6. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 7. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID029587 Rev 3 1711/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.4.7 RM0433 PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the proper TI1[x] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. 2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). 4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to ‘1’ (active on falling edge). 6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register (TI1FP1 selected). 7. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 8. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 490. PWM input mode timing 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 1712/3178 DocID029587 Rev 3 RM0433 41.4.8 General-purpose timers (TIM15/TIM16/TIM17) Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 41.4.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). DocID029587 Rev 3 1713/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Procedure 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. 5. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 491. Figure 491. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 06 9 41.4.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. 1714/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). The TIM15/TIM16/TIM17 are capable of upcounting only. Refer to Upcounting mode on page 1701. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 492 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8. Figure 492. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 06 9 41.4.11 Combined PWM mode (TIM15 only) Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined DocID029587 Rev 3 1715/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: • OC1REFC (or OC2REFC) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. When a given channel is used as a combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 493 represents an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration: • Channel 1 is configured in Combined PWM mode 2, • Channel 2 is configured in PWM mode 1, Figure 493. Combined PWM mode on channel 1 and 2 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 06 9 1716/3178 DocID029587 Rev 3 RM0433 41.4.12 General-purpose timers (TIM15/TIM16/TIM17) Complementary outputs and dead-time insertion The TIM15/TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 329: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) on page 1765 for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0). Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 494. Complementary output with dead-time insertion. 2&[5() 2&[ GHOD\ 2&[1 GHOD\ 06 9 DocID029587 Rev 3 1717/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 495. Dead-time waveforms with delay greater than the negative pulse. 2&[5() 2&[ GHOD\ 2&[1 06 9 Figure 496. Dead-time waveforms with delay greater than the positive pulse. 2&[5() 2&[ 2&[1 GHOD\ 06 9 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 41.6.13: TIM16/TIM17 break and dead-time register (TIMx_BDTR) on page 1768 for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: 1718/3178 When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. DocID029587 Rev 3 RM0433 41.4.13 General-purpose timers (TIM15/TIM16/TIM17) Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM15/TIM16/TIM17 timers. The break input is usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state. The break channel gathers both system-level fault (clock failure, parity error,...) and application fault (from input pins and built-in comparator), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration. The output enable signal and output levels during break are depending on several control bits: • the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. • the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode) • the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shutdown level, either active or inactive. The OCx and OCxN outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values. Refer to Table 327: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) on page 1745 for more details. When exiting from reset, the break circuit is disabled and the MOE bit is low. The break function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. • Programmable filter (BKF[3:0] bits in the TIMx_BDTR register) to avoid spurious events. The break can be generated from multiple sources which can be individually enabled and with programmable edge sensitivity, using the TIMx_OR2 register. DocID029587 Rev 3 1719/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 The sources for break (BRK) channel are: • An external source connected to one of the BKIN pin (as per selection done in the AFIO controller), with polarity selection and optional digital filtering • An internal source: – the output from a comparator, with polarity selection and optional digital filtering – the analog watchdog output of the DFSDM1 peripheral – A system break: - the Cortex®-M7 with FPU LOCKUP output - the PVD output - the SRAM parity error signal - a Flash ECC error - a clock failure event generated by the CSS detector Figure 497. Break circuitry overview &RUH/RFNXS 39' /RFNXS/2&. 39'/2&. 6\VWHPEUHDNUHTXHVWV 5$0SDULW\(UURU (&&(UURU 6%,)IODJ 3DULW\/2&. (&&/2&. &66 %.,13 %.,1LQSXWV IURP$) FRQWUROOHU %.,1( 6RIWZDUHEUHDNUHTXHVWV %* %.&033 %.&03( &203RXWSXW %.)> @ %.( %,)IODJ %.3 %5.UHTXHVW %.&033 &203RXWSXW ')6'0 %5($.RXWSXW )LOWHU %.&03( $SSOLFDWLRQEUHDNUHTXHVWV %.')%.[( 06Y9 Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or the CSS) must be used to guarantee that break events are handled. Caution: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (example, using the internal PLL and/or the CSS) must be used to guarantee that break events are handled. 1720/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) When a break occurs (selected level on the break input): Note: • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the AFIO controller (selected by the OSSI bit). This feature functions even if the MCU oscillator is off. • Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the AFIO controller) else the enable output remains high. • When complementary outputs are used: – The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs (taken over by the AFIO controller which forces a Hi-Z state) else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. • The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 41.6.13: TIM16/TIM17 break and dead-time register (TIMx_BDTR) on page 1768. The LOCK bits can be written only once after an MCU reset. The Figure 498 shows an example of behavior of the outputs in response to a break. DocID029587 Rev 3 1721/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Figure 498. Output behavior in response to a break %5($. 02( 2&[5() 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 &&[1( &&[13 2,6[ 2,6[1 RU2,6[ 2,6[1 06 9 1722/3178 DocID029587 Rev 3 RM0433 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • CNT < CCRx ≤ ARR (in particular, 0 < CCRx) Figure 499. Example of one pulse mode. 7, 2&5() 2& 7,0B$55 &RXQWHU 41.4.14 General-purpose timers (TIM15/TIM16/TIM17) 7,0B&&5 W'(/$< W38/6( W 06 9 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: 1. Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. 2. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 3. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’00110’ in the TIMx_SMCR register. 5. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). DocID029587 Rev 3 1723/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 41.4.15 Retriggerable one pulse mode (OPM) (TIM15 only) This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one pulse mode described in Section 41.4.14: – The pulse starts as soon as the trigger occurs (no programmable delay) – The pulse is extended if a new trigger occurs before the previous one is completed The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for Retrigerrable OPM mode 1 or 2. If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode, CCRx must be above or equal to ARR. Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit are not contiguous with the 3 least significant ones. This mode must not be used with center-aligned PWM modes. It is mandatory to have CMS[1:0] = 00 in TIMx_CR1. 1724/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Figure 500. Retriggerable one pulse mode 75*, &RXQWHU 2XWSXW 069 41.4.16 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the assertions of the UIF and UIFCPY flags. DocID029587 Rev 3 1725/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.4.17 RM0433 Timer input XOR function (TIM15 only) The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture. It is useful for measuring the interval between the edges on two input signals, as shown in Figure 501. Figure 501. Measuring time interval between edges on 2 signals 7, 7, 7,;257, &RXQWHU 069 1726/3178 DocID029587 Rev 3 RM0433 41.4.18 General-purpose timers (TIM15/TIM16/TIM17) External trigger synchronization (TIM15 only) The TIM timers are linked together internally for timer synchronization or chaining. The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=’0’ and CC1NP=’0’ in the TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=00101 in TIMx_SMCR register. 3. Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 502. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 DocID029587 Rev 3 1727/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP = ‘0’ in the TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=00101 in TIMx_SMCR register. 3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 503. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 1728/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=’1’ and CC2NP=’0’ in the TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=110 in the TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in the TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 504. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 41.4.19 Slave mode – combined reset + trigger mode In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter. This mode is used for one-pulse mode. 41.4.20 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests on a single event. The main purpose is to be able to re-program several timer registers multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals. The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers. DocID029587 Rev 3 1729/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, For example, the timer DMA burst feature could be used to update the contents of the CCRx registers (x = 2, 3, 4) on an update event, with the DMA transferring half words into the CCRx registers. This is done in the following steps: 1. Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into the CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register is to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. Note: 1730/3178 A null value can be written to the reserved registers. DocID029587 Rev 3 RM0433 41.4.21 General-purpose timers (TIM15/TIM16/TIM17) Timer synchronization (TIM15) The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 41.4.21: Timer synchronization (TIM15) for details. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 41.4.22 Debug mode When the microcontroller enters debug mode (Cortex®-M7 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on TIMx bit in DBGMCU module. For more details, refer to Section 60: Debug infrastructure. For safety purposes, when the counter is stopped (TIMx = 1 in DBGMCU_APB2FZ1), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force them to Hi-Z. DocID029587 Rev 3 1731/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.5 RM0433 TIM15 registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. 41.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 11 10 Res. UIFRE MAP Res. rw 9 8 CKD[1:0] rw 7 6 5 4 3 2 1 0 ARPE Res. Res. Res. OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 00: tDTS = tCK_INT 01: tDTS = 2*tCK_INT 10: tDTS = 4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 1732/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt if enabled Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 41.5.2 TIM15 control register 2 (TIM15_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. OIS2 OIS1N OIS1 TI1S rw rw rw rw 6 5 4 MMS[2:0] rw rw rw 3 2 1 0 CCDS CCUS Res. CCPC rw rw rw Bits 15:11 Reserved, must be kept at reset value. Bit 10 OIS2: Output idle state 2 (OC2 output) 0: OC2=0 when MOE=0 1: OC2=1 when MOE=0 Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIMx_BKR register). Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). DocID029587 Rev 3 1733/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO). 101: Compare - OC2REF signal is used as trigger output (TRGO). Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). Note: This bit acts only on channels that have a complementary output. 1734/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) 41.5.3 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. MSM rw 21 20 TS[4:3] rw rw 5 4 TS[2:0] rw rw 19 18 17 16 Res. Res. Res. SMS[3] 3 2 1 rw Res. rw 0 SMS[2:0] rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 TS[4:3]: Trigger selection - bit 4:3 Refer to TS[4:0] description - bits 6:4. Bits 19:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits 2:0. Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[4:0]: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1) 00110: Filtered Timer Input 2 (TI2FP2) Other: Reserved See Table 326: TIMx Internal trigger connection on page 1736 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. DocID029587 Rev 3 1735/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 0001: Reserved 0010: Reserved 0011: Reserved 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Table 326. TIMx Internal trigger connection 41.5.4 Slave TIM ITR0 (TS = 00000) ITR1 (TS = 00001) TIM15 TIM1 TIM3 ITR2 (TS = 00010) ITR3 (TS = 00011) TIM16 OC1 TIM17 OC1 TIM15 DMA/interrupt enable register (TIM15_DIER) Address offset: 0x0C Reset value: 0x0000 15 Res. 14 13 12 11 TDE COMD E Res. Res. rw rw 10 9 CC2DE CC1DE rw rw 8 7 6 5 4 3 2 1 0 UDE BIE TIE COMIE Res. Res. CC2IE CC1IE UIE rw rw rw rw rw rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bits 12:11 Reserved, must be kept at reset value. 1736/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bits 4:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 41.5.5 TIM15 status register (TIM15_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 Res. Res. Res. Res. Res. 10 9 CC2OF CC1OF rc_w0 rc_w0 8 7 6 5 4 3 2 1 0 Res. BIF TIF COMIF Res. Res. CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/Compare 2 overcapture flag Refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set DocID029587 Rev 3 1737/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending Bit 5 COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending Bits 5:3 Reserved, must be kept at reset value. Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 41.5.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 1738/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) 41.5.6 TIM15 event generation register (TIM15_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. BG TG COMG Res. Res. CC2G CC1G UG w w rw w w w Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. Bits 4:3 Reserved, must be kept at reset value. Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). DocID029587 Rev 3 1739/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.5.7 RM0433 TIM15 capture/compare mode register 1 (TIM15_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 Res. OC2M [3] 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. OC1M [3] Res. Res. rw 15 14 Res. 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE 9 rw 8 CC2S[1:0] 7 6 Res. rw rw 4 OC1M[2:0] IC2PSC[1:0] rw 5 IC1F[3:0] rw rw rw rw rw 3 2 OC1 PE OC1 FE 1 0 CC1S[1:0] IC1PSC[1:0] rw rw rw rw rw Output compare mode: Bits 31:25 Reserved, always read as 0 Bit 24 OC2M[3]: Output Compare 2 mode - bit 3 Bits 23:17 Reserved, always read as 0 Bit 16 OC1M[3]: Output Compare 1 mode - bit 3 refer to OC1M description on bits 6:4 Bit 15 Reserved, always read as 0 Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 Reserved, always read as 0 1740/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 1750/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) 41.5.16 TIM15 DMA control register (TIM15_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res. Res. Res. rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 41.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). DocID029587 Rev 3 1751/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.5.18 RM0433 TIM15 alternate register 1 (TIM15_AF1) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BKCM P2P BKCM P1P BKINP BKDF1 BK0E Res. Res. Res. Res. Res. BKCM P2E BKCM P1E BKINE rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDF1BK0E: BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer’s BRK input. dfsdm1_break[0] output is ‘ORed’ with the other BRK sources. 0: dfsdm1_break[0]input disabled 1: dfsdm1_break[0]input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1752/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 41.5.19 TIM15 input selection register (TIM15_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 3 2 1 0 15 14 13 12 Res. Res. Res. Res. TI2SEL[3:0] rw rw rw 7 6 5 4 Res. Res. Res. Res. rw TI1SEL[3:0] rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits [11:8] TI2SEL[3:0]: selects TI2[0] to TI2[15] input 0000: TIM15_CH2 input 0001: TIM2_CH2 input 0010: TIM3_CH2 input 0011: TIM4_CH2 input Others: Reserved Bits 7:4 Reserved, must be kept at reset value. Bits [3:0] TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM15_CH1 input 0001: TIM2_CH1 input 0010: TIM3_CH1 input 0011: TIM4_CH1 input 0100: LSE 0101: CSI 0110: MCO2 Other: Reserved DocID029587 Rev 3 1753/3178 1777 0x20 TIM15_CCER 1754/3178 Reset value DocID029587 Rev 3 0 0 0 0 0 0 0 0 CC1E 0 0 CC1P 0 CC1NE IC2F[3:0] Reset value CC2S [1:0] 0 0 0 IC2 PSC [1:0] CC2S [1:0] Res. 0 0 0 0 0 0 0 0 0 0 IC1F[3:0] UG OC1M [2:0] CC2IF CC1IF UIF 0 CC1G 0 CC2G 0 CC2IE CC1IE UIE OPM URS UDIS CEN 0 0 CCUS Res. CCPC Res. Res. Res. 0 CCDS TS[2:0] 0 0 0 Res. 0 0 0 0 OC1FE Res. 0 Res. 0 Res. 0 Res. 0 OC1PE Res. TI1S 0 MSM ARPE OIS1 0 Res. Res. 0 OIS2 0 MMS[2:0] Res. UIFREMAP Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 OIS1N Res. Res. Res. Res. Res. SMS[3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CKD [1:0] Res. 0 Res. COMIE 0 COMIF 0 COMG TIE 0 TIF BIE 0 TG UDE 0 BIF 0 BG Res. CC1DE CC1OF Res. Res. CC2DE CC2OF Res. Res. Res. 0 Res. OC2FE Res. Res. COMDE Res. 0 CC1NP 0 Res. 0 OC2PE OC2M [2:0] 0 CC2E 0 Res. 0 Res. Reset value CC2P 0 Res. 0 Res. TDE Res. Res. Res. Res. 0 Res. 0 Res. 0 0 Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. OC1M[3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC2NP 0 Res. Reset value Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS [4:3] Res. Res. Res. Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. TIM15_CCMR1 Input Capture mode Res. TIM15_CCMR1 Output Compare mode Res. TIM15_EGR Res. 0x18 TIM15_SR Res. 0x10 Res. 0x14 TIM15_DIER Res. 0x0C TIM15_SMCR Res. 0x08 TIM15_CR2 Res. 0x04 TIM15_CR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 41.5.20 Res. General-purpose timers (TIM15/TIM16/TIM17) RM0433 TIM15 register map TIM15 registers are mapped as 16-bit addressable registers as described in the table below: Table 328. TIM15 register map and reset values SMS[2:0] 0 0 0 0 0 0 0 0 0 0 CC1S [1:0] 0 0 0 0 IC1 PSC [1:0] CC1S [1:0] 0 0 0 0 0 0 0x68 TIM15_TISEL Reset value DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. BKCMP2E BKCMP1E BKINE 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 0 0 0 0 0 0 0 0 DBL[4:0] TI2SEL[3:0] 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UIFCPY or Res. Res. Res. 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 Res. 0 Res. Reset value 0 0 0 Res. 0 0 0 0 Res. 0 Res. OSSI 0 0 0 0 Res. 0 BKDF1BK0E OSSR 0 0 0 0 Res. Reset value 0 BKINP Reset value BKCMP1P BKE 0 Res. BKF[3:0] Res. BKCMP2P BKP 0 Res. Res. 0 0 0 Res. AOE 0 Res. Reset value Res. 0 Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. MOE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOCK [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. TIM15_AF1 Res. TIM15_DMAR Res. TIM15_DCR Res. TIM15_BDTR Res. 0x60 TIM15_CCR2 Res. 0x4C TIM15_CCR1 Res. 0x48 TIM15_PSC Res. 0x44 0 Res. 0x38 TIM15_RCR Res. 0x34 Reset value Res. 0x30 TIM15_ARR Res. 0x2C TIM15_CNT Res. 0x28 Res. 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. RM0433 General-purpose timers (TIM15/TIM16/TIM17) Table 328. TIM15 register map and reset values (continued) CNT[15:0] PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 REP[7:0] CCR1[15:0] CCR2[15:0] DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA[4:0] 0 0 0 0 0 DMAB[15:0] 0 0 0 0 0 0 1 TI1SEL[3:0] 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 1755/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.6 RM0433 TIM16/TIM17 registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. 41.6.1 TIM16/TIM17 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 11 10 Res. UIF REMAP Res. rw 9 8 CKD[1:0] rw 7 6 5 4 3 2 1 0 ARPE Res. Res. Res. OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 1756/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 41.6.2 TIM16/TIM17 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. OIS1N OIS1 Res. Res. Res. Res. CCDS CCUS Res. CCPC rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bits 7:4 Reserved, must be kept at reset value. Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. DocID029587 Rev 3 1757/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. 41.6.3 TIM16/TIM17 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. COMDE Res. Res. Res. CC1DE UDE BIE Res. COMIE Res. Res. Res. CC1IE UIE rw rw rw rw rw rw Bits 15:14 Reserved, must be kept at reset value. Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bits 12:10 Reserved, must be kept at reset value. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 Reserved, must be kept at reset value. Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 1758/3178 DocID029587 Rev 3 rw RM0433 General-purpose timers (TIM15/TIM16/TIM17) 41.6.4 TIM16/TIM17 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. CC1OF Res. BIF Res. COMIF Res. Res. Res. CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 Reserved, must be kept at reset value. Bit 5 COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) DocID029587 Rev 3 1759/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) RM0433 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 41.6.5 TIM16/TIM17 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. BG Res. COMG Res. Res. Res. CC1G UG w w w w Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 Reserved, must be kept at reset value. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 1760/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) 41.6.6 TIM16/TIM17 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. OC1M [3] Res. rw 15 Res. 14 Res. 13 Res. 12 Res. 11 Res. 10 Res. 9 8 Res. Res. 7 6 Res. 5 4 OC1M[2:0] rw rw 2 OC1PE OC1FE IC1F[3:0] rw 3 IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode: Bits 31:17 Reserved, always read as 0 Bit 16 OC1M[3]: Output Compare 1 mode (bit 3) Bits 15:7 Reserved Bits 6:4 OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 41.6.14 TIM16/TIM17 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 10 9 8 DBL[4:0] rw 1770/3178 11 rw rw rw 7 6 5 Res. Res. Res. rw DocID029587 Rev 3 4 3 2 1 0 rw rw DBA[4:0] rw rw rw RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 41.6.15 TIM16/TIM17 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). DocID029587 Rev 3 1771/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.6.16 RM0433 TIM16 alternate function register 1 (TIM16_AF1) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BKCM P2P BKCM P1P BKINP BKDF1 BK1E Res. Res. Res. Res. Res. BKCM P2E BKCM P1E BKINE rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDFBK1E: BRK dfsdm1_break[1] enable This bit enables the dfsdm1_break[1] for the timer’s BRK input. dfsdm1_break[1] output is ‘ORed’ with the other BRK sources. 0: dfsdm1_break[1] input disabled 1: dfsdm1_break[1] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value 1772/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 41.6.17 TIM16 input selection register (TIM16_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1SEL[3:0] rw rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bits [3:0] TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM16_CH1 input 0001: LSI 0010: LSE 0011: WKUP_IT Other: Reserved DocID029587 Rev 3 1773/3178 1777 General-purpose timers (TIM15/TIM16/TIM17) 41.6.18 RM0433 TIM17 alternate function register 1 (TIM17_AF1) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BKCM P2P BKCM P1P BKINP BKDF1 BK2E Res. Res. Res. Res. Res. BKCM P2E BKCM P1E BKINE rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDF1BK2E: BRK dfsdm1_break[2] enable This bit enables the dfsdm1_break[2] for the timer’s BRK input. dfsdm1_break[2] output is ‘ORed’ with the other BRK sources. 0: dfsdm1_break[2] input disabled 1: dfsdm1_break[2] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value 1774/3178 DocID029587 Rev 3 RM0433 General-purpose timers (TIM15/TIM16/TIM17) Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 41.6.19 TIM17 input selection register (TIM17_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1SEL[3:0] rw rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bits [3:0] TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM17_CH1 input 0001: SPDIF FS 0010: HSE_1MHz 0011: MCO1 Other: Reserved DocID029587 Rev 3 1775/3178 1777 0x2C TIMx_ARR 1776/3178 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value DocID029587 Rev 3 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 IC1F[3:0] 0 0 0 0 0 0 0 Reset value CC1E 0 UIF Res. Res. Res. COMIF 0 0 UG 0 CC1IF Res. Res. Res. BIF CC1IE UIE Res. Res. Res. COMIE Res. Res. 0 CC1G OC1M [2:0] OC1FE 0 OC1PE 0 CC1P 0 COMG 0 CC1NE 0 Res. BIE 0 Res. UDE 0 CC1NP 0 Res. Reset value Res. Reset value BG Res. 0 Res. Res. ARPE Res. OPM URS UDIS CEN 0 0 0 CCUS Res. CCPC Res. Res. Res. 0 CCDS Res. Res. Res. OIS1 Res. 0 Res. 0 OIS1N UIFREMAP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. CC1DE Res. Res. Res. 0 CC1OF Res. Res. Res. COMDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CKD [1:0] 0 Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. OC1M[3] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. TIMx_PSC Res. 0 Res. Reset value Res. 0x28 TIMx_CNT Res. 0x24 Res. TIMx_CCER Res. TIMx_CCMR1 Input Capture mode Res. TIMx_CCMR1 Output Compare mode Res. TIMx_EGR Res. 0x14 Res. TIMx_SR Res. 0x10 Res. TIMx_DIER Res. TIMx_CR2 Res. 0x04 Res. TIMx_CR1 Res. 0x00 Res. 0x20 UIFCPY or Res. 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. 0x0C Res. Offset Res. 41.6.20 Res. General-purpose timers (TIM15/TIM16/TIM17) RM0433 TIM16/TIM17 register map TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 330. TIM16/TIM17 register map and reset values 0 0 0 0 0 0 0 CC1 S [1:0] 0 IC1 PSC [1:0] 0 0 CC1 S [1:0] 0 0 0 0 0 CNT[15:0] PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0x68 TIM17_TISEL DocID029587 Rev 3 0 0 0 0 0 Res. Reset value Reset value BKCMP1E BKINE 0 0 1 BKINE 0 BKCMP1E 0 Res. BKCMP2E 0 Res. Res. CCR1[15:0] DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. BKCMP2E 0 0 Res. 0 0 0 Res. DBL[4:0] 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 0 0 Res. OSSI 0 Res. 0 Res. 0 0 Res. OSSR 0 Res. 0 Res. 0 BKDF1BK1E BKE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. BKDF1BK2E 0 Res. 0 BKINP BKP 0 Res. 0 Res. BKINP 0 Res. 0 BKCMP1P Reset value 0 Res. BKCMP1P 0 Res. 0 0 Res. 0 Res. 0 Res. BKCMP2P AOE 0 Res. 0 Res. Reset value Res. BKCMP2P 0 Res. Reset value Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. MOE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOC K [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKF[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. TIM16_TISEL Res. 0x68 TIM17_AF1 Res. 0x60 TIM16_AF1 Res. 0x60 TIMx_DMAR Res. 0x4C TIMx_DCR Res. 0x48 TIMx_BDTR Res. 0x44 TIMx_CCR1 Res. 0x34 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_RCR Res. 0x30 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. RM0433 General-purpose timers (TIM15/TIM16/TIM17) Table 330. TIM16/TIM17 register map and reset values (continued) REP[7:0] 0 DBA[4:0] 0 0 0 0 0 DMAB[15:0] 0 0 1 TISEL[3:0] 0 0 0 0 0 0 0 TISEL[3:0] 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 1777/3178 1777 Basic timers (TIM6/TIM7) RM0433 42 Basic timers (TIM6/TIM7) 42.1 TIM6/TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs. The timers are completely independent, and do not share any resources. 42.2 TIM6/TIM7 main features Basic timer (TIM6/TIM7) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 • Synchronization circuit to trigger the DAC • Interrupt/DMA generation on the update event: counter overflow Figure 505. Basic timer block diagram 7ULJJHU FRQWUROOHU ,QWHUQDOFORFN &.B,17 7,0[&/.IURP5&& &RQWURO &.B&17 5HVHWHQDEOH&RXQW 8, 6WRSFOHDURUXS 36& SUHVFDOHU WR'$& $XWRUHORDGUHJLVWHU 8 &.B36& 75*2 8 &17FRXQWHU 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 069 1778/3178 DocID029587 Rev 3 RM0433 Basic timers (TIM6/TIM7) 42.3 TIM6/TIM7 functional description 42.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC) • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set. Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 506 and Figure 507 give some examples of the counter behavior when the prescaler ratio is changed on the fly. DocID029587 Rev 3 1779/3178 1790 Basic timers (TIM6/TIM7) RM0433 Figure 506. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 507. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 1780/3178 DocID029587 Rev 3 RM0433 42.3.2 Basic timers (TIM6/TIM7) Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 508. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID029587 Rev 3 1781/3178 1790 Basic timers (TIM6/TIM7) RM0433 Figure 509. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 06 9 Figure 510. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1782/3178 DocID029587 Rev 3 RM0433 Basic timers (TIM6/TIM7) Figure 511. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 512. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 DocID029587 Rev 3 1783/3178 1790 Basic timers (TIM6/TIM7) RM0433 Figure 513. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 42.3.3 069 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the assertions of the UIF and UIFCPY flags. 42.3.4 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 514 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 1784/3178 DocID029587 Rev 3 RM0433 Basic timers (TIM6/TIM7) Figure 514. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 42.3.5 Debug mode When the microcontroller enters the debug mode (Cortex®-M7 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBGMCU module. For more details, refer to Section 60.5.8: Microcontroller debug unit (DBGMCU). 42.4 TIM6/TIM7 registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 42.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res 14 Res 13 Res 12 11 10 9 8 7 6 5 4 3 2 1 0 Res UIF REMAP Res Res Res ARPE Res Res Res OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bits 10:8 Reserved, must be kept at reset value. DocID029587 Rev 3 1785/3178 1790 Basic timers (TIM6/TIM7) RM0433 Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit). Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 1786/3178 DocID029587 Rev 3 RM0433 Basic timers (TIM6/TIM7) 42.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res Res Res Res Res Res Res Res Res 6 5 4 MMS[2:0] rw rw 3 2 1 0 Res Res Res Res rw Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bits 3:0 Reserved, must be kept at reset value. 42.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res UDE Res Res Res Res Res Res Res UIE rw rw Bits 15:9 Reserved, must be kept at reset value. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bits 7:1 Reserved, must be kept at reset value. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. DocID029587 Rev 3 1787/3178 1790 Basic timers (TIM6/TIM7) 42.4.4 RM0433 TIM6/TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 UIF rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 42.4.5 TIM6/TIM7 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res UG w Bits 15:1 Reserved, must be kept at reset value. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 42.4.6 TIM6/TIM7 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UIF CPY Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw r 15 CNT[15:0] rw rw 1788/3178 rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Basic timers (TIM6/TIM7) Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 42.4.7 TIM6/TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 42.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 42.3.1: Time-base unit on page 1779 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID029587 Rev 3 1789/3178 1790 0x2C 1790/3178 TIMx_ARR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x180x20 Res Res Res Res Res Res Res Res Res Res Reset value Reset value DocID029587 Rev 3 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. Reset value Reset value UIF Res Res 0 UG Res Res Res Res Res Res UIE URS UDIS CEN OPM Res Res Res ARPE Res Res Res UIFREMAP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res 0 Res 0 Res Reserved 0 Res MMS [2:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Reset value Res Res UDE Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x08 Res Res Res Res Res TIMx_PSC Res 0 Res Reset value Res TIMx_CNT Res TIMx_EGR Res 0x28 TIMx_SR Res 0x24 TIMx_DIER Res 0x14 TIMx_CR2 Res 0x10 TIMx_CR1 Res 0x0C UIFCPY or Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res 0x00 Res Offset Res 42.4.9 Res Basic timers (TIM6/TIM7) RM0433 TIM6/TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 331. TIM6/TIM7 register map and reset values 0 0 0 0 0 0 Reserved CNT[15:0] PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 RM0433 Low-power timer (LPTIM) 43 Low-power timer (LPTIM) 43.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter” which can be useful in some applications. Also, the LPTIM capability to wake up the system from low-power modes, makes it suitable to realize “Timeout functions” with extremely low power consumption. The LPTIM introduces a flexible clock scheme that provides the needed functionalities and performance, while minimizing the power consumption. 43.2 43.3 LPTIM main features • 16 bit upcounter • 3-bit prescaler with 8 possible dividing factors (1,2,4,8,16,32,64,128) • Selectable clock – Internal clock sources: LSE, LSI, HSI or APB clock – External clock source over LPTIM input (working with no LP oscillator running, used by Pulse Counter application) • 16 bit ARR autoreload register • 16 bit compare register • Continuous/One-shot mode • Selectable software/hardware input trigger • Programmable Digital Glitch filter • Configurable output: Pulse, PWM • Configurable I/O polarity • Encoder mode LPTIM implementation Table 332 describes LPTIM implementation on STM32H7x3 devices. Table 332. STM32H7x3 LPTIM features LPTIM modes/features(1) Encoder mode LPTIM1 LPTIM2 LPTIM3 LPTIM4 LPTIM5 X X - - - 1. X = supported. DocID029587 Rev 3 1791/3178 1818 Low-power timer (LPTIM) RM0433 43.4 LPTIM functional description 43.4.1 LPTIM block diagram Figure 515. Low-power timer block diagram (LPTIM1 and LPTIM2) OSWLPBSFON OSWLPBSFON FORFNGRPDLQ OSWLPBNHUBFNFORFNGRPDLQ 8SGRZQ *OLWFK ILOWHU (QFRGHU /37,0 UHJLVWHU LQWHUIDFH 6\QFKURQ]DWLRQ ELW$3%EXV /37,0 *OLWFK ILOWHU *OLWFK ILOWHU &176757 61*6757 OSWLPBLQBPX[ OSWLPBLQBPX[ OSWLPBLQBPX[ /37,0B,1 OSWLPBLQBPX[ OSWLPBLQBPX[ OSWLPBLQBPX[ /37,0B,1 OSWLPBH[WBWUJ[ ELW$55 /37,0B(75 0X[WULJJHU OSWLPBLW OSWLPB NHUBFN ,54 LQWHUIDFH &/.08; &RXQW PRGH 3UHVFDOHU ELWFRXQWHU /37,0B287 OSWLPBRXW ELWFRPSDUH OSWLPB ZNXS 06Y9 1792/3178 DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Figure 516. Low-power timer block diagram (LPTIM3) /37,0 /37,0 UHJLVWHU LQWHUIDFH OSWLPB SFON OSWLPBNHUBFNFORFNGRPDLQ 6\QFKURQ]DWLRQ ELW$3%EXV OSWLPBSFON FORFNGRPDLQ *OLWFK ILOWHU *OLWFK ILOWHU &176757 61*6757 OSWLPBLQBPX[ OSWLPBLQBPX[ OSWLPBLQBPX[ /37,0B,1 OSWLPBH[WBWUJ[ ELW$55 0X[WULJJHU ,54 LQWHUIDFH OSWLPBLW OSWLP BNHUBFN &/.08; /37,0B287 &RXQW PRGH 3UHVFDOHU ELWFRXQWHU OSWLPBRXW ELWFRPSDUH OSWLP BZNXS 06Y9 Figure 517. Low-power timer block diagram (LPTIM4 and LPTIM5) OSWLPBSFON OSWLPBSFON FORFNGRPDLQ /37,0 UHJLVWHU LQWHUIDFH OSWLPBNHUBFNFORFNGRPDLQ 6\QFKURQ]DWLRQ ELW$3%EXV /37,0 *OLWFK ILOWHU OSWLPBH[WBWUJ[ &176757 61*6757 ELW$55 0X[WULJJHU OSWLPBLW ,54 LQWHUIDFH /37,0B287 ELWFRXQWHU OSWLPBRXW OSWLPBNHUBFN 3UHVFDOHU ELWFRPSDUH OSWLPBZNXS 06Y9 DocID029587 Rev 3 1793/3178 1818 Low-power timer (LPTIM) 43.4.2 RM0433 LPTIM pins and internal signals Table 334 and Table 333 gives the list of LPTIM internal signals and pins, respectively. Table 333. LPTIM input/output pins Names Signal type Description LPTIM_IN1 Digital input LPTIM Input 1 from GPIO pin on mux input 0 LPTIM_IN2 Digital input LPTIM Input 2 from GPIO pin on mux input 0 LPTIM_ETR Digital input LPTIM external trigger GPIO pin LPTIM_OUT Digital output LPTIM Output GPIO pin Table 334. LPTIM internal signals 43.4.3 Names Signal type Description lptim_pclk Digital input LPTIM APB clock domain lptim_ker_ck Digital input LPTIM kernel clock lptim_in1_mux1 Digital input Internal LPTIM input 1 connected to mux input 1 lptim_in1_mux2 Digital input Internal LPTIM input 1 connected to mux input 2 lptim_in1_mux3 Digital input Internal LPTIM input 1 connected to mux input 3 lptim_in2_mux1 Digital input Internal LPTIM input 2 connected to mux input 1 lptim_in2_mux2 Digital input Internal LPTIM input 2 connected to mux input 2 lptim_in2_mux3 Digital input Internal LPTIM input 2 connected to mux input 3 lptim_ext_trgx Digital input LPTIM external trigger input x lptim_out Digital output LPTIM counter output lptim_it Digital output LPTIM global interrupt lptim_wakeup Digital output LPTIM wakeup event LPTIM input and trigger mapping Table 335 to Table 339 describe LPTIM external trigger connections, while Table 340 to Table 344 show LPTIM input 1 and input 2 connections. Table 335. LPTIM1 external trigger connection 1794/3178 TRIGSEL External trigger lptim_ext_trig0 GPIO pin as LPTIM1_ETR alternate function lptim_ext_trig1 RTC_ALARMA lptim_ext_trig2 RTC_ALARMB lptim_ext_trig3 RTC_TAMP1_OUT lptim_ext_trig4 RTC_TAMP2_OUT lptim_ext_trig5 RTC_TAMP3_OUT DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Table 335. LPTIM1 external trigger connection TRIGSEL External trigger lptim_ext_trig6 COMP1_OUT lptim_ext_trig7 COMP2_OUT Table 336. LPTIM2 external trigger connection TRIGSEL External trigger lptim_ext_trig0 GPIO pin as LPTIM2_ETR alternate function lptim_ext_trig1 RTC_ALARMA lptim_ext_trig2 RTC_ALARMB lptim_ext_trig3 RTC_TAMP1_OUT lptim_ext_trig4 RTC_TAMP2_OUT lptim_ext_trig5 RTC_TAMP3_OUT lptim_ext_trig6 COMP1_OUT lptim_ext_trig7 COMP2_OUT Table 337. LPTIM3 external trigger connection TRIGSEL External trigger lptim_ext_trig0 LPTIM2_OUT lptim_ext_trig1 Not connected lptim_ext_trig2 LPTIM4_OUT lptim_ext_trig3 LPTIM5_OUT lptim_ext_trig4 SAI1_FS_A lptim_ext_trig5 SAI1_FS_B lptim_ext_trig6 Not connected lptim_ext_trig7 Not connected Table 338. LPTIM4 external trigger connection TRIGSEL External trigger lptim_ext_trig0 LPTIM2_OUT lptim_ext_trig1 LPTIM3_OUT lptim_ext_trig2 Not connected lptim_ext_trig3 LPTIM5_OUT lptim_ext_trig4 SAI2_FS_A lptim_ext_trig5 SAI2_FS_B DocID029587 Rev 3 1795/3178 1818 Low-power timer (LPTIM) RM0433 Table 338. LPTIM4 external trigger connection TRIGSEL External trigger lptim_ext_trig6 Not connected lptim_ext_trig7 Not connected Table 339. LPTIM5 external trigger connection TRIGSEL External trigger lptim_ext_trig0 LPTIM2_OUT lptim_ext_trig1 LPTIM3_OUT lptim_ext_trig2 LPTIM4_OUT lptim_ext_trig3 SAI4_FS_A lptim_ext_trig4 SAI4_FS_B lptim_ext_trig5 Not connected lptim_ext_trig6 Not connected lptim_ext_trig7 Not connected Table 340. LPTIM1 Input 1 connection lptim_in1_mux LPTIM1 Input 1 connected to lptim_in1_mux0 GPIO pin as LPTIM1_IN1 alternate function lptim_in1_mux1 COMP1_OUT lptim_in1_mux2 Not connected lptim_in1_mux3 Not connected Table 341. LPTIM1 Input 2 connection lptim_in2_mux LPTIM1 Input 2 connected to lptim_int2_mux0 GPIO pin as LPTIM1_IN2 alternate function lptim_in2_mux1 COMP2_OUT lptim_in2_mux2 Not connected lptim_in2_mux3 Not connected Table 342. LPTIM2 Input 1 connection 1796/3178 lptim_in1_mux LPTIM2 Input 1 connected to lptim_in1_mux0 GPIO pin as LPTIM2_IN1 alternate function lptim_in1_mux1 COMP1_OUT lptim_in1_mux2 COMP2_OUT lptim_in1_mux3 COMP1_OUT OR COMP2_OUT DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Table 343. LPTIM2 Input 2 connection lptim_in2_mux LPTIM2 Input 2 connected to lptim_int2_mux0 GPIO pin as LPTIM2_IN2 alternate function lptim_in2_mux1 COMP2_OUT lptim_in2_mux2 Not connected lptim_in2_mux3 Not connected Table 344. LPTIM3 Input 1 connection 43.4.4 lptim_in1_mux LPTIM3 Input 1 connected to lptim_in1_mux0 Not connected lptim_in1_mux1 SAI4_FS_A lptim_in1_mux2 SAI4_FS_B lptim_in1_mux3 Not connected LPTIM reset and clocks The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be chosen among APB, LSI, LSE or HSI sources through the Reset and Clock controller (RCC). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1. When clocked with an external clock source, the LPTIM may run in one of these two possible configurations: • The first configuration is when the LPTIM is clocked by an external signal but in the same time an internal clock signal is provided to the LPTIM either from APB or any other embedded oscillator including LSE, LSI and HSI. • The second configuration is when the LPTIM is solely clocked by an external clock source through its external Input1. This configuration is the one used to realize Timeout function or Pulse counter function when all the embedded oscillators are turned off after entering a low-power mode. Programming the CKSEL and COUNTMODE bits allows controlling whether the LPTIM will use an external clock source or an internal one. When configured to use an external clock source, the CKPOL bits are used to select the external clock signal active edge. If both edges are configured to be active ones, an internal clock signal should also be provided (first configuration). In this case, the internal clock signal frequency should be at least four times higher than the external clock signal frequency. 43.4.5 Glitch filter The LPTIM inputs, either external (mapped to microcontroller GPIOs) or internal (mapped on the chip-level to other embedded peripherals, such as embedded comparators), are protected with digital filters that prevent any glitches and noise perturbations to propagate inside the LPTIM. This is in order to prevent spurious counts or triggers. Before activating the digital filters, an internal clock source should first be provided to the LPTIM. This is necessary to guarantee the proper operation of the filters. DocID029587 Rev 3 1797/3178 1818 Low-power timer (LPTIM) RM0433 The digital filters are divided into two groups: Note: • The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits • The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits. The digital filters sensitivity is controlled by groups. It is not possible to configure each digital filter sensitivity separately inside the same group. The filter sensitivity acts on the number of consecutive equal samples that should be detected on one of the LPTIM inputs to consider a signal level change as a valid transition. Figure 518 shows an example of glitch filter behavior in case of a 2 consecutive samples programmed. Figure 518. Glitch filter timing diagram &/.08; ,QSXW )LOWHURXW FRQVHFXWLYHVDPSOHV FRQVHFXWLYHVDPSOHV )LOWHUHG 06 9 Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches. 43.4.6 Prescaler The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible division ratios: Table 345. Prescaler division ratios 1798/3178 programming dividing factor 000 /1 001 /2 010 /4 011 /8 100 /16 101 /32 110 /64 111 /128 DocID029587 Rev 3 RM0433 43.4.7 Low-power timer (LPTIM) Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: • When TRIGEN[1:0] equals ‘00’, The LPTIM counter is started as soon as one of the CNTSTRT or the SNGSTRT bits is set by software. • The three remaining possible values for the TRIGEN[1:0] are used to configure the active edge used by the trigger inputs. The LPTIM counter starts as soon as an active edge is detected. When TRIGEN[1:0] is different than ‘00’, TRIGSEL[2:0] is used to select which of the 8 trigger inputs is used to start the counter. The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization. If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled). Note: The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these bits when the timer is disabled will be discarded by hardware. 43.4.8 Operating mode The LPTIM features two operating modes: • The Continuous mode: the timer is free running, the timer is started from a trigger event and never stops until the timer is disabled • One-shot mode: the timer is started from a trigger event and stops when reaching the ARR value. A new trigger event will re-start the timer. Any trigger event occurring after the counter starts and before the counter reaches ARR will be discarded. To enable the one-shot counting, the SNGSTRT bit must be set. In case an external trigger is selected, each external trigger event arriving after the SNGSTRT bit is set, and after the counter register has stopped (contains zero value), will start the counter for a new one-shot counting cycle as shown in Figure 519. Figure 519. LPTIM output waveform, Single counting mode configuration $55 &RPSDUH 3:0 ([WHUQDOWULJJHUHYHQW 06Y 9 DocID029587 Rev 3 1799/3178 1818 Low-power timer (LPTIM) RM0433 It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Setonce mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 519. Figure 520. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) $55 &RPSDUH 'LVFDUGHGWULJJHU 3:0 ([WHUQDOWULJJHUHYHQW 06Y 9 In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one-shot counting. To enable the continuous counting, the CNTSTRT bit must be set. In case an external trigger is selected, an external trigger event arriving after CNTSTRT is set will start the counter for continuous counting. Any subsequent external trigger event will be discarded as shown in Figure 521. In case of software start (TRIGEN[1:0] = ‘00’), setting CNTSTRT will start the counter for continuous counting. Figure 521. LPTIM output waveform, Continuous counting mode configuration 'LVFDUGHGWULJJHUV $55 &RPSDUH 3:0 ([WHUQDOWULJJHUHYHQW 06Y 9 SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One-shot mode. The counter (if active) will stop as soon as it reaches ARR. 1800/3178 DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) If the One-shot mode was previously selected, setting CNTSTRT will switch the LPTIM to the Continuous mode. The counter (if active) will restart as soon as it reaches ARR. 43.4.9 Timeout function The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart. A low-power timeout function can be realized. The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event. 43.4.10 Waveform generation Two 16-bit registers, the LPTIM_ARR (autoreload register) and LPTIM_CMP (Compare register), are used to generate several different waveforms on LPTIM output The timer can generate the following waveforms: • The PWM mode: the LPTIM output is set as soon as a match occurs between the LPTIM_CMP and the LPTIM_CNT registers. The LPTIM output is reset as soon as a match occurs between the LPTIM_ARR and the LPTIM_CNT registers • The One-pulse mode: the output waveform is similar to the one of the PWM mode for the first pulse, then the output is permanently reset • The Set-once mode: the output waveform is similar to the One-pulse mode except that the output is kept to the last signal level (depends on the output configured polarity). The above described modes require that the LPTIM_ARR register value be strictly greater than the LPTIM_CMP register value. The LPTIM output waveform can be configured through the WAVE bit as follow: • Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. • Setting the WAVE bit to ‘1’ forces the LPTIM to generate a Set-once mode waveform. The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled. Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. Figure 522 below shows the three possible waveforms that can be generated on the LPTIM output. Also, it shows the effect of the polarity change using the WAVPOL bit. DocID029587 Rev 3 1801/3178 1818 Low-power timer (LPTIM) RM0433 Figure 522. Waveform generation $55 &RPSDUH 3:0 2QHVKRW 3RO 6HWRQFH 3:0 3RO 2QHVKRW 6HWRQFH 069 43.4.11 Register update The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started. The PRELOAD bit controls how the LPTIM_ARR and the LPTIM_CMP registers are updated: • When the PRELOAD bit is reset to ‘0’, the LPTIM_ARR and the LPTIM_CMP registers are immediately updated after any write access. • When the PRELOAD bit is set to ‘1’, the LPTIM_ARR and the LPTIM_CMP registers are updated at the end of the current period, if the timer has been already started. The LPTIM APB interface and the LPTIM kernel logic use different clocks, so there is some latency between the APB write and the moment when these values are available to the counter comparator. Within this latency period, any additional write into these registers must be avoided. The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register. After a write to the LPTIM_ARR register or the LPTIM_CMP register, a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before respectively the ARROK flag or the CMPOK flag be set, will lead to unpredictable results. 1802/3178 DocID029587 Rev 3 RM0433 43.4.12 Low-power timer (LPTIM) Counter mode The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter. In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits. The count modes below can be selected, depending on CKSEL and COUNTMODE values: • CKSEL = 0: the LPTIM is clocked by an internal clock source – COUNTMODE = 0 When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must not be prescaled (PRESC[2:0] = ‘000’). – COUNTMODE = 1 The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM. Consequently, in order not to miss any event, the frequency of the changes on the external Input1 signal should never exceed the frequency of the internal clock provided to the LPTIM. • CKSEL = 1: the LPTIM is clocked by an external clock source COUNTMODE value is don’t care. In this configuration, the LPTIM has no need for an internal clock source (except if the glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as system clock for the LPTIM. This configuration is suitable for operation modes where no embedded oscillator is enabled. For this configuration, the LPTIM counter can be updated either on rising edges or falling edges of the input1 clock signal but not on both rising and falling edges. Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM kernel logic, there is some initial latency (after the LPTIM is enabled) before the counter is incremented. More precisely, the first five active edges on the LPTIM external Input1 (after LPTIM is enable) are lost. 43.4.13 Timer enable The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled. The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled. DocID029587 Rev 3 1803/3178 1818 Low-power timer (LPTIM) 43.4.14 RM0433 Timer counter reset In order to reset the content of LPTIM_CNT register to zero, two reset mechanisms are implemented: • The synchronous reset mechanism: the synchronous reset is controlled by the COUNTRST bit in the LPTIM_CR register. After setting the COUNTRST bit-field to '1', the reset signal is propagated in the LPTIM kernel clock domain. So it is important to note that a few clock pulses of the LPTIM kernel logic will elapse before the reset is taken into account. This will make the LPTIM counter count few extra pluses between the time when the reset is trigger and it become effective. Since the COUNTRST bit is located in the APB clock domain and the LPTIM counter is located in the LPTIM kernel clock domain, a delay of 3 clock cycles of the kernel clock is needed to synchronize the reset signal issued by the APB clock domain when writing '1' to the COUNTRST bit. • The asynchronous reset mechanism: the asynchronous reset is controlled by the RSTARE bit located in the LPTIM_CR register. When this bit is set to '1', any read access to the LPTIM_CNT register will reset its content to zero. Asynchronous reset should be triggered within a timeframe in which no LPTIM core clock is provided. For example when LPTIM Input1 is used as external clock source, the asynchronous reset should be applied only when there is enough insurance that no toggle will occur on the LPTIM Input1. It should be noted that to read reliably the content of the LPTIM_CNT register two successive read accesses must be performed and compared. A read access can be considered reliable when the value of the two read accesses is equal. Unfortunately when asynchronous reset is enabled there is no possibility to read twice the LPTIM_CNT register. Warning: 43.4.15 There is no mechanism inside the LPTIM that prevents the two reset mechanisms from being used simultaneously. So developer should make sure that these two mechanisms are used exclusively. Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to 0 depending on the direction). Therefore you must configure LPTIM_ARR before starting. From the two external input signals, Input1 and Input2, a clock signal is generated to clock the LPTIM counter. The phase between those two signals determines the counting direction. The Encoder mode is only available when the LPTIM is clocked by an internal clock source. The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal clock frequency divided by 4. This is mandatory in order to guarantee a proper operation of the LPTIM. Direction change is signalized by the two Down and Up flags in the LPTIM_ISR register. Also, an interrupt can be generated for both direction change events if enabled through the LPTIM_IER register. 1804/3178 DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be configured in Continuous mode. When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder. Therefore, its content always represents the encoder’s position. The count direction, signaled by the Up and Down flags, correspond to the rotation direction of the encoder rotor. According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting scenarios are possible. The following table summarizes the possible combinations, assuming that Input1 and Input2 do not switch at the same time. Table 346. Encoder counting scenarios Active edge Rising Edge Falling Edge Both Edges Level on opposite signal (Input1 for Input2, Input2 for Input1) Input1 signal Input2 signal Rising Falling Rising Falling High Down No count Up No count Low Up No count Down No count High No count Up No count Down Low No count Down No count Up High Down Up Up Down Low Up Down Down Up The following figure shows a counting sequence for Encoder mode where both-edge sensitivity is configured. Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’). DocID029587 Rev 3 1805/3178 1818 Low-power timer (LPTIM) RM0433 Figure 523. Encoder mode counting sequence 7 7 &RXQWHU XS 43.5 GRZQ XS 06 9 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_IER register: Note: • Compare match • Auto-reload match (whatever the direction if encoder mode) • External trigger event • Autoreload register write completed • Compare register write completed • Direction change (encoder mode), programmable (up / down / both). If any bit in the LPTIM_IER register (Interrupt Enable Register) is set after that its corresponding flag in the LPTIM_ISR register (Status Register) is set, the interrupt is not asserted. Table 347. Interrupt events Interrupt event 1806/3178 Description Compare match Interrupt flag is raised when the content of the Counter register (LPTIM_CNT) matches the content of the Compare register (LPTIM_CMP). Auto-reload match Interrupt flag is raised when the content of the Counter register (LPTIM_CNT) matches the content of the Auto-reload register (LPTIM_ARR). External trigger event Interrupt flag is raised when an external trigger event is detected Auto-reload register write complete Interrupt flag is raised when the write operation to the LPTIM_ARR register is complete. DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Table 347. Interrupt events (continued) Interrupt event Description Compare register write Interrupt flag is raised when the write operation to the LPTIM_CMP register complete is complete. Used in Encoder mode. Two interrupt flags are embedded to signal direction change: – UP flag signals up-counting direction change – DOWN flag signals down-counting direction change. Direction change 43.6 LPTIM registers 43.6.1 LPTIM interrupt and status register (LPTIM_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARROK CMPOK EXTTRIG r r r r r ARRM CMPM r r Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWN: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. Bit 5 UP: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. Bit 4 ARROK: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. If so, a new one can be initiated. Bit 3 CMPOK: Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed. If so, a new one can be initiated. Bit 2 EXTTRIG: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. Bit 1 ARRM: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. Bit 0 CMPM: Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. DocID029587 Rev 3 1807/3178 1818 Low-power timer (LPTIM) 43.6.2 RM0433 LPTIM interrupt clear register (LPTIM_ICR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN CF UPCF ARRO KCF ARRM CF CMPM CF w w w w w CMPO EXTTR KCF IGCF w w Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNCF: Direction change to down Clear Flag Writing 1 to this bit clear the DOWN flag in the LPT_ISR register Bit 5 UPCF: Direction change to UP Clear Flag Writing 1 to this bit clear the UP flag in the LPT_ISR register Bit 4 ARROKCF: Autoreload register update OK Clear Flag Writing 1 to this bit clears the ARROK flag in the LPT_ISR register Bit 3 CMPOKCF: Compare register update OK Clear Flag Writing 1 to this bit clears the CMPOK flag in the LPT_ISR register Bit 2 EXTTRIGCF: External trigger valid edge Clear Flag Writing 1 to this bit clears the EXTTRIG flag in the LPT_ISR register Bit 1 ARRMCF: Autoreload match Clear Flag Writing 1 to this bit clears the ARRM flag in the LPT_ISR register Bit 0 CMPMCF: compare match Clear Flag Writing 1 to this bit clears the CMP flag in the LPT_ISR register 43.6.3 LPTIM interrupt enable register (LPTIM_IER) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DOWNI E UPIE ARRO KIE rw rw rw Res. Res. 1808/3178 Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 CMPO EXTTR ARRMI CMPMI KIE IGIE E E rw rw rw rw RM0433 Low-power timer (LPTIM) Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNIE: Direction change to down Interrupt Enable 0: DOWN interrupt disabled 1: DOWN interrupt enabled Bit 5 UPIE: Direction change to UP Interrupt Enable 0: UP interrupt disabled 1: UP interrupt enabled Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable 0: ARROK interrupt disabled 1: ARROK interrupt enabled Bit 3 CMPOKIE: Compare register update OK Interrupt Enable 0: CMPOK interrupt disabled 1: CMPOK interrupt enabled Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable 0: EXTTRIG interrupt disabled 1: EXTTRIG interrupt enabled Bit 1 ARRMIE: Autoreload match Interrupt Enable 0: ARRM interrupt disabled 1: ARRM interrupt enabled Bit 0 CMPMIE: Compare match Interrupt Enable 0: CMPM interrupt disabled 1: CMPM interrupt enabled Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit is reset to ‘0’) 43.6.4 LPTIM configuration register (LPTIM_CFGR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 TRIGSEL rw rw Res. rw PRESC rw rw 24 ENC 23 22 21 COUNT PRELOAD WAVPOL MODE 20 19 WAVE TIMOUT 18 17 TRIGEN Res. rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 rw rw Res. rw TRGFLT rw rw Res. CKFLT rw 16 CKPOL 0 CKSEL rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 ENC: Encoder mode enable The ENC bit controls the Encoder mode 0: Encoder mode disabled 1: Encoder mode enabled Bit 23 COUNTMODE: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid clock pulse on the LPTIM external Input1 DocID029587 Rev 3 1809/3178 1818 Low-power timer (LPTIM) RM0433 Bit 22 PRELOAD: Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality 0: Registers are updated after each APB bus write access 1: Registers are updated at the end of the current LPTIM period Bit 21 WAVPOL: Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers Bit 20 WAVE: Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 1: Activate the Set-once mode Bit 19 TIMOUT: Timeout enable The TIMOUT bit controls the Timeout feature 0: a trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the counter Bits18:17 TRIGEN[1:0]: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges Bit 16 Reserved, must be kept at reset value. Bits 15:13 TRIGSEL[2:0]: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext_trig0 001: lptim_ext_trig1 010: lptim_ext_trig2 011: lptim_ext_trig3 100: lptim_ext_trig4 101: lptim_ext_trig5 110: lptim_ext_trig6 111: lptim_ext_trig7 Bit 12 Reserved, must be kept at reset value. 1810/3178 DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Bits 11:9 PRESC[2:0]: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 Bit 8 Reserved, must be kept at reset value. Bits 7:6 TRGFLT[1:0]: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. Bit 5 Reserved, must be kept at reset value. DocID029587 Rev 3 1811/3178 1818 Low-power timer (LPTIM) RM0433 Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. Bits 2:1 CKPOL[1:0]: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed If the LPTIM is configured in Encoder mode (ENC bit is set): 00: the encoder sub-mode 1 is active 01: the encoder sub-mode 2 is active 10: the encoder sub-mode 3 is active Refer to Section 43.4.15: Encoder mode for more details about Encoder mode sub-modes. Bit 0 CKSEL: Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 1: LPTIM is clocked by an external clock source through the LPTIM external Input1 Caution: The LPTIM_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit is reset to ‘0’). 43.6.5 LPTIM control register (LPTIM_CR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RST ARE COUN TRST CNT STRT SNG STRT ENA BLE w rs rw rw rw Res. Res. 1812/3178 Res. Res. Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Bits 31:5 Reserved, must be kept at reset value. Bit 4 RSTARE: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content. Caution: This bitfield is write-only. This means that the bit cannot be read back to verify the value which has been written. As an example, if this bit is set to 1, attempting to read it back will return 0 even if the "Reset after read" function is enabled (due to the fact that this bitfield has previously been written to 1). To turn off the "Reset after read" or to make sure that it has already been turned off, this bit should be reset (by programming it to 0) even if it already contains 0. Bit 3 COUNTRST: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). Caution: COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. Bit 2 CNTSTRT: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware. Bit 1 SNGSTRT: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware. Bit 0 ENABLE: LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled DocID029587 Rev 3 1813/3178 1818 Low-power timer (LPTIM) 43.6.6 RM0433 LPTIM compare register (LPTIM_CMP) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMP[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP[15:0]: Compare value CMP is the compare value used by the LPTIM. The LPTIM_CMP register’s content must only be modified when the LPTIM is enabled (ENABLE bit is set to ‘1’). 43.6.7 LPTIM autoreload register (LPTIM_ARR) Address offset: 0x18 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ARR[15:0]: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP[15:0] value. The LPTIM_ARR register’s content must only be modified when the LPTIM is enabled (ENABLE bit is set to ‘1’). 43.6.8 LPTIM counter register (LPTIM_CNT) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] r 1814/3178 DocID029587 Rev 3 RM0433 Low-power timer (LPTIM) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal. 43.6.9 LPTIM configuration register 2 (LPTIM_CFGR2) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5 4 3 2 1 0 Res. Res. 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IN2SEL rw rw IN1SEL rw rw Bits 31:6 Reserved, must be kept at reset value. Bits 5:4 IN2SEL[1:0]: LPTIMx Input 2 selection The IN2SEL bits control the LPTIMx Input 2 multiplexer, which connect LPTIMx Input 2 to one of the available inputs. 00: lptim_in2_mux0 01: lptim_in2_mux1 10: lptim_in2_mux2 11: lptim_in2_mux3 For connection details refer to Table 341: LPTIM1 Input 2 connection for LPTIM1 Input 2 connection and to Table 343: LPTIM2 Input 2 connection for LPTIM2 input 2 connection. Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 IN1SEL[1:0]: LPTIMx Input 1 selection The IN1SEL bits control the LPTIMx Input 1 multiplexer, which connects LPTIMx Input 1 to one of the available inputs. 00: lptim_in1_mux0 01: lptim_in1_mux1 10: lptim_in1_mux2 11: lptim_in1_mux3 For connection details refer to table Table 340: LPTIM1 Input 1 connection for LPTIM1 input 1 connection and to Table 342: LPTIM2 Input 1 connection for LPTIM2 Input 1 connection. Caution: The LPTIM_CFGR2 register may only be modified when the LPTIM is disabled (ENABLE bit cleared). DocID029587 Rev 3 1815/3178 1818 Low-power timer (LPTIM) 43.6.10 RM0433 LPTIM3 configuration register 2 (LPTIM3_CFGR2) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IN1SEL rw rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 IN1SEL: LPTIM3 Input1 selection The IN1SEL bits control the LPTIM3 Input 1 multiplexer, which connects LPTIM3 Input 1 to one of the available inputs. 00: lptim_in1_mux0 01: lptim_in1_mux1 10: lptim_in1_mux2 11: lptim_in1_mux3 For connection details refer to Table 344: LPTIM3 Input 1 connection. Caution: 1816/3178 The LPTIM3_CFGR2 registers must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’). DocID029587 Rev 3 0x14 0x18 0x1C 0x24 LPTIM_CMP LPTIM_ARR LPTIM_CNT LPTIM_CFGR2 0 0 0 0 0 0 0 0 Reset value Reset value Reset value Reset Value DocID029587 Rev 3 0 0 0 0 0 0 0 0 IN1SEL[1:0] Reset value Res. Res. 0x10 LPTIM_CFGR IN2SEL[1:0] 0x0C CKSEL CKPOL[1:0] CKFLT[1:0] Res. TRGFLT[1:0] Res. PRESC[2:0] Res. TRIGSEL[2:0] Res. TRIGEN[1:0] Res. Res. Res. Res. Res. Res. Res. ENC COUNTMODE PRELOAD WAVPOL WAVE TIMOUT LPTIM_ISR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARROK CMPOK EXTTRIG ARRM CMPM Reset value 0 0 0 0 0 0 0 LPTIM_ICR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNCF UPCF ARROKCF CMPOKCF EXTTRIGCF ARRMCF CMPMCF Reset value 0 0 0 0 0 0 0 LPTIM_IER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNIE UPIE ARROKIE CMPOKIE EXTTRIGIE ARRMIE CMPMIE 0x08 LPTIM_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RSTARE COUNTRST CNTSTRT SNGSTRT ENABLE 0x04 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x00 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 43.6.11 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RM0433 Low-power timer (LPTIM) LPTIM register map The following table summarizes the LPTIM registers. Table 348. LPTIM register map and reset values Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CNT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1817/3178 1818 Low-power timer (LPTIM) RM0433 0 0 Reset Value Refer to Section 2.2.2 on page 105 for the register boundary addresses. 1818/3178 IN1SEL 0x24 LPTIM3_ CFGR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 348. LPTIM register map and reset values (continued) DocID029587 Rev 3 RM0433 System window watchdog (WWDG) 44 System window watchdog (WWDG) 44.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates a reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. A reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. The WWDG clock is prescaled from the APB clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. The WWDG is best suited for applications which require the watchdog to react within an accurate timing window. 44.2 WWDG main features • Programmable free-running downcounter • Conditional reset • 44.3 – Reset (if watchdog activated) when the downcounter value becomes less than 0x40 – Reset (if watchdog activated) if the downcounter is reloaded outside the window (see Figure 525) Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 0x40. WWDG functional description If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent a reset. This operation must occur only when the counter value is lower than the window register value and higher than 0x3F. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0. Refer to Figure 524 for the WWDG block diagram and to Section 44.3.2: WWDG internal signals. DocID029587 Rev 3 1819/3178 1825 System window watchdog (WWDG) 44.3.1 RM0433 WWDG block diagram Figure 524. Watchdog block diagram ::'* $3%EXV 5HJLVWHUV &03 ZKHQ 7> @!:> @ :> @ &03 ::'*B&)5 ::'*B65 :ULWHWR ::'*B&5 ZGKZRQ 7> @ :'*7*> @ · :'*$ 7 (:, (:,) FQWBRXW /RJLF SUHORDG [" UHDGEDFN 7> @ ::'*B&5 SFON ZZGJB RXWBUVW ZZGJ BLW ELW'RZQ&RXQWHU &17 · 06Y 9 44.3.2 WWDG internal signals Table 349 gives the list of WWDG internal signals. Table 349. WWDG internal input/output signals 44.3.3 Signal name Signal type pclk Digital input APB bus clock wwdg1_out_rst Digital output WWDG1 reset signal output wwdg1_it Digital output WWDG1 interrupt output Description Enabling the watchdog The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. 44.3.4 Controlling the downcounter This downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 525). The Configuration register (WWDG_CFR) contains the high limit of the window: 1820/3178 DocID029587 Rev 3 RM0433 System window watchdog (WWDG) To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 525 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 44.3.5 Advanced watchdog interrupt feature The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device. In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated. 44.3.6 How to program the watchdog timeout You can use the formula in Figure 525 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. DocID029587 Rev 3 1821/3178 1825 System window watchdog (WWDG) RM0433 Figure 525. Window watchdog timing diagram &17'RZQFRXQWHU 5HIUHVKQRWDOORZHG 5HIUHVKDOORZHG 7> @ :> @ [) 7LPH 7SFON[ [:'*7% [ [ [) ZZGJ[BHZLW (:,) ZZGJ[BUVW 7ELW 06Y9 The formula to calculate the timeout value is given by: WDGTB[2:0] t WWDG = t PCLK × 4096 × 2 × ( T [ 5:0 ] + 1 ) ( ms ) where: tWWDG: WWDG timeout tPCLK: APB clock period measured in ms 4096: value corresponding to internal divider As an example, lets assume APB frequency is equal to 48 MHz, WDGTB[2:0] is set to 3 and T[5:0] is set to 63: 3 t WWDG = ( 1 ⁄ 48000 ) × 4096 × 2 × ( 63 + 1 ) = 43.69ms Refer to the datasheet for the minimum and maximum values of the tWWDG. 44.3.7 Debug mode When the CPU enters debug mode, WWDG1 counter either continue to work normally or stop, depending on DBGMCU_APB3LFZ1. For more details, refer to Section 60: Debug infrastructure. 1822/3178 DocID029587 Rev 3 RM0433 System window watchdog (WWDG) 44.4 .WWDG registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 44.4.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0] rs rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[2:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). DocID029587 Rev 3 1823/3178 1825 System window watchdog (WWDG) 44.4.2 RM0433 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 6 5 4 3 2 1 0 Res. Res. rw rw rw WDGTB[2:0] rw rw 10 9 8 7 Res. EWI Res. Res. rw rs W[6:0] rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:11 WDGTB[2:0]: Timer base The timebase of the prescaler can be modified as follows: 000: CK Counter Clock (PCLK div 4096) div 1 001: CK Counter Clock (PCLK div 4096) div 2 010: CK Counter Clock (PCLK div 4096) div 4 011: CK Counter Clock (PCLK div 4096) div 8 100: CK Counter Clock (PCLK div 4096) div 16 101: CK Counter Clock (PCLK div 4096) div 32 110: CK Counter Clock (PCLK div 4096) div 64 111: CK Counter Clock (PCLK div 4096) div 128 Bit 10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. Bits 8:7 Reserved, must be kept at reset value. Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 44.4.3 Status register (WWDG_SR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF rc_w0 1824/3178 DocID029587 Rev 3 RM0433 System window watchdog (WWDG) Bits 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not enabled. 44.4.4 WWDG register map The following table gives the WWDG register map and reset values. 1 1 1 1 1 1 1 Res. 1 EWIF 1 1 1 1 1 1 Res. Res. Res. Res. W[6:0] Res. Res. Res. EWI Res. T[6:0] Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x08 WWDG_ SR Res. Reset value WDGTB [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG_CFR Res. 0x04 0 Res. Reset value WDGA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG_ CR Res. 0x00 Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 350. WWDG register map and reset values Register name Reset value 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID029587 Rev 3 1825/3178 1825 Independent watchdog (IWDG) RM0433 45 Independent watchdog (IWDG) 45.1 Introduction The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The IWDG is best suited for applications that require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. For further information on the window watchdog, refer to Section 44 on page 1819. 45.2 IWDG main features • Free-running downcounter • Clocked from an independent RC oscillator (can operate in Standby and Stop modes) • Conditional Reset – Reset (if watchdog activated) when the downcounter value becomes lower than 0x000 – Reset (if watchdog activated) if the downcounter is reloaded outside the window 45.3 IWDG functional description 45.3.1 IWDG block diagram Figure 526 shows the functional blocks of the independent watchdog module. Figure 526. Independent watchdog block diagram 9'' 3UHVFDOHUUHJLVWHU 6WDWXVUHJLVWHU 5HORDGUHJLVWHU ,:'*B35 ,:'*B65 ,:'*B5/5 OVLBFN N+] .H\UHJLVWHU ,:'*B.5 ELWUHORDG YDOXH ELW SUHVFDOHU ELW GRZQFRXQWHU LZGJBRXWB UVW 9''YROWDJHGRPDLQ 06Y 9 1. The watchdog function is implemented in the VDD voltage domain that is still functional in Stop and 1826/3178 DocID029587 Rev 3 RM0433 Independent watchdog (IWDG) Standby modes. When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the Key register (IWDG_KR), the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. 45.3.2 IWDG internal signals Table 351 gives the list of IWDG internal signals. Table 351. IWDG internal input/output signals 45.3.3 Signal name Signal type lsi_ck Digital input LSI clock iwdg1_out_rst Digital output IWDG1 reset signal output Description Window option The IWDG can also work as a window watchdog by setting the appropriate window in the Window register (IWDG_WINR). If the reload operation is performed while the counter is greater than the value stored in the Window register (IWDG_WINR), then a reset is provided. The default value of the Window register (IWDG_WINR) is 0x0000 0FFF, so if it is not updated, the window option is disabled. As soon as the window value is changed, a reload operation is performed in order to reset the downcounter to the Reload register (IWDG_RLR) value and ease the cycle number calculation to generate the next reload. Configuring the IWDG when the window option is enabled Note: 1. Enable the IWDG by writing 0x0000 CCCC in the Key register (IWDG_KR). 2. Enable register access by writing 0x0000 5555 in the Key register (IWDG_KR). 3. Write the IWDG prescaler by programming Prescaler register (IWDG_PR) from 0 to 7. 4. Write the Reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Write to the Window register (IWDG_WINR). This automatically refreshes the counter value in the Reload register (IWDG_RLR). Writing the window value allows to refresh the Counter value by the RLR when Status register (IWDG_SR) is set to 0x0000 0000. Configuring the IWDG when the window option is disabled When the window option it is not used, the IWDG can be configured as follows: DocID029587 Rev 3 1827/3178 1834 Independent watchdog (IWDG) 45.3.4 RM0433 1. Enable the IWDG by writing 0x0000 CCCC in the Key register (IWDG_KR). 2. Enable register access by writing 0x0000 5555 in the Key register (IWDG_KR). 3. Write the prescaler by programming the Prescaler register (IWDG_PR) from 0 to 7. 4. Write the Reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA). Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register (IWDG_KR) is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window. 45.3.5 Low-power freeze Depending on the IWDG_FZ_STOP and IWDG_FZ_STBY options configuration, the IWDG can continue counting or not during the Stop mode and the Standby mode respectively. If the IWDG is kept running during Stop or Standby modes, it can wake up the device from this mode. Refer to Section 3.3.11: FLASH option bytes for more details. 45.3.6 Behavior in Stop and Standby modes Once running, the IWDG cannot be stopped. 45.3.7 Register access protection Write access to Prescaler register (IWDG_PR), Reload register (IWDG_RLR) and Window register (IWDG_WINR) is protected. To modify them, the user must first write the code 0x0000 5555 in the Key register (IWDG_KR). A write access to this register with a different value will break the sequence and register access will be protected again. This is the case of the reload operation (writing 0x0000 AAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value or the window value is on going. 45.3.8 Debug mode When the microcontroller enters Debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. 1828/3178 DocID029587 Rev 3 RM0433 Independent watchdog (IWDG) 45.4 IWDG registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 45.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w KEY[15:0] w w w w w w w w w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 45.3.7: Register access protection) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected) DocID029587 Rev 3 1829/3178 1834 Independent watchdog (IWDG) 45.4.2 RM0433 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0] rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected see Section 45.3.7: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the Status register (IWDG_SR) must be reset in order to be able to change the prescaler divider. 000: divider /4 001: divider /8 010: divider /16 011: divider /32 100: divider /64 101: divider /128 110: divider /256 111: divider /256 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the Status register (IWDG_SR) is reset. 1830/3178 DocID029587 Rev 3 RM0433 Independent watchdog (IWDG) 45.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. RL[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 RL[11:0]: Watchdog counter reload value These bits are write access protected see Register access protection. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the Key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the Status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the Status register (IWDG_SR) is reset. DocID029587 Rev 3 1831/3178 1834 Independent watchdog (IWDG) 45.4.4 RM0433 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 WVU: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic “window” = 1 Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. Bit 0 PVU: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. Note: 1832/3178 If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. DocID029587 Rev 3 RM0433 Independent watchdog (IWDG) 45.4.5 Window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. WIN[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 WIN[11:0]: Watchdog counter window value These bits are write access protected, see Section 45.3.7, they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the Status register (IWDG_SR) must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the Status register (IWDG_SR) is reset. DocID029587 Rev 3 1833/3178 1834 0x0C 0x10 1834/3178 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 1 1 1 1 1 WIN[11:0] 1 1 1 1 PVU Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 RVU 1 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 WVU 1 Res. 1 Res. 1 Res. 1 Res. Res. Res. 1 Res. Res. Res. 1 Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Res. Res. Reset value Res. IWDG_WINR Res. IWDG_SR Res. 0x08 IWDG_RLR Res. 0x04 IWDG_PR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IWDG_KR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name Res. 0x00 Res. Offset Res. 45.4.6 Res. Independent watchdog (IWDG) RM0433 IWDG register map The following table gives the IWDG register map and reset values. Table 352. IWDG register map and reset values KEY[15:0] 0 PR[2:0] Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 0 0 RL[11:0] 0 0 0 0 0 0 1 1 1 RM0433 Real-time clock (RTC) 46 Real-time clock (RTC) 46.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability. Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy. After Backup domain reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset). DocID029587 Rev 3 1835/3178 1880 Real-time clock (RTC) 46.2 RM0433 RTC main features The RTC unit main features are the following (see Figure 528: Detailed RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. • Daylight saving compensation programmable by software. • Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields. • Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Accurate synchronization with an external clock using the subsecond shift feature. • Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds • Time-stamp function for event saving • Tamper detection event with configurable filter and internal pull-up • Maskable interrupts/events: • – Alarm A – Alarm B – Wakeup interrupt – Time-stamp – Tamper detection 32 backup registers. 46.3 RTC functional description 46.3.1 RTC block diagram Figure 527. RTC block overview ELW$3%EXV [ 57&B7$03[ 57&B76 57&B5(),1 $3% LQWHUIDFH 57&B287 57&NHUQHO UWFBZXW UWFBDOUD UWFBSFON UWFBDOUE UWFBWDPS[ UWFBNHUBFN 57&&/. [ UWFBWV 06Y9 1836/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) Figure 528. Detailed RTC block diagram 57&B7$03 %DFNXSUHJLVWHUV DQG57&WDPSHU FRQWUROUHJLVWHU 57&B7$03 57&B7$03 7$03[) 7LPHVWDPS UHJLVWHUV 57&B76 57&B5(),1 76) /6( +] 'LYLGHG+6( 57&&/. /6, 57&B&$/5 6PRRWK FDOLEUDWLRQ 57&B35(5 $V\QFKURQRXV ELWSUHVFDOHU GHIDXOW FNBDSUH GHIDXOW+] FNBVSUH GHIDXOW+] 57&B35(5 6\QFKURQRXV ELWSUHVFDOHU GHIDXOW &DOHQGDU 6KDGRZUHJLVWHU 57&B665 :8&.6(/> @ 6KDGRZUHJLVWHUV 57&B75 57&B'5 3UHVFDOHU 57&B&$/,% 57&B$/$50 2XWSXW FRQWURO 57&B287 57&B:875 :87) ELWZDNHXS DXWRUHORDGWLPHU 26(/> @ $ODUP$ 57&B$/50$5 57&B$/50$665 $/5$) $ODUP% 57&B$/50%5 57&B$/50%665 $/5%) 069 DocID029587 Rev 3 1837/3178 1880 Real-time clock (RTC) RM0433 Figure 529. Tamper detection 57&B7$03 57&B7$03 57&WDPSHU DQGEDFNXS UHJLVWHUV 57&B7$03 3:5B&5 7DPSHURXW 9ROWDJH PRQLWRU FOHDU .%EDFNXS 65$0 7HPSHUDWXUH PRQLWRU 06Y 9 The RTC includes: • Two alarms • Three tamper events from I/Os – Tamper detection erases the backup registers and the backup RAM. – In addition, the tamper detection forbids software access to the backup SRAM until its erase operation is finished. Refer to Section 46.3.15: Tamper detection – The tamper3 event detection is generated either by an event on I/O, or by an over or under voltage of the RTC power supply domain, or by an over or under temperature detection. These voltage and temperature monitor detections are enabled in the PWR control register 2 (PWR_CR2). • One timestamp event from I/O • Tamper event detection can generate a timestamp event • Timestamp can be generated when a switch to VBAT occurs • 32 x 32-bit backup registers – • • 46.3.2 The backup registers (RTC_BKPxR) are implemented in the RTC domain that remains powered-on by VBAT when the VDD power is switched off. Output functions: RTC_OUT which selects one of the following two outputs: – RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz). This output is enabled by setting the COE bit in the RTC_CR register. – RTC_ALARM: This output is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select the Alarm A, Alarm B or Wakeup outputs. Input functions: – RTC_TS: timestamp event – RTC_TAMP1: tamper1 event detection – RTC_TAMP2: tamper2 event detection – RTC_TAMP3: tamper3 event detection – RTC_REFIN: 50 or 60 Hz reference clock input RTC pins and internal signals Table 353. RTC pins and internal signals Signal name 1838/3178 Signal type Description RTC_TS Input Timestamp input RTC_TAMPx (x = 1,2,3) Input Tamper input DocID029587 Rev 3 RM0433 Real-time clock (RTC) Table 353. RTC pins and internal signals (continued) Signal name Signal type RTC_REFIN Input RTC_OUT 46.3.3 Description Reference clock input Output RTC output rtc_ker_ck (RTCCLK) Internal input RTC clock source (LSE clock, LSI clock and HSE clock) rtc_pclk Internal input RTC APB interface clock rtc_wut Internal output RTC wakeup event output for on chip peripherals rtc_alra Internal output RTC Alarm A event output for on chip peripherals rtc_alrb Internal output RTC Alarm B event output for on chip peripherals rtc_tampx Internal output RTC Tamper[1..3] event output for on chip peripherals rtc_ts Internal output RTC Timestamp event output for on chip peripherals GPIOs controlled by the RTC RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). PC13 pin configuration is controlled by the RTC, whatever the PC13 GPIO configuration, except for the RTC_ALARM output open-drain mode. The RTC functions mapped on PC13 are available in all low-power modes and in VBAT mode. The output mechanism follows the priority order shown in Table 354. Table 354. RTC pin PC13 configuration(1) OSEL[1:0] bits PC13 Pin configuration (RTC_ALARM and function output enable) COE bit (RTC_CALIB output enable) RTC_OUT _RMP bit 01 or 10 or 11 Don’t care RTC_ALARM output PP 01 or 10 or 11 Don’t care RTC_CALIB output PP 00 1 0 00 0 Don’t care 00 1 01 or 10 or 11 0 00 0 00 1 01 or 10 or 11 0 RTC_TAMP1 input floating RTC_TS and RTC_TAMP1 input floating TAMP1E bit (RTC_TAMP1 input enable) (RTC_TS input enable) 0 Don’t care Don’t care 1 Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care 1 0 Don’t care 1 1 0 RTC_ALARM output OD TSE bit RTC_ALARM _TYPE bit 1 0 1 1 Don’t care 1 DocID029587 Rev 3 1839/3178 1880 Real-time clock (RTC) RM0433 Table 354. RTC pin PC13 configuration(1) (continued) OSEL[1:0] bits PC13 Pin configuration (RTC_ALARM and function output enable) COE bit (RTC_CALIB output enable) RTC_OUT 00 0 Don’t care 00 1 01 or 10 or 11 0 00 0 00 1 01 or 10 or 11 0 RTC_TS input floating Wakeup pin or Standard GPIO _RMP bit TSE bit RTC_ALARM _TYPE bit TAMP1E bit (RTC_TAMP1 input enable) (RTC_TS input enable) Don’t care 0 1 Don’t care 0 0 1 Don’t care 1 1. OD: open drain; PP: push-pull. In addition, it is possible to remap RTC_OUT on PB2 pin thanks to RTC_OUT_RMP bit. In this case it is mandatory to configure PB2 GPIO registers as alternate function with the correct type. The remap functions are shown in Table 355. Table 355. RTC_OUT mapping OSEL[1:0] bits (RTC_ALARM output enable) COE bit (RTC_CALIB output enable) 00 0 00 1 01 or 10 or 11 RTC_OUT_RMP bit RTC_OUT on PC13 RTC_OUT on PB2 - - RTC_CALIB - Don’t care RTC_ALARM - 00 0 - - 00 1 - RTC_CALIB 01 or 10 or 11 0 - RTC_ALARM 01 or 10 or 11 1 RTC_ALARM RTC_CALIB 0 1 The table below summarizes the RTC pins and functions capability in all modes. Table 356. RTC functions over modes 1840/3178 Pin RTC functions Functional in all lowpower modes except Standby modes Functional in Standby mode Functional in VBAT mode PC13 RTC_TAMP1 RTC_TS RTC_OUT YES YES YES PI8 RTC_TAMP2 YES YES YES PC1 RTC_TAMP3 YES YES YES DocID029587 Rev 3 RM0433 Real-time clock (RTC) Table 356. RTC functions over modes (continued) 46.3.4 Pin RTC functions Functional in all lowpower modes except Standby modes Functional in Standby mode Functional in VBAT mode PB2 RTC_OUT YES NO NO PB15 RTC_REFIN YES NO NO Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 8: Reset and Clock Control (RCC). A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 528: Detailed RTC block diagram): Note: • A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register. • A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register. When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz. The minimum division factor is 1 and the maximum division factor is 222. This corresponds to a maximum input frequency of around 4 MHz. fck_apre is given by the following formula: f RTCCLK f CK_APRE = --------------------------------------PREDIV_A + 1 The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S. fck_spre is given by the following formula: f RTCCLK f CK_SPRE = ----------------------------------------------------------------------------------------------( PREDIV_S + 1 ) × ( PREDIV_A + 1 ) The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 46.3.7: Periodic auto-wakeup for details). DocID029587 Rev 3 1841/3178 1880 Real-time clock (RTC) 46.3.5 RM0433 Real-time clock and calendar The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration. • RTC_SSR for the subseconds • RTC_TR for the time • RTC_DR for the date Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 46.6.4: RTC initialization and status register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods. When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers. When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock (fRTCCLK). The shadow registers are reset by system reset. 46.3.6 Programmable alarms The RTC unit provides programmable alarm: Alarm A and Alarm B. The description below is given for Alarm A, but can be translated in the same way for Alarm B. The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior. Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the RTC_CR register. 46.3.7 Periodic auto-wakeup The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits. The wakeup function is enabled through the WUTE bit in the RTC_CR register. 1842/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) The wakeup timer clock input can be: • RTC clock (RTCCLK) divided by 2, 4, 8, or 16. When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61 µs. • ck_spre (usually 1 Hz internal clock) When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts: – from 1s to 18 hours when WUCKSEL [2:1] = 10 – and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is added to the 16-bit counter current value.When the initialization sequence is complete (see Programming the wakeup timer on page 1844), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes. The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be configured through the POL bit in the RTC_CR register. System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wakeup timer. 46.3.8 RTC initialization and configuration RTC register access The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0. RTC register write protection After system reset, the RTC registers are protected against parasitic write access by clearing the DBP bit in the PWR_CR1 register (refer to the power control section). DBP bit must be set in order to enable RTC registers write access. After Backup domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. The following steps are required to unlock the write protection on all the RTC registers except for RTC_TAMPCR, RTC_BKPxR, RTC_OR and RTC_ISR[13:8]. 1. Write ‘0xCA’ into the RTC_WPR register. 2. Write ‘0x53’ into the RTC_WPR register. Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset. DocID029587 Rev 3 1843/3178 1880 Real-time clock (RTC) RM0433 Calendar initialization and configuration To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required: 1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. 2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register. 4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register. 5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles. When the initialization sequence is complete, the calendar starts counting. Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its Backup domain reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register. Daylight saving time The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register. Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure. In addition, the software can use the BKP bit to memorize this operation. Programming the alarm A similar procedure must be followed to program or update the programmable alarms. The procedure below is given for Alarm A but can be translated in the same way for Alarm B. Note: 1. Clear ALRAE in RTC_CR to disable Alarm A. 2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR). 3. Set ALRAE in the RTC_CR register to enable Alarm A again. Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization. Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR): 1844/3178 DocID029587 Rev 3 RM0433 46.3.9 Real-time clock (RTC) 1. Clear WUTE in RTC_CR to disable the wakeup timer. 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again. The wakeup timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK clock cycles after WUTE is cleared, due to clock synchronization. Reading the calendar When BYPSHAD control bit is cleared in the RTC_CR register To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism. If the APB clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB clock frequency must never be lower than the RTC clock frequency. The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers. After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers. The RSF bit must be cleared after wakeup and not before entering low-power mode. After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values. After an initialization (refer to Calendar initialization and configuration on page 1844): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. After synchronization (refer to Section 46.3.11: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting DocID029587 Rev 3 1845/3178 1880 Real-time clock (RTC) RM0433 from low-power modes (STOP or Standby), since the shadow registers are not updated during these modes. When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register. Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to complete. 46.3.10 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are reset to their default values by a Backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper configuration register (RTC_TAMPCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR), and the Option register (RTC_OR). In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if the reset source is different from the Backup domain reset one (refer to the RTC clock section of the Reset and clock controller for details on the list of RTC clock sources not affected by system reset). When a Backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values. 46.3.11 RTC synchronization The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR. RTC_SSR contains the value of the synchronous prescaler counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution of 1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF. However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the asynchronous prescaler output increases, which may increase the RTC dynamic consumption. The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the 1846/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock. If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of second, so this will advance the clock. Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow will occur. As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed. Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON=1. 46.3.12 RTC reference clock detection The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz). Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock. The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A smaller window of 3 ck_apre periods is used for subsequent calendar updates. Each time the reference clock is detected in the window, the asynchronous prescaler which outputs the ck_apre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little for them to be aligned with the reference clock. If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge. When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values: Note: • PREDIV_A = 0x007F • PREVID_S = 0x00FF RTC_REFIN clock detection is not available in Standby mode. DocID029587 Rev 3 1847/3178 1880 Real-time clock (RTC) 46.3.13 RM0433 RTC smooth digital calibration The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time. The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or 32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit counter, cal_cnt[19:0], clocked by RTCCLK. The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle. Note: • Setting CALM[1] to 1 causes two additional cycles to be masked • Setting CALM[2] to 1 causes four additional cycles to be masked • and so on up to CALM[8] set to 1 which causes 256 clocks to be masked. CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the 32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1 causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800). While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle. Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of about 0.954 ppm. The formula to calculate the effective calibrated frequency (FCAL) given the input frequency (FRTCCLK) is as follows: FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)] Calibration when PREDIV_A<3 The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0. To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to 244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits. With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other 1848/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less). If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows: FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)] In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz. Verifying the RTC calibration RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period. However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration. • By default, the calibration cycle period is 32 seconds. Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution). • CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period. In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1. • CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration cycle period. In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1. Re-calibration on-the-fly The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow process: 1. Poll the RTC_ISR/RECALPF (re-calibration pending flag). 2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1 3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect. DocID029587 Rev 3 1849/3178 1880 Real-time clock (RTC) 46.3.14 RM0433 Time-stamp function Time-stamp is enabled by setting the TSE or ITSE bits of RTC_CR register to 1. When TSE is set: The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a time-stamp event is detected on the RTC_TS pin. When ITSE is set: The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when an internal time-stamp event is detected. The internal timestamp event is generated by the switch to the VBAT supply. When a time-stamp event occurs, due to internal or external event, the time-stamp flag bit (TSF) in RTC_ISR register is set. In case the event is internal, the ITSF flag is also set in RTC_ISR register. By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp event occurs. If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization process. There is no delay in the setting of TSOVF. This means that if two time-stamp events are close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is recommended to poll TSOVF only after TSF has been set. Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the same moment, the application must not write ‘0’ into TSF bit unless it has already read it to ‘1’. Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS control bit in Section 46.6.16: RTC tamper configuration register (RTC_TAMPCR). 46.3.15 Tamper detection The RTC_TAMPx input events can be configured either for edge detection, or for level detection with filtering. The tamper detection can be configured for the following purposes: • erase the RTC backup registers and backup SRAM (default configuration) • generate an interrupt, capable to wakeup from Stop and Standby modes • generate a hardware trigger for the low-power timers RTC backup registers The backup registers (RTC_BKPxR) are not reset by system reset or when the device wakes up from Standby mode. The backup registers are reset when a tamper detection event occurs (see Section 46.6.20: RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 1851) 1850/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) except if the TAMPxNOERASE bit is set, or if TAMPxMF is set in the RTC_TAMPCR register. Tamper detection initialization Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the RTC_TAMPCR register. Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR register. When TAMPxMF is cleared: The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided below: • 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering) • 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event) • No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0 A new tamper occurring on the same pin during this period and as long as TAMPxF is set cannot be detected. When TAMPxMF is set: A new tamper occurring on the same pin cannot be detected during the latency described above and 2.5 ck_rtc additional cycles. By setting the TAMPIE bit in the RTC_TAMPCR register, an interrupt is generated when a tamper detection event occurs (when TAMPxF is set). Setting TAMPIE is not allowed when one or more TAMPxMF is set. When TAMPIE is cleared, each tamper pin event interrupt can be individually enabled by setting the corresponding TAMPxIE bit in the RTC_TAMPCR register. Setting TAMPxIE is not allowed when the corresponding TAMPxMF is set. Trigger output generation on tamper event The tamper event detection can be used as trigger input by the low-power timers. When TAMPxMF bit in cleared in RTC_TAMPCR register, the TAMPxF flag must be cleared by software in order to allow a new tamper detection on the same pin. When TAMPxMF bit is set, the TAMPxF flag is masked, and kept cleared in RTC_ISR register. This configuration allows to trig automatically the low-power timers in Stop mode, without requiring the system wakeup to perform the TAMPxF clearing. In this case, the backup registers are not cleared. Timestamp on tamper event With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time that TSF or TSOVF is set. Edge detection on tamper inputs If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when either a rising edge or a falling edge is observed depending on the corresponding DocID029587 Rev 3 1851/3178 1880 Real-time clock (RTC) RM0433 TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated when edge detection is selected. Caution: When using the edge detection, it is recommended to check by software the tamper pin level just after enabling the tamper detection (by reading the GPIO registers), and before writing sensitive values in the backup registers, to ensure that an active edge did not occur before enabling the tamper event detection. When TAMPFLT="00" and TAMPxTRG = 0 (rising edge detection), a tamper event may be detected by hardware if the tamper input is already at high level before enabling the tamper detection. After a tamper event has been detected and cleared, the RTC_TAMPx should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (RTC_BKPxR). This prevents the application from writing to the backup registers while the RTC_TAMPx input value still indicates a tamper detection. This is equivalent to a level detection on the RTC_TAMPx input. Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the RTC_TAMPx is mapped should be externally tied to the correct level. Level detection with filtering on RTC_TAMPx inputs Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bits. The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the RTC_TAMPx inputs. The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection. Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors. 46.3.16 Calibration clock output When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S = 0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift operation is on going and may toggle during the shift operation (SHPF=1). 1852/3178 DocID029587 Rev 3 RM0433 Note: Real-time clock (RTC) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured as output. When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the asynchronous prescaler. When COSEL bit is set, the RTC_CALIB output is the output of the 8th stage of the synchronous prescaler. 46.3.17 Alarm output The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm output RTC_ALARM, and to select the function which is output. These functions reflect the contents of the corresponding flags in the RTC_ISR register. The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1. Alarm output The RTC_ALARM pin can be configured in output open drain or output push-pull using the control bit RTC_ALARM_TYPE in the RTC_OR register. Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't care and must be kept cleared). When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured as output. 46.4 RTC low-power modes Table 357. Effect of low-power modes on RTC Mode 46.5 Description Stop Peripheral registers content is kept. Standby The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Standby mode. RTC interrupts All RTC interrupts are connected to the EXTI controller. Refer to Section 20: Extended interrupt and event controller (EXTI). To enable the RTC Alarm interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC Alarm event in interrupt mode and select the rising edge sensitivity. 2. Configure and enable the RTC_ALARM IRQ channel in the NVIC. 3. Configure the RTC to generate RTC alarms. To enable the RTC Tamper interrupt, the following sequence is required: DocID029587 Rev 3 1853/3178 1880 Real-time clock (RTC) RM0433 1. Configure and enable the EXTI line corresponding to the RTC Tamper event in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC tamper event. To enable the RTC TimeStamp interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC TimeStamp event in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC time-stamp event. To enable the Wakeup timer interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the Wakeup timer even in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_WKUP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC Wakeup timer event. Table 358. Interrupt control bits Interrupt event Event flag Enable control bit Exit from Sleep mode Exit from Stop mode Exit from Standby mode Alarm A ALRAF ALRAIE yes yes(1) yes(1) Alarm B ALRBF ALRBIE yes yes(1) yes(1) RTC_TS input (timestamp) TSF TSIE yes yes(1) yes(1) RTC_TAMP1 input detection TAMP1F TAMPIE yes yes(1) yes(1) RTC_TAMP2 input detection TAMP2F TAMPIE yes yes(1) yes(1) RTC_TAMP3 input detection TAMP3F TAMPIE yes yes(1) yes(1) Wakeup timer interrupt WUTF WUTIE yes yes(1) yes(1) 1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI. 46.6 RTC registers Refer to Section 1.1 on page 98 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 46.6.1 RTC time register (RTC_TR) The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1844 and Reading the calendar on page 1845. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x00 Backup domain reset value: 0x0000 0000 1854/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. PM 15 14 13 12 11 10 9 8 7 Res. MNT[2:0] rw rw MNU[3:0] rw rw rw rw 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw Res. rw 21 ST[2:0] rw rw SU[3:0] rw rw rw Bits 31-23 Reserved, must be kept at reset value Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format Bits 19:16 HU[3:0]: Hour units in BCD format Bit 15 Reserved, must be kept at reset value. Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 46.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1844 and Reading the calendar on page 1845. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x04 Backup domain reset value: 0x0000 2101 System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 14 13 WDU[2:0] rw rw 12 11 MT rw rw 10 9 8 MU[3:0] rw rw rw 21 20 19 18 YT[3:0] rw 15 22 17 16 YU[3:0] rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. rw rw rw DT[1:0] rw rw DU[3:0] rw rw Bits 31:24 Reserved, must be kept at reset value Bits 23:20 YT[3:0]: Year tens in BCD format Bits 19:16 YU[3:0]: Year units in BCD format DocID029587 Rev 3 1855/3178 1880 Real-time clock (RTC) RM0433 Bits 15:13 WDU[2:0]: Week day units 000: forbidden 001: Monday ... 111: Sunday Bit 12 MT: Month tens in BCD format Bits 11:8 MU: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format 1856/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. ITSE COE rw rw rw 15 14 13 12 11 10 9 8 7 6 TSIE rw WUTIE ALRBIE ALRAIE rw rw rw TSE WUTE rw rw ALRBE ALRAE rw Res. rw 22 21 20 19 18 POL COSEL BKP rw rw rw rw w w 5 4 3 2 1 0 OSEL[1:0] FMT rw BYPS REFCKON TSEDGE HAD rw rw rw 17 16 SUB1H ADD1H WUCKSEL[2:0] rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 ITSE: timestamp on internal event enable 0: internal event timestamp disabled 1: internal event timestamp enabled Bit 23 COE: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled Bits 22:21 OSEL[1:0]: Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Alarm B output enabled 11: Wakeup output enabled Bit 20 POL: Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]). Bit 19 COSEL: Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz (with default prescaler setting) 1: Calibration output is 1 Hz (with default prescaler setting) These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 46.3.16: Calibration clock output Bit 18 BKP: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. DocID029587 Rev 3 1857/3178 1880 Real-time clock (RTC) RM0433 Bit 17 SUB1H: Subtract 1 hour (winter time change) When this bit is set, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode. Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode. Bit 15 TSIE: Time-stamp interrupt enable 0: Time-stamp Interrupt disable 1: Time-stamp Interrupt enable Bit 14 WUTIE: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled Bit 13 ALRBIE: Alarm B interrupt enable 0: Alarm B Interrupt disable 1: Alarm B Interrupt enable Bit 12 ALRAIE: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled Bit 11 TSE: timestamp enable 0: timestamp disable 1: timestamp enable Bit 10 WUTE: Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled Bit 9 ALRBE: Alarm B enable 0: Alarm B disabled 1: Alarm B enabled Bit 8 ALRAE: Alarm A enable 0: Alarm A disabled 1: Alarm A enabled Bit 7 Reserved, must be kept at reset value. Bit 6 FMT: Hour format 0: 24 hour/day format 1: AM/PM hour format Bit 5 BYPSHAD: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to ‘1’. 1858/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: RTC_REFIN detection disabled 1: RTC_REFIN detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value (see note below) Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1 = 11]. Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1. It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour. ADD1H and SUB1H changes are effective in the next second. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Caution: TSE must be reset when TSEDGE is changed to avoid spuriously setting of TSF. DocID029587 Rev 3 1859/3178 1880 Real-time clock (RTC) 46.6.4 RM0433 RTC initialization and status register (RTC_ISR) This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x0C Backup domain reset value: 0x0000 0007 System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ITSF RECALPF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 INIT INITF RSF INITS rw r rc_w0 r TAMP3F TAMP2F TAMP1F TSOVF rc_w0 rc_w0 rc_w0 rc_w0 TSF rc_w0 WUTF ALRBF ALRAF rc_w0 rc_w0 rc_w0 SHPF WUTWF r r rc_w0 r 1 0 ALRB WF ALRAWF r r Bits 31:18 Reserved, must be kept at reset value Bit 17 ITSF: Internal tTime-stamp flag This flag is set by hardware when a time-stamp on the internal event occurs. This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits. Bit 16 RECALPF: Recalibration pending Flag The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly. Bit 15 TAMP3F: RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0 Bit 14 TAMP2F: RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0 Bit 13 TAMP1F: RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0 Bit 12 TSOVF: Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. Bit 11 TSF: Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits. 1860/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) Bit 10 WUTF: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. Bit 9 ALRBF: Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0. Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. Bit 7 INIT: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. Bit 6 INITF: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed Bit 5 RSF: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized Bit 4 INITS: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 0: Calendar has not been initialized 1: Calendar has been initialized Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. DocID029587 Rev 3 1861/3178 1880 Real-time clock (RTC) RM0433 Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed Bit 1 ALRBWF: Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm B update not allowed 1: Alarm B update allowed Bit 0 ALRAWF: Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed Note: 1862/3178 The bits ALRAF, ALRBF, WUTF and TSF are cleared 2 APB clock cycles after programming them to 0. DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.5 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 1844. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x10 Backup domain reset value: 0x007F 00FF System reset: not affected 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 rw rw rw rw rw rw rw Res. 22 21 20 19 18 17 16 PREDIV_A[6:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PREDIV_S[14:0] rw Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) DocID029587 Rev 3 1863/3178 1880 Real-time clock (RTC) 46.6.6 RM0433 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ISR. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x14 Backup domain reset value: 0x0000 FFFF System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw WUT[15:0] rw Bits 31:16 Reserved, must be kept at reset value Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. 1864/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.7 RTC alarm A register (RTC_ALRMAR) This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x1C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 MSK4 WDSEL 29 28 27 DT[1:0] 26 25 24 DU[3:0] 23 22 MSK3 PM 21 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw MSK2 rw MNT[2:0] rw rw MNU[3:0] rw rw rw MSK1 rw rw rw ST[2:0] rw rw SU[3:0] rw rw rw Bit 31 MSK4: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day don’t care in Alarm A comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format. Bits 27:24 DU[3:0]: Date units or day in BCD format. Bit 23 MSK3: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours don’t care in Alarm A comparison Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 MSK2: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes don’t care in Alarm A comparison Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID029587 Rev 3 1865/3178 1880 Real-time clock (RTC) 46.6.8 RM0433 RTC alarm B register (RTC_ALRMBR) This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x20 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 MSK4 WDSEL 29 28 27 DT[1:0] 26 25 24 DU[3:0] 23 22 MSK3 PM 21 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw MSK2 rw MNT[2:0] rw rw MNU[3:0] rw rw rw rw MSK1 rw rw ST[2:0] rw rw Bit 31 MSK4: Alarm B date mask 0: Alarm B set if the date and day match 1: Date and day don’t care in Alarm B comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format Bits 27:24 DU[3:0]: Date units or day in BCD format Bit 23 MSK3: Alarm B hours mask 0: Alarm B set if the hours match 1: Hours don’t care in Alarm B comparison Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format Bits 19:16 HU[3:0]: Hour units in BCD format Bit 15 MSK2: Alarm B minutes mask 0: Alarm B set if the minutes match 1: Minutes don’t care in Alarm B comparison Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 1866/3178 DocID029587 Rev 3 SU[3:0] rw rw rw RM0433 Real-time clock (RTC) 46.6.9 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 w w w w 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. KEY w w w w Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 KEY: Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 46.6.10 RTC sub second register (RTC_SSR) Address offset: 0x28 Backup domain reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r SS[15:0] r r r r r r r r r Bits31:16 Reserved, must be kept at reset value Bits 15:0 SS: Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. DocID029587 Rev 3 1867/3178 1880 Real-time clock (RTC) 46.6.11 RM0433 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w 15 Res. SUBFS[14:0] w w w w w w w w Bit 31 ADD1S: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. Bits 30:15 Reserved, must be kept at reset value Bits 14:0 SUBFS: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time. 1868/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.12 RTC timestamp time register (RTC_TSTR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x30 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. PM r 15 14 Res. 13 12 11 MNT[2:0] r r 10 9 8 MNU[3:0] r r r r 7 6 Res. r 21 20 19 18 HT[1:0] r r r r 5 4 3 2 ST[2:0] r r 17 16 HU[3:0] r r 1 0 r r SU[3:0] r r r Bits 31:23 Reserved, must be kept at reset value Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 Reserved, must be kept at reset value Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID029587 Rev 3 1869/3178 1880 Real-time clock (RTC) 46.6.13 RM0433 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. r r 15 WDU[1:0] r r MT r r MU[3:0] r r r r Bits 31:16 Reserved, must be kept at reset value Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format 1870/3178 DocID029587 Rev 3 DT[1:0] r DU[3:0] r r r RM0433 Real-time clock (RTC) 46.6.14 RTC time-stamp sub second register (RTC_TSSSR) The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. Address offset: 0x38 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r SS[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value Bits 15:0 SS: Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred. DocID029587 Rev 3 1871/3178 1880 Real-time clock (RTC) 46.6.15 RM0433 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 1843. Address offset: 0x3C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CALP CALW8 CALW 16 Res. Res. Res. Res. rw rw rw rw rw rw rw CALM[8:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section 46.3.13: RTC smooth digital calibration. Bit 14 CALW8: Use an 8-second calibration cycle period When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 46.3.13: RTC smooth digital calibration. Bit 13 CALW16: Use a 16-second calibration cycle period When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1. Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 46.3.13: RTC smooth digital calibration. Bits 12:9 Reserved, must be kept at reset value Bits 8:0 CALM[8:0]: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 46.3.13: RTC smooth digital calibration on page 1848. 1872/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.16 RTC tamper configuration register (RTC_TAMPCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 TAMP PUDIS rw TAMPPRCH [1:0] rw rw TAMPFLT[1:0] rw rw 24 rw 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 TAMPFREQ[2:0] rw 23 TAMP3 TAMP2 TAMP1 TAMP3 TAMP3 TAMP2 TAMP2 TAMP1 TAMP1 NO NO NO MF IE MF IE MF IE ERASE ERASE ERASE TAMP TS rw rw TAMP3 TAMP3 TAMP2 TAMP2 TRG E TRG E rw rw rw rw TAMPI E TAMP1 TAMP1 TRG E rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 TAMP3MF: Tamper 3 mask flag 0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. 1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and the backup SRAM are not erased. Note: The Tamper 3 interrupt must not be enabled when TAMP3MF is set. Bit 23 TAMP3NOERASE: Tamper 3 no erase 0: Tamper 3 event erases the backup registers and the backup SRAM. 1: Tamper 3 event does not erase the backup registers and the backup SRAM. Bit 22 TAMP3IE: Tamper 3 interrupt enable 0: Tamper 3 interrupt is disabled if TAMPIE = 0. 1: Tamper 3 interrupt enabled. Bit 21 TAMP2MF: Tamper 2 mask flag 0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. 1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and the backup SRAM are not erased. Note: The Tamper 2 interrupt must not be enabled when TAMP2MF is set. Bit 20 TAMP2NOERASE: Tamper 2 no erase 0: Tamper 2 event erases the backup registers and the backup SRAM. 1: Tamper 2 event does not erase the backup registers and the backup SRAM. Bit 19 TAMP2IE: Tamper 2 interrupt enable 0: Tamper 2 interrupt is disabled if TAMPIE = 0. 1: Tamper 2 interrupt enabled. Bit 18 TAMP1MF: Tamper 1 mask flag 0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. 1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers and the backup SRAM are not erased. Note: The Tamper 1 interrupt must not be enabled when TAMP1MF is set. DocID029587 Rev 3 1873/3178 1880 Real-time clock (RTC) RM0433 Bit 17 TAMP1NOERASE: Tamper 1 no erase 0: Tamper 1 event erases the backup registers and the backup SRAM. 1: Tamper 1 event does not erase the backup registers and the backup SRAM. Bit 16 TAMP1IE: Tamper 1 interrupt enable 0: Tamper 1 interrupt is disabled if TAMPIE = 0. 1: Tamper 1 interrupt enabled. Bit 15 TAMPPUDIS: RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are precharged before each sample. 0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) 1: Disable precharge of RTC_TAMPx pins. Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs. 0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). 0x1: Tamper event is activated after 2 consecutive samples at the active level. 0x2: Tamper event is activated after 4 consecutive samples at the active level. 0x3: Tamper event is activated after 8 consecutive samples at the active level. Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled. 0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) Bit 7 TAMPTS: Activate timestamp on tamper detection event 0: Tamper detection event does not cause a timestamp to be saved 1: Save timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register. Bit 6 TAMP3TRG: Active level for RTC_TAMP3 input if TAMPFLT ≠ 00: 0: RTC_TAMP3 input staying low triggers a tamper detection event. 1: RTC_TAMP3 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP3 input rising edge triggers a tamper detection event. 1: RTC_TAMP3 input falling edge triggers a tamper detection event. 1874/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) Bit 5 TAMP3E: RTC_TAMP3 detection enable 0: RTC_TAMP3 input detection disabled 1: RTC_TAMP3 input detection enabled Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input if TAMPFLT != 00: 0: RTC_TAMP2 input staying low triggers a tamper detection event. 1: RTC_TAMP2 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP2 input rising edge triggers a tamper detection event. 1: RTC_TAMP2 input falling edge triggers a tamper detection event. Bit 3 TAMP2E: RTC_TAMP2 input detection enable 0: RTC_TAMP2 detection disabled 1: RTC_TAMP2 detection enabled Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled. Note: This bit enables the interrupt for all tamper pins events, whatever TAMPxIE level. If this bit is cleared, each tamper event interrupt can be individually enabled by setting TAMPxIE. Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. 1: RTC_TAMP1 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP1 input rising edge triggers a tamper detection event. 1: RTC_TAMP1 input falling edge triggers a tamper detection event. Bit 0 TAMP1E: RTC_TAMP1 input detection enable 0: RTC_TAMP1 detection disabled 1: RTC_TAMP1 detection enabled Caution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid spuriously setting TAMPxF. DocID029587 Rev 3 1875/3178 1880 Real-time clock (RTC) 46.6.17 RM0433 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 1843 Address offset: 0x44 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw MASKSS[3:0] Res. 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw SS[14:0] rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Bits23:15 Reserved, must be kept at reset value. Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 1876/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection. Address offset: 0x48 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw MASKSS[3:0] Res. 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw SS[14:0] rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared. 0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared. 0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared. ... 0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared. 0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared. 0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared. 0xF: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Bits 23:15 Reserved, must be kept at reset value. Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. DocID029587 Rev 3 1877/3178 1880 Real-time clock (RTC) 46.6.19 RM0433 RTC option register (RTC_OR) Address offset: 0x4C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RTC_ OUT_ RMP RTC_ ALARM _TYPE rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:2 Reserved, must be kept at reset value. Bit 1 RTC_OUT_RMP: RTC_OUT remap Setting this bit allows to remap the RTC outputs on PB2 as follows: RTC_OUT_RMP = ‘0’: If OSEL/= ‘00’: RTC_ALARM is output on PC13 If OSEL= ‘00’ and COE = ‘1’: RTC_CALIB is output on PC13 RTC_OUT_RMP = ‘1’: If OSEL /= ‘00’ and COE = ‘0’: RTC_ALARM is output on PB2 If OSEL = ‘00’ and COE = ‘1’: RTC_CALIB is output on PB2 If OSEL /= ‘00’ and COE = ‘1’: RTC_CALIB is output on PB2 and RTC_ALARM is output on PC13. Bit 0 RTC_ALARM_TYPE: RTC_ALARM output type on PC13 This bit is set and cleared by software 0: RTC_ALARM, when mapped on PC13, is open-drain output 1: RTC_ALARM, when mapped on PC13, is push-pull output 46.6.20 RTC backup registers (RTC_BKPxR) Address offset: 0x50 to 0xCC Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw BKP[31:16] BKP[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 BKP[31:0] The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. 1878/3178 DocID029587 Rev 3 RM0433 Real-time clock (RTC) 46.6.21 RTC register map Res. 0 0 0 0 0 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_WPR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DU[3:0] 0 0 0 0 0 HT [1:0] 0 0 0 0 HU[3:0] MNT[2:0] 0 0 0 MNU[3:0] 0 MNT[2:0] 0 0 0 MNU[3:0] Res. 0 0 0 0 0 Res. Res. Res. Res. WDU[1:0] 0 MT 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset value 1 ST[2:0] 0 0 0 SU[3:0] 0 ST[2:0] 0 0 0 0 0 0 SU[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MU[3:0] 0 0 0 0 0 0 0 0 0 0 0 ST[2:0] 0 0 0 0 SU[3:0] 0 DT [1:0] 0 0 0 DU[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 SS[15:0] 0 DocID029587 Rev 3 1 KEY Res. 0 Res. Res. Res. Res. 0 MNT[2:0] Res. HT[1:0] 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 MNU[3:0] Res. PM 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Res. RTC_TSSSR 0 SUBFS[14:0] 0 Reset value 0x38 0 Res. Res. Res. Res. Res. HU[3:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_TSDR Res. Reset value 0x34 Res. Res. Res. Res. Res. Res. Res. Res. RTC_TSTR 0 0 Res. 0 Res. ADD1S Reset value Res. RTC_SHIFTR Res. 0x30 0 SS[15:0] 0 Res. Reset value 0x2C 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_SSR 0 0 Res. Reset value 0x28 0 MSK2 0 HU[3:0] MSK2 0 0 MSK1 PM 0 DT [1:0] 0 MSK2 MSK3 Reset value 0 PM RTC_ALRMBR 0 MSK3 0 Res. 1 Res. 1 Res. 1 MSK4 1 WDSEL 1 MSK4 1 WDSEL 1 0 0 0 WUCKS EL[2:0] WUT[15:0] Reset value HT [1:0] 1 0 Res. 1 RTC_ALRMAR DU[3:0] 0 PREDIV_S[14:0] 1 DT [1:0] 0 ALRAWF 0 0 ALRBWF ALRAF 0 0 TSEDGE WUTF ALRBF 0 0 SHPF TSF 0 DU[3:0] WUT WF 0 0 BYPSHAD 0 0 REFCKON 0 0 RSF 0 0 INITS ALRAE 0 0 DT [1:0] Res. Res. WUTE ALRBE 0 0 FMT TSE 0 Res. ALRAIE 0 PREDIV_A[6:0] 0 SU[3:0] INITF ALRBIE 0 ST[2:0] INIT Res. 0 TSOVF 1 TAMP1F 0 TSIE 0 WUTIE 0 .TAMP2F Res. 0 MU[3:0] Res. 0x24 1 0 Res. 0x20 0 0 0 Reset value 0x1C 0 0 ADD1H Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_WUTR Res. 0x14 Res. Reset value WDU[2:0] 0 TAMP3F 0 0 RECALPF 0 0 0 BKP 0 0 0 SUB1H 0 Res. Res. Res. Res. Res. Res. Res. Res. RTC_PRER 0 0 Reset value 0x10 0 MNU[3:0] Res. 0 Res. POL COE 0 Res. OSE L [1:0] 0 COSEL 0 Res. 0 0 MNT[2:0] MT 0 YU[3:0] ITSE Res. Res. Res. Res. Res. RTC_ISR Res. 0x0C Res. Reset value 0 Res. Res. Res. Res. Res. Res. RTC_CR Res. 0x08 0 HU[3:0] YT[3:0] 0 Res. Reset value HT [1:0] ITSF Res. Res. Res. Res. Res. Res. RTC_DR Res. 0x04 0 Res. Reset value PM Res. Res. Res. Res. Res. Res. Res. RTC_TR Res. 0x00 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 359. RTC register map and reset values 0 0 0 0 0 0 0 0 0 1879/3178 1880 0x50 to 0xCC 0x4C RTC_ OR Reset value Reset value 1880/3178 0 0 0 0 0 0 Res. Reset value 0 0 MASKSS [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_BKP0R 0 to RTC_BKP31R 0 0 0 DocID029587 Rev 3 Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. Reset value TAMP2NOERASE TAMP2IE TAMP1MF TAMP1NOERASE TAMP1IE TAMPPUDIS 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1E 0 .TAMPIE SS[14:0] TAMP1TRG 0 .TAMP2E SS[14:0] TAMP3E 0 TAMP2TRG 0 TAMPTS CALW8 CALW16 Res. Res. Res. Res. CALP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TAMP3TRG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. RTC_ CALR 0 TAMPFREQ[2:0] TAMPFLT[1:0] TAMPPRCH[1:0] TAMP3IE TAMP2MF TAMP3NOERASE 0 Res. MASKSS [3:0] TAMP3MF Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 0 0 Reset value RTC_ALARM_TYPE RTC_ ALRMBSSR Res. Reset value RTC_OUT_RMP 0x48 RTC_ ALRMASSR Res. 0x44 RTC_TAMPCR Res. 0x40 Res. 0x3C Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Real-time clock (RTC) RM0433 Table 359. RTC register map and reset values (continued) CALM[8:0] 0 0 0 0 0 0 0 0 0 0 BKP[31:0] BKP[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Inter-integrated circuit (I2C) interface 47 Inter-integrated circuit (I2C) interface 47.1 Introduction The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). It is also SMBus (system management bus) and PMBus (power management bus) compatible. DMA can be used to reduce CPU overload. 47.2 I2C main features • I2C bus specification rev03 compatibility: – Slave and master modes – Multimaster capability – Standard-mode (up to 100 kHz) – Fast-mode (up to 400 kHz) – Fast-mode Plus (up to 1 MHz) – 7-bit and 10-bit addressing mode – Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) – All 7-bit addresses acknowledge mode – General call – Programmable setup and hold times – Easy to use event management – Optional clock stretching – Software reset • 1-byte buffer with DMA capability • Programmable analog and digital noise filters DocID029587 Rev 3 1881/3178 1950 Inter-integrated circuit (I2C) interface RM0433 The following additional features are also available depending on the product implementation (see Section 47.3: I2C implementation): • SMBus specification rev 2.0 compatibility: – 47.3 Hardware PEC (Packet Error Checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection • PMBus rev 1.1 standard compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the i2c_pclk reprogramming • Wakeup from Stop mode on address match. I2C implementation This manual describes the full set of features implemented in I2C peripheral.In the STM32H7xxx devices I2C1, I2C2, I2C3 and I2C4 implement the full set of features as shown in the following table. Table 360. STM32H7x3 I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 7-bit addressing mode X X X X 10-bit addressing mode X X X X Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X X Independent clock X X X X SMBus X X X X Wakeup from Stop mode X X X X 1. X = supported. 47.4 I2C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to 1 MHz) I2C bus. This interface can also be connected to a SMBus with the data pin (SDA) and clock pin (SCL). 1882/3178 DocID029587 Rev 3 RM0433 Inter-integrated circuit (I2C) interface If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available. 47.4.1 I2C block diagram The block diagram of the I2C interface is shown in Figure 530. Figure 530. I2C block diagram LFBNHUBFNFORFNGRPDLQ )URPV\VWHPFRQILJXUDWLRQ FRQWUROOHU 6<6&)* )0GULYH 'DWDFRQWURO LFBNHUBFN 6KLIWUHJLVWHU 'LJLWDO QRLVH ILOWHU $QDORJ QRLVH ILOWHU *3,2 ORJLF 6'$ 60%86 3(& JHQHUDWLRQ FKHFN LFBZNXS :DNHXS RQ DGGUHVV PDWFK )URPV\VWHPFRQILJXUDWLRQ FRQWUROOHU 6<6&)* )0GULYH &ORFNFRQWURO 0DVWHUFORFN JHQHUDWLRQ 6ODYHFORFN VWUHWFKLQJ 'LJLWDO QRLVH ILOWHU $QDORJ QRLVH ILOWHU *3,2 ORJLF 6&/ 60%XV 7LPHRXW FKHFN 60%XV$OHUW FRQWURO VWDWXV 60%$ LFBSFONFORFNGRPDLQ LFBHYHQWBLW LFBHUURUBLW '0$LQWHUIDFH ,54LQWHUIDFH LFBW[BGPD LFBU[BGPD 5HJLVWHUV LFBSFON $3%EXV 0699 The I2C is clocked by an independent clock source which allows to the I2C to operate independently from thei2c_pclk frequency. Refer to Figure 43: Kernel clock distribution for I2Cs for more details. DocID029587 Rev 3 1883/3178 1950 Inter-integrated circuit (I2C) interface RM0433 I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled by setting the driving capability control bits for SCL and SDA in Section 12: System configuration controller (SYSCFG). 47.4.2 I2C clock requirements The I2C kernel is clocked by i2c_ker_ck. The i2c_ker_ck period tI2CCLK must respect the following conditions: tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH with: tLOW: SCL low time and tHIGH: SCL high time tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter. Analog filter delay is maximum 260 ns. Digital filter delay is DNF x tI2CCLK. The i2c_pclk clock period tPCLK must respect the following condition: tPCLK < 4/3 tSCL with tSCL: SCL period Caution: When the I2C kernel is clocked by i2c_pclk, this clock must respect the conditions for tI2CCLK. 47.4.3 Mode selection The interface can operate in one of the four following modes: • Slave transmitter • Slave receiver • Master transmitter • Master receiver By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability. Communication flow In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a START condition and ends with a STOP condition. Both START and STOP conditions are generated in master mode by software. In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the General Call address. The General Call address detection can be enabled or disabled by software. The reserved SMBus addresses can also be enabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to the following figure. 1884/3178 DocID029587 Rev 3 RM0433 Inter-integrated circuit (I2C) interface Figure 531. I2C bus protocol 6'$ 06% $&. 6&/ 6WDUW FRQGLWLRQ 6WRS FRQGLWLRQ 06 9 Acknowledge can be enabled or disabled by software. The I2C interface addresses can be selected by software. DocID029587 Rev 3 1885/3178 1950 Inter-integrated circuit (I2C) interface 47.4.4 RM0433 I2C initialization Enabling and disabling the peripheral The I2C peripheral clock must be configured and enabled in the clock controller (refer to Section 8: Reset and Clock Control (RCC)). Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register. When the I2C is disabled (PE=0), the I2C performs a software reset. Refer to Section 47.4.5: Software reset for more details. Noise filters Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must configure the noise filters, if needed. By default, an analog noise filter is present on the SDA and SCL inputs. This analog filter is compliant with the I2C specification which requires the suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register. When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x i2c_ker_ck periods. This allows to suppress spikes with a programmable length of 1 to 15 i2c_ker_ck periods. Table 361. Comparison of analog vs. digital filters Pulse width of suppressed spikes Benefits Drawbacks Caution: 1886/3178 Analog filter Digital filter ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks Available in Stop mode – Programmable length: extra filtering capability vs. standard requirements – Stable length Variation vs. temperature, voltage, process Wakeup from Stop mode on address match is not available when digital filter is enabled Changing the filter configuration is not allowed when the I2C is enabled. DocID029587 Rev 3 RM0433 Inter-integrated circuit (I2C) interface I2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 532. Setup and hold timings d,K>d/D 6&/IDOOLQJHGJHLQWHUQDO GHWHFWLRQ W6<1& 6'$'(/ 6&/VWUHWFKHGORZE\WKH,& 6'$RXWSXWGHOD\ 6&/ 6'$ W+' '$7 'DWDKROGWLPH LQFDVHRIWUDQVPLVVLRQWKHGDWDLVVHQWRQ6'$RXWSXWDIWHU WKH6'$'(/GHOD\LILWLVDOUHDG\DYDLODEOHLQ,&B7;'5 d^ dhWd/D 6&/'(/ 6&/VWUHWFKHGORZE\WKH,& 6&/ 6'$ W68 67$ 'DWDVHWXSWLPH LQFDVHRIWUDQVPLVVLRQWKH6&/'(/FRXQWHUVWDUWV ZKHQWKHGDWDLVVHQWRQ6'$RXWSXW 06Y9 DocID029587 Rev 3 1887/3178 1950 Inter-integrated circuit (I2C) interface • RM0433 When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is tSDADEL = SDADEL x tPRESC + tI2CCLK where tPRESC = (PRESC+1) x tI2CCLK. TSDADEL impacts the hold time tHD;DAT. The total SDA output delay is: tSYNC1 + {[SDADEL x (PRESC+1) + 1] x tI2CCLK } tSYNC1 duration depends on these parameters: – SCL falling slope – When enabled, input delay brought by the analog filter: tAF(min) < tAF < tAF(max) ns. – When enabled, input delay brought by the digital filter: tDNF = DNF x tI2CCLK – Delay due to SCL synchronization to i2c_ker_ck clock (2 to 3 i2c_ker_ck periods) In order to bridge the undefined region of the SCL falling edge, the user must program SDADEL in such a way that: {tf (max) +tHD;DAT (min) -tAF(min) - [(DNF +3) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } ≤ SDADEL SDADEL ≤ {tHD;DAT (max) -tAF(max) - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } Note: tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to device datasheet for tAF values. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode and Fast-mode Plus, but must be less than the maximum of tVD;DAT by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. The SDA rising edge is usually the worst case, so in this case the previous equation becomes: SDADEL ≤ {tVD;DAT (max) -tr (max) -260 ns - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }. Note: This condition can be violated when NOSTRETCH=0, because the device stretches SCL low to guarantee the set-up time, according to the SCLDEL value. Refer to Table 362: I2C-SMBUS specification data setup and hold times for tf, tr, tHD;DAT and tVD;DAT standard values. • After tSDADEL delay, or after sending SDA output in case the slave had to stretch the clock because the data was not yet written in I2C_TXDR register, SCL line is kept at low level during the setup time. This setup time is tSCLDEL = (SCLDEL+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK. tSCLDEL impacts the setup time tSU;DAT . In order to bridge the undefined region of the SDA transition (rising edge usually worst case), the user must program SCLDEL in such a way that: {[tr (max) + tSU;DAT (min)] / [(PRESC+1)] x tI2CCLK]} - 1 <= SCLDEL Refer to Table 362: I2C-SMBUS specification data setup and hold times for tr and tSU;DAT standard values. The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. 1888/3178 DocID029587 Rev 3 RM0433 Note: Inter-integrated circuit (I2C) interface At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK, in both transmission and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts, continuing stretching SCL low to guarantee the data setup time. If NOSTRETCH=1 in slave mode, the SCL is not stretched. Consequently the SDADEL must be programmed in such a way to guarantee also a sufficient setup time. Table 362. I2C-SMBUS specification data setup and hold times Symbol Parameter Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+) SMBUS Unit Min. Max Min. Max Min. Max Min. Max tHD;DAT Data hold time 0 - 0 - 0 - 0.3 - tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 - - tSU;DAT Data setup time 250 - 100 - 50 - 250 - µs tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 - 1000 tf Fall time of both SDA and SCL signals - 300 - 300 - 120 - 300 ns Additionally, in master mode, the SCL clock high and low levels must be configured by programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register. • When the SCL falling edge is internally detected, a delay is inserted before releasing the SCL output. This delay is tSCLL = (SCLL+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK. tSCLL impacts the SCL low time tLOW . • When the SCL rising edge is internally detected, a delay is inserted before forcing the SCL output to low level. This delay is tSCLH = (SCLH+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK. tSCLH impacts the SCL high time tHIGH . Refer to I2C master initialization for more details. Caution: Changing the timing configuration is not allowed when the I2C is enabled. The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral. Refer to I2C slave initialization for more details. Caution: Changing the NOSTRETCH configuration is not allowed when the I2C is enabled. DocID029587 Rev 3 1889/3178 1950 Inter-integrated circuit (I2C) interface RM0433 Figure 533. I2C initialization flowchart ,QLWLDOVHWWLQJV &OHDU3(ELWLQ,&B&5 &RQILJXUH$1)2))DQG'1)> @LQ,&B&5 &RQILJXUH35(6&> @ 6'$'(/> @6&/'(/> @6&/+> @ 6&//> @LQ,&B7,0,1*5 &RQILJXUH12675(7&+LQ,&B&5 6HW3(ELWLQ,&B&5 (QG D^ϭϵϴϰϳsϮ 47.4.5 Software reset A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that case I2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value. The configuration registers are not impacted. Here is the list of impacted register bits: 1. I2C_CR2 register: START, STOP, NACK 2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR, ARLO, OVR and in addition when the SMBus feature is supported: 1. I2C_CR2 register: PECBYTE 2. I2C_ISR register: PECERR, TIMEOUT, ALERT PE must be kept low during at least 3 APB clock cycles in order to perform the software reset. This is ensured by writing the following software sequence: - Write PE=0 - Check PE=0 - Write PE=1. 1890/3178 DocID029587 Rev 3 RM0433 47.4.6 Inter-integrated circuit (I2C) interface Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th SCL pulse (before the Acknowledge pulse). Figure 534. Data reception $&.SXOVH $&.SXOVH OHJHQG 6&/ 6KLIWUHJLVWHU 6&/ VWUHWFK [[ GDWD [[ GDWD [[ 5;1( UGGDWD UGGDWD ,&B5;'5 GDWD GDWD GDWD 06 9 DocID029587 Rev 3 1891/3178 1950 Inter-integrated circuit (I2C) interface RM0433 Transmission If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written. The stretch is done after the 9th SCL pulse. Figure 535. Data transmission $&.SXOVH $&.SXOVH OHJHQG [[ [[ GDWD 6KLIWUHJLVWHU GDWD 6&/ 6&/ VWUHWFK [[ 7;( ZUGDWD ,&B7;'5 GDWD ZUGDWD GDWD GDWD 06 9 Hardware transfer management The I2C has a byte counter embedded in hardware in order to manage byte transfer and to close the communication in various modes such as: – NACK, STOP and ReSTART generation in master mode – ACK control in slave receiver mode – PEC generation/checking when SMBus feature is supported The byte counter is always used in master mode. By default it is disabled in slave mode, but it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2C_CR2 register. The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or if a receiver wants to control the acknowledge value of a received data byte, the reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode, TCR flag is set when the number of bytes programmed in NBYTES has been transferred, and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR is cleared by software when NBYTES is written to a non-zero value. When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be cleared. 1892/3178 DocID029587 Rev 3 RM0433 Inter-integrated circuit (I2C) interface When RELOAD=0 in master mode, the counter can be used in 2 modes: Caution: • Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred. • Software end mode (AUTOEND = ‘0’ in the I2C_CR2 register). In this mode, software action is expected once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred; the TC flag is set and an interrupt is generated if the TCIE bit is set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by software when the START or STOP bit is set in the I2C_CR2 register. This mode must be used when the master wants to send a RESTART condition. The AUTOEND bit has no effect when the RELOAD bit is set. Table 363. I2C configuration table 47.4.7 Function SBC bit RELOAD bit AUTOEND bit Master Tx/Rx NBYTES + STOP x 0 1 Master Tx/Rx + NBYTES + RESTART x 0 0 Slave Tx/Rx all received bytes ACKed 0 x x Slave Rx with ACK control 1 1 x I2C slave mode I2C slave initialization In order to work in slave mode, the user must enable at least one slave address. Two registers I2C_OAR1 and I2C_OAR2 are available in order to program the slave own addresses OA1 and OA2. • OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by setting the OA1MODE bit in the I2C_OAR1 register. OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register. • If additional slave addresses are required, the 2nd slave address OA2 can be configured. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received address. As soon as OA2MSK is not equal to 0, the address comparator for OA2 excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except reserved addresses). OA2 is always a 7-bit address. These reserved addresses can be acknowledged if they are enabled by the specific enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with OA2MSK=0. OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register. • The General Call address is enabled by setting the GCEN bit in the I2C_CR1 register. When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is set, and an interrupt is generated if the ADDRIE bit is set. DocID029587 Rev 3 1893/3178 1950 Inter-integrated circuit (I2C) interface RM0433 By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the I2C_CR1 register. After receiving an ADDR interrupt, if several addresses are enabled the user must read the ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR flag must also be checked in order to know the transfer direction. Slave clock stretching (NOSTRETCH = 0) In default mode, the I2C slave stretches the SCL clock in the following situations: • When the ADDR flag is set: the received address matches with one of the enabled slave addresses. This stretch is released when the ADDR flag is cleared by software setting the ADDRCF bit. • In transmission, if the previous data transmission is completed and no new data is written in I2C_TXDR register, or if the first data byte is not written when the ADDR flag is cleared (TXE=1). This stretch is released when the data is written to the I2C_TXDR register. • In reception when the I2C_RXDR register is not read yet and a new data reception is completed. This stretch is released when I2C_RXDR is read. • When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1), meaning that the last data byte has been transferred. This stretch is released when then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field. • After SCL falling edge detection, the I2C stretches SCL low during [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK. Slave without clock stretching (NOSTRETCH = 1) When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL signal. 1894/3178 • The SCL clock is not stretched while the ADDR flag is set. • In transmission, the data must be written in the I2C_TXDR register before the first SCL pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. The OVR flag is also set when the first data transmission starts and the STOPF bit is still set (has not been cleared). Therefore, if the user clears the STOPF flag of the previous transfer only after writing the first data to be transmitted in the next transfer, he ensures that the OVR status is provided, even for the first data to be transmitted. • In reception, the data must be read from the I2C_RXDR register before the 9th SCL pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. DocID029587 Rev 3 RM0433 Inter-integrated circuit (I2C) interface Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards. Reload mode must be selected in order to allow byte ACK control in slave reception mode (RELOAD=1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is received, the TCR bit is set, stretching the SCL signal low between the 8th and 9th SCL pulses. The user can read the data from the I2C_RXDR register, and then decide to acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is released by programming NBYTES to a non-zero value: the acknowledge or notacknowledge is sent and next byte can be received. NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is continuous during NBYTES data reception. Note: The SBC bit must be configured when the I2C is disabled, or when the slave is not addressed, or when ADDR=1. The RELOAD bit value can be changed when ADDR=1, or when TCR=1. Caution: Slave Byte Control mode is not compatible with NOSTRETCH mode. Setting SBC when NOSTRETCH=1 is not allowed. Figure 536. Slave initialization flowchart 6ODYH LQLWLDOL]DWLRQ ,QLWLDOVHWWLQJV &OHDU^2$(12$(1`LQ,&B2$5DQG,&B2$5 &RQILJXUH^2$> @2$02'(2$(1 2$> @2$06.> @2$(1*&(1` &RQILJXUH6%&LQ,&B&5 (QDEOHLQWHUUXSWVDQGRU '0$LQ,&B&5 (QG 6%&PXVWEHVHWWRVXSSRUW60%XVIHDWXUHV 06 9 DocID029587 Rev 3 1895/3178 1950 Inter-integrated circuit (I2C) interface RM0433 Slave transmitter A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register. The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted. When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases the SCL and SDA lines in order to let the master perform a STOP or a RESTART condition. The TXIS bit is not set when a NACK is received. When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is received (ADDR=1), the user can choose either to send the content of the I2C_TXDR register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in order to program a new data byte. In Slave Byte Control mode (SBC=1), the number of bytes to be transmitted must be programmed in NBYTES in the address match interrupt subroutine (ADDR=1). In this case, the number of TXIS events during the transfer corresponds to the value programmed in NBYTES. Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to program the first data byte. The first data byte to be sent must be previously programmed in the I2C_TXDR register: • This data can be the data written in the last TXIS event of the previous transmission message. • If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by setting the TXE bit in order to program a new data byte. The STOPF bit must be cleared only after these actions, in order to guarantee that they are executed before the first data transmission starts, following the address acknowledge. If STOPF is still set when the first data transmission starts, an underrun error will be generated (the OVR flag is set). If a TXIS event is needed, (Transmit Interrupt or Transmit DMA request), the user must set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event. 1896/3178 DocID029587 Rev 3 RM0433 Inter-integrated circuit (I2C) interface Figure 537. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0 6ODYH WUDQVPLVVLRQ 6ODYHLQLWLDOL]DWLRQ 1R ,&B,65$''5 " 255 bytes 0DVWHU WUDQVPLVVLRQ 0DVWHULQLWLDOL]DWLRQ 1%<7(6 [)) 1 1 5(/2$' &RQILJXUHVODYHDGGUHVV 6HW,&B&567$57 1R 1R ,&B,657;,6 ,&B,651$&.) " " 255 bytes 0DVWHUUHFHSWLRQ 0DVWHULQLWLDOL]DWLRQ 1%<7(6 [)) 1 1 5(/2$' &RQILJXUHVODYHDGGUHVV 6HW,&B&567$57 ,&B,655;1( " 1R @ 86$57[B%55UHJLVWHU DQGRYHUVDPSOLQJ 06Y9 Some usart_ker_ck sources allow the USART to receive data while the MCU is in low-power mode. Depending on the received data and wakeup mode selected, the USART wakes up the MCU, when needed, in order to transfer the received data, by performing a software read to the USART_RDR register or by DMA. For the other clock sources, the system must be active to allow USART communications. The communication speed range (specially the maximum communication speed) is also determined by the clock source. The receiver implements different user-configurable oversampling techniques (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise. This allows obtaining the best a trade-off between the maximum communication speed and noise/clock inaccuracy immunity. The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register either to 16 or 8 times the baud rate clock (see Figure 567 and Figure 568). 1966/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Depending on your application: • select oversampling by 8 (OVER8=’1’) to achieve higher speed (up to usart_ker_ck_pres/8). In this case the maximum receiver tolerance to clock deviation is reduced (refer to Section 48.5.8: Tolerance of the USART receiver to clock deviation on page 1970) • select oversampling by 16 (OVER8=’0’) to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum usart_ker_ck_pres/16 (where usart_ker_ck_pres is the USART input clock divided by a prescaler). Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. Two options are available: • The majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NE bit is set. • A single sample in the center of the received bit Depending on your application: – select the three sample majority vote method (ONEBIT=’0’) when operating in a noisy environment and reject the data when a noise is detected (refer to Figure 377) because this indicates that a glitch occurred during the sampling. – select the single sample method (ONEBIT=’1’) when the line is noise-free to increase the receiver tolerance to clock deviations (see Section 48.5.8: Tolerance of the USART receiver to clock deviation on page 1970). In this case the NE bit will never be set. When noise is detected in a frame: • The NE bit is set at the rising edge of the RXNE bit (RXFNE in case of FIFO mode enabled). • The invalid data is transferred from the Shift register to the USART_RDR register. • No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit (RXFNE in case of FIFO mode enabled) which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the USART_CR3 register. The NE bit is reset by setting NFCF bit in ICR register. Note: Noise error is not supported in SPI mode. Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes, the OVER8 bit is forced to ‘0 ’ by hardware. DocID029587 Rev 3 1967/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Figure 567. Data sampling when oversampling by 16 5;OLQH VDPSOHGYDOXHV 6DPSOHFORFN 2QHELWWLPH 06Y9 Figure 568. Data sampling when oversampling by 8 5;OLQH VDPSOHGYDOXHV 6DPSOH FORFN [ 2QHELWWLPH 06Y9 Table 377. Noise detection from sampled data 1968/3178 Sampled value NE status Received bit value 000 0 0 001 1 0 010 1 0 011 1 1 100 1 0 101 1 1 110 1 1 111 0 1 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Framing error A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. When the framing error is detected: • the FE bit is set by hardware; • the invalid data is transferred from the Shift register to the USART_RDR register (RXFIFO in case FIFO mode is enabled). • no interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit (RXFNE in case FIFO mode is enabled) which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the USART_CR3 register. The FE bit is reset by writing ‘1’ to the FECF in the USART_ICR register. Note: Framing error is not supported in SPI mode. Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of USART_CR: it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. • 0.5 stop bit (reception in Smartcard mode): no sampling is done for 0.5 stop bit. As a consequence, no framing error and no break frame can be detected when 0.5 stop bit is selected. • 1 stop bit: sampling for 1 stop bit is done on the 8th, 9th and 10th samples. • 1.5 stop bits (Smartcard mode) When transmitting in Smartcard mode, the device must check that the data are correctly sent. The receiver block must consequently be enabled (RE =’1’ in USART_CR1) and the stop bit is checked to test if the Smartcard has detected a parity error. In the event of a parity error, the Smartcard forces the data signal low during the sampling (NACK signal), which is flagged as a framing error. The FE flag is then set through RXNE flag (RXFNE if the FIFO mode is enabled) at the end of the 1.5 stop bit. Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the beginning of the stop bit). The 1.5 stop bit can be broken into 2 parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit period during which sampling occurs halfway through (refer to Section 48.5.16: USART receiver timeout on page 1983 for more details). • 2 stop bits Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit. The framing error flag is set if a framing error is detected during the first stop bit. The second stop bit is not checked for framing error. The RXNE flag (RXFNE if the FIFO mode is enabled) is set at the end of the first stop bit. DocID029587 Rev 3 1969/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.5.7 RM0433 USART baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the value programmed in the USART_BRR register. Equation 1: baud rate for standard USART (SPI mode included) (OVER8 = ‘0’ or ‘1’) In case of oversampling by 16, the baud rate is given by the following formula: usart_ker_ckpres Tx/Rx baud = ----------------------------------------------USARTDIV In case of oversampling by 8, the baud rate is given by the following formula: 2 × usart_ker_ckpres Tx/Rx baud = ---------------------------------------------------------USARTDIV Equation 2: baud rate in Smartcard, LIN and IrDA modes (OVER8 = ’0’) The baud rate is given by the following formula: usart_ker_ckpres Tx/Rx baud = ----------------------------------------------USARTDIV USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register. Note: • When OVER8 = ’0’, BRR = USARTDIV. • When OVER8 = ’1’ – BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. – BRR[3] must be kept cleared. – BRR[15:4] = USARTDIV[15:4] The baud counters are updated to the new value in the baud registers after a write operation to USART_BRR. Hence the baud rate register value should not be changed during communication. In case of oversampling by 16 and 8, USARTDIV must be greater than or equal to 0d16. How to derive USARTDIV from USART_BRR register values Example 1 To obtain 9600 baud with usart_ker_ck_pres= 8 MHz: • In case of oversampling by 16: USARTDIV = 8 000 000/9600 BRR = USARTDIV = 833d = 0341h • In case of oversampling by 8: USARTDIV = 2 * 8 000 000/9600 USARTDIV = 1666,66 (1667d = 683h) BRR[3:0] = 3h >>1 = 1h BRR = 0x681 1970/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Example 2 To obtain 921.6 Kbaud with usart_ker_ck_pres = 48 MHz: • In case of oversampling by 16: USARTDIV = 48 000 000/921 600 BRR = USARTDIV = 52d = 34h • In case of oversampling by 8: USARTDIV = 2 * 48 000 000/921 600 USARTDIV = 104 (104d = 68h) BRR[3:0] = USARTDIV[3:0] >> 1 = 8h >> 1 = 4h BRR = 0x64 48.5.8 Tolerance of the USART receiver to clock deviation The USART asynchronous receiver operates correctly only if the total clock system deviation is less than the tolerance of the USART receiver. The causes which contribute to the total deviation are: • DTRA: deviation due to the transmitter error (which also includes the deviation of the transmitter’s local oscillator) • DQUANT: error due to the baud rate quantization of the receiver • DREC: deviation of the receiver local oscillator • DTCL: deviation due to the transmission line (generally due to the transceivers which can introduce an asymmetry between the low-to-high transition timing and the high-tolow transition timing) DTRA + DQUANT + DREC + DTCL + DWU < USART receiver tolerance where DWU is the error due to sampling point deviation when the wakeup from lowpower mode is used. The USART receiver can receive data correctly at up to the maximum tolerated deviation specified in Table 378, Table 379, depending on the following settings: • 9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register • Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register • Bits BRR[3:0] of USART_BRR register are equal to or different from 0000. • Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in the USART_CR3 register. Table 378. Tolerance of the USART receiver when BRR [3:0] = 0000 OVER8 bit = ’0’ OVER8 bit = ’1’ M bits ONEBIT=’0’ ONEBIT=’1’ ONEBIT=’0’ ONEBIT=’1’ 00 3.75% 4.375% 2.50% 3.75% 01 3.41% 3.97% 2.27% 3.41% 10 4.16 4.86 2.77 4.16 DocID029587 Rev 3 1971/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Table 379. Tolerance of the USART receiver when BRR[3:0] is different from 0000 OVER8 bit = ’0’ OVER8 bit = ’1’ M bits ONEBIT=’0’ ONEBIT=’1’ ONEBIT=’0’ ONEBIT=’1’ 00 3.33% 3.88% 2% 3% 01 3.03% 3.53% 1.82% 2.73% 10 3.7 4.31 2.22 3.33 Note: The data specified in Table 378 and Table 379 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit times when M bits = ‘00’ (11bit times when M=’01’ or 9- bit times when M = ‘10’). 48.5.9 USART Auto baud rate detection The USART can detect and automatically set the USART_BRR register value based on the reception of one character. Automatic baud rate detection is useful under two circumstances: • The communication speed of the system is not known in advance. • The system is using a relatively low accuracy clock source and this mechanism allows the correct baud rate to be obtained without measuring the clock deviation. The clock source frequency must be compatible with the expected communication speed. • When oversampling by 16, the baud rate ranges from usart_ker_ck_pres/65535 and usart_ker_ck_pres/16. • When oversampling by 8, the baud rate ranges from usart_ker_ck_pres/65535 and usart_ker_ck_pres/8. Before activating the auto baud rate detection, the auto baud rate detection mode must be selected through the ABRMOD[1:0] field in the USART_CR2 register. There are four modes based on different character patterns. In these auto baud rate modes, the baud rate is measured several times during the synchronization data reception and each measurement is compared to the previous one. 1972/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) These modes are the following: • Mode 0: Any character starting with a bit at ‘1’. In this case the USART measures the duration of the start bit (falling edge to rising edge). • Mode 1: Any character starting with a 10xx bit pattern. In this case, the USART measures the duration of the Start and of the 1st data bit. The measurement is done falling edge to falling edge, to ensure a better accuracy in the case of slow signal slopes. • Mode 2: A 0x7F character frame (it may be a 0x7F character in LSB first mode or a 0xFE in MSB first mode). In this case, the baud rate is updated first at the end of the start bit (BRs), then at the end of bit 6 (based on the measurement done from falling edge to falling edge: BR6). Bit0 to bit6 are sampled at BRs while further bits of the character are sampled at BR6. • Mode 3: A 0x55 character frame. In this case, the baud rate is updated first at the end of the start bit (BRs), then at the end of bit0 (based on the measurement done from falling edge to falling edge: BR0), and finally at the end of bit6 (BR6). Bit 0 is sampled at BRs, bit 1 to bit 6 are sampled at BR0, and further bits of the character are sampled at BR6. In parallel, another check is performed for each intermediate RX line transition. An error is generated if the transitions on RX are not sufficiently synchronized with the receiver (the receiver being based on the baud rate calculated on bit 0). Prior to activating the auto baud rate detection, the USART_BRR register must be initialized by writing a non-zero baud rate value. The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2 register. The USART will then wait for the first character on the RX line. The auto baud rate operation completion is indicated by the setting of the ABRF flag in the USART_ISR register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this case the BRR value may be corrupted and the ABRE error flag will be set. This also happens if the communication speed is not compatible with the automatic baud rate detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between 8 and 65536 clock periods (oversampling by 8)). The auto baud rate detection can be re-launched later by resetting the ABRF flag (by writing a ‘0’). When FIFO management is disabled and an auto baud rate error occurs, the ABRE flag is set through RXNE and FE bits. When FIFO management is enabled and an auto baud rate error occurs, the ABRE flag is set through RXFNE and FE bits. If the FIFO mode is enabled, the auto baud rate detection should be made using the data on the first RXFIFO location. So, prior to launching the auto baud rate detection, make sure that the RXFIFO is empty by checking the RXFNE flag in USART_ISR register. Note: The BRR value might be corrupted if the USART is disabled (UE=’0’) during an auto baud rate operation. DocID029587 Rev 3 1973/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.5.10 RM0433 USART multiprocessor communication It is possible to perform USART multiprocessor communications (with several USARTs connected in a network). For instance one of the USARTs can be the master with its TX output connected to the RX inputs of the other USARTs, while the others are slaves with their respective TX outputs logically ANDed together and connected to the RX input of the master. In multiprocessor configurations, it is often desirable that only the intended message recipient actively receives the full message contents, thus reducing redundant USART service overhead for all non addressed receivers. The non-addressed devices can be placed in Mute mode by means of the muting function. To use the Mute mode feature, the MME bit must be set in the USART_CR1 register. Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared and then set again quickly (within two usart_ker_ck cycles), otherwise Mute mode might remain active. When the Mute mode is enabled: • none of the reception status bits can be set; • all the receive interrupts are inhibited; • the RWU bit in USART_ISR register is set to ‘1’. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the USART_RQR register, under certain conditions. The USART can enter or exit from Mute mode using one of two methods, depending on the WAKE bit in the USART_CR1 register: • Idle Line detection if the WAKE bit is reset, • Address Mark detection if the WAKE bit is set. Idle line detection (WAKE=’0’) The USART enters Mute mode when the MMRQ bit is written to ‘1’ and the RWU is automatically set. The USART wakes up when an Idle frame is detected. The RWU bit is then cleared by hardware but the IDLE bit is not set in the USART_ISR register. An example of Mute mode behavior using Idle line detection is given in Figure 569. 1974/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 569. Mute mode using Idle line detection 5;1( 'DWD 'DWD 'DWD 'DWD 5; ,'/( 0XWHPRGH 5:8 0054ZULWWHQWR 5;1( 'DWD 'DWD 1RUPDOPRGH ,GOHIUDPHGHWHFWHG 06Y9 Note: If the MMRQ is set while the IDLE character has already elapsed, Mute mode will not be entered (RWU is not set). If the USART is activated while the line is IDLE, the idle state is detected after the duration of one IDLE frame (not only after the reception of one character frame). 4-bit/7-bit address mark detection (WAKE=’1’) In this mode, bytes are recognized as addresses if their MSB is a ‘1’, otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the USART_CR2 register. Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and ADD[7:0]) respectively. The USART enters Mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the USART enters Mute mode. When FIFO management is enabled, the software should ensure that there is at least one empty location in the RXFIFO before entering Mute mode. The USART also enters Mute mode when the MMRQ bit is written to 1. The RWU bit is also automatically set in this case. The USART exits from Mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE/RXFNE bit is set for the address character since the RWU bit has been cleared. Note: When FIFO management is enabled, when MMRQ is set while the receiver is sampling last bit of a data, this data may be received before effectively entering in Mute mode An example of Mute mode behavior using address mark detection is given in Figure 570. DocID029587 Rev 3 1975/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Figure 570. Mute mode using address mark detection ,QWKLVH[DPSOHWKHFXUUHQWDGGUHVVRIWKHUHFHLYHULV SURJUDPPHGLQWKH86$57B&5UHJLVWHU 5;1( ,'/( 5; $GGU 'DWD 'DWD 5:8 ,'/( 5;1( $GGU 'DWD 'DWD $GGU 'DWD 0XWHPRGH 1RUPDOPRGH 0DWFKLQJDGGUHVV 0054ZULWWHQWR 5;1(ZDVFOHDUHG 5;1( 0XWHPRGH 1RQPDWFKLQJDGGUHVV 1RQPDWFKLQJDGGUHVV 06Y9 48.5.11 USART Modbus communication The USART offers basic support for the implementation of Modbus/RTU and Modbus/ASCII protocols. Modbus/RTU is a Half-duplex, block-transfer protocol. The control part of the protocol (address recognition, block integrity control and command interpretation) must be implemented in software. The USART offers basic support for the end of the block detection, without software overhead or other resources. Modbus/RTU In this mode, the end of one block is recognized by a “silence” (idle line) for more than 2 character times. This function is implemented through the programmable timeout function. The timeout function and interrupt must be activated, through the RTOEN bit in the USART_CR2 register and the RTOIE in the USART_CR1 register. The value corresponding to a timeout of 2 character times (for example 22 x bit time) must be programmed in the RTO register. When the receive line is idle for this duration, after the last stop bit is received, an interrupt is generated, informing the software that the current block reception is completed. Modbus/ASCII In this mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function. By programming the LF ASCII code in the ADD[7:0] field and by activating the character match interrupt (CMIE=’1’), the software is informed when a LF has been received and can check the CR/LF in the DMA buffer. 1976/3178 DocID029587 Rev 3 RM0433 48.5.12 Universal synchronous asynchronous receiver transmitter (USART) USART parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bits, the possible USART frame formats are as listed in Table 380. Table 380. USART frame formats M bits PCE bit USART frame(1) 00 0 | SB | 8 bit data | STB | 00 1 | SB | 7-bit data | PB | STB | 01 0 | SB | 9-bit data | STB | 01 1 | SB | 8-bit data PB | STB | 10 0 | SB | 7bit data | STB | 10 1 | SB | 6-bit data | PB | STB | 1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB position (8th or 7th, depending on the M bit value). Even parity The parity bit is calculated to obtain an even number of “1s” inside the frame of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit. As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even parity is selected (PS bit in USART_CR1 = ’0’). Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit. As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is selected (PS bit in USART_CR1 = ’1’). Parity checking in reception If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the USART_ICR register. Parity generation in transmission If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=’0’) or an odd number of “1s” if odd parity is selected (PS=’1’)). DocID029587 Rev 3 1977/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.5.13 RM0433 USART LIN (local interconnection network) mode This section is relevant only when LIN mode is supported. Please refer to Section 48.4: USART implementation on page 1953. The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: • CLKEN in the USART_CR2 register, • STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. LIN transmission The procedure described in Section 48.5.4 has to be applied for LIN Master transmission. It must be the same as for normal USART transmission with the following differences: • Clear the M bit to configure 8-bit word length. • Set the LINEN bit to enter LIN mode. In this case, setting the SBKRQ bit sends 13 ‘0 bits as a break character. Then 2 bits of value ‘1 are sent to allow the next start detection. LIN reception When LIN mode is enabled, the break detection circuit is activated. The detection is totally independent from the normal USART receiver. A break can be detected whenever it occurs, during Idle state or during a frame. When the receiver is enabled (RE=’1’ in USART_CR1), the circuit looks at the RX input for a start signal. The method for detecting start bits is the same when searching break characters or data. After a start bit has been detected, the circuit samples the next bits exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = ’0’ in USART_CR2) or 11 (when LBDL=’1’ in USART_CR2) consecutive bits are detected as ‘0, and are followed by a delimiter character, the LBDF flag is set in USART_ISR. If the LBDIE bit=’1’, an interrupt is generated. Before validating the break, the delimiter is checked for as it signifies that the RX line has returned to a high level. If a ‘1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the current detection and searches for a start bit again. If the LIN mode is disabled (LINEN=’0’), the receiver continues working as normal USART, without taking into account the break detection. If the LIN mode is enabled (LINEN=’1’), as soon as a framing error occurs (i.e. stop bit detected at ‘0, which will be the case for any break frame), the receiver stops until the break detection circuit receives either a ‘1, if the break word was not complete, or a delimiter character if a break has been detected. The behavior of the break detector state machine and the break flag is shown on the Figure 571: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 1978. Examples of break frames are given on Figure 572: Break detection in LIN mode vs. Framing error detection on page 1979. 1978/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 571. Break detection in LIN mode (11-bit break length - LBDL bit is set) &DVH EUHDNVLJQDOQRWORQJHQRXJK !EUHDNGLVFDUGHG/%')LVQRWVHW %UHDNIUDPH 5;OLQH &DSWXUHVWUREH %UHDNVWDWH PDFKLQH ,GOH %LW %LW %LW %LW 5HDGVDPSOHV %LW %LW %LW %LW %LW %LW %LW ,GOH &DVH EUHDNVLJQDOMXVWORQJHQRXJK !EUHDNGHWHFWHG/%')LVVHW %UHDNIUDPH 5;OLQH 'HOLPLWHULVLPPHGLDWH &DSWXUHVWUREH %UHDNVWDWH PDFKLQH ,GOH %LW %LW %LW %LW 5HDGVDPSOHV %LW %LW %LW %LW %LW %LW % ,GOH /%') &DVH EUHDNVLJQDOORQJHQRXJK !EUHDNGHWHFWHG/%')LVVHW %UHDNIUDPH 5;OLQH &DSWXUHVWUREH %UHDNVWDWH ,GOH PDFKLQH 5HDGVDPSOHV %LW %LW %LW %LW %LW %LW %LW %LW %LW %LW %LW ZDLWGHOLPLWHU ,GOH /%') 06Y9 DocID029587 Rev 3 1979/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Figure 572. Break detection in LIN mode vs. Framing error detection &DVH EUHDNRFFXUULQJDIWHUDQ,GOH 5;OLQH GDWD ,'/( %5($. GDWDWLPH GDWD [ GDWD KHDGHU GDWDWLPH 5;1()( /%') &DVH EUHDNRFFXUULQJZKLOHGDWDLVEHLQJUHFHLYHG 5;OLQH GDWD GDWD %5($. GDWDWLPH GDWD [ GDWD KHDGHU GDWDWLPH 5;1()( /%') 06Y9 48.5.14 USART synchronous mode Master mode The synchronous master mode is selected by programming the CLKEN bit in the USART_CR2 register to ‘1’. In synchronous mode, the following bits must be kept cleared: • LINEN bit in the USART_CR2 register, • SCEN, HDSEL and IREN bits in the USART_CR3 register. In this mode, the USART can be used to control bidirectional synchronous serial communications in master mode. The SCLK pin is the output of the USART transmitter clock. No clock pulses are sent to the SCLK pin during start bit and stop bit. Depending on the state of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated during the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is used to select the clock polarity, and the CPHA bit in the USART_CR2 register is used to select the phase of the external clock (see Figure 573, Figure 574 and Figure 575). During the Idle state, preamble and send break, the external SCLK clock is not activated. In synchronous master mode, the USART transmitter operates exactly like in asynchronous mode. However, since SCLK is synchronized with TX (according to CPOL and CPHA), the data on TX is synchronous. In synchronous master mode, the USART receiver operates in a different way compared to asynchronous mode. If RE is set to ’1’, the data are sampled on SCLK (rising or falling edge, depending on CPOL and CPHA), without any oversampling. A given setup and a hold time must be respected (which depends on the baud rate: 1/16 bit time). 1980/3178 DocID029587 Rev 3 RM0433 Note: Universal synchronous asynchronous receiver transmitter (USART) In master mode, the SCLK pin operates in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=’1’) and data are being transmitted (USART_TDR data register written). This means that it is not possible to receive synchronous data without transmitting data. Figure 573. USART example of synchronous master transmission 5; 7; 'DWDRXW 'DWDLQ 6\QFKURQRXVGHYLFH HJVODYH63, 86$57 &ORFN 6&/. 06Y9 Figure 574. USART data clock timing diagram in synchronous master mode (M bits =’00’) ,GOHRUSUHFHGLQJ 6WDUW WUDQVPLVVLRQ ,GOHRUQH[W 6WRS WUDQVPLVVLRQ 0ELWV GDWDELWV &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ 'DWDRQ7; IURPPDVWHU 6WDUW 'DWDRQ5; IURPVODYH /6% 06% 6WRS 06% /6% &DSWXUHVWUREH /%&/ELWFRQWUROVODVWGDWDSXOVH 06Y 9 DocID029587 Rev 3 1981/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Figure 575. USART data clock timing diagram in synchronous master mode (M bits = ‘01’) ,GOHRU SUHFHGLQJ 6WDUW WUDQVPLVVLRQ 0ELWV GDWDELWV 6WRS ,GOHRUQH[W WUDQVPLVVLRQ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ 'DWDRQ7; IURPPDVWHU 'DWDRQ5; IURPVODYH 06% 6WDUW /6% /6% &DSWXUH VWUREH 6WRS 06% /%&/ELWFRQWUROVODVWGDWDSXOVH 06Y9 Slave mode The synchronous slave mode is selected by programming the SLVEN bit in the USART_CR2 register to ‘1’. In synchronous slave mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the USART_CR2 register, • SCEN, HDSEL and IREN bits in the USART_CR3 register. In this mode, the USART can be used to control bidirectional synchronous serial communications in slave mode. The SCLK pin is the input of the USART in slave mode. Note: When the peripheral is used in SPI slave mode, the frequency of peripheral clock source (usart_ker_ck_pres) must be greater than 3 times the CK input frequency. The CPOL bit and the CPHA bit in the USART_CR2 register are used to select the clock polarity and the phase of the external clock, respectively (see Figure 576). An underrun error flag is available in slave transmission mode. This flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value to USART_TDR. The slave supports the hardware and software NSS management. 1982/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 576. USART data clock timing diagram in synchronous slave mode (M bits =’00’) 0ELWV GDWDELWV 166 IURP0DVWHU &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ 'DWDRQ7; IURPVODYH /6% 'DWDRQ5; IURPPDVWHU 06% 06% /6% &DSWXUHVWUREH 06Y 9 Slave Select (NSS) pin management The hardware or software slave select management can be set through the DIS_NSS bit in the USART_CR2 register: • Software NSS management (DIS_NSS = ’1’) SPI slave will always be selected and NSS input pin will be ignored. The external NSS pin remains free for other application uses. • Hardware NSS management (DIS_NSS = ’0’) The SPI slave selection depends on NSS input pin. The slave is selected when NSS is low and deselected when NSS is high. Note: The LBCL (used only on SPI master mode), CPOL and CPHA bits have to be selected when the USART is disabled (UE=’0’) to ensure that the clock pulses function correctly. In SPI slave mode, the USART must be enabled before starting the master communications (or between frames while the clock is stable). Otherwise, if the USART slave is enabled while the master is in the middle of a frame, it will become desynchronized with the master. The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication, otherwise the SPI slave will transmit zeros. SPI Slave underrun error When an underrun error occurs, the UDR flag is set in the USART_ISR register, and the SPI slave goes on sending the last data until the underrrun error flag is cleared by software. The underrun flag is set at the beginning of the frame. An underrun error interrupt is triggered if EIE bit is set in the USART_CR3 register. The underrun error flag is cleared by setting bit UDRCF in the USART_ICR register. DocID029587 Rev 3 1983/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 In case of underrun error, it is still possible to write to the TDR register. Clearing the underrun error will allow sending new data. If an underrun error occurred and there is no new data written in TDR, then the TC flag is set at the end of the frame. Note: An underrun error may occur if the moment the data is written to the USART_TDR is too close to the first SCLK transmission edge. To avoid this underrun error, the USART_TDR should be written 3 usart_ker_ck cycles before the first SCLK edge. 48.5.15 USART single-wire Half-duplex communication Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the USART_CR2 register, • SCEN and IREN bits in the USART_CR3 register. The USART can be configured to follow a Single-wire Half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and Full-duplex communication is made with a control bit HDSEL in USART_CR3. As soon as HDSEL is written to ‘1’: • The TX and RX lines are internally connected. • The RX pin is no longer used. • The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up. Apart from this, the communication protocol is similar to normal USART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter). In particular, the transmission is never blocked by hardware and continues as soon as data are written in the data register while the TE bit is set. 48.5.16 USART receiver timeout The receiver timeout feature is enabled by setting the RTOEN bit in the USART_CR2 control register. The timeout duration is programmed using the RTO bitfields in the USART_RTOR register. The receiver timeout counter starts counting: • from the end of the stop bit if STOP = ‘00’ or STOP = ‘11’ • from the end of the second stop bit if STOP = ‘10’. • from the beginning of the stop bit if STOP = ‘01’. When the timeout duration has elapsed, the RTOF flag in the USART_ISR register is set. A timeout will be generated if RTOIE bit in USART_CR1 register is set. 1984/3178 DocID029587 Rev 3 RM0433 48.5.17 Universal synchronous asynchronous receiver transmitter (USART) USART Smartcard mode This section is relevant only when Smartcard mode is supported. Please refer to Section 48.4: USART implementation on page 1953. Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In Smartcard mode, the following bits must be kept cleared: • LINEN bit in the USART_CR2 register, • HDSEL and IREN bits in the USART_CR3 register. The CLKEN bit can also be set to provide a clock to the Smartcard. The Smartcard interface is designed to support asynchronous Smartcard protocol as defined in the ISO 7816-3 standard. Both T=’0’ (character mode) and T=’1’ (block mode) are supported. The USART should be configured as: • 8 bits plus parity: M=’1’ and PCE=’1’ in the USART_CR1 register • 1.5 stop bits when transmitting and receiving data: STOP=’11’ in the USART_CR2 register. It is also possible to choose 0.5 stop bit for reception. In T=’0’ (character) mode, the parity error is indicated at the end of each character during the guard time period. Figure 577 shows examples of what can be seen on the data line with and without parity error. Figure 577. ISO 7816-3 asynchronous protocol :LWKRXW3DULW\HUURU 6 *XDUGWLPH S 6WDUWELW :LWK3DULW\HUURU 6 *XDUGWLPH 6WDUWELW S /LQHSXOOHGORZE\UHFHLYHU GXULQJVWRSLQFDVHRISDULW\HUURU 06Y9 When connected to a Smartcard, the TX output of the USART drives a bidirectional line that is also driven by the Smartcard. The TX pin must be configured as open drain. Smartcard mode implements a single wire half duplex communication protocol. • Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation a full transmit shift register starts shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • In transmission, if the Smartcard detects a parity error, it signals this condition to the USART by driving the line low (NACK). This NACK signal (pulling transmit line low for 1 baud clock) causes a framing error on the transmitter side (configured with 1.5 stop bits). The USART can handle automatic re-sending of data according to the protocol. DocID029587 Rev 3 1985/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 The number of retries is programmed in the SCARCNT bitfield. If the USART continues receiving the NACK after the programmed number of retries, it stops transmitting and signals the error as a framing error. The TXE bit (TXFNF bit in case FIFO mode is enabled) may be set using the TXFRQ bit in the USART_RQR register. Note: • Smartcard auto-retry in transmission: A delay of 2.5 baud periods is inserted between the NACK detection by the USART and the start bit of the repeated character. The TC bit is set immediately at the end of reception of the last repeated character (no guardtime). If the software wants to repeat it again, it must insure the minimum 2 baud periods required by the standard. • If a parity error is detected during reception of a frame programmed with a 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. This is to indicate to the Smartcard that the data transmitted to the USART has not been correctly received. A parity error is NACKed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted (to be used in T=1 mode). If the received character is erroneous, the RXNE (RXFNE in case FIFO mode is enabled)/receive DMA request is not activated. According to the protocol specification, the Smartcard must resend the same character. If the received character is still erroneous after the maximum number of retries specified in the SCARCNT bitfield, the USART stops transmitting the NACK and signals the error as a parity error. • Smartcard auto-retry in reception: the BUSY flag remains set if the USART NACKs the card but the card doesn’t repeat the character. • In transmission, the USART inserts the Guard Time (as programmed in the Guard Time register) between two successive characters. As the Guard Time is measured after the stop bit of the previous character, the GT[7:0] register must be programmed to the desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12 (the duration of one character). • The assertion of the TC flag can be delayed by programming the Guard Time register. In normal operation, TC is asserted when the transmit shift register is empty and no further transmit requests are outstanding. In Smartcard mode an empty transmit shift register triggers the Guard Time counter to count up to the programmed value in the Guard Time register. TC is forced low during this time. When the Guard Time counter reaches the programmed value TC is asserted high. The TCBGT flag can be used to detect the end of data transfer without waiting for guard time completion. This flag is set just after the end of frame transmission and if no NACK has been received from the card. • The de-assertion of TC flag is unaffected by Smartcard mode. • If a framing error is detected on the transmitter end (due to a NACK from the receiver), the NACK is not detected as a start bit by the receive block of the transmitter. According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud clock periods. • On the receiver side, if a parity error is detected and a NACK is transmitted the receiver does not detect the NACK as a start bit. Break characters are not significant in Smartcard mode. A 0x00 data with a framing error is treated as data and not as a break. No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the other configurations) is not defined by the ISO protocol. Figure 578 shows how the NACK signal is sampled by the USART. In this example the USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the USART is enabled in order to check the integrity of the data and the NACK signal. 1986/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 578. Parity error detection using the 1.5 stop bits %LW 3DULW\ELW ELWWLPH 6WRSELW ELWWLPH 6DPSOLQJDW 6DPSOLQJDW WK WKWK WK WKWK ELWWLPH 6DPSOLQJDW 6DPSOLQJDW WK WKWK WK WKWK 06Y9 The USART can provide a clock to the Smartcard through the SCLK output. In Smartcard mode, SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. The division ratio is configured in the USART_GTPR register. SCLK frequency can be programmed from usart_ker_ck_pres/2 to usart_ker_ck_pres/62, where usart_ker_ck_pres is the peripheral input clock divided by a programmed prescaler. Block mode (T=’1’) In T=’1’ (block) mode, the parity error transmission can be deactivated by clearing the NACK bit in the UART_CR3 register. When requesting a read from the Smartcard, in block mode, the software must program the RTOR register to the BWT (block wait time) - 11 value. If no answer is received from the card before the expiration of this period, a timeout interrupt will be generated. If the first character is received before the expiration of the period, it is signaled by the RXNE/RXFNE interrupt. Note: The RXNE/RXFNE interrupt must be enabled even when using the USART in DMA mode to read from the Smartcard in block mode. In parallel, the DMA must be enabled only after the first received byte. After the reception of the first character (RXNE/RXFNE interrupt), the RTO register must be programmed to the CWT (character wait time -11 value), in order to allow the automatic check of the maximum wait time between two consecutive characters. This time is expressed in baud time units. If the Smartcard does not send a new character in less than the CWT period after the end of the previous character, the USART will signal it to the software through the RTOF flag and interrupt (when RTOIE bit is set). Note: As in the Smartcard protocol definition, the BWT/CWT values should be defined from the beginning (start bit) of the last character. The RTO register must be programmed to BWT 11 or CWT -11, respectively, taking into account the length of the last character itself. A block length counter is used to count all the characters received by the USART. This counter is reset when the USART is transmitting. The length of the block is communicated by the Smartcard in the third byte of the block (prologue field). This value must be programmed to the BLEN field in the USART_RTOR register. When using DMA mode, before the start of the block, this register field must be programmed to the minimum value DocID029587 Rev 3 1987/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 (0x0). With this value, an interrupt is generated after the 4th received character. The software must read the LEN field (third byte), its value must be read from the receive buffer. In interrupt driven receive mode, the length of the block may be checked by software or by programming the BLEN value. However, before the start of the block, the maximum value of BLEN (0xFF) may be programmed. The real value will be programmed after the reception of the third character. If the block is using the LRC longitudinal redundancy check (1 epilogue byte), the BLEN=LEN. If the block is using the CRC mechanism (2 epilog bytes), BLEN=LEN+1 must be programmed. The total block length (including prologue, epilogue and information fields) equals BLEN+4. The end of the block is signaled to the software through the EOBF flag and interrupt (when EOBIE bit is set). In case of an error in the block length, the end of the block is signaled by the RTO interrupt (Character Wait Time overflow). Note: The error checking code (LRC/CRC) must be computed/verified by software. Direct and inverse convention The Smartcard protocol defines two conventions: direct and inverse. The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=’0’, DATAINV=’0’ (default values). The inverse convention is defined as: MSB first, logical bit value 1 corresponds to an L state on the signal line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=’1’, DATAINV=’1’. Note: When logical data values are inverted (0=H, 1=L), the parity bit is also inverted in the same way. In order to recognize the card convention, the card sends the initial character, TS, as the first character of the ATR (Answer To Reset) frame. The two possible patterns for the TS are: LHHL LLL LLH and LHHL HHH LLH. • (H) LHHL LLL LLH sets up the inverse convention: state L encodes value 1 and moment 2 conveys the most significant bit (MSB first). When decoded by inverse convention, the conveyed byte is equal to '3F'. • (H) LHHL HHH LLH sets up the direct convention: state H encodes value 1 and moment 2 conveys the least significant bit (LSB first). When decoded by direct convention, the conveyed byte is equal to '3B'. Character parity is correct when there is an even number of bits set to 1 in the nine moments 2 to 10. As the USART does not know which convention is used by the card, it needs to be able to recognize either pattern and act accordingly. The pattern recognition is not done in hardware, but through a software sequence. Moreover, supposing that the USART is configured in direct convention (default) and the card answers with the inverse convention, TS = LHHL LLL LLH => the USART received character will be ‘03’ and the parity will be odd. 1988/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Therefore, two methods are available for TS pattern recognition: Method 1 The USART is programmed in standard Smartcard mode/direct convention. In this case, the TS pattern reception generates a parity error interrupt and error signal to the card. • The parity error interrupt informs the software that the card did not answer correctly in direct convention. Software then reprograms the USART for inverse convention • In response to the error signal, the card retries the same TS character, and it will be correctly received this time, by the reprogrammed USART Alternatively, in answer to the parity error interrupt, the software may decide to reprogram the USART and to also generate a new reset command to the card, then wait again for the TS. Method 2 The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives any of the two TS patterns as: (H) LHHL LLL LLH = 0x103 -> inverse convention to be chosen (H) LHHL HHH LLH = 0x13B -> direct convention to be chosen The software checks the received character against these two patterns and, if any of them match, then programs the USART accordingly for the next character reception. If none of the two is recognized, a card reset may be generated in order to restart the negotiation. 48.5.18 USART IrDA SIR ENDEC block This section is relevant only when IrDA mode is supported. Please refer to Section 48.4: USART implementation on page 1953. IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: • LINEN, STOP and CLKEN bits in the USART_CR2 register, • SCEN and HDSEL bits in the USART_CR3 register. The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse (see Figure 579). The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream output from USART. The output pulse stream is transmitted to an external output driver and infrared LED. USART supports only bit rates up to 115.2 Kbps for the SIR ENDEC. In normal mode the transmitted pulse width is specified as 3/16 of a bit period. The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The decoder input is normally high (marking state) in the Idle state. The transmit encoder output has the opposite polarity to the decoder input. A start bit is detected when the decoder input is low. • IrDA is a half duplex communication protocol. If the Transmitter is busy (when the USART is sending data to the IrDA encoder), any data on the IrDA receive line is ignored by the IrDA decoder and if the Receiver is busy (when the USART is receiving decoded data from the USART), data on the TX from the USART to IrDA is not DocID029587 Rev 3 1989/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 encoded. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. • A ‘0‘ is transmitted as a high pulse and a ‘1’ is transmitted as a ‘0’. The width of the pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 580). • The SIR decoder converts the IrDA compliant receive signal into a bit stream for USART. • The SIR receive logic interprets a high state as a logic one and low pulses as logic zeros. • The transmit encoder output has the opposite polarity to the decoder input. The SIR output is in low state when Idle. • The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The acceptable pulse width is programmable. Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods (PSC is the prescaler value programmed in the USART_GTPR). Pulses of width less than 1 PSC period are always rejected, but those of width greater than one and less than two periods may be accepted or rejected, those greater than 2 periods will be accepted as a pulse. The IrDA encoder/decoder doesn’t work when PSC=’0’. • The receiver can communicate with a low-power transmitter. • In IrDA mode, the stop bits in the USART_CR2 register must be configured to ‘1 stop bit’. IrDA low-power mode • Transmitter In low-power mode, the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A lowpower mode programmable divisor divides the system clock to achieve this value. • Receiver Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in the USART_GTPR). Note: A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception (IrDA is a half duplex protocol). 1990/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 579. IrDA SIR ENDEC block diagram 7; 25 6,5(1 86$57B7; 6,5 7UDQVPLW (QFRGHU ,U'$B287 6,5 5HFHLYH '(FRGHU ,U'$B,1 86$57 5; 86$57B5; 06Y9 Figure 580. IrDA data modulation (3/16) - Normal mode 7; 6WDUW ELW 6WRS ELW ,U'$B287 %LWSHULRG ,U'$B,1 5; 06Y9 DocID029587 Rev 3 1991/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.5.19 RM0433 Continuous communication using USART and DMA The USART is capable of performing continuous communications using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Refer to Section 48.4: USART implementation on page 1953 to determine if the DMA mode is supported. If DMA is not supported, use the USART as explained in Section 48.5.6. To perform continuous communications when the FIFO is disabled, clear the TXE/ RXNE flags in the USART_ISR register. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data are loaded from an SRAM area configured using the DMA peripheral (refer to Section 15: Direct memory access controller (DMA1, DMA2) andSection 16: Basic direct memory access controller (BDMA)) to the USART_TDR register whenever the TXE flag (TXFNF flag if FIFO mode is enabled) is set. To map a DMA channel for USART transmission, use the following procedure (x denotes the channel number): 1. Write the USART_TDR register address in the DMA control register to configure it as the destination of the transfer. The data is moved to this address from memory after each TXE (or TXFNF if FIFO mode is enabled) event. 2. Write the memory address in the DMA control register to configure it as the source of the transfer. The data is loaded into the USART_TDR register from this memory area after each TXE (or TXFNF if FIFO mode is enabled) event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA register 5. Configure DMA interrupt generation after half/ full transfer as required by the application. 6. Clear the TC flag in the USART_ISR register by setting the TCCF bit in the USART_ICR register. 7. Activate the channel in the DMA register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART communication is complete. This is required to avoid corrupting the last transmission before disabling the USART or before the system enters a low-power mode when the peripheral clock is disabled. Software must wait until TC=’1’. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame. 1992/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 581. Transmission using DMA ,GOHSUHDPEOH )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 7;(IODJ 6HWE\KDUGZDUH ,JQRUHGE\WKH'0$EHFDXVH WKHWUDQVIHULVFRPSOHWH '0$UHTXHVW ) 86$57B7'5 ) ) 7&IODJ 6HWE\ KDUGZDUH '0$ZULWHV 86$57B7'5 '0$7&,)IODJ WUDQVIHU FRPSOHWH 6HWE\KDUGZDUH 6RIWZDUH FRQILJXUHV'0$ '0$ZULWHV '0$ZULWHV '0$ZULWHV )LQWR )LQWR )LQWR WRVHQGGDWD EORFNVDQG 86$57B7'5 86$57B7'5 86$57B7'5 HQDEOHV86$57 &OHDUHG E\ VRIWZDUH 7KH'0$ WUDQVIHULV FRPSOHWH 7&,) LQ '0$B,65 6RIWZDUHZDLWVXQWLO7& AIB Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full (i.e. TXFNF = ’1’). Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data are loaded from the USART_RDR register to an SRAM area configured using the DMA peripheral (refer to Section 15: Direct memory access controller (DMA1, DMA2) and Section 16: Basic direct memory access controller (BDMA)) whenever a data byte is received. To map a DMA channel for USART reception, use the following procedure: 1. Write the USART_RDR register address in the DMA control register to configure it as the source of the transfer. The data is moved from this address to the memory after each RXNE (RXFNE in case FIFO mode is enabled) event. 2. Write the memory address in the DMA control register to configure it as the destination of the transfer. The data is loaded from USART_RDR to this memory area after each RXNE (RXFNE in case FIFO mode is enabled) event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA control register 5. Configure interrupt generation after half/ full transfer as required by the application. 6. Activate the channel in the DMA control register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. DocID029587 Rev 3 1993/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Figure 582. Reception using DMA )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 5;1(IODJ '0$UHTXHVW ) ) 86$57B7'5 ) '0$UHDGV 86$57B7'5 '0$7&,)IODJ WUDQVIHUFRPSOHWH 6RIWZDUHFRQILJXUHVWKH '0$WRUHFHLYHGDWD EORFNVDQGHQDEOHV WKH86$57 &OHDUHG E\ VRIWZDUH 6HWE\KDUGZDUH '0$UHDGV) IURP86$57B7'5 '0$UHDGV) IURP86$57B7'5 7KH'0$WUDQVIHU '0$UHDGV) LVFRPSOHWH IURP86$57B7'5 7&,) LQ '0$B,65 DL E Note: When FIFO management is enabled, the DMA request is triggered by Receive FIFO not empty (i.e. RXFNE = ’1’). Error flagging and interrupt generation in multibuffer communication If any error occurs during a transaction in multibuffer communication mode, the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur. 48.5.20 RS232 Hardware flow control and RS485 Driver Enable It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. The Figure 583 shows how to connect 2 devices in this mode: Figure 583. Hardware flow control between 2 USARTs 86$57 86$57 7; 7;FLUFXLW &76 5; 5; 576 5;FLUFXLW 7; 5;FLUFXLW 7;FLUFXLW 576 &76 06Y 9 1994/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits to ‘1’ in the USART_CR3 register. RS232 RTS flow control If the RTS flow control is enabled (RTSE=’1’), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 584 shows an example of communication with RTS flow control enabled. Figure 584. RS232 RTS flow control 5; 6WDUW ELW 'DWD 6WRS 6WDUW ,GOH ELW ELW 'DWD 6WRS ELW 576 5;1( 5;1( 'DWDUHDG 'DWDFDQQRZEHWUDQVPLWWHG 06Y9 Note: When FIFO mode is enabled, nRTS is de-asserted only when RXFIFO is full. RS232 CTS flow control If the CTS flow control is enabled (CTSE=’1’), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that data is to be transmitted, in other words, if TXE/TXFE=’0’), else the transmission does not occur. When nCTS is deasserted during a transmission, the current transmission is completed before the transmitter stops. When CTSE=’1’, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 585 shows an example of communication with CTS flow control enabled. DocID029587 Rev 3 1995/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Figure 585. RS232 CTS flow control &76 &76 &76 7UDQVPLWGDWDUHJLVWHU 7'5 'DWD 7; 'DWD HPSW\ 6WRS 6WDUW ELW ELW HPSW\ 'DWD 'DWD :ULWLQJGDWDLQ7'5 6WRS 6WDUW ,GOH ELW ELW 'DWD 7UDQVPLVVLRQRI'DWDLV GHOD\HGXQWLO&76 06Y9 Note: For correct behavior, nCTS must be asserted at least 3 USART clock source periods before the end of the current character. In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods. RS485 driver enable The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register. This allows the user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the USART_CR1 control register. The de-assertion time is the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed using the DEDT [4:0] bitfields in the USART_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the USART_CR3 control register. In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). 48.5.21 USART low-power management The USART has advanced low-power mode functions, that allow transferring properly data even when the usart_pclk clock is disabled. The USART is able to wake up the MCU from low-power mode when the UESM bit is set. 1996/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) When the usart_pclk is gated, the USART provides a wakeup interrupt (usart_wkup) if a specific action requiring the activation of the usart_pclk clock is needed: • If FIFO mode is disabled usart_pclk clock has to be activated to empty the USART data register. In this case, the usart_wkup interrupt source is RXNE set to ‘1’. The RXNEIE bit must be set before entering low-power mode. • If FIFO mode is enabled usart_pclk clock has to be activated to: – to fill the TXFIFO – or to empty the RXFIFO In this case, the usart_wkup interrupt source can be: – RXFIFO not empty. In this case, the RXFNEIE bit must be set before entering lowpower mode. – RXFIFO full. In this case, the RXFFIE bit must be set before entering low-power mode, the number of received data corresponds to the RXFIFO size, and the RXFF flag is not set. – TXFIFO empty. In this case, the TXFEIE bit must be set before entering low-power mode. This allows sending/receiving the data in the TXFIFO/RXFIFO during low-power mode. To avoid overrun/underrun errors and transmit/receive data in low-power mode, the usart_wkup interrupt source can be one of the following events: – TXFIFO threshold reached. In this case, the TXFTIE bit must be set before entering low-power mode. – RXFIFO threshold reached. In this case, the RXFTIE bit must be set before entering low-power mode. For example, the application can set the threshold to the maximum RXFIFO size if the wakeup time is less than the time required to receive a single byte across the line. Using the RXFIFO full, TXFIFO empty, RXFIFO not empty and RXFIFO/TXFIFO threshold interrupts to wakeup the MCU from low-power mode allows doing as many USART transfers as possible during low-power mode with the benefit of optimizing consumption. Alternatively, a specific usart_wkup interrupt can be selected through the WUS bitfields. When the wakeup event is detected, the WUF flag is set by hardware and a usart_wkup interrupt is generated if the WUFIE bit is set. In this case the usart_wkup interrupt is not mandatory and setting the WUF being is sufficient to wake up the MCU from low-power mode. DocID029587 Rev 3 1997/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) Note: RM0433 Before entering low-power mode, make sure that no USART transfers are ongoing. Checking the BUSY flag cannot ensure that low-power mode is never entered when data reception is ongoing. The WUF flag is set when a wakeup event is detected, independently of whether the MCU is in low-power or active mode. When entering low-power mode just after having initialized and enabled the receiver, the REACK bit must be checked to make sure the USART is enabled. When DMA is used for reception, it must be disabled before entering low-power mode and re-enabled when exiting from low-power mode. When the FIFO is enabled, waking up from low-power mode on address match is only possible when Mute mode is enabled. Using Mute mode with low-power mode If the USART is put into Mute mode before entering low-power mode: Note: • Wakeup from Mute mode on idle detection must not be used, because idle detection cannot work in low-power mode. • If the wakeup from Mute mode on address match is used, then the low-power mode wakeup source must also be the address match. If the RXNE flag was set when entering the low-power mode, the interface will remain in Mute mode upon address match and wake up from low-power mode. When FIFO management is enabled, Mute mode can be used with wakeup from low-power mode without any constraints (i.e.the two points mentioned above about Mute and lowpower mode are valid only when FIFO management is disabled). Wakeup from low-power mode when USART kernel clock (usart_ker_ck) is OFF in low-power mode If during low-power mode, the usart_ker_ck clock is switched OFF when a falling edge on the USART receive line is detected, the USART interface requests the usart_ker_ck clock to be switched ON thanks to the usart_ker_ck_req signal. usart_ker_ck is then used for the frame reception. If the wakeup event is verified, the MCU wakes up from low-power mode and data reception goes on normally. If the wakeup event is not verified, usart_ker_ck is switched OFF again, the MCU is not woken up and remains in low-power mode, and the kernel clock request is released. The example below shows the case of a wakeup event programmed to “address match detection” and FIFO management disabled. 1998/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Figure 586 shows the USART behavior when the wakeup event is verified. Figure 586. Wakeup event verified (wakeup event = address match, FIFO disabled) 'DWDUHFHSWLRQJRHVRQ 5[GDWD 6WRSELW 5[GDWD 6WDUWELW 5;OLQH 6WRSELW ,GOH 6WDUWELW $GGUHVVPDWFKHYHQW:8) ¶ 86$57VHQGVDZDNHXSHYHQWWRWKH0&8 6WDUWXSWLPH 8VDUWBNHUBFN 21 2)) /RZSRZHUPRGH 5XQPRGH 06Y9 Figure 587 shows the USART behavior when the wakeup event is not verified. Figure 587. Wakeup event not verified (wakeup event = address match, FIFO disabled) 5;OLQH ,GOH 5[GDWD 6WRSELW ,GOH 6WDUWELW $GGUHVVGRHVQRWPDWFK 6WDUWXSWLPH 8VDUWBNHUBFN 2)) 21 2)) /RZSRZHUPRGH 06Y9 Note: The figures above are valid when address match or any received frame is used as wakeup event. If the wakeup event is the start bit detection, the USART sends the wakeup event to the MCU at the end of the start bit. DocID029587 Rev 3 1999/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.6 RM0433 USART interrupts During USART communications, an interrupt (usart_it) can be generated by different events. The USART block can also generate a wakeup interrupt (usart_wkup). Refer to Table 381 for a detailed description of all USART interrupt requests. Table 381. USART interrupt requests Interrupt event Transmit data register empty Transmit FIFO Not Full Transmit FIFO Empty Event flag Enable Control bit TXE TXEIE TXFNF TXFE Interrupt activated Interrupt clear method usart_it usart_wkup TXE cleared when a data is written in TDR YES NO TXFNFIE TXFNF cleared when TXFIFO is full. YES NO TXFEIE TXFE cleared when the TXFIFO contains at least one data or by setting TXFRQ bit. YES YES YES YES Transmit FIFO threshold reached TXFT TXFTIE TXFT is cleared by hardware when the TXFIFO content is less than the programmed threshold CTS interrupt CTSIF CTSIE CTSIF cleared by software by setting CTSCF bit. YES NO Transmission Complete TC TCIE TC cleared when a data is written in TDR or by setting TCCF bit. YES NO Transmission Complete Before Guard Time TCBGT TCBGT cleared when a data is TCBGTIE written in TDR or by setting TCBGTCF bit. YES NO RXNE cleared by reading RDR or by setting RXFRQ bit. YES YES RXFNE cleared when the RXFNEIE RXFIFO is empty or by setting RXFRQ bit. YES YES RXFFIE RXFF cleared when the RXFIFO contains at least one data. YES YES YES YES Receive data register not empty (data ready to be read) RXNE Receive FIFO Not Empty RXFNE Receive FIFO Full RXFF(1) RXNEIE Receive FIFO threshold reached RXFT RXFTIE RXFT is cleared by hardware when the RXFIFO content is less than the programmed threshold Overrun error detected ORE RXNEIE/RX FNEIE ORE cleared by setting ORECF bit. YES NO Idle line detected IDLE IDLEIE IDLE cleared by setting IDLECF bit. YES NO 2000/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Table 381. USART interrupt requests Interrupt event Parity error LIN break Noise Flag, Overrun error and Framing Error in multibuffer communication. Event flag Enable Control bit PE PEIE LBDF LBDIE Interrupt activated Interrupt clear method usart_it usart_wkup PE cleared by setting PECF bit. YES NO LBDF cleared by setting LBDCF bit. YES NO NE cleared by setting NFCF bit. ORE cleared by setting ORECF bit. FE flag cleared by setting FECF bit. YES NO CMF cleared by setting CMCF bit. YES NO NE or ORE or FE EIE Character match CMF CMIE Receiver timeout RTOF RTOFIE RTOF cleared by setting RTOCCF bit. YES NO End of Block EOBF EOBIE EOBF is cleared by setting EOBCF bit. YES NO Wakeup from low-power mode WUF(2) WUFIE WUF is cleared by setting WUCF bit. NO YES SPI slave underrun error UDR EIE UDR is cleared by setting UDRCF bit. YES NO TXFTIE TXFT is cleared by hardware when the TXFIFO content is less than the programmed threshold YES YES RXFTIE RXFT is cleared by hardware when the RXFIFO content is less than the programmed threshold. YES YES Transmit FIFO threshold reached Receive FIFO threshold reached TXFT RXFT 1. RXFF flag is asserted if the USART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in USART_RDR. In Stop mode, USART_RDR is not clocked. As a result, this register will not be written and once n data are received and written in the RXFIFO, the RXFF interrupt will be asserted (RXFF flag is not set). 2. The WUF interrupt is active only in low-power mode. DocID029587 Rev 3 2001/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.7 RM0433 USART registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. 48.7.1 USART control register 1 (USART_CR1) Address offset: 0x00 Reset value: 0x0000 30 29 28 27 26 RXF FIE 31 TXFEIE FIFO EN 25 24 M1 EOBIE RTOIE rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 23 22 21 20 19 DEAT[4:0] rw 8 7 6 TCIE rw OVER8 CMIE MME M0 WAKE PCE PS PEIE rw rw rw rw rw rw rw rw rw 17 16 DEDT[4:0] rw TXEIE/ TXFNFI E 18 rw rw rw rw rw rw 5 4 3 2 1 0 TE RE UESM UE rw rw rw rw RXNEIE /RXFNE IDLEIE IE rw rw Bit 31 RXFFIE:RXFIFO Full interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when RXFF=’1’ in the USART_ISR register Note: When FIFO mode is disabled, this bit is reserved and must be kept at reset value. Bit 30 TXFEIE:TXFIFO empty interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when TXFE=’1’ in the USART_ISR register Note: When FIFO mode is disabled, this bit is reserved and must be kept at reset value. Bit 29 FIFOEN:FIFO mode enable This bit is set and cleared by software. 0: FIFO mode is disabled. 1: FIFO mode is enabled. This bitfield can only be written when the USART is disabled (UE=’0’). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. Bit 28 M1: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=’0’). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. 2002/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 27 EOBIE: End of Block interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when the EOBF flag is set in the USART_ISR register Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 26 RTOIE: Receiver timeout interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when the RTOF bit is set in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Section 48.4: USART implementation on page 1953. Bits 25:21 DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=’0’). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Please refer to Section 48.4: USART implementation on page 1953. Bits 20:16 DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=’0’). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Please refer to Section 48.4: USART implementation on page 1953. Bit 15 OVER8: Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 This bit can only be written when the USART is disabled (UE=’0’). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. Bit 14 CMIE: Character match interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when the CMF bit is set in the USART_ISR register. Bit 13 MME: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. 0: Receiver in active mode permanently 1: Receiver can switch between Mute mode and active mode. Bit 12 M0: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=’0’). DocID029587 Rev 3 2003/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bit 11 WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. 0: Idle line 1: Address mark This bitfield can only be written when the USART is disabled (UE=’0’). Bit 10 PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=’1’; 8th bit if M=’0’) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled This bitfield can only be written when the USART is disabled (UE=’0’). Bit 9 PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity This bitfield can only be written when the USART is disabled (UE=’0’). Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever PE=’1’ in the USART_ISR register Bit 7 TXEIE/TXFNFIE: Transmit data register empty/TXFIFO not full interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever TXE/TXFNF =’1’ in the USART_ISR register Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever TC=’1’ in the USART_ISR register Bit 5 RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever ORE=’1’ or RXNE/RXFNE=’1’ in the USART_ISR register Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever IDLE=’1’ in the USART_ISR register 2004/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 3 TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to ‘1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. 0: USART not able to wake up the MCU from low-power mode. 1: USART able to wake up the MCU from low-power mode. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 0 UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. 0: USART prescaler and outputs disabled, low-power mode 1: USART enabled Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = ’0’ so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = ’1’), the SCLK is always available when CLKEN = ’1’, regardless of the UE bit value. DocID029587 Rev 3 2005/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.7.2 RM0433 USART control register 2 (USART_CR2) Address offset: 0x04 Reset value: 0x0000 31 30 29 28 27 ADD[7:4] 26 25 24 ADD[3:0] 23 RTOEN 22 21 ABRMOD[1:0] 20 19 18 17 MSBFI DATAINV TXINV ABREN RST 16 RXINV rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWAP LINEN CLKEN CPOL CPHA LBCL Res LBDIE LBDL ADDM7 DIS_ NSS. Res. Res. SLVEN. rw rw rw rw rw rw rw rw rw rw rw STOP[1:0] rw rw rw Bits 31:28 ADD[7:4]: Address of the USART node This bitfield gives the address of the USART node or a character code to be recognized. It is used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. It can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bitfield can only be written when reception is disabled (RE = ’0’) or the USART is disabled (UE=’0’) Bits 27:24 ADD[3:0]: Address of the USART node This bitfield gives the address of the USART node or a character code to be recognized. This is used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. This bitfield can only be written when reception is disabled (RE = ’0’) or the USART is disabled (UE=’0’) Bit 23 RTOEN: Receiver timeout enable This bit is set and cleared by software. 0: Receiver timeout feature disabled. 1: Receiver timeout feature enabled. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bits 22:21 ABRMOD[1:0]: Auto baud rate mode These bits are set and cleared by software. 00: Measurement of the start bit is used to detect the baud rate. 01: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) 10: 0x7F frame detection. 11: 0x55 frame detection This bitfield can only be written when ABREN = ’0’ or the USART is disabled (UE=’0’). Note: If DATAINV=’1’ and/or MSBFIRST=’1’ the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. 2006/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 20 ABREN: Auto baud rate enable This bit is set and cleared by software. 0: Auto baud rate detection is disabled. 1: Auto baud rate detection is enabled. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 19 MSBFIRST: Most significant bit first This bit is set and cleared by software. 0: data is transmitted/received with data bit 0 first, following the start bit. 1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bitfield can only be written when the USART is disabled (UE=’0’). Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bitfield can only be written when the USART is disabled (UE=’0’). Bit 17 TXINV: TX pin active level inversion This bit is set and cleared by software. 0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=’0’). Bit 16 RXINV: RX pin active level inversion This bit is set and cleared by software. 0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=’0’). Bit 15 SWAP: Swap TX/RX pins This bit is set and cleared by software. 0: TX/RX pins are used as defined in standard pinout 1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bitfield can only be written when the USART is disabled (UE=’0’). Bit 14 LINEN: LIN mode enable This bit is set and cleared by software. 0: LIN mode disabled 1: LIN mode enabled The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=’0’). Note: If the USART does not support LIN mode, this bit is reserved and forced by hardware to ‘0’.Please refer to Section 48.4: USART implementation on page 1953. DocID029587 Rev 3 2007/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bits 13:12 STOP[1:0]: stop bits These bits are used for programming the stop bits. 00: 1 stop bit 01: 0.5 stop bit. 10: 2 stop bits 11: 1.5 stop bits This bitfield can only be written when the USART is disabled (UE=’0’). Bit 11 CLKEN: Clock enable This bit allows the user to enable the SCLK pin. 0: SCLK pin disabled 1: SCLK pin enabled This bit can only be written when the USART is disabled (UE=’0’). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: - UE = ’0’ - SCEN = ’1’ - GTPR configuration - CLKEN= ’1’ - UE = ’1’ Bit 10 CPOL: Clock polarity This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship 0: Steady low value on SCLK pin outside transmission window 1: Steady high value on SCLK pin outside transmission window This bit can only be written when the USART is disabled (UE=’0’). Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 9 CPHA: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 567 and Figure 568) 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge This bit can only be written when the USART is disabled (UE=’0’). Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 8 LBCL: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=’0’). Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 7 Reserved, must be kept at reset value. 2008/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 6 LBDIE: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). 0: Interrupt is inhibited 1: An interrupt is generated whenever LBDF=’1’ in the USART_ISR register Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 5 LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection This bit can only be written when the USART is disabled (UE=’0’). Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. 0: 4-bit address detection 1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=’0’) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. Bit 3 DIS_NSS When the DSI_NSS bit is set, the NSS pin input is ignored. 0: SPI slave selection depends on NSS input pin. 1: SPI slave is always selected and NSS input pin is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Please refer to Section 48.4: USART implementation on page 1953. Bits 2:1 Reserved, must be kept at reset value Bit 0 SLVEN: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. 0: Slave mode disabled. 1: Slave mode enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Please refer to Section 48.4: USART implementation on page 1953. Note: The CPOL, CPHA and LBCL bits should not be written while the transmitter is enabled. 48.7.3 USART control register 3 (USART_CR3) Address offset: 0x08 Reset value: 0x0000 31 30 29 TXFTCFG rw 15 14 28 27 RXF TIE. 26 25 24 TCBG TIE RXFTCFG rw rw TXFTIE WUFIE Res. rw rw rw rw rw 5 4 3 2 1 0 SCEN NACK HD SEL IRLP IREN EIE rw rw rw rw rw rw DMAT DMAR rw rw rw rw rw rw rw SCARCNT2:0] 16 6 RTSE rw 17 rw CTSE rw WUS[2:0] 18 7 CTSIE rw 19 rw ONE BIT DDRE 20 8 11 DEM 21 rw 12 DEP 9 22 13 OVR DIS 10 23 DocID029587 Rev 3 2009/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bits 31:29 TXFTCFG: TXFIFO threshold configuration 000:TXFIFO reaches 1/8 of its depth 001:TXFIFO reaches 1/4 of its depth 010:TXFIFO reaches 1/2 of its depth 011:TXFIFO reaches 3/4 of its depth 100:TXFIFO reaches 7/8 of its depth 101:TXFIFO becomes empty Remaining combinations: Reserved Bit28 RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. Bits 27:25 RXFTCFG: Receive FIFO threshold configuration 000:Receive FIFO reaches 1/8 of its depth 001:Receive FIFO reaches 1/4 of its depth 010:Receive FIFO reaches 1/2 of its depth 011:Receive FIFO reaches 3/4 of its depth 100:Receive FIFO reaches 7/8 of its depth 101:Receive FIFO becomes full Remaining combinations: Reserved Bit 24 TCBGTIE: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever TCBGT=’1’ in the USART_ISR register Note: If the USART does not support the Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 23 TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. Bit 22 WUFIE: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. 0: Interrupt inhibited 1: USART interrupt generated whenever WUF=’1’ in the USART_ISR register Note: WUFIE must be set before entering in low-power mode. The WUF interrupt is active only in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. 2010/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bits 21:20 WUS[1:0]: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01: Reserved. 10: WUF active on start bit detection 11: WUF active on RXNE/RXFNE. This bitfield can only be written when the USART is disabled (UE=’0’). If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=’0’). When the USART is enabled (UE=’1’), this bitfield may only be written to 0x0, in order to stop retransmission. 0x0: retransmission disabled - No automatic retransmission in transmit mode. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 16 Reserved, must be kept at reset value. Bit 15 DEP: Driver enable polarity selection 0: DE signal is active high. 1: DE signal is active low. This bit can only be written when the USART is disabled (UE=’0’). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Please refer to Section 48.4: USART implementation on page 1953. Bit 14 DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. 0: DE function is disabled. 1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=’0’). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Section 48.4: USART implementation on page 1953. Bit 13 DDRE: DMA Disable on Reception Error 0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. (used for Smartcard mode) 1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = ’0’) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. This bit can only be written when the USART is disabled (UE=’0’). Note: The reception errors are: parity error, framing error or noise error. DocID029587 Rev 3 2011/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bit 12 : OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data will be written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=’0’). Note: This control bit allows checking the communication flow w/o reading the data Bit 11 ONEBIT: One sample bit method enable This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. 0: Three sample bit method 1: One sample bit method This bit can only be written when the USART is disabled (UE=’0’). Bit 10 CTSIE: CTS interrupt enable 0: Interrupt is inhibited 1: An interrupt is generated whenever CTSIF=’1’ in the USART_ISR register Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=’0’) Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 8 RTSE: RTS enable 0: RTS hardware flow control disabled 1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=’0’). Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 7 DMAT: DMA enable transmitter This bit is set/reset by software 1: DMA mode is enabled for transmission 0: DMA mode is disabled for transmission Bit 6 DMAR: DMA enable receiver This bit is set/reset by software 1: DMA mode is enabled for reception 0: DMA mode is disabled for reception 2012/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 5 SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. 0: Smartcard Mode disabled 1: Smartcard Mode enabled This bitfield can only be written when the USART is disabled (UE=’0’). Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 4 NACK: Smartcard NACK enable 0: NACK transmission in case of parity error is disabled 1: NACK transmission during parity error is enabled This bitfield can only be written when the USART is disabled (UE=’0’). Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 3 HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected 1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=’0’). Bit 2 IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes 0: Normal mode 1: Low-power mode This bit can only be written when the USART is disabled (UE=’0’). Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 1 IREN: IrDA mode enable This bit is set and cleared by software. 0: IrDA disabled 1: IrDA enabled This bit can only be written when the USART is disabled (UE=’0’). Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=’1’ or ORE=’1’ or NE=’1’or UDR = ’1’ in the USART_ISR register). 0: Interrupt inhibited 1: interrupt generated when FE=’1’ or ORE=’1’ or NE=’1’ or UDR = ’1’ (in SPI slave mode) in the USART_ISR register. DocID029587 Rev 3 2013/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.7.4 RM0433 USART baud rate register (USART_BRR) This register can only be written when the USART is disabled (UE=’0’). It may be automatically updated by hardware in auto baud rate detection mode. Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BRR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 BRR[15:4] BRR[15:4] = USARTDIV[15:4] Bits 3:0 BRR[3:0] When OVER8 = ’0’, BRR[3:0] = USARTDIV[3:0]. When OVER8 = ’1’: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 48.7.5 USART guard time and prescaler register (USART_GTPR) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2014/3178 GT[7:0] PSC[7:0] rw rw DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 GT[7:0]: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=’0’). Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bits 7:0 PSC[7:0]: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power Baud Rate Used for programming the prescaler for dividing the USART source clock to achieve the lowpower frequency: The source clock is divided by the value given in the register (8 significant bits): 00000000: Reserved - do not program this value 00000001: divides the source clock by 1 00000010: divides the source clock by 2 ... In Smartcard mode: PSC[4:0]: Prescaler value Used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: 00000: Reserved - do not program this value 00001: divides the source clock by 2 00010: divides the source clock by 4 00011: divides the source clock by 6 ... This bitfield can only be written when the USART is disabled (UE=’0’). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to ‘0’ when the Smartcard and IrDA modes are not supported. Please refer to Section 48.4: USART implementation on page 1953. 48.7.6 USART receiver timeout register (USART_RTOR) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 BLEN[7:0] 20 19 18 17 16 RTO[23:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RTO[15:0] rw DocID029587 Rev 3 2015/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bits 31:24 BLEN[7:0]: Block Length This bitfield gives the Block length in Smartcard T=’1’ Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 -> 0 information characters + LEC BLEN = 1 -> 0 information characters + CRC BLEN = 255 -> 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=’0’ (TXFE = ’0’ in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=’0’ (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. Bits 23:0 RTO[23:0]: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of baud clocks. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character. Note: RTOR can be written on-the-fly. If the new value is lower than or equal to the counter, the RTOF flag is set. This register is reserved and forced by hardware to “0x00000000” when the Receiver timeout feature is not supported. Please refer to Section 48.4: USART implementation on page 1953. 48.7.7 USART request register (USART_RQR) Address offset: 0x18 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFRQ RXFRQ MMRQ SBKRQ ABRRQ w_r0 2016/3178 DocID029587 Rev 3 w_r0 w_r0 w_r0 w_r0 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:5 Reserved, must be kept at reset value. Bit 4 TXFRQ: Transmit data flush request When FIFO mode is disabled, writing ‘1’ to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’ When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. Bit 3 RXFRQ: Receive data flush request Writing ’1’ to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This allows to discard the received data without reading them, and avoid an overrun condition. Bit 2 MMRQ: Mute mode request Writing ’1’ to this bit puts the USART in Mute mode and resets the RWU flag. Bit 1 SBKRQ: Send break request Writing ’1’ to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. Bit 0 ABRRQ: Auto baud rate request Writing ’1’ to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. 48.7.8 USART interrupt and status register (USART _ISR) Address offset: 0x1C Reset value: 0x0000 00C0 (if FIFO disabled). Reset value: 0x0280 00C0 (if FIFO/Smartcard mode enabled). Reset value: 0x0080 00C0 (if FIFO enabled and Smartcard mode disabled). 31 Res. 15 30 Res. 14 29 Res. 13 28 Res. 12 27 26 25 24 23 22 21 20 19 18 17 16 TE ACK WUF RWU SBKF CMF BUSY r r r r r r TXFT RXFT TCBGT RXFF TXFE RE ACK r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 TC RXNE/ RXFNE IDLE ORE NE FE PE r r r r r r r ABRF ABRE UDR EOBF RTOF CTS CTSIF LBDF TXE/TX FNF r r r r r r r r r DocID029587 Rev 3 2017/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bits 31:28 Reserved, must be kept at reset value. Bit 27 TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =’1’ (bit 31) in the USART_CR3 register. 0: TXFIFO does not reach the programmed threshold. 1: TXFIFO reached the programmed threshold. Bit 26 RXFT: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =’1’ (bit 27) in the USART_CR3 register. 0: Receive FIFO does not reach the programmed threshold. 1: Receive FIFO reached the programmed threshold. Note: When the RXFTCFG threshold is configured to ‘101’, RXFT flag will be set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data will not cause an overrun error. The overrun error occurs after receiving the 18th data. Bit 25 TCBGT: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=’1’ in the USART_CR3 register. This bit is cleared by software, by writing ’1’ to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. 0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) 1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). Note: If the USART does not support the Smartcard mode, this bit is reserved and forced by hardware to ‘0’. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is ‘1’. Please refer to Section 48.4: USART implementation on page 1953. Bit 24 RXFF: RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =’1’ in the USART_CR1 register. 0: RXFIFO not full. 1: RXFIFO Full. Bit 23 TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing ’1’ to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =’1’ (bit 30) in the USART_CR1 register. 0: TXFIFO not empty. 1: TXFIFO empty. 2018/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 21 TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=’0’, followed by TE=’1’ in the USART_CR1 register, in order to respect the TE=’0’ minimum period. Bit 20 WUF: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=’1’ in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. The WUF interrupt is active only in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 19 RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing ’1’ to the MMRQ bit in the USART_RQR register. 0: Receiver in active mode 1: Receiver in Mute mode Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 18 SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing ’1’ to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 0: No break character is transmitted 1: Break character will be transmitted Bit 17 CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing ’1’ to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=’1’in the USART_CR1 register. 0: No Character match detected 1: Character Match detected DocID029587 Rev 3 2019/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bit 16 BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 0: USART is idle (no reception) 1: Reception on going Bit 15 ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = ’1’) or when the auto baud rate operation was completed without success (ABRE=’1’) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing ’1’ to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Bit 14 ABRE: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing ’1’ to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Bit 13 UDR: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. 0: No underrun error 1: underrun error Note: If the USART does not support the SPI slave mode, this bit is reserved and forced by hardware to ‘0. Please refer to Section 48.4: USART implementation on page 1953. Bit 12 EOBF: End of block flag This bit is set by hardware when a complete block has been received (for example T=’1’ Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=’1’ in the USART_CR2 register. It is cleared by software, writing ’1’ to the EOBCF in the USART_ICR register. 0: End of Block not reached 1: End of Block (number of characters) reached Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. 2020/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 11 RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing ’1’ to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=’1’ in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. 0: Timeout value not reached 1: Timeout value reached without any data reception Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = ’0’ but RTOF is set only when RE = ’1’. If the timeout has already elapsed when RE is set, then RTOF will be set. If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Bit 10 CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. 0: nCTS line set 1: nCTS line reset Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 9 CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing ’1’ to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=’1’ in the USART_CR3 register. 0: No change occurred on the nCTS status line 1: A change occurred on the nCTS status line Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 8 LBDF: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing ’1’ to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = ’1’ in the USART_CR2 register. 0: LIN Break not detected 1: LIN break detected Note: If the USART does not support LIN mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. DocID029587 Rev 3 2021/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) RM0433 Bit 7 TXE/TXFNF: Transmit data register empty/TXFIFO not full When the FIFO mode is disabled, TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing ’1’ to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=’0’ mode, in case of transmission failure). When the FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXEIE/TXFNFIE bit =’1’ in the USART_CR1 register. 0: Data register is full/Transmit FIFO is full. 1: Data register/Transmit FIFO is not full. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE will be set at the same time). This bit is used during single buffer transmission. Bit 6 TC: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE/TXFE is set. An interrupt is generated if TCIE=’1’ in the USART_CR1 register. TC bit is is cleared by software, by writing ’1’ to the TCCF in the USART_ICR register or by a write to the USART_TDR register. 0: Transmission is not complete 1: Transmission is complete Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately. Bit 5 RXNE/RXFNE: Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing ’1’ to the RXFRQ in the USART_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXNE/RXFNE is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing ’1’ to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=’1’ in the USART_CR1 register. 0: Data is not received 1: Received data is ready to be read. Bit 4 IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=’1’ in the USART_CR1 register. It is cleared by software, writing ’1’ to the IDLECF in the USART_ICR register. 0: No Idle line is detected 1: Idle line is detected Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=’1’), IDLE is set if the USART is not mute (RWU=’0’), whatever the Mute mode selected by the WAKE bit. If RWU=’1’, IDLE is not set. 2022/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 3 ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE=’1’ (RXFF = ’1’ in case FIFO mode is enabled). It is cleared by a software, writing ’1’ to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=’1’ or EIE = ’1’ in the USART_CR1 register. 0: No overrun error 1: Overrun error is detected Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. Bit 2 NE: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing ’1’ to the NFCF bit in the USART_ICR register. 0: No noise is detected 1: Noise is detected Note: This bit does not generate an interrupt as it appears at the same time as the RXNE/RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 48.5.8: Tolerance of the USART receiver to clock deviation on page 1970). In FIFO mode, this error is associated with the character in the USART_RDR. Bit 1 FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing ’1’ to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. 0: No Framing error is detected 1: Framing error or break character is detected Note: In FIFO mode, this error is associated with the character in the USART_RDR. Bit 0 PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing ’1’ to the PECF in the USART_ICR register. An interrupt is generated if PEIE = ’1’ in the USART_CR1 register. 0: No parity error 1: Parity error Note: In FIFO mode, this error is associated with the character in the USART_RDR. DocID029587 Rev 3 2023/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.7.9 RM0433 USART interrupt flag clear register (USART_ICR) Address offset: 0x20 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res. 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 Res. Res. TCBGT CF TCCF NECF FECF PECF w w w w w w UDRCF EOBCF RTOCF w w Res. CTSCF LBDCF w w w 4 w TXFEC IDLECF ORECF F w w w Bits 31:21 Reserved, must be kept at reset value. Bit 20 WUCF: Wakeup from low-power mode clear flag Writing ’1’ to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bits 19:18 Reserved, must be kept at reset value. Bit 17 CMCF: Character match clear flag Writing ’1’ to this bit clears the CMF flag in the USART_ISR register. Bits 16:14 Reserved, must be kept at reset value. Bit 13 UDRCF:SPI slave underrun clear flag Writing ’1’ to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953 Bit 12 EOBCF: End of block clear flag Writing ’1’ to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 11 RTOCF: Receiver timeout clear flag Writing ’1’ to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 10 Reserved, must be kept at reset value. Bit 9 CTSCF: CTS clear flag Writing ’1’ to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. Bit 8 LBDCF: LIN break detection clear flag Writing ’1’ to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation on page 1953. 2024/3178 DocID029587 Rev 3 RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bit 7 TCBGTCF: Transmission complete before Guard time clear flag Writing ’1’ to this bit clears the TCBGT flag in the USART_ISR register. Bit 6 TCCF: Transmission complete clear flag Writing ’1’ to this bit clears the TC flag in the USART_ISR register. Bit 5 TXFECF: TXFIFO empty clear flag Writing ’1’ to this bit clears the TXFE flag in the USART_ISR register. Bit 4 IDLECF: Idle line detected clear flag Writing ’1’ to this bit clears the IDLE flag in the USART_ISR register. Bit 3 ORECF: Overrun error clear flag Writing ’1’ to this bit clears the ORE flag in the USART_ISR register. Bit 2 NECF: Noise detected clear flag Writing ’1’ to this bit clears the NE flag in the USART_ISR register. Bit 1 FECF: Framing error clear flag Writing ’1’ to this bit clears the FE flag in the USART_ISR register. Bit 0 PECF: Parity error clear flag Writing ’1’ to this bit clears the PE flag in the USART_ISR register. 48.7.10 USART receive data register (USART_RDR) Address offset: 0x24 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 r r r r 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. RDR[8:0] r r r r r Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 561). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. DocID029587 Rev 3 2025/3178 2074 Universal synchronous asynchronous receiver transmitter (USART) 48.7.11 RM0433 USART transmit data register (USART_TDR) Address offset: 0x28 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw rw rw rw TDR[8:0] rw Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 561). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=’1’. 48.7.12 USART prescaler register (USART_PRESC) This register can only be written when the USART is disabled (UE=’0’). Address offset: 0x2C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRESCALER[3:0] rw 2026/3178 DocID029587 Rev 3 rw rw rw RM0433 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 PRESCALER[3:0]: Clock prescaler The USART input clock can be divided by a prescaler factor: 0000: input clock not divided 0001: input clock divided by 2 0010: input clock divided by 4 0011: input clock divided by 6 0100: input clock divided by 8 0101: input clock divided by 10 0110: input clock divided by 12 0111: input clock divided by 16 1000: input clock divided by 32 1001: input clock divided by 64 1010: input clock divided by 128 1011: input clock divided by 256 Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be ‘1011’ i.e. input clock divided by 256. DocID029587 Rev 3 2027/3178 2074 0x28 USART_TDR 2028/3178 Reset value DocID029587 Rev 3 CTS CTSIF LBDF TXE TC RXNE IDLE ORE NE FE PE 0 0 0 0 1 0 0 0 0 0 0 0 Res. CTSCF LBDCF TCBGTCF TCCF TXFECF IDLECF 0 0 0 0 0 0 SCAR [1:0] CNT2:0] DEM DDRE OVRDIS ONEBIT CTSIE CTSE 0 0 0 0 0 0 0 BRR[15:0] 0 0 0 0 0 Reset value 0 EIE 0 DEP DEDT1 DEDT0 OVER8 CMIE MME M WAKE PCE PS PEIE TXEIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UE 0 0 0 0 0 0 SLVEN 0 UESM 0 0 Res. 0 RE 0 0 Res. DIS_NSS DEDT2 0 TE ADDM7 DEDT3 0 IDLEIE LBDL DEDT4 0 RXNEIE LBDIE DEAT0 0 TCIE LBCL Res. DEAT1 0 GT[7:0] 0 0 0 0 0 0 USART_RQR Reset value 0 0 0 0 ABRRQ 0 Res. DEAT2 0 RDR[8:0] 0 TDR[8:0] 0 PECF 0 IREN 0 IRLP CPOL CPHA 0 HDSEL CLKEN 0 NACK LINEN 0 SCEN SWAP 0 DMAR RXINV 0 RTSE TXINV 0 DMAT DATAINV DEAT3 0 SBKRQ 0 Res. Res. MSBFIRST DEAT4 0 FECF 0 Res. Res. ABREN RTOIE 0 MMRQ 0 Res. Res. ABRMOD0 EOBIE 0 NECF 0 Res. Res. ABRMOD1 M1 0 RXFRQ 0 Res. Res. FIFOEN 0 ORECF 0 Res. Res. RTOEN RXFFIE TXFEIE 0 TXFRQ 0 Res. 0 0 Res. 0 Res. BLEN[7:0] 0 0 Res. RTOCF 0 0 Res. RTOF 0 0 0 Res. EOBF 0 EOBCF 0 Res. 0 Res. Res. STOP [1:0] Res. 0 Res. Reset value 0 Res. UDR 0 UDRCF 0 Res. Reset value Res. 0 Res. USART_BRR Res. 0 Res. 0 Res. ABRE 0 Res. 0 Res. Res. 0 Res. ABRF 0 Res. 0 Res. Res. 0 Res. BUSY 0 Res. 0 Res. Res. 0 Res. CMF 0 CMCF 0 Res. Res. WUFIE 0 Res. SBKF 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. RWU 0 Res. 0 Res. TXFTIE 0 Res. 0 Res. WUF 0 WUCF 0 Res. Res. TCBGTIE 0 Res. 0 Res. TEACK 0 Res. 0 Res. Res. 0 Res. 0 Res. REACK 0 Res. 0 Res. Res. 0 RXFTIE 0 Res. Res. Res. Res. Res. TXFE 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. RXFF 0 Res. 0 Res. Res. 0 RXFT CFG Res. TCBGT X Res. 0 Res. Res. ADD[3:0] Res. RXFT 0 Res. 0 Res. 0 Res. Res. Res. 0 TXFT Res. 0 Res. 0 Res. USART_RDR 0 Res. 0x24 ADD[7:4] Res. Reset value 0 Res. Reset value Res. USART_ICR Res. 0 TXFT CFG 0 Res. 0x20 0 Res. USART_ISR 0 Res. 0x1C 0 0 Res. 0 Res. USART_RTOR Res. USART_GTPR Res. Reset value Res. 0x08 WUS Res. USART_CR3 Res. 0x10 0 Res. 0x0C Res. USART_CR2 Res. 0 Res. 0x18 Reset value Res. 0x04 Res. Reset value Res. Reset value Res. USART_CR1 Res. 0x00 Res. 0x14 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Register name Res. Offset Res. 48.7.13 Res. Universal synchronous asynchronous receiver transmitter (USART) RM0433 USART register map The table below gives the USART register map and reset values. Table 382. USART register map and reset values 0 PSC[7:0] 0 0 0 0 0 0 0 0 0 0 RTO[23:0] 0 0 0 0 0 RM0433 Universal synchronous asynchronous receiver transmitter (USART) 0 1 PRESCALE R[3:0] 0 Reset value 2 3 5 6 7 8 9 4 Res. Res. Res. Res. Res. Res. 11 12 10 Res. Res. Res. 13 Res. 14 Res. 16 17 18 19 20 21 22 15 Res. Res. Res. Res. Res. Res. Res. Res. 23 Res. 24 Res. 25 Res. 26 Res. 28 29 30 27 Res. Res. Res. USART_ PRESC Res. 0x2C Register name Res. Offset 31 Table 382. USART register map and reset values (continued) 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 2029/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) 49 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) This section describes the low-power universal asynchronous receiver transmitted (LPUART). 49.1 LPUART introduction The LPUART is an UART which allows bidirectional UART communications with a limited power consumption. Only 32.768 kHz LSE clock is required to allow UART communications up to 9600 baud/s. Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock. Even when the microcontroller is in low-power mode, the LPUART can wait for an incoming UART frame while having an extremely low energy consumption. The LPUART includes all necessary hardware support to make asynchronous serial communications possible with minimum power consumption. It supports Half-duplex Single-wire communications and modem operations (CTS/RTS). It also supports multiprocessor communications. DMA (direct memory access) can be used for data transmission/reception. 2030/3178 DocID029587 Rev 3 RM0433 49.2 Low-power universal asynchronous receiver transmitter (LPUART) LPUART main features • Full-duplex asynchronous communications • NRZ standard format (mark/space) • Programmable baud rate • From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source. • Higher baud rates can be achieved by using a higher frequency clock source • Two internal FIFOs to transmit and receive data Each FIFO can be enabled/disabled by software and come with status flags for FIFOs states. • Dual clock domain with dedicated kernel clock for peripherals independent from PCLK. • Programmable data word length (7 or 8 or 9 bits) • Programmable data order with MSB-first or LSB-first shifting • Configurable stop bits (1 or 2 stop bits) • Single-wire Half-duplex communications • Continuous communications using DMA • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA. • Separate enable bits for transmitter and receiver • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Transfer detection flags: • • – Receive buffer full – Transmit buffer empty – Busy and end of transmission flags Parity control: – Transmits parity bit – Checks parity of received data byte Four error detection flags: – Overrun error – Noise detection – Frame error – Parity error • Interrupt sources with flags • Multiprocessor communications: wakeup from Mute mode by idle line detection or address mark detection DocID029587 Rev 3 2031/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) 49.3 LPUART functional description 49.3.1 LPUART block diagram RM0433 Figure 588. LPUART block diagram /38$57 OSXDUWBNHUBFN FORFNGRPDLQ OSXDUWBZNXS OSXDUWBLW OSXDUWBW[BGPD OSXDUWBU[BGPD ,54,QWHUIDFH OSXDUWBSFON FORFNGRPDLQ '0$,QWHUIDFH OSXDUWBSFON OSXDUWBNHUBFN &. +DUGZDUH IORZFRQWURO 7[),)2 /38$57B&5 /38$57B545 /38$57B,&5 /38$57B7'5 /38$57B5'5 /38$57B 5725 /38$57B *735 /38$57B%55 /38$57B 35(6& 5[),)2 ELW$3%EXV &20&RQWUROOHU /38$57B&5 /38$57B,65 /38$57B&5 &76166 576'( 7;6KLIW5HJ 7; 5;6KLIW5HJ 5; %DXGUDWH JHQHUDWRU RUYHUVDPSOLQJ OSXDUWBNHUBFNBSUHV 06Y9 The simplified block diagram given in Figure 588 shows two fully independent clock domains: • The lpuart_pclk clock domain The lpuart_pclk clock signal feeds the peripheral bus interface. It must be active when accesses to the LPUART registers are required. • The lpuart_ker_ck kernel clock domain The lpuart_ker_ck is the LPUART clock source. It is independent of the lpuart_pclk and delivered by the RCC. So, the LPUART registers can be written/read even when the lpuart_ker_ck is stopped. When the dual clock domain feature is disabled, the lpuart_ker_ck is the same as the lpuart_pclk clock. There is no constraint between lpuart_pclk and lpuart_ker_ck: lpuart_ker_ck can be faster or slower than lpuart_pclk, with no more limitation than the ability for the software to manage the communication fast enough. 2032/3178 DocID029587 Rev 3 RM0433 49.3.2 Low-power universal asynchronous receiver transmitter (LPUART) LPUART signals LPUART bidirectional communications requires a minimum of two pins: Receive Data In (RX) and Transmit Data Out (TX): • RX (Receive Data Input) RX is the serial data input. • TX (Transmit Data Output) When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high level. In Single-wire mode, this I/O is used to transmit and receive the data. RS232 hardware flow control mode The following pins are required in RS232 Hardware flow control mode: • CTS (Clear To Send) When driven high, this signal blocks the data transmission at the end of the current transfer. • RTS (Request to send) When it is low, this signal indicates that the USART is ready to receive data. RS485 hardware flow control mode The following pin is required in RS485 Hardware control mode: • DE (Driver Enable) This signal activates the transmission mode of the external transceiver. Note: DE and RTS share the same pin. 49.3.3 LPUART character description The word length can be set to 7 or 8 or 9 bits, by programming the M bits (M0: bit 12 and M1: bit 28) in the LPUART_CR1 register (see Figure 562). • 7-bit character length: M[1:0] = ‘10’ • 8-bit character length: M[1:0] = ‘00’ • 9-bit character length: M[1:0] = ‘01’ By default, the signal (TX or RX) is in low state during the start bit. It is in high state during the stop bit. These values can be inverted, separately for each signal, through polarity configuration control. An Idle character is interpreted as an entire frame of “1”s. (The number of “1” ‘s will include the number of stop bits). A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame, the transmitter inserts 2 stop bits. Transmission and reception are driven by a common baud rate generator. The transmission and reception clocks are generated when the enable bit is set for the transmitter and receiver, respectively. The details of each block is given below. DocID029587 Rev 3 2033/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Figure 589. LPUART word length programming ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN 6WDUW ELW ,GOHIUDPH 6WRS ELW 6WRS ELW 6WRS ELW 6WRS ELW 6WDUW ELW 6WRS ELW 6WDUW ELW %UHDNIUDPH 6WDUW ELW ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN 6WDUW ELW ,GOHIUDPH %UHDNIUDPH ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN ,GOHIUDPH %UHDNIUDPH 6WDUW ELW 6WRS ELW /%&/ELWFRQWUROVODVWGDWDFORFNSXOVH 06 9 2034/3178 DocID029587 Rev 3 RM0433 49.3.4 Low-power universal asynchronous receiver transmitter (LPUART) LPUART FIFOs and thresholds The LPUART can operate in FIFO mode. The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The FIFO mode is enabled by setting FIFOEN bit (bit 29) in LPUART_CR1 register. Since 9 bits the maximum data word length is 9 bits, the TXFIFO is 9-bits wide. However the RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store the data in the FIFO, but also the error flags associated to each character (Parity error, Noise error and Framing error flags). Note: The received data is stored in the RXFIFO together with the corresponding flags. However, only the data are read when reading the RDR. The status flags are available in the LPUART_ISR register. It is possible to define the TXFIFO and RXFIFO levels at which the Tx and RX interrupts are triggered. These thresholds are programmed through RXFTCFG and TXFTCFG bitfields in LPUART_CR3 control register. In this case: • The Rx interrupt is generated when the number of received data in the RXFIFO reaches the threshold programmed in the RXFTCFG bitfields. In this case, the RXFT flag is set in the LPUART_ISR register. This means that RXFTCFG data have been received: 1 data in LPUART_RDR and (RXFTCFG - 1) data in the RXFIFO. As an example, when the RXFTCFG is programmed to ‘101’, the RXFT flag will be set when a number of data corresponding to the FIFO size has been received: FIFO size - 1 data in the RXFIFO and 1 data in the LPUART_RDR. As a result, the next received data will not set the overrun flag. • 49.3.5 The Tx interrupt is generated when the number of empty locations in the TXFIFO reaches the threshold programmed in the TXFTCFG bitfields. LPUART transmitter The transmitter can send data words of either 7 or 8 or 9 bits, depending on the M bit status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin. Character transmission During an LPUART transmission, data shifts out least significant bit first (default configuration) on the TX pin. In this mode, the LPUART_TDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 588). When FIFO mode is enabled, the data written to the LPUART_TDR register are queued in the TXFIFO. Every character is preceded by a start bit which corresponds to a low logic level for one bit period. The character is terminated by a configurable number of stop bits. The number of stop bits can be 1 or 2. DocID029587 Rev 3 2035/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) Note: RM0433 The TE bit must be set before writing the data to be transmitted to the LPUART_TDR. The TE bit should not be reset during data transmission. Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters is frozen. The current data being transmitted are lost. An idle frame will be sent after the TE bit is enabled. Configurable stop bits The number of stop bits to be transmitted with every character can be programmed in LPUART_CR2 (bits 13,12). • 1 stop bit: This is the default value of number of stop bits. • 2 Stop bits: This will be supported by normal LPUART, Single-wire and Modem modes. An idle frame transmission will include the stop bits. A break transmission will be 10 low bits (when M[1:0] = ‘00’) or 11 low bits (when M[1:0] = ‘01’) or 9 low bits (when M[1:0] = ‘10’) followed by 2 stop bits. It is not possible to transmit long breaks (break of length greater than 9/10/11 low bits). Figure 590. Configurable stop bits ELW:RUGOHQJWK 0> @ ELWLVUHVHW D 6WRSELW 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 1H[WGDWDIUDPH VWDUW ELW &/2&. /%&/ELWFRQWUROVODVWGDWDFORFNSXOVH E 6WRSELWV 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELWV 1H[W VWDUW ELW 1H[WGDWDIUDPH 069 Character transmission procedure To transmit a character, follow the sequence below: 2036/3178 1. Program the M bits in LPUART_CR1 to define the word length. 2. Select the desired baud rate using the LPUART_BRR register. 3. Program the number of stop bits in LPUART_CR2. 4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to ‘1’. 5. Select DMA enable (DMAT) in LPUART_CR3 if Multi buffer Communication is to take place. Configure the DMA register as explained in Section 48.5.10: USART multiprocessor communication. 6. Set the TE bit in LPUART_CR1 to send an idle frame as first transmission. 7. Write the data to send in the LPUART_TDR register. Repeat this operation for each data to be transmitted in case of single buffer. DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) – When FIFO mode is disabled, writing a data in the LPUART_TDR clears the TXE flag. – When FIFO mode is enabled, writing a data in the LPUART_TDR adds one data to the TXFIFO. Write operations to the LPUART_TDR are performed when TXFNF flag is set. This flag remains set until the TXFIFO is full. 8. When the last data is written to the LPUART_TDR register, wait until TC=’1’. This indicates that the transmission of the last frame is complete. – When FIFO mode is disabled, this indicates that the transmission of the last frame is complete. – When FIFO mode is enabled, this indicates that both TXFIFO and shift register are empty. This check is required to avoid corrupting the last transmission when the LPUART is disabled or enters Halt mode. Single byte communication • When FIFO mode disabled: Writing to the transmit data register always clears the TXE bit. The TXE flag is set by hardware to indicate that: – the data have been moved from the LPUART_TDR register to the shift register and data transmission has started; – the LPUART_TDR register is empty; – the next data can be written to the LPUART_TDR register without overwriting the previous data. The TXE flag generates an interrupt if the TXEIE bit is set. When a transmission is ongoing, a write instruction to the LPUART_TDR register stores the data in the TDR register, which is copied to the shift register at the end of the current transmission. When no transmission is ongoing, a write instruction to the LPUART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set. • When FIFO mode is enabled, the TXFNF (TXFIFO Not Full) flag is set by hardware to indicate that: – the TXFIFO is not full; – the LPUART_TDR register is empty; – the next data can be written to the LPUART_TDR register without overwriting the previous data. When a transmission is ongoing, a write operation to the DocID029587 Rev 3 2037/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 LPUART_TDR register stores the data in the TXFIFO. Data are copied from the TXFIFO to the shift register at the end of the current transmission. When the TXFIFO is not full, the TXFNF flag stays at ‘1’ even after a write in LPUART_TDR. It is cleared when the TXFIFO is full. This flag generates an interrupt if TXFNEIE bit is set. Alternatively, interrupts can be generated and data can be written to the TXFIFO when the TXFIFO threshold is reached. In this case, the CPU can write a block of data defined by the programmed threshold. If a frame is transmitted (after the stop bit) and the TXE flag (TXFE is case of FIFO mode) is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the LPUART_CR1 register. After writing the last data in the LPUART_TDR register, it is mandatory to wait for TC=’1’ before disabling the LPUART or causing the microcontroller to enter the lowpower mode (see Figure 591: TC/TXE behavior when transmitting). Figure 591. TC/TXE behavior when transmitting )UDPH )UDPH ,GOHSUHDPEOH )UDPH 7;OLQH 7;(IODJ /38$57B'5 6HWE\KDUGZDUH FOHDUHGE\VRIWZDUH 6HWE\KDUGZDUH FOHDUHGE\VRIWZDUH ) ) ) 6HWE\KDUGZDUH 6HWE\KDUGZDUH 7&IODJ 6RIWZDUH HQDEOHVWKH /38$57 6RIWZDUHZDLWVXQWLO7;( DQGZULWHV)LQWR'5 6RIWZDUHZDLWVXQWLO7;( DQGZULWHV)LQWR'5 7&LVQRWVHW EHFDXVH7;( 6RIWZDUHZDLWVXQWLO 7;( DQGZULWHV )LQWR'5 7&LVQRWVHW EHFDXVH7;( 7&LVVHW EHFDXVH7;( 6RIWZDUHZDLWVXQWLO7& 06Y 9 Note: When FIFO management is enabled, the TXFNF flag is used for data transmission. Break characters Setting the SBKRQ bit transmits a break character. The break frame length depends on the M bits (see Figure 589). If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing the current character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the break character is completed (during the stop bits after the break character). The LPUART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame. When the SBKRQ bit is set, the break character is sent at the end of the current transmission. 2038/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) When FIFO mode is enabled, sending the break character has priority on sending data even if the TXFIFO is full. Idle characters Setting the TE bit drives the LPUART to send an idle frame before the first data frame. 49.3.6 LPUART receiver The LPUART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the LPUART_CR1 register. Start bit detection In the LPUART, the start bit is detected when a falling edge occurs on the Rx line, followed by a sample taken in the middle of the start bit to confirm that it is still ‘0’. If the start sample is at ‘1’, then the noise error flag (NE) is set, then the start bit is discarded and the receiver waits for a new start bit. Else, the receiver continues to sample all incoming bits normally. Character reception During an LPUART reception, data are shifted in least significant bit first (default configuration) through the RX pin. In this mode, the LPUART_RDR register consists of a buffer (RDR) between the internal bus and the received shift register. Character reception procedure To receive a character, follow the sequence below: 1. Program the M bits in LPUART_CR1 to define the word length. 2. Select the desired baud rate using the baud rate register LPUART_BRR 3. Program the number of stop bits in LPUART_CR2. 4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to ‘1’. 5. Select DMA enable (DMAR) in LPUART_CR3 if multibuffer communication is to take place. Configure the DMA register as explained in Section 48.5.10: USART multiprocessor communication. 6. Set the RE bit LPUART_CR1. This enables the receiver which begins searching for a start bit. When a character is received • When FIFO mode is disabled, the RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags). • When FIFO mode is enabled, the RXFNE bit is set indicating that the RXFIFO is not empty. Reading the LPUART_RDR returns the oldest data entered in the RXFIFO. DocID029587 Rev 3 2039/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 When a data is received, it is stored in the RXFIFO, together with the corresponding error bits. • An interrupt is generated if the RXNEIE (RXFNEIE in case of FIFO mode) bit is set. • The error flags can be set if a frame error, noise or an overrun error has been detected during reception. • In multibuffer communication mode: • – When FIFO mode is disabled, the RXNE flag is set after every byte received and is cleared by the DMA read of the Receive Data Register. – When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not empty. After every DMA request, a data is retrieved from the RXFIFO. DMA request is triggered by RXFIFO is not empty i.e. there is a data in the RXFIFO to be read. In single buffer mode: – When FIFO mode is disabled, clearing the RXNE flag is done by performing a software read from the LPUART_RDR register. The RXNE flag can also be cleared by writing ’1’ to the RXFRQ in the LPUART_RQR register. The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error. – When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not empty. After every read operation from the LPUART_RDR register, a data is retrieved from the RXFIFO. When the RXFIFO is empty, the RXFNE flag is cleared. The RXFNE flag can also be cleared by writing ’1’ to the RXFRQ bit in the LPUART_RQR register. When the RXFIFO is full, the first entry in the RXFIFO must be read before the end of the reception of the next character to avoid an overrun error. The RXFNE flag generates an interrupt if the RXFNEIE bit is set. Alternatively, interrupts can be generated and data can be read from RXFIFO when the RXFIFO threshold is reached. In this case, the CPU can read a block of data defined by the programmed threshold. Break character When a break character is received, the USART handles it as a framing error. Idle character When an idle frame is detected, it is handled in the same way as a data character reception except that an interrupt is generated if the IDLEIE bit is set. 2040/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Overrun error • FIFO mode disabled An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: • – the ORE bit is set; – the RDR content will not be lost. The previous data is available when a read to LPUART_RDR is performed.; – the shift register will be overwritten. After that, any data received during overrun is lost. – an interrupt is generated if either the RXNEIE bit or EIE bit is set. FIFO mode enabled An overrun error occurs when the shift register is ready to be transferred when the receive FIFO is full. Data can not be transferred from the shift register to the LPUART_RDR register until there is one free location in the RXFIFO. The RXFNE flag is set when the RXFIFO is not empty. An overrun error occurs if the RXFIFO is full and the shift register is ready to be transferred. When an overrun error occurs: – the ORE bit is set; – the first entry in the RXFIFO will not be lost. It is available when a read to LPUART_RDR is performed. – the shift register will be overwritten. After that, any data received during overrun is lost. – an interrupt is generated if either the RXFNEIE bit or EIE bit is set. The ORE bit is reset by setting the ORECF bit in the ICR register. Note: The ORE bit, when set, indicates that at least 1 data has been lost. T When the FIFO mode is disabled, there are two possibilities • if RXNE=’1’, then the last valid data is stored in the receive register (RDR) and can be read, • if RXNE=’0’, then the last valid data has already been read and there is nothing left to be read in the RDR. This case can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received. Selecting the clock source The choice of the clock source is done through the Clock Control system (see Section Reset and clock controller (RCC)). The clock source must be selected through the UE bit, before enabling the LPUART. The clock source must be selected according to two criteria: • Possible use of the LPUART in low-power mode • Communication speed. The clock source frequency is lpuart_ker_ck. DocID029587 Rev 3 2041/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 When the dual clock domain and the wakeup from low-power mode features are supported, the lpuart_ker_ck clock source can be configured in the RCC (see Section Reset and clock controller (RCC)). Otherwise, the lpuart_ker_ck is the same as lpuart_pclk. The lpuart_ker_ck can be divided by a programmable factor in the LPUART_PRESC register. Figure 592. lpuart_ker_ck clock divider block diagram OSXDUWBNHUBFNBSUHV OSXDUWBNHUBFN /38$57[B35(6&> @ /38$57[B%55 UHJLVWHUDQG RYHUVDPSOLQJ 06Y 9 Some lpuart_ker_ck sources allow the LPUART to receive data while the MCU is in lowpower mode. Depending on the received data and wakeup mode selection, the LPUART wakes up the MCU, when needed, in order to transfer the received data by software reading the LPUART_RDR register or by DMA. For the other clock sources, the system must be active to allow LPUART communications. The communication speed range (specially the maximum communication speed) is also determined by the clock source. The receiver samples each incoming baud as close as possible to the middle of the baudperiod. Only a single sample is taken of each of the incoming bauds. Note: There is no noise detection for data. Framing error A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. When the framing error is detected: • the FE bit is set by hardware; • the invalid data is transferred from the Shift register to the LPUART_RDR register. • no interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer communication, an interrupt will be issued if the EIE bit is set in the LPUART_CR3 register. The FE bit is reset by writing ’1’ to the FECF in the LPUART_ICR register. 2042/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of LPUART_CR2: it can be either 1 or 2 in normal mode. 49.3.7 • 1 stop bit: sampling for 1 stop bit is done on the 8th, 9th and 10th samples. • 2 stop bits: sampling for the 2 stop bits is done in the middle of the second stop bit. The RXNE and FE flags are set just after this sample i.e. during the second stop bit. The first stop bit is not checked for framing error. LPUART baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the value programmed in the LPUART_BRR register. 256 × lpuart ckpres Tx/Rx baud = ----------------------------------------------------LPUARTDIV LPUARTDIV is defined in the LPUART_BRR register. Note: The baud counters are updated to the new value in the baud registers after a write operation to LPUART_BRR. Hence the baud rate register value should not be changed during communication. It is forbidden to write values lower than 0x300 in the LPUART_BRR register. fCK must range from 3 x baud rate to 4096 x baud rate. The maximum baud rate that can be reached when the LPUART clock source is the LSE, is 9600 baud. Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock. For example, if the LPUART clock source frequency is 100 MHz, the maximum baud rate that can be reached is about 33 Mbaud. Table 383. Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32,768 KHz lpuart_ker_ck_pres= 32,768 KHz Baud rate S.No Desired Actual Value programmed in the baud rate register % Error = (Calculated - Desired) B.rate / Desired B.rate 1 0.3 KBps 0.3 KBps 0x6D3A 0 2 0.6 KBps 0.6 KBps 0x369D 0 3 1200 Bps 1200.087 Bps 0x1B4E 0.007 4 2400 Bps 2400.17 Bps 0xDA7 0.007 5 4800 Bps 4801.72 Bps 0x6D3 0.035 6 9600 KBps 9608.94 Bps 0x369 0.093 DocID029587 Rev 3 2043/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Table 384. Error calculation for programmed baud rates at fCK = 100 MHz fCK = 100MHz Baud rate Value programmed in the baud % Error = (Calculated - Desired) rate register B.rate / Desired B.rate S.No Desired Actual 1 38400 Baud 38400,04 Baud A2C2A 0,0001 2 57600 Baud 57600,06 Baud 6C81C 0,0001 3 115200 Baud 115200,12 Baud 3640E 0,0001 4 230400 Baud 230400,23 Baud 1B207 0,0001 5 460800 Baud 460804,61 Baud D903 0,001 6 921600 Baud 921625,81 Baud 6C81 0,0028 7 4000 KBaud 4000000,00 Baud 1900 0 8 10000 Kbaud 10000000,00 Baud A00 0 9 20000 Kbaud 20000000,00 Baud 500 0 10 30000 Kbaud 33032258,06 Baud 307 0,1 49.3.8 Tolerance of the LPUART receiver to clock deviation The asynchronous receiver of the LPUART works correctly only if the total clock system deviation is less than the tolerance of the LPUART receiver. The causes which contribute to the total deviation are: • DTRA: deviation due to the transmitter error (which also includes the deviation of the transmitter’s local oscillator) • DQUANT: error due to the baud rate quantization of the receiver • DREC: deviation of the receiver local oscillator • DTCL: deviation due to the transmission line (generally due to the transceivers which can introduce an asymmetry between the low-to-high transition timing and the high-tolow transition timing) DTRA + DQUANT + DREC + DTCL + DWU < LPUART receiver tolerance where DWU is the error due to sampling point deviation when the wakeup from lowpower mode is used. The LPUART receiver can receive data correctly at up to the maximum tolerated deviation specified in Table 385: 2044/3178 • Number of Stop bits defined through STOP[1:0] bits in the LPUART_CR2 register • LPUART_BRR register value. DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Table 385. Tolerance of the LPUART receiver 1024 < BRR < 2048 2048 < BRR < 4096 4096 ≤ BRR M bits 768 < BRR < 1024 8 bits (M=’00’), 1 Stop bit 1.82% 2.56% 3.90% 4.42% 9 bits (M=’01’), 1 Stop bit 1.69% 2.33% 2.53% 4.14% 7 bits (M=’10’), 1 Stop bit 2.08% 2.86% 4.35% 4.42% 8 bits (M=’00’), 2 Stop bit 2.08% 2.86% 4.35% 4.42% 9 bits (M=’01’), 2 Stop bit 1.82% 2.56% 3.90% 4.42% 7 bits (M=’10’), 2 Stop bit 2.34% 3.23% 4.92% 4.42% Note: The data specified in Table 385 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit times when M bits = ‘00’ (11-bit times when M=’01’ or 9- bit times when M = ‘10’). 49.3.9 LPUART multiprocessor communication It is possible to perform LPUART multiprocessor communications (with several LPUARTs connected in a network). For instance one of the LPUARTs can be the master, with its TX output connected to the RX inputs of the other LPUARTs. The others are slaves, with their respective TX outputs are logically ANDed together and connected to the RX input of the master. In multiprocessor configurations it is often desirable that only the intended message recipient actively receives the full message contents, thus reducing redundant LPUART service overhead for all non addressed receivers. The non addressed devices can be placed in Mute mode by means of the muting function. To use the Mute mode feature, the MME bit must be set in the LPUART_CR1 register. Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared and then set again quickly (within two lpuart_ker_ck cycles), otherwise Mute mode might remain active. When the Mute mode is enabled: • none of the reception status bits can be set; • all the receive interrupts are inhibited; • the RWU bit in LPUART_ISR register is set to ‘1’. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the LPUART_RQR register, under certain conditions. The LPUART can enter or exit from Mute mode using one of two methods, depending on the WAKE bit in the LPUART_CR1 register: • Idle Line detection if the WAKE bit is reset, • Address Mark detection if the WAKE bit is set. Idle line detection (WAKE=’0’) The LPUART enters Mute mode when the MMRQ bit is written to 1 and the RWU is automatically set. DocID029587 Rev 3 2045/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 The LPUART wakes up when an Idle frame is detected. The RWU bit is then cleared by hardware but the IDLE bit is not set in the LPUART_ISR register. An example of Mute mode behavior using Idle line detection is given in Figure 593. Figure 593. Mute mode using Idle line detection 5;1( 'DWD 'DWD 'DWD 'DWD 5; ,'/( 0XWHPRGH 5:8 0054ZULWWHQWR 5;1( 'DWD 'DWD 1RUPDOPRGH ,GOHIUDPHGHWHFWHG 06Y9 Note: If the MMRQ is set while the IDLE character has already elapsed, Mute mode will not be entered (RWU is not set). If the LPUART is activated while the line is IDLE, the idle state is detected after the duration of one IDLE frame (not only after the reception of one character frame). 4-bit/7-bit address mark detection (WAKE=’1’) In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the LPUART_CR2 register. Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and ADD[7:0]) respectively. The LPUART enters Mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the LPUART enters Mute mode. The LPUART also enters Mute mode when the MMRQ bit is written to ‘1’. The RWU bit is also automatically set in this case. The LPUART exits from Mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE/RXFNE bit is set for the address character since the RWU bit has been cleared. Note: When FIFO management is enabled, when MMRQ bit is set while the receiver is sampling the last bit of a data, this data may be received before effectively entering in Mute mode. An example of Mute mode behavior using address mark detection is given in Figure 594. 2046/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Figure 594. Mute mode using address mark detection ,QWKLVH[DPSOHWKHFXUUHQWDGGUHVVRIWKHUHFHLYHULV SURJUDPPHGLQWKH/8$57B&5UHJLVWHU 5;1( ,'/( 5; $GGU 'DWD 'DWD 5:8 ,'/( 5;1( $GGU 'DWD 'DWD $GGU 'DWD 0XWHPRGH 1RUPDOPRGH 0DWFKLQJDGGUHVV 0054ZULWWHQWR 5;1(ZDVFOHDUHG 5;1( 0XWHPRGH 1RQPDWFKLQJDGGUHVV 1RQPDWFKLQJDGGUHVV 06Y9 49.3.10 LPUART parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the LPUART_CR1 register. Depending on the frame length defined by the M bits, the possible LPUART frame formats are as listed in Table 386. Table 386: LPUART frame formats M bits PCE bit LPUART frame(1) 00 0 | SB | 8 bit data | STB | 00 1 | SB | 7-bit data | PB | STB | 01 0 | SB | 9-bit data | STB | 01 1 | SB | 8-bit data PB | STB | 10 0 | SB | 7bit data | STB | 10 1 | SB | 6-bit data | PB | STB | 1. Legends: SB: start bit, STB: stop bit, PB: parity bit. 2. In the data register, the PB is always taking the MSB position (8th or 7th, depending on the M bit value). Even parity The parity bit is calculated to obtain an even number of “1s” inside the frame which is made of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit. As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even parity is selected (PS bit in LPUART_CR1 = ’0’). Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit. As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is selected (PS bit in LPUART_CR1 = ’1’). DocID029587 Rev 3 2047/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Parity checking in reception If the parity check fails, the PE flag is set in the LPUART_ISR register and an interrupt is generated if PEIE is set in the LPUART_CR1 register. The PE flag is cleared by software writing ’1’ to the PECF in the LPUART_ICR register. Parity generation in transmission If the PCE bit is set in LPUART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=’0’) or an odd number of “1s” if odd parity is selected (PS=’1’)). 49.3.11 LPUART single-wire Half-duplex communication Single-wire Half-duplex mode is selected by setting the HDSEL bit in the LPUART_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the LPUART_CR2 register, • SCEN and IREN bits in the LPUART_CR3 register. The LPUART can be configured to follow a Single-wire Half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and Full-duplex communication is made with a control bit HDSEL in LPUART_CR3. As soon as HDSEL is written to ‘1’: • The TX and RX lines are internally connected. • The RX pin is no longer used • The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up. Apart from this, the communication protocol is similar to normal LPUART mode. Any conflict on the line must be managed by software (for instance by using a centralized arbiter). In particular, the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set. Note: In LPUART communications, in the case of 1-stop bit configuration, the RXNE flag is set in the middle of the stop bit. 49.3.12 Continuous communication using DMA and LPUART The LPUART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Refer to Section 48.4: USART implementation on page 1953 to determine if the DMA mode is supported. If DMA is not supported, use the LPUSRT as explained in Section 48.5.6. To perform continuous communication. When FIFO is disabled, you can clear the TXE/ RXNE flags in the LPUART_ISR register. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the LPUART_CR3 register. Data are loaded from an SRAM area configured using the DMA peripheral (refer to Section 15: Direct memory access controller (DMA1, DMA2) andSection 16: Basic direct memory access controller (BDMA)) to the LPUART_TDR register whenever the TXE flag 2048/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) (TXFNF flag if FIFO mode is enabled) is set. To map a DMA channel for LPUART transmission, use the following procedure (x denotes the channel number): 1. Write the LPUART_TDR register address in the DMA control register to configure it as the destination of the transfer. The data is moved to this address from memory after each TXE (or TXFNF if FIFO mode is enabled) event. 2. Write the memory address in the DMA control register to configure it as the source of the transfer. The data is loaded into the LPUART_TDR register from this memory area after each TXE (or TXFNF if FIFO mode is enabled) event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA register 5. Configure DMA interrupt generation after half/ full transfer as required by the application. 6. Clear the TC flag in the LPUART_ISR register by setting the TCCF bit in the LPUART_ICR register. 7. Activate the channel in the DMA register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the LPUART communication is complete. This is required to avoid corrupting the last transmission before disabling the LPUART or entering low-power mode. Software must wait until TC=’1’. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame. Figure 595. Transmission using DMA ,GOHSUHDPEOH )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 7;(IODJ 6HWE\KDUGZDUH ,JQRUHGE\WKH'0$EHFDXVH WKHWUDQVIHULVFRPSOHWH '0$UHTXHVW ) 86$57B7'5 ) ) 7&IODJ 6HWE\ KDUGZDUH '0$ZULWHV 86$57B7'5 '0$7&,)IODJ WUDQVIHU FRPSOHWH 6HWE\KDUGZDUH 6RIWZDUH FRQILJXUHV'0$ '0$ZULWHV '0$ZULWHV '0$ZULWHV )LQWR )LQWR )LQWR WRVHQGGDWD EORFNVDQG 86$57B7'5 86$57B7'5 86$57B7'5 HQDEOHV86$57 &OHDUHG E\ VRIWZDUH 7KH'0$ WUDQVIHULV FRPSOHWH 7&,) LQ '0$B,65 6RIWZDUHZDLWVXQWLO7& AIB Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full (i.e. TXFNF = ’1’). DocID029587 Rev 3 2049/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in LPUART_CR3 register. Data are loaded from the LPUART_RDR register to a SRAM area configured using the DMA peripheral (refer to Section 15: Direct memory access controller (DMA1, DMA2) andSection 16: Basic direct memory access controller (BDMA)) whenever a data byte is received. To map a DMA channel for LPUART reception, use the following procedure: 1. Write the LPUART_RDR register address in the DMA control register to configure it as the source of the transfer. The data is moved from this address to the memory after each RXNE (RXFNE in case FIFO mode is enabled) event. 2. Write the memory address in the DMA control register to configure it as the destination of the transfer. The data is loaded from LPUART_RDR to this memory area after each RXNE (RXFNE in case FIFO mode is enabled) event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA control register 5. Configure interrupt generation after half/ full transfer as required by the application. 6. Activate the channel in the DMA control register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. Figure 596. Reception using DMA )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 5;1(IODJ '0$UHTXHVW ) ) 86$57B7'5 ) '0$UHDGV 86$57B7'5 '0$7&,)IODJ WUDQVIHUFRPSOHWH 6RIWZDUHFRQILJXUHVWKH '0$WRUHFHLYHGDWD EORFNVDQGHQDEOHV WKH86$57 6HWE\KDUGZDUH '0$UHDGV) IURP86$57B7'5 '0$UHDGV) IURP86$57B7'5 &OHDUHG E\ VRIWZDUH 7KH'0$WUDQVIHU '0$UHDGV) LVFRPSOHWH IURP86$57B7'5 7&,) LQ '0$B,65 DL E Note: When FIFO management is enabled, the DMA request is triggered by Receive FIFO not empty (i.e. RXFNE = ’1’). Error flagging and interrupt generation in multibuffer communication If any error occurs during a transaction In multibuffer communication mode, the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt 2050/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) enable bit (EIE bit in the LPUART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur. 49.3.13 RS232 Hardware flow control and RS485 Driver Enable It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. The Figure 583 shows how to connect 2 devices in this mode: Figure 597. Hardware flow control between 2 LPUARTs /38$57 /38$57 7; 7;FLUFXLW 5; &76 576 5; 5;FLUFXLW 5;FLUFXLW 7; 7;FLUFXLW 576 &76 06Y 9 RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the LPUART_CR3 register). RS232 RTS flow control If the RTS flow control is enabled (RTSE=’1’), then nRTS is asserted (tied low) as long as the LPUART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 598 shows an example of communication with RTS flow control enabled. Figure 598. RS232 RTS flow control 5; 6WDUW ELW 'DWD 6WRS 6WDUW ,GOH ELW ELW 'DWD 6WRS ELW Q576 5;1( 5;1( 'DWDUHDG 'DWDFDQQRZEHWUDQVPLWWHG 06Y9 Note: When FIFO mode is enabled, nRTS is de-asserted only when RXFIFO is full. DocID029587 Rev 3 2051/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 RS232 CTS flow control If the CTS flow control is enabled (CTSE=’1’), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that data is to be transmitted, in other words, if TXE/TXFE=’0’), else the transmission does not occur. When nCTS is deasserted during a transmission, the current transmission is completed before the transmitter stops. When CTSE=’1’, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the LPUART_CR3 register is set. Figure 599 shows an example of communication with CTS flow control enabled. Figure 599. RS232 CTS flow control &76 &76 Q&76 7UDQVPLWGDWDUHJLVWHU 7'5 'DWD 7; 'DWD HPSW\ 6WRS 6WDUW ELW ELW HPSW\ 'DWD 'DWD :ULWLQJGDWDLQ7'5 6WRS 6WDUW ,GOH ELW ELW 'DWD 7UDQVPLVVLRQRI'DWDLV GHOD\HGXQWLOQ&76 06Y9 Note: For correct behavior, nCTS must be asserted at least 3 LPUART clock source periods before the end of the current character. In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods. RS485 driver enable The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control register. This allows activating the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the LPUART_CR1 control register. The de-assertion time is the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed using the DEDT [4:0] bitfields in the LPUART_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the LPUART_CR3 control register. 2052/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) The LPUART DEAT and DEDT are expressed in LPUART clock source (fCK) cycles: • • The Driver enable assertion time equals – (1 + (DEAT x P)) x fCK, if P # 0 – (1 + DEAT) x fCK , if P = 0 The Driver enable de-assertion time equals – (1 + (DEDT x P)) x fCK, if P # 0 – (1 + DEDT) x fCK, if P = 0 where P = BRR[20:11] 49.3.14 LPUART low-power management The LPUART has advanced low-power mode functions allowing it to transfer properly data even when the lpuart_pclk clock is disabled. The LPUART is able to wake up the MCU from low-power mode when the UESM bit is set. When the usart_pclk is gated, the LPUART provides a wakeup interrupt (usart_wkup) if a specific action requiring the activation of the usart_pclk clock is needed: • If FIFO mode is disabled luart_pclk clock has to be activated to empty the LPUART data register. In this case, the lpuart_wkup interrupt source is the RXNE set to ‘1’. The RXNEIE bit must be set before entering low-power mode. • If FIFO mode is enabled luart_pclk clock has to be activated – to fill the TXFIFO – or to empty the RXFIFO In this case, the lpuart_wkup interrupt source can be: – RXFIFO not empty. In this case, the RXFNEIE bit must be set before entering lowpower mode. – RXFIFO full. In this case, the RXFFIE bit must be set before entering low-power mode, the number of received data corresponds to the RXFIFO size, and the RXFF flag is not set . – TXFIFO empty. In this case, the TXFEIE bit must be set before entering low-power mode. This allows sending/receiving the data in the TXFIFO/RXFIFO during low-power mode. To avoid overrun/underrun errors and transmit/receive data in low-power mode, the lpuart_wkup interrupt source can be one of the following events: – TXFIFO threshold reached. In this case, the TXFTIE bit must be set before entering low-power mode. – RXFIFO threshold reached. In this case, the RXFTIE bit must be set before entering low-power mode. For example, the application can set the threshold to the maximum RXFIFO size if the wakeup time is less than the time to receive a single byte across the line. Using the RXFIFO full, TXFIFO empty, RXFIFO not empty and RXFIFO/TXFIFO threshold interrupts to wakeup the MCU from low-power mode allows doing as many LPUART transfers as possible during low-power mode with the benefit of optimizing consumption. DocID029587 Rev 3 2053/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Alternatively, a specific lpuart_wkup interrupt may be selected through the WUS bitfields. When the wakeup event is detected, the WUF flag is set by hardware and lpuart_wkup interrupt is generated if the WUFIE bit is set. In this case the lpuart_wkup interrupt is not mandatory for the wakeup. The WUF being set is sufficient to wakeup the MCU from lowpower mode. Note: Before entering low-power mode, make sure that no LPUART transfer is ongoing. Checking the BUSY flag cannot ensure that low-power mode is never entered when data reception is ongoing. The WUF flag is set when a wakeup event is detected, independently of whether the MCU is in low-power or in an active mode. When entering low-power mode just after having initialized and enabled the receiver, the REACK bit must be checked to ensure the LPUART is actually enabled. When DMA is used for reception, it must be disabled before entering low-power mode and re-enabled upon exit from low-power mode. When FIFO is enabled, the wakeup from low-power mode on address match is only possible when Mute mode is enabled. Using Mute mode with low-power mode If the LPUART is put into Mute mode before entering low-power mode: Note: • Wakeup from Mute mode on idle detection must not be used, because idle detection cannot work in low-power mode. • If the wakeup from Mute mode on address match is used, then the low-power mode wakeup source from must also be the address match. If the RXNE flag was set when entering the low-power mode, the interface will remain in Mute mode upon address match and wake up from low-power mode. When FIFO management is enabled, Mute mode is used with wakeup from low-power mode without any constraints (i.e.the two points mentioned above about mute and lowpower mode are valid only when FIFO management is disabled). Wakeup from low-power mode when LPUART kernel clock lpuart_ker_ck is OFF in low-power mode If during low-power mode, the lpuart_ker_ck clock is switched OFF, when a falling edge on the LPUART receive line is detected, the LPUART interface requests the lpuart_ker_ck clock to be switched ON thanks to the lpuart_ker_ck_req signal. The lpuart_ker_ck is then used for the frame reception. If the wakeup event is verified, the MCU wakes up from low-power mode and data reception goes on normally. If the wakeup event is not verified, the usart_ker_ck is switched OFF again, the MCU is not waken up and stays in low-power mode and the kernel clock request is released. The example below shows the case of wakeup event programmed to “address match detection” and FIFO management disabled. Figure 600 shows the behavior when the wakeup event is verified. 2054/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Figure 600. Wakeup event verified (wakeup event = address match, FIFO disabled) 'DWDUHFHSWLRQJRHVRQ 5[GDWD 6WRSELW 5[GDWD 6WDUWELW 5;OLQH 6WRSELW ,GOH 6WDUWELW $GGUHVVPDWFKHYHQW:8) ¶ /38$57VHQGVDZDNHXSHYHQWWRWKH0&8 6WDUWXSWLPH OSXDUWBNHUBFN 21 2)) /RZSRZHUPRGH 5XQPRGH 06Y9 Figure 601 shows the behavior when the wakeup event is not verified. Figure 601. Wakeup event not verified (wakeup event = address match, FIFO disabled) 5;OLQH ,GOH 5[GDWD 6WRSELW ,GOH 6WDUWELW $GGUHVVGRHVQRWPDWFK 6WDUWXSWLPH OSXDUWBNHUBFN 2)) 21 2)) /RZSRZHUPRGH 06Y9 Note: The above figures are valid when address match or any received frame is used as wakeup event. In the case the wakeup event is the start bit detection, the LPUART sends the wakeup event to the MCU at the end of the start bit. DocID029587 Rev 3 2055/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) 49.4 RM0433 LPUART interrupts Refer to Table 381 for a detailed description of all LPUART interrupt requests. Table 387. LPUART interrupt requests Interrupt event Transmit data register empty Transmit FIFO Not Full Transmit FIFO Empty Event flag Enable Control bit TXE TXEIE TXFNF TXFE Interrupt activated Interrupt clear method lpuart_it lpuart_wkup TXE cleared when a data is written in TDR YES NO TXFNFIE TXFNF cleared when TXFIFO is full. YES NO TXFEIE TXFE cleared when the TXFIFO contains at least one data or by setting TXFRQ bit. YES YES YES YES Transmit FIFO threshold reached TXFT TXFTIE TXFT is cleared by hardware when the TXFIFO content is less than the programmed threshold CTS interrupt CTSIF CTSIE CTSIF cleared by software by setting CTSCF bit. YES NO TC TCIE TC cleared when a data is written in TDR or by setting TCCF bit. YES NO Receive data register not empty (data ready to be read) RXNE RXNEIE RXNE cleared by reading RDR or by setting RXFRQ bit. YES YES Receive FIFO Not Empty RXFNE RXFNE cleared when the RXFNEIE RXFIFO is empty or by setting RXFRQ bit. YES YES Receive FIFO Full RXFF(1) RXFFIE RXFF cleared when the RXFIFO contains at least one data. YES YES RXFT is cleared by hardware when the RXFIFO content is less than the programmed threshold YES YES Transmission Complete Receive FIFO threshold reached RXFT RXFTIE Overrun error detected ORE RXORE cleared by setting NEIE/RX ORECF bit. FNEIE YES NO Idle line detected IDLE IDLEIE IDLE cleared by setting IDLECF bit. YES NO PE PEIE PE cleared by setting PECF bit. YES NO Parity error 2056/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Table 387. LPUART interrupt requests (continued) Event flag Interrupt event Noise Flag, Overrun error and Framing Error in multibuffer communication. Interrupt activated Interrupt clear method lpuart_it lpuart_wkup NE cleared by setting NFCF bit. ORE cleared by setting ORECF bit. FE flag cleared by setting FECF bit. YES NO YES NO NO YES NE or ORE or FE EIE CMF CMIE CMF cleared by setting CMCF bit. WUF(2) WUFIE WUF is cleared by setting WUCF bit. TXFTIE TXFT is cleared by hardware when the TXFIFO content is less than the programmed threshold YES YES RXFTIE RXFT is cleared by hardware when the RXFIFO content is less than the programmed threshold. YES YES Character match Wakeup from low-power mode Enable Control bit Transmit FIFO threshold reached TXFT Receive FIFO threshold reached RXFT 1. RXFF flag is asserted if the LPUART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in LPUART_RDR. In Stop mode, LPUART_RDR is not clocked. As a result, this register will not be written and once n data are received and written in the RXFIFO, the RXFF interrupt will be asserted (RXFF flag is not set). 2. The WUF interrupt is active only in low-power mode. 49.5 LPUART registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. 49.5.1 Control register 1 (LPUART_CR1) Address offset: 0x00 Reset value: 0x0000 31 30 29 28 27 26 RXF FIE TXFEIE FIFO EN M1 Res. Res. 11 10 rw rw rw rw 15 14 13 12 Res. 25 24 23 22 21 20 19 DEAT[4:0] 18 17 16 DEDT[4:0] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 TCIE TE RE UESM UE rw rw rw rw rw CMIE MME M0 WAKE PCE PS PEIE TXEIET XFN FIE rw rw rw rw rw rw rw rw DocID029587 Rev 3 RXNEIE RXFN IDLEIE EIE rw rw 2057/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bit 31 RXFFIE:RXFIFO Full interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated when RXFF=’1’ in the LPUART_ISR register Note: When FIFO mode is disabled, this bit is reserved and must be kept at reset value. Bit 30 TXFEIE:TXFIFO empty interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated when TXFE=’1’ in the LPUART_ISR register Note: When FIFO mode is disabled, this bit is reserved and must be kept at reset value. Bit 29 FIFOEN:FIFO mode enable This bit is set and cleared by software. 0: FIFO mode is disabled. 1: FIFO mode is enabled. Bit 28 M1: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ‘00’: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = ‘01’: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = ‘10’: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UE=’0’). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. Bits 27:26 Reserved, must be kept at reset value. Bits 25:21 DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 48.5.20: RS232 Hardware flow control and RS485 Driver Enable. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bits 20:16 DEDT[4:0]: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 49.3.13: RS232 Hardware flow control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 15 Reserved, must be kept at reset value. Bit 14 CMIE: Character match interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. Bit 13 MME: Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. 0: Receiver in active mode permanently 1: Receiver can switch between Mute mode and active mode. 2058/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bit 12 M0: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UE=’0’). Bit 11 WAKE: Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. 0: Idle line 1: Address mark This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 10 PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=’1’; 8th bit if M=’0’) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 9 PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever PE=’1’ in the LPUART_ISR register Bit 7 TXEIE/TXFNFIE: Transmit data register empty/TXFIFO not full interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A LPUART interrupt is generated whenever TXE/TXFNF =’1’ in the LPUART_ISR register Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever TC=’1’ in the LPUART_ISR register Bit 5 RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A LPUART interrupt is generated whenever ORE=’1’ or RXNE/RXFNE=’1’ in the LPUART_ISR register Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever IDLE=’1’ in the LPUART_ISR register DocID029587 Rev 3 2059/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bit 3 TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Note: During transmission, a low pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts. Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. 0: LPUART not able to wake up the MCU from low-power mode. 1: LPUART able to wake up the MCU from low-power mode. When this function is active, the clock source for the LPUART must be HSI or LSE (see RCC chapter) Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode. Bit 0 UE: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. 0: LPUART prescaler and outputs disabled, low-power mode 1: LPUART enabled Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = ’0’ so the DMA channel must be disabled before resetting the UE bit. 49.5.2 Control register 2 (LPUART_CR2) Address offset: 0x04 Reset value: 0x0000 31 30 29 28 27 ADD[7:4] 26 25 24 ADD[3:0] 23 22 21 20 Res. Res. Res. Res. 19 18 17 MSBFI DATAINV TXINV RST 16 RXINV rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWAP Res. Res. Res. Res. Res. Res. Res. Res. ADDM7 Res. Res. Res. Res. rw 2060/3178 STOP[1:0] rw rw rw DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:28 ADD[7:4]: Address of the LPUART node This bitfield gives the address of the LPUART node or a character code to be recognized. It is used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or Stop mode. The MSB of the character sent by the transmitter should be equal to 1. It can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bitfield can only be written when reception is disabled (RE = ’0’) or the LPUART is disabled (UE=’0’) Bits 27:24 ADD[3:0]: Address of the LPUART node This bitfield gives the address of the LPUART node or a character code to be recognized. This is used for wakeup with address mark detection in multiprocessor communication during Mute mode or low-power mode. This bitfield can only be written when reception is disabled (RE = ’0’) or the LPUART is disabled (UE=’0’) Bits 23:20 Reserved, must be kept at reset value. Bit 19 MSBFIRST: Most significant bit first This bit is set and cleared by software. 0: data is transmitted/received with data bit 0 first, following the start bit. 1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 17 TXINV: TX pin active level inversion This bit is set and cleared by software. 0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 16 RXINV: RX pin active level inversion This bit is set and cleared by software. 0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 15 SWAP: Swap TX/RX pins This bit is set and cleared by software. 0: TX/RX pins are used as defined in standard pinout 1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bitfield can only be written when the LPUART is disabled (UE=’0’). Bit 14 Reserved, must be kept at reset value. DocID029587 Rev 3 2061/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bits 13:12 STOP[1:0]: STOP bits These bits are used for programming the stop bits. 00: 1 stop bit 01: Reserved. 10: 2 stop bits 11: Reserved This bitfield can only be written when the LPUART is disabled (UE=’0’). Bits 11:5 Reserved, must be kept at reset value. Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. 0: 4-bit address detection 1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the LPUART is disabled (UE=’0’) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. Bits 3:0 Reserved, must be kept at reset value. 49.5.3 Control register 3 (LPUART_CR3) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 RXFTI E. RXFTCFG rw 26 25 24 RXFTCFG rw 22 TXFTIE WUFIE 21 20 WUS[2:0] 19 18 17 16 Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEP DEM DDRE OVR DIS Res. CTSIE CTSE RTSE DMAT DMAR Res. Res. HD SEL Res. Res. EIE rw rw rw rw rw rw rw rw rw 2062/3178 rw Res. 23 DocID029587 Rev 3 rw rw RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:29 TXFTCFG: TXFIFO threshold configuration 000:TXFIFO reaches 1/8 of its depth. 001:TXFIFO reaches 1/4 of its depth. 110:TXFIFO reaches 1/2 of its depth. 011:TXFIFO reaches 3/4 of its depth. 100:TXFIFO reaches 7/8 of its depth. 101:TXFIFO becomes empty. Remaining combinations: Reserved. Bit28 RXFTIE: RXFIFO threshold interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. Bits 27:25 RXFTCFG: Receive FIFO threshold configuration 000:Receive FIFO reaches 1/8 of its depth. 001:Receive FIFO reaches 1/4 of its depth. 110:Receive FIFO reaches 1/2 of its depth. 011:Receive FIFO reaches 3/4 of its depth. 100:Receive FIFO reaches 7/8 of its depth. 101:Receive FIFO becomes full. Remaining combinations: Reserved. Bit 24 Reserved, must be kept at reset value. Bit 23 TXFTIE: TXFIFO threshold interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. Bit 22 WUFIE: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever WUF=’1’ in the LPUART_ISR register Note: WUFIE must be set before entering in low-power mode. The WUF interrupt is active only in low-power mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation. Bits 21:20 WUS[1:0]: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01:Reserved. 10: WUF active on Start bit detection 11: WUF active on RXNE. This bitfield can only be written when the LPUART is disabled (UE=’0’). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation. Bits 19:16 Reserved, must be kept at reset value. DocID029587 Rev 3 2063/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bit 15 DEP: Driver enable polarity selection 0: DE signal is active high. 1: DE signal is active low. This bit can only be written when the LPUART is disabled (UE=’0’). Bit 14 DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. 0: DE function is disabled. 1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the LPUART is disabled (UE=’0’). Bit 13 DDRE: DMA Disable on Reception Error 0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. 1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = ’0’) or clear RXNE before clearing the error flag. This bit can only be written when the LPUART is disabled (UE=’0’). Note: The reception errors are: parity error, framing error or noise error. Bit 12 :OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=’0’). Note: This control bit allows checking the communication flow w/o reading the data. Bit 11 Reserved, must be kept at reset value. Bit 10 CTSIE: CTS interrupt enable 0: Interrupt is inhibited 1: An interrupt is generated whenever CTSIF=’1’ in the LPUART_ISR register Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the LPUART is disabled (UE=’0’) Bit 8 RTSE: RTS enable 0: RTS hardware flow control disabled 1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the LPUART is disabled (UE=’0’). Bit 7 DMAT: DMA enable transmitter This bit is set/reset by software 1: DMA mode is enabled for transmission 0: DMA mode is disabled for transmission 2064/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bit 6 DMAR: DMA enable receiver This bit is set/reset by software 1: DMA mode is enabled for reception 0: DMA mode is disabled for reception Bits 5:4 Reserved, must be kept at reset value. Bit 3 HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected 1: Half duplex mode is selected This bit can only be written when the LPUART is disabled (UE=’0’). Bits 2:1 Reserved, must be kept at reset value. Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=’1’ or ORE=’1’ or NE=’1’ in the LPUART_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=’1’ or ORE=’1’ or NE=’1’ in the LPUART_ISR register. 49.5.4 Baud rate register (LPUART_BRR) This register can only be written when the LPUART is disabled (UE=’0’). It may be automatically updated by hardware in auto baud rate detection mode. Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19 18 17 16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BRR[19:16] BRR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:0 BRR[19:0] Note: It is forbidden to write values lower than 0x300 in the LPUART_BRR register. Provided that LPUART_BRR must be ≥ 0x300 and LPUART_BRR is 20 bits, a care should be taken when generating high baud rates using high fck values. fck must be in the range [3 x baud rate..4096 x baud rate]. DocID029587 Rev 3 2065/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) 49.5.5 RM0433 Request register (LPUART_RQR) Address offset: 0x18 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFRQ RXFRQ MMRQ SBKRQ w w w Res. w Bits 31:5 Reserved, must be kept at reset value. Bit 4 TXFRQ: Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This will set the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. Bit 3 RXFRQ: Receive data flush request Writing ’1’ to this bit clears the RXNE flag. This allows discarding the received data without reading it, and avoid an overrun condition. Bit 2 MMRQ: Mute mode request Writing ’1’ to this bit puts the LPUART in Mute mode and resets the RWU flag. Bit 1 SBKRQ: Send break request Writing ’1’ to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. Bit 0 Reserved, must be kept at reset value. 49.5.6 Interrupt & status register (LPUART_ISR) Address offset: 0x1C Reset value: 0x00C0 (In case FIFO disabled) Reset value: 0x08000C0 (In case FIFO enabled) 31 30 29 28 27 26 Res. Res. Res. Res. TXFT r r 15 14 13 12 11 Res. Res. Res. Res. Res. 2066/3178 RXFT 25 24 23 22 21 20 19 18 17 16 TXFE RE ACK TE ACK WUF RWU SBKF CMF BUSY Res. RXFF r r r r r r r r r 10 9 8 7 6 5 4 3 2 1 0 CTS CTSIF Res. TXE TC RXNE IDLE ORE NE FE PE r r r r r r r r r r DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:28 Reserved, must be kept at reset value. Bit 27 TXFT: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =’1’ (bit 31) in the LPUART_CR3 register. 0: TXFIFO does not reach the programmed threshold. 1: TXFIFO reached the programmed threshold. Bit 26 RXFT: RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =’1’ (bit 27) in the LPUART_CR3 register. 0: Receive FIFO does not reach the programmed threshold. 1: Receive FIFO reached the programmed threshold. Bit 25 Reserved, must be kept at reset value. Bit 24 RXFF: RXFIFO Full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit =’1’ in the LPUART_CR1 register. 0: RXFIFO is not Full. 1: RXFIFO is Full. Bit 23 TXFE: TXFIFO Empty This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing ’1’ to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit =’1’ (bit 30) in the LPUART_CR1 register. 0: TXFIFO is not empty. 1: TXFIFO is empty. Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bit 21 TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE=’0’, followed by TE=’1’ in the LPUART_CR1 register, in order to respect the TE=’0’ minimum period. Bit 20 WUF: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=’1’ in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. The WUF interrupt is active only in low-power mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. DocID029587 Rev 3 2067/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bit 19 RWU: Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing ’1’ to the MMRQ bit in the LPUART_RQR register. 0: Receiver in active mode 1: Receiver in Mute mode Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bit 18 SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing ’1’ to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 0: No break character is transmitted 1: Break character will be transmitted Bit 17 CMF: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing ’1’ to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE=’1’in the LPUART_CR1 register. 0: No Character match detected 1: Character Match detected Bit 16 BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 0: LPUART is idle (no reception) 1: Reception on going Bits 15:11 Reserved, must be kept at reset value. Bit 10 CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. 0: nCTS line set 1: nCTS line reset Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 9 CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing ’1’ to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE=’1’ in the LPUART_CR3 register. 0: No change occurred on the nCTS status line 1: A change occurred on the nCTS status line Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 8 Reserved, must be kept at reset value. 2068/3178 DocID029587 Rev 3 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bit 7 TXE/TXFNF: Transmit data register empty/TXFIFO not full When FIFO mode is disabled, TXE is set by hardware when the content of the LPUART_TDR register has been transferred into the shift register. It is cleared by a write to the LPUART_TDR register. When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO. (TXFNF and TXFE will be set at the same time). An interrupt is generated if the TXEIE/TXFNFIE bit =’1’ in the LPUART_CR1 register. 0: Data register is full/Transmit FIFO is full. 1: Data register/Transmit FIFO is not full. Note: This bit is used during single buffer transmission. Bit 6 TC: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXE/TXFF is set. An interrupt is generated if TCIE=’1’ in the LPUART_CR1 register. It is cleared by software, writing ’1’ to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIE=’1’ in the LPUART_CR1 register. 0: Transmission is not complete 1: Transmission is complete Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately. Bit 5 RXNE/RXFNE: Read data register not empty/RXFIFO not empty RXNE bit is set by hardware when the content of the LPUART_RDR shift register has been transferred to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The RXNE flag can also be cleared by writing ’1’ to the RXFRQ in the LPUART_RQR register. RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXNE/RXFNE flag can also be cleared by writing ’1’ to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXNEIE/RXFNEIE=’1’ in the LPUART_CR1 register. 0: Data is not received 1: Received data is ready to be read. Bit 4 IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=’1’ in the LPUART_CR1 register. It is cleared by software, writing ’1’ to the IDLECF in the LPUART_ICR register. 0: No Idle line is detected 1: Idle line is detected Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=’1’), IDLE is set if the LPUART is not mute (RWU=’0’), whatever the Mute mode selected by the WAKE bit. If RWU=’1’, IDLE is not set. DocID029587 Rev 3 2069/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bit 3 ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXNE=’1’ (RXFF = ’1’ in case FIFO mode is enabled). It is cleared by a software, writing ’1’ to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXNEIE/ RXFNEIE=’1’ or EIE = ’1’ in the LPUART_CR1 register. 0: No overrun error 1: Overrun error is detected Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. Bit 2 NE Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing ’1’ to the NFCF bit in the LPUART_ICR register. 0: No noise is detected 1: Noise is detected Note: This bit does not generate an interrupt as it appears at the same time as the RXNE/RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. In FIFO mode, this error is associated with the character in the LPUART_RDR. Bit 1 FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing ’1’ to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the LPUART_CR1 register. 0: No Framing error is detected 1: Framing error or break character is detected Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. Bit 0 PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing ’1’ to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = ’1’ in the LPUART_CR1 register. 0: No parity error 1: Parity error Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. 49.5.7 Interrupt flag clear register (LPUART_ICR) Address offset: 0x20 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res. 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 Res. Res. Res. Res. Res. Res. CTSCF Res. Res. TCCF Res. NECF FECF PECF w_r0 w_r0 w_r0 w_r0 w_r0 2070/3178 w_r0 DocID029587 Rev 3 4 w_r0 IDLECF ORECF w_r0 w_r0 RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:21 Reserved, must be kept at reset value. Bit 20 WUCF: Wakeup from low-power mode clear flag Writing ’1’ to this bit clears the WUF flag in the LPUART_ISR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 48.4: USART implementation. Bits 19:18 Reserved, must be kept at reset value. Bit 17 CMCF: Character match clear flag Writing ’1’ to this bit clears the CMF flag in the LPUART_ISR register. Bits 16:10 Reserved, must be kept at reset value. Bit 9 CTSCF: CTS clear flag Writing ’1’ to this bit clears the CTSIF flag in the LPUART_ISR register. Bits 8:7 Reserved, must be kept at reset value. Bit 7 Reserved, must be kept at reset value. Bit 6 TCCF: Transmission complete clear flag Writing ’1’ to this bit clears the TC flag in the LPUART_ISR register. Bit 5 Reserved, must be kept at reset value. Bit 4 IDLECF: Idle line detected clear flag Writing ’1’ to this bit clears the IDLE flag in the LPUART_ISR register. Bit 3 ORECF: Overrun error clear flag Writing ’1’ to this bit clears the ORE flag in the LPUART_ISR register. Bit 2 NECF: Noise detected clear flag Writing ’1’ to this bit clears the NE flag in the LPUART_ISR register. Bit 1 FECF: Framing error clear flag Writing ’1’ to this bit clears the FE flag in the LPUART_ISR register. Bit 0 PECF: Parity error clear flag Writing ’1’ to this bit clears the PE flag in the LPUART_ISR register. 49.5.8 Receive data register (LPUART_RDR) Address offset: 0x24 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. r r r r r r r r RDR[8:0] DocID029587 Rev 3 r 2071/3178 2074 Low-power universal asynchronous receiver transmitter (LPUART) RM0433 Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 588). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 49.5.9 Transmit data register (LPUART_TDR) Address offset: 0x28 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw rw 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. TDR[8:0] rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 588). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=’1’. 49.5.10 Prescaler register (LPUART_PRESC) This register can only be written when the LPUART is disabled (UE=’0’). Address offset: 0x2C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRESCALER[3:0] rw 2072/3178 DocID029587 Rev 3 rw rw rw RM0433 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 PRESCALER[3:0]: Clock prescaler The LPUART input clock can be divided by a prescaler: 0000: input clock not divided 0001: input clock divided by 2 0010: input clock divided by 4 0011: input clock divided by 6 0100: input clock divided by 8 0101: input clock divided by 10 0110: input clock divided by 12 0111: input clock divided by 16 1000: input clock divided by 32 1001: input clock divided by 64 1010: input clock divided by 128 1011: input clock divided by 256 Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value will be «1011» i.e. input clock divided by 256. DocID029587 Rev 3 2073/3178 2074 0x2C LPUART_ PRESC 2074/3178 DocID029587 Rev 3 0 0 0 0 Reset value Refer to Section 2.2.2 on page 105 for the register boundary addresses. FE PE 0 0 0 0 0 0 0 Res. SBKRQ 0 MMRQ Reset value 0 0 0 0 0 0 0 RDR[8:0] 0 TDR[8:0] 0 FECF NE 0 TXFRQ 0 RXFRQ 0 Res. DMAT 0 TE UESM UE 0 0 Res. Res. Res. EIE HDSEL RE Res. 0 Res. TCIE RXNEIE Res. 0 Res. TXEIE Res. IDLEIE 0 0 ADDM7 Res. Res. DMAR Res. 0 PECF ORE 0 Res. 0 NECF IDLE 0 IDLECF 0 Res. 0 ORECF RXNE 1 Res. 0 TC PS 0 Res. PEIE 0 Res. 0 TXE RTSE PCE 0 Res. 0 Res. 0 Res. CTSE WAKE 0 Res. 0 TCCF 0 Res. CTSIE 0 Res. Reset value Res. CTSCF 0 Res. M 0 Res. Reset value Res. CTSIF 0 Res. MME 0 Res. CMIE DEDT0 Res. 0 Res. Res. CTS 0 Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. OVRDIS 0 Res. 0 Res. DEM DDRE 0 Res. Res. 0 Res. Res. 0 Res. Reserved 0 Res. 0 Res. Res. Res. Res. [1:0] Res. Res. Res. Res. SWAP Res. DEP STOP Res. Res. Res. Reset value Res. Res. 0 Res. Res. Res. DEDT1 RXINV 0 Res. Res. Res. 0 Res. Res. Res. TXINV 0 Res. 0 Res. Res. BUSY 0 Res. Res. DATAINV 0 Res. DEDT2 MSBFIRST 0 Res. 0 Res. 0 Res. DEAT0 DEDT4 DEDT3 DEAT1 0 Res. Res. DEAT2 0 Res. CMF 0 CMCF 0x14 Res. 0x10- Res. [1:0] Res. WUS Res. 0 Res. 0 Res. 0 Res. RWU SBKF 0 Res. Res. 0 Res. Res. DEAT3 0 Res. WUF 0 WUCF Res. WUFIE 0 Res. Res. 0 Res. TEACK 0 Res. Res. Res. TXFTIE 0 Res. Res. 0 Res. REACK 0 Res. Res. Res. 0 Res. TXFF 0 Res. Res. DEAT4 0 Res. Res. Res. Res. RXFF 0 Res. FIFOEN M1 Res. TXFEIE 0 Res. Res. Res. Res. Reset value Res. Res. Res. Res. RXFT CFG Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. RXFTIE ADD[3:0] Res. Res. Res. 0 Res. RXFFIE 0 Res. Res. RXFT Res. Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. TXFT Reset value Res. Res. Res. 0 Res. Res. Res. TXFT CFG Res. Res. 0 Res. Res. 0 Res. ADD[7:4] Res. LPUART_TDR 0 Res. LPUART_RDR 0 Res. LPUART_ICR 0 Res. 0x28 LPUART_ISR Res. 0x24 LPUART_RQR 0 Res. 0x20 BRR 0 Res. LPUART_ Res. 0x1C LPUART_CR3 Res. 0x0C Res. Reset value 0 Res. Reset value Res. 0x18 LPUART_CR2 Res. Reset value Res. 0x08 CR1 Res. LPUART_ Res. 0x00 Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 49.5.11 Res. Low-power universal asynchronous receiver transmitter (LPUART) RM0433 LPUART register map The table below gives the LPUART register map and reset values. Table 388. LPUART register map and reset values 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR[19:0] 0 0 0 0 PRESCALE R[3:0] 0 0 0 RM0433 Serial peripheral interface (SPI) 50 Serial peripheral interface (SPI) 50.1 Introduction The serial peripheral interface (SPI) can be used to communicate with external devices while using the specific synchronous protocol. The (SPI) interface supports a half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master or slave and is capable of operating in multi slave or multi master configurations. In case of master configuration it provides the communication clock (SCK) to the external slave device. The slave select signal can be provided by the master and accepted by the slave optionally, too. The Motorola data format is used by default, but some other specific modes are supported as well. 50.2 SPI main features • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) • 4-bit to 32-bit data size selection • Multi master or multi slave mode capability • Dual clock domain, separated clock for the peripheral kernel which can be independent of PCLK • 8 master mode baud rate prescalers up to kernel frequency/2 • Slave mode frequency up to kernel frequency/2 • Protection of configuration and setting • Hardware or software management of SS for both master and slave • Adjustable minimum delays between data and between SS and data flow • Configurable SS signal polarity and timing, MISO x MOSI swap capability • Programmable clock polarity and phase • Programmable data order with MSB-first or LSB-first shifting • Programmable number of data within a transaction to control SS and CRC • Dedicated transmission and reception flags with interrupt capability • Slave's transmission and/or reception capability in Stop mode (no clock provided to the peripheral) with wake up • SPI Motorola and TI formats support • Hardware CRC feature can secure communication at the end of transaction by: - Adding CRC value at Tx mode - Automatic CRC error checking for Rx mode • Master mode fault, overrun or underrun, CRC error detection with interrupt capability • Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability • Programmable number of data in transaction • Configurable FIFO thresholds (data packing) • Configurable behavior at slave underrun condition (support of cascaded circular buffers) DocID029587 Rev 3 2075/3178 2149 Serial peripheral interface (SPI) 50.3 RM0433 SPI implementation Table 389. STM32H7xx SPI features SPI modes/features SPI2S1 SPI2S2 SPI2S3 SPI4 SPI5 SPI6 Rx & TxFIFO size (N) [x 8-bit] 16 16 16 8 8 8 Maximum configurable data size [bits] 32 32 32 16 16 16 I2S feature Yes Yes Yes No No No 50.4 SPI functional description 50.4.1 SPI block diagram The SPI allows a synchronous, serial communication between the MCU and external devices. The application software can manage the communication by polling the status flag or using a dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram at Figure 602. 2076/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 602. SPI2S block diagram 63,6 6HULDOLQWHUIDFHFORFNGRPDLQ ,54,QWHUIDFH 66/RJLF '0$,QWHUIDFH :6 6<1& 63,6B7;'5 5[),)2 63,B8'5'5 63,6B5;'5 63,B,6&)*5 63,6B&5 63,B&5 63,B&)*> @ VSLBSFON FORFNGRPDLQ &5& &RQWUROOHU 7;6KLIW5HJ 8'5 &RQWUROOHU 7[),)2 ELW$3%EXV 63,B&5&32/< 63,B7;&5& 63,B5;&5& VSLBSFON 66 6<1& &20&RQWUROOHU 63,6B,(5 63,6B65 63,6B,)&5 6<1& VSLBZNXS VSLBLW VSLBW[BGPD VSLBU[BGPD 5;6KLIW5HJ &ORFN*HQHUDWRU 026, 6'2 0,62 6', 6&. &. 0&. VSLBNHUBFNFORFNGRPDLQ VSLBNHUBFN 06Y9 The simplified scheme of Figure 602 shows three fully independent clock domains: • The spi_pclk clock domain, • The spi_ker_ck kernel clock domain, • The serial interface clock domain, All the control and status signals between these domains are strictly synchronized. There is no specific constraint concerning the frequency ratio between these clock signals. The user has to consider a ratio compatible with the data flow speed in order to avoid any data underrun or overrun events only. The spi_pclk clock signal feeds the peripheral bus interface. It has to be active when it accesses to the SPI registers are required. The SPI working in slave mode handles data flow using the serial interface clock derived from the external SCK signal provided by external master SPI device. That is why the SPI slave is able to receive and send data even when the spi_pclk and spi_ker_ck clock signals are inactive. This is not the case for the SPI master as it needs an active spi_ker_ck kernel clock coming from the RCC to feed the clock generator at least. On the other side, a specific slave logic DocID029587 Rev 3 2077/3178 2149 Serial peripheral interface (SPI) RM0433 working within the serial interface clock domain needs some additional traffic to be setup correctly (e.g. when underrun or overrun is evaluated). This cannot be done when the bus becomes into idle. At specific case the slave even requires the clock generator working (see Section 50.5.1: TI mode). 50.4.2 SPI signals Four I/O pins are dedicated to SPI communication with external devices. • MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data in slave mode and receive data in master mode. • MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data in master mode and receive data in slave mode. • SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves. • SS: Slave select pin. Depending on the SPI and SS settings, this pin can be used to either: – Select an individual slave device for communication – Synchronize the data frame or – Detect a conflict between multiple masters See Section 50.4.6: Multi-master communication for details. The SPI bus allows the communication between one master device and one or more slave devices. The bus consists of at least two wires: one for the clock signal and the other for synchronous data transfer. Other signals can be added depending on the data exchange between SPI nodes and their slave select signal management. the functionality between MOSI and MISO pins can be inverted in any SPI mode (see the IOSWP bit at SPI_CFG2 register). 50.4.3 SPI communication general aspects The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software SS management) or 3/4 wires (with hardware SS management). The communication is always initiated and controlled by the master. The master provides a clock signal on the SCK line and selects or synchronizes slave(s) for communication by SS line when it is managed by HW. The data between the master and the slave, flow on the MOSI and/or MISO lines. 50.4.4 Communications between one master and one slave The communication flow may use one of 3 possible modes: full-duplex (3 wires), half-duplex (2 wires) or simplex (2 wires). The SS signal is optional in single master-slave configuration and is often not connected between the two communication nodes. Nevertheless, the SS signal can be helpful at this configuration to synchronize the data flow and it is used by default at some specific SPI modes (e.g. TI mode). Full-duplex communication By default, the SPI is configured for full-duplex communication (bits COMM[1:0]=00 in the SPI_CFG2 register). In this configuration, the shift registers of the master and slave are linked using two unidirectional lines between the MOSI and the MISO pins. During the SPI communication, the data are shifted synchronously on the SCK clock edges provided by the 2078/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) master. The master transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO line simultaneously. When the data frame transfer is complete (all the bits are shifted) the information between the master and slave is exchanged. Figure 603. Full-duplex single master/ single slave application 5[VKLIWUHJLVWHU 7[VKLIWUHJLVWHU 63,FORFN JHQHUDWRU 0,62 0,62 026, 026, 6&. 6&. 66 7[VKLIWUHJLVWHU 5[VKLIWUHJLVWHU 66 0DVWHU 6ODYH 06Y9 1. The SS pin is configured at output mode at master. The pins can be left unconnected then SS is managed by software internally on both master and slave side. Half-duplex communication The SPI can communicate in half-duplex mode by setting COMM[1:0]=11 in the SPI_CFG2 register. In this configuration, one single cross connection line is used to link the shift registers of the master and slave together. During this communication, the data are synchronously shifted between the shift registers on the SCK clock edge in the transfer direction selected reciprocally by both master and slave with the HDDIR bit in their SPI_CR1 registers. Note that the SPI has to be disabled when changing direction of the communication. In this configuration, the MISO pin at master and the MOSI pin at slave are free for other application uses and act as GPIOs. Figure 604. Half-duplex single master/ single slave application 5[VKLIWUHJLVWHU 7[VKLIWUHJLVWHU 63,FORFN JHQHUDWRU 0,62 026, 0,62 Nȍ 6&. 66 0DVWHU 026, 7[VKLIWUHJLVWHU 5[VKLIWUHJLVWHU 6&. 66 6ODYH 06Y9 1. The SS pin is configured at output mode at master. The pins can be left unconnected then SS is managed by software internally on both master and slave side. 2. In this configuration, the MISO pin at master and MOSI pin at slave can be used as GPIOs 3. A critical situation can happen when communication direction is changed not synchronously between two nodes working at bidirectional mode and new transmitter accesses the common data line while former transmitter still keeps an opposite value on the line (the value depends on SPI configuration and communicated data). Both nodes can fight with opposite outputs levels on the line temporary till next node change its direction setting correspondingly, too. It is suggested to insert serial resistance between MISO and MOSI pins at this mode to protect the outputs and limit the current blowing between them at this situation, DocID029587 Rev 3 2079/3178 2149 Serial peripheral interface (SPI) RM0433 Simplex communications The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receiveonly using the COMM[1:0] field in the SPI_CFG2 register. In this configuration, only one line is used for the transfer between the shift registers of the master and slave. The remaining MISO or MOSI pins pair is not used for communication and can be used as standard GPIOs. • Transmit-only mode: COMM[1:0]=01 The master in transmit-only mode generates the clock as long as there are data available in the TxFIFO and the master transfer is on-going. The slave in transmit only mode sends data as long as it receives a clock on the SCK pin and the SS pin (or SW managed internal signal) is active (see 50.4.6: Multi-master communication). • Receive-only mode: COMM[1:0]=10 In master mode, the MOSI output is disabled and may be used as GPIO. The clock signal is generated continuously as long as the SPI is enabled and the CSTART bit in the SPI_CR1 register is set. The clock will be stopped either by SW explicitly requesting this by setting the CSUSP bit in the SPI_CR1 register or automatically when the RxFIFO is full, when the MASRX bit in the SPI_CR1 is set. In slave configuration, the MISO output is disabled and the pin can be used as a GPIO. The slave continues to receive data from the MOSI pin while its slave select signal is active (see 50.4.6: Multi-master communication). Received data events appear depending on the data buffer configuration. Note: At whatever master and slave modes, the data pin dedicated for transmission can be replaced by the data pin dedicated for reception and vice versa by changing the IOSWP bit value in the SPI_CFG2 register. (This bit may only be modified when the SPI is disabled). Any simplex communication can be replaced by a variant of the half duplex communication with a constant setting of the transaction direction (bidirectional mode is enabled, while the HDDIR bit is never changed). Figure 605. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) 5[VKLIWUHJLVWHU 7[VKLIWUHJLVWHU 63,FORFN JHQHUDWRU 0,62 0,62 026, 026, 6&. 6&. 66 0DVWHU 7[VKLIWUHJLVWHU 5[VKLIWUHJLVWHU 66 ^ůĂǀĞ 06Y9 1. The SS pin is configured at output mode at master. The pins can be left unconnected then SS is managed by software internally on both master and slave side. 2. The input information is captured in the shift register and must be ignored in standard transmit only mode (for example, OVF flag) 3. In this configuration, both the MISO pins can be used as GPIOs. 2080/3178 DocID029587 Rev 3 RM0433 50.4.5 Serial peripheral interface (SPI) Standard multi-slave communication In a configuration with two or more independent slaves, the master uses a star topology with dedicated GPIO pins to manage the chip select lines for each slave separately (see Figure 606.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave SS input (only one slave can control data on common MISO line at time). When this is done, a communication between the master and the selected slave is established. Except the simplicity, the advantage of this topology is that a specific SPI configuration can be applied for each slave as all the communication sessions are performed separately just within single master-slave pair. Optionally, when there is no need to read any information from slaves, the master can transmit the same information to the multiple slaves. Figure 606. Master and three independent slaves at star topology 66 5[VKLIWUHJLVWHU 7[VKLIWUHJLVWHU 63,FORFN JHQHUDWRU 9FF 0,62 0,62 026, 026, 6&. 6&. ,2 0DVWHU 7[VKLIWUHJLVWHU 5[VKLIWUHJLVWHU 66 6ODYH ,2 ,2 0,62 026, 7[VKLIWUHJLVWHU 5[VKLIWUHJLVWHU 6&. 66 6ODYH 0,62 026, 7[VKLIWUHJLVWHU 5[VKLIWUHJLVWHU 6&. 66 6ODYH 06Y9 1. SS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to prevent any MODF error. 2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their MISO pin set as alternate function open-drain (see Section 11.3.7: I/O alternate function input/output on page 489.) DocID029587 Rev 3 2081/3178 2149 Serial peripheral interface (SPI) RM0433 The master can handle the SPI communication with all the slaves in time when a circular topology is applied (see Figure 607). All the slaves behave like simple shift registers applied at serial chain under common slave select and clock control. All the information is shifted simultaneously around the circle while returning back to the master. Sessions have fixed the length where the number of data frames transacted by the master is equal to the number of slaves. Then when a first data frame is transacted in the chain, the master just sends information dedicated for the last slave node in the chain via the first slave node input while the first information received by the master comes from the last node output at this time. Correspondingly, the lastly transacted data finishing the session is dedicated for the first slave node while its firstly outgoing data just reaches the master input after its circling around the chain passing through all the other slaves during the session. The data format configuration and clock setting has to be the same for all the nodes in the chain at this topology. As the receive and transmit shift registers are separated internally, a trick with intentional underrun has to be applied at the TxFIFO slaves when information is transacted between the receiver and the transmitter by hardware. At this case, the transmission underrun feature is configured at a mode repeating lastly received data frame (UDRCFG[1:0]=01). A session can start optionally with a single data pattern written into the TxFIFO by each slave (usually slave status information is applied) before the session starts. At this case the underrun happens in fact after this first data frame is transacted (underrun detection has to be set at end of data transaction at slaves UDRDET[1:0]=01). To be able to clear the internal underrun condition immediately and restart the session by the TxFIFO content again, the user has to disable and enable the SPI between sessions and fill the TxFIFO by a new single data pattern (to overcome the propagating delay of the clearing raised at case the underrun is cleared in a standard way by the UDRC bit). 2082/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 607. Master and three slaves at circular (daisy chain) topology ZdžƐŚŝĨƚƌĞŐŝƐƚĞƌ ddžƐŚŝĨƚƌĞŐŝƐƚĞƌ ^W/ĐůŽĐŬ ŐĞŶĞƌĂƚŽƌ D/^K D/^K DK^/ DK^/ ^< ^< ^^ ^^ DĂƐƚĞƌ ddžƐŚŝĨƚƌĞŐŝƐƚĞƌ ;ϭͿ ZdžƐŚŝĨƚƌĞŐŝƐƚĞƌ ^ůĂǀĞϭ D/^K DK^/ ddžƐŚŝĨƚƌĞŐŝƐƚĞƌ ;ϭͿ ZdžƐŚŝĨƚƌĞŐŝƐƚĞƌ ^< ^^ ^ůĂǀĞϮ D/^K DK^/ ddžƐŚŝĨƚƌĞŐŝƐƚĞƌ ;ϭͿ ZdžƐŚŝĨƚƌĞŐŝƐƚĞƌ ^< ^^ ^ůĂǀĞϯ 06Y9 1. Underrun feature is used at slaves at this configuration when slaves are able to transmit data received previously into the Rx shift register once their TxFIFOs become empty. DocID029587 Rev 3 2083/3178 2149 Serial peripheral interface (SPI) 50.4.6 RM0433 Multi-master communication Unless the SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time. For this detection, the SS pin is used configured at hardware input mode. The connection of more than two SPI nodes working at this mode is impossible as only one node can apply its output on a common data line at time. When nodes are non active, both stay at slave mode by default. Once one node wants to overtake control on the bus, it switches itself into master mode and applies active level on the slave select input of the other node via the dedicated GPIO pin. After the session is completed, the active slave select signal is released and the node mastering the bus temporary returns back to passive slave mode waiting for next session start. If potentially both nodes raised their mastering request at the same time a bus conflict event appears (see mode fault MODF event). Then the user can apply some simple arbitration process (e.g. to postpone next attempt by predefined different time-outs applied at both nodes). Figure 608. Multi-master application 5[ 7[ VKLIWUHJLVWHU 7[ 5[ VKLIWUHJLVWHU 63,FORFN JHQHUDWRU 0,62 0,62 026, 026, 6&. 6&. *3,2 0DVWHU 6ODYH 66 66 5[ 7[ VKLIWUHJLVWHU *3,2 7[ 5[ VKLIWUHJLVWHU 63,FORFN JHQHUDWRU DĂƐƚĞƌ ;^ůĂǀĞͿ 06Y 9 1. The SS pin is configured at hardware input mode at both nodes. Its active level enable the MISO line output control as passive node is configured as a slave. 50.4.7 Slave select (SS) pin management In slave mode, the SS works as a standard ‘chip select’ input and lets the slave communicate with the master. In master mode, the SS can be used either as an output or an input. As an input it can prevent a multi master bus collision, and as an output it can drive a slave select signal of a single slave. The SS signal can be managed internally (software management of the SS input) or externally when both the SS input and output are associated with the SS pin (hardware SS management). The user can configure which level of this input/output external signal (present on the SS pin) is considered as active one by the SSIOP bit setting. While low level is considered as active internally SSIOP=1 setting can invert this logic for external world. 2084/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) The hardware or software slave select management can be set using the SSM bit in the SPI_CFG2 register: Note: • Software SS management (SSM = 1): in this configuration, slave select information is driven internally by the SSI bit value in the register SPI_CR1. The external SS pin is free for other application uses (as GPIO or other alternate function). • Hardware SS management (SSM = 0): in this case, there are two possible configurations. The configuration used depends on the SS output configuration (SSOE bit in register SPI_CFG2). – SS output enable (SSOE = 1): this configuration is only used when the MCU is set as master. The SS pin is managed by the hardware. a) When SSOM = 0 and SP = 000, the SS signal is driven to the active level as soon as the master transfer starts (CSTART=1) and it is kept active until its EOT flag is set or the transmission is suspended. b) When SP = 001, a pulse is generated as defined by the TI mode. c) When SSOM=1, SP=000 and MIDI>1 the SS is pulsed inactive between data frames, and kept inactive for a number of SPI clock periods defined by the MIDI value decremented by one (1 to 14). – SS output disable (SSM=0, SSOE = 0): a) if the micro-controller is acting as the master on the bus, this configuration allows multi master capability. If the SS pin is pulled into an active level in this mode, the SPI enters master mode fault state and the SPI is device is automatically reconfigured in slave mode (MASTER=0). b) In slave mode, the SS pin works as a standard ‘chip select’ input and the slave is selected while the SS line is at its active level. The purpose of automatic switching into slave mode at mode fault condition is to avoid the possible conflicts on data and clock line. The SPE is not automatically reset, as this would automatically flush both RX and TxFIFOs and current data may be lost. Following the MODF event, the SW must correctly manage the FIFO read/flush and correctly re-program the SPI configuration for taking over the slave role in the system. DocID029587 Rev 3 2085/3178 2149 Serial peripheral interface (SPI) RM0433 Figure 609. Scheme of SS control logic 66,23FRQWURO 66,FRQWURO 660FRQWURO 0DVWHU PRGH 6ODYH PRGH 9GG 2. 1RQDFWLYH 9VV &RQIOLFW $FWLYH 66B,1 66B,1 66 SLQ *3,2 ORJLF 66200,', 066,FRQWURO 66 RXWSXW FRQWURO 66B287 0DVWHUPRGH +:66 PDQDJHPHQW 660 RQO\ 66 RXWSXW ORJLF 662(FRQWURO 66H[WHUQDO ORJLF 66LQWHUQDOORJLF 06Y9 When a hardware output SS control is applied (SSM=0, SSOE=1), by configuration of MIDI[3:0] and MSSI[3:0] bit fields the user can control timing of the SS signal between data frames and insert an extra delay at begin of every transaction (to separate the SS and clock starts). This can be useful when the slave needs to slow down the flow to obtain sufficient room for correct data handling (see Figure 610: Data flow timing control (SSOE=1, SSOM=0, SSM=0) Figure 610. Data flow timing control (SSOE=1, SSOM=0, SSM=0) 66 6&. 026, 0,62 06% 066,> @ /6% W6&. '6,=(> @ 06% 0,',> @ '6,=(> @ 06Y9 1. MSSI[3:0]=0011, MIDI[3:0]=0011 (SCK flow is continuous when MIDI[3;0]=0). 2. CPHA=0, CPOL=0, SSOP=0, LSBFRST=0. Additionally, bit SSOM=1 setting invokes specific mode which interleaves pulses between data frames if there is a sufficient space to provide them (MIDI[3:0] has to be set greater then one SPI period). Some configuration examples are shown at Figure 611: SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). 2086/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 611. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0) ,&3+$ &32/ 6623 /6%)567 0,',> @ 66 6&. 026, ; 06% 0,62 06% ; W 6&. 066,> @ /6% 06% ; /6% ; '6,=(> @ ; 06% 0,',> @ ,,&3+$ &32/ 6623 /6%)567 '6,=(> @ 0,',> @ 66 6&. 026, 06% ; 0,62 ; 06% W 6&. 066,> @ 06% ; /6% ; /6% '6,=(> @ 06% 0,',> @ ,,,&3+$ &32/ 6623 /6%)567 '6,=(> @ 0,',> @ 66 6&. 026, ; 0,62 /6% 06% 06% ; /6% ; W6&. 066,> @ /6% ; '6,=(> @ ; /6% 0,',> @ ,9&3+$ &32/ 6623 /6%)567 '6,=(> @ 0,',> @ 66 6&. 026, 0,62 ; /6% ; 066,> @ 06% /6% W 6&. ; ; /6% 06% '6,=(> @ /6% 0,',> @ '6,=(> @ 06Y9 DocID029587 Rev 3 2087/3178 2149 Serial peripheral interface (SPI) RM0433 1. MSSI[3:0]=0010, MIDI[3:0]=0010. 2. SS interleaves between data when MIDI[3:0]>1. 50.4.8 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format. To be able to communicate together, the master and slave devices must follow the same communication format and be synchronized correctly. Clock phase and polarity controls Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CFG2 register. The CPOL (clock polarity) bit controls the idle state value of the clock when no data are being transferred. This bit affects both master and slave modes. If CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state. If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type. The combination of the CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge. Figure 612, shows an SPI full-duplex transfer with the four combinations of the CPHA and CPOL bits. Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit. The idle state of SCK must correspond to the polarity selected in the SPI_CFG2 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). 2088/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 612. Data clock timing diagram &3+$ &32/ &32/ 026, 06%LW 0,62 06%LW /6%LW /6%LW 166 WRVODYH &DSWXUHVWUREH &3+$ &32/ &32/ 026, 0,62 /6%LW 06%LW 06%LW /6%LW 166 WRVODYH &DSWXUHVWUREH DLH 1. The order of data bits depends on LSBFRST bit setting. Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFRST bit in SPI_CFG2 register. The data frame size is chosen by using the DSIZE[4:0] bits. It can be set from 4-bit up to 32-bit length and the setting applies for both transmission and reception. When the SPI_TXDR/SPI_RXDR registers are accessed, data frames are always right-aligned into either a byte (if the data fit into a byte), a half-word or a word (see Figure 613). If the access is a multiple of the minimum data size needed for a single data frame, 2 or 4 data frames will be packed into the register. During communication, only bits within the data frame are clocked and transferred. DocID029587 Rev 3 2089/3178 2149 Serial peripheral interface (SPI) RM0433 Figure 613. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit '6,=( ELWV GDWDLVULJKWDOLJQHGRQE\WH ([DPSOH '6,=(> @ 7[ ;;;; 5[ ELWV '6,=( ELWV GDWDLVULJKWDOLJQHGRQKDOIZRUG ([DPSOH '6,=(> @ ;; ELWV '6,=( ELWV GDWDLVULJKWDOLJQHGRQZRUG ([DPSOH '6,=(> @ ;;;;; 06Y9 Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced to an 4-bit data frame size. 50.4.9 Configuration of SPI The configuration procedure is almost the same for the master and the slave. For specific mode setups, follow the dedicated chapters. When a standard communication has to be initialized, perform these steps: 7. Write the proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins. 8. Write to the SPI_CFG1 and SPI_CFG2 registers to set up proper values of all not reserved bits and bit fields included there with next exceptions: a) 9. SSOM, SSOE, MBR[2:0], MIDI[3:0] and MSSI[3:0] are required at master mode only, the MSSI bits take effect when SSOE is set, MBR setting is required for slave at TI mode, too b) UDRDET[1:0] and UDRCFG[1:0] are required at slave mode only, c) CRCSIZE[4:0] is required if CRCEN is set, d) CPOL, CPHA, LSBFRST, SSOM, SSOE, SSIOP and SSM are not required at TI mode. e) Once the AFCNTR bit is set at SPI_CFG2 register, all the SPI outputs start to be propagated onto the associated GPIO pins regardless the peripheral enable so any later configurations changes of the SPI_CFG1 and SPI_CFG2 registers can affect level of signals at these pins. f) The I2SMOD bit at SPI_I2SCGFR register has to be kept cleared to prevent any unexpected influence of occasional I2S configuration. Write to the SPI_CR2 register to select length of the transfer, if it is not known TSIZE has to be programmed to zero. 10. Write to SPI_CRCPOLY and into TCRCINI, RCRCINI and CRC33_17 bits at SPI2S_CR1 register to configure the CRC polynomial and CRC calculation if needed. 11. Configure DMA streams dedicated for the SPI Tx and Rx in DMA registers if the DMA streams are used (see chapter Communication using DMA). 12. Program the IOLOCK bit in the SPI_CFG1 register if the configuration protection is required (for safety). 2090/3178 DocID029587 Rev 3 RM0433 50.4.10 Serial peripheral interface (SPI) Procedure for enabling SPI It is recommended to configure and enable the SPI slave before the master sends the clock but there is no impact if the configuration and enabling procedure is done while a traffic is on going on the bus. The data register of the slave transmitter should contain data to be sent before the master starts its clocking.The SCK signal must be settled to idle state level corresponding to the selected polarity before the SPI slave is selected by SS else following transaction may be desynchronized. When the SPI slave is enabled at the hardware SS management mode all the traffics are ignored even in case of the SS is found at active level till the slave detects a start of the SS signal (its transaction from non-active to active level) just synchronizing the slave with the master. That is why the hardware management mode cannot be used when external SS pin is fixed. There is no such protection at the SS software management. The SSI bit should be changed when there is no traffic on the bus and the SCK signal is at idle state level between transfers exclusively at this case. The master at full duplex (or in any transmit-only mode) starts to communicate when the SPI is enabled, the CSTART bit is set and the TxFIFO is not empty, or with the next write to TxFIFO. In any master receive only mode, the master starts to communicate and the clock starts running after the SPI is enabled and the CSTART bit is set. For handling DMA, see Section 50.4.14: Communication using DMA (direct memory addressing). 50.4.11 SPI data transmission and reception procedures RxFIFO and TxFIFO All SPI data transactions pass through the embedded FIFOs organized by bytes (N x 8-bit). The size of the FIFOs (N) is product and the peripheral instance dependent. This enables the SPI to work in a continuous flow, and prevents overruns when the data frame size is short or the interrupt/DMA latency is too long. Each direction has its own FIFO called TxFIFO and RxFIFO, respectively. The handling of FIFOs depends on the data exchange mode (duplex, simplex), the data frame format (number of bits in the frame), the access size performed on the FIFO data registers (8-bit, 16-bit or 32-bit), and how data are organized at packets. A read access to the SPI2S_RXDR register returns the oldest value stored in the RxFIFO that has not been read yet. A write access to the SPI2S_TXDR stores the written data in the TxFIFO at the end of a send queue. A read access to the SPI2S_RXDR register must be managed by the RXP event. This flag is set by hardware when at least one complete data packet (defined as receiver threshold by FTHVL[3:0] bits at the SPI_CFG1 register) is available at the reception FIFO while reception is active. The RXP is cleared as soon as less data are available in the RxFIFO, when reading SPI2S_RXDR by software or by DMA. The RXP triggers an interrupt if the RXPIE bit is set or a/o a DMA request if RXDMAEN is set. Upon setting of the RXP flag, the application software performs the due number of SPI data register reads to download the content of one data packet. Once a complete data packet is downloaded, the application software checks the RXP value to see if other packets are DocID029587 Rev 3 2091/3178 2149 Serial peripheral interface (SPI) RM0433 pending into the receive FIFO and, if so, downloads them packet by packet until the RXP reads 0. RxFIFO can store up to N data frames (for frame size =< 8-bit), N/2 data frames (for 8-bit < frame =< 16-bit), N/3 data frames (for 16-bit < frame =< 24-bit) or N/4 data frames (if data frame >24-bit) where N is the size of the FIFO in bytes. At the end of a reception, it may happen that some data may still be available in the RxFIFO, without reaching the FTHVL level, thus the RXP is not set. In this case, the number of remaining RX data frames in the FIFO will be indicated by RXWNE and RXPLVL fields in the SPI_SR register. It happens when number of the last data received in a transfer cannot fully accomplish the configured packet size in the case transfer size and packet size are not aligned. Nevertheless the application software can still perform the standard number of reads from the RxFIFO used for the previous complete data packets without drawbacks: only the consistent data (completed data frames) will be popped from the RxFIFO while redundant reads (or any uncompleted data) will be reading 0. Thanks to that, the application software can treat all the data in a transfer in the same way and is off-loaded to foresee the reception of the last data in a transfer and from calculating the due number of reads to be popped from RxFIFO. In a similar way, write access of a data frame to be transmitted is managed by the TXP event. This flag is set by hardware when there is enough space for the application software to push at least one complete data packet (defined at FTHVL[3:0] bits at SPI_CFG1 register) into the transmission FIFO while transmission is active. The TXP is cleared as soon as the TxFIFO is filled by software a/o by DMA and space currently available for any next complete data packet is lost. This can lead to oscillations of the TXP signal when data are released out from the TxFIFO while a new packet is stored frame by frame. Any write to the TxFIFO is ignored when there is no sufficient room to store at least a single data frame (TXP event is not respected), when TXTF is set or when the SPI is disabled. The TXP triggers an interrupt if the TXPIE bit is set or a/o a DMA request if TXDMAEN is set. The TXPIE mask is cleared by hardware when the TXTF flag is set. Upon setting of the TXP flag application software performs the due number of SPI data register writes to upload the content of one entire data packet. Once new complete data packet is uploaded, the application software checks the TXP value to see if other packets can be pushed into the TxFIFO and, if so, uploads them packet by packet until TXP reads 0 at the end of any packet load. The number of last data in a transfer can be shorter than the configured packet size in the case when the transfer size and the packet size are not aligned. Nevertheless the application software can still perform the standard number of data register writes used for the previous packets without drawbacks: only the consistent data will be pushed into the TxFIFO while redundant writes will be discarded. Thanks to that, the application software can treat all the data in a transfer in the same way and is off-loaded to foresee the transmission of the last data in a transfer and from calculating the due number of writes to push the last data into TxFIFO. Just for the last data case, the TXP event is asserted by SPI once there is enough space into TxFIFO to store remaining data to complete current transfer. Both TXP and RXP events can be polled or handled by interrupts. The DXP bit can be monitored as a common TXP and RXP event at full duplex mode. Upon setting of the DXP flag the application software performs the due number of writes to the SPI data register to upload the content of one entire data packet for transmission, followed by the same number of reads from the SPI data register to download the content of one data packet. Once one data packet is uploaded and one is downloaded, the application 2092/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) software checks the DXP value to see if other packets can be pushed and popped in sequence and, if so, uploads/downloads them packet by packet until DXP reads 0. The DXP triggers an interrupt if the DXPIE bit is set or a/o a DMA requests if TXDMAEN and RXDMAEN are set. The DXPIE mask is cleared by hardware when the TXTF flag is set. The DXP is useful in Full-Duplex communication in order to optimize performance in data uploading/downloading, and reducing the number of interrupts required to support an SPI transfer thus minimizing the request for CPU bandwidth and system power especially when SPI is operated in Stop mode. Another way to manage the data exchange is to use DMA (see Communication using DMA (direct memory addressing)). If the next data is received when the RxFIFO is full, an overrun event occurs (see description of OVR flag at Section 50.5.2: SPI error flags). An overrun event can be polled or handled by an interrupt. This may happen in slave mode or master mode (full duplex or receive only with MASRX = 0). In master receive only mode, with MASRX = 1, the generated clock stops automatically when the RxFIFO is full, therefore overrun is prevented. Both RxFIFO and TxFIFO content is kept flushed when SPI is disabled (SPE=0). Sequence handling A few data frames can be passed at single sequence to complete a message. The user can handle number of data within a message thanks to values stored into TSIZE and TSER fields. In principle, the transaction of a message starts when the SPI is enabled by setting CSTART bit and finishes when number of required data is transacted. The end of transaction controls the CRC and the hardware SS management when applied. If TSIZE is kept at zero while CSTART is set, an endless transaction is initialized (no data size control is applied). The transaction can be suspended at any time thanks to CSUSP which clears the CSTART bit. In master mode, the user can extend the number of data within the current session. When the number of data programmed into TSIZE is transacted and if TSER contains a non-zero value, the content of TSER is copied into TSIZE, and TSER value is cleared automatically. The transaction is then extended by a number of data corresponding to the value reloaded into TSIZE. The EOT event is not raised in this case as the transaction continues. After the reload operation, the TSERF flag is set and an interrupt is raised if TSERFIE is set. The user can write the next non-zero value into TSER before the next reload occurs, so an unlimited number of data can be transacted while repeating this process. When any data extension is applied, it always starts by aligned data packet. That is why it is suggested to keep number of data to be extended always aligned with packet size else the last data packet just before the extension is applied has to be handled as an incomplete one (see data packing chapter). If overall number of data is not aligned, the user should implement the rest not aligned number of data into TSER just at the last extension cycle and then handle the last incomplete packet of data standardly within EOT event handler. For example, if the user wants to transfer 23 bytes while applies data number extension at configuration of 8-bit data size, data packet set to 4 data and 32-bit access to FIFO is used then whatever next sequence is correct – TSIZE=16 TSER=7; – TSIZE=12 TSER=8; last extensionTSER=3; As the last not aligned MSB byte is ignored just within the last (6th) access of the FIFO. DocID029587 Rev 3 2093/3178 2149 Serial peripheral interface (SPI) RM0433 When a not aligned sequence is applied for data to be extended like at the following cases – TSIZE=15 TSER=8 or – TSIZE=8 TSER=7; last extension TSER=8; The MSB byte is ignored within the 4th access of the FIFO while the other accesses handle always 4 data at the FIFO. When the transmission is enabled, a sequence begins and continues while any data is present in the TxFIFO of the master. The clock signal is provided permanently by the master until TxFIFO becomes empty, then it stops, waiting for additional data. In receive-only modes, half duplex (COMM[1:0]=11, HDDIR=0) or simplex (COMM[1:0]=10) the master starts the sequence when SPI is enabled and transaction is released by setting the CSTART bit. The clock signal is provided by the master and it does not stop until either SPI or receive-only mode is disabled/suspended by the master. The master receives data frames permanently up to this moment. The reception can be suspended either by SW control, writing 1 to the CSUSP bit in the SPI_CR1 register, or automatically when MASRX=1 and RxFIFO becomes full. The reception will be automatically stopped also when the number of frames programmed in TSIZE and TSER fields of the SPI_CR2 register has been completed. In order to disable the master receive only mode, the SPI must be suspended at first. When the SPI is suspended, the current frame is completed, before changing the configuration. Caution: If SPE is written to 0 at master, while reception is ongoing without any suspending, the clock is stopped without completing the current frame, and the RxFIFO is flushed. While the master can provide all the transactions in continuous mode (SCK signal is continuous) it has to respect slave capability to handle data flow and its content at anytime. When necessary, the master must slow down the communication and provide either a slower clock or separate frames or data sessions with sufficient delays by MIDI[3:0] bits setting or provide an initial delay by setting MSSI[1:0] which postpones any transaction start to give slave sufficient room for preparing data. Be aware data from the slave are always transacted and processed by the master even if the slave could not prepare it correctly in time. It is preferable for the slave to use DMA, especially when data frames are short, FIFO is accessed by bytes and the SPI bus rate is high. In order to add some SW control on the SPI communication flow from a slave transmitter node, a specific value written in the SPI_UDRDR (SPI Underrun Data Register) may be used. On slave side, when TxFIFO becomes empty, this value will be sent out automatically as next data and may be interpreted by SW on the master receiver side (either simply dropped or interpreted as a XOFF like command, in order to suspend the master receiver by SW). Each sequence must be enabled by the SS pulse in parallel with the multi slave system to select just one of the slaves for communication. In a single slave system it is not necessary to control the slave with SS, but it is often better to provide the pulse here too, to synchronize the slave with the beginning of each data sequence. The SS can be managed by both software and hardware (Section 50.4.6: Multi-master communication). 2094/3178 DocID029587 Rev 3 RM0433 50.4.12 Serial peripheral interface (SPI) Procedure for disabling the SPI When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. At the master mode, it is important to do this before the system enters a low-power mode when the peripheral clock is stopped. Otherwise, ongoing transactions may be corrupted in this case. In slave mode, the SPI communication can continue when the spi_pclk and spi_ker_ck clocks are stopped, without interruption, until any end of communication or data service request condition will be reached. The spi_pclk can generally be stopped by setting the system into STOP mode. Please refer to the RCC section for further information. The master in full duplex or transmit only mode can finish any transaction when it stops providing data for transmission. In this case, the clock stops after the last data transaction. TXC flag can be polled (or interrupt enabled with EOTIE=1) in order to wait for the last data frame to be sent. When the master is in any receive only mode, in order to stop the peripheral, the SPI communication must be first suspended, by setting CSUSP to 1. The data received but not read remain stored in RxFIFO when the SPI is suspended. When SPI is disabled, RxFIFO is flushed. To prevent losing unread data, the user has to ensure that RxFIFO is empty when disabling the SPI, by reading all remaining data (as indicated by the RXP, RXWNE and RXPLVL fields in the SPI_SR register). The standard disable procedure is based on polling EOT and/or TXC status to check if a transmission session is (fully) completed. This check can be done in specific cases, too, when it is necessary to identify the end of ongoing transactions, for example: • When the SS signal is managed by software and the master has to provide proper end of SS pulse for slave, or • When transaction streams from DMA or FIFO are completed while the last data frame or CRC frame transaction is still ongoing in the peripheral bus. The correct disable procedure in master mode, except when receive only mode is used, is: 1. Wait until TXC=1 and/or EOT=1 (no more data to transmit and last data frame sent). When CRC is used, it is sent automatically after the last data in the block is processed. TXC/EOT is set when CRC frame is completed at this case. When a transmission is suspended the software has to wait till CSTART bit is cleared. 2. Read all RxFIFO data (until RXWNE=0 and RXPLVL=00) 3. Disable the SPI (SPE=0). The correct disable procedure for master receive only modes is: 1. Wait on EOT or break the receive flow by suspending SPI (CSUSP=1) 2. Wait until SUSP=1 (the last data frame is processed) if receive flow is suspended. 3. Read all RxFIFO data (until RXWNE=0 and RXPLVL=00) 4. Disable the SPI (SPE=0). In slave mode, any on going data will be lost when disabling the SPI. DocID029587 Rev 3 2095/3178 2149 Serial peripheral interface (SPI) 50.4.13 RM0433 Data packing From user point of view there are two ways of data packing which can overlay each other: • Type of access when data are written to TxFIFO or read from RxFIFO Multiple data can be pushed or fetched effectively by single access if data size is considerably less than access performed upon SPI2S_TXDR or SPI2S_RXDR registers. • Number of data to be handled during the single software service It is convenient to group data into packets and cumulate the FIFO services overall the data packet content exclusively instead of handling data frame by frame separately. The user can define packets by FIFO threshold settings. Then all the FIFO occupancy events are related to that threshold level while required services are signalized by proper flags with interrupt and/or wake up capabilities. When the data frame size fits into one byte (less than or equal to 8 bits), the data packing is used automatically when any read or write 16-bit or 32-bit access is performed on the SPI2S_RXDR/SPI2S_TXDR register. The multiple data frame pattern is handled in parallel in this case. At first, the SPI operates using the pattern stored in the LSB of the accessed word, then with the other data stored in the MSB. Figure 614 provides an example of data packing mode sequence handling. While DSIZE[3:0] is configured to 4-bit there, two or four data frames are written in the TxFIFO after the single 16-bit or 32-bit access the SPI2S_TXDR register of the transmitter. When the data frame size is between 9-bit and 16-bit, data packing is used automatically when a 32-bit access is done. Least Significant Half-word will be used first. (regardless of the LSBFRST value) This sequence can generate two or four RXP events in the receiver if the RxFIFO threshold is set to 1 frame (and data is read on a frame basis, unpacked), or it can generate a single RXP event if the FTHLV[3:0] field in the SPI_CFG1 register is programmed to a multiple of the frames to be read in a packed mode (16-bit or 32-bit read access). The data are aligned in accordance with Figure 613: Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit. The valid bits are performed on the bus exclusively. Unused bits are not cared at transmitter while padded by zeros at receiver. When short data frames (<8-bit or < 16-bit) are used together with a larger data access mode (16-bit or 32-bit), the FTHVL value must be programmed as a multiple of the number of frames/data access (i.e. multiple of 4 if 32-bit access is used to up to 8-bit frames or multiple of 2 if 16-bit access is used to up to 8-bit frames or 32-bit access to up to 16-bit frames.). The RxFIFO threshold setting must always be higher than the following read access size, as spurious extra data would be read otherwise. The FIFO data access less than the configured data size is forbidden. One complete data frame has to be always accessed at minimum. A specific problem appears if an incomplete data packet is available at FIFO: less than 4x8bit frames or one single 16-bit frame is available. There are two ways of dealing with this problem: 2096/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) A. without using TSIZE field On transmitter side, writing the last data frame of any odd sequence with an 8-bit/16-bit access to SPI2S_TXDR is enough. On receiver side, the remaining data may be read by any access. Any extra data read will be padded with zeros. Polling the RXWNE and RXPLVL may be used to detect when the RX data are available in the RxFIFO. (A time out may be used at system level in order to detect the polling) B. using the TSIZE field On transmitter side, the transaction is stopped by the master when it faces EOT event. In reception, the RXP flag will not be set when EOT is set. In the case when the number of data to be received (TSIZE) is not a multiple of packet size, the number of remaining data is indicated by the RXWNE and RXPLVL fields in the SPI_SR register. The remaining data can be read by any access. Any extra read will be padded by zeros. Figure 614. Packing data in FIFO for transmission and reception 66 7;),)2 [$ 6&. 5;),)2 026, [$ [$ 63, IVP VKLIW 63,6B7;'5 [ [ [ &3+$ &32/ /6%)567 '6,=(> @ 63, IVP VKLIW 63,6B5;'5 5;),)2EHIRUHUHDGDFFHVVIURP63,6B5;'5 [ELW [$[[[ RU [ELW [$[ RU [ELW [$ 7;),)2DIWHUZULWHDFFHVVWR63,6B7;'5 [ELW [$[[[ RU [ELW [$[ RU [ELW [$ 06Y9 1. DSIZE[3:0] is configured to 4-bit, data is right aligned, valid bits are performed only on the bus, their order depends on LSBFRST, content of LSB byte goes first on the bus. 50.4.14 Communication using DMA (direct memory addressing) To operate at its maximum speed and to facilitate the data register read/write process required to avoid overrun, the SPI features a DMA capability, which implements a simple request/acknowledge protocol. A DMA access is requested when the TXDMAEN or RXDMAEN enable bits in the SPI_CFG1 register are set. Separate requests must be issued to the Tx and Rx buffers. • In transmission, a series of DMA requests is triggered each time TXP is set to 1. The DMA then performs series of writes to the SPI2S_TXDR register. • In reception, a series of DMA requests is triggered each time RXP is set to 1. The DMA then performs series of reads from the SPI2S_RXDR register. When EOT is set at the end of transaction and last data packet is incomplete then DMA request is activated automatically in according with RXWNE and RXPLVL[1:0] setting to read rest of data. When the SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel. DocID029587 Rev 3 2097/3178 2149 Serial peripheral interface (SPI) RM0433 If the SPI is programmed in receive only mode, UDR will never be set. If the SPI is programmed in a transmit mode, TXP and UDR can be eventually set at slave side, because transmit data may not be available. In this case, some data will be sent on the TX line according with the UDR management selection. When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA channel. If the SPI is programmed in transmit only mode, RXP and OVR will never be set. If the SPI is programmed in full-duplex mode, RXP and OVR will be eventually be set, because received data are not read. In transmission mode, when the DMA or the user has written all the data to be transmitted (the TXTF flag is set at SPI2C_SR register), the TXC flag can be monitored to ensure that the SPI communication is complete. This is required to avoid corrupting the last transmission before disabling the SPI or before disabling the spi_pclk in master mode. The software must first wait until EOT=1 and/or TXC=1. When starting communication using DMA, to prevent DMA channel management raising error events, these steps must be followed in order: 1. Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CFG1 register, if DMA Rx is used. 2. Enable DMA requests for Tx and Rx in DMA registers, if the DMA is used. 3. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CFG1 register, if DMA Tx is used. 4. Enable the SPI by setting the SPE bit. To close communication it is mandatory to follow these steps in order: 1. Disable DMA request for Tx and Rx in the DMA registers, if the DMA issued. 2. Disable the SPI by following the SPI disable procedure. 3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CFG1 register, if DMA Tx and/or DMA Rx are used. Data packing with DMA If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPI_CFG1 register) the packing mode is enabled/disabled automatically depending on the PSIZE value configured for SPI TX and the SPI RX DMA channel. If the DMA channel PSIZE value is equal to 16-bit or 32-bit and SPI data size is less than or equal to 8-bit, then packing mode is enabled. Similarly, If the DMA channel PSIZE value is equal to 32-bit and SPI data size is less than or equal to 16-bit, then packing mode is enabled.The DMA then automatically manages the write operations to the SPI2S_TXDR register. Regardless data packing mode is used and the number of data to transfer is not a multiple of the DMA data size (16-bit or 32-bit) while the frame size is smaller, DMA completes the transfer automatically in according with the TSIZE field setting. Alternatively, last data frames may be written by software, in the single/unpacked mode. To configure any DMA data access less than the configured data size is forbidden. One complete data frame has to be always accessed at minimum. 2098/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) 50.5 SPI specific modes and control 50.5.1 TI mode By specific setting of the SP[2:0] bit field at the SPI_CFG2 register the SPI can be configured to be compliant with TI protocol. The SCK and SS signals polarity, phase and flow as well as the bits order are fixed so the setting of CPOL, CPHA, LSBFRST, SSOM, SSOE, SSIOP and SSM is not required when the SPI is at TI mode configuration. The SS signal synchronizes the protocol by pulses over the LSB data bit as it is shown at the Figure 615: TI mode transfer. Figure 615. TI mode transfer 66 6&. 026, ; 0,62 ; 06% /6% 06% /6% 06% /6% 06% /6% '6,=(> @ '6,=(> @ 75(/($6( 06Y9 In slave mode, the clock generator is used to define time when the slave output at MISO pin becomes to HiZ when the current transaction finishes. The master baud setting is applied and any baud rate can be used to determine this moment with optimal flexibility. The delay for the MISO signal to become HiZ (TRELEASE) depends on internal re-synchronization, too. It is given by formula: Tbaud Tbaud ------------------ + 2 × Tcom < Trelease < ------------------ + 4 × Tcom 2 2 If the slave detects misplaced SS pulse during data transaction the TIFRE flag is set. 50.5.2 SPI error flags An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled by setting the corresponding Interrupt Enable bit. Overrun flag (OVR) An overrun condition occurs when data are received by a master or slave and the RxFIFO has not enough space to store these received data. This can happen if the software or the DMA did not have enough time to read the previously received data (stored in the RxFIFO). When an overrun condition occurs, the OVR flag is set and the newly received value does not overwrite the previous one in the RxFIFO. The newly received value is discarded and all data transmitted subsequently are lost. OVR flag triggers an interrupt if OVRIE bit is set. Clearing the OVR bit is done by a writing 1 to the OVRC bit in the SPI_IFCR. To prevent any DocID029587 Rev 3 2099/3178 2149 Serial peripheral interface (SPI) RM0433 next overrun event the clearing should be done after RxFIFO is emptied by software reads. At master mode, the user can prevent the RxFIFO overrun by automatic communication suspend (MASRX bit). Underrun flag (UDR) At a slave-transmitting mode, the underrun condition is captured internally by hardware if no data is available for transmission in the slave TxFIFO at the moment specified by UDRDET bits. The UDR flag setting is then propagated into the status register by hardware (see note below). UDR triggers an interrupt if the UDRIE bit is set. Once the underrun is captured next provided data for transmission depends on the UDRCFG bits. The slave can provide out either data stored lastly to its TxFIFO or the data received previously from the master or a constant pattern stored by the user at the UDRDR register. The second configuration can be used at circular topography structure (see Figure 607). Standard transmission is re-enabled once the software clears the UDR flag and this clearing is propagated into SPI Iogic by hardware. The user should write some data into TxFIFO prior clearing UDR flag to prevent any next underrun condition occurrence capture. The data transacted by slave is unpredictable especially when the transaction starts or continues while TxFIFO is empty and underrun condition is either not yet captured or just cleared. Typically, this is the case when UDRDET[1:0]=00 or SPI is just enabled or when a transaction with a defined size just starts. First bits can be corrupted in this case, as well, when slave software writes first data into the empty TxFIFO too close prior the data transaction starts (propagation of the data into TxFIFO takes few APB clock cycles). If the user cannot insure to write data into empty TxFIFO in time the UDRDET[1:0]=00 setting should be avoid. To handle the underrun control feature correctly the user should avoid next critical encroachments especially Note: • Any fill of empty TxFIFO when master starts clocking (at UDRDET[1:0]=00 especially) • Any clear of UDR flag while TxFIFO is empty • Any setting of UDRDET[1:0]=00 together with UDRCFG[1:0]=10 • Any setting of UDRDET[1:0]=10 when underrun should be detected after each data frame while SS signal does not toggle between the frames • Any setting of UDRDET[1:0]=10 while SS is managed by software The hardware propagation of an UDR flag change needs additional traffic on the bus. It always takes 3 SPI clock cycles after the event happen (underrun captured by hardware or the UDR flag cleared by software). Mode fault (MODF) Mode fault occurs when the master device has its internal SS signal (SS pin in SS hardware mode, or SSI bit in SS software mode) pulled low. This automatically affects the SPI interface in the following ways: • The MODF bit is set and an SPI interrupt is generated if the MODFIE bit is set. • The SPE bit is cleared. This blocks all output from the device and disables the SPI interface. • The MASTER bit is cleared, thus forcing the device into slave mode. MODF is cleared by writing 1 to the MODFC bit in the SPI_IFCR. To avoid any multiple slave conflicts in a system comprising several MCUs, the SS pin must be pulled to its non-active level before re-enabling the SPI, by setting the SPE bit. 2100/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) As a security, hardware does not allow the SPE bit to be set while the MODF bit is set. In a slave device the MODF bit cannot be set except as the result of a previous multi master conflict. A correct SW procedure when master overtakes the bus at multi master system should be the following one: • Switch into master mode while SSOE=0 (potential conflict can appear when another master occupies the bus. MODF is raised at this case which prevents any next node switching into master mode) • Put GPIO pin dedicated for another master SS control into active level • Perform data transaction • Put GPIO pin dedicated for another master SS control into non active level • Switch back to slave mode CRC error (CRCE) This flag is used to verify the validity of the value received when the CRCEN bit in the SPI_CFG1 register is set. The CRCE flag in the SPI_SR register is set if the value received in the shift register does not match the receiver SPI_RXCRC value, after the last data is received (as defined by TSIZE). The CRCE flag triggers an interrupt if CRCIE bit is set. Clearing the bit CRCE is done by a writing 1 to the CRCEC bit in the SPI_IFCR. TI mode frame format error (TIFRE) A TI mode frame format error is detected when an SS pulse occurs during an ongoing communication when the SPI is operating in slave mode and configured to conform to the TI mode protocol. When this error occurs, the TIFRE flag is set in the SPI_SR register. The SPI is not disabled when an error occurs, the SS pulse is ignored, and the SPI waits for the next SS pulse before starting a new transfer. The data may be corrupted since the error detection may result in the loss of few data bytes. The TIFRE flag is cleared by writing 1 to the TIFREC bit in the SPI_IFCR. If the TIFREIE bit is set, an interrupt is generated on the SS error detection. As data consistency is no longer guaranteed, communication should be re-initiated by SW between master and slave. 50.5.3 CRC computation Two separate 33-bit or two separate 17-bit CRC calculators are implemented in order to check the reliability of transmitted and received data. The SPI offers any CRC polynomial length from 5 to 33 bits when maximum data size is 32-bit and from 5 to 17 bits for the peripheral instances where maximum data size is limited to 16-bit. The length of the polynomial is defined by the most significant bit of the value stored at the CRCPOLY register. It has to be set greater than data frame length defined at DSIZE field. When maximum data size is applied, the CRC33_17 bit has to be set additionally to define the most significant bit of the polynomial string while keep its size always greater than data. The CRCSIZE field in the SPI_CFG1 then defines how many the most significant bits from CRC calculation registers are transacted and compared as CRC frame. It is defined independently from the data frame length, but it must be either equal or an integer multiple of the data frame size. CRC principle The CRC calculation is enabled by setting the CRCEN bit in the SPI_CFG1 register before the SPI is enabled (SPE = 1). The CRC value is then calculated using the CRC polynomial DocID029587 Rev 3 2101/3178 2149 Serial peripheral interface (SPI) RM0433 defined by the CRCPOLY register and CRC33_17 bit. When SPI is enabled, the CRC polynomial can be changed but only in case when there is no traffic on the bus. The CRC computation is done, bit by bit, on the sampling clock edge defined by the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked automatically at the end of the data block defined by the SPI_CR2 register exclusively. When a mismatch is detected between the CRC calculated internally on the received data and the CRC received from the transmitter, a CRCERR flag is set to indicate a data corruption error. The right procedure for handling the CRC depends on the SPI configuration and the chosen transfer management. CRC transfer management Communication starts and continues normally until the last data frame has to be sent or received in the SPI_DR register. The length of the transfer has to be defined by TSIZE and TSER. When the desired number of data is transacted, the TXCRC will be transmitted and the data received on the line will be compared to the RXCRC value. TSIZE cannot be set to 0xFFFF value if CRC is enabled. A correct way of sending e.g. 65535 data with CRC is to set: – TSIZE= 0xFFFE and TSER=1 when data packet is configured to keep one data respective – TSIZE= 0xFFFC and TSER=3 when data packet keeps 4 data (to ensure the TSIZE value aligned with packet size when its extension is applied). In transmission, the CRC computation is frozen during CRC transaction and the TXCRC will be transmitted, in a frame of length equal to the CRCSIZE field value. In reception, the RXCRC is also frozen when desired number of data is transacted. Information to be compared with the RXCRC register content is then received in a frame of length equal to the CRCSIZE value. Once the CRC frame is completed, an automatic check is performed comparing the received CRC value and the value calculated in the SPIx_RXCRC register. Software has to check the CRCERR flag in the SPI_SR register to determine if the data transfers were corrupted or not. Software clears the CRCERR flag by writing 1 to the CRCERRC. The user takes no care about any flushing redundant CRC information, it is done automatically. Resetting the SPIx_TXCRC and SPIx_RXCRC values The SPI_TXCRC and SPI_RXCRC values are initialized automatically when new data is sampled after a CRC phase. This allows the use of DMA circular mode in order to transfer data without any interruption (several data blocks covered by intermediate CRC checking phases). Initialization patterns for receiver and transmitter can be configured either to zero or to all ones in dependency on setting bits TCRCINI and RCRCINI at SPI2S_CR1 register. The CRC values are reset when the SPI is disabled. 2102/3178 DocID029587 Rev 3 RM0433 50.6 Serial peripheral interface (SPI) Low-power mode management The SPI has advanced low-power mode functions allowing it to transfer properly data between the FIFOs and the serial interface even when the spi_pclk clock is disabled. In master mode the spi_ker_ck kernel clock is needed in order to provide the timings of the serial interface. In slave mode, the spi_ker_ck clock can be removed as well during the transfer of data between the FIFOs and the serial interface. In this mode the clock is provided by the external SPI device. When the spi_pclk clock is gated, (and the spi_ker_ck clock as well if the SPI is in slave), the SPI provides a wakeup event signal (spi_wkup) if a specific action requiring the activation of the spi_pclk clock is needed, such as: • To fill-up the TxFIFO, • To empty the RxFIFO, • Other signaling: end of transfer, errors... The generation of spi_ker_ck and spi_pclk clock are controlled by the RCC block according to register settings and the processors modes. Please refer to the RCC section for details. The application shall acknowledge all pending interrupts events before switching the SPI to low-power mode (i.e. removing spi_pclk). The Figure 616 shows an example of the clock handling when the SPI2S is working in lowpower mode. The example is given for a transmit mode. In master mode the spi_ker_ck clock is required for the timing generation. The Figure 616 shows two kinds of supported scenarios for the handling of the spi_ker_ck kernel clock in slave mode: • In most of the slave modes, the spi_ker_ck kernel clock can be disabled, • In some products, the spi_ker_ck kernel clock activation may follow the system state. DocID029587 Rev 3 2103/3178 2149 Serial peripheral interface (SPI) RM0433 Figure 616. Low-power mode application example 63, &RPPXQLFDWLRQ 7[),)2 OHYHO VSLBZNXS VSLBLW VSLBSFON VSLBNHUBFN 0$67(5PRGH VSLBNHUBFN 6/$9(PRGH VSLBNHUBFN 6/$9(PRGH /HVVWKDQ)7+9/HPSW\ORFDWLRQV $WOHDVW)7+9/HPSW\ORFDWLRQV 06Y9 The figure clearly shows that the spi_pclk must be provided to the SPI2S, when data need to be transferred from the memory to the SPI2S TxFIFO. Here is the description of the most important steps: 2104/3178 • Step 1 The TxFIFO level goes below the programmed threshold, this event (TXP) activates the spi_wkup signal. This signal is generally used to wake-up the system from lowpower mode, and thus to activate the bus clock (spi_pclk). • Step 2 When spi_pclk is activated, the spi_it is also activated, and the product is ready to fillup the TxFIFO either by DMA or by software. Note as well that is some product the system wake-up will automatically enable the spi_ker_ck kernel clock as well. • Step 3 When the amount of empty locations in the TxFIFO is less than FTHVL, then the spi_wkup and spi_it signals are deactivated, but the fill-up of the TxFIFO may continue. Please note that spi_wkup falling edge is aligned with the serial interface clock domain, and the falling edge of the spi_it is aligned with the spi_pclk clock domain. • Step 4 The fill-up of the TxFIFO is completed; the software can switch the system back to lowpower mode until the next spi_wkup occurs. DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) 50.7 SPI wakeup and interrupts Table 390 gives an overview of the SPI events capable to generate interrupt events (spi_it). Some of them feature wake-up from low-power mode capability additionally (spi_wkup). Most of them can be enabled and disabled independently while using specific interrupt enable control bits. Table 390. SPI wakeup and interrupt requests Interrupt event Event flag(1) Enable Control bit Event clear method Interrupt/Wakeup activated spi_it spi_wkup TxFIFO ready to be loaded (space available for one data packet - FIFO threshold) TXP TXPIE TXP cleared by hardware when TxFIFO contains less than FTHVL empty locations YES Data received in RxFIFO (one data packet available - FIFO threshold) RXP RXPIE RXP cleared by hardware when RxFIFO contains less than FTHVL samples YES Both TXP and RXP active DXP DXPIE When TXP or RXP are cleared YES Transmission Transfer Filled TXTF TXTFIE Writing TXTFC to 1 NO Underrun UDR UDRIE Writing UDRC to 1 YES Overrun OVR OVRIE Writing OVRC to 1 YES CRC Error CRCE CRCEIE Writing CRCEC to 1 TI Frame Format Error TIFRE TIFREIE Writing TIFREC to 1 NO Mode Fault MODF MODFIE Writing MODFC to 1 NO Writing EOTC to 1 YES Writing SUSPC to 1 YES TXC cleared by HW when a transmission activity starts on the bus NO End Of Transfer (full transfer sequence completed - based on TSIZE value) Master mode suspended TxFIFO transmission complete (TxFIFO empty) TSER value transferred to TSIZE (new value may be loaded to TSER) EOT SUSP TXC TSERF EOTIE TSERFIE Writing TSERFC to 1 YES YES NO 1. Refer to SPI2S register description for more details about the event flags. DocID029587 Rev 3 2105/3178 2149 Serial peripheral interface (SPI) 50.8 2106/3178 RM0433 I2S main features • Full duplex communication • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler • Data length may be 16, 24 or 32 bits • Channel length can be 16 or 32 in master, any value in slave • Programmable clock polarity • Error flags signaling for improved reliability: Underrun, Overrun and Frame Error • Embedded Rx and TxFIFOs • Supported I2S protocols: – I2S Philips standard – MSB-Justified standard (Left-Justified) – LSB-Justified standard (Right-Justified) – PCM standard (with short and long frame synchronization) • Data ordering programmable (LSb or MSb first) • DMA capability for transmission and reception • Master clock can be output to drive an external audio component. The ratio is fixed at 256 x FWS (where FWS is the audio sampling frequency) DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) 50.9 I2S functional description 50.9.1 I2S general description The block diagram shown on Figure 602 also applies for I2S mode. The SPI/I2S block can work on I2S/PCM mode, when the bit I2SMOD is set to 1. A dedicated register (SPI_I2SCFGR) is available for configuring the dedicated I2S parameters, which include the clock generator, and the serial link interface. The I2S/PCM function uses the clock generator to produce the communication clock when the SPI/I2S is set in master mode. This clock generator is also the source of the master clock output (MCK). Resources such as RxFIFO, TxFIFO, DMA and parts of interrupt signaling are shared with SPI function. The low-power mode function is also available in I2S mode, refer to Section 50.6: Low-power mode management and Section 50.10: I2S wakeup and interrupts. 50.9.2 Pin sharing with SPI function The I2S shares four common pins with the SPI: • SDO: Serial Data Output (mapped on the MOSI pin) to transmit the audio samples in master, and to receive the audio sample in slave. Please refer to Section : Serial Data Line swapping on page 2116. • SDI: Serial Data Input (mapped on the MISO pin) to receive the audio samples in master, and to transmit the audio sample in slave. Please refer to Section : Serial Data Line swapping on page 2116. • WS: Word Select (mapped on the SS pin) is the frame synchronization. It is configured as output in master mode, and as input for slave mode. • CK: Serial Clock (mapped on the SCK pin) is the serial bit clock. It is configured as output in master mode, and as input for slave mode. An additional pin can be used when a master clock output is needed for some external audio devices: • MCK: Master Clock (mapped separately) is used, when the I2S is configured in master mode. The master clock rate is fixed to 256 x FWS, where FWS is the audio sampling frequency. DocID029587 Rev 3 2107/3178 2149 Serial peripheral interface (SPI) 50.9.3 RM0433 Bits and fields usable in I2S/PCM mode When the I2S/PCM mode is selected (I2SMOD = ‘1’), some bit fields are no longer relevant, and must be forced to a specific value in order to guarantee the behavior of the I2S/PCM function. Table 391 shows the list of bits and fields available in the I2S/PCM mode, and indicates which must be forced to a specific value. Table 391. Bit fields usable in PCM/I2S mode Bit fields usable in PCM/I2S Mode Constraints on other bit fields IOLOCK, CSUSP, CSTART Other fields set to their reset values - Set to reset value SPI configuration register 1 (SPI_CFG1) TXDMAEN, RXDMAEN, FTHVL Other fields set to their reset values SPI configuration register 2 (SPI_CFG2) AFCNTR, LSBFRST, IOSWP Register name SPI/I2S control register 1 (SPI2S_CR1) SPI control register 2 (SPI_CR2) Other fields set to their reset values SPI/I2S Interrupt Enable Register (SPI2S_IER) TIFREIE, OVRIE, UDRIE, TXPIE, RXPIE SPI/I2S Status Register (SPI2S_SR) RXWNE, RXPLVL, SUSP, TIFRE, OVR, UDR, TXP, RXP Other flags not relevant SPI/I2S Interrupt/Status Flags Clear Register (SPI2S_IFCR) SUSPC, TIFREC, OVRC, UDRC Other fields set to their reset values SPI/I2S Transmit Data Register (SPI2S_TXDR) The complete register - SPI/I2S Receive Data Register (SPI2S_RXDR) The complete register - SPI Polynomial Register (SPI_CRCPOLY) - SPI Transmitter CRC Register (SPI_TXCRC) - SPI Receiver CRC Register (SPI_RXCRC) - SPI Underrun Data Register (SPI_UDRDR) - SPI/I2S configuration register (SPI_I2SCGFR) 2108/3178 The complete register DocID029587 Rev 3 Set to reset value - RM0433 50.9.4 Serial peripheral interface (SPI) Slave and master modes The SPI/I2S block supports master and slave mode for both I2S and PCM protocols. In master mode, both CK, WS and MCK signals are set to output. In slave mode, both CK and WS signals are set to input. The signal MCK is not used in slave mode. In order to improve the robustness of the SPI/I2S block in slave mode, the peripheral resynchronizes each reception and transmission on WS signal. This means that: • In I2S Philips standard, the shift-in or shift-out of each data is triggered one bit clock after each transition of WS. • In I2S MSB justified standard, the shift-in or shift-out of each data is triggered as soon as a transition of WS is detected. • In PCM standard, the shift-in or shift-out of each data is triggered one bit clock after the rising edge WS. Note: This re-synchronization mechanism is not available for the I2S LSB justified standard. Note: Note as well that there is no need to provide a kernel clock when the SPI/I2S is configured in slave mode. 50.9.5 Supported audio protocols The I2S/PCM interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPIx_I2SCFGR register. In the I2S protocol, the audio data are time-multiplexed on two channels: the left channel and the right channel. The WS signal is used to indicate which channel shall be considered as the left, and which one is the right. In I2S master mode, four frames formats are supported: • 16-bit data packed in a 16-bit channel • 16-bit data packed in a 32-bit channel • 24-bit data packed in a 32-bit channel • 32-bit data packed in a 32-bit channel In PCM master mode, three frames formats are supported: • 16-bit data packed in a 16-bit channel • 16-bit data packed in a 32-bit channel • 24-bit data packed in a 32-bit channel DocID029587 Rev 3 2109/3178 2149 Serial peripheral interface (SPI) RM0433 The figure hereafter shows the main definition used in this section: data length, channel length and frame length. Figure 617. Waveform examples 0&. )0&. 6DPSOLQJUDWHÆ)0&. [):6 :6 &. &.32/ 6' ,QRU2XW 6HULDOGDWD 6HULDOGDWD ,6 6HULDO 'DWDOHQJWK &KDQQHOOHQJWK )UDPHOHQJWK 6DPSOLQJUDWHÆ)0&. [):6 :6 &. &.32/ 6' ,QRU2XW 3&0 6HULDOGDWD 6HULDOGDWD 6HULDO 'DWDOHQJWK &KDQQHOOHQJWK )UDPHOHQJWK ,6B'HILQLWLRQ 06Y9 2110/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) I2S Philips standard The I2S Philips standard is selected by setting I2SSTD to 0b00. This standard is supported in master and slave mode. In this standard, the WS signal toggles one CK clock cycle before the first bit (MSb in I2S Philips standard) is available. A falling edge transition of WS indicates that the next data transfered is the left channel, and a rising edge transition indicates that the next data transfered is the right channel. Figure 618. Master I2S Philips protocol waveforms (16/32-bit full accuracy) 'DWD VWDEOH :6 :6,19 /HIWFKDQQHO &DQEHRUELWV 06E /6E 06E 6'2RU6', /6%)567 /6E /6E 06E &. &.32/ 5LJKWFKDQQHO &DQEHRUELWV 5LJKWFKDQQHOELWV 06Y9 CKPOL is set to 0 in order to match the I2S Philips protocol. See Selection of the CK sampling edge for information concerning the handling of WS signal. Figure 618 shows an example of waveform generated by the SPI/I2S in the case where the channel length is equal to the data length. More precisely, this is true when CHLEN = 0 and DATLEN = 0b00 or when CHLEN = 1 and DATLEN = 0b10. See Control of the WS Inversion for information concerning the handling of WS signal. Figure 619. I2S Philips standard waveforms 'DWDVWDEOH :6 ,2 :6,19 &. ,2 &.32/ 5LJKWFKDQQHOELWV 06E 06E /HIWFKDQQHO ELWFKDQQHO PDVWHU RWKHUOHQJWK VODYH UHPDLQLQJELWV IRUFHGWR QRWWDNHQLQWR DFFRXQW 06E 06E QRWWDNHQLQWR DFFRXQW /6E UHPDLQLQJELWV IRUFHGWR /6E /6E RUELWOHQJWK /6E 06E 06E 6', /6E 6'2 /6E /6%)567 RUELWOHQJWK 5LJKWFKDQQHO ELWFKDQQHO PDVWHU RWKHUOHQJWK VODYH 06Y9 In the case where the channel length is bigger than the data length, the remaining bits are forced to zero when the SPI/I2S is configured in transmit mode. This is applicable for both master and slave mode. DocID029587 Rev 3 2111/3178 2149 Serial peripheral interface (SPI) RM0433 MSB justified standard For this standard, the WS signal toggles when the first data bit, is provided. The data transfered represents the left channel if WS is high, and the right channel if WS is low. Figure 620. Master MSB Justified 16-bit or 32-bit full-accuracy length 'DWDVWDEOH :6 2 :6,19 &. 2 /HIWFKDQQHO 06E /6E 06E /6E /6%)567 06E 6'2RU6', /6E &.32/ 5LJKWFKDQQHO RUELWV RUELWV 5LJKWFKDQQHOELWV 06Y9 CKPOL is set to 0 in order to match the I2S MSB justified protocol. See Selection of the CK sampling edge for information concerning the handling of WS signal. See Control of the WS Inversion for information concerning the handling of WS signal. Figure 621. Master MSB justified 16 or 24-bit data length 'DWDVWDEOH :6 2 :6,19 &. 2 &.32/ /HIWFKDQQHO ELWFKDQQHO 5LJKWFKDQQHOELWV /6E UHPDLQLQJELWV IRUFHGWR 06E /6E QRWWDNHQLQWR DFFRXQW 06E QRWWDNHQLQWR DFFRXQW 06E /6E 06E RUELWOHQJWK /6E 06E 06E 6', /6E 6'2 /6E /6%)567 RUELWOHQJWK 5LJKWFKDQQHO ELWFKDQQHO 06Y 9 In the case where the channel length is bigger than the data length, the remaining bits are forced to zero when the SPI/I2S is configured in master transmit mode. In slave transmit the remaining bits are forced to the value of the first bit of the next data to be generated in order to avoid timing issues (see Figure 622). 2112/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 622. Slave MSB justified 'DWDVWDEOH :6 :6,19 &. &.32/ /HIWFKDQQHO /6E QRWWDNHQLQWR DFFRXQW QRWWDNHQLQWR DFFRXQW 06E 06E UHPDLQLQJELWVIRUFHGWR 06ERIQH[WOHIWFKDQQHO /6E 06E RUELWOHQJWK 06E /6E 6', UHPDLQLQJELWVIRUFHGWR 06ERIQH[WULJKWFKDQQHO /6E 06E 6'2 06E /6%)567 RUELWOHQJWK 5LJKWFKDQQHO 5LJKWFKDQQHOELWV 06Y9 LSB justified standard This standard is similar to the MSB justified standard in master mode (no difference for the 16 and 32-bit full-accuracy frame formats). The LSB justified 16 or 32-bit full-accuracy format give similar waveforms than MSB justified mode (see Figure 620) because the channel and data have the same length. In the LSB justified format, only 16 and 32-bit channel length are supported in master and slave mode. This is due to the fact that it is not possible to transfer properly the data if the channel length is not known by transmitter and receiver side. Figure 623. LSB justified 16 or 24-bit data length 'DWDVWDEOH :6 :6,19 &. &.32/ /HIWFKDQQHO ELWFKDQQHO 5LJKWFKDQQHOELWV QRWWDNHQLQWR DFFRXQW /6E /6E IRUFHGWR 06E RUELWOHQJWK 06E /6E 06E QRWWDNHQLQWR DFFRXQW /6E IRUFHGWR 06E 6', /6E 6'2 /6E RUELWOHQJWK /6%)567 Note: 5LJKWFKDQQHO ELWFKDQQHO 06Y9 CKPOL is set to 0 in order to match the I2S LSB justified protocol. See Selection of the CK sampling edge for information concerning the handling of WS signal. See Control of the WS Inversion for information concerning the handling of WS signal. DocID029587 Rev 3 2113/3178 2149 Serial peripheral interface (SPI) RM0433 PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPI_I2SCFGR register. Note: The difference between the PCM long and short frame, is just the width of the frame synchronization: for both protocols, the active edge of the frame is generated (or is expected for the Slave mode) one CK clock cycle before the first bit. Figure 624. Master PCM when the frame length is equal the data length 'DWDVWDEOH :6 2 3&06<1& :6,19 ELWV :6 2 3&06<1& :6,19 &. &.32/ /6E /6E 06E ELWOHQJWK 06E 6'2RU6', /6%)567 /6E ELWOHQJWK 06Y9 For long frame synchronization, the WS signal assertion time is fixed to 13 bits in master mode. A data size of 16 or 24 bits can be used when the channel length is set to 32 bits. For short frame synchronization, the WS synchronization signal is only one cycle long. See Control of the WS Inversion for information concerning the handling of WS signal. Figure 625. Master PCM standard waveforms (16 or 24-bit data length) 'DWDVWDEOH :6 2 3&06<1& :6,19 ELWV :6 2 3&06<1& :6,19 &. 2 /6E UHPDLQLQJELWV IRUFHGWR 06E /6E 'RQ¶WFDUH 06E /6E 6', RUELWOHQJWK /6E 6'2 06E RUELWOHQJWK 06E /6%)567 &.32/ ELWIUDPH UHPDLQLQJELWV IRUFHGWR 'RQ¶WFDUH ELWIUDPH 06Y9 If the PCM protocol is used in slave mode, frame lengths can be different from 16 or 32 bits. As shown in Figure 626, in slave mode various pulse widths of WS can be accepted as the start of frame is detected by a rising edge of WS. The only constraint is that the WS must go back to its inactive state for at least one CK cycle. 2114/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 626. Slave PCM waveforms &.F\FOH PLQ 'DWDVWDEOH :6 , 3&06<1& 7KHIDOOLQJHGJHFDQRFFXULQWRWKLVDUHD 7KHIDOOLQJHGJHFDQRFFXULQWRWKLVDUHD &. , &.32/ 06E /6E /6E 'RQ¶WFDUH UHPDLQLQJELWV IRUFHGWR 06E /6E UHPDLQLQJELWV IRUFHGWR /6E 6', 06E 6'2 RUELWOHQJWK 06E /6%)567 RUELWOHQJWK 'RQ¶WFDUH 06Y9 CKPOL is set to 0 in order to match the PCM protocol. See Selection of the CK sampling edge for information concerning the handling of WS signal. 50.9.6 Additional Serial Interface Flexibility Variable frame length in slave In slave mode, channel lengths different from 16 or 32 bits can be accepted, as long as the channel length is bigger than the data length. This is true for all protocols except for I2S LSB justified protocol. Data ordering For all data formats and communication standards, it is possible to select the data ordering (MSb or LSb first) thanks to the bit LSBFRST located into SPI configuration register 2 (SPI_CFG2). Selection of the CK sampling edge The CKPOL bit located into SPI/I2S configuration register (SPI_I2SCGFR) allows the user to choose the sampling edge polarity of the CK for slave and master modes, for all protocols. • When CKPOL = 0, serial data SDO and WS (when master) are changed on the falling edge of CK and the serial data SDI and WS (when slave) are read on the rising edge. • When CKPOL = 1, serial data SDO and WS (when master) are changed on the rising edge of CK and the serial data SDI and WS (when slave) are read on the falling edge. Control of the WS Inversion It is possible to invert the default WS signal polarity for master and slave modes, for all protocols, by setting WSINV to 1. By default the WS polarity is the following: • In I2S Philips Standard, WS is LOW for left channel, and HIGH for right channel • In MSB/LSB justified mode, WS is HIGH for left channel, and LOW for right channel • In PCM mode, the start of frame is indicated by a rising edge of WS. DocID029587 Rev 3 2115/3178 2149 Serial peripheral interface (SPI) RM0433 When WSINV is set to 1, the WS polarity is inverted, then: • In I2S Philips Standard, WS is HIGH for left channel, and LOW for right channel • In MSB/LSB justified mode, WS is LOW for left channel, and HIGH for right channel • In PCM mode, the start of frame is indicated by a falling edge of WS. WSINV is located into SPI/I2S configuration register (SPI_I2SCGFR). Control of the IOs The SPI/I2S block allows the settling of the WS and CK signals to their inactive state before enabling the SPI/I2S thanks to the AFCNTR bit of SPI configuration register 2 (SPI_CFG2). This can be done by programming CKPOL and WSINV using the following sequence: Assuming that AFCNTR is initially set to 0 – Set I2SMOD = 1, (In order to inform the hardware that the CK and WS polarity is controlled via CKPOL and WSINV). – Set bits CKPOL and WSINV to the wanted value. – Set AFCNTR = 1. Then the inactive level of CK and WS IOs is set according to CKPOL and WSINV values, even if the SPI/I2S is not yet enabled. – Then performs the activation sequence of the I2S/PCM Table 392 shows the level of WS and CK signals, when the AFCNTR bit is set to 1, and before the SPI/I2S block is enabled (i.e. inactive level). Note that the level of WS depends also on the protocol selected. Table 392. WS and CK level before SPI/I2S is enabled when AFCNTR = 1 WSINV 0 1 Note: I2SSTD WS level before SPI/I2S is enabled CKPOL CK level before SPI/I2S is enabled I2S Std (00) → High 0 → Low Others → Low 1 → High I2S Std (00) → Low Others → High The bit AFCNTR shall not be set to 1, when the SPI2S is in slave mode. Serial Data Line swapping The SPI/I2S offers the possibility to swap the function of SDI and SDO lines thanks to IOSWP bit located into SPI configuration register 2 (SPI_CFG2). Table 393 gives details on this feature. Table 393. Serial data line swapping Configuration Master/slave RX 2116/3178 IOSWP SDI direction SDO direction 0 IN - 1 - IN DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Table 393. Serial data line swapping (continued) Configuration IOSWP SDI direction SDO direction 0 - OUT 1 OUT - 0 IN OUT 1 OUT IN Master/slave TX Master/slave Full-duplex For simplification, the waveforms shown in the I2S functional description section have been done with IOSWP = 0. Start-up sequence When the bit SPE is set to 0, the user is not allowed to read and write into the SPI2S_RXDR and SPI2S_TXDR registers, but the access to other registers is allowed. When the application wants to use the SPI/I2S block the user has to proceed as follow: 1. Insure that the SPE is set to 0, otherwise write SPE to 0. 2. Program all the configuration and control registers according to the wanted configuration. Refer to Section 50.9.16 for detailed programming examples. 3. Set the SPE bit to 1, in order to activate the SPI/I2S block. When this bit is set, the serial interface is still disabled, but the DMA and interrupt services are working, allowing for example, the data transfer into the TxFIFO. 4. Set bit CSTART to 1, in order to activate the serial interface. As shown in Figure 627, in I2S Philips standard master TX, the generation of the WS, MCK and CK signals is started as soon as the bit CSTART is set to 1 and the TxFIFO is not empty. Note that the bit clock CK is activated 4 rising edges before the falling edge of WS in order to insure that the external slave device can detect properly WS transition. Other standards behave similarly. Figure 627. Start-up sequence, I2S Philips standard, master 0&. 2 :6 2 :6,19 &. 2 / 5 06E /6E 6<1&B'/< 06E 6'2 /6%)567 /6E &.32/ 06E 50.9.7 &67$57 63( $FFHVVHVWR 63,6EORFN 63,6 'DWDWUDQVIHUWR FRQILJXUDWLRQ WKH7;B),)2 (QDEOLQJRIWKH VHULDOLQWHUIDFH 5LJKWFKDQQHOELWV 06Y9 1. In this figure, the MCK is enabled before setting the bit SPE to 1. See MCK Generation for more information. 2. Note that the level of WS and CK signals will be controlled by the SPI/I2S block during the configuration phase as soon as the AFCNTR bit is set to 1 DocID029587 Rev 3 2117/3178 2149 Serial peripheral interface (SPI) Note: RM0433 Due to clock domain resynchronization, the CSTART bit is taken into account by the hardware after about 3 periods of CK clock (SYNC_DLY1). In slave mode, once the bit CSTART is set to 1, the data transfer starts when the start-offrame condition is met: • For I2S Philips standard, the start-of-frame condition is a falling edge of WS signal. The transmission/reception will start one bit clock later. If WSINV = 1, then the start-of-frame condition is a rising edge. • For other protocols, the start-of-frame condition is a rising edge of WS signal. The transmission/reception will start at rising edge of WS for MSB aligned protocol.The transmission/reception will start one bit clock later for PCM protocol. If WSINV = 1, then the start-of-frame condition is a falling edge. Figure 628 shows an example of start-up sequence in I2S Philips standard, slave mode. Figure 628. Start-up sequence, I2S Philips standard, slave 6HDUFKLQJIRUWKHVWDUWRIIUDPH :6 , :6,19 &. , 6'2 6', /B,1 5B,1 /B287 5B287 /B287 /B,1 5B,1 /B,1 &67$57 63( 6<1&B'/< 1RWVWRUHGLQWRWKH5;),)2 6WDUWRIIUDPHFRQGLWLRQIRXQGWKHUHFHSWLRQ DQGWUDQVPLVVLRQRIGDWDFDQVWDUW 06Y9 Note: Due to clock domain resynchronization, the CSTART bit is taken into account by the hardware after 2 periods of CK clock (SYNC_DLY). 50.9.8 Stop sequence The application can stop the I2S/PCM transfers by setting the SPE bit to 0. In that case the communication is stopped immediately, without waiting for the end of the current frame. In master mode it is also possible to stop the I2S/PCM transfers at the end of the current frame. For that purpose, the user has to set the bit CSUSP to 1, and polls the CSTART bit until it goes to 0. The CSTART bit will go to 0 when the current stereo (if an I2S mode was selected) or mono sample are completely shifted in or out. Then the SPE bit can be set to 0. The Figure 629 shows an example of stop sequence in the case of master mode. The CSUSP bit is set to 1, during the transmission of left sample, the transfer continue until the last bit of the right sample is transferred. Then CSTART and CSUSP go back to 0, CK and WS signals go back to their inactive state, and the user can set SPE to 0. 2118/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Figure 629. Stop sequence, I2S Philips standard, master :6 2 / :6,19 5 &. 2 /6E 06E /6E 06E 6'2 /6%)567 /6E 06E &.32/ &6863 &67$57 63( 5LJKWFKDQQHOELWV 06Y 9 Note: In slave mode, the stop sequence is only controlled by the SPE bit. 50.9.9 Clock generator When the I2S or PCM is configured in master mode, the user needs to program the clock generator in order to produce the Frame Synchronization (WS), the bit clock (CK) and the master clock (MCK) at the desired frequency. If the I2S or PCM is used in slave mode, there is no need to configure the clock generator. Figure 630. I2S clock generator architecture &/.*(1 VSLBNHUBFN 0&. ELWOLQHDUGLYLGHU UHVKDSLQJVWDJH · ,602' ,6',9> @ 2'' · &. &+/(1 0&.2( 06Y 9 The frequency generated on MCK, CK and WS depends mainly on I2SDIV, ODD, CHLEN and MCKOE. The bit MCKOE indicates if a master clock need to be generated or not. The master clock has a frequency 256 times higher than the frame synchronization. This master clock is often required to provide a reference clock to external audio codecs. Note: In master mode, there is no specific constraints on the ratio between the bus clock rate (Fpclk) and the bit clock (FCK). The bus clock frequency must be high enough in order to support the data throughput. DocID029587 Rev 3 2119/3178 2149 Serial peripheral interface (SPI) RM0433 When the master clock is generated (MCKOE = 1), the frequency of the frame synchronization is given by the following formula in I2S mode: F i2s_clk F WS = ----------------------------------------------------------------------------256 × {( 2 × I2SDIV ) + ODD } and by this formula in PCM mode: F i2s_clk F WS = ----------------------------------------------------------------------------128 × {( 2 × I2SDIV ) + ODD } In addition, the frequency of the MCK (FMCK) is given by the formula: F i2s_clk F MCK = ----------------------------------------------------------{( 2 × I2SDIV ) + ODD } When the master clock is disabled (MCKOE = 0), the frequency of the frame synchronization is given by the following formula in I2S mode: F i2s_clk F WS = --------------------------------------------------------------------------------------------------------------------32 × ( CHLEN + 1 ) × {( 2 × I2SDIV ) + ODD } And by this formula in PCM mode: F i2s_clk F WS = --------------------------------------------------------------------------------------------------------------------16 × ( CHLEN + 1 ) × {( 2 × I2SDIV ) + ODD } Where FWS is the frequency of the frame synchronization, and Fi2s_clk is the frequency of the kernel clock provided to the SPI/I2S block. Note: CHLEN and ODD can be either 0 or 1. I2SDIV can take any values from 0 to 255 when ODD = 0, but when ODD = 1, the value I2SDIV = 1 is not allowed. When I2SDIV = 0, then {(2 x I2SDIV) + ODD} is forced to 1. Note: When {(2 x I2SDIV) + ODD} is odd, the duty cycle of MCK or the CK signals will not be 50%. Care must be taken when odd ratio is used: it can impact margin on setup and hold time. For example if {(2 x I2SDIV) + ODD} = 5, then the duty cycle can be 40%. Table 394 provides examples of clock generator programming for I2S modes. MCK Generation The master clock MCK can be generated regardless to the SPE bit. The MCK generating is controlled by the following bits: 2120/3178 – I2SMOD must equal to 1, – I2SCFG must select a master mode, – MCKOE must be set to 1 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Table 394. CLKGEN programming examples for usual I2S frequencies 50.9.10 i2s_clk (MHz) Channel length (bits) I2SDIV ODD 12.288 16 12 0 16 12.288 32 6 0 16 12.288 16 6 0 32 12.288 32 3 0 32 49.152 16 16 0 49.152 32 8 0 49.152 16 8 0 96 49.152 32 4 0 96 49.152 16 4 0 192 49.152 32 2 0 192 4.096 16 or 32 0 - 24.576 16 or 32 3 0 49.152 16 or 32 3 0 12.288 16 or 32 0 - 49.152 16 or 32 2 0 61.44 16 or 32 2 1 98.304 16 or 32 2 0 96 196.608 16 or 32 2 0 192 MCK No Sampling rate: FWS (kHz) 48 48 16 32 Yes 48 Internal FIFOs The I2S interface can use a dedicated FIFO for the RX and the TX path. The samples to transmit can be written into the TxFIFO via the SPI2S_TXDR register. The reading of RxFIFO is performed via the SPI2S_RXDR register. Data alignment and ordering It is possible to select the data alignment into the SPI2S_RXDR and SPI2S_TXDR registers thanks to the DATFMT bit. Note as well that the format of the data located into the SPI2S_RXDR or SPI2S_TXDR depends as well on the way those registers are accessed via the APB bus. Figure 631 shows the allowed settings between APB access sizes, DATFMT and DATLEN. Note: Caution shall be taken when the APB access size is 32 bits, and DATLEN = 0. For read operation the RxFIFO must contain at least two data, otherwise the read data will be invalid. In the same way, for write operation, the TxFIFO must have at least two empty locations, otherwise a data can be lost. DocID029587 Rev 3 2121/3178 2149 Serial peripheral interface (SPI) RM0433 Figure 631. Data Format $3%$FFHVV 6L]H 63,B5;'563,B7;'5 '$7)07 '$7/(1 63,B5;'563,B7;'5 '$7)07 ELWV E ELWV ELWV E ELWV YDOLGVDPSOH1 YDOLGVDPSOH1 YDOLGVDPSOH1 YDOLGVDPSOH1 E ELWV ]HURV ELWV ELWV E ELWV YDOLGVDPSOH YDOLGVDPSOH YDOLGVDPSOH YDOLGVDPSOH YDOLGVDPSOH ]HURV YDOLGVDPSOH 06Y 9 1. In I2S mode, the sample N represents the left sample, and the sample N+1 is the right sample. It is possible to generate an interrupt or a DMA request according to a programmable FIFO threshold levels. The FIFO threshold is common to RX and TxFIFOs can be adjusted via FTHVL. In I2S mode, the left and right audio samples are interleaved into the FIFOs. It means that for transmit operations, the user has to start to fill-up the TxFIFO with a left sample, followed by a right sample, and so on. For receive mode, the first data read from the RxFIFO is supposed to represent a left channel, the next one will be a right channel, and so on. Note that the read and write pointers of the FIFOs are reset when the bit SPE is set to 0. Please refer to Section 50.9.11 and Section 50.9.15 for additional information. FIFO size optimization The basic element of the FIFO is the byte. This allows an optimization of the FIFO locations. For example when the data size is fixed to 24 bits, each audio sample will take 3 basic FIFO elements. For example, a FIFO with 16 basic elements can have a depth of: 50.9.11 – 8 samples, if the DATLEN = 0 (16 bits), – 5 samples, if the DATLEN = 1 (24 bits), – 4 samples, if the DATLEN = 2 (32 bits). FIFOs status flags Two status flags are provided for the application to fully monitor the state of the I2S interface. Both flags can generate an interrupt request. The receive interrupt is generated if RXPIE bit is enabled, the transmit interrupt is generated if TXPIE bit is enabled. Those bits are located into the SPI_IER register. TxFIFO threshold reached (TXP) When set, this flag indicates that the TxFIFO contains at least FTHVL empty locations. thus FTHVL new data to be transmitted can be written into SPI2S_TXDR. The TXP flag is reset when the amount of empty locations is lower than FTHVL. Note that TXP = 1, when the I2S is disabled (SPE bit is reset). 2122/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) RxFIFO threshold reached (RXP) When set, this flag indicates that there is at least FTHVL valid data into the RxFIFO, thus the user can read those data via SPI2S_RXDR. It is reset when the RxFIFO contains less than FTHVL data. See Section 50.10 for additional information on interrupt function in I2S mode. 50.9.12 Handling of underrun situation In transmit mode, the UDR flag is set when a new data needs to be loaded into the shift register while the TxFIFO is already empty. In such a situation at least a data will be lost. In I2S mode, there is a hardware mechanism in order to prevent misalignment situation (left and right channel swapped). As shown in the following figure, when an underrun occurs, the peripheral re-plays the last valid data on left and right channels as long as conditions of restart are not met. The transmission will restart: – When there is enough data into the TxFIFO, and – When the UDR flag is cleared by the software, Then the next data transmitted will be: – A right channel if the underrun occurred when a right channel data needed to be transmitted, or – A left channel if the underrun occurred when a left channel data needed to be transmitted. Figure 632. Handling of underrun situation GPDBUHT GPDBFOU 7;),)2 / 5 / / 5 / (PSW\ / 5 / / / 5 / 5 5 / 5 / / 5 / 5 5 / 5 / / 5 / 5 5 / 5 / ; 6' ; :6 / 5 / 5 / 5 / 5 / 5 &. 8'5IODJ ,QYDOLGIUDPH XQGHUUXQGHWHFWHGGXULQJ WUDQVPLVVLRQRIULJKWFKDQQHO /DVWYDOLGGDWD UHSHDWHG $FNQRZOHGJHG E\6: 7KHUHDUHGDWDLQWRWKH7;),)2EXW WKHUHVWDUWZLOORFFXURQ QH[WULJKWFKDQQHO 06Y 9 The UDR flag can trigger an interrupt if the UDRIE bit in the SPI_IER register is set. The UDR bit is cleared by writing UDRC bit of SPI_IFCR register to 1. When the block is configured in PCM mode, this re-alignment mechanism is not activated. Note: An underrun situation can occur in master or slave mode. In master mode, when an underrun occurs, the WS, CK and MCK signal are not gated. Due to resynchronization, any change on the UDR flag will be taken into account by the hardware after at least 2 periods of CK clock. DocID029587 Rev 3 2123/3178 2149 Serial peripheral interface (SPI) 50.9.13 RM0433 Handling of overrun situation The OVR flag is set when received data need to written into the RxFIFO, while the RxFIFO is already full. As a result, some incoming data are lost. In I2S mode, there is a hardware mechanism in order to prevent misalignment situation (left and right channel swapped). As shown in the following figure, when an overrun occurs, the peripheral stops writing data into the RxFIFO as long as conditions of restart are not met. When there is enough room into the RxFIFO, and the OVR flag is cleared, the block will start by writing next the right channel into the RxFIFO if the overrun occurred when a right channel data was received or by writing the next left channel if the overrun occurred when a left channel data was received. Figure 633. Handling of overrun situation GPDBUHT GPDBFOU / 5 / )XOO / 5 / 5 :6 6' / 5 / 5 / 5 / / 5 / / 5 / 5 ; / 5 ; 5; ),)2 5 / 5 / 5 / 5 &. 295IODJ RYHUUXQGHWHFWHGGXULQJ UHFHSWLRQRIOHIWFKDQQHO /LVORVWGXHWR5;),)2IXOO 5LVORVWEHFDXVHWKH,3VKDOOUHVWDUWWKH UHFHSWLRQRQOHIWFKDQQHOWRDYRLGPLVDOLJQPHQWV $FNQRZOHGJHG E\6: 7KHUHFHSWLRQUHVWDUWSURSHUO\RQWKH QH[WOHIWFKDQQHO 06Y 9 An interrupt may be generated if the OVRIE bit is set in the SPI_IER register. The OVR bit is cleared by writing OVRC bit of SPI_IFCR register to 1. When the block is configured in PCM mode, this re-alignment mechanism is not activated Note: An overrun situation can occur in master or slave mode. In master mode, when an overrun occurs, the WS, CK and MCK signal are not gated. 50.9.14 Frame error detection When configured in slave mode, the SPI/I2S block detects two kinds of frame errors: • A frame synchronization received while the shift-in or shift-out of the previous data is not completed (early frame error). This mode is selected with FIXCH = 0. • A frame synchronization occurring at an unexpected position. This mode is selected with FIXCH = 1. In slave mode, if the frame length provided by the external master device is different from 32 or 64 bits, the user has to set FIXCH to 0. As the SPI/I2S synchronize each transfer with the WS there is no misalignment risk, but in a noisy environment, if a glitch occurs in the CK signal, a sample may be affected and the application will not be aware of this. If the frame length provided by the external master device is equal to 32 or 64 bits, then the user can set FIXCH to 1 and adjust accordingly CHLEN. As the SPI/I2S synchronize each transfer with the WS there is still no misalignment risk, and if the amount of bit clock 2124/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) between each channel boundary is different from CHLEN, the frame error flag (TIFRE) will be set to 1. Figure 634 shows an example of frame error detection. The SPI/I2S block is in slave mode and the amount of bit clock periods for left channel are not enough to shift-in or shift-out the data. The figure shows that the on-going transfer is interrupted and the next one is started in order to remain aligned to the WS signal. Figure 634. Frame error detection, with FIXCH=0 :6 , / 5 / 5 5 5 5 5 / / / 5 6' ,2 / / &. , 7,)5( IODJ $FNQRZOHGJHG E\6: 7KHOHIWFKDQQHOLVQRWFRPSOHWHO\VKLIWHG LQRURXWZKLOHLWLVUHTXHVWHGWRVKLIWLQ RURXWWKHULJKWFKDQQHOqHUURU 06Y 9 An interrupt can be generated if the TIFREIE bit is set. The frame error flag (TIFRE) is cleared by writing the TIFREC bit of the SPI_IFCR register to 1. It is possible to extend the coverage of the frame error flag by setting the bit FIXCH to 1. When this bit is set to 1, then the SPI/I2S is expecting fixed channel lengths in slave mode. This means that the expected channel length can be 16 or 32 bits, according to CHLEN. As shown in Figure 635, in this mode the SPI/I2S block is able to detect if the WS signal is changing at the expected moment (too early or too late). Note: Figure 634 and Figure 635 show the mechanism for the slave transmit mode, but this is also true for slave receive and slave full-duplex. Figure 635. Frame error detection, with FIXCH=1 :6 , $FNQRZOHGJHG E\6: 7,)5( IODJ (UURU WKH:6VLJQDOLVFKDQJLQJDIWHU FORFNSHULRGVLQVWHDGRI 1RWHWKDWWKHULJKWVDPSOHLVSURSHUO\ V\QFKURQL]HGZLWK:6 / / 5 5 5 5 / / 5 / / 6' 2 &. , $FNQRZOHGJHG E\6: (UURU WKH:6VLJQDOLVFKDQJLQJDIWHU FORFNSHULRGVLQVWHDGRI 1RWHWKDWWKHOHIWVDPSOHLVSURSHUO\ V\QFKURQL]HGZLWK:6 06Y 9 The frame error detection can be generally due to noisy environment disturbing the good reception of WS or CK signals. Note: The SPI/I2S is not able to recover properly if an overrun and an early frame occur within the same frame. In this case the user has to disable and re-enable the SPI/I2S. DocID029587 Rev 3 2125/3178 2149 Serial peripheral interface (SPI) 50.9.15 RM0433 DMA Interface The I2S/PCM mode shares the same DMA requests lines than the SPI function. There is a separated DMA channel for TX and RX paths. Each DMA channel can be enabled via RXDMAEN and TXDMAEN bits of SPI_CFG1 register. In receive mode, the DMA interface is working as follow: 1. The hardware evaluates the RxFIFO level, 2. If the RxFIFO contains at least FTHVL samples, then FTHVL DMA requests are generated, – 3. When the FTHVL DMA requests are completed, the hardware loops to step 1 If the RxFIFO contains less than FTHVL samples, no DMA request is generated, and the hardware loop to step 1 In transmit mode, the DMA interface is working as follow: 1. The hardware evaluates the TxFIFO level, 2. If the TxFIFO contains at least FTHVL empty locations, then FTHVL DMA requests are generated, – 3. 2126/3178 When the FTHVL DMA requests are completed, the hardware loops to step 1 If the TxFIFO contains less than FTHVL empty locations, no DMA request is generated, and the hardware loop to step 1 DocID029587 Rev 3 RM0433 50.9.16 Serial peripheral interface (SPI) Programing examples Master I2S Philips standard, transmit This example shows how to program the interface for supporting the Philips I2S standard in master transmit mode, with a sampling rate of 48 kHz, using the master clock. The assumption taken is that SPI/I2S is receiving a kernel clock (i2s_clk) of 61.44 MHz from the clock controller of the circuit. Start Procedure 1. Enable the bus interface clock (pclk or hclk), release the reset signal if needed in order to be able to program the SPI/I2S block. 2. Insure that the SPI/I2S block receives properly a kernel frequency (at 61.44 MHz in this example). 3. Insure that SPE is set to 0. 4. Program the clock generator in order to provide the MCK clock and to have a frame synchronization rate at exactly 48 kHz. So I2SDIV = 2, ODD = 1, and MCKOE = 1. 5. Program the serial interface protocol: CKPOL = 0, WSINV = 0, LSBFRST = 0, CHLEN = 1 (32 bits per channel) DATLEN = 1 (24 bits), I2SSTD = 0 (Philips Standard), I2SCFG = 2 (master transmit), I2SMOD = 1, for I2S/PCM mode. The register SPI_I2SCFGR must be updated before going to next steps. 6. Adjust the FIFO threshold, by setting the wanted value into FTHVL. For example if a threshold of 2 audio samples is required, FTHVL = 1. 7. Clear all status flag registers. 8. Enable the flags who shall generate an interrupt such as UDRIE. Note that TIFRE is not meaningful in master mode. 9. If the data transfer uses DMA: – Program the DMA peripheral, – Initialize the memory buffer with valid audio samples, – Enable the DMA channel, 10. If the data transfer will be done via interrupt, then the user has to enable the interrupt by setting the TXPIE bit to 1. 11. Set SPE to 1, as soon as this bit is set to one the following actions may happen: – If the interrupt generation is enabled, the SPI/I2S will generate an interrupt request allowing the interrupt handler to fill-up the TxFIFO. – If the DMA transfer are enabled (TXDMAEN = 1), the SPI/I2S will generate DMA requests in order to fill-up the TxFIFO 12. Finally, the user has to insure that the TxFIFO is not empty before enabling the serial interface. This is important in order to avoid an underrun condition when the interface will be enabled. Then the SPI/I2S block can be enabled by setting the bit CSTART to 1. CSTART bit is located into SPI_CR1 register. Stop Procedure in master mode 1. Set the bit CSUSP to 1, in order to stop on-going transfers 2. Check the value of CSTART bit until it goes to 0 3. Stop DMA peripheral, bus clock... 4. Set bit SPE to 0 in order to disable the SPI/I2S block DocID029587 Rev 3 2127/3178 2149 Serial peripheral interface (SPI) RM0433 Master I2S MSB Aligned, full-duplex This example shows how to program the interface for supporting the I2S MSB aligned protocol in master full-duplex mode, with a sampling rate of 48 kHz, without using the master clock. We took the assumption that the SPI/I2S is receiving a kernel clock (i2s_clk) of 12.288 MHz from the clock controller of the circuit. Procedure 1. Enable the bus interface clock (pclk or hclk), release the reset signal if needed in order to be able to program the SPI/I2S block. 2. Insure that the SPI/I2S block receives properly a kernel frequency (at 12.288 MHz in this example). 3. Insure that SPE is set to 0. 4. Program the clock generator in order to provide the MCK clock, and to have a frame synchronization rate at exactly 48 kHz. So I2SDIV = 2, ODD = 0, and MCKOE = 0. 5. Program the serial interface protocol: CKPOL = 0, WSINV = 0, LSBFRST = 0, CHLEN = 1 (32 bits per channel) DATLEN = 1 (24 bits), I2SSTD = 1 (MSB Justified), I2SCFG = 5 (master Full-duplex), I2SMOD = 1, for I2S/PCM mode. The register SPI_I2SCFGR must be updated before going to next steps. 6. Adjust the FIFO threshold, by setting the wanted value into FTHVL. For example if a threshold of 2 audio samples is required, FTHVL = 1. 7. Clear all status flag registers. 8. Enable the flags who shall generate an interrupt such as UDRIE. Note that TIFRE is not meaningful in master mode. 9. If the data transfer uses DMA: – Program the DMA peripheral: two channels, one for RX and one for TX – Initialize the memory buffer with valid audio samples for TX path – Enable the DMA channels, – In the SPI/I2S block, enable the DMA by setting the TXDMAEN and RXDMAEN bits to 1. As soon as these bits are set to 1, the SPI/I2S start to fill-up the TxFIFO by sending DMA requests 10. If the data transfer will be done via interrupt, then the user has to enable the interrupt by setting the TXPIE and RXPIE bits to 1. 11. Set SPE to 1, as soon as this bit is set to one the following actions may happen: – If the interrupt generation is enabled, the SPI/I2S will generate an interrupt request allowing the interrupt handler to fill-up the TxFIFO. – If the DMA transfer are enabled, the SPI/I2S will generate DMA requests in order to fill-up the TxFIFO 12. Finally, the user has to insure that the TxFIFO is not empty before enabling the serial interface. This is important in order to avoid an underrun condition when the interface will be enabled. Then the SPI/I2S block can be enabled by setting the bit CSTART to 1. CSTART bit is located into SPI_CR1 register. Refer to Stop Procedure in master mode for details on the stop sequence. 2128/3178 DocID029587 Rev 3 RM0433 50.9.17 Serial peripheral interface (SPI) Slave I2S Philips standard, receive This example shows how to program the interface for supporting the I2S Philips standard protocol in slave receiver mode, with a sampling rate of 48 kHz. Note that in slave mode the SPI/I2S block cannot control the sample rate of the received samples. In this example we took the assumption that the external master device is delivering an I2S frame structure with a channel length of 24 bits. So we cannot use the capability offered for frame error detection when FIXCH is set to 1. Procedure 1. Enable the bus interface clock (pclk or hclk), release the reset signal if needed in order to be able to program the SPI/I2S block. 2. Insure that SPE is set to 0. 3. Program the serial interface protocol: CKPOL = 0, WSINV = 0, LSBFRST = 0, FIXCH = 0 (because channel length is different from 16 and 32 bits), DATLEN = 0 (16 bits), I2SSTD = 0 (Philips protocol), I2SCFG = 1 (slave RX), I2SMOD = 1, for I2S mode. The register SPI_I2SCFGR must be properly programmed before going to next steps. 4. Adjust the FIFO threshold, by setting the wanted value into FTHVL. For example if a threshold of 2 audio samples is required, FTHVL = 1. 5. Clear all status flag registers. 6. Enable the flags who shall generate an interrupt such as UDRIE and TIFRE. 7. If the data transfer uses DMA: – Program the DMA peripheral: one RX channel – Enable the DMA channel, – In the SPI/I2S block, enable the DMA by setting the RXDMAEN bit to 1. 8. If the data transfer will be done via interrupt, then the user has to enable the interrupt by setting the RXPIE bit to 1. 9. Set SPE to 1. 10. Finally the user can set the bit CSTART to 1 in order to enable the serial interface. The SPI/I2S will start to store data into the RxFIFO on the next occurrence of left data transmitted by the external master device. Stop Procedure in slave mode 1. Set bit SPE to 0 in order to disable the SPI/I2S block 2. Stop DMA peripheral, bus clock... DocID029587 Rev 3 2129/3178 2149 Serial peripheral interface (SPI) 50.10 RM0433 I2S wakeup and interrupts In PCM/I2S mode an interrupt (spi_it) or a wakeup event signal (spi_wkup) can be generated according to the events described in the Table 395. Interrupt events can be enabled and disabled separately. Table 395. I2S interrupt requests Interrupt event Event flag Enable control bit Event clear method Interrupt/Wakeup activated spi_it TxFIFO threshold reached TXP TXPIE TXP flag is cleared when the TxFIFO contains less than FTHVL empty locations RxFIFO threshold reached RXP RXPIE RXP flag is cleared when the RxFIFO contains less than FTHVL samples Overrun error OVR OVRIE OVR is cleared by writing OVRC to 1 Underrun error UDR UDRIE UDR is cleared by writing UDRC to 1 TIFRE TIFREIE Frame error flag 2130/3178 TIFRE is cleared by writing TIFREC to 1 DocID029587 Rev 3 spi_wkup YES YES NO RM0433 Serial peripheral interface (SPI) 50.11 SPI/I2S registers 50.11.1 SPI/I2S control register 1 (SPI2S_CR1) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IOLOCK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. SPE rs TCRCINI RCRCINI CRC33_17 rw rw rw SSI rw HDDIR CSUSP CSTART MASRX rw w rs rw rw Bits 31:17 Reserved Bit 16 IOLOCK: Locking the AF configuration of associated IOs This bit is set by software and cleared by hardware on next device reset 0: AF configuration is not locked 1: AF configuration is locked When this bit is set, SPI_CFG2 register content cannot be modified any more. This bit should be configured when the SPI is disabled. When SPE=1, it is write protected. Bit 15 TCRCI: CRC calculation initialization pattern control for transmitter 0: All zero pattern is applied 1: All ones pattern is applied Bit 14 RCRCI: CRC calculation initialization pattern control for receiver 0: All zero pattern is applied 1: All ones pattern is applied Bit 13 CRC33_17: 32-bit CRC polynomial configuration 0: Full size (33-bit or 17-bit) CRC polynomial is not used 1: Full size (33-bit or 17-bit) CRC polynomial is used Bit 12 SSI: Internal SS signal input level This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input and the I/O value of the SS pin is ignored. Bit 11 HDDIR: Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. 0: SPI is Receiver 1: SPI is transmitter Bit 10 CSUSP: Master SUSPend request This bit reads as zero. In master mode, when this bit is set by software, CSTART bit will be reset at the end of the current frame and SPI communication will be suspended. The user has to check SUSP flag to check end of the frame transaction. The master mode communication must be suspended (using this bit or keeping TXDR empty) before disabling the SPI or going to low-power mode. DocID029587 Rev 3 2131/3178 2149 Serial peripheral interface (SPI) RM0433 Bit 9 CSTART: Master transfer start This bit is set by software to start an SPI transfer in master mode. It is cleared by hardware when End Of Transfer (EOT) flag is set or when an CSUSPend request is accepted. 0: Master transfer is at idle 1: Master transfer is on-going or temporary suspended by automatic suspend In SPI mode, CSTART can be set only when SPE=1 and MASTER=1. In SPI mode, In case of master transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. In I2S/PCM mode, CSTART can be set when SPE = 1. Bit 8 MASRX: Master automatic SUSP in Receive mode This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. 0: SPI flow/clock generation is continuous, regardless of overrun condition. (data will be lost) 1: SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. SUSP flag will be set when SPI communication is suspended. When SPI communication is suspended to prevent overrun condition it could happen that few bits of next frame are already clocked out due to internal synchronization delay. Once the RxFIFO is read the communication resumes and continues by subsequent bits transaction without any next constrain. For the same reason, the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles should always produce interval at length of 8 SPI clock periods at minimum. Bits 7:1 Reserved Bit 0 SPE: Serial Peripheral Enable This bit is set by and cleared by software. 0: Serial peripheral disabled. 1: Serial peripheral enabled When SPE=1, SPI data transfer is enabled, Configuration registers and IOLOCK bit in SPI_CR1 are write protected. They can be changed only when SPE=0. When SPI=0 any SPI operation is stopped and disabled, internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. SPE cannot be set when MODF error flag is active. 50.11.2 SPI control register 2 (SPI_CR2) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 TSER[15:0] rs 15 14 13 12 11 10 9 8 7 TSIZE[15:0] rw 2132/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Bits 31:16 TSER[15:0]: Number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted This register can be set by software when its content is cleared only. It is cleared by hardware once TSIZE reload is done. TSER value has to be programmed in advance before CTSIZE counter reaches zero otherwise the reload is not taken into account and traffic will terminate with normal EOT event. Bits 15:0 TSIZE[15:0]: Number of data at current transfer These bits are changed by software. The value should not be changed while CSTART bit is set. Endless transaction is initialized when CSTART is set while zero value is stored at TSIZE. TSIZE cannot be set to 0xFFFF value when CRC is enabled. 50.11.3 SPI configuration register 1 (SPI_CFG1) Address offset: 0x08 Reset value: 0x0007 0007 Content of this register is write protected when SPI is enabled 31 30 29 Res 28 MBR[2:0] 27 26 25 24 23 22 21 Res Res Res Res Res CRCEN Res 11 10 9 8 7 rw 15 14 13 TXDMA RXDMA EN EN Res 20 19 UDRDET[1:0] UDRCFG[1:0] 6 17 16 1 0 CRCSIZE[4:0] rw 12 18 rw 5 4 3 2 FTHLV[3:0] DSIZE[4:0] rw rw Bit 31 Reserved Bits 30:28 MBR [2:0]: Master baud rate 000: SPI master clock/2 001: SPI master clock/4 010: SPI master clock/8 011: SPI master clock/16 100: SPI master clock/32 101: SPI master clock/64 110: SPI master clock/128 111: SPI master clock/256 Bits 27:23 Reserved Bit 22 CRCEN: Hardware CRC computation enable 0: CRC calculation disabled 1: CRC calculation Enabled Bit 21 Reserved DocID029587 Rev 3 2133/3178 2149 Serial peripheral interface (SPI) RM0433 Bits 20:16 CRCSIZE [4:0]: Length of CRC frame to be transacted and compared Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. 00000: Not used 00001: Not used 00010: Not used 00011: 4-bits 00100: 5-bits 00101: 6-bits 00110: 7-bits 00111: 8-bits ..... 11101: 30-bits 11110: 31-bits 11111: 32-bits The value must be equal or multiply of DSIZE length Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. Bit 15 TXDMAEN: Tx DMA stream enable 0: Tx DMA disabled 1: Tx DMA enabled Bit 14 RXDMAEN: Rx DMA stream enable 0: Rx-DMA disabled 1: Rx-DMA enabled Bit 13 Reserved Bits 12:11 UDRDET [1:0]: Detection of underrun condition at slave transmitter 00: Underrun is detected at begin of data frame (no protection of 1-st bit) 01: Underrun is detected at end of last data frame 10: Underrun is detected by begin of active SS signal 11: Reserved The user can define here when and how the underrun condition is detected at slave receiver 2134/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Bits 10:9 UDRCFG [1:0]: Behavior of slave transmitter at underrun condition 00: Slave sends a constant pattern defined by the user at SPI_UDRDR register 01: Slave repeats lastly received data frame from master 10: Slave repeats its lastly transmitted data frame 11: Reserved While TxFIFO is empty shift register for transmission keeps value of SPI_UDRDR register. This register can be either locked to send value defined by the user or refreshed automatically by lastly transacted frame received from master or updated by data stored lastly at slave TxFIFO (by write to TXDR). Bits 8:5 FTHVL [3:0]: FIFO threshold level Defines number of data frames at single data packet. Size of the packet should not exceed 1/2 of FIFO space. 0000: 1-data 0001: 2-data 0010: 3-data 0011: 4-data 0100: 5-data 0101: 6-data 0110: 7-data 0111: 8-data 1000: 9-data 1001: 10-data 1010: 11-data 1011: 12-data 1100: 13-data 1101: 14-data 1110: 15-data 1111: 16-data SPI interface is more efficient if configured packet sizes are aligned with data register access parallelism: – If SPI data register is accessed as a 16-bit register and DSIZE<=8bit, better to select FTHVL=2, 4, 6 etc, – If SPI data register is accessed as a 32-bit register and DSIZE>8bit, better to select FTHVL=2, 4, 6 etc, while if DSIZE<=8bit, better to select FTHVL=4, 8, 12 etc Bits 4:0 DSIZE [4:0]: Number of bits in at single SPI data frame 00000: Not used 00001: Not used 00010: Not used 00011: 4-bits 00100: 5-bits 00101: 6-bits 00110: 7-bits 00111: 8-bits ..... 11101: 30-bits 11110: 31-bits 11111: 32-bits Note: The most significant bit at DSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. DocID029587 Rev 3 2135/3178 2149 Serial peripheral interface (SPI) 50.11.4 RM0433 SPI configuration register 2 (SPI_CFG2) Address offset: 0x0C Reset value: 0x0000 0000 Content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 31 30 29 28 AFCNTR SSOM SSOE SSIOP 27 26 25 24 Res SSM CPOL CPHA 23 22 21 LSBFRST MASTER rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 IOSWP Res Res Res Res Res Res Res rw 20 19 SP[2:0] rw 5 4 rw 17 COMM[1:0] 16 Res rw 3 MIDI [3:0] rw 18 2 1 0 MSSI [3:0] rw rw rw rw rw rw Bit 31 AFCNTR: Alternate function GPIOs control This bit is taken into account when SPE=0 only 0: The peripheral takes no control of GPIOs while it is disabled 1: The peripheral keeps always control of all associated GPIOs When SPI master has to be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. This bit should be never used at slave mode as any slave transmitter must not force its MISO output once the SPI is disabled. Note: This bit can be also used in PCM and I2S modes. Bit 30 SSOM: SS output management in master mode This bit is used in master mode when SSOE is enabled. It allows to configure SS output between two consecutive data transfers. 0: SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag 1: SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1 Bit 29 SSOE: SS output enable This bit is taken into account at master mode only 0: SS output is disabled and the SPI can work in multi-master configuration 1: SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer in according with SSOM, MIDI, MSSI, SSIOP bits setting Bit 28 SSIOP: SS input/output polarity 0: low level is active for SS signal 1: high level is active for SS signal Bit 27 Reserved Bit 26 SSM: Software management of SS signal input 0: SS input value is determined by the SS PAD 1: SS input value is determined by the SSI bit SS signal input has to be managed by software (SSM=1, SSI=1) when SS output mode is enabled (SSOE=1) at master mode. Bit 25 CPOL: Clock polarity 0: SCK signal is at 0 when idle 1: SCK signal is at 1 when idle 2136/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Bit 24 CPHA: Clock phase 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge Bit 23 LSBFRST: Data frame format 0: MSB transmitted first 1: LSB transmitted first Note: This bit can be also used in PCM and I2S modes. Bit 22 MASTER: SPI Master 0: SPI Slave 1: SPI Master Bits 21:19 SP[2:0]: Serial Protocol 000: SPI Motorola 001: SPI TI others: Reserved, must not be used Bits 18:17 COMM: SPI Communication Mode 00: Full-duplex 01: Simplex transmitter 10: Simplex receiver 11: Half-duplex Bit 16 Reserved Bit 15 IOSWP: Swap functionality of MISO and MOSI pins 0: no swap 1: MOSI and MISO are swapped When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. Note that this bit can be also used in PCM and I2S modes. Bits 14:8 Reserved Bits 7:4 MIDI [3:0]: Master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in master mode. 0000: no delay 0001: 1 clock cycle period delay ... 1111: 15 clock cycle periods delay This feature is not supported in TI mode. Bits 3:0 MSSI [3:0]: Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS and first data transaction start in master mode when SSOE is enabled. 0000: no extra delay 0001: 1 clock cycle period delay added ... 1111: 15 clock cycle periods delay added This feature is not supported in TI mode. DocID029587 Rev 3 2137/3178 2149 Serial peripheral interface (SPI) 50.11.5 RM0433 SPI/I2S Interrupt Enable Register (SPI2S_IER) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. TSERFIE MODFIE TIFREIE CRCEIE OVRIE rw rw rw rw rw UDRIE TXTFIE EOTIE rw rw Bits 31:11 Reserved Bit 10 TSERFIE: Additional number of transactions reload interrupt enable 0: TSERF interrupt disabled 1: TSERF interrupt enabled Bit 9 MODFIE: Mode Fault interrupt enable 0: MODF interrupt disabled 1: MODF interrupt enabled Bit 8 TIFREIE: TIFRE interrupt enable 0: TIFRE interrupt disabled 1: TIFRE interrupt enabled Bit 7 CRCIE: CRC Interrupt enable 0: CRC interrupt disabled 1: CRC interrupt enabled Bit 6 OVRIE: OVR interrupt enable 0: OVR interrupt disabled 1: OVR interrupt enabled Bit 5 UDRIE: UDR interrupt enable 0: UDR interrupt disabled 1: UDR interrupt enabled Bit 4 TXTFIE: TXTFIE interrupt enable 0: TXTF interrupt disabled 1: TXTF interrupt enabled Bit 3 EOTIE: EOT, SUSP and TXC interrupt enable 0: EOT/SUSP/TXC interrupt disabled 1: EOT/SUSP/TXC interrupt enabled 2138/3178 DocID029587 Rev 3 rw DPXPIE TXPIE RXPIE rs rs rw RM0433 Serial peripheral interface (SPI) Bit 2 DXPIE: DXP interrupt enabled DXPIE is set by software and cleared by TXTF flag set event. 0: DXP interrupt disabled 1: DXP interrupt enabled Bit 1 TXPIE: TXP interrupt enable TXPIE is set by software and cleared by TXTF flag set event. 0: TXP interrupt disabled 1: TXP interrupt enabled Bit 0 RXPIE: RXP Interrupt Enable 0: RXP interrupt disabled 1: RXP interrupt enabled 50.11.6 SPI/I2S Status Register (SPI2S_SR) Address offset: 0x14 Reset value: 0x0000 1002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CTSIZE[15:0] r 15 RXWNE r 14 13 RXPLVL[1:0] r r 12 11 10 9 8 7 6 5 4 3 2 1 0 TXC SUSP TSERF MODF TIFRE CRCE OVR UDR TXTF EOT DPXP TXP RXP r r r r r r r r r r r r r Bits 31:16 CTSIZE[15:0]: Number of data frames remaining in current TSIZE session The value is not quite reliable when traffic is ongoing on bus Bit 15 RXWNE: RxFIFO Word Not Empty RxFIFO contains more than one 32-bit data 0: Less than 32-bit data frame available in RxFIFO 1: At least one 32-bit data is available in the RxFIFO Bits 14:13 RXPLVL[1:0]: RxFIFO Packing LeVeL Number of packed frames available in the last 32-bit word of the RxFIFO. This number of frames will be read from the RxFIFO when RXWNE=0. When frame size is smaller than or equal to 8-bit 00: The number of frames in RxFIFO is 0 or a multiple of 4. 01: 1 frame available when RXWNE=0 10: 2 frames available when RXWNE=0 11: 3 frames available when RXWNE=0 When frame size is smaller than or equal to 16-bit, but larger than 8-bit, RXPLV[1:0] can take the values 0 or 1. 00: The number of frames in RxFIFO is 0 or a multiple of 2. 01: The number of frame in RxFIFO is odd. One 16-bit data is available when RXWNE=0 Other values forbidden. When frame size is greater than 16-bit, these bits read as 00. 00: Other values forbidden. DocID029587 Rev 3 2139/3178 2149 Serial peripheral interface (SPI) RM0433 Bit 12 TXC: TxFIFO transmission complete This flag is changed by hardware. When TSIZE=0 the TXC raises each time the TxFIFO becomes empty and there is no activity on the bus. If TSIZE <>0 the TXC raises at the end of transfer no matter on TxFIFO occupancy. When this flag is set, master transmission is completed. The flag is not reliable to consider end of master reception.When CRC mode is enabled, TXC will be set only after the CRC transmission. TXC generates an interrupt when EOTIE is set. 0: Current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going (including CRC). 1: Last TxFIFO or CRC frame transmission completed Bit 11 SUSP: SUSPend In Master mode, SUSP is set by hardware when a CSUSP request is done, as soon as the current frame is completed or at master automatic suspend receive mode (MASRX bit is set at SPI2S_CR1 register) on RxFIFO full condition. SUSP generates an interrupt when EOTIE is set. This bit is cleared by write 1 to SUSPC bit at SPI2S_IFCR 0: SPI not suspended (master mode active or other mode). 1: Master mode SUSPended (Current Frame completed) Bit 10 TSERF: Additional number of SPI data to be transacted was reload This bit is cleared by write 1 to TSERFC bit at SPI2S_IFCR or by writing the TSER[15:0] (SPI_CR2) register 0: No acceptation 1: Additional number of data accepted, current transaction continues Bit 9 MODF: Mode Fault 0: No mode fault 1: Mode fault detected This bit is cleared by write 1 to MODFC bit at SPI2S_IFCR Bit 8 TIFRE: TI frame format error 0: No TI Frame Error 1: TI Frame Error detected This bit is cleared by write 1 to TIFREC bit at SPI2S_IFCR Bit 7 CRCE: CRC Error 0: No CRC error 1: CRC error detected This bit is cleared by write 1 to CRCEC bit at SPI2S_IFCR Bit 6 OVR: Overrun 0: No Overrun 1: Overrun detected This bit is cleared by write 1 to OVRC bit at SPI2S_IFCR Bit 5 UDR: Underrun at slave transmission mode 0: No Underrun 1: Underrun detected This bit is cleared by write 1 to UDRC bit at SPI2S_IFCR Note: UDR flag applies to Slave mode only 2140/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Bit 4 TXTF: Transmission Transfer Filled 0: Upload of TxFIFO is on-going or not started 1: TxFIFO upload is finished TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. This bit is cleared by software write 1 to TXTFC bit at SPI2S_IFCR TXTF flag triggers an interrupt if TXTFIE bit is set. TXTF setting clears the TXIE and DPXIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts. Bit 3 EOT: End Of Transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared by software write 1 to EOTC bit at SPI2S_IFCR. EOT flag triggers an interrupt if EOTIE bit is set. If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. 0: Transfer is on-going or not started 1: Transfer complete In master, EOT event terminates the data transaction and handles SS output optionally. In both master and slave, the event handles CRC transaction. Bit 2 DXP: Duplex Packet 0: TxFIFO is Full and/or RxFIFO is Empty 1: Both TxFIFO has space for write and RxFIFO contains for read a single packet at least DXP flag is set when both TXP and RXP flags are set. Bit 1 TXP: Tx-Packet space available 0: There is not enough space to locate next data packet at TxFIFO 1: TxFIFO has enough free location to host 1 data packet TXP flag is changed by hardware. It monitors overall space currently available at TxFIFO if SPI is enabled. It has to be checked once a complete data packet is stored at TxFIFO. Bit 0 RXP: Rx-Packet available 0: RxFIFO is empty or a not complete data packet is received 1: RxFIFO contains at least 1 data packet RXP flag is changed by hardware. It monitors number of overall data currently available at RxFIFO if SPI is enabled. It has to be checked once a data packet is completely read out from RxFIFO. DocID029587 Rev 3 2141/3178 2149 Serial peripheral interface (SPI) 50.11.7 RM0433 SPI/I2S Interrupt/Status Flags Clear Register (SPI2S_IFCR) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res UDRC TXTFC EOTC Res Res Res w w w SUSPC TSERFC MODFC TIFREC CRCEC OVRC w w w w w w Bits 31:12 Reserved, must be kept at reset value. Bit 11 SUSPC: SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI2S_SR register Bit 10 TSERFC: TSERFC flag clear Writing a 1 into this bit clears TSERF flag in the SPI2S_SR register Note: TSERF is also reset by writing the TSER[15:0] (SPI_CR2) register Bit 9 MODFC: Mode Fault flag clear Writing a 1 into this bit clears MODF flag in the SPI2S_SR register Bit 8 TIFREC: TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI2S_SR register Bit 7 CRCEC: CRC Error flag clear Writing a 1 into this bit clears CRCE flag in the SPI2S_SR register Bit 6 OVRC: Overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI2S_SR register Bit 5 UDRC: Underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI2S_SR register Bit 4 TXTFC: Transmission Transfer Filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI2S_SR register Bit 3 EOTC: End Of Transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI2S_SR register Bits 2:0 Reserved, must be kept at reset value. 2142/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) 50.11.8 SPI/I2S Transmit Data Register (SPI2S_TXDR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 TXDR[31:16] w 15 14 13 12 11 10 9 8 7 TXDR[15:0] w Bits 31:0 TXDR[31:0]: Transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. 50.11.9 SPI/I2S Receive Data Register (SPI2S_RXDR) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RXDR[31:16] r 15 14 13 12 11 10 9 8 7 RXDR[15:0] r Bits 31:0 RXDR[31:0]: Receive data register The register serves as an interface with RxFIFO. When it is read, RxFIFO is accessed. Note: Data is always right-aligned. Unused bits are read as zero when the register is read. Writing to the register is ignored. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is read by single access halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be read by single access word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be read by single access DocID029587 Rev 3 2143/3178 2149 Serial peripheral interface (SPI) RM0433 50.11.10 SPI Polynomial Register (SPI_CRCPOLY) Address offset: 0x40 Reset value: 0x0000 0107 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CRCPOLY[31:16] rw 15 14 13 12 11 10 9 8 7 CRCPOLY[15:0] rw Bits 31:0 CRCPOLY[31:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The default 9-bit polynomial setting 0x107 corresponds to default 8-bit setting of DSIZE. It is compatible with setting 0x07 used at some other ST products with fixed length of the polynomial string where the most significant bit of the string is always kept hidden. Length of the polynomial is given by the most significant bit of the value stored at this register. It has to be set greater than DSIZE. CRC33_17 bit has to be set additionally with CRCPOLY register when DSIZE is configured to maximum 32-bit or 16-bit size and CRC is enabled (to keep polynomial length grater than data size). Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 50.11.11 SPI Transmitter CRC Register (SPI_TXCRC) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 TXCRC[31:16] rw 15 14 13 12 11 10 9 8 7 TXCRC[15:0] rw Bits 31:0 TXCRC[31:0]: CRC register for transmitter When CRC calculation is enabled, the TXCRC[31:0] bits contain the computed CRC value of the subsequently transmitted bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: A read to this register when the communication is ongoing could return an incorrect value. Not used for the I2S mode. Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 2144/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) 50.11.12 SPI Receiver CRC Register (SPI_RXCRC) Address offset: 0x48 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RXCRC[31:16] rw 15 14 13 12 11 10 9 8 7 RXCRC[15:0] rw Bits 31:0 RXCRC[31:0]: CRC register for receiver When CRC calculation is enabled, the RXCRC[31:0] bits contain the computed CRC value of the subsequently received bytes. CRC calculation is initialized when the CRCEN bit of SPI_CR1 is written to 1 or when a data block is transacted completely. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPOLY register. The number of bits considered at calculation depends on SPI_CRCPOLY register and CRCSIZE bits settings at SPI_CFG1 register. Note: A read to this register when the communication is ongoing could return an incorrect value. Not used for the I2S mode. Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. 50.11.13 SPI Underrun Data Register (SPI_UDRDR) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 UDRDR[31:16] rw 15 14 13 12 11 10 9 8 7 UDRDR[15:0] rw Bits 31:0 UDRDR[31:0]: Data at slave underrun condition The register is taken into account at slave mode and at underrun condition only. The number of bits considered depends on DSIZE bit settings at SPI_CFG1 register. Underrun condition handling depends on setting if UDRDET and UDRCFG bits at SPI_CFG1 register. Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. DocID029587 Rev 3 2145/3178 2149 Serial peripheral interface (SPI) RM0433 50.11.14 SPI/I2S configuration register (SPI_I2SCGFR) Address offset: 0x50 Reset value: 0x0000 0000 31 30 29 28 27 26 Res Res Res Res Res Res 15 Res 11 10 25 24 23 MCKOE ODD (1) (1) I2SDIV[7:0] (1) rw rw rw 9 8 14 13 12 DATFMT WSINV FIXCH DATLEN[1:0] PCMSYNC (1) (1) (1) (1) (1) (1) (1) rw rw rw rw rw rw rw CKPOL CHLEN 7 22 6 Res 21 20 5 4 19 3 18 17 16 2 1 0 I2SSTD[1:0] I2SCFG[2:0] I2SMOD (1) (1) (1) rw rw rw 1. Those bits must be configured when the I2S is disabled (SPE = 0). Those fields are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. Bits 31:26 Reserved: Forced to 0 by hardware Bit 25 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Bit 24 ODD: Odd factor for the prescaler 0: Real divider value is = I2SDIV *2 1: Real divider value is = (I2SDIV * 2) + 1 Refer to Section 50.9.9: Clock generator for details Bits 23:16 I2SDIV: I2S linear prescaler I2SDIV can take any values except the value 1, when ODD is also equal to 1. Refer to Section 50.9.9: Clock generator for details Bit 15 Reserved: Forced to 0 by hardware Bit 14 DATFMT: Data format 0: The data inside the SPI2S_RXDR or SPI2S_TXDR are right aligned 1: The data inside the SPI2S_RXDR or SPI2S_TXDR are left aligned. Bit 13 WSINV: Word select inversion This bit is used to invert the default polarity of WS signal. 0: In I2S Philips standard, Left channel is transfered when WS is LOW, and right channel when WS is HIGH. In MSB or LSB justified mode, Left channel is transfered when WS is HIGH, and right channel when WS is LOW. In PCM mode the start of frame is indicated by a rising edge. 1: In I2S Philips standard, Left channel is transfered when WS is HIGH, and right channel when WS is LOW. In MSB or LSB justified mode, Left channel is transfered when WS is LOW, and right channel when WS is HIGH. In PCM mode the start of frame is indicated by a falling edge. Bit 12 FIXCH: Fixed channel length in slave 0: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account) 1: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) 2146/3178 DocID029587 Rev 3 RM0433 Serial peripheral interface (SPI) Bit 11 CKPOL: Serial audio clock polarity 0: The signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK. 1: The signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK. Bit 10 CHLEN: Channel length (number of bits per audio channel) 0: 16-bit wide 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Bits 9:8 DATLEN: Data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed Bit 7 PCMSYNC: PCM frame synchronization 0: Short frame synchronization 1: Long frame synchronization Bit 6 Reserved: forced at 0 by hardware Bits 5:4 I2SSTD: I2S standard selection 00: I2S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I2S standards, refer to Section 50.9.5: Supported audio protocols Bits 3:1 I2SCFG: I2S configuration mode 000: Slave - transmit 001: Slave - receive 010: Master - transmit 011: Master - receive 100: Slave - Full Duplex 101: Master - Full Duplex others, not used Bit 0 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S/PCM mode is selected DocID029587 Rev 3 2147/3178 2149 Serial peripheral interface (SPI) 50.12 RM0433 SPI register map and reset values SPI_CR2 SPE Res. Res. Res. Res. Res. Res. Res. 0 0 MIDI[3:0] 0 1 1 1 MSSI[3:0] 0 0 0 0 0 0 UDRCFG [1:0] TIFRE CRCERR OVR UDR TXTF EOT DPXP TXP RXP 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 SPI2S_IFCR Res. Res. Res. Res. Res. Res. Res. Res. SUSPC TSERFC MODFC TIFREC CRCEC 0 0 0 0 0 Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. EOTC MODF 0 TXTFC TSERF 0 UDRC SUSP 0 OVRC TXC 0 RXWNE 0 CTSIZE[15:0] RXPLVL [1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. RXPIE 0 TXPIE 0 DPXPIE Res. DSIZE[4:0] EOTIE Res. 0 0 TXTFIE Res. 0 0 0 UDRIE Res. 0 0 OVRIE Res. 0 Res. Res. 0 0 SPI2S_TXDR Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 0 0 0 0 0 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Reset value Res. TXDR[15:0] Res. TXDR[31:16] 0 0 0 0 0 0 0 0 0 0 0 Reset value Res. RXDR[15:0] Res. RXDR[31:16] Res. SPI2S_RXDR Res. 0x4C 0 Res. 0x48 0 CRCEIE 0 0 TIFREIE 0 0 Res. 0 0 FTHLV[3:0] Res. 0 0 MODFIE 0 0 TSERFIE 0 0 0 0x34 0x3C 0x44 0 Reset value 0x24 0x2C 0x40 0 0 Reset value 0x30 0 Res. 0 0 Res. MASTER 0 Res. Res. LSBFRST 0 0 UDRDET [1:0] CRCEN 0 0 SPI2S_SR 0x14 0x20 0 Res. Res. 0 Res. Res. 1 0 Res. Res. Res. SP[2:0] 0 1 1 CPHA SPI2S_IER 1 Res. 0 1 0 Res. Res. 0 0 CPOL 0 0 CRCSIZE[4:0] Res. SSOE SSIOP 0 0 Res. Res. SSOM Reset value 0 SSM SPI_CFG2 AFCNTR 0 Res. 0 0 TXDMAEN MBR[2:0] 0 RXDMAEN 0 Res. 0 IOSWP 0 Res. 0 Res. 0 Res. 0 Res. 0 Reset value 0x18 MASRX 0 CSUSP 0 CSTART SSI CRC33_17 HDDIR TCRCINI 0 COMM [1:0] 0 0 0 Res. 0x10 0 Res. SPI_CFG1 Reset value 0x0C 0 TSIZE[15:0] Res. 0 Res. Reset value Res. 0x08 0 TSER[15:0] Res. 0x04 0 RCRCINI Res. Reset value IOLOCK Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPI2S_CR1 Res. 0x00 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 396. SPI register map and reset values 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value CRCPOLY[31:16](1) SPI_CRCPOLY Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2148/3178 0 0 CRCPOLY[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 TXCRC[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRC[15:0] 0 0 0 0 0 0 0 0 0 0 0 UDRDR[31:16](1) SPI_UDRDR Reset value 0 RXCRC[31:16](1) SPI_RXCRC Reset value 0 TXCRC[31:16](1) SPI_TXCRC Reset value 0 0 0 0 0 UDRDR[15:0] 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 RM0433 Serial peripheral interface (SPI) 0 0 0 0 0 0 0 0 0 0 0 0 I2SMOD I2SCFG[2:0] I2SSTD[1:0] 0 Res. 0 PCMSYNC 0 DATLEN 0 CHLEN 0 FIXCH 0 CKPOL 0 Res. 0 I2SDIV[7:0] WSINV 0 Res. ODD Res. Res. Res. MCKOE Reset value Res. SPI_I2SCGFR Res. 0x50 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 396. SPI register map and reset values (continued) 0 0 1. Bits 31-16 are reserved at the peripheral instances with data size limited to 16-bit. There is no constrain when 32-bit access is applied at these addresses. Reserved bits 31-16 are always read zero while any write to them is ignored. Refer to Table register boundary addresses. DocID029587 Rev 3 2149/3178 2149 Serial audio interface (SAI) RM0433 51 Serial audio interface (SAI) 51.1 Introduction The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted. I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC’97 protocols may be addressed for example. SPDIF output is offered when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or not (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. 2150/3178 DocID029587 Rev 3 RM0433 51.2 Serial audio interface (SAI) SAI main features • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Possible synchronization between multiple SAIs. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 • PDM interface, supporting up to 4 microphone pairs • SPDIF output available if required. • Up to 16 slots available with configurable size. • Number of bits by frame can be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • – Overrun and underrun detection, – Anticipated frame synchronization signal detection in slave mode, – Late frame synchronization signal detection in slave mode, – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors, – FIFO requests. 2-channel DMA interface. DocID029587 Rev 3 2151/3178 2203 Serial audio interface (SAI) RM0433 51.3 SAI functional description 51.3.1 SAI block diagram Figure 636 shows the SAI block diagram while Table 397 and Table 398 list SAI internal and external signals. Figure 636. SAI functional block diagram ELW$3%EXV $XGLREORFN$ ),)2FWUO ),)2 VDLBDB NHUBFN &ORFNJHQHUDWRU $XGLREORFN$ &RQILJXUDWLRQ DQGVWDWXV UHJLVWHUV )60 ELWVKLIWUHJLVWHU VDLBSFON $XGLREORFN% ),)2FWUO ),)2 VDLBEB NHUBFN &ORFNJHQHUDWRU $XGLREORFN% 6\QFKUR FWUORXW 3'0B,) &RQILJXUDWLRQ DQGVWDWXV UHJLVWHUV )6B$ 6&.B$ 6'B$ 0&/.B$ )6B% 6&.B% 6'B% 0&/.B% '> @ &.> @ )60 ELWVKLIWUHJLVWHU 6$,B%&5 VDLBV\QFBRXWBVFN VDLBV\QFBRXWBIV $3%,QWHUIDFH VDLBEBJEOBLW VDLBEBGPD ELW$3%EXV VDLBV\QFBLQBVFN VDLBV\QFBLQBIV )URPRWKHU6$,%ORFNV 6$,B$&5 6$,B*&5 ,2/LQH0DQDJHPHQW $3%,QWHUIDFH 6\QFKUR LQ 6$, 7RRWKHU6$,%ORFNV VDLBDBJEOBLW VDLBDBGPD 06Y9 The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine. Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by DMA in order to leave the CPU free during the communication. Each audio block is independent. They can be synchronous with each other. An I/O line controller manages a set of 4 dedicated pins (SD, SCK, FS, MCLK) for a given audio block in the SAI. Some of these pins can be shared if the two sub-blocks are declared as synchronous to leave some free to be used as general purpose I/Os. The MCLK pin can be output, or not, depending on the application, the decoder requirement and whether the audio block is configured as the master. If one SAI is configured to operate synchronously with another one, even more I/Os can be freed (except for pins SD_x). The functional state machine can be configured to address a wide range of audio protocols. Some registers are present to set-up the desired protocols (audio frame waveform generator). 2152/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) The audio sub-block can be a transmitter or receiver, in master or slave mode. The master mode means the SCK_x bit clock and the frame synchronization signal are generated from the SAI, whereas in slave mode, they come from another external or internal master. There is a particular case for which the FS signal direction is not directly linked to the master or slave mode definition. In AC’97 protocol, it will be an SAI output even if the SAI (link controller) is set-up to consume the SCK clock (and so to be in Slave mode). Note: For ease of reading of this section, the notation SAI_x refers to SAI_A or SAI_B, where ‘x’ represents the SAI A or B sub-block. 51.3.2 SAI pins and internal signals Table 397. SAI internal input/output signals Internal signal name Signal type sai_a_gbl_it/ sai_b_gbl_it sai_a_dma, sai_b_dma Output Description Audio block A and B global interrupts. Input/output Audio block A and B DMA acknowledges and requests. sai_sync_out_sck, sai_sync_out_fs Output Internal clock and frame synchronization output signals exchanged with other SAI blocks. sai_sync_in_sck, sai_sync_in_fs Input Internal clock and frame synchronization input signals exchanged with other SAI blocks. sai_a_ker_ck/ sai_b_ker_ck Input Audio block A/B kernel clock. sai_pclk Input APB clock. Table 398. SAI input/output pins Name SAI_SCK_A/B SAI_MCLK_A/B 51.3.3 Signal type Comments Input/output Audio block A/B bit clock. Output Audio block A/B master clock. SAI_SD_A/B Input/output Data line for block A/B. SAI_FS_A/B Input/output Frame synchronization line for audio block A/B. SAI_CK[4:1] Output PDM bitstream clock. SAI_D[4:1] Input PDM bitstream data. Main SAI modes Each audio sub-block of the SAI can be configured to be master or slave via MODE bits in the SAI_xCR1 register of the selected audio block. Master mode In master mode, the SAI delivers the timing signals to the external connected device: • The bit clock and the frame synchronization are output on pin SCK_x and FS_x, respectively. • If needed, the SAI can also generate a master clock on MCLK_x pin. DocID029587 Rev 3 2153/3178 2203 Serial audio interface (SAI) RM0433 Both SCK_x, FS_x and MCLK_x are configured as outputs. Slave mode The SAI expects to receive timing signals from an external device. • If the SAI sub-block is configured in asynchronous mode, then SCK_x and FS_x pins are configured as inputs. • If the SAI sub-block is configured to operate synchronously with another SAI interface or with the second audio sub-block, the corresponding SCK_x and FS_x pins are left free to be used as general purpose I/Os. In slave mode, MCLK_x pin is not used and can be assigned to another function. It is recommended to enable the slave device before enabling the master. Configuring and enabling SAI modes Each audio sub-block can be independently defined as a transmitter or receiver through the MODE bit in the SAI_xCR1 register of the corresponding audio block. As a result, SAI_SD_x pin will be respectively configured as an output or an input. Two master audio blocks in the same SAI can be configured with two different MCLK and SCK clock frequencies. In this case they have to be configured in asynchronous mode. Each of the audio blocks in the SAI are enabled by SAIEN bit in the SAI_xCR1 register. As soon as this bit is active, the transmitter or the receiver is sensitive to the activity on the clock line, data line and synchronization line in slave mode. In master TX mode, enabling the audio block immediately generates the bit clock for the external slaves even if there is no data in the FIFO, However FS signal generation is conditioned by the presence of data in the FIFO. After the FIFO receives the first data to transmit, this data is output to external slaves. If there is no data to transmit in the FIFO, 0 values are then sent in the audio frame with an underrun flag generation. In slave mode, the audio frame starts when the audio block is enabled and when a start of frame is detected. In Slave TX mode, no underrun event is possible on the first frame after the audio block is enabled, because the mandatory operating sequence in this case is: 51.3.4 1. Write into the SAI_xDR (by software or by DMA). 2. Wait until the FIFO threshold (FLH) flag is different from 000b (FIFO empty). 3. Enable the audio block in slave transmitter mode. SAI synchronization mode There are two levels of synchronization, either at audio sub-block level or at SAI level. Internal synchronization An audio sub-block can be configured to operate synchronously with the second audio subblock in the same SAI. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication. The audio block configured in synchronous mode sees its own SCK_x, FS_x, and MCLK_x pins released back as GPIOs while the audio block configured in asynchronous mode is the one for which FS_x and SCK_x ad MCLK_x I/O pins are relevant (if the audio block is considered as master). 2154/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Typically, the audio block in synchronous mode can be used to configure the SAI in full duplex mode. One of the two audio blocks can be configured as a master and the other as slave, or both as slaves with one asynchronous block (corresponding SYNCEN[1:0] bits set to 00 in SAI_xCR1) and one synchronous block (corresponding SYNCEN[1:0] bits set to 01 in the SAI_xCR1). Note: Due to internal resynchronization stages, PCLK APB frequency must be higher than twice the bit rate clock frequency. External synchronization The audio sub-blocks can also be configured to operate synchronously with another SAI. This can be done as follow: Note: 1. The SAI, which is configured as the source from which the other SAI is synchronized, has to define which of its audio sub-block is supposed to provide the FS and SCK signals to other SAI. This is done by programming SYNCOUT[1:0] bits. 2. The SAI which shall receive the synchronization signals has to select which SAI will provide the synchronization by setting the proper value on SYNCIN[1:0] bits. For each of the two SAI audio sub-blocks, the user must then specify if it operates synchronously with the other SAI via the SYNCEN bit. SYNCIN[1:0] and SYNCOUT[1:0] bits are located into the SAI_GCR register, and SYNCEN bits into SAI_xCR1 register. If both audio sub-blocks in a given SAI need to be synchronized with another SAI, it is possible to choose one of the following configurations: • Configure each audio block to be synchronous with another SAI block through the SYNCEN[1:0] bits. • Configure one audio block to be synchronous with another SAI through the SYNCEN[1:0] bits. The other audio block is then configured as synchronous with the second SAI audio block through SYNCEN[1:0] bits. The following table shows how to select the proper synchronization signal depending on the SAI block used. For example SAI2 can select the synchronization from SAI1 by setting SAI2 SYNCIN to 0. If SAI1 wants to select the synchronization coming from SAI2, SAI1 SYNCIN must be set to 1. Positions noted as ‘res’ shall not be used. Table 399. External synchronization selection Block instance 51.3.5 SYNCIN= 3 SYNCIN= 2 SYNCIN= 1 SYNCIN= 0 SAI1 SAI4 sync SAI3 sync SAI2 sync Res. SAI2 SAI4 sync SAI3 sync Res. SAI1 sync SAI3 SAI4 sync Res. SAI2 sync SAI1 sync SAI4 Res. SAI3 sync SAI2 sync SAI1 sync Audio data size The audio frame can target different data sizes by configuring bit DS[2:0] in the SAI_xCR1 register. The data sizes may be 8, 10, 16, 20, 24 or 32 bits. During the transfer, either the MSB or the LSB of the data are sent first, depending on the configuration of bit LSBFIRST in the SAI_xCR1 register. DocID029587 Rev 3 2155/3178 2203 Serial audio interface (SAI) 51.3.6 RM0433 Frame synchronization The FS signal acts as the Frame synchronization signal in the audio frame (start of frame). The shape of this signal is completely configurable in order to target the different audio protocols with their own specificities concerning this Frame synchronization behavior. This reconfigurability is done using register SAI_xFRCR. Figure 637 illustrates this flexibility. Figure 637. Audio frame )6/HQJWK XSWRELWV )6DFWLYH XSWRELWV )6 7KHIDOOLQJHGJHFDQRFFXULQWRWKLVDUHD 6&. 6' )62)) 6ORW 6' )62)) 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW « « 6ORW 6ORW 06Y9 In AC’97 mode or in SPDIF mode (bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01 in the SAI_xCR1 register), the frame synchronization shape is forced to match the AC’97 protocol. The SAI_xFRCR register value is ignored. Each audio block is independent and consequently each one requires a specific configuration. Frame length • Master mode The audio frame length can be configured to up to 256 bit clock cycles, by setting FRL[7:0] field in the SAI_xFRCR register. If the frame length is greater than the number of declared slots for the frame, the remaining bits to transmit will be extended to 0 or the SD line will be released to HI-z depending the state of bit TRIS in the SAI_xCR2 register (refer to Section : FS signal role). In reception mode, the remaining bit is ignored. If bit NOMCK is cleared, (FRL+1) must be equal to a power of 2, from 8 to 256, to ensure that an audio frame contains an integer number of MCLK pulses per bit clock cycle. If bit NOMCK is set, the (FRL+1) field can take any value from 8 to 256. Refer to Section 51.3.8: SAI clock generator”. • Slave mode The audio frame length is mainly used to specify to the slave the number of bit clock cycles per audio frame sent by the external master. It is used mainly to detect from the master any anticipated or late occurrence of the Frame synchronization signal during an on-going audio frame. In this case an error will be generated. For more details refer to Section 51.3.14: Error flags. In slave mode, there are no constraints on the FRL[7:0] configuration in the SAI_xFRCR register. The number of bits in the frame is equal to FRL[7:0] + 1. 2156/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) The minimum number of bits to transfer in an audio frame is 8. Frame synchronization polarity FSPOL bit in the SAI_xFRCR register sets the active polarity of the FS pin from which a frame is started. The start of frame is edge sensitive. In slave mode, the audio block waits for a valid frame to start transmitting or receiving. Start of frame is synchronized to this signal. It is effective only if the start of frame is not detected during an ongoing communication and assimilated to an anticipated start of frame (refer to Section 51.3.14: Error flags). In master mode, the frame synchronization is sent continuously each time an audio frame is complete until the SAIEN bit in the SAI_xCR1 register is cleared. If no data are present in the FIFO at the end of the previous audio frame, an underrun condition will be managed as described in Section 51.3.14: Error flags), but the audio communication flow will not be interrupted. Frame synchronization active level length The FSALL[6:0] bits of the SAI_xFRCR register allow configuring the length of the active level of the Frame synchronization signal. The length can be set from 1 to 128 bit clock cycles. As an example, the active length can be half of the frame length in I2S, LSB or MSB-justified modes, or one-bit wide for PCM/DSP or TDM mode. Frame synchronization offset Depending on the audio protocol targeted in the application, the Frame synchronization signal can be asserted when transmitting the last bit or the first bit of the audio frame (this is the case in I2S standard protocol and in MSB-justified protocol, respectively). FSOFF bit in the SAI_xFRCR register allows to choose one of the two configurations. FS signal role The FS signal can have a different meaning depending on the FS function. FSDEF bit in the SAI_xFRCR register selects which meaning it will have: • 0: start of frame, like for instance the PCM/DSP, TDM, AC’97, audio protocols, • 1: start of frame and channel side identification within the audio frame like for the I2S, the MSB or LSB-justified protocols. When the FS signal is considered as a start of frame and channel side identification within the frame, the number of declared slots must be considered to be half the number for the left channel and half the number for the right channel. If the number of bit clock cycles on half audio frame is greater than the number of slots dedicated to a channel side, and TRIS = 0, 0 is sent for transmission for the remaining bit clock cycles in the SAI_xCR2 register. Otherwise if TRIS = 1, the SD line is released to HI-Z. In reception mode, the remaining bit clock cycles are not considered until the channel side changes. DocID029587 Rev 3 2157/3178 2203 Serial audio interface (SAI) RM0433 Figure 638. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) 1XPEHURIVORWVQRWDOLJQHGZLWKWKHDXGLRIUDPH $XGLRIUDPH +DOIRIIUDPH )6 VFN VORW 6ORW21 6ORW2)) 6ORW21 6ORW21 6ORW2)) 6ORW21 1XPEHURIVORWVDOLJQHGZLWKWKHDXGLRIUDPH $XGLRIUDPH +DOIRIIUDPH )6 VFN VORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 069 1. The frame length should be even. If FSDEF bit in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then: 2158/3178 • if TRIS = 0 in the SAI_xCR2 register, the remaining bit after the last slot will be forced to 0 until the end of frame in case of transmitter, • if TRIS = 1, the line will be released to HI-Z during the transfer of these remaining bits. In reception mode, these bits are discarded. DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Figure 639. FS role is start of frame (FSDEF = 0) $XGLRIUDPH VFN VORW 6ORW 6ORW 6ORW 6ORWQ 'DWD DIWHUVORWQLI75,6 6'RXWSXWUHOHDVHG +,= DIWHUVORWQLI75,6 06 9 The FS signal is not used when the audio block in transmitter mode is configured to get the SPDIF output on the SD line. The corresponding FS I/O will be released and left free for other purposes. 51.3.7 Slot configuration The slot is the basic element in the audio frame. The number of slots in the audio frame is equal to NBSLOT[3:0] + 1. The maximum number of slots per audio frame is fixed at 16. For AC’97 protocol or SPDIF (when bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01), the number of slots is automatically set to target the protocol specification, and the value of NBSLOT[3:0] is ignored. Each slot can be defined as a valid slot, or not, by setting SLOTEN[15:0] bits of the SAI_xSLOTR register. When a invalid slot is transferred, the SD data line is either forced to 0 or released to HI-z depending on TRIS bit configuration (refer to Section : Output data line management on an inactive slot) in transmitter mode. In receiver mode, the received value from the end of this slot is ignored. Consequently, there will be no FIFO access and so no request to read or write the FIFO linked to this inactive slot status. The slot size is also configurable as shown in Figure 640. The size of the slots is selected by setting SLOTSZ[1:0] bits in the SAI_xSLOTR register. The size is applied identically for each slot in an audio frame. DocID029587 Rev 3 2159/3178 2203 Serial audio interface (SAI) RM0433 Figure 640. Slot size configuration with FBOFF = 0 in SAI_xSLOTR $XGLREORFNLVUHFHLYHU $XGLREORFNLVWUDQVPLWWHU 6ORWVL]H GDWDVL]H 6ORWVL]H GDWDVL]H VORW[ GDWDVL]H VORW[ GDWDVL]H GDWDVL]H GDWDVL]H VORW[ GDWDVL]H VORW[ GDWDVL]H ELW ELW VORW[ ;; GDWDVL]H VORW[ GDWDVL]H ;;;; ELW ELW ; GRQ¶WFDUH 069 It is possible to choose the position of the first data bit to transfer within the slots. This offset is configured by FBOFF[4:0] bits in the SAI_xSLOTR register. 0 values will be injected in transmitter mode from the beginning of the slot until this offset position is reached. In reception, the bit in the offset phase is ignored. This feature targets the LSB justified protocol (if the offset is equal to the slot size minus the data size). Figure 641. First bit offset $XGLREORFNLVWUDQVPLWWHU $XGLREORFNLVUHFHLYHU 6ORWVL]H GDWDVL]H 6ORWVL]H GDWDVL]H VORW[ VORW[ GDWDVL]H GDWDVL]H GDWDVL]H GDWDVL]H )%2)) )%2)) VORW[ ;; GDWDVL]H VORW[ ELW GDWDVL]H ;; ELW )%2)) 6/276='6 )%2)) 6/276='6 VORW[ GDWDVL]H VORW[ ;;;; GDWDVL]H ELW ; GRQ¶WFDUH ELW 069 It is mandatory to respect the following conditions to avoid bad SAI behavior: FBOFF ≤(SLOTSZ - DS), DS ≤SLOTSZ, NBSLOT x SLOTSZ ≤FRL (frame length), The number of slots must be even when bit FSDEF in the SAI_xFRCR register is set. In AC’97 and SPDIF protocol (bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01), the slot size is automatically set as defined in Section 51.3.11: AC’97 link controller. 2160/3178 DocID029587 Rev 3 RM0433 51.3.8 Serial audio interface (SAI) SAI clock generator Each audio sub-block has its own clock generator that makes these two blocks completely independent. There is no difference in terms of functionality between these two clock generators. When the audio block is configured as master, the clock generator provides the bit clock (SCK_x) and the master clock (MCLK_x) for external decoders. The frame synchronization (FS_x) is also derived from the signals provided by the clock generator. The clock source for the SAI clock generator (sai_x_ker_ck) is delivered by the product clock controller (RCC). When the audio block is defined as slave, the clock generator is OFF. The value of NOMCK, MCKDIV and OSR bits are ignored. In addition, MCLK_x I/O pin is released and can be used as a general purpose I/O. The bit clock strobing edge of (SCK_x) can be configured through CKSTR bit in the SAI_xCR1 register. This bit is functional in master and slave mode. Figure 642 illustrates the architecture of the audio block clock generator. Figure 642. Audio block clock generator overview 6$,FORFNJHQHUDWRU[ 0&.',9> @ VDLB[BNHUB FN &ORFNGLYLGHU )5/> @ 265 · · )5/ 0&/.B[ 120&. >@ 6&.B[ $XGLR%ORFN[ · )5/ )6B[ )5/> @ >@ )5/PXVWEHDSRZHURIZKHQ120&. 06Y9 The NOMCK bit of the SAI_xCR1 register is used to define whether the master clock is generated or not. When the SAI is used in master mode, the clock generator configuration differs depending on whether a master clock (MCLK_x) needs to be provided or not. If NOMCK is set to 1, the master clock is not generated, and the user has more flexibility to select the frame length and frame synchronization frequency. In addition, MCLK_x signal is driven Low if this pin is configured as the SAI pin in GPIO peripherals. MCKDIV can still be used to adjust the SCK_x clock to the required frequency. If NOMCK is set to 0, the master clock is generated, and can be used as reference clock for external decoders. In this case, the frequency ratio between the frame synchronization and the master clock is fixed to 512 or 256, and the frame length must be a power of 2. More details are given hereafter. DocID029587 Rev 3 2161/3178 2203 Serial audio interface (SAI) RM0433 Clock generator programming with MCLK (NOMCK = 0) In that case, MCLK_x frequency will be: F MCLK_x = 256 × F FS_x if OSR=0 F MCLK_x = 512 × F FS_x if OSR=1 When MCKDIV is different from 0, MCLK_x frequency is given by the equation below: F sai_x_ker_ck F MCLK_x = -------------------------------------MCKDIV The frame synchronization frequency is given by: F sia_x_ker_ck F FS_x = -----------------------------------------------------------------------------MCKDIV × ( OSR + 1 ) × 256 The frequency of the bit clock (SCK_x) is given by the following expression: F MCLK_x × ( FRL + 1 ) F SCK_x = -------------------------------------------------------------( OSR + 1 ) × 256 Note: If NOMCK = 0, (FRL+1) must be a power of two. In addition (FRL+1) must be between 8 and 256 (see Section : FS signal role). When MCKDIV division ratio is odd, the duty cycle of MCLK will not be 50%. The bit clock signal (SCK_x) can also have a duty cycle different from 50% if MCKDIV is odd, and if OSR is equal to 0, and if (FRL+1) = 2 8. It is recommended to configure MCKDIV to an even or big values (higher than 10). Note that MCKDIV = 0 gives the same result as MCKDIV = 1. Clock generator programming without MCLK (NOMCK = 1) When MCKDIV is different from 0, SCK_x frequency is given in the equation below: F sai_x_ker_ck F SCK_x = -------------------------------------MCKDIV The frequency of the frame synchronization (FS_x) in given by the following equation: F sai_x_ker_ck F FS_x = ----------------------------------------------------------( FRL + 1 ) × MCKDIV Note: When NOMCK = 0, (FRL+1) can take any values from 8 to 256. Note that MCKDIV = 0 gives the same result as MCKDIV = 1. 2162/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Clock generator programming examples Table 400 shows some programming examples for 48, 96 and 192 kHz. Table 400. Clock generator programming examples Input sai_x_ker_ck clock frequency MCLK Y 98.304 MHz FMCLK/ FFS FRL (1) OSR NOMCK MCKDIV[5:0] Audio Sampling frequency (FFS) 512 2N-1 1 0 0 or 1 192 kHz 512 2N 1 0 2 96 kHz 512 N 2 -1 1 0 4 48 kHz 256 2N-1 0 0 2 192 kHz 256 2N-1 0 0 4 96 kHz 256 N-1 0 0 8 48 kHz - 63 - 1 8 192 kHz - 63 - 1 16 96 kHz - 63 - 1 32 48 kHz N -1 2 1. N is an integer value between 3 and 8. 51.3.9 Internal FIFOs Each audio block in the SAI has its own FIFO. Depending if the block is defined to be a transmitter or a receiver, the FIFO can be written or read, respectively. There is therefore only one FIFO request linked to FREQ bit in the SAI_xSR register. An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: • FIFO threshold setting (FLVL bits in SAI_xCR2) • Communication direction (transmitter or receiver). Refer to Section : Interrupt generation in transmitter mode and Section : Interrupt generation in reception mode. Interrupt generation in transmitter mode The interrupt generation depends on the FIFO configuration in transmitter mode: • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO empty (FTH[2:0] set to 000b), an interrupt is generated (FREQ bit set by hardware to 1 in SAI_xSR register) if no data are available in SAI_xDR register (FLVL[2:0] bits in SAI_xSR is less than 001b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is no more empty (FLVL[2:0] bits in SAI_xSR are different from 000b) i.e one or more data are stored in the FIFO. • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter full (FTH[2:0] set to 001b), an interrupt is generated (FREQ bit set by hardware to 1 in SAI_xSR register) if less than a quarter of the FIFO contains data (FLVL[2:0] bits in SAI_xSR are less than 010b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when at least a quarter of the FIFO contains data (FLVL[2:0] bits in SAI_xSR are higher or equal to 010b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO half full (FTH[2:0] set to 010b), an interrupt is generated (FREQ bit set by hardware to 1 in DocID029587 Rev 3 2163/3178 2203 Serial audio interface (SAI) RM0433 SAI_xSR register) if less than half of the FIFO contains data (FLVL[2:0] bits in SAI_xSR are less than 011b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when at least half of the FIFO contains data (FLVL[2:0] bits in SAI_xSR are higher or equal to 011b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO three quarter (FTH[2:0] set to 011b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if less than three quarters of the FIFO contain data (FLVL[2:0] bits in SAI_xSR are less than 100b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when at least three quarters of the FIFO contain data (FLVL[2:0] bits in SAI_xSR are higher or equal to 100b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO full (FTH[2:0] set to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if the FIFO is not full (FLVL[2:0] bits in SAI_xSR is less than 101b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is full (FLVL[2:0] bits in SAI_xSR is equal to 101b value). Interrupt generation in reception mode The interrupt generation depends on the FIFO configuration in reception mode: • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO empty (FTH[2:0] set to 000b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least one data is available in SAI_xDR register(FLVL[2:0] bits in SAI_xSR is higher or equal to 001b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO becomes empty (FLVL[2:0] bits in SAI_xSR is equal to 000b) i.e no data are stored in FIFO. • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter fully (FTH[2:0] set to 001b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least one quarter of the FIFO data locations are available (FLVL[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when less than a quarter of the FIFO data locations become available (FLVL[2:0] bits in SAI_xSR is less than 010b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO half fully (FTH[2:0] set to 010b value), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least half of the FIFO data locations are available (FLVL[2:0] bits in SAI_xSR is higher or equal to 011b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when less than half of the FIFO data locations become available (FLVL[2:0] bits in SAI_xSR is less than 011b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO three quarter full(FTH[2:0] set to 011b value), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least three quarters of the FIFO data locations are available (FLVL[2:0] bits in SAI_xSR is higher or equal to 100b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO has less than three quarters of the FIFO data locations avalable(FLVL[2:0] bits in SAI_xSR is less than 100b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO full(FTH[2:0] set to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if the FIFO is full (FLVL[2:0] bits in SAI_xSR is equal to 101b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is not full (FLVL[2:0] bits in SAI_xSR is less than 101b). 2164/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Like interrupt generation, the SAI can use the DMA if DMAEN bit in the SAI_xCR1 register is set. The FREQ bit assertion mechanism is the same as the interruption generation mechanism described above for FREQIE. Each FIFO is an 8-word FIFO. Each read or write operation from/to the FIFO targets one word FIFO location whatever the access size. Each FIFO word contains one audio slot. FIFO pointers are incremented by one word after each access to the SAI_xDR register. Data should be right aligned when it is written in the SAI_xDR. Data received will be right aligned in the SAI_xDR. The FIFO pointers can be reinitialized when the SAI is disabled by setting bit FFLUSH in the SAI_xCR2 register. If FFLUSH is set when the SAI is enabled the data present in the FIFO will be lost automatically. PDM Interface The PDM (Pulse Density Modulation) interface is provided in order to support digital microphones. Up to 4 digital microphone pairs can be connected in parallel. Figure 643 shows a typical connection of a digital microphone pair via a PDM interface. Both microphones share the same bitstream clock and data line. Thanks to a configuration pin (LR), a microphone can provide valid data on SAI_CK[m] rising edge while the other provides valid data on SAI_CK[m] falling edge (m being the number of clock lines). Figure 643. PDM typical connection and timing 9FF /5 6$, 6$,B$ 0 7'0OLQN 7'0OLQN 3'0B,) 51.3.10 6$,B'Q 0S/ 6$,B&.P /5 *1' 0S5 6$,B'Q 0S/ 0S5 0S/ 0S5 0S/ 0S5 0S/ 0S5 0S/ 6$,B&.P 06Y9 1. n refers to the number of data lines and p to the number of microphone pairs. The PDM function is intended to be used in conjunction with SAI_A sub-block configured in TDM MASTER mode. It cannot be used with SAI_B sub-block. The PDM interface uses the timing signals provided by the TDM interface of SAI_A and adapts them to generate a bitstream clock (SAI_CK[m]). DocID029587 Rev 3 2165/3178 2203 Serial audio interface (SAI) RM0433 The data processing sequence into the PDM is the following: 1. The PDM interface builds the bitstream clock from the bit clock received from the TDM interface of SAI_A. 2. The bitstream data received from the microphones (SAI_D[n]) are de-interleaved and go through a 7-bit delay line in order to fine-tune the delay of each microphone with the accuracy of the bitstream clock. 3. The shift registers translate each serial bitstream into bytes. 4. The last operation consists in shifting-out the resulting bytes to SAI_A via the serial data line of the TDM interface. Figure 644 hereafter shows the block diagram of PDM interface, with a detailed view of a de-interleaver. Note: The PDM interface does not embed the decimation filter required to build-up the PCM audio samples from the bitstream. It is up to the application software to perform this operation. Figure 644. Detailed PDM interface block diagram /DWFK5HJ 7RVDLDBVGBLQ 3'0B,) 'H,QWHUOHDYHU 6$,B' 'H,QWHUOHDYHU 6$,B' 'H,QWHUOHDYHU 6$,B' 'H,QWHUOHDYHU 6$,B' 6$,B&. )URPVDLDBIVBRXW 6$,B&. &RQWURO /RJLF SGPBFN 6$,B&. )URPVDLDBVFNBRXW 6$,B&. 0,&1%5 3'0(1 6$,UHJLVWHULQWHUIDFH '/<0> @/ '/<0> @5 &.(1> @ '/<0S/ 'H,QWHUOHDYHUQ GHOD\OLQH VKLIWUHJ GHOD\OLQH VKLIWUHJ 6$,B'>Q@ '/<0S5 06Y9 1. n refers to the number of data lines and p to the number of microphone pairs. The PDM interface can be enabled through the PDMEN bit in SAI_PDMCR register. However the PDM interface must be enabled prior to enabling SAI_A block. To reduce the memory footprint, the user can select the amount of microphones the application needs. This can be done through MICNBR[1:0] bits. It is possible to select between 2,4,6 or 8 microphones. For example, if the application is using 3 microphones, the user has to select 4. 2166/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Enabling the PDM interface To enable the PDM interface, follow the sequence below: Note: 1. Configure SAI_A in TDM MASTER mode (see Table 401). 2. Configure the PDM interface as follows: a) Define the number of digital microphones via MICNBR. b) Enable the bitstream clock needed in the application by setting the corresponding bits on CKEN to 1. 3. Enable the PDM interface, via PDMEN bit. 4. Enable the SAI_A. Once the PDM interface and SAI_A are enabled, the first 2 TDMA frames received on SAI_ADR are invalid and shall be dropped. Start-up sequence Figure 645 shows the start-up sequence: Once the PDM interface is enabled, it waits for the frame synchronization event prior to starting the acquisition of the microphone samples. After 8 SAI_CK clock periods, a data byte coming from each microphone is available, and transferred to the SAI, via the TDM interface. Figure 645. Start-up sequence 3GPBFN VDLDBFONBRXW 'RQ¶WFDUH VDLDBVGBLQ 0/[ 05[ 0/[ 05[ 0/\ 05\ 0/\ 05\ VDLDBIVBRXW 3'0(1 1 6$,(1 :DLWIRUIUDPH V\QF 1 )UDPHV\QFLVGHWHFWHGZDLWLQJ IRUUHFHLYLQJELWVIURPHDFK PLFURSKRQH 1 7UDQVPLVVLRQWR6$,RIWKHGDWDUHFHLYHG 7UDQVPLVVLRQWR6$,RIWKHGDWDUHFHLYHG RQIUDPH1DQGDFTXLVLWLRQRIWKHQH[W RQIUDPH1DQGDFTXLVLWLRQRIWKHQH[W ELWVIURPHDFKPLFURSKRQH ELWVIURPHDFKPLFURSKRQH 1RUHV\QFZLWKWKHIUDPHV\QF 1RUHV\QFZLWKWKHIUDPHV\QF 06Y 9 SAI_ADR data format The arrangement of the data coming from the microphone into the SAI_ADR register depends on the following parameters: • The amount of microphones • The slot width selected • LSBFIRST bit. The slot width defines the amount of significant bits into each word available into the SAI_ADR. When a slot width of 32 bits is selected, each data available into the SAI_ADR will contain 32 useful bits. This reduces the amount of words stored into the memory. However the DocID029587 Rev 3 2167/3178 2203 Serial audio interface (SAI) RM0433 counterpart is that the software has to perform some operations to de-interleave the data of each microphone. In the other hand, when the slot width is set to 8 bits, each data available into the SAI_ADR will contain 8 useful bits. This increases the amount of words stored into the memory. However, it offers the advantage to avoid extra processing since each word contains information from one microphone. SAI_ADR data format example • 32-bit slot width (DS = 0b111 and SLOTSZ = 0). Refer to Figure 646. For an 8 microphone configuration, two consecutive words read from the SAI_ADR register contain a data byte from each microphone. For a 4 microphones configuration, each word read from the SAI_ADR register contains a data byte from each microphone. Figure 646. SAI_ADR format in TDM, 32-bit slot width 0LFURSKRQHVFRQILJXUDWLRQ 05 05 05 05 05 05 05 05 05 05 05 05 05 05 0/ 0/ 05 05 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 05 05 05 05 05 05 05 05 05 05 05 05 05 05 0/ 0/ 05 05 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ ZRUGQ E /6%),567 0/ 0/ ZRUGQ 0/ 0/ E 0LFURSKRQHVFRQILJXUDWLRQ 05 05 05 05 05 05 05 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 05 05 05 05 05 05 05 05 0/ 0/ 0/ 0/ 0/ 0/ 05 E /6%),567 0/ ZRUGQ 0/ E 06Y9 • 16-bit slot width (DS = 0b100 and SLOTSZ = 0). Refer to Figure 647. For an 8 microphone configuration, four consecutive words read from the SAI_ADR register contain a data byte from each microphone. Note that the 16-bit data of SAI_ADR are right aligned. For 4 or 2 microphone configuration, the SAI behavior is similar to 8-microphone configurations. Up to 2 words of 16 bits are required to acquire a byte from 4 microphones and a single word for 2 microphones. 2168/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Figure 647. SAI_ADR format in TDM, 16-bit slot width 0LFURSKRQHVFRQILJXUDWLRQ 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 0/ 0/ 0/ 0/ 0/ 0/ 0/ 05 05 0/ 0/ 0/ 05 0/ 0/ 0/ E 0/ 0/ 0/ 0/ ]HURV 0/ 0/ ZRUGQ 0/ ]HURV 0/ 0/ ZRUGQ /6%),567 0/ E E 0/ E ]HURV ZRUGQ 0LFURSKRQHVFRQILJXUDWLRQ E 05 05 05 05 05 05 05 05 05 05 05 05 05 05 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/ ]HURV 0/ 0/ ZRUGQ 0/ 0/ ]HURV 0/ 0/ /6%),567 ZRUGQ 05 05 E 0LFURSKRQHVFRQILJXUDWLRQ E 05 05 05 05 05 05 05 0/ 0/ 0/ 0/ 0/ 0/ ]HURV 0/ /6%),567 0/ ZRUGQ 05 E 06Y9 • Using a 8-bit slot width (DS = 0b010 and SLOTSZ = 0). Refer to Figure 648. For an 8 microphone configuration, 8 consecutive words read from the SAI_ADR register contain a byte of data from each microphone. Note that the 8-bit data of SAI_ADR are right aligned. For 4 or 2 microphone configuration, the SAI behavior is similar to 8 microphone configurations. Up to 4 words of 8 bits are required to acquire a byte from 4 microphones and 2 words from 2 microphones. DocID029587 Rev 3 2169/3178 2203 Serial audio interface (SAI) RM0433 Figure 648. SAI_ADR format in TDM, 8-bit slot width 0LFURSKRQHVFRQILJXUDWLRQ 05 0/ 05 0/ 05 0/ 05 0/ 05 0/ 05 0/ 05 0/ 05 05 05 05 05 ]HURV E 05 ZRUGQ E E 05 0/ ]HURV 05 ZRUGQ 05 /6%),567 E ]HURV ZRUGQ 0LFURSKRQHVFRQILJXUDWLRQ 05 0/ 05 0/ 05 0/ 05 0/ 05 0/ 05 05 05 05 ]HURV ZRUGQ 05 05 0/ ]HURV 05 0/ ZRUGQ 05 ]HURV 05 ZRUGQ 05 0/ E /6%),567 05 E 0LFURSKRQHVFRQILJXUDWLRQ E 05 0/ 05 0/ 05 0/ 05 0/ ]HURV 05 0/ ZRUGQ 05 0/ ]HURV 05 0/ /6%),567 ZRUGQ 05 0/ E 06Y9 TDM configuration for PDM interface SAI_A TDM interface is internally connected to the PDM interface to get the microphone samples. The user application must configure the PDM interface as shown in Table 401 to ensure a good connection with the PDM interface. Table 401. TDM settings 2170/3178 Bit Fields Values Comments MODE 0b01 Mode must be MASTER receiver PRTCFG 0b00 Free protocol for TDM DS X To be adjusted according to the required data format, in accordance to the frame length and the number of slots (FRL and NBSLOT). See Table 402. LSBFIRST X This parameter can be used according to the wanted data format CKSTR 0 Signal transitions occur on the rising edge of the SCK_A bit clock. Signals are stable on the falling edge of the bit clock. MONO 0 Stereo mode FRL X To be adjusted according to the number of microphones (MICNBR). See Table 402. FSALL 0 Pulse width is one bit clock cycle DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Table 401. TDM settings (continued) Bit Fields Values Comments FSDEF 0 FS signal is a start of frame FSPOL 1 FS is active High FSOFF 0 FS is asserted on the first bit of slot 0 FBOFF 0 No offset on slot SLOTSZ 0 Slot size = data size NBSLOT X To be adjusted according to the required data format, in accordance to the slot size, and the frame length (FRL and DS). See Table 402. SLOTEN X To be adjusted according to NBSLOT NOMCK 1 No need to generate a master clock MCLK MCKDIV X Depends on the frequency provided to sai_a_ker_ck input. This parameter shall be adjusted to generate the proper bitstream clock frequency. See Table 402. Adjusting the bitstream clock rate To properly program the SAI TDM interface, the user application must take into account the settings given in Table 401, and follow the below rules: 1. Adjust the bit clock frequency (FSCK_A) according to the required frequency for the PDM bitstream clock, using the following formula: F SCK_A = F PDM_CK × ( MICNBR + 1 ) × 2 MICNBR can be 0,1,2 or 3 (0 = 2 microphones., see Section 51.5.10) 2. Set the frame length (FRL) using the following formula FRL = ( 16 × ( MICNBR + 1 ) ) – 1 3. Configure the slot size (DS) to a multiple of (FRL+1). DocID029587 Rev 3 2171/3178 2203 Serial audio interface (SAI) RM0433 up to 8 up to 6 48 kHz up to 4 up to 2 up to 8 up to 6 16 kHz up to 4 up to 2 Wanted bit clock SAI_CKn frequency (SCK_A) Frame sync (FS_A) frequency frequency 3.072 MHz 24.576 MHz 384 kHz NBSLOT Nber of Mic DS Microphone Sample rate FRL Table 402. Allowed TDM frame configuration(1) Comments 63 0b111 1 2 slots of 32 bits per frame 3.072 MHz 24.576 MHz 384 kHz 63 0b100 3 4 slots of 16 bits per frame 3.072 MHz 24.576 MHz 384 kHz 63 0b010 7 8 slots of 8 bits per frame 3.072 MHz 18.432 MHz 384 kHz 47 0b110 1 2 slots of 24 bits per frame 3.072 MHz 18.432 MHz 384 kHz 47 0b100 2 3 slots of 16 bits per frame 3.072 MHz 18.432 MHz 384 kHz 47 0b010 5 6 slots of 8 bits per frame 3.072 MHz 12.288 MHz 384 kHz 31 0b111 0 1 slot of 32 bits per frame 3.072 MHz 12.288 MHz 384 kHz 31 0b100 1 2 slots of 16 bits per frame 3.072 MHz 12.288 MHz 384 kHz 31 0b010 3 4 slots of 8 bits per frame 3.072 MHz 6.144 MHz 384 kHz 15 0b100 0 1 slots of 16 bits per frame 3.072 MHz 6.144 MHz 384 kHz 15 0b010 1 2 slots of 8 bits per frame 1.024 MHz 8.192 MHz 128 kHz 63 0b111 1 2 slots of 32 bits per frame 1.024 MHz 8.192 MHz 128 kHz 63 0b100 3 4 slots of 16 bits per frame 1.024 MHz 8.192 MHz 128 kHz 63 0b010 7 8 slots of 8 bits per frame 1.024 MHz 6.144 MHz 128 kHz 47 0b110 1 2 slots of 24 bits per frame 1.024 MHz 6.144 MHz 128 kHz 47 0b010 5 6 slots of 8 bits per frame 1.024 MHz 4.096 MHz 128 kHz 31 0b111 0 1 slot of 32 bits per frame 1.024 MHz 4.096 MHz 128 kHz 31 0b100 1 2 slots of 16 bits per frame 1.024 MHz 4.096 MHz 128 kHz 31 0b010 3 4 slots of 8 bits per frame 1.024 MHz 2.048 MHz 128 kHz 15 0b100 0 1 slot of 16 bits per frame 1.024 MHz 2.048 MHz 128 kHz 15 0b010 1 2 slots of 8 bits per frame 1. Refer to Table 401: TDM settings for additional information on TDM configuration. The sai_a_ker_ck clock frequency provided to the SAI should be a multiple of the SCK_A frequency, and MCKDIV should be programmed accordingly. 2. The table above gives allowed settings for a decimation ratio of 64. Adjusting the delay lines When the PDM interface is enabled, the application can adjust on-the-fly the delay cells of each microphone input via SAI_PDMDLY register. The new delays values will become effective after two TDM frames. 2172/3178 DocID029587 Rev 3 RM0433 51.3.11 Serial audio interface (SAI) AC’97 link controller The SAI is able to work as an AC’97 link controller. In this protocol: • The slot number and the slot size are fixed. • The frame synchronization signal is perfectly defined and has a fixed shape. To select this protocol, set PRTCFG[1:0] bits in the SAI_xCR1 register to 10. When AC’97 mode is selected, only data sizes of 16 or 20 bits can be used, otherwise the SAI behavior is not guaranteed. • NBSLOT[3:0] and SLOTSZ[1:0] bits are consequently ignored. • The number of slots is fixed to 13 slots. The first one is 16-bit wide and all the others are 20-bit wide (data slots). • FBOFF[4:0] bits in the SAI_xSLOTR register are ignored. • The SAI_xFRCR register is ignored. • The MCLK is not used. The FS signal from the block defined as asynchronous is configured automatically as an output, since the AC’97 controller link drives the FS signal whatever the master or slave configuration. Figure 649 shows an AC’97 audio frame structure. Figure 649. AC’97 audio frame )6 6', 7DJ 6'2 7DJ &0' &0' 3&0 3&0 /,1( 3&0 3&0 3&0 $''5 '$7$ /)5217 5)5217 '$& &(17(5 /6855 56855 67$786 67$786 3&0 3&0 $''5 '$7$ /()7 5,*+7 /,1( $'& 3&0 0,& 565 9' 565 9' 3&0 /)( /,1( '$& +6(7 '$& ,2 &75/ 565 /9' /,1( $'& +6(7 ,2 67$786 06 9 Note: In AC’97 protocol, bit 2 of the tag is reserved (always 0), so bit 2 of the TAG is forced to 0 level whatever the value written in the SAI FIFO. For more details about tag representation, refer to the AC’97 protocol standard. One SAI can be used to target an AC’97 point-to-point communication. Using two SAIs (for devices featuring two embedded SAIs) allows controlling three external AC’97 decoders as illustrated in Figure 650. In SAI1, the audio block A must be declared as asynchronous master transmitter whereas the audio block B is defined to be slave receiver and internally synchronous to the audio block A. The SAI2 is configured for audio block A and B both synchronous with the external SAI1 in slave receiver mode. DocID029587 Rev 3 2173/3178 2203 Serial audio interface (SAI) RM0433 Figure 650. Example of typical AC’97 configuration on devices featuring at least 2 embedded SAIs (three external AC’97 decoders) $&¶ /LQN&RQWUROOHU %LWFORFNSURYLGHU $XGLREORFN$ 3ULPDU\FRGHF 0DVWHU 6'$ ),)2 %ORFN% V\QFKURQRXVZLWK EORFN$ 7UDQVPLWWHU )6$ 6&/.$ &ORFN JHQHUDWRU 6GDWDBRXW 6\QF %LWBFON 6GDWDBLQ 6ODYH 6'% ),)2 5HFHLYHU )6% 6&/.% 6HFRQGDU\FRGHF $XGLREORFN% 6GDWDBRXW 6\QF %LWBFON 6$, $XGLREORFN$ 6ODYH 6GDWDBLQ 6'$ ),)2 6\QFKURQRXVZLWK RWKHU6$,FORFNV 5HFHLYHU )6$ 6&/.$ 6HFRQGDU\FRGHF &ORFN JHQHUDWRU 6ODYH ),)2 5HFHLYHU 6'% )6% 6&/.% 6GDWDBRXW 6\QF %LWBFON 6GDWDBLQ $XGLREORFN% 6$, 06Y9 In receiver mode, the SAI acting as an AC’97 link controller requires no FIFO request and so no data storage in the FIFO when the Codec ready bit in the slot 0 is decoded low. If bit CNRDYIE is enabled in the SAI_xIM register, flag CNRDY will be set in the SAI_xSR register and an interrupt is generated. This flag is dedicated to the AC’97 protocol. Clock generator programming in AC’97 mode In AC’97 mode, the frame length is fixed at 256 bits, and its frequency shall be set to 48 kHz. The formulas given in Section 51.3.8: SAI clock generator shall be used with FRL = 255, in order to generate the proper frame rate (FFS_x). 2174/3178 DocID029587 Rev 3 RM0433 51.3.12 Serial audio interface (SAI) SPDIF output The SPDIF interface is available in transmitter mode only. It supports the audio IEC60958. To select SPDIF mode, set PRTCFG[1:0] bit to 01 in the SAI_xCR1 register. For SPDIF protocol: • Only SD data line is enabled. • FS, SCK, MCLK I/Os pins are left free. • MODE[1] bit is forced to 0 to select the master mode in order to enable the clock generator of the SAI and manage the data rate on the SD line. • The data size is forced to 24 bits. The value set in DS[2:0] bits in the SAI_xCR1 register is ignored. • The clock generator must be configured to define the symbol-rate, knowing that the bit clock should be twice the symbol-rate. The data is coded in Manchester protocol. • The SAI_xFRCR and SAI_xSLOTR registers are ignored. The SAI is configured internally to match the SPDIF protocol requirements as shown in Figure 651. Figure 651. SPDIF format "LOCK . "LOCK . &RAME &RAME &RAME &RAME 6XEIUDPH % &KDQQHO$ : &KDQQHO% 0 &KDQQHO$ : &KDQQHO% 623' 3/0$ " - 7 '' '' 0 &KDQQHO$ : &KDQQHO% % '' ' '' 93 BIT DATA 8 &KDQQHO$ : &KDQQHO% &6 3TATUS BIT #HANNEL -36 A SPDIF block contains 192 frames. Each frame is composed of two 32-bit sub-frames, generally one for the left channel and one for the right channel. Each sub-frame is composed of a SOPD pattern (4-bit) to specify if the sub-frame is the start of a block (and so is identifying a channel A) or if it is identifying a channel A somewhere in the block, or if it is referring to channel B (see Table 403). The next 28 bits of channel information are composed of 24 bits data + 4 status bits. DocID029587 Rev 3 2175/3178 2203 Serial audio interface (SAI) RM0433 Table 403. SOPD pattern Preamble coding SOPD Description last bit is 0 last bit is 1 B 11101000 00010111 Channel A data at the start of block W 11100100 00011011 Channel B data somewhere in the block M 11100010 00011101 Channel A data The data stored in SAI_xDR has to be filled as follows: • SAI_xDR[26:24] contain the Channel status, User and Validity bits. • SAI_xDR[23:0] contain the 24-bit data for the considered channel. If the data size is 20 bits, then data shall be mapped on SAI_xDR[23:4]. If the data size is 16 bits, then data shall be mapped on SAI_xDR[23:8]. SAI_xDR[23] always represents the MSB. Figure 652. SAI_xDR register ordering 6$,B['5> @ &6 8 9 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 'DWD> @ 6WDWXV ELWV 06Y9 Note: The transfer is performed always with LSB first. The SAI first sends the adequate preamble for each sub-frame in a block. The SAI_xDR is then sent on the SD line (manchester coded). The SAI ends the sub-frame by transferring the Parity bit calculated as described in Table 404. Table 404. Parity bit calculation SAI_xDR[26:0] Parity bit P value transferred odd number of 0 0 odd number of 1 1 The underrun is the only error flag available in the SAI_xSR register for SPDIF mode since the SAI can only operate in transmitter mode. As a result, the following sequence should be 2176/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) executed to recover from an underrun error detected via the underrun interrupt or the underrun status bit: 1. Disable the DMA stream (via the DMA peripheral) if the DMA is used. 2. Disable the SAI and check that the peripheral is physically disabled by polling the SAIEN bit in SAI_xCR1 register. 3. Clear the COVRUNDR flag in the SAI_xCLRFR register. 4. Flush the FIFO by setting the FFLUSH bit in SAI_xCR2. The software needs to point to the address of the future data corresponding to a start of new block (data for preamble B). If the DMA is used, the DMA source base address pointer should be updated accordingly. 5. Enable again the DMA stream (DMA peripheral) if the DMA used to manage data transfers according to the new source base address. 6. Enable again the SAI by setting SAIEN bit in SAI_xCR1 register. Clock generator programming in SPDIF generator mode For the SPDIF generator, the SAI shall provide a bit clock equal to the symbol-rate. The table hereafter shows usual examples of symbol rates with respect to the audio sampling rate. Table 405. Audio sampling frequency versus symbol rates Audio Sampling Frequencies (FS) Symbol-rate 44.1 kHz 2.8224 MHz 48 kHz 3.072 MHz 96 kHz 6.144 MHz 192 kHz 12.288 MHz More generally, the relationship between the audio sampling rate (FS) and the bit-clock rate (FSCK_X) is given by the formula: 51.3.13 Specific features The SAI interface embeds specific features which can be useful depending on the audio protocol selected. These functions are accessible through specific bits of the SAI_xCR2 register. Mute mode The mute mode can be used when the audio sub-block is a transmitter or a receiver. Audio sub-block in transmission mode In transmitter mode, the mute mode can be selected at anytime. The mute mode is active for entire audio frames. The MUTE bit in the SAI_xCR2 register enables the mute mode when it is set during an ongoing frame. The mute mode bit is strobed only at the end of the frame. If it is set at this time, the mute mode is active at the beginning of the new audio frame and for a complete frame, until the next end of frame. The bit is then strobed to determine if the next frame will still be a mute frame. DocID029587 Rev 3 2177/3178 2203 Serial audio interface (SAI) RM0433 If the number of slots set through NBSLOT[3:0] bits in the SAI_xSLOTR register is lower than or equal to 2, it is possible to specify if the value sent in mute mode is 0 or if it is the last value of each slot. The selection is done via MUTEVAL bit in the SAI_xCR2 register. If the number of slots set in NBSLOT[3:0] bits in the SAI_xSLOTR register is greater than 2, MUTEVAL bit in the SAI_xCR2 is meaningless as 0 values are sent on each bit on each slot. The FIFO pointers are still incremented in mute mode. This means that data present in the FIFO and for which the mute mode is requested are discarded. Audio sub-block in reception mode In reception mode, it is possible to detect a mute mode sent from the external transmitter when all the declared and valid slots of the audio frame receive 0 for a given consecutive number of audio frames (MUTECNT[5:0] bits in the SAI_xCR2 register). When the number of MUTE frames is detected, the MUTEDET flag in the SAI_xSR register is set and an interrupt can be generated if MUTEDETIE bit is set in SAI_xCR2. The mute frame counter is cleared when the audio sub-block is disabled or when a valid slot receives at least one data in an audio frame. The interrupt is generated just once, when the counter reaches the value specified in MUTECNT[5:0] bits. The interrupt event is then reinitialized when the counter is cleared. Note: The mute mode is not available for SPDIF audio blocks. Mono/stereo mode In transmitter mode, the mono mode can be addressed, without any data preprocessing in memory, assuming the number of slots is equal to 2 (NBSLOT[3:0] = 0001 in SAI_xSLOTR). In this case, the access time to and from the FIFO will be reduced by 2 since the data for slot 0 is duplicated into data slot 1. To enable the mono mode, 1. Set MONO bit to 1 in the SAI_xCR1 register. 2. Set NBSLOT to 1 and SLOTEN to 3 in SAI_xSLOTR. In reception mode, the MONO bit can be set and is meaningful only if the number of slots is equal to 2 as in transmitter mode. When it is set, only slot 0 data will be stored in the FIFO. The data belonging to slot 1 will be discarded since, in this case, it is supposed to be the same as the previous slot. If the data flow in reception mode is a real stereo audio flow with a distinct and different left and right data, the MONO bit is meaningless. The conversion from the output stereo file to the equivalent mono file is done by software. Companding mode Telecommunication applications can require to process the data to be transmitted or received using a data companding algorithm. Depending on the COMP[1:0] bits in the SAI_xCR2 register (used only when TDM mode is selected), the application software can choose to process or not the data before sending it on SD serial output line (compression) or to expand the data after the reception on SD serial input line (expansion) as illustrated in Figure 653. The two companding modes supported are the µ-Law and the A-Law log which are a part of the CCITT G.711 recommendation. The companding standard used in the United States and Japan is the µ-Law. It supports 14 bits of dynamic range (COMP[1:0] = 10 in the SAI_xCR2 register). 2178/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) The European companding standard is A-Law and supports 13 bits of dynamic range (COMP[1:0] = 11 in the SAI_xCR2 register). Both µ-Law or A-Law companding standard can be computed based on 1’s complement or 2’s complement representation depending on the CPL bit setting in the SAI_xCR2 register. In µ-Law and A-Law standards, data are coded as 8 bits with MSB alignment. Companded data are always 8-bit wide. For this reason, DS[2:0] bits in the SAI_xCR1 register will be forced to 010 when the SAI audio block is enabled (SAIEN bit = 1 in the SAI_xCR1 register) and when one of these two companding modes selected through the COMP[1:0] bits. If no companding processing is required, COMP[1:0] bits should be kept clear. Figure 653. Data companding hardware in an audio block in the SAI 5HFHLYHUPRGH ELW02'(>@ LQ6$,B[&5 &203>@ ),)2 6' H[SDQG ELWVKLIWUHJLVWHU 7UDQVPLWWHUPRGH ELW02'(>@ LQ6$,B[&5 ),)2 FRPSUHVV 6' ELWVKLIWUHJLVWHU &203>@ 06 9 1. Not applicable when AC’97 or SPDIF are selected. Expansion and compression mode are automatically selected through the SAI_xCR2: • If the SAI audio block is configured to be a transmitter, and if the COMP[1] bit is set in the SAI_xCR2 register, the compression mode will be applied. • If the SAI audio block is declared as a receiver, the expansion algorithm will be applied. Output data line management on an inactive slot In transmitter mode, it is possible to choose the behavior of the SD line output when an inactive slot is sent on the data line (via TRIS bit). • Either the SAI forces 0 on the SD output line when an inactive slot is transmitted, or • The line is released in HI-z state at the end of the last bit of data transferred, to release the line for other transmitters connected to this node. It is important to note that the two transmitters cannot attempt to drive the same SD output pin simultaneously, which could result in a short circuit. To ensure a gap between transmissions, if the data is lower than 32-bit, the data can be extended to 32-bit by setting bit SLOTSZ[1:0] = 10 in the SAI_xSLOTR register. The SD output pin will then be tri-stated at the end of the LSB of the active slot (during the padding to 0 phase to extend the data to 32-bit) if the following slot is declared inactive. DocID029587 Rev 3 2179/3178 2203 Serial audio interface (SAI) RM0433 In addition, if the number of slots multiplied by the slot size is lower than the frame length, the SD output line will be tri-stated when the padding to 0 is done to complete the audio frame. Figure 654 illustrates these behaviors. Figure 654. Tristate strategy on SD output line on an inactive slot %LW75,6 LQWKH6$,B[&5DQGIUDPHOHQJWK QXPEHURIVORWV $XGLRIUDPH SCK 6ORWVL]H GDWDVL]H 3LOT /. VORW 6' RXWSXW 3LOT /&& 3LOT /&& $ATA 3LOT /. $ATA /. /. 3LOT N /. $ATA M 6ORWVL]H!GDWDVL]H VORW 3LOT /. 6' RXWSXW VORW 3LOT /&& 3LOT /&& $ATA $ATA 3LOT /. 3LOT /. 3LOT /&& 3LOT /&& 6' RXWSXW 3LOT /. $ATA /. /. /. /. 3LOT N /. $ATA M 3LOT N /. $ATA M %LW75,6 LQWKH6$,B[&5DQGIUDPHOHQJWK!QXPEHURIVORWV $XGLRIUDPH SCK 6ORWVL]H GDWDVL]H VORW 6' RXWSXW 3LOT /. 3LOT /&& 3LOT /&& $ATA /. 3LOT N /. $ATA M 6ORWVL]H!GDWDVL]H VORW 6' RXWSXW VORW 6' RXWSXW 3LOT /. 3LOT /&& 3LOT /&& $ATA 3LOT /. /. 3LOT /&& 3LOT /&& /. 3LOT N /. $ATA M /. $ATA M 06 9 When the selected audio protocol uses the FS signal as a start of frame and a channel side identification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed 2180/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) according to Figure 655 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and half frame length is higher than number of slots/2, and NBSLOT=6). Figure 655. Tristate on output data line in a protocol like I2S SCK 6ORWVL]H GDWDVL]H VORW 3LOT /. 6' RXWSXW 3LOT /&& $ATA 3LOT /. 3LOT /. $ATA $ATA 3LOT /&& 3LOT /. $ATA 6ORWVL]H!GDWDVL]H 3LOT /. VORW 6' RXWSXW 3LOT /&& $ATA 3LOT /. VORW 6' RXWSXW $ATA 3LOT /. $ATA 3LOT /&& 3LOT /. 3LOT /. 3LOT /&& $ATA 3LOT /. $ATA 3LOT /. $ATA 3LOT /&& 3LOT /. $ATA M 06 9 If the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD output line on Figure 654 and Figure 655 are replaced by a drive with a value of 0. 51.3.14 Error flags The SAI implements the following error flags: • FIFO overrun/underrun • Anticipated frame synchronization detection • Late frame synchronization detection • Codec not ready (AC’97 exclusively) • Wrong clock configuration in master mode. FIFO overrun/underrun (OVRUDR) The FIFO overrun/underrun bit is called OVRUDR in the SAI_xSR register. The overrun or underrun errors share the same bit since an audio block can be either receiver or transmitter and each audio block in a given SAI has its own SAI_xSR register. Overrun When the audio block is configured as receiver, an overrun condition may appear if data are received in an audio frame when the FIFO is full and not able to store the received data. In this case, the received data are lost, the flag OVRUDR in the SAI_xSR register is set and an interrupt is generated if OVRUDRIE bit is set in the SAI_xIM register. The slot number, from which the overrun occurs, is stored internally. No more data will be stored into the FIFO until it becomes free to store new data. When the FIFO has at least one data free, the SAI audio DocID029587 Rev 3 2181/3178 2203 Serial audio interface (SAI) RM0433 block receiver will store new data (from new audio frame) from the slot number which was stored internally when the overrun condition was detected. This avoids data slot dealignment in the destination memory (refer to Figure 656). The OVRUDR flag is cleared when COVRUDR bit is set in the SAI_xCLRFR register. Figure 656. Overrun detection error ([DPSOH ),)2RYHUUXQRQ6ORW $XGLRIUDPH $XGLRIUDPH VFN GDWD 6ORW21 6ORW21 3LOT /. 6ORW21 6ORW21 21 6ORWQ21 ),)2IXOO 'DWDVWRUHGDJDLQLQ),)2 5HFHLYHGGDWDGLVFDUGHG 2958'5 &2958'5 06 9 Underrun An underrun may occur when the audio block in the SAI is a transmitter and the FIFO is empty when data need to be transmitted. If an underrun is detected, the slot number for which the event occurs is stored and MUTE value (00) is sent until the FIFO is ready to transmit the data corresponding to the slot for which the underrun was detected (refer to Figure 657). This avoids desynchronization between the memory pointer and the slot in the audio frame. The underrun event sets the OVRUDR flag in the SAI_xSR register and an interrupt is generated if the OVRUDRIE bit is set in the SAI_xIM register. To clear this flag, set COVRUDR bit in the SAI_xCLRFR register. The underrun event can occur when the audio sub-block is configured as master or slave. Figure 657. FIFO underrun event ([DPSOH ),)2XQGHUUXQRQ6ORW $XGLRIUDPH $XGLRIUDPH VFN 3LOT SIZE DATA SIZE GDWD 6' RXWSXW 6ORW21 087( 087( 087( 6ORW21 21 6ORW21 ),)2HPSW\ 29581' 29581' -36 2182/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Anticipated frame synchronization detection (AFSDET) The AFSDET flag is used only in slave mode. It is never asserted in master mode. It indicates that a frame synchronization (FS) has been detected earlier than expected since the frame length, the frame polarity, the frame offset are defined and known. Anticipated frame detection sets the AFSDET flag in the SAI_xSR register. This detection has no effect on the current audio frame which is not sensitive to the anticipated FS. This means that “parasitic” events on signal FS are flagged without any perturbation of the current audio frame. An interrupt is generated if the AFSDETIE bit is set in the SAI_xIM register. To clear the AFSDET flag, CAFSDET bit must be set in the SAI_xCLRFR register. To resynchronize with the master after an anticipated frame detection error, four steps are required: Note: 1. Disable the SAI block by resetting SAIEN bit in SAI_xCR1 register. To make sure the SAI is disabled, read back the SAIEN bit and check it is set to 0. 2. Flush the FIFO via FFLUS bit in SAI_xCR2 register. 3. Enable again the SAI peripheral (SAIEN bit set to 1). 4. The SAI block will wait for the assertion on FS to restart the synchronization with master. The SAIEN flag is not asserted in AC’97 mode since the SAI audio block acts as a link controller and generates the FS signal even when declared as slave.It has no meaning in SPDIF mode since the FS signal is not used. Late frame synchronization detection The LFSDET flag in the SAI_xSR register can be set only when the SAI audio block operates as a slave. The frame length, the frame polarity and the frame offset configuration are known in register SAI_xFRCR. If the external master does not send the FS signal at the expecting time thus generating the signal too late, the LFSDET flag is set and an interrupt is generated if LFSDETIE bit is set in the SAI_xIM register. The LFSDET flag is cleared when CLFSDET bit is set in the SAI_xCLRFR register. The late frame synchronization detection flag is set when the corresponding error is detected. The SAI needs to be resynchronized with the master (see sequence described in Section : Anticipated frame synchronization detection (AFSDET)). In a noisy environment, glitches on the SCK clock may be wrongly detected by the audio block state machine and shift the SAI data at a wrong frame position. This event can be detected by the SAI and reported as a late frame synchronization detection error. There is no corruption if the external master is not managing the audio data frame transfer in continuous mode, which should not be the case in most applications. In this case, the LFSDET flag will be set. Note: The LFSDET flag is not asserted in AC’97 mode since the SAI audio block acts as a link controller and generates the FS signal even when declared as slave.It has no meaning in SPDIF mode since the signal FS is not used by the protocol. DocID029587 Rev 3 2183/3178 2203 Serial audio interface (SAI) RM0433 Codec not ready (CNRDY AC’97) The CNRDY flag in the SAI_xSR register is relevant only if the SAI audio block is configured to operate in AC’97 mode (PRTCFG[1:0] = 10 in the SAI_xCR1 register). If CNRDYIE bit is set in the SAI_xIM register, an interrupt is generated when the CNRDY flag is set. CNRDY is asserted when the Codec is not ready to communicate during the reception of the TAG 0 (slot0) of the AC’97 audio frame. In this case, no data will be automatically stored into the FIFO since the Codec is not ready, until the TAG 0 indicates that the Codec is ready. All the active slots defined in the SAI_xSLOTR register will be captured when the Codec is ready. To clear CNRDY flag, CCNRDY bit must be set in the SAI_xCLRFR register. Wrong clock configuration in master mode (with NOMCK = 0) When the audio block operates as a master (MODE[1] = 0) and NOMCK bit is equal to 0, the WCKCFG flag is set as soon as the SAI is enabled if the following conditions are met: • (FRL+1) is not a power of 2, and • (FRL+1) is not between 8 and 256. MODE, NOMCK, and SAIEN bits belong to SAI_xCR1 register and FRL to SAI_xFRCR register. If WCKCFGIE bit is set, an interrupt is generated when WCKCFG flag is set in the SAI_xSR register. To clear this flag, set CWCKCFG bit in the SAI_xCLRFR register. When WCKCFG bit is set, the audio block is automatically disabled, thus performing a hardware clear of SAIEN bit. 51.3.15 Disabling the SAI The SAI audio block can be disabled at any moment by clearing SAIEN bit in the SAI_xCR1 register. All the already started frames are automatically completed before the SAI is stops working. SAIEN bit remains High until the SAI is completely switched-off at the end of the current audio frame transfer. If an audio block in the SAI operates synchronously with the other one, the one which is the master must be disabled first. 51.3.16 SAI DMA interface To free the CPU and to optimize bus bandwidth, each SAI audio block has an independent DMA interface to read/write from/to the SAI_xDR register (to access the internal FIFO). There is one DMA channel per audio sub-block supporting basic DMA request/acknowledge protocol. To configure the audio sub-block for DMA transfer, set DMAEN bit in the SAI_xCR1 register. The DMA request is managed directly by the FIFO controller depending on the FIFO threshold level (for more details refer to Section 51.3.9: Internal FIFOs). DMA transfer direction is linked to the SAI audio sub-block configuration: 2184/3178 • If the audio block operates as a transmitter, the audio block FIFO controller outputs a DMA request to load the FIFO with data written in the SAI_xDR register. • If the audio block is operates as a receiver, the DMA request is related to read operations from the SAI_xDR register. DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Follow the sequence below to configure the SAI interface in DMA mode: 1. Configure SAI and FIFO threshold levels to specify when the DMA request will be launched. 2. Configure SAI DMA channel. 3. Enable the DMA. 4. Enable the SAI interface. Note: Before configuring the SAI block, the SAI DMA channel must be disabled. 51.4 SAI interrupts The SAI supports 7 interrupt sources as shown in Table 406. Table 406. SAI interrupt sources Interrupt source Interrupt group Audio block mode Interrupt enable Interrupt clear Depends on: FREQ FREQ – FIFO threshold setting (FLVL bits in SAI_xCR2) FREQIE in SAI_xIM – Communication direction (transmitter register or receiver) Master or slave Receiver or transmitter For more details refer to Section 51.3.9: Internal FIFOs OVRUDR ERROR Master or slave Receiver or transmitter OVRUDRIE in SAI_xIM register COVRUDR = 1 in SAI_xCLRFR register AFSDET ERROR Slave (not used in AC’97 mode and SPDIF mode) AFSDETIE in SAI_xIM register CAFSDET = 1 in SAI_xCLRFR register LFSDET ERROR Slave (not used in AC’97 mode and SPDIF mode) LFSDETIE in SAI_xIM register CLFSDET = 1 in SAI_xCLRFR register CNRDY ERROR Slave (only in AC’97 mode) CNRDYIE in SAI_xIM register CCNRDY = 1 in SAI_xCLRFR register MUTEDET MUTE Master or slave Receiver mode only MUTEDETIE in SAI_xIM register CMUTEDET = 1 in SAI_xCLRFR register WCKCFG ERROR Master with NOMCK = 0 in WCKCFGIE in SAI_xCR1 register SAI_xIM register CWCKCFG = 1 in SAI_xCLRFR register Follow the sequence below to enable an interrupt: 1. Disable SAI interrupt. 2. Configure SAI. 3. Configure SAI interrupt source. 4. Enable SAI. DocID029587 Rev 3 2185/3178 2203 Serial audio interface (SAI) RM0433 51.5 SAI registers 51.5.1 Global configuration register (SAI_GCR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNCOUT[1:0] rw rw SYNCIN[1:0] rw rw Bits 31:6 Reserved, must be kept at reset value. Bits 5:4 SYNCOUT[1:0]: Synchronization outputs These bits are set and cleared by software. 00: No synchronization output signals. SYNCOUT[1:0] should be configured as “No synchronization output signals” when audio block is configured as SPDIF 01: Block A used for further synchronization for others SAI 10: Block B used for further synchronization for others SAI 11: Reserved. These bits must be set when both audio block (A and B) are disabled. Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 SYNCIN[1:0]: Synchronization inputs These bits are set and cleared by software. Refer to for information on how to program this field. These bits must be set when both audio blocks (A and B) are disabled. They are meaningful if one of the two audio blocks is defined to operate in synchronous mode with an external SAI (SYNCEN[1:0] = 10 in SAI_ACR1 or in SAI_BCR1 registers). 51.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1) Address offset: Block A: 0x004 Address offset: Block B: 0x024 Reset value: 0x0000 0040 31 30 29 28 27 26 Res. Res. Res. Res. Res. OSR rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. OUTD MONO RIV rw 2186/3178 rw SYNCEN[1:0] rw rw 25 24 23 22 21 20 MCKDIV[5:0] CKSTR LSBFIRST rw rw DS[2:0] rw rw DocID029587 Rev 3 Res. rw 19 18 NOMCK Res. 2 17 16 DMAEN SAIEN rw rw 1 0 PRTCFG[1:0] MODE[1:0] rw rw rw rw RM0433 Serial audio interface (SAI) Bits 31:27 Reserved, must be kept at reset value. Bit 26 OSR: Oversampling ratio for master clock 0: Master clock frequency = FFS x 256 1: Master clock frequency = FFS x 512 Bits 25:20 MCKDIV[5:0]: Master clock divider These bits are set and cleared by software. 000000: Divides by 1 the kernel clock input (sai_x_ker_ck). Otherwise, The master clock frequency is calculated according to the formula given in Section 51.3.8: SAI clock generator. These bits have no meaning when the audio block is slave. They have to be configured when the audio block is disabled. Bit 19 NOMCK: No divider This bit is set and cleared by software. 0: Master clock generator is enabled 1: Master clock generator is disabled. The clock divider controlled by MCKDIV can still be used to generate the bit clock. Bit 18 Reserved, must be kept at reset value. Bit 17 DMAEN: DMA enable This bit is set and cleared by software. 0: DMA disabled 1: DMA enabled Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. Bit 16 SAIEN: Audio block enable This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows controlling the state of the SAI audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. 0: SAI audio block disabled 1: SAI audio block enabled. Note: When the SAI block (A or B) is configured in master mode, the clock must be present on the SAI block input before setting SAIEN bit. Bits 15:14 Reserved, must be kept at reset value. Bit 13 OUTDRIV: Output drive This bit is set and cleared by software. 0: Audio block output driven when SAIEN is set 1: Audio block output driven immediately after the setting of this bit. Note: This bit has to be set before enabling the audio block and after the audio block configuration. Bit 12 MONO: Mono mode This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section : Mono/stereo mode for more details. 0: Stereo mode 1: Mono mode. DocID029587 Rev 3 2187/3178 2203 Serial audio interface (SAI) RM0433 Bits 11:10 SYNCEN[1:0]: Synchronization enable These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. 00: audio sub-block in asynchronous mode. 01: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 10: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode. 11: Reserved Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. Bit 9 CKSTR: Clock strobing edge This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 0: Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge. 1: Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge. Bit 8 LSBFIRST: Least significant bit first This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC’97 audio protocol since AC’97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 0: Data are transferred with MSB first 1: Data are transferred with LSB first Bits 7:5 DS[2:0]: Data size These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 000: Reserved 001: Reserved 010: 8 bits 011: 10 bits 100: 16 bits 101: 20 bits 110: 24 bits 111: 32 bits 2188/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Bit 4 Reserved, must be kept at reset value. Bits 3:2 PRTCFG[1:0]: Protocol configuration These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 00: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register. 01: SPDIF protocol 10: AC’97 protocol 11: Reserved Bits 1:0 MODE[1:0]: SAIx audio block mode These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. 00: Master transmitter 01: Master receiver 10: Slave transmitter 11: Slave receiver Note: When the audio block is configured in SPDIF mode, the master transmitter mode is forced (MODE[1:0] = 00). In Master transmitter mode, the audio block starts generating the FS and the clocks immediately. 51.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2) Address offset: Block A: 0x008 Address offset: Block B: 0x028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP[1:0] rw rw CPL rw MUTECNT[5:0] rw rw rw rw rw rw MUTE VAL MUTE TRIS F FLUSH rw rw rw w DocID029587 Rev 3 FTH rw rw rw 2189/3178 2203 Serial audio interface (SAI) RM0433 Bits 31:16 Reserved, must be kept at reset value. Bits 15:14 COMP[1:0]: Companding mode. These bits are set and cleared by software. The µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section : Companding mode for more details. 00: No companding algorithm 01: Reserved. 10: µ-Law algorithm 11: A-Law algorithm Note: Companding mode is applicable only when TDM is selected. Bit 13 CPL: Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode 0: 1’s complement representation. 1: 2’s complement representation. Note: This bit has effect only when the companding mode is µ-Law algorithm or A-Law algorithm. Bits 12:7 MUTECNT[5:0]: Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section : Mute mode for more details. Bit 6 MUTEVAL: Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section : Mute mode for more details. 0: Bit value 0 is sent during the mute mode. 1: Last values are sent during the mute mode. Note: This bit is meaningless and should not be used for SPDIF audio blocks. Bit 5 MUTE: Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section : Mute mode for more details. 0: No mute mode. 1: Mute mode enabled. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 2190/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Bit 4 TRIS: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section : Output data line management on an inactive slot for more details. 0: SD output line is still driven by the SAI when a slot is inactive. 1: SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive. Bit 3 FFLUSH: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 0: No FIFO flush. 1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interruption must be disabled Bits 2:0 FTH: FIFO threshold. This bit is set and cleared by software. 000: FIFO empty 001: ¼ FIFO 010: ½ FIFO 011: ¾ FIFO 100: FIFO full 101: Reserved 110: Reserved 111: Reserved 51.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR) Address offset: Block A: 0x00C Address offset: Block B: 0x02C Reset value: 0x0000 0007 Note: This register has no meaning in AC’97 and SPDIF audio protocol 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw Res. FSALL[6:0] rw rw rw rw rw 18 17 16 FSOFF FSPOL FSDEF FRL[7:0] rw rw rw rw DocID029587 Rev 3 rw rw 2191/3178 2203 Serial audio interface (SAI) RM0433 Bits 31:19 Reserved, must be kept at reset value. Bit 18 FSOFF: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 0: FS is asserted on the first bit of the slot 0. 1: FS is asserted one bit before the first bit of the slot 0. Bit 17 FSPOL: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 0: FS is active low (falling edge) 1: FS is active high (rising edge) Bit 16 FSDEF: Frame synchronization definition. This bit is set and cleared by software. 0: FS signal is a start frame signal 1: FS signal is a start of frame signal + channel side identification When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC’97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. Bit 15 Reserved, must be kept at reset value. Bits 14:8 FSALL[6:0]: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC’97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. Bits 7:0 FRL[7:0]: Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NOMCK = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC’97 or SPDIF audio block configuration. 2192/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) 51.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR) Address offset: Block A: 0x010 Address offset: Block B: 0x030 Reset value: 0x0000 0000 Note: 31 This register has no meaning in AC’97 and SPDIF audio protocol 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SLOTEN[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. rw rw NBSLOT[3:0] rw rw rw SLOTSZ[1:0] rw rw rw Res. FBOFF[4:0] rw rw rw Bits 31:16 SLOTEN[15:0]: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). 0: Inactive slot. 1: Active slot. The slot must be enabled when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. Bits 15:12 Reserved, must be kept at reset value. Bits 11:8 NBSLOT[3:0]: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. DocID029587 Rev 3 2193/3178 2203 Serial audio interface (SAI) RM0433 Bits 7:6 SLOTSZ[1:0]: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section : Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. 00: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register). 01: 16-bit 10: 32-bit 11: Reserved Bit 1 Reserved, must be kept at reset value. Bits 4:0 FBOFF[4:0]: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. 51.5.6 Interrupt mask register 2 (SAI_AIM / SAI_BIM) Address offset: block A: 0x014 Address offset: block B: 0x034 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. LFSDET AFSDET CNRDY FREQ WCKCFG MUTEDET OVRUDR IE IE IE IE IE IE IE rw rw rw rw rw rw rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 LFSDETIE: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC’97, SPDIF mode or when the audio block operates as a master. Bit 5 AFSDETIE: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC’97, SPDIF mode or when the audio block operates as a master. 2194/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Bit 4 CNRDYIE: Codec not ready interrupt enable (AC’97). This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC’97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC’97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. Bit 3 FREQIE: FIFO request interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, Bit 2 WCKCFGIE: Wrong clock configuration interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NOMCK = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. Bit 1 MUTEDETIE: Mute detection interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. Bit 0 OVRUDRIE: Overrun/underrun interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 51.5.7 Status register (SAI_ASR / SAI_BSR) Address offset: block A: 0x018 Address offset: block B: 0x038 Reset value: 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. LFSDET AFSDET CNRDY r r DocID029587 Rev 3 r FREQ r 18 17 16 FLVL r r r 2 1 0 WCKCFG MUTEDET OVRUDR r r r 2195/3178 2203 Serial audio interface (SAI) RM0433 Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 FLVL: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: 000: FIFO empty 001: FIFO <= ¼ but not empty 010: ¼ < FIFO <= ½ 011: ½ < FIFO <= ¾ 100: ¾ < FIFO but not full 101: FIFO full If SAI block is configured as receiver: 000: FIFO empty 001: FIFO < ¼ but not empty 010: ¼ <= FIFO < ½ 011: ½ =< FIFO < ¾ 100: ¾ =< FIFO but not full 101: FIFO full Bits 15:7 Reserved, must be kept at reset value. Bit 6 LFSDET: Late frame synchronization detection. This bit is read only. 0: No error. 1: Frame synchronization signal is not present at the right time. This flag can be set only if the audio block is configured in slave mode. It is not used in AC’97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register Bit 5 AFSDET: Anticipated frame synchronization detection. This bit is read only. 0: No error. 1: Frame synchronization signal is detected earlier than expected. This flag can be set only if the audio block is configured in slave mode. It is not used in AC’97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. Bit 4 CNRDY: Codec not ready. This bit is read only. 0: External AC’97 Codec is ready 1: External AC’97 Codec is not ready This bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 2196/3178 DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Bit 3 FREQ: FIFO request. This bit is read only. 0: No FIFO request. 1: FIFO request to read or to write the SAI_xDR. The request depends on the audio block configuration: – If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. – If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. Bit 2 WCKCFG: Wrong clock configuration flag. This bit is read only. 0: Clock configuration is correct 1: Clock configuration does not respect the rule concerning the frame length specification defined in Section 51.3.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register) This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NOMCK = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. Bit 1 MUTEDET: Mute detection. This bit is read only. 0: No MUTE detection on the SD input line 1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. Bit 0 OVRUDR: Overrun / underrun. This bit is read only. 0: No overrun/underrun error. 1: Overrun/underrun error detection. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 51.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR) Address offset: block A: 0x01C Address offset: block B: 0x03C Reset value: 0x0000 0000 31 Res. 15 Res. 30 29 28 27 26 Res. Res. Res. Res. Res. 14 13 12 11 10 Res. Res. Res. Res. Res. 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CLFSDET CAFSDET w w DocID029587 Rev 3 CCNRDY w Res. CMUTE COVRUD CWCKCFG DET R w w w 2197/3178 2203 Serial audio interface (SAI) RM0433 Bits 31:7 Reserved, must be kept at reset value. Bit 6 CLFSDET: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC’97or SPDIF mode Reading this bit always returns the value 0. Bit 5 .CAFSDET: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC’97or SPDIF mode. Reading this bit always returns the value 0. Bit 4 CCNRDY: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. Bit 3 Reserved, must be kept at reset value. Bit 2 CWCKCFG: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NOMCK = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. Bit 1 CMUTEDET: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. Bit 0 COVRUDR: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 51.5.9 Data register (SAI_ADR / SAI_BDR) Address offset: block A: 0x020 Address offset: block B: 0x040 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATA[15:0] rw 2198/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Serial audio interface (SAI) Bits 31:0 DATA[31:0]: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 51.5.10 PDM control register (SAI_PDMCR) Address offset: 0x0044 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. PDMEN CKEN4 CKEN3 CKEN2 CKEN1 (1) (1) (1) (1) rw rw rw rw MICNBR[1:0] (1) rw rw rw 1. It is not recommended to configure these fields when PDMEN = 1 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 Reserved, must be kept at reset value. Bit 11 CKEN4: Clock enable of bitstream clock number 4 This bit is set and cleared by software. 0: SAI_CK4 clock disabled 1: SAI_CK4 clock enabled Bit 10 CKEN3: Clock enable of bitstream clock number 3 This bit is set and cleared by software. 0: SAI_CK3 clock disabled 1: SAI_CK3 clock enabled Bit 9 CKEN2: Clock enable of bitstream clock number 2 This bit is set and cleared by software. 0: SAI_CK2 clock disabled 1: SAI_CK2 clock enabled Bit 8 CKEN1: Clock enable of bitstream clock number 1 This bit is set and cleared by software. 0: SAI_CK1 clock disabled 1: SAI_CK1 clock enabled Bits 7:6 Reserved, must be kept at reset value. DocID029587 Rev 3 2199/3178 2203 Serial audio interface (SAI) RM0433 Bits 5:4 MICNBR: Number of microphones This bit is set and cleared by software. 0b00: Configuration with 2 microphones 0b01: Configuration with 4 microphones 0b10: Configuration with 6 microphones 0b11: Configuration with 8 microphones Bits 3:1 Reserved, must be kept at reset value. Bit 0 PDMEN: PDM enable This bit is set and cleared by software. This bit allows to control the state of the PDM interface block. Make sure that the SAI in already operating in TDM master mode before enabling the PDM interface. 0: PDM interface disabled 1: PDM interface enabled 51.5.11 PDM delay register (SAI_PDMDLY) Address offset: 0x0048 Reset value: 0x0000 0000 31 30 Res. 29 28 DLYM4R[2:0] 27 26 Res. 14 Res. 13 DLYM2R[2:0] rw 24 DLYM4L[2:0] rw 15 25 23 22 Res. 11 Res. 10 9 7 Res. rw Bit 31 Reserved, must be kept at reset value. Bits 30:28 DLYM4R: Delay line for second microphone of pair 4 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly. Bit 27 Reserved, must be kept at reset value. Bits 26:24 DLYM4L: Delay line for first microphone of pair 4 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 of TSAI_CK periods This field can be changed on-the-fly. Bit 23 Reserved, must be kept at reset value. 2200/3178 19 18 Res. DocID029587 Rev 3 6 5 DLYM1R[2:0] rw 17 16 DLYM3L[2:0] rw 8 DLYM2L[2:0] 20 DLYM3R[2:0] rw 12 21 rw 4 3 Res. 2 1 DLYM1L[2:0] rw 0 RM0433 Serial audio interface (SAI) Bits 22:20 DLYM3R: Delay line for second microphone of pair 3 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly. Bit 19 Reserved, must be kept at reset value. Bits 18:16 DLYM3L: Delay line for first microphone of pair 3 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly. Bit 15 Reserved, must be kept at reset value. Bits 14:12 DLYM2R: Delay line for second microphone of pair 2 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly. Bit 11 Reserved, must be kept at reset value. Bits 10:8 DLYM2L: Delay line for first microphone of pair 2 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly. Bit 7 Reserved, must be kept at reset value. DocID029587 Rev 3 2201/3178 2203 Serial audio interface (SAI) RM0433 Bits 6:4 DLYM1R: Delay line adjust for second microphone of pair 1 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly. Bit 3 Reserved, must be kept at reset value. Bits 2:0 DLYM1L: Delay line adjust for first microphone of pair 1 This bit is set and cleared by software. 0b000: No delay 0b001: Delay of 1 TSAI_CK period 0b010: Delay of 2 TSAI_CK periods ... 0b111: Delay of 7 TSAI_CK periods This field can be changed on-the-fly.0 51.5.12 SAI register map The following table summarizes the SAI registers. 2202/3178 FSDEF DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 SYNCIN[1:0] Res. Res.. 0 0 0 0 FSALL[6:0] 0 0 MODE[1:0] PRTCFG[1:0] 0 0 0 0 0 FTH MUTECN[5:0] 1 FFLUS 0 Res. 0 TRIS 0 DS[2:0] LSBFIRST 0 0 MUTE 0 0 0 MUTE VAL 0 SYNCEN[1:0] 0 Res. FSPOL 0 Res. Res. Res. 0 0 CKSTR Res. Res. 0 MONO Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSOFF Reset value Res. SAI_xFRCR Res. 0x000C or 0x002C 0 Res. Reset value OUTDRIV Res. 0 CPL Res. 0 COMP[1:0] 0 SAIEN 0 Res. 0 DMAEN 0 Res. 0 Res. 0 Res. NOMCK MCKDIV[3:0] 0 Res. OSR 0 Res. Res. Res. Res. SAI_xCR2 Res. 0x0008 or 0x0028 Res. Reset value Res. Res. Res. Res. SAI_xCR1 Res. 0x0004 or 0x0024 0 Res. Reset value SYNCOUT[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SAI_GCR Res. 0x0000 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 407. SAI register map and reset values 0 0 0 1 1 1 FRL[7:0] 0 0 0 0 0 0 0 0x0048 SAI_PDMDLY Reset value 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 SAI_PDMCR Res. Res. Res. 0 0 0 CKEN4 0 CKEN3 CKEN2 0 CKEN1 Res. 0 Res. 0 Reset value DATA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDR 1 MUTEDET 0 0 0 0 0 0 0 0 Res. 0 PDMEN OVRUDR 0 MUTEDET 0 FREQ 0 WCKCFG 0 Res. 0 WCKCFG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AFSDETIE CNRDYIE FREQIE WCKCFG MUTEDET OVRUDRIE Res. Res. Res. Res. Res. LFSDET Reset value Res. Res. 0 Res. Res. 0 CNRDY Res. 0 AFSDET Res. 0 LFSDET Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. SAI_xIM Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 DLYM1L[2:0] 0 Res. 0 Res. FLVL[2:0] 0 Res. 0 Res. 0 Res. 0 CNRDY 0 Res. 0 Res. Res. 0 CAFSDET 0 Res. Res. Res. 0 MICNBR[1:0] 0 Res. Res. Res. 0 DLYM1R[2:0] 0 Res. Res. Res. 0 LFSDET 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 DLYM2L[2:0] 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Reset value Res. Res. SLOTSZ[1:0} NBSLOT[3:0] Res. Res. Res. Res. SLOTEN[15:0] DLYM2R[2:0] 0 Res. SAI_xDR Res. 0 Res. Res. Reset value DLYM3L[2:0] Res. DLYM3R[2:0] 0 Res. Res. Res. Res. Res. SAI_xSLOTR Res. DLYM4L[2:0] Res. Reset value 0 Res. 0x0044 Reset value Res. 0x0020 or 0x0040 SAI_xCLRFR DLYM4R[2:0] 0x001C or 0x003C SAI_xSR Res. 0x0018 or 0x0038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. 0x0014 or 0x0034 Res. 0x0010 or 0x0030 Res. Offset Res. RM0433 Serial audio interface (SAI) Table 407. SAI register map and reset values (continued) FBOFF[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2 on page 105 for the register boundary addresses. 2203/3178 2203 SPDIF receiver interface (SPDIFRX) RM0433 52 SPDIF receiver interface (SPDIFRX) 52.1 SPDIFRX interface introduction The SPDIFRX interface handles S/PDIF audio protocol. 52.2 52.3 SPDIFRX main features • Up to 4 inputs available • Automatic symbol rate detection • Maximum symbol rate: 12.288 MHz • Stereo stream from 8 to 192 kHz supported • Supports Audio IEC-60958 and IEC-61937, consumer applications • SOPDs B, M and W insertion inside S/PDIF flow • Parity bit management • Communication using DMA for audio samples • Communication using DMA for control and user channel information • Interrupt capabilities SPDIFRX functional description The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS. The receiver provides all the necessary features to detect the symbol rate, and decode the incoming data. It is possible to use a dedicated path for the user and channel information in order to ease the interface handling. Figure 658 shows a simplified block diagram. The SPDIFRX_DC block is responsible of the decoding of the S/PDIF stream received from SPDIFRX_IN[4:1] inputs. This block re-sample the incoming signal, decode the manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the REG_IF part, decoded data, and associated status flags. This peripheral can be fully controlled via the APB1 bus, and can handle two DMA channels: • A DMA channel dedicated to the transfer of audio samples • A DMA channel dedicated to the transfer of IEC60958 channel status and user information Interrupt services are also available either as an alternative function to the DMA, or for signaling error or key status of the peripheral. The SPDIFRX also offers a signal named spdifrx_frame_sync, which toggles every time that a sub-frame’s preamble is detected. So the duty cycle will be 50%, and the frequency equal to the frame rate. This signal can be connected to timer events, in order to compute frequency drift. In addition the SPDIFRX also provides a signal named spdifrx_symb_ck toggling at the symbol rate. 2204/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 658. SPDIFRX block diagram 63',)5;B65 63',)5;B,)&5 63',)5;B,1 63',)5;B,1 FWUO FK 6<1& ELW$3% EXV 63',)5;B&65 63',)5;B)( 63',)5;B&5 63',)5;B,05 5HV\QF (GJHGHWHFWLRQ 5;B%8) ELWV GDWD 63',)5;B'(& 5HJLVWHU LQWHUIDFH 63',)5;B'5 %LSKDVHDQGWUDQVLWLRQ GHFRGHU 63',)5;B'& 63',)5;B6(4 VSGLIU[BSFON 63',)5; 63',)GDWDSDFNLQJDQG VHTXHQFHU VSGLIU[BNHUBFN 63',)5;B,1>Q@ 63',)5;B',5 VSGLIU[BLW VSGLIU[BGDWBGPD VSGLIU[BFWUOBGPD ,54 LQWHUIDFH '0$ LQWHUIDFH VSGLIU[BV\PEBFN VSGLIU[BIUDPHBV\QF VSGLIU[BSFON FORFNGRPDLQ VSGLIBNHUBFNFORFNGRPDLQ 06Y 9 1. ‘n’ is fixed to 4. 52.3.1 SPDIFRX pins and internal signals Table 408 lists the SPDIFRX internal input/output signals, Table 409 the SPDIFRX pins (alternate functions). Table 408. SPDIFRX internal input/output signals Signal name Signal type Description spdifrx_ker_ck Digital input SPDIFRX kernel clock spdifrx_pclk Digital input SPDIFRX register interface clock spdifrx_it Digital output spdifrx_dat_dma Digital input/output SPDIFRX DMA request (and acknowledge) for data transfer spdifrx_ctrl_dma Digital input/output SPDIFRX DMA request (and acknowledge) for channel status and user information transfer spdifrx_frame_sync Digital output SPDIFRX frame rate synchronization signal spdifrx_symb_ck Digital output SPDIFRX channel symbol clock SPDIFRX global interrupt Table 409. SPDIFRX pins Signal name Signal type Description SPDIFRX_IN1 Digital input Input 1 for S/PDIF signal SPDIFRX_IN2 Digital input Input 2 for S/PDIF signal SPDIFRX_IN3 Digital input Input 3 for S/PDIF signal SPDIFRX_IN4 Digital input Input 4 for S/PDIF signal DocID029587 Rev 3 2205/3178 2242 SPDIF receiver interface (SPDIFRX) 52.3.2 RM0433 S/PDIF protocol (IEC-60958) S/PDIF block A S/PDIF frame is composed of two sub-frames (see Figure 660). Each sub-frame contains 32 bits (or time slots): • Bits 0 to 3 carry one of the synchronization preambles • Bits 4 to 27 carry the audio sample word in linear 2's complement representation. The most significant bit (MSB) is carried by bit 27. When a 20-bit coding range is used, bits 8 to 27 carry the audio sample word with the LSB in bit 8. • Bit 28 (validity bit “V”) indicates if the data is valid (for converting it to analog for example) • Bit 29 (user data bit “U”) carries the user data information like the number of tracks of a Compact Disk. • Bit 30 (channel status bit “C”) carries the channel status information like sample rate and protection against copy. • Bit 31 (parity bit “P”) carries a parity bit such that bits 4 to 31 inclusive carry an even number of ones and an even number of zeroes (even parity). Figure 659. S/PDIF Sub-Frame Format 6\QF3UHDPEOH ' ' ' ' ' ' ' 9 8 & 3 /6E 06E 6\QFKURQL]DWLRQ $XGLRVDPSOHXSWRELWV W\SH%0RU: 6WDWXVELWV LQIRUPDWLRQELWV 06Y 9 For linear coded audio applications, the first sub-frame (left or “A” channel in stereophonic operation and primary channel in monophonic operation) normally starts with preamble “M”. However, the preamble changes to preamble “B” once every 192 frames to identify the start of the block structure used to organize the channel status and user information. The second sub-frame (right or “B” channel in stereophonic operation and secondary channel in monophonic operation) always starts with preamble “W”. A S/PDIF block contains 192 pairs of sub-frames of 32 bits. Figure 660. S/PDIF block format ; 0 < &K$ : = &K% % < &K$ : ; &K% 0 < &K$ : ; &K% 0 < &K$ : = &K% % < &K$ : &K% 6XEIUDPH 6XEIUDPH )UDPH )UDPH )UDPH 6WDUWRIEORFN )UDPH )UDPH 6WDUWRIEORFN 127( )RUKLVWRULFDOUHDVRQVSUHDPEOHV%0DQG:DUHIRUXVHLQSURIHVVLRQDODSSOLFDWLRQVUHIHUUHGWRDV=;DQG<UHVSHFWLYHO\ 06Y 9 2206/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Synchronization preambles The preambles patterns are inverted or not according to the previous half-bit value. This previous half-bit value is the level of the line before enabling a transfer for the first “B” preamble of the first frame. For the others preambles, this previous half-bit value is the second half-bit of the parity bit of the previous sub-frame. The preambles patterns B, M and W are described in the Figure 661. Figure 661. S/PDIF Preambles 8, 8, 8, 8, 8, 8, 8, 8, 3UHYLRXVKDOIELW 3UHDPEOH³%´ 3UHYLRXVKDOIELW /DFNRIWUDQVLWLRQV 3UHYLRXVKDOIELW 3UHDPEOH³0´ 3UHYLRXVKDOIELW /DFNRIWUDQVLWLRQV 3UHYLRXVKDOIELW 3UHDPEOH³:´ 3UHYLRXVKDOIELW /DFNRIWUDQVLWLRQV 6\PEROERXQGDU\ 06Y 9 Coding of information bits In order to minimize the DC component value on the transmission line, and to facilitate clock recovery from the data stream, bits 4 to 31 are encoded in biphase-mark. Each bit to be transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit to be transmitted is logical 0. However, it is different if the bit is logical 1. These states are named “UI” (Unit Interval) in the IEC-60958 specification. The 24 data bits are transferred LSB first. DocID029587 Rev 3 2207/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 Figure 662. Channel coding example 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, %LW&ORFN 6RXUFHFRGLQJ &KDQQHOFRGLQJ %LSKDVH0DUN %LW6WUHDP%LSKDVH0DUN &RGHG 06Y 9 52.3.3 SPDIFRX decoder (SPDIFRX_DC) Main principle The technique used by the SPDIFRX in order to decode the S/PDIF stream is based on the measurement of the time interval between two consecutive edges. Three kinds of time intervals may be found into an S/PDIF stream: • The long time interval, having a duration of 3 x UI, noted TL. It appears only during preambles. • The medium time interval, having a duration of 2 x UI, noted TM. It appears both in some preambles or into the information field. • The short time interval, having a duration of 1 x UI, noted TS. It appears both in some preambles or into the information field. The SPDIFRX_DC block is responsible of the decoding of the received S/PDIF stream. It takes care of the following functions: 2208/3178 • Resampling and filtering of the incoming signal • Estimation of the time-intervals • Estimation of the symbol rate and synchronization • Decoding of the serial data, and check of integrity • Detection of the block, and sub-frame preambles • Continuous tracking of the symbol rate DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 663 gives a detailed view of the SPDIFRX decoder. Figure 663. SPDIFRX decoder 63',)5;B'& 63',)5;B6(4 WUDQVLWLRQBSXOVH VSGLIU[BNHUBFN 0$;B &17 63',)5;B)( 63',)5;B,1 63',)5;B,1>Q@ /RQJHVW VKRUWHVW WUDQVLWLRQ 0,1B GHWHFWRU &17 1RLVHILOWHULQJ (GJH GHWHFWLRQ 75&17 ELWV SUHDPEOHB LQIR 7UDQVLWLRQ FRGHU %LSKDVH WUDQVB GHFRGHU 3UHDPEOH LQIR GHWHFWRU GDWDB YDOLG 5;B%8) 'DWD 3DFNLQJ GDWD GDWD 6<1& WUDQVLWLRQBZLGWKBFRXQW FWUOBFK :,'7+ :,'7+ 63',)5;B'(& ),1( 6<1& WUDQVLWLRQBSXOVH 06Y 9 Noise filtering & rising/falling edge detection The S/PDIF signal received on the selected SPDIFRX_IN is re-sampled using the spdifrx_ker_ck clock (acquisition clock). A simple filtering is applied in order cancel spurs. This is performed by the stage detecting the edge transitions. The edge transitions are detected as follow: • A rising edge is detected when the sequence 0 followed by two 1 is sampled. • A falling edge is detected when the sequence 1 followed by two 0 is sampled. • After a rising edge, a falling edge sequence is expected. • After a falling edge, a rising edge sequence is expected. Figure 664. Noise filtering and edge detection 6 6 *OLWFK 6 6 63',)5;B,1>Q @ VSGLIU[BNHUBFN UHVDPSOHGLQSXW ILOWHUHGLQSXW WUDQVLWLRQBSXOVH 06Y 9 Longest and shortest transition detector The longest and shortest transition detector block detects the maximum (MAX_CNT) and minimum (MIN_CNT) duration between two transitions. The TRCNT counter is used to measure the time interval duration. It is clocked by the spdifrx_ker_ck signal. On every transition pulse, the counter value is stored and the counter is reset to start counting again. The maximum duration is normally found during the preamble period. This maximum duration is sent out as MAX_CNT. The minimum duration is sent out as MIN_CNT. DocID029587 Rev 3 2209/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 The search of the longest and shortest transition is stopped when the transition timer expires. The transition timer is like a watchdog timer that generates a trigger after 70 transitions of the incoming signal. Note that counting 70 transitions insures a delay a bit longer than a sub-frame. Note that when the TRCNT overflows due to a too long time interval between two pulses, the SPDIFRX is stopped and the flag TERR of SPDIFRX_SR register is set to 1. Transition coder and preamble detector The transition coder and preamble detector block receives the MAX_CNT and MIN_CNT. It also receives the current transition width from the TRCNT counter (see Figure 663). This block encodes the current transition width by comparing the current transition width with two different thresholds, names THHI and THLO. • If the current transition width is less than (THLO - 1), then the data received is half part of data bit ‘1’, and is coded as TS. • If the current transition width is greater than (THLO - 1), and less than THHI, then the data received is data bit ‘0’, and is coded as TM. • If the current transition width is greater than THHI, then the data received is the long pulse of preambles, and is coded as TL. • Else an error code is generated (FERR flag is set). The thresholds THHI and THLO are elaborated using two different methods. If the peripheral is doing its initial synchronization (‘coarse synchronization’), then the thresholds are computed as follow: • THLO = MAX_CNT / 2. • THHI = MIN_CNT + MAX_CNT / 2. Once the ‘coarse synchronization’ is completed, then the SPDIFRX uses a more accurate reference in order to elaborate the thresholds. The SPDIFRX measures the length of 24 symbols (WIDTH24) for defining THLO and the length of 40 symbols (WIDTH40) for THHI. THHI and THLO are computed as follow: • THLO = (WIDTH24) / 32 • THHI = (WIDTH40) / 32 This second synchronization phase is called the ‘fine synchronization’. Refer to Figure 667 for additional information. As shown in the figure hereafter, THLO is ideally equal to 1.5 UI, and to THHI 2.5 UI. 2210/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 665. Thresholds 0$;B&17 0,1B&17 8, 8, 8, 63',)5;6LJQDO 8, 8, 'HWHFWLRQRI6KRUW 7UDQVLWLRQ 'HWHFWLRQRI0HGLXP 7UDQVLWLRQ 7+/2 'HWHFWLRQRI/RQJ 7UDQVLWLRQ 7++, 06Y 9 The preamble detector checks four consecutive transitions of a specific sequence to determine if they form the part of preamble. Let us say TRANS0, TRANS1, TRANS2 and TRANS3 represent four consecutive transitions encoded as mentioned above. Table 410 shows the values of these four transitions to form a preamble. Absence of this pattern indicates that these transitions form part of the data in the sub frame and bi-phase decoder will decode them. Table 410. Transition sequence for preamble Preamble type Biphase data pattern TRANS3 TRANS2 TRANS1 TRANS0 Preamble B 11101000 TL TS TS TL Preamble M 11100010 TL TL TS TS Preamble W 11100100 TL TM TS TM Bi-phase decoder The Bi-phase decoder decodes the input bi-phase marked data stream using the transition information provided by the transition coder and preamble detector block. It first waits for the preamble detection information. After the preamble detection, it decodes the following transition information: • If the incoming transition information is TM then it is decoded as a ‘0’. • Two consecutive TS are decoded as a ‘1’. • Any other transition sequence generates an error signal (FERR set to 1). After decoding 28 data bits this way, this module looks for the following preamble data. If the new preamble is not what is expected, then this block generates an error signal (FERR set to 1). Refer to Section 52.3.9: Reception errors, for additional information on error flags. Data packing This block is responsible of the decoding of the IEC-60958 frames and blocks. It also handles the writing into the RX_BUF or into SPDIFRX_CSR register. DocID029587 Rev 3 2211/3178 2242 SPDIF receiver interface (SPDIFRX) 52.3.4 RM0433 SPDIFRX tolerance to clock deviation The SPDIFRX tolerance to clock deviation depends on the number of sample clock cycles in one bit slot. The fastest spdifrx_ker_ck is, the more robust the reception will be. The ratio between spdifrx_ker_ck frequency and the symbol rate must be at least 11. Two kinds of phenomenon (at least!) can degrade the reception quality: 52.3.5 • The cycle-to-cycle jitter which reflects the difference of transition length between two consecutive transitions. • The long term jitter which reflects a cumulative effect of the cycle-to-cycle jitter. It can be seen as a low-frequency symbol modulation. SPDIFRX synchronization The synchronization phase starts when setting SPDIFRXEN to 0b01 or 0b11. Figure 666 shows the synchronization process. If the bit WFA of SPDIFRX_CR register is set to 1, then the peripheral must first detect activity on the selected SPDIFRX_IN line before starting the synchronization process. The activity detection is performed by detecting four transitions on the selected SPDIFRX_IN. The peripheral remains in this state until transitions are not detected. This function can be particularly helpful because the IP switches in COARSE SYNC mode only if activity is present on the selected SPDIFRX_IN input, avoiding synchronization errors. See Section 52.4: Programming procedures for additional information. The user can still set the SPDIFRX into STATE_IDLE by setting SPDIFRXEN to 0. If the WFA is set to 0, the peripheral starts the coarse synchronization without checking activity. The next step consists on doing a first estimate of the thresholds (COARSE SYNC), in order to perform the fine synchronization (FINE SYNC). Due to disturbances of the SPDIFRX line, it could happen that the process is not executed first time right. For this purpose, the user can program the number of allowed re-tries (NBTR) before setting SERR error flag. When the SPDIFRX has been able to measure properly the duration of 24 and 40 consecutive symbols then the FINE SYNC is completed, the threshold values are updated, and the flag SYNCD is set to 1. Refer to Section : Transition coder and preamble detector for additional information. Two kinds of errors are detected: • An overflow of the TRCNT, which generally means that there is no valid S/PDIF stream in the input line. This overflow is indicated by TERR flag. • The number of retries reached the programmed value. This means that strong jitter is present on the S/PDIF signal. This error is indicated by SERR flag. When the first FINE SYNC is completed, the reception of channel status (C) and user data (U) will start when the next “B” preamble is detected (see Figure 670).Then the user can read IEC-60958 C and U bits through SPDIFRX_CSR register. According to this information the user can then select the proper settings for DRFMT and RXSTEO. For example if the user detects that the current audio stream transports encoded data, then he can put RXSTEO to 0, and DRFMT to 0b10 prior to start data reception. Note that DRFMT and RXSTEO cannot be modified when SPDIFRXEN = 0b11. Writes to these fields are ignored if SPDIFRXEN is already 0b11, though these field can be changed with the same write instruction that causes SPDIFRXEN to become 0b11. Then the SPDIFRX waits for SPDIFRXEN = 0b11 and the “B” preamble before starting saving audio samples. 2212/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 666. Synchronization flowchart ,QLWLDO6\QF 3URFHVV :DLWIRUWUDQVLWLRQVLI:)$ HOVHVNLSWKLVVWHS 3DUDOOHOIORZV 6HDUFKIRU/RQJHVW6KRUWHVW SXOVHVIRUWUDQVLWLRQV &RPSXWH&2$56(WKUHVKROGV 7+/27++, &2$56(6<1& 6HDUFKIRUSUHDPEOHIRU WUDQVLWLRQV 1 1 SUHDPEOH IRXQGZLWKLQ WUDQV" 75&17 RYHUIORZV" ),1(6<1& < 'HFRGHSURSHUO\WKHQH[WV\PEROV 0HDVXUHPHQWRIDQGV\PEROVGXUDWLRQ :,'7+:,'7+ < 1 6\PE GHFRGLQJ 2." < $77(037 &RPSXWH),1(WKUHVKROGV 7+/27++, 1 $77(037 1%75" < (5525 6\QFIDLOXUH 7(55 6HW6<1&'WR (5525 6\QFIDLOXUH 6(55 6\QFKURQL]DWLRQ GRQH 6\QFVWRSSHG ā 7KHGHFRGLQJLVFRQVLGHUHG2.ZKHQWKHV\PEROVDUHSURSHUO\GHFRGHGDQGSUHDPEOHRFFXUVDWWKHH[SHFWHGSRVLWLRQ 06Y 9 Refer to Frame structure and synchronization error for additional information concerning TRCNT overflow. The FINE SYNC process is re-triggered every frame in order to update thresholds as shown in Figure 667 in order to continuously track S/PDIF synchronization. DocID029587 Rev 3 2213/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 Figure 667. Synchronization process scheduling 67$7(B6<1& WUDQV )UDPH 63',)5;B,1 6\QFKURQL]DWLRQ SURFHVVHV )UDPH 67$7(B5&9 )UDPH )UDPH )UDPH )UDPH )UDPH 0 $ : % 0 $ : % 0 $ : % % $ : % 0 $ : % 0 $ : % 0 $ : % 0 $ : % 7 6 &2$56( 63',)5;(1 ),1( ),1( E ),1( ),1( ),1( ),1( ),1( E 6<1&' &RDUVH6\QFKURQL]DWLRQSURFHVV &2$56( )LQH6\QFKURQL]DWLRQSURFHVV ),1( 7 6 52.3.6 7UDQVLWLRQ6HDUFK RSWLRQDOSKDVH 06Y 9 SPDIFRX handling The software can control the state of the SPDIFRX through SPDIFRXEN field. The SPDIFRX can be into one of the following states: • STATE_IDLE: The peripheral is disabled, the spdifrx_ker_ck domain is reset. The spdifrx_pclk domain is functional. • STATE_SYNC: The peripheral is synchronized to the stream, thresholds are updated regularly, user and channel status can be read via interrupt of DMA. The audio samples are not provided to receive buffer. • STATE_RCV: The peripheral is synchronized to the stream, thresholds are updated regularly, user, channel status and audio samples can be read via interrupt or DMA channels. When SPDIFRXEN goes to 0b11, the SPDIFRX waits for “B” preamble before starting saving audio samples. • STOP_STATE: The peripheral is no longer synchronized, the reception of the user, channel status and audio samples are stopped. It is expected that the software re-starts the SPDIFRX. The Figure 668 shows the possible states of the SPDIFRX, and how to transition from one state to the other. The bits under software control are followed by the mention “(SW)”, the bits under IP control are followed by the mention “(HW)”. 2214/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 668. SPDIFRX States 67$7(B,'/( 63',)5;(1 E 6: 63',)5;(1 E 6: RU 63',)5;(1 E 6: 63',)5;(1 E 6: 63',)5;(1 E 6: 67$7(B6<1& )(55 +: RU 7(55 +: RU 6(55 +: 67$7(B6723 63',)5;(1 E 6: DQG V\QFBGRQH +: 67$7(B5&9 )(55 +: RU 7(55 +: 127( V\QFBGRQHLVDQLQWHUQDOHYHQWLQIRUPLQJWKDWWKH63',)5;LVSURSHUO\V\QFKURQL]HG 06Y 9 When SPDIFRX is in STATE_IDLE: • The software can transition to STATE_SYNC by setting SPDIFRXEN to 0b01 or 0b11 When SPDIFRX is in STATE_SYNC: • If the synchronization fails or if the received data are not properly decoded with no chance of recovery without a re-synchronization (FERR or SERR or TERR = 1), the SPDIFRX goes to STATE_STOP, and waits for software acknowledge. • When the synchronization phase is completed, if SPDIFRXEN = 0b01 the peripheral remains in this state. • At any time the software can set SPDIFRXEN to 0, then SPDIFRX returns immediately to STATE_IDLE. If a DMA transfer is on-going, it will be properly completed. • The SPDIFRX goes to STATE_RCV if SPDIFRXEN = 0b11 and if the SYNCD = 1 When SPDIFRX is in STATE_RCV: • If the received data are not properly decoded with no chance of recovery without a resynchronization (FERR or SERR or TERR = 1), the SPDIFRX goes to STATE_STOP, and waits for software acknowledge. • At any time the software can set SPDIFRXEN to 0, then SPDIFRX returns immediately to STATE_IDLE. If a DMA transfer is on-going, it will properly be completed. When SPDIFRX is in STATE_STOP: • The SPDIFRX stops reception and synchronization, and waits for the software to set the bit SPDIFRXEN to 0, in order to clear the error flags. DocID029587 Rev 3 2215/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 When SPDIFRXEN is set to 0, the IP is disabled, meaning that all the state machines are reset, and RX_BUF is flushed. Note as well that flags FERR, SERR and TERR are reset. 52.3.7 Data reception management The SPDIFRX offers a double buffer for the audio sample reception. A 32-bit buffer located into the spdifrx_ker_ck clock domain (RX_BUF), and the SPDIFRX_DR register. The valid data contained into the RX_BUF will be immediately transferred into SPDIFRX_DR if SPDIFRX_DR is empty. The valid data contained into the RX_BUF will be transferred into SPDIFRX_DR when the two following conditions are reached: • The transition between the parity bit (P) and the next preamble is detected (this indicated that the word has been completely received). • The SPDIFRX_DR is empty. Having a 2-word buffer gives more flexibility for the latency constraint. The maximum latency allowed is TSAMPLE - 2TPCLK - 2Tspdifrx_ker_ck Where TSAMPLE is the audio sampling rate of the received stereo audio samples, TPCLK is the period of spdifrx_pclk clock, and Tspdifrx_ker_ck is the period of spdifrx_ker_ck clock. The SPDIFRX offers the possibility to use either DMA (spdifrx_dat_dma and spdifrx_ctrl_dma) or interrupts for transferring the audio samples into the memory. The recommended option is DMA, refer to Section 52.3.12: DMA Interface for additional information. The SPDIFRX offers several way on handling the received data. The user can either have a separate flow for control information and audio samples, or get them all together. For each sub-frame, the data reception register SPDIFRX_DR contains the 24 data bits, and optionally the V, U, C, PE status bits, and the PT (see Mixing data and control flow). Note that PE bit stands for Parity Error bit, and will be set to 1 when a parity error is detected in the decoded sub-frame. The PT field carries the preamble type (B, M or W). V, U and C are a direct copy of the value received from the S/PDIF interface. The bit DRFMT allows the selection between 3 audio formats as shown in Figure 669. 2216/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 669. SPDIFRX_DR register format )UDPH ,(& EORFNIRUPDW 0 &K$ 6\QF3UHDPEOH ,(& VXEIUDPH : )UDPH &K% % &K$ : )UDPH &K% 0 &K$ : &K% 6 6 6 6 6 6 6 6 9 8 & 3 /6E 06E '5)07 E 37> @RU &RU 8RU 9RU 3(RU 6 6 '5> @ 06E 63',)5;B'5 /6E '5)07 E 6 '5> @ 06E 6 37> @RU &RU 8RU 9RU 3(RU /6E '5)07 E 6 06E '51/> @ &K$ 6 /6E 6 06E '51/> @ &K% 6 /6E 06Y 9 Setting DRFMT to 0b00 or 0b01, offers the possibility to have the data either right or left aligned into the SPDIFRX_DR register. The status information can be enabled or forced to zero according to the way the software wants to handle them. The format given by DRFMT= 0b10 is interesting in non-linear mode, as only 16 bits per sub-frame are used. By using this format, the data of two consecutive sub-frames are stored into SPDIFRX_DR, dividing by two the amount of memory footprint. Note that when RXSTEO = 1, there is no misalignment risks (i.e. data from ChA will be always stored into SPDIFRX_DR[31:16]). If RXSTEO = 0, then there is a misalignment risk is case of overrun situation. In that case SPDIFRX_DR[31:16] will always contain the oldest value and SPDIFRX_DR[15:0] the more recent value (see Figure 671). In this format the status information cannot be mixed with data, but the user can still get them through SPDIFRX_CSR register, and use a dedicated DMA channel or interrupt to transfer them to memory (see Section 52.3.8: Dedicated control flow) Mixing data and control flow The user can choose to use this mode in order to get the full flexibility of the handling of the control flow. The user can select which field shall be kept into the data register (SPDIFRX_DR). • When bit PMSK = 1, the Parity Error information is masked (set to 0), otherwise it is copied into SPDIFRX_DR. • When bit VMSK = 1, the Validity information is masked (set to 0), otherwise it is copied into SPDIFRX_DR. • When bit CUMSK = 1, the Channel Status, and Used data information are masked (set to 0), otherwise they are copied into SPDIFRX_DR. • When bit PTMSK = 1, the Preamble Type is masked (set to 0), otherwise it is copied into SPDIFRX_DR. DocID029587 Rev 3 2217/3178 2242 SPDIF receiver interface (SPDIFRX) 52.3.8 RM0433 Dedicated control flow The SPDIFRX offers the possibility to catch both user data and channel status information via a dedicated DMA channel. This feature allows the SPDIFRX to acquire continuously the channel status and user information. The acquisition will start at the beginning of a IEC 60958 block. Two fields are available to control this path: CBDMAEN and SPDIFRXEN. When SPDIFRXEN is set to 0b01 or 0x11, the acquisition is started, after completion of the synchronization phase. When 8 channel status and 16 user data bits have been received, they are packed and stored into SPDIFRX_CSR register. A DMA request is triggered if the bit CBDMAEN is set to 1 (see Figure 670). If CS[0] corresponds to the first bit of a new block, the bit SOB will be set to 1. Refer to Section 52.5.8: Channel status register (SPDIFRX_CSR). A bit is available (CHSEL) in order to select if the user wants to select channel status information (C) from the channel A or B. Figure 670. Channel/user data format )UDPH 63',)5;B,1 0 $ : % % $ : % )UDPH )UDPH 0 $ : % % $ : % )UDPH )UDPH 0 $ : % 0 $ : % )UDPH 0 $ : % 0 $ : % ERUE 63',)5;(1 6<1&' 6WDUWRIDQHZEORFN VSGLIU[BGDWBGPD VSGLIU[BFWUOBGPD 6\QFKURQL]DWLRQGRQH $FTXLVLWLRQRI&DQG8 ELWVVWDUWHG 7UDQVIHURIILUVW 63',)5;B&%ZRUG ZLWK62% 7UDQVIHURIVHFRQG 63',)5;B&%ZRUG ZLWK62% 63',)5;B&65IRUPDW UHVHUYHG 62% &6> @ 865> @ 06Y 9 Note: Once the first start of block is detected (B preamble), the SPDIFRX is checking the preamble type every 8 frames. Note: Overrun error on SPDIFRX_DR register does not affect this path. 2218/3178 DocID029587 Rev 3 RM0433 52.3.9 SPDIF receiver interface (SPDIFRX) Reception errors Frame structure and synchronization error The SPDIFRX, detects errors, when one of the following condition occurs: • The FERR bit is set to 1 on the following conditions: – For each of the 28 information bits, if one symbol transition sequence is not correct: for example if short pulses are not grouped by pairs. – If preambles occur to an unexpected place, or an expected preamble is not received. • The SERR bit is set when the synchronization fails, because the number of re-tries exceeded the programmed value. • The TERR bit is set when the counter used to estimate the width between two transitions overflows (TRCNT). The overflow occurs when no transition is detected during 8192 periods of spdifrx_ker_ck clock. It represents at most a time interval of 11.6 frames. When one of those flags goes to 1, the traffic on selected SPDIFRX_IN is then ignored, an interrupt is generated if the IFEIE bit of the SPDIFRX_CR register is set. The normal procedure when one of those errors occur is: • Set SPDIFRXEN to 0 in order to clear the error flags • Set SPDIFRXEN to 0b01 or 0b11 in order to restart the IP Refer to Figure 668 for additional information. Parity error For each sub-frame, an even number of zeros and ones is expected inside the 28 information bits. If not, the parity error bit PERR is set in the SPDIFRX_SR register and an interrupt is generated if the parity interrupt enable PERRIE bit is set in the SPDIFRX_CR register. The reception of the incoming data is not paused, and the SPDIFRX continue to deliver data to SPDIFRX_DR even if the interrupt is still pending. The interrupt is acknowledged by clearing the PERR flag through PERRCF bit. If the software wants to guarantee the coherency between the data read in the SPDIFRX_DR register and the value of the bit PERR, the bit PMSK must be set to 0. Overrun error If both SPDIFRX_DR and RX_BUF are full, while the SPDIFRX_DC needs to write a new sample in RX_BUF, this new sample is dropped, and an overrun condition is triggered. The overrun error flag OVR is set in the SPDIFRX_SR register and an interrupt is generated if the OVRIE bit of the SPDIFRX_CR register is set. If the RXSTEO bit is set to 0, then as soon as the RX_BUF is empty, the IP will store the next incoming data, even if the OVR flag is still pending. The main purpose is to reduce as much as possible the amount of lost samples. Note that the behavior is similar independently of DRFMT value. See Figure 671. DocID029587 Rev 3 2219/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 Figure 671. S/PDIF overrun error when RXSTEO = 0 '5)07 E[ &K%FDQQRWEHZULWWHQLQWRWKH5;B%8) EHFDXVHLWLV)8//Î2YHUUXQ 63',)5;B,1 &K$FDQEHZULWWHQLQWRWKH5;B%8) 0 &K$ : &K% % &K$ : &K% 0 &K$ : &K% 0 &K$ : &K% % &K$ : &K% &K$ &K% &K$ &K% &K$ &K% &K$ &K% &K$ &K$ &K% &K% 5;B%8)DQG 63',)5;B'5FRQWHQW &K$ 5;B%8))8// &K% &K$ &K$ &K% &K$ &K$ &K% 6DPSOHVVWRUHGLQWR PHPRU\ &K% VSGLIU[BGDWBGPD VSGLIU[BLW $FNQRZOHGJHGE\6: '5)07 E 5;B%8)FDQQRWEHHPSWLHGEHFDXVH63',)B5;LV)8// )UDPH ,(& EORFNIRUPDW )UDPH )UDPH 'LVDYDLODEOHDQG5;B%8)LV)8//Î2YHUUXQ )UDPH )UDPH )UDPH 0 ' : ' % ' : ' 0 ' : ' 0 ' : ' 0 ' : ' 0 ' : ' &K$ &K% &K$ &K% &K$ &K% &K$ &K% &K$ &K% &K$ &K% 5;B%8))8// 5;1( VSGLIU[BGDWBGPD $FNQRZOHGJHG E\6: VSGLIU[BLW 'DWDUHDGIURP 63',)5;B'5 ' ' 63',)5;B'5 ' ' 63',)5;B'5 ' ' 63',)5;B'5 ' ' 63',)5;B'5 ' ' 63',)5;B'5 'LVORVW63',)5;> @FRQWDLQVWKHROGHVWGDWD 06Y 9 If the RXSTEO bit is set to 1, it means that stereo data are transported, then the SPDIFRX has to avoid misalignment between left and right channels. So the peripheral has to drop a second sample even if there is room inside the RX_BUF in order to avoid misalignment. Then the incoming samples can be written normally into the RX_BUF even if the OVR flag is still pending. Refer to Figure 672. The OVR flag is cleared by software, by setting the OVRCF bit to 1. 2220/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Figure 672. S/PDIF overrun error when RXSTEO = 1 &K%FDQQRWEHZULWWHQLQWRWKH5;B%8) EHFDXVHLWLV)8//Î2YHUUXQ 63',)5;B,1 &K$FDQQRWEHZULWWHQLQWRWKH5;B%8)HYHQLIWKH 5;B%8)LVQRW)8//LQRUGHUWRDYRLGPLVDOLJQPHQWV 0 &K$ : &K% % &K$ : &K% 0 &K$ : &K% 0 &K$ : &K% % &K$ : &K% &K% &K$ &K% &K$ &K% &K% &K$ &K% &K$ &K$ &K$ &K% &K% &K$ 5;B%8)DQG 63',)5;B'5FRQWHQW &K% 5;B%8))8// &K$ &K% &K$ &K% VSGLIU[BGDWBGPD 6DPSOHVVWRUHGLQWR PHPRU\ VSGLIU[BLW $FNQRZOHGJHG E\6: 06Y 9 52.3.10 Clocking strategy The SPDIFRX block needs two different clocks: • The APB clock (spdifrx_pclk), which is used for the register interface, • The spdifrx_ker_ck which is mainly used by the SPDIFRX_DC part. Those clocks are not supposed to be phase locked, so all signals crossing those clock domains are resynchronized (SYNC block on Figure 658). In order to decode properly the incoming S/PDIF stream the SPDIFRX_DC shall re-sample the received data with a clock at least 11 times higher than the maximum symbol rate, or 704 times higher than the audio sample rate. For example if the user expects to receive a symbol rate to up to 12.288 MHz, the sample rate shall be at least 135.2 MHz. The clock used by the SPDIFRX_DC is the spdifrx_ker_ck. The frequency of the spdifrx_pclk must be at least equal to the symbol rate. Table 411. Minimum spdifrx_ker_ck frequency versus audio sampling rate Symbol Rate Minimum spdifrx_ker_ck frequency 3.072 MHz 33.8 MHz For 48 kHz stream 6.144 MHz 67.6 MHz For 96 kHz stream 12.288 MHz 135.2 MHz For 192 kHz stream DocID029587 Rev 3 Comments 2221/3178 2242 SPDIF receiver interface (SPDIFRX) 52.3.11 RM0433 Symbol clock generation The SPDIFRX block provides a symbol clock on signal named spdifrx_symb_ck, which can be used as the reference kernel clock for another audio device such as SAI or SPI/I2S. It could be used for SPDIFRX to I2S bridge function. The symbol clock is built using the values of WIDTH24, WIDTH40 and the symbol boundaries. • During the reception of the sub-frame sync preambles, the falling and rising edges of the symbol clock are built from the WIDTH24 and WIDTH40 values. Note that WIDTH24 and WIDTH40 are also used for the generation of the symbol clock, when the SPDIFRX is STATE_STOP or STATE_IDLE. See Table 412 for details. • During the reception of the sub-frame payload, the SPDIFRX uses the symbols boundaries to generate the rising edge, the WIDTH24 and WIDTH40 values for the generation of the falling edge. The duty cycle of the symbol clock is close to 50% during the reception of the sub-frame payload. However, the duty cycle can be altered when the SPDIFRX transitions from a symbol clock generated with WIDTH24 and WIDTH40 to a clock generated by the symbol clock boundaries or vice-versa. The symbol clock will have an important jitter mainly due to: • The re-sampling of the S/PDIF signal with spdifrx_ker_ck clock • The transition of the symbol clock generation mode For that reason the application shall consider the quality degradation if the symbol clock is used as the reference clock for A/D or D/A converters. The generation of this symbol clock is controlled by the CKSEN bit. When CKSEN = ‘1’, the clock symbol is generated when the SPDIFRX completes successfully the first fine synchronization (SYNCD = 1), and when it is receiving correct data from the selected SPDIFRX input. When the SPDIFRX goes to STATE_STOP, or STATE_IDLE, the symbol clock is gated if the bit CKSBKPEN = ‘0’. If the CKSBKPEN = ‘1’, then a backup symbol clock is still generated if the SPDIFRX is properly synchronized (i.e. valid values available for WIDTH24 and WIDTH40). Table 412 gives more details on the conditions controlling the generation of the symbol clock. 2222/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Any state CKSBKPEN SPDIFRX states and conditions CKSEN Table 412. Conditions of spdifrx_symb_ck generation spdifrx_s ymb_ck state 0 X Disabled 0 Enabled 0 Disabled – SPDIFRX in STATE_SYNC and completing successfully the fine synchronization (SYNCD = '1') or, – SPDIFRX in STATE_RCV, and valid data are received via the selected SPDIFRX input. – – – – SPDIFRX in STATE_IDLE or, SPDIFRX in STATE_STOP or, SPDIFRX did not complete the fine synchronization (on-going) SPDIFRX is in STATE_RCV, but no data (transitions) detected on the selected SPDIFRX input. – SPDIFRX in STATE_IDLE, but with valid values for WIDTH40 and WIDTH24 or – SPDIFRX in STATE_SYNC and completing successfully the fine synchronization (SYNCD = '1') or, – SPDIFRX in STATE_SYNC the on-going fine synchronization is not completed, but WIDTH40 and WIDTH24 contain the valid values from the previous synchronization or, – SPDIFRX in STATE_RCV, and valid data are received via the selected SPDIFRX input or, – SPDIFRX in STATE_STOP, but with valid values for WIDTH40 and WIDTH24. 1 Enabled 1 – SPDIFRX in IDLE, with invalid values for WIDTH40 and WIDTH24 or, – SPDIFRX in STOP with invalid values for WIDTH40 and WIDTH24 (SERR = '1') or, – SPDIFRX in STATE_SYNC with invalid values for WIDTH40 and WIDTH24, and did not completed the on-going fine synchronization or, – SPDIFRX in STATE_RCV and no transitions detected on the selected SPDIFRX input 1 Disabled Note that when the flag SERR is set to ‘1’, neither the symbol clock nor the backup clock can be generated, since there is no synchronization. Note that when both CKSEN and CKSBKPEN are set to ‘1’, the symbol clock will loose some transitions when the SPDIFRX switches from STATE_SYNC or STATE_RCV to STATE_STOP, or STATE_IDLE. The bits CKSEN and CKSBKPEN are located into Control register (SPDIFRX_CR). 52.3.12 DMA Interface The SPDIFRX interface is able to perform communication using the DMA. Note: The user should refer to product specifications for availability of the DMA controller. The SPDIFRX offers two independent DMA channels: • A DMA channel dedicated to the data transfer • A DMA channel dedicated to the channel status and user data transfer The DMA mode for the data can be enabled for reception by setting the RXDMAEN bit in the SPDIFRX_CR register. In this case, as soon as the SPDIFRX_DR is not empty, the DocID029587 Rev 3 2223/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 SPDIFRX interface sends a transfer request to the DMA. The DMA reads the data received through the SPDIFRX_DR register without CPU intervention. For the use of DMA for the control data refer to Section 52.3.8: Dedicated control flow. 52.3.13 Interrupt Generation An interrupt line is shared between: • Reception events for data flow (RXNE) • Reception event for control flow (CSRNE) • Data corruption detection (PERR) • Transfer flow interruption (OVR) • Frame structure and synchronization errors (SERR, TERR and FERR) • Start of new block interrupt (SBD) • Synchronization done (SYNCD) Figure 673. SPDIFRX interface interrupt mapping diagram 6<1&' 6<1&',( 5;1( 5;1(,( 3(55 3(55,( 295 25 295,( VSGLIU[BLW &651( &651(,( 6%' 6%',( )(55 25 6(55 7(55 ,)(,( 06Y 9 Clearing interrupt source Note: 2224/3178 • RXNE is cleared when SPDIFRX_DR register is read • CSRNE is cleared when SPDIFRX_CSR register is read • FERR is cleared when SPDIFRXEN is set to 0 • SERR is cleared when SPDIFRXEN is set to 0 • TERR is cleared when SPDIFRXEN is set to 0 • Others are cleared through SPDIFRX_IFCR register The SBD event can only occur when the SPDIFRX is synchronized to the input stream (SYNCD = 1). DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) The SBD flag behavior is not guaranteed when the sub-frame which contains the B preamble is lost due to an overrun. 52.3.14 Register protection The SPDIFRX block embeds some hardware protection avoid erroneous use of control registers. The table hereafter shows the bit field properties according to the SPDIFRX state. Table 413. Bit field property versus SPDIFRX state SPDIFRXEN Registers SPDIFRX_CR SPDIFRX_IMR Field 0b00 0b01 0b11 (STATE_IDLE) (STATE_SYNC) (STATE_RCV) INSEL rw r r WFA rw r r NBTR rw r r CHSEL rw r r CBDMAEN rw rw rw PTMSK rw rw rw CUMSK rw rw rw VMSK rw rw rw PMSK rw rw rw DRFMT rw rw r RXSTEO rw rw r RXDMAEN rw rw rw All fields rw rw rw The table clearly shows that fields such as INSEL must be programmed when the IP is in STATE_IDLE. In the others IP states, the hardware prevents writing to this field. Note: Even if the hardware allows the writing of CBDMAEN and RXDMAEN “on-the-fly”, it is not recommended to enable the DMA when the IP is already receiving data. Note: Note that each of the mask bits (PMSK, VMSK, …) can be changed “on-the-fly” at any IP state, but any change does not affect data which is already being held in SPDIFRX_DR. 52.4 Programming procedures The following example illustrates a complete activation sequence of the SPDIFRX block. The data path and channel status & user information will both use a dedicated DMA channel. The activation sequence is then split into the following steps: • Wait for valid data on the selected SPDIFRX_IN input • Synchronize to the S/PDIF stream • Read the channel status and user information in order to setup the complete audio path • Start data acquisition DocID029587 Rev 3 2225/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 A simple way to check if valid data are available into the SPDIFRX_IN line is to switch the SPDIFRX into the STATE_SYNC, with bit WFA set to 1. The description hereafter will focus on detection. It is also possible to implement this function as follow: • The software has to check from time to time (i.e. every 100 ms for example) if the SPDIFRX can find synchronization. This can be done by checking if the bit TERR is set. When it is set it indicates that no activity as been found. • Connect the SPDIFRX_IN input to an external interrupt event block in order to detect transitions of SPDIFRX_IN line. When activity is detected, then SPDIFRXEN can be set to 0b01 or 0b11. For those two implementations, the bit WFA is set to 0. 52.4.1 Initialization phase • The initialization function will look like this: • Configure the DMA transfer for both audio samples and IEC60958 channel status and user information (DMA channel selection and activation, priority, number of data to transfer, circular/no circular mode, DMA interrupts) • Configure the destination address: – Configure the address of the SPDIFRX_CSR register as source address for IEC60958 channel status and user information – Configure the address of the SPDIFRX_DR register as source address for audio samples – Enable the generation of the spdifrx_ker_ck. Refer to Table 411 in order to define the minimum clock frequency versus supported audio sampling rate. Note that the audio sampling rate of the received stream is not known in advance. This means that the user has to select a spdifrx_ker_ck frequency at least 704 times higher than the maximum audio sampling rate the application is supposed to handle: for example if the application is able to handle streams to up to 96 kHz, then Fspdifrx_ker_ck shall be at least 704 x 96 kHz = 67.6 MHz • Enable interrupt for errors and event signaling (IFEIE = SYNCDIE = OVRIE, PERRIE = 1, others set to 0). Note that SYNCDIE can be set to 0. • Configure the SPDIFRX_CR register: • – INSEL shall select the wanted input – NBTR = 2, WFA = 1 (16 re-tries allowed, wait for activity before going to synchronization phase), – PTMSK = CUMSK = 1 (Preamble, C and U bits are not mixed with data) – VMSK = PMSK = 0 (Parity error and validity bit mixed with data) – CHSEL = 0 (channels status will be read from sub-frame A) – DRFMT = 0b01 (data aligned to the left) – RXSTEO = 1 (expected stereo mode linear) – CBDMAEN = RXDMAEN = 1 (enable DMA channels) – SPDIFRXEN = 0b01 (switch SPDIFRX to STATE_SYNC) The CPU can enter in WFI mode Then the CPU will receive interrupts coming either from DMA or SPDIFRX. 2226/3178 DocID029587 Rev 3 RM0433 52.4.2 SPDIF receiver interface (SPDIFRX) Handling of interrupts coming from SPDIFRX When an interrupt from the SPDIFRX is received, then the software has to check what is the source of the interrupt by reading the SPDIFRX_SR register. • If SYNCD is set to 1, then it means that the synchronization has been properly completed. No action has to be performed in our case as the DMA is already programmed. The software just needs to wait for DMA interrupt in order to read channel status information. The SYNCD flag must be cleared by setting SYNCDCF bit of SPDIFRX_IFCR register to 1. • If TERR or SERR or FERR are set to 1, the software has to set SPDIFRXEN to 0, and re-start from the initialization phase. • 52.4.3 – TERR indicates that a time-out occurs either during synchronization phase or after. – SERR indicates that the synchronization fails because the maximum allowed retries have been reached. – FERR indicates that the reading of information after synchronization fails (unexpected preamble, bad data decoding...). If PERR is set to 1, it means that a parity error has been detected, so one of the received audio sample or the channel status or user data bits are corrupted. The action taken here depends on the application: one action could be to drop the current channel status block as it is not reliable. There is no need to re-start from the initialization phase, as the synchronization is not lost. The PERR flag must be cleared by setting PERRCF bit of SPDIFRX_IFCR register to 1. Handling of interrupts coming from DMA If an interrupt is coming from the DMA channel used of the channel status (SPDIFRX_CSR): If no error occurred (i.e. PERR), the CPU can start the decoding of channel information. For example bit 1 of the channel status informs the user if the current stream is linear or not. This information is very important in order to set-up the proper processing chain. In the same way, bits 24 to 27 of the channel status give the sampling frequency of the stream incoming stream. Thanks to that information, the user can then configure the RXSTEO bit and DRFMT field prior to start the data reception. For example if the current stream is non linear PCM then RXSTEO is set to 0, and DRFMT is set to 0b10. Then the user can enable the data reception by setting SPDIFRXEN to 0b11. The bit SOB, when set to 1 indicates the start of a new block. This information will help the software to identify the bit 0 of the channel status. Note that if the DMA generates an interrupt every time 24 values are transferred into the memory, then the first word will always correspond to the start of a new block. If an interrupt is coming from the DMA channel used of the audio samples (SPDIFRX_DR): The process performed here depends of the data type (linear or non-linear), and on the data format selected. For example in linear mode, if PE or V bit is set a special processing can be performed locally in order to avoid spurs on output. In non-linear mode those bits are not important as data frame have their own checksum. DocID029587 Rev 3 2227/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 52.5 SPDIFRX interface registers 52.5.1 Control register (SPDIFRX_CR) Address offset: 0x00 Reset value: 0x00000000 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw 1. 12 rw rw 11 10 9 8 7 6 rw rw rw rw rw rw 5 4 rw rw 17 16 INSEL[2:0](1) rw rw rw 3 2 1 0 rw rw SPDIFRXEN[1:0](1) Res. 13 rw DRFMT[1:0](1) 14 NBTR[1:0](1) 15 rw 18 RXDMAEN(1) 21 RXSTEO(1) 22 CKSEN 23 CKSBKPEN 24 PMSK(1) 25 VMSK(1) 26 CUMSK(1) 27 PTMSK(1) 28 CBDMAEN(1) 29 CHSEL(1) 30 WFA (1) 31 rw Refer to Section 52.3.14: Register protection for additional information on fields properties. Bits 31:22 Reserved, forced by hardware to 0. Bit 21 CKSBKPEN: Backup Symbol Clock Enable This bit is set/reset by software 1: The SPDIFRX generates a backup symbol clock if CKSEN = ‘1’ 0: The SPDIFRX does not generate a backup symbol clock Bit 20 CKSEN: Symbol Clock Enable This bit is set/reset by software 1: The SPDIFRX generates a symbol clock 0: The SPDIFRX does not generate a symbol clock Bit 19 Reserved, forced by hardware to 0.par Bits18:16 INSEL[2:0]: SPDIFRX input selection 0b000: SPDIFRX_IN1 selected 0b001: SPDIFRX_IN2 selected 0b010: SPDIFRX_IN3 selected 0b011: SPDIFRX_IN4 selected others reserved Bit 15 Reserved, forced by hardware to 0. Bit 14 WFA: Wait For Activity This bit is set/reset by software 1: The SPDIFRX waits for activity on SPDIFRX_IN line (4 transitions) before performing the synchronization 0: The SPDIFRX does not wait for activity on SPDIFRX_IN line before performing the synchronization 2228/3178 DocID029587 Rev 3 rw RM0433 SPDIF receiver interface (SPDIFRX) Bits 13:12 NBTR[1:0]: Maximum allowed re-tries during synchronization phase 0b00: No re-try is allowed (only one attempt) 0b01: 3 re-tries allowed 0b10: 15 re-tries allowed 0b11: 63 re-tries allowed Bit 11 CHSEL: Channel Selection This bit is set/reset by software 1: The control flow will take the channel status from channel B 0: The control flow will take the channel status from channel A Bit 10 CBDMAEN: Control Buffer DMA ENable for control flow This bit is set/reset by software 1: DMA mode is enabled for reception of channel status and used data information. 0: DMA mode is disabled for reception of channel status and used data information. When this bit is set, the DMA request is made whenever the CSRNE flag is set. Bit 9 PTMSK: Mask of Preamble Type bits This bit is set/reset by software 1: The preamble type bits are not copied into the SPDIFRX_DR, zeros are written instead 0: The preamble type bits are copied into the SPDIFRX_DR Bit 8 CUMSK: Mask of channel status and user bits This bit is set/reset by software 1: The channel status and user bits are not copied into the SPDIFRX_DR, zeros are written instead 0: The channel status and user bits are copied into the SPDIFRX_DR Bit 7 VMSK: Mask of Validity bit This bit is set/reset by software 1: The validity bit is not copied into the SPDIFRX_DR, a zero is written instead 0: The validity bit is copied into the SPDIFRX_DR Bit 6 PMSK: Mask Parity error bit This bit is set/reset by software 1: The parity error bit is not copied into the SPDIFRX_DR, a zero is written instead 0: The parity error bit is copied into the SPDIFRX_DR Bits 5:4 DRFMT[1:0]: RX Data format This bit is set/reset by software 0b11: reserved 0b10: Data sample are packed by setting two 16-bit sample into a 32-bit word 0b01: Data samples are aligned in the left (MSB) 0b00: Data samples are aligned in the right (LSB) DocID029587 Rev 3 2229/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 Bit 3 RXSTEO: STerEO Mode This bit is set/reset by software 1: The peripheral is in STEREO mode 0: The peripheral is in MONO mode This bit is used in case of overrun situation in order to handle misalignment Bit 2 RXDMAEN: Receiver DMA ENable for data flow This bit is set/reset by software 1: DMA mode is enabled for reception. 0: DMA mode is disabled for reception. When this bit is set, the DMA request is made whenever the RXNE flag is set. Bits 1:0 SPDIFRXEN[1:0]: Peripheral Block Enable This field is modified by software. It shall be used to change the peripheral phase among the three possible states: STATE_IDLE, STATE_SYNC and STATE_RCV. 0b00: Disable SPDIFRX (STATE_IDLE). 0b01: Enable SPDIFRX Synchronization only 0b10: Reserved 0b11: Enable SPDIF Receiver Note: 2230/3178 1 it is not possible to transition from STATE_RCV to STATE_SYNC, the user shall first go the STATE_IDLE. 2 it is possible to transition from STATE_IDLE to STATE_RCV: in that case the peripheral transitions from STATE_IDLE to STATE_SYNC and as soon as the synchronization is performed goes to STATE_RCV. DocID029587 Rev 3 RM0433 52.5.2 SPDIF receiver interface (SPDIFRX) Interrupt mask register (SPDIFRX_IMR) Address offset: 0x04 Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. IFEIE SYNCDIE SBLKIE OVRIE PERRIE CSRNEIE RXNEIE rw rw rw rw rw rw rw Bits 31:7 Reserved, forced by hardware to 0. Bit 6 IFEIE: Serial Interface Error Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever SERR=1, TERR=1 or FERR=1 in the SPDIFRX_SR register. Bit 5 SYNCDIE: Synchronization Done This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever SYNCD = 1 in the SPDIFRX_SR register. Bit 4 SBLKIE: Synchronization Block Detected Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever SBD = 1 in the SPDIFRX_SR register. Bit 3 OVRIE: Overrun error Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever OVR=1 in the SPDIFRX_SR register Bit 2 PERRIE: Parity error interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever PERR=1 in the SPDIFRX_SR register Bit 1 CSRNEIE: Control Buffer Ready Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever CSRNE = 1 in the SPDIFRX_SR register. Bit 0 RXNEIE: RXNE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A SPDIFRX interface interrupt is generated whenever RXNE=1 in the SPDIFRX_SR register DocID029587 Rev 3 2231/3178 2242 SPDIF receiver interface (SPDIFRX) 52.5.3 RM0433 Status register (SPDIFRX_SR) Address offset: 0x08 Reset value: 0x00000000 31 30 29 28 27 26 25 24 Res. 23 22 21 20 19 18 17 16 WIDTH5[14:0] r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. TERR SERR FERR SYNCD SBD OVR PERR CSRNE RXNE r r r r r r r r r Bit 31 Reserved, forced by hardware to 0. Bits 30:16 WIDTH5[14:0]: Duration of 5 symbols counted with spdifrx_ker_ck This value represents the amount of spdifrx_ker_ck clock periods contained on a length of 5 consecutive symbols. This value can be used to estimate the S/PDIF symbol rate. Its accuracy is limited by the frequency of spdifrx_ker_ck. For example if the spdifrx_ker_ck is fixed to 84 MHz, and WIDTH5 = 147d. The estimated sampling rate of the S/PDIF stream is: Fs = 5 x Fspdifrx_ker_ck / (WIDTH5 x 64) ~ 44.6 kHz, so the closest standard sampling rate is 44.1 kHz. Note that WIDTH5 is updated by the hardware when SYNCD goes high, and then every frame. Bits 15:9 Reserved, forced by hardware to 0. Bit 8 TERR: Time-out error This bit is set by hardware when the counter TRCNT reaches its max value. It indicates that the time interval between two transitions is too long. It generally indicates that there is no valid signal on SPDIFRX_IN input. This flag is cleared by writing SPDIFRXEN to 0 An interrupt is generated if IFEIE=1 in the SPDIFRX_IMR register 0: No sequence error is detected 1: Sequence error is detected Bit 7 SERR: Synchronization error This bit is set by hardware when the synchronization fails due to amount of re-tries for NBTR. This flag is cleared by writing SPDIFRXEN to 0 An interrupt is generated if IFEIE=1 in the SPDIFRX_IMR register. 0: No synchronization error is detected 1: Synchronization error is detected Bit 6 FERR: Framing error This bit is set by hardware when an error occurs during data reception: preamble not at the expected place, short transition not grouped by pairs... This is set by the hardware only if the synchronization has been completed (SYNCD = 1). This flag is cleared by writing SPDIFRXEN to 0 An interrupt is generated if IFEIE=1 in the SPDIFRX_IMR register. 0: no Manchester Violation detected 1: Manchester Violation detected 2232/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) Bit 5 SYNCD: Synchronization Done This bit is set by hardware when the initial synchronization phase is properly completed. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. An interrupt is generated if SYNCDIE = 1 in the SPDIFRX_IMR register 0: Synchronization is pending 1: Synchronization is completed Bit 4 SBD: Synchronization Block Detected This bit is set by hardware when a “B” preamble is detected This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. An interrupt is generated if SBLKIE = 1 in the SPDIFRX_IMR register 0: No “B” preamble detected 1: “B” preamble has been detected Bit 3 OVR: Overrun error This bit is set by hardware when a received data is ready to be transferred in the SPDIFRX_DR register while RXNE = 1 and both SPDIFRX_DR and RX_BUF are full. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. An interrupt is generated if OVRIE=1 in the SPDIFRX_IMR register. 0: No Overrun error 1: Overrun error is detected Note: When this bit is set, the SPDIFRX_DR register content will not be lost but the last data received will. Bit 2 PERR: Parity error This bit is set by hardware when the data and status bits of the sub-frame received contain an odd number of 0 and 1. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. An interrupt is generated if PIE = 1 in the SPDIFRX_IMR register. 0: No parity error 1: Parity error Bit 1 CSRNE: The Control Buffer register is not empty This bit is set by hardware when a valid control information is ready. This flag is cleared when reading SPDIFRX_CSR register. An interrupt is generated if CBRDYIE = 1 in the SPDIFRX_IMR register 0: No control word available on SPDIFRX_CSR register 1: A control word is available on SPDIFRX_CSR register Bit 0 RXNE: Read data register not empty This bit is set by hardware when a valid data is available into SPDIFRX_DR register. This flag is cleared by reading the SPDIFRX_DR register. An interrupt is generated if RXNEIE=1 in the SPDIFRX_IMR register. 0: Data is not received 1: Received data is ready to be read. 52.5.4 Interrupt flag clear register (SPDIFRX_IFCR) Address offset: 0x0C DocID029587 Rev 3 2233/3178 2242 SPDIF receiver interface (SPDIFRX) RM0433 Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNCDCF SBDCF OVRCF PERRCF Res. Res. w w w w Bits 31:6 Reserved, forced by hardware to 0. Bit 5 SYNCDCF: Clears the Synchronization Done flag Writing 1 in this bit clears the flag SYNCD in the SPDIFRX_SR register. Reading this bit always returns the value 0. Bit 4 SBDCF: Clears the Synchronization Block Detected flag Writing 1 in this bit clears the flag SBD in the SPDIFRX_SR register. Reading this bit always returns the value 0. Bit 3 OVRCF: Clears the Overrun error flag Writing 1 in this bit clears the flag OVR in the SPDIFRX_SR register. Reading this bit always returns the value 0. Bit 2 PERRCF: Clears the Parity error flag Writing 1 in this bit clears the flag PERR in the SPDIFRX_SR register. Reading this bit always returns the value 0. Bits 1:0 Reserved 2234/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) 52.5.5 Data input register (SPDIFRX_DR) Address offset: 0x10 Reset value: 0x00000000 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b00: 31 30 Res. Res. 15 14 29 28 PT[1:0] 27 26 25 24 C U V PE 23 22 21 20 19 18 17 16 DR[23:16] r r r r r r r r r r r r r r 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r DR[15:0] r r r r r r r r r Bits 31:30 Reserved: forced by hardware to 0 Bits 29:28 PT: Preamble Type These bits indicate the preamble received. 00: not used 01: Preamble B received 10: Preamble M received 11: Preamble W received Note that if PTMSK = 1, this field is forced to zero Bit 27 C: Channel Status bit Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0 Bit 26 U: User bit Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0 Bit 25 V: Validity bit Contains the received validity bit if VMSK = 0, otherwise it is forced to 0 Bit 24 PE: Parity Error bit Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0 Bits 23:0 DR: Data value Contains the 24 received data bits, aligned on D[23] DocID029587 Rev 3 2235/3178 2242 SPDIF receiver interface (SPDIFRX) 52.5.6 RM0433 Data input register (SPDIFRX_DR) Address offset: 0x10 Reset value: 0x00000000 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b01: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DR[23:8] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. C U V PE r r r r DR[7:0] r r r r r r r r PT[1:0] r r Bits 31:8 DR: Data value Contains the 24 received data bits, aligned on D[23] Bits 7:6 Reserved: forced by hardware to 0 Bits 5:4 PT: Preamble Type These bits indicate the preamble received. 00: not used 01: Preamble B received 10: Preamble M received 11: Preamble W received Note that if PTMSK = 1, this field is forced to zero Bit 3 C: Channel Status bit Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0 Bit 2 U: User bit Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0 Bit 1 V: Validity bit Contains the received validity bit if VMSK = 0, otherwise it is forced to 0 Bit 0 PE: Parity Error bit Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0 2236/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) 52.5.7 Data input register (SPDIFRX_DR) Address offset: 0x10 Reset value: 0x00000000 This register can take 3 different formats according to DRFMT. The data format proposed when DRFMT = 0b10, is dedicated to non-linear mode, as only 16 bits are used (bits 23 to 8 from S/PDIF sub-frame). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DRNL2[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r DRNL1[15:0] r r r r r r r r r Bits 31:16 DRNL2: Data value This field contains the Channel A Bits 15:0 DRNL1: Data value This field contains the Channel B DocID029587 Rev 3 2237/3178 2242 SPDIF receiver interface (SPDIFRX) 52.5.8 RM0433 Channel status register (SPDIFRX_CSR) Address offset: 0x14 Reset value: 0x00000000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. SOB 15 14 13 12 11 10 9 23 22 21 20 19 18 17 16 CS[7:0] r r r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r USR[15:0] r r r r r r r r r Bits 31:25 Reserved Bit 24 SOB: Start Of Block This bit indicates if the bit CS[0] corresponds to the first bit of a new block 0: CS[0] is not the first bit of a new block 1: CS[0] is the first bit of a new block Bits 23:16 CS[7:0]: Channel A status information Bit CS[0] is the oldest value Bits 15:0 USR[15:0]: User data information Bit USR[0] is the oldest value, and comes from channel A, USR[1] comes channel B. So USR[n] bits come from channel A is n is even, otherwise they come from channel B. 2238/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) 52.5.9 Debug Information register (SPDIFRX_DIR) Address offset: 0x18 Reset value: 0x00000000 31 30 29 Res. Res. Res. 15 14 13 Res. Res. Res. 28 27 26 25 24 23 22 21 20 19 18 17 16 TLO[12:0] r r r r r r r r r r r r r 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r THI[12:0] r r r r r r r Bits 31:29 Reserved, forced by hardware to 0. Bits 16:28 TLO: Threshold LOW (TLO = 1.5 x UI / Tspdifrx_ker_ck) This field contains the current threshold LOW estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of TLO is limited to a period of the spdifrx_ker_ck. The sampling rate can be estimated as follow: Sampling Rate = [2 x TLO x Tspdifrx_ker_ck +/- Tspdifrx_ker_ck] x 2/3 Note that TLO is updated by the hardware when SYNCD goes high, and then every frame. Bits 15:13 Reserved, forced by hardware to 0. Bits 12:0 THI: Threshold HIGH (THI = 2.5 x UI / Tspdifrx_ker_ck) This field contains the current threshold HIGH estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of THI is limited to a period of the spdifrx_ker_ck. The sampling rate can be estimated as follow: Sampling Rate = [2 x THI x Tspdifrx_ker_ck +/- Tspdifrx_ker_ck] x 2/5 Note that THI is updated by the hardware when SYNCD goes high, and then every frame. DocID029587 Rev 3 2239/3178 2242 SPDIF receiver interface (SPDIFRX) 52.5.10 RM0433 SPDIFRX version register (SPDIFRX_VERR) Address offset: 0x03F4 Reset value: 0x0000 0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res MAJREV[3:0] MINREV[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 MAJREV[3:0]: Major revision These bits return the SPDIFRX major revision. Major revision is 1. Bits 3:0 MINREV[3:0]: Minor revision These bits return the SPDIFRX minor revision. Minor revision is 2. 52.5.11 SPDIFRX identification register (SPDIFRX_IDR) Address offset: 0x03F8 Reset value: 0x0013 0041 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ID[31:16] r 15 14 13 12 11 10 9 8 7 ID[15:0] r Bits 31:0 ID[31:0]: SPDIFRX identifier These bits return the SPDIFRX identifier value. 2240/3178 DocID029587 Rev 3 RM0433 SPDIF receiver interface (SPDIFRX) 52.5.12 SPDIFRX size identification register (SPDIFRX_SIDR) Address offset: 0x03FC Reset value: 0xA3C5 DD01 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SID[31:16] r 15 14 13 12 11 10 9 8 7 SID[15:0] r Bits 31:0 SID[31:0]: Size identification These bits return the size of the memory region allocated to SPDIFRX registers. The size of this memory region is of 1 Kbyte. DocID029587 Rev 3 2241/3178 2242 SPDIF receiver interface (SPDIFRX) 52.5.13 RM0433 SPDIFRX interface register map Table 414 gives the SPDIFRX interface register map and reset values. 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. RXNE Res. CSRNE Res. 0 0 0 0 Res. Res. 0 Res. Res. OVR Res. PERR Res. 0 OVRCF Res. 0 PERRCF Res. SBD Res. 0 SBDCF Res. SYNCD Res. 0 SYNCDCF Res. FERR 0 SERR 0 Res. 0 Res. 0 TERR 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 0 0 0 0x10 PT[1:0] Res. Res. Reset value C U V PE DR[23:0] SPDIFRX_DR DR[23:0] Res. 0x03F8 0x03FC Res. Res. SOB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 ID[15:0] 0 0 1 0 0 1 1 0 0 0 0 0 0 0 SID[31:16] 1 0 MAJREV[3:0] MINREV[3:0] 0 0 0 THI[12:0] ID[31:16] 0 PE USR[15:0] Res. Res. 0 Res. Res. Res. 0 Res. Res. 2242/3178 0 0 SPDIFRX_SIDR Reset value 0 TLO[12:0] SPDIFRX_IDR Reset value 0 CS[7:0] 0 C U V DRNL1[15:0] 0 Res. Res. Res. Res. 0x03F4 Reset value SPDIFRX_VER R Reset value Res. 0x18 0 Res. Reset value SPDIFRX_DIR 0 Res. SPDIFRX_CSR 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0x14 0 Res. DRNL2[15:0] Reset value PT[1:0] Res. 0 Res. SPDIFRX_IFCR 0 Res. 0x0C Res. Reset value WIDTH5[14:0] Res. SPDIFRX_SR SPDIFRXEN[1:0] 0 RXNEIE 0 CSRNEIE RXSTEO RXDMAEN 0 OVRIE 0 PERRIE 0 Reset value 0x08 DRFMT[1:0] 0 SBLKIE Res. PMSK Res. 0 SYNCDIE Res. VMSK Res. 0 Res. 0 IFEIE 0 Res. PTMSK 0 Res. CUMSK CHSEL CBDMAEN 0 NBTR[1:0] 0 WFA Res. Res. Res. 0 Res. INSEL[2:0] 0 Res. Res. 0 Res. CKSEN 0 Res. 0 Res. Res. CKSBKPEN Res. Res. Res. Res. Res. Res. Res. Res. SPDIFRX_IMR Res. 0x04 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. SPDIFRX_CR Res. 0x00 Res. Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 414. SPDIFRX interface register map and reset values 1 0 0 SID[15:0] 0 0 0 1 0 1 DocID029587 Rev 3 1 1 0 1 1 1 0 1 0 RM0433 Single Wire Protocol Master Interface (SWPMI) 53 Single Wire Protocol Master Interface (SWPMI) 53.1 Introduction The Single Wire Protocol Master Interface (SWPMI) is the master interface corresponding to the Contactless front-end (CLF) defined in the ETSI TS 102 613 technical specification. The principle of the Single wire protocol (SWP) is based on the transmission of digital information in full duplex mode: • S1 signal (from Master to Slave) is transmitted by a digital modulation (L or H) in the voltage domain (refer to Figure 674: S1 signal coding), • S2 signal (from Slave to Master) is transmitted by a digital modulation (L or H) in the current domain (refer to Figure 675: S2 signal coding). Figure 674. S1 signal coding 7 7 9 /RJLFDO W 9 7 /RJLFDO DQGLGOHELW W 069 Figure 675. S2 signal coding s d ϯͬϰd s ^ϭ ϭͬϰd ^ϭ ƚ / / ^Ϯ >ŽŐŝĐĂůϭ ϭͬϰd ^Ϯ >ŽŐŝĐĂůϭ ƚ s ƚ d ϯͬϰd s ^ϭ ϭͬϰd ^ϭ ƚ ƚ / ^Ϯ ƚ / >ŽŐŝĐĂůϬ ^Ϯ ƚ >ŽŐŝĐĂůϬ ƚ D^ϯϯϯϰϯsϭ DocID029587 Rev 3 2243/3178 2270 Single Wire Protocol Master Interface (SWPMI) 53.2 RM0433 SWPMI main features The SWPMI module main features are the following (see Figure 53.3.4: SWP bus states): 2244/3178 • Full-duplex communication mode • Automatic SWP bus state management • Automatic handling of Start of frame (SOF) • Automatic handling of End of frame (EOF) • Automatic handling of stuffing bits • Automatic CRC-16 calculation and generation in transmission • Automatic CRC-16 calculation and checking in reception • 32-bit Transmit data register • 32-bit Receive data register • Multi software buffer mode for efficient DMA implementation and multi frame buffering • Configurable bit-rate up to 2 Mbit/s • Configurable interrupts • CRC error, underrun, overrun flags • Frame reception and transmission complete flags • Slave resume detection flag • Loopback mode for test purpose • Embedded SWPMI_IO transceiver compliant with ETSI TS 102 613 technical specification • Dedicated mode to output SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals on GPIOs, in case of external transceiver connection DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) 53.3 SWPMI functional description 53.3.1 SWPMI block diagram Figure 676. SWPMI block diagram ELW$3%EXV VZSPLBSFON VZSPLBJEOBLW VZSPLBW[BGPD VZSPLBU[BGPD 6:30,B5'5 &RQWURO6WDWXV UHJLVWHUV VZSPLBNHUBFN 6:30,B7'5 6:30,FRUH VZSPLBZNXS 6:30,B7; 6:30,B5; 6:30,B6863(1' 6:30, 6:30,B,2 6:3EXV 06Y 9 Refer to the bit SWPSRC in Section 8.7.18: RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP1R) to select the swpmi_ker_ck (SWPMI core clock source). Note: In order to support the exit from Stop mode by a RESUME by slave, it is mandatory to select HSI for swpmi_ker_ck. If this feature is not required, swpmi_pclk can be selected, and SWPMI must be disabled before entering the Stop mode. 53.3.2 SWPMI pins and internal signals Table 415 lists the SWPMI slave inputs and output signals connected to package pins or balls, while Table 416 shows the internal SWPMI signals. Table 415. SWPMI input/output signals connected to package pins or balls Signal name Signal type SWPMI_SUSPEND Digital output SWPMI suspend signal SWPMI_TX Digital output SWPMI transmit signal SWPMI_RX Digital input SWPMI receive signal Description DocID029587 Rev 3 2245/3178 2270 Single Wire Protocol Master Interface (SWPMI) RM0433 Table 416. SWPMI internal input/output signals 53.3.3 Signal name Signal type swpmi_pclk Digital input APB clock swpmi_ker_ck Digital input SWPMI kernel clock swpmi_wkup Digital output SWPMI wakeup signal swpmi_gbl_it Digital output SWPMI interrupt signal swpmi_tx_dma Digital output SWPMI DMA transmit request swpmi_rx_dma Digital output SWPMI DMA receive request Description SWP initialization and activation The initialization and activation will set the SWPMI_IO state from low to high. When using the internal transceiver, the procedure is the following: 53.3.4 1. Configure the SWP_CLASS bit in SWPMI_OR register according to the VDD voltage (3 V or 1.8 V), 2. Set SWPTEN in SWPMI_CR register to enable the SWPMI_IO transceiver and set the SWPMI_IO to low level (SWP bus DEACTIVATED) 3. Wait for the RDYF flag in SWPMI_SR register to be set (polling the flag or enabling the interrupt with RDYIE bit in SWPMI_IER register), 4. Set SWPACT bit in SWPMI_CR register to ACTIVATE the SWP i.e. to move from DEACTIVATED to SUSPENDED. SWP bus states The SWP bus can have the following states: DEACTIVATED, SUSPENDED, ACTIVATED. Several transitions are possible: • ACTIVATE: transition from DEACTIVATED to SUSPENDED state, • SUSPEND: transition from ACTIVATED to SUSPENDED state, • RESUME by master: transition from SUSPENDED to ACTIVATED state initiated by the master, • RESUME by slave: transition from SUSPENDED to ACTIVATED state initiated by the slave, • DEACTIVATE: transition from SUSPENDED to DEACTIVATED state. ACTIVATE During and just after reset, the SWPMI_IO is configured in analog mode. Refer to Section 53.3.3: SWP initialization and activation to activate the SWP bus. 2246/3178 DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) SUSPEND The SWP bus stays in the ACTIVATED state as long as there is a communication with the slave, either in transmission or in reception. The SWP bus switches back to the SUSPENDED state as soon as there is no more transmission or reception activity, after 7 idle bits. RESUME by master Once the SWPMI is enabled, the user can request a SWPMI frame transmission. The SWPMI first sends a transition sequence and 8 idle bits (RESUME by master) before starting the frame transmission. The SWP moves from the SUSPENDED to ACTIVATED state after the RESUME by master (refer to Figure 677: SWP bus states). RESUME by slave Once the SWPMI is enabled, the SWP can also move from the SUSPENDED to ACTIVATED state if the SWPMI receives a RESUME from the slave. The RESUME by slave sets the SRF flag in the SWPMI_ISR register. DEACTIVATE Deactivate request If no more communication is required, and if SWP is in the SUSPENDED mode, the user can request to switch the SWP to the DEACTIVATED mode by disabling the SWPMI peripheral. The software must set DEACT bit in the SWPMI_CR register in order to request the DEACTIVATED mode. If no RESUME by slave is detected by SWPMI, the DEACTF flag is set in the SWPMI_ISR register and the SWPACT bit is cleared in the SWPMI_ICR register. In case a RESUME by slave is detected by the SWPMI while the software is setting DEACT bit, the SRF flag is set in the SWPMI_ISR register, DEACTF is kept cleared, SWPACT is kept set and DEACT bit is cleared. In order to activate SWP again, the software must clear DEACT bit in the SWPMI_CR register before setting SWPACT bit. Deactivate mode In order to switch the SWP to the DEACTIVATED mode immediately, ignoring any possible incoming RESUME by slave, the user must clear SWPACT bit in the SWPMI_CR register. Note: In order to further reduce current consumption, configure the SWPMI_IO port as output push pull low in GPIO controller and then clear the SWPTEN bit in SWPMI_CR register (refer to Section 11: General-purpose I/Os (GPIO)). DocID029587 Rev 3 2247/3178 2270 Single Wire Protocol Master Interface (SWPMI) RM0433 Figure 677. SWP bus states 6 $&7,9$7(' PDVWHU(2) 6XVSHQGVHTXHQFH LGOHELWV 6863(1'(' 6 '($&7,9$7(' 6863(1'(' 6 6863(1'(' 5(680(E\PDVWHU LGOHELWV $&7,9$7(' PDVWHU62) WUDQVLWLRQVHTXHQFH 6 5(680( E\VODYH 6 WUDQVLWLRQVHTXHQFH 6863(1'(' $&7,9$7(' VODYH62) 069 53.3.5 SWPMI_IO (internal transceiver) bypass A SWPMI_IO (transceiver), compliant with ETSI TS 102 613 technical specification, is embedded in the microcontroller. Nevertheless, this is possible to bypass it by setting SWP_TBYP bit in SWPMI_OR register. In this case, the SWPMI_IO is disabled and the SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate functions on three GPIOs (refer to “Pinouts and pin description” in product datasheet). This configuration is selected to connect an external transceiver. Note: In SWPMI_IO bypass mode, SWPTEN bit in SWPMI_CR register must be kept cleared. 53.3.6 SWPMI Bit rate The bit rate must be set in the SWPMI_BRR register, according to the following formula: FSWP = Fswpmi_ker_ck / ((BR[7:0]+1)x4) Note: 2248/3178 The maximum bitrate is 2 Mbit/s. DocID029587 Rev 3 RM0433 53.3.7 Single Wire Protocol Master Interface (SWPMI) SWPMI frame handling The SWP frame is composed of a Start of frame (SOF), a Payload from 1 to 30 bytes, a 16bit CRC and an End of frame (EOF) (Refer to Figure 678: SWP frame structure). Figure 678. SWP frame structure 62) (K E 62) ' (2) )K E ' ' ͘͘͘ &5& E\WHV (2) 3$ K& džͲdžͲϭϯͲϭϮ ϭϰĚ ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJ^t d& ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJD ZyE ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJ^t Zy&& ƐĞƚďLJ,t ^h^W E DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ džͲdžͲϭϯͲϭϮ ZD D^ϯϯϯϱϭsϭ Multi software buffer mode This mode allows to work with several frame buffers in the RAM memory, in order to ensure a continuous reception, keeping a very low CPU load, using the DMA. The frame payloads are stored in the RAM memory, together with the frame status flags. The software can check the DMA counters and status flags at any time to handle the received SWP frames in the RAM memory. The Multi software buffer mode must be used in combination with the DMA in circular mode. The Multi software buffer mode is selected by setting both RXDMA and RXMODE bits in SWPMI_CR register. 2256/3178 DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) In order to work with n reception buffers in RAM, the DMA channel or stream must be configured in following mode (refer to DMA section): • memory to memory mode disabled, • memory increment mode enabled, • memory size set to 32-bit, • peripheral size set to 32-bit, • peripheral increment mode disabled, • circular mode enabled, • data transfer direction set to read from peripheral, • the number of words to be transfered must be set to 8 x n (8 words per buffer), • the source address is the SWPMI_TDR register, • the destination address is the buffer1 address in RAM Then the user must: 1. Set RXDMA in the SWPMI_CR register 2. Set RXBFIE in the SWPMI_IER register 3. Enable stream or channel in the DMA module. In the SWPMI interrupt routine, the user must check RXBFF in the SWPMI_ISR register. If it is set, the user must set CRXBFF bit in the SWPMI_ICR register to clear RXBFF flag and the user can read the first frame payload received in the first buffer (at the RAM address set in DMA2_CMAR1). The number of data bytes in the payload is available in bits [23:16] of the last 8th word. In the next SWPMI interrupt routine occurrence, the user will read the second frame received in the second buffer (address set in DMA2_CMAR1 + 8), and so on (refer to Figure 684: SWPMI Multi software buffer mode reception). In case the application software cannot ensure to handle the SMPMI interrupt before the next frame reception, each buffer status is available in the most significant byte of the 8th buffer word: • The CRC error flag (equivalent to RXBERF flag in the SWPMI_ISR register) is available in bit 24 of the 8th word. Refer to Section 53.3.10: Error management for an CRC error description. • The receive overrun flag (equivalent to RXOVRF flag in the SWPMI_ISR register) is available in bit 25 of the 8th word. Refer to Section 53.3.10: Error management for an overrun error description. • The receive buffer full flag (equivalent to RXBFF flag in the SWPMI_ISR register) is available in bit 26 of the 8th word. In case of a CRC error, both RXBFF and RXBERF flags are set, thus bit 24 and bit 26 are set. In case of an overrun, an overrun flag is set, thus bit 25 is set. The receive buffer full flag is set only in case of an overrun during the last word reception; then, both bit 25 and bit 26 are set for the current and the next frame reception. The software can also read the DMA counter (number of data to transfer) in the DMA registers in order to retrieve the frame which has already been received and transferred into the RAM memory through DMA. For example, if the software works with 4 reception buffers, DocID029587 Rev 3 2257/3178 2270 Single Wire Protocol Master Interface (SWPMI) RM0433 and if the DMA counter equals 17, it means that two buffers are ready for reading in the RAM area. In Multi software buffer reception mode, if the software is reading bits 24, 25 and 26 of the 8th word, it does not need to clear RXBERF, RXOVRF and RXBFF flags after each frame reception. Figure 684. SWPMI Multi software buffer mode reception ^tW ŝŶƉƵƚ ^K& Ϭ ϭ ^tWD/ͺZZ džͲdžͲdžͲdž ^tWD/ͺZZ džͲdžͲdžͲdž Ϯ ϯ ϰ ϱ ϲ ϯͲϮͲϭͲϬ ϳ ϴ ϵ ϭϬ ϭϭ ϳͲϲͲϱͲϰ ϯͲϮͲϭͲϬ ϭϮ ϭϯ Z ϭϭͲϭϬͲϵͲϴ ϳͲϲͲϱͲϰ dž ^tWD/ͺZ&> K& ^K& ϭϭͲϭϬͲ ϵͲϴ Ϭ džͲdžͲϭϯͲϭϮ džͲdžͲϭϯͲϭϮ ϭϰĚ d& ZyE ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJD Zy&& ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJ^t ^h^W E ƐĞƚďLJ,t DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZ ƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZƚŽ ZD DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZ ƚŽZD &ƌĂŵĞϭ &ƌĂŵĞϮ &ƌĂŵĞϯ &ƌĂŵĞϰ DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZƚŽ ZD ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ džͲdžͲϭϯͲϭϮ džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲϭϰͲdžͲdž ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲϴͲdžͲdž ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ ϭϱͲϭϰͲϭϯͲϭϮ ϭϵͲϭϴͲϭϳͲϭϲ džͲdžͲdžͲϮϬ džͲdžͲdžͲdž džͲϮϭͲdžͲdž ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ ϭϱͲϭϰͲϭϯͲϭϮ ϭϵͲϭϴͲϭϳͲϭϲ ϮϯͲϮϮͲϮϭͲϮϬ ϮϳͲϮϲͲϮϱͲϮϰ džͲϮϵͲdžͲϮϴ ZD D^ϯϯϯϱϮsϭ 53.3.10 Error management Underrun during payload transmission During the transmission of the frame payload, a transmit underrun is indicated by the TXUNRF flag in the SWPMI_ISR register. An interrupt is generated if TXBUNREIE bit is set in the SWPMI_IER register. If a transmit underrun occurs, the SWPMI stops the payload transmission and sends a corrupted CRC (the first bit of the first CRC byte sent is inverted), followed by an EOF. If DMA is used, TXDMA bit in the SWPMI_CR register is automatically cleared. 2258/3178 DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) Any further write to the SWPMI_TDR register while TXUNRF is set will be ignored. The user must set CTXUNRF bit in the SWPMI_ICR register to clear TXUNRF flag. Overrun during payload reception During the reception of the frame payload, a receive overrun is indicated by RXOVRF flag in the SWPMI_ISR register. If a receive overrun occurs, the SWPMI does not update SWPMI_RDR with the incoming data. The incoming data will be lost. The reception carries on up to the EOF and, if the overrun condition disappears, the RXBFF flag is set. When RXBFF flag is set, the user can check the RXOVRF flag. The user must set CRXOVRF bit in the SWPMI_ICR register to clear RXBOVRF flag. If the user wants to detect the overrun immediately, RXBOVREIE bit in the SWPMI_IER register can be set in order to generate an interrupt as soon as the overrun occurs. The RXOVRF flag is set at the same time as the RXNE flag, two SWPMI_RDR reads after the overrun event occurred. It indicates that at least one received byte was lost, and the loaded word in SWPMI_RDR contains the bytes received just before the overrun. In Multi software buffer mode, if RXOVRF flag is set for the last word of the received frame, then the overrun bit (bit 25 of the 8th word) is set for both the current and the next frame. CRC error during payload reception Once the two CRC bytes have been received, if the CRC is wrong, the RXBERF flag in the SWPMI_ISR register is set after the EOF reception. An interrupt is generated if RXBEIE bit in the SWPMI_IER register is set (refer toFigure 685: SWPMI single buffer mode reception with CRC error).The user must set CRXBERF bit in SWPMI_ICR to clear RXBERF flag. Figure 685. SWPMI single buffer mode reception with CRC error ^tW ŝŶƉƵƚ ^K& ^tWD/ͺZZ Ϭ ϭ Ϯ ϯ ϰ ϱ džͲdžͲdžͲdž ϲ ϳ ϴ ϯͲϮͲϭͲϬ ϵ ϭϬ ϳͲϲͲϱͲϰ ϭϭ ϭϮ ϭϯ ϭϭͲϭϬͲϵͲϴ dž ^tWD/ͺZ&> Z K& džͲdžͲϭϯͲϭϮ ϭϰĚ VHWE\+:FOHDUHGE\6: d& VHWE\+:FOHDUHGE\6:RU'0$ ZyE Zy&& VHWE\+:FOHDUHGE\6: VHWE\+: ^h^W E VHWE\+:FOHDUHGE\6: Zy Z& ^tƌĞĂĚƐ ^tWD/ͺZZ ^tƌĞĂĚƐ ^tWD/ͺZZ ^tƌĞĂĚƐ ^tWD/ͺZZ ^tĚĞƚĞĐƚƐĞƌƌŽƌ ǁŝƚŚZy Z&ĨůĂŐ 069 Missing or corrupted stuffing bit during payload reception When a stuffing bit is missing or is corrupted in the payload, RXBERF and RXBFF flags are set in SWPMI_ISR after the EOF reception. DocID029587 Rev 3 2259/3178 2270 Single Wire Protocol Master Interface (SWPMI) RM0433 Corrupted EOF reception Once an SOF has been received, the SWPMI accumulates the received bytes until the reception of an EOF (ignoring any possible SOF). Once an EOF has been received, the SWPMI is ready to start a new frame reception and waits for an SOF. In case of a corrupted EOF, RXBERF and RXBFF flags will bet set in the SWPMI_ISR register after the next EOF reception. Note: In case of a corrupted EOF reception, the payload reception carries on, thus the number of bytes in the payload might get the value 31 if the number of received bytes is greater than 30. The number of bytes in the payload is read in the SWPMI_RFL register or in bits [23:16] of the 8th word of the buffer in the RAM memory, depending on the operating mode. 53.3.11 Loopback mode The loopback mode can be used for test purposes. The user must set LPBK bit in the SWPMI_CR register in order to enable the loopback mode. When the loopback mode is enabled, SWPMI_TX and SWPMI_RX signals are connected together. As a consequence, all frames sent by the SWPMI will be received back. 53.4 SWPMI low-power modes Table 417. Effect of low-power modes on SWPMI Mode 2260/3178 Description Sleep No effect. SWPMI interrupts cause the device to exit the Sleep mode. Stop A RESUME from SUSPENDED mode issued by the slave can wake up the device from Stop mode if the swpmi_ker_ck is HSI (refer to Section 53.3.1: SWPMI block diagram). Standby The SWPMI is stopped. DocID029587 Rev 3 RM0433 53.5 Single Wire Protocol Master Interface (SWPMI) SWPMI interrupts All SWPMI interrupts are connected to the NVIC. To enable the SWPMI interrupt, the following sequence is required: 1. Configure and enable the SWPMI interrupt channel in the NVIC 2. Configure the SWPMI to generate SWPMI interrupts (refer to the SWPMI_IER register). Table 418. Interrupt control bits Event flag Enable control bit Exit the Sleep mode Exit the Stop mode Exit the Standby mode Receive buffer full RXBFF RXBFIE yes no no Transmit buffer empty TXBEF TXBEIE yes no no Receive buffer error (CRC error) RXBERF RXBEIE yes no no Receive buffer overrun RXOVRF RXBOVEREIE yes no no Transmit buffer underrun TXUNRF TXBUNREIE yes no no RXNE RIE yes no no Transmit data register full TXE TIE yes no no Transfer complete flag TCF TCIE yes no no Slave resume flag SRF SRIE yes yes (1) no RDYF RDYIE yes no no Interrupt event Receive data register not empty Transceiver ready flag 1. If HSI is selected for swpmi_ker_ck. DocID029587 Rev 3 2261/3178 2270 Single Wire Protocol Master Interface (SWPMI) 53.6 RM0433 SWPMI registers Refer to Section 1.1 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 53.6.1 SWPMI Configuration/Control register (SWPMI_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP EN DEACT Res. SWP ACT LPBK rw rw rw rw Res. Res. Res. Res. Res. Res. TXMOD RXMO TXDMA RXDMA E DE rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 SWPTEN: Single wire protocol master transceiver enable This bit is used to enable the transceiver and control the SWPMI_IO with SWPMI (refer to Section 53.3.3: SWP initialization and activation). 0: SPWMI_IO pin is controlled by GPIO controller 1: SWPMI_IO transceiver is controlled by SWPMI Bit 10 DEACT: Single wire protocol master interface deactivate This bit is used to request the SWP DEACTIVATED state. Setting this bit has the same effect as clearing the SWPACT, except that a possible incoming RESUME by slave will keep the SWP in the ACTIVATED state. Bits 9:6 Reserved, must be kept at reset value. Bit 5 SWPACT: Single wire protocol master interface activate This bit is used to activate the SWP bus (refer to Section 53.3.3: SWP initialization and activation). 0: SWPMI_IO is pulled down to ground, SWP bus is switched to DEACTIVATED state 1: SWPMI_IO is released, SWP bus is switched to SUSPENDED state To be able to set SWPACT bit, DEACT bit must be have been cleared previously. Bit 4 LPBK: Loopback mode enable This bit is used to enable the loopback mode 0: Loopback mode is disabled 1: Loopback mode is enabled Note: This bit cannot be written while SWPACT bit is set. Bit 3 TXMODE: Transmission buffering mode This bit is used to choose the transmission buffering mode. This bit is relevant only when TXDMA bit is set (refer to Table 419: Buffer modes selection for transmission/reception). 0: SWPMI is configured in Single software buffer mode for transmission 1: SWPMI is configured in Multi software buffer mode for transmission. Note: This bit cannot be written while SWPACT bit is set. 2262/3178 DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) Bit 2 RXMODE: Reception buffering mode This bit is used to choose the reception buffering mode. This bit is relevant only when TXDMA bit is set (refer to Table 419: Buffer modes selection for transmission/reception). 0: SWPMI is configured in Single software buffer mode for reception 1: SWPMI is configured in Multi software buffer mode for reception. Note: This bit cannot be written while SWPACT bit is set. Bit 1 TXDMA: Transmission DMA enable This bit is used to enable the DMA mode in transmission 0: DMA is disabled for transmission 1: DMA is enabled for transmission Note: TXDMA is automatically cleared if the payload size of the transmitted frame is given as 0x00 (in the least significant byte of TDR for the first word of a frame). TXDMA is also automatically cleared on underrun events (when TXUNRF flag is set in the SWP_ISR register) Bit 0 RXDMA: Reception DMA enable This bit is used to enable the DMA mode in reception 0: DMA is disabled for reception 1: DMA is enabled for reception Table 419. Buffer modes selection for transmission/reception Buffer mode 53.6.2 No software buffer Single software buffer Multi software buffer RXMODE/TXMODE x 0 1 RXDMA/TXDMA 0 1 1 SWPMI Bitrate register (SWPMI_BRR) Address offset: 0x04 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. BR[7:0] rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 BR[7:0]: Bitrate prescaler This field must be programmed to set SWP bus bitrate, taking into account the Fswpmi_ker_ck programmed in the RCC (Reset and Clock Control), according to the following formula: FSWP= Fswpmi_ker_ck / ((BR[7:0]+1)x4) Note: The programmed bitrate must stay within the following range: from 100 kbit/s up to 2 Mbit/s. BR[7:0] cannot be written while SWPACT bit is set in the SWPMI_CR register. DocID029587 Rev 3 2263/3178 2270 Single Wire Protocol Master Interface (SWPMI) 53.6.3 RM0433 SWPMI Interrupt and Status register (SWPMI_ISR) Address offset: 0x0C Reset value: 0x0000 02C2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. RDYF DEACT F SUSP SRF TCF TXE RXNE r r r r r r r TXUNR RXOVR RXBER TXBEF RXBFF F F F r r r r r Bits 31:12 Reserved, must be kept at reset value. Bit 11 RDYF: transceiver ready flag This bit is set by hardware as soon as transceiver is ready. After setting the SWPTEN bit in SWPMI_CR register to enable the SWPMI_IO transceiver, software must wait for this flag to be set before setting the SWPACT bit to activate the SWP bus. 0: transceiver not ready 1: transceiver ready Bit 10 DEACTF: DEACTIVATED flag This bit is a status flag, acknowledging the request to enter the DEACTIVATED mode. 0: SWP bus is in ACTIVATED or SUSPENDED state 1: SWP bus is in DEACTIVATED state If a RESUME by slave state is detected by the SWPMI while DEACT bit is set by software, the SRF flag will be set, DEACTF will not be set and SWP will move in ACTIVATED state. Bit 9 SUSP: SUSPEND flag This bit is a status flag, reporting the SWP bus state 0: SWP bus is in ACTIVATED state 1: SWP bus is in SUSPENDED or DEACTIVATED state Bit 8 SRF: Slave resume flag This bit is set by hardware to indicate a RESUME by slave detection. It is cleared by software, writing 1 to CSRF bit in the SWPMI_ICR register. 0: No Resume by slave state detected 1: A Resume by slave state has been detected during the SWP bus SUSPENDED state Bit 7 TCF: Transfer complete flag This flag is set by hardware as soon as both transmission and reception are completed and SWP is switched to the SUSPENDED state. It is cleared by software, writing 1 to CTCF bit in the SWPMI_ICR register. 0: Transmission or reception is not completed 1: Both transmission and reception are completed and SWP is switched to the SUSPENDED state Bit 6 TXE: Transmit data register empty This flag indicates the transmit data register status 0: Data written in transmit data register SWPMI_TDR is not transmitted yet 1: Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again 2264/3178 DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) Bit 5 RXNE: Receive data register not empty This flag indicates the receive data register status 0: Data is not received in the SWPMI_RDR register 1: Received data is ready to be read in the SWPMI_RDR register Bit 4 TXUNRF: Transmit underrun error flag This flag is set by hardware to indicate an underrun during the payload transmission i.e. SWPMI_TDR has not been written in time by the software or the DMA. It is cleared by software, writing 1 to the CTXUNRF bit in the SWPMI_ICR register. 0: No underrun error in transmission 1: Underrun error in transmission detected Bit 3 RXOVRF: Receive overrun error flag This flag is set by hardware to indicate an overrun during the payload reception, i.e. SWPMI_RDR has not be read in time by the software or the DMA. It is cleared by software, writing 1 to CRXOVRF bit in the SWPMI_ICR register. 0: No overrun in reception 1: Overrun in reception detected Bit 2 RXBERF: Receive CRC error flag This flag is set by hardware to indicate a CRC error in the received frame. It is set synchronously with RXBFF flag. It is cleared by software, writing 1 to CRXBERF bit in the SWPMI_ICR register. 0: No CRC error in reception 1: CRC error in reception detected Bit 1 TXBEF: Transmit buffer empty flag This flag is set by hardware to indicate that no more SWPMI_TDR update is required to complete the current frame transmission. It is cleared by software, writing 1 to CTXBEF bit in the SWPMI_ICR register. 0: Frame transmission buffer no yet emptied 1: Frame transmission buffer has been emptied Bit 0 RXBFF: Receive buffer full flag This flag is set by hardware when the final word for the frame under reception is available in SWPMI_RDR. It is cleared by software, writing 1 to CRXBFF bit in the SWPMI_ICR register. 0: The last word of the frame under reception has not yet arrived in SWPMI_RDR 1: The last word of the frame under reception has arrived in SWPMI_RDR 53.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. CRDY F Res. Res. CSRF CTCF Res. Res. rc_w1 rc_w1 rc_w1 DocID029587 Rev 3 CTXUN CRXOV CRXBE CTXBE CRXBF RF RF RF F F rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 2265/3178 2270 Single Wire Protocol Master Interface (SWPMI) RM0433 Bits 31:12 Reserved, must be kept at reset value. Bit 11 CRDYF Clear transceiver ready flag Writing 1 to this bit clears the RDYF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bits 10:9 Reserved, must be kept at reset value. Bit 8 CSRF: Clear slave resume flag Writing 1 to this bit clears the SRF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 7 CTCF: Clear transfer complete flag Writing 1 to this bit clears the TCF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bits 6:5 Reserved, must be kept at reset value. Bit 4 CTXUNRF: Clear transmit underrun error flag Writing 1 to this bit clears the TXUNRF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 3 CRXOVRF: Clear receive overrun error flag Writing 1 to this bit clears the RXBOCREF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 2 CRXBERF: Clear receive CRC error flag Writing 1 to this bit clears the RXBERF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 1 CTXBEF: Clear transmit buffer empty flag Writing 1 to this bit clears the TXBEF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 0 CRXBFF: Clear receive buffer full flag Writing 1 to this bit clears the RXBFF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect 53.6.5 SWPMI Interrupt Enable register (SMPMI_IER) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. RDYIE rw 2266/3178 Res. Res. SRIE TCIE TIE RIE rw rw rw rw DocID029587 Rev 3 TXUNR RXOVR RXBEI TXBERI RXBFIE EIE EIE E E rw rw rw rw rw RM0433 Single Wire Protocol Master Interface (SWPMI) Bits 31:12 Reserved, must be kept at reset value. Bit 11 RDYIE: Transceiver ready interrupt enable 0: Interrupt is inhibited 1: A SWPMI interrupt is generated whenever RDYF flag is set in the SWPMI_ISR register Bits 10:9 Reserved, must be kept at reset value. Bit 8 SRIE: Slave resume interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever SRF flag is set in the SWPMI_ISR register Bit 7 TCIE: Transmit complete interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TCF flag is set in the SWPMI_ISR register Bit 6 TIE: Transmit interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TXE flag is set in the SWPMI_ISR register Bit 5 RIE: Receive interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXNE flag is set in the SWPMI_ISR register Bit 4 TXUNRIE: Transmit underrun error interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TXBUNRF flag is set in the SWPMI_ISR register Bit 3 RXOVRIE: Receive overrun error interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXBOVRF flag is set in the SWPMI_ISR register Bit 2 RXBERIE: Receive CRC error interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXBERF flag is set in the SWPMI_ISR register Bit 1 TXBEIE: Transmit buffer empty interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TXBEF flag is set in the SWPMI_ISR register Bit 0 RXBFIE: Receive buffer full interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXBFF flag is set in the SWPMI_ISR register DocID029587 Rev 3 2267/3178 2270 Single Wire Protocol Master Interface (SWPMI) 53.6.6 RM0433 SWPMI Receive Frame Length register (SWPMI_RFL) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r r r RFL[4:0] r Bits 31:5 Reserved, must be kept at reset value. Bits 4:0 RFL[4:0]: Receive frame length RFL[4:0] is the number of data bytes in the payload of the received frame. The two least significant bits RFL[1:0] give the number of relevant bytes for the last SWPMI_RDR register read. 53.6.7 SWPMI Transmit data register (SWPMI_TDR) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TD[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w w TD[15:0] w Bits 31:0 TD[31:0]: Transmit data Contains the data to be transmitted. Writing to this register triggers the SOF transmission or the next payload data transmission, and clears the TXE flag. 53.6.8 SWPMI Receive data register (SWPMI_RDR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RD[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r RD[15:0] 2268/3178 r DocID029587 Rev 3 RM0433 Single Wire Protocol Master Interface (SWPMI) Bits 31:0 RD[31:0]: received data Contains the received data Reading this register is clearing the RXNE flag. 53.6.9 SWPMI Option register (SWPMI_OR) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWP_ CLASS SWP_ TBYP rw rw Bits 31:2 Reserved, must be kept at reset value Bit 1 SWP_CLASS: SWP class selection This bit is used to select the SWP class (refer to Section 53.3.3: SWP initialization and activation). 0: Class C: SWPMI_IO uses directly VDD voltage to operate in class C. This configuration must be selected when VDD is in the range [1.62 V to 1.98 V] 1: Class B: SWPMI_IO uses an internal voltage regulator to operate in class B. This configuration must be selected when VDD is in the range [2.70 V to 3.30 V] Bit 0 SWP_TBYP: SWP transceiver bypass This bit is used to bypass the internal transceiver (SWPMI_IO), and connect an external transceiver. 0: Internal transceiver is enabled. The external interface for SWPMI is SWPMI_IO (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs) 1: Internal transceiver is disabled. SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate function on GPIOs. This configuration is selected to connect an external transceiver DocID029587 Rev 3 2269/3178 2270 2270/3178 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWPMI_OR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWPMI_RDR RD[31:0] 0 DocID029587 Rev 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWP_ TBYP 0 Res. SWPMI_TDR Res. 0 Res. SWPMI_RFL SWP_ CLASS 0 Res. 0x24 Reset value Res. 0x1C Res. 0x18 Res. Refer to Section 2.2.2 on page 105 for the register boundary addresses. Res. CTXUNRF CRXOVRF CRXBERF CTXBEF CRXBFF 0 0 RXBERIE TXBEIE RXBFIE 0 0 TXUNRIE 0 0 RXOVRIE 0 0 RIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDYF DEACTF SUSP. SRF TCF TXE. RXNE. TXUNRF RXOVRF RXBERF TXBEF RXBFF 0 Res. Res. TIE Res. Res. 0 Res. CTCF 0 TCIE Res. Res. Reset value Res. Res. CSRF 0 0 SRIE 0 Res. Res. Res. Res. Res. 0 BRR[7:0] 0 Reset value 0 0 TXDMA 0 RXDMA LPBK TXMODE 0 RXMODE SWPACT Res. Res. Res. Res. DEACT Res. Res. SWPTEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. CRDYF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value Res. Reset value RDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWPMI_IER Res. SWPMI_ICR Res. 0x14 Res. 0x10 Res. Reset value Res. Reset value Res. SWPMI_ISR Res. 0x0C Res. RESERVED Res. 0x08 Res. 0x20 SWPMI_BRR Res. 0x04 SWPMI_CR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 0x00 Res. 53.6.10 Res. Single Wire Protocol Master Interface (SWPMI) RM0433 SWPMI register map and reset value table Table 420. SWPMI register map and reset values 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0 0 RFL[4:0] 0 0 0 0 0 0 0 0 0 TD[31:0] 0 0 RM0433 Management data input/output (MDIOS) 54 Management data input/output (MDIOS) 54.1 MDIOS introduction An MDIO bus can be useful in systems where a master chip needs to manage (configure and get status data from) one or multiple slave chips. The bus protocol uses only two signals: • MDC: the Management Data Clock • MDIO: the data line carrying the opcode (write or read), the slave (port) address, the MDIOS register address, and the data In each transaction, the master either reads the contents of an MDIOS register in one of its slaves, or it writes data to an MDIOS register in one of its slaves. The MDIOS peripheral serves as a slave interface to an MDIO bus. An MDIO master can use the MDC/MDIO lines to write and read 32 16-bit MDIOS registers which are held in the MDIOS. These MDIOS registers are managed by the firmware, thus allowing the MDIO master to configure the application running on the STM32 and get status information from it. The MDIOS can operate in Stop mode, optionally waking up the STM32 if the MDIO master performs a read or a write to one of its MDIOS registers. 54.2 MDIOS main features The MDIOS includes the following features: • 32 MDIOS registers addresses, each of which is managed using separate input and output data registers: – 32 x 16-bit firmware read/write, MDIOS read-only output data registers – • • • 32 x 16-bit firmware read-only, MDIOS write-only input data registers Configurable slave (port) address Independently maskable interrupts/events: – MDIOS register write – MDIOS register read – MDIOS protocol error Able to operate in and wake up from Stop mode DocID029587 Rev 3 2271/3178 2286 Management data input/output (MDIOS) RM0433 54.3 MDIOS functional description 54.3.1 MDIOS block diagram Figure 686. MDIOS block diagram 0',26 $3%B,17(5)$&( PGLRVBZNXS PGLRVBLW 0',26B$'$37(5 &RQWURO UHJLVWHUV 0',26B0'& )UDPH GHFRGHU 0',26B0',2 $3%EXV PGLRVBSFON ',1UHJLVWHUV 'DWDUHFHLYH '287 UHJLVWHUV 'DWDWUDQVPLW 06Y 9 54.3.2 MDIOS pins and internal signals Table 421 lists the MDIOS inputs and output signals connected to package pins or balls, while Table 422 shows the internal PWR signals. Table 421. MDIOS input/output signals connected to package pins or balls Signal name Signal type MDIOS_MDC Digital input MDIO master clock MDIOS_MDIO Digital input/ output MDIO signal (opcode, address, input/output data) Description Table 422. MDIOS internal input/output signals 2272/3178 Signal name Signal type mdios_wkup Digital output MDIOS wakeup signal mdios_it Digital output MDIOS interrupt signal mdios_pclk Digital input APB clock Description DocID029587 Rev 3 RM0433 54.3.3 Management data input/output (MDIOS) MDIOS protocol The MDIOS protocol uses two signals: 1. MDIOS_MDC: the clock, always driven by the master 2. MDIOS_MDIO: signal carrying the opcode, address, and bidirectional data Each transaction is performed using a “frame”. Each frame contains 32 bits: 14 control bits, 2 turn-around bits, and then 16 data bits, each passed serially. • • • 14 control bits, driven by the master – 2 start bits: always “01” – 2 opcode bits: read=”10”, write=”01” – 5 port address bits, indicating which slave device is being addressed – 5 MDIOS register address bits, up to 32 MDIOS registers can be addressed in each slave 2 turn-around state bits – On write operations, the master drives “10” – On read operations, the first bit is high-impedance, and the second bit is driven by the slave to ‘0’ 16 data bits – On write operations, data written to slave’s MDIOS register is driven by the master – On read operations, data read from slave’s MDIOS register is driven by the slave Each frame is usually preceded by a preamble, where the MDIOS stays at ‘1’ for 32 MDC clocks. The master can continue to keep MDIO at ‘1’, indicating the “idle” condition, when it has no frame to send. When MDIO signal is driven by the master, MDIOS samples it using the rising edge of MDC. When MDIOS drives MDIO, the output changes on the rising edge of MDC. Figure 687. MDIO protocol write frame waveform 0',26B0'& 0',26B0',2 ELW 3UHDPEOH 6WDUW :ULWH G GGG G G G G G G G G G G G G D D D D D U U U U U 5HJLVWHU 7XUQDURXQG 3+< 5HJLVWHU $GGUHVV $GGUHVV 'DWD 069 9 Figure 688. MDIO protocol read frame waveform 0',26B0'& D D D D D U U U U U 0',26B0',2 ELW 3UHDPEOH 6WDUW 5HDG 3+< $GGUHVV 5HJLVWHU $GGUHVV GG GG G G G G G G G G G G G G 7XUQDURXQG 5HJLVWHU 'DWD 7XUQDURXQG 0',26B0',2GULYHQE\0DVWHU 0',26B0',2GULYHQE\6ODYH 06Y 9 DocID029587 Rev 3 2273/3178 2286 Management data input/output (MDIOS) 54.3.4 RM0433 MDIOS enabling and disabling The MDIOS is enabled by setting the EN bit in the MDIOS_CR register. When EN=1, the MDIOS monitors the MDIO bus and service frames addressed to one of its MDIOS registers. When the MDIOS is enabled (setting EN to ‘1’), the same write operation to the MDIOS_CR register must properly set the PORT_ADDRESS[4:0] field to indicate the slave port address. A frame is ignored by the MDIOS if its port address is not the same as PORT_ADDRESS[4:0] (presumably intended for another slave). When EN=0, the MDIOS ignores the frames being transmitted on the MDC/MDIO lines, and the IP is in a reduced consumption mode. Clearing EN also clears all of the DIN registers. If EN is cleared while the MDIOS is driving read data, it immediately releases the bus and does not drive the rest of the data. If EN is cleared while the MDIOS is receiving a frame, the frame is aborted and the data is lost. When the MDIOS is enabled, then disabled and subsequently re-enabled, the status flags are not cleared. For a correct operation the firmware shall clear the status flag before reenabling the MDIOS. 54.3.5 MDIOS data From the point of view of the MDIO master, there are 32 16-bit MDIOS registers in the MDIOS which can be written and read. In reality, for each MDIOS register ‘n’ there are two sets of registers: DINn[15:0] and DOUTn[15:0]. Input data When the MDIO master transmits a frame which writes to MDIOS register ‘n’ in the MDIOS, it is the DINn[15:0] register which is updated with the incoming data. The DIN registers (DIN0 - DIN31) can be read by the firmware, but they can be written only by the MDIO master via the MDIO bus. The contents of DINn change immediately after the MDC rising edge when the last data bit is sampled. If the firmware happens to read the contents of DINn at the moment that it is being updated, there is a possibility that the value read is corrupted (a bit-by-bit cross between the old value and the new value). For this reason, the frmware should assure that two subsequent reads from the same DINn register give the same value and assure that the data was stable when it was read. In the very worst case, the firmware would need to read DINn four times: first to get the old value, second to get an incoherent value (when reading at the moment the register changes), third to get the new value, and forth to confirm the new value. If the firmware uses the WRF interrupt and can guarantee that it reads the DINn register before any new MDIOS write frame completes, the firmware can perform a single read. If the MDIO master performs a write operation with a register address that is greater than 31, the MDIOS ignores the frame (the data is not saved and no flag is set). Output data When the MDIOS receives a frame which requests to read register ‘n’, it returns the value found in the DOUTn[15:0] register. Thus, if the MDIO master expects to read the same value which it previously wrote to MDIOS register ‘n’, the firmware must copy the data from 2274/3178 DocID029587 Rev 3 RM0433 Management data input/output (MDIOS) DINn to DOUTn each time new data is written to DINn. For correct operation, the firmware must copy the data to the DOUTn register within a preamble (if the master sends preambles before each frame) plus 15 cycles time. When an MDIOS register is read via the MDIO bus, the MDIOS passes the 16-bit value (from the corresponding DOUTn register) to the MDIOS clock domain during the 15th cycle of the read frame. If the firmware attempts to write the DOUTn register while the MDIO Master is currently reading MDIOS register ‘n’, then the firmware write operation will be ignored if it occurs during the 15th cycle of the frame (during a one-MDC-cycle window). Therefore, after writing a DOUTn register, the firmware should read back the same DOUTn register and confirm that the value was actually written. If the DOUTn register does not contain the value which was written, then the firmware can simply try writing and re-reading again. If the MDIOS frequency is very slow compared to the mdios_pclk frequency, then it might be best not to tie up the CPU by continuously writing and re-reading a DOUT register. Please note that the read flag (RDFn) is set as soon as the DOUTn value is passed to the MDIOS clock domain. Thus, when a write to DOUTn is ignored (when the value read back is not the value which was just written), then the firmware can use a read interrupt to know when it is able to write DOUTn. DocID029587 Rev 3 2275/3178 2286 Management data input/output (MDIOS) RM0433 Here is a procedure which can be used if the MDC clock is very slow: 1. Write DOUTn. 2. Assure that all of the read flags are zero (MDIOS_RDFR = 0x0000). Clear the flags if necessary using MDIOS_CRDFR. 3. Read back the same DOUTn register and compare the value with the value which was written in step 1. 4. If the values are the same, then the procedure is done. Otherwise, continue to step 5. 5. Enable read interrupts by setting the RDIE bit in MDIOS_CR1. 6. In the interrupt routine, assure that RDFn is set. (no other read flags will be set before bit n). 7. There is a 31 cycle + preamble time window (if the master sends a preamble before each frame) to write DOUTn safely without needing to do a read-back and compare. If this maximum delay cannot be guaranteed, go back to step #1. If the MDIO master performs a read operation with a register address which is greater than 31, the MDIOS returns a data value of all zeros. 54.3.6 MDIOS APB frequency Whenever the firmware reads from an MDIOS_DINRn register or writes to an MDIOS_DOUTRn register, the frequency of the APB bus must be at least 1.5 times the MDC frequency. For example, if MDC is at 20MHz, the APB must be at 30MHz or faster. 54.3.7 Write/read flags and interrupts When MDIOS register ‘n’ is written via the MDIO bus, the WRFn bit in the MDIOS_WRFR register is set. WRFn becomes ‘1’ a the moment that DINn is updated, which is when the last data bit is sampled on a write frame. An interrupt is generated if WRIEN=1 (in the MDIOS_CR register). WRFn is cleared by software by writing ‘1’ to CWRFn (in the MDIOS_CWRFR register). When MDIOS register ‘n’ is read via the MDIO bus, the RDFn bit in the MDIOS_RDFR register is set. RDFn becomes ‘1’ at the moment that DOUTn is copied to the MDC clock domain, which is on the 15th cycle of a read frame. An interrupt is generated if RDIEN=1 (in the MDIOS_CR register). RDFn is cleared by software by writing ‘1’ to CRDFn (in the MDIOS_CRDFR register). 54.3.8 MDIOS error management There are three types of errors with their corresponding error flags: • Preamble error: PERF (bit 0 of MDIOS_SR register) • Start error: SERF (bit 1 of MDIOS_SR register) • Turnaround error: TERF (bit 2 of MDIOS_SR register) Each error flag is set by hardware when the corresponding error condition occurs. Each flag can be cleared by writing ‘1’ to the corresponding bit in the clear flag register (MDIOS_CLRFR). An interrupt occurs if any of the three error flags is set while EIE=1 (MDIOS_CR). 2276/3178 DocID029587 Rev 3 RM0433 Management data input/output (MDIOS) Besides setting an error flag, the MDIOS performs no action for a frame in which an error is detected: the DINn registers are not updated and the MDIO line is not forced during the data phase. For a given frame, errors do not accumulate. For example, if a preamble error is detected, no check is done for a start error or a turnaround error for the rest of the current frame. When DPC=0, following an detected error, all new frames and errors will be ignored until a complete full preamble has been detected. When DPC=1 (Disable Preamble Check, MDIOS_CR[7]), all frames and new errors are ignored as long as one of the error flags is set. As soon as the error bit is cleared, the MDIOS starts looking for a start sequence. Thus, the application must clear the error flag only when it is sure that no frame is currently in progress. Otherwise, the MDIOS will likely misinterpret the bits being sent and become desynchronized with the master. Preamble errors A preamble error occurs when a start sequence begins (with MDIO sampled at ‘0’) without being immediately preceded by a preamble (MDIO sampled at ‘1’ for at least 32 consecutive clocks). Preamble errors are not reported after the MDIOS is first enabled (EN=1 in MDIOS_CR) until after a full preamble is received. This is to avoid an error condition when the peripheral frame detection is enabled while a preamble or frame is already in progress. In this case, the MDIOS ignores the first frame (since it did not first detect a full preamble), but does not set PERF. If the DPC bit (Disable Preamble Check, MDIOS_CR[7]) is set, then the MDIO Master can send frames without preceding preambles and no preamble error will be signaled. When DPC=1, the application must assure that the master is not in the process of sending a frame at the moment that the MDIOS is enabled (EN is set). Otherwise, the slave might become desynchronized with the master. Start errors A start error occurs when an illegal start sequence occurs or if an illegal command is given. The start sequence must always be “01”, and the command must be either “01” (write) or “10” (read). As with preamble errors, start errors are not reported until after a full preamble is received. Turnaround errors A turnaround error occurs when an error is detected in the turnaround bits of write frames. The 15th bit of the write frame must be ‘1’ and the 16th bit must be ‘0’. Turnaround errors are only reported after a full preamble is received, there is no start error, the port address in the current frame matches and the register address is in the supported range 0 to 31. 54.3.9 MDIOS in Stop mode The MDIOS can operate in Stop mode, responding to all reads, performing all writes, and causing the STM32 to wakeup from Stop mode on MDIOS interrupts. DocID029587 Rev 3 2277/3178 2286 Management data input/output (MDIOS) 54.3.10 RM0433 MDIOS interrupts There is a single interrupt vector for the three types of interrupts (write, read, and error). Any of these interrupt sources can wake the STM32 up from Stop mode. All interrupt flags need to be cleared in order to clear the interrupt line. Table 423. Interrupt control bits 2278/3178 Interrupt event Event flag Enable control bit Write interrupt WRF[31:0] WRIE Read interrupt RDF[31:0] RDIE Error interrupt PERF (preamble), SERF (start), TERF (turnaround) EIE DocID029587 Rev 3 RM0433 Management data input/output (MDIOS) 54.4 MDIOS registers 54.4.1 MDIOS configuration register (MDIOS_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 15 14 13 Res. Res. Res. PORT_ADDRESS[4:0] rw rw rw rw 7 6 5 4 3 2 1 0 DPC Res. Res. Res. EIE RDIE WRIE EN rw rw rw rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 PORT_ADDRESS[4:0]: Slave’s address. Can be written only when the peripheral is disabled (EN=0). If the address given by the MDIO master matches PORT_ADRESS[4:0], then the MDIOS services the frame. Otherwise the frame is ignored. Bit 7 DPC: Disable Preamble Check. 0: MDIO Master must give preamble before each frame. 1: MDIO Master can send each frame without a preceding preamble, and the MDIOS will not signal a preamble error. When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. This bit cannot be changed unless EN=0 (though it can be changed at the same time that EN is being set). Bits 6:4 Reserved, must be kept at reset value. Bit 3 EIE: Error interrupt enable. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set. Bit 2 RDIE: Register Read Interrupt Enable. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if any of the read flags (RDF[31:0] in the MDIOS_RDFR register) is set. Bit 1 WRIE: Register write interrupt enable. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if any of the read flags (WRF[31:0] in the MDIOS_WRFR register) is set. Bit 0 EN: Peripheral enable. 0: MDIOS is disabled 1: MDIOS is enabled and monitoring the MDIO bus (MDC/MDIO) DocID029587 Rev 3 2279/3178 2286 Management data input/output (MDIOS) 54.4.2 RM0433 MDIOS write flag register (MDIOS_WRFR) Address offset: 0x04 Power-on reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRF[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r WRF[15:0] r r Bits 31:0 WRF[31:0]: Write flags for MDIOS registers 0 to 31. Each bit is set by hardware when the MDIO master performs a write to the corresponding MDIOS register. An interrupt is generates if WRIE (in MDIOS_CR) is set. Each bit is cleared by software by writing ‘1’ to the corresponding CWRF bit in the MDIOS_CWRFR register. For WRFn: 0: MDIOS register ‘n’ has not been written by the MDIO master 1: MDIOS register ‘n’ has been written by the MDIO master and the data is available in DINn[15:0] in the MDIOS_DINRn register 54.4.3 MDIOS clear write flag register (MDIOS_CWRFR) Address offset: 0x08 Power-on reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CWRF[31:16] w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 15 14 13 12 11 10 9 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 8 7 6 5 4 3 2 1 0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 CWRF[15:0] w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 Bits 31:0 CWRF[31:0]: Clear the write flag Writing ‘1’ to CWRFn clears the WRFn bit in the MDIOS_WRF register. 2280/3178 DocID029587 Rev 3 RM0433 Management data input/output (MDIOS) 54.4.4 MDIOS read flag register (MDIOS_RDFR) Address offset: 0x0C Power-on reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDF[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r RDF[15:0] r r Bits 31:0 RDF[31:0]: Read flags for MDIOS registers 0 to 31. Each bit is set by hardware when the MDIO master performs a read from the corresponding MDIOS register. An interrupt is generates if RDIE (in MDIOS_CR) is set. Each bit is cleared by software by writing ‘1’ to the corresponding CRDF bit in the MDIOS_CRDFR register. For RDFn: 0: MDIOS register ‘n’ has not been read by the MDIO master 1: MDIOS register ‘n’ has been read by the MDIO master 54.4.5 MDIOS clear read flag register (MDIOS_CRDFR) Address offset: 0x10 Power-on reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRDF[31:16] w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 w_r0 CRDF[15:0] w_r0 Bits 31:0 CRDF[31:0]: Clear the read flag Writing ‘1’ to CRDFn clears the RDFn bit in the MDIOS_RDF register. DocID029587 Rev 3 2281/3178 2286 Management data input/output (MDIOS) 54.4.6 RM0433 MDIOS status register (MDIOS_SR) Address offset: 0x14 Power-on reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TERF SERF PERF r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 TERF: Turnaround error flag 0: No turnaround error has occurred 1: A turnaround error has occurred Writing ‘1’ to CTERF (MDIOS_CLRFR) clears this bits. Bit 1 SERF: Start error flag 0: No start error has occurred 1: A start error has occurred Writing ‘1’ to CSERF (MDIOS_CLRFR) clears this bits. Bit 0 PERF: Preamble error flag 0: No preamble error has occurred 1: A preamble error has occurred Writing ‘1’ to CPERF (MDIOS_CLRFR) clears this bits. This bit will not get set if DPC (Disable Preamble Check, MDIOS_CR[7]) is set. Note: 2282/3178 Writes to MDIOS_SR have no effect. DocID029587 Rev 3 RM0433 Management data input/output (MDIOS) 54.4.7 MDIOS clear flag register (MDIOS_CLRFR) Address offset: 0x18 Power-on reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTERF CSERF CPERF w_r0 w_r0 w_r0 Bits 31:3 Reserved, must be kept at reset value. Bit 2 CTERF: Clear the turnaround error flag Writing ‘1’ to this bit clears the TERF flag (MDIOS_SR). When DPC=’1’ (MDIOS_CR[7]), the TERF flag must be cleared only when there is not a frame already in progress. Bit 1 CSERF: Clear the start error flag Writing ‘1’ to this bit clears the SERF flag (MDIOS_SR). When DPC=’1’ (MDIOS_CR[7]), the SERF flag must be cleared only when there is not a frame already in progress. Bit 0 CPERF: Clear the preamble error flag Writing ‘1’ to this bit clears the PERF flag (MDIOS_SR). Note: Reading MDIOS_CLRFR returns all zeros. DocID029587 Rev 3 2283/3178 2286 Management data input/output (MDIOS) 54.4.8 RM0433 MDIOS input data register (MDIOS_DINR0-MDIOS_DINR31) Address offset: 0x100-0x17C Reset value: 0x0000_0000 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r DINn[15:0] r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 DINn[15:0]: Input data received from MDIO Master during write frames This field written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register ‘n’. 54.4.9 MDIOS output data register (MDIOS_DOUTR0-MDIOS_DOUTR31) Address offset: 0x180-0x1FC Reset value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw DOUTn[15:0] rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 DOUTn[15:0]: Output data sent to MDIO Master during read frames This field is written by SW. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register ‘n’. 2284/3178 DocID029587 Rev 3 0x184 MDIOS_DOUTR1 Res. Reset value Reset value Reset value Reset value Reset value DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIN31[15:0] 0 DOUT0[15:0] 0 DOUT1[15:0] 0 Res. ... Res. 0 Res. DIN1[15:0] Res. 0 Res. DIN0[15:0] Res. Res. 0 0 0 0 0 0 MDIOS_SR Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. EN 0 WRIE 0 EEI 0 RDIE 0 Reset value Reset value PERF 0 Res. 0 SERF 0 Res. 0 CPERF 0 Res. 0 CSERF 0 Res. 0 TERF 0 Res. RDF[31:0] 0 CTERF 0 Res. CWRF[31:0] 0 Res. 0 Res. WRF[31:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PORT_ ADDRESS[4:0] Res. Res. Res. Res. Res. 0 Res. 0 Res. Reset value Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. MDIOS_CRDFR 0 Res. 0 Res. 0 Res. MDIOS_RDFR 0 Res. Res. Res. 0 Res. 0 Res. MDIOS_CWRFR Res. Res. 0 Res. Res. Res. MDIOS_WRFR Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. MDIOS_DINR0 Res. 0 Res. Res. Reserved Res. 0 Res. 0 Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. 0 0 Res. MDIOS_DOUTR0 0 0 Res. 0x180 MDIOS_DINR31 0 Res. 0x17C MDIOS_DINR1 0 Res. 0x104 0 0 0 Res. 0x100 MDIOS_CLRFR Res. Reset value 0 Res. 0x1C 0xFC Res. 0x18 Res. 0x14 Res. 0x10 Res. 0x0C 0 Res. Reset value Res. 0x08 0 Res. Reset value Res. 0x04 MDIOS_CR Res. 0x00 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 54.4.10 Res. RM0433 Management data input/output (MDIOS) MDIOS register map Table 424. MDIOS register map and reset values CRDF[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 2285/3178 2286 Management data input/output (MDIOS) RM0433 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MDIOS_DOUTR31 Res. 0x1FC Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 424. MDIOS register map and reset values (continued) Reset value 2286/3178 DOUT31[15:0] 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 55 Secure digital input/output MultiMediaCard interface (SDMMC) 55.1 SDMMC main features The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices. The MultiMediaCard system specifications are available through the MultiMediaCard Association website at www.mmca.org, published by the MMCA technical committee. SD memory card and SD I/O card system specifications are available through the SD card Association website at www.sdcard.org. The SDMMC features include the following: • Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit. • Full compatibility with previous versions of MultiMediaCards (backward compatibility). • Full compliance with SD memory card specifications version 4.1. (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported). • Full compliance with SDIO card specification version 4.0. Card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported). • Data transfer up to 208 Mbyte/s for the 8-bit mode. (depending maximum allowed I/O speed). • Data and command output enable signals to control external bidirectional drivers. The MultiMediaCard/SD bus connects cards to the host. The current version of the SDMMC supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version 4.51 or previous. 55.2 SDMMC bus topology Communication over the bus is based on command/response and data transfers. The basic transaction on the SD/SDIO/MMC bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure. In addition, some operations have a data token. Data transfers are done in the following ways: • Block mode: data block(s) with block size 2N bytes with N in the range 0-14. • SDIO multibyte mode: single data block with block size range 1-512 bytes • MMC Stream mode: continuous data stream Data transfers to/from MMC cards are done in data blocks or streams. DocID029587 Rev 3 2287/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Figure 689. SDMMC “no response” and “no data” operations 6'00&B&0' &0' &0' 5HVSRQVH 6'00&B' 2SHUDWLRQQRUHVSRQVHDQGQRGDWD 2SHUDWLRQUHVSRQVHQRGDWD )URPKRVWWRFDUG )URPFDUGWRKRVW 06Y9 Figure 690. SDMMC (multiple) block read operation 'DWDVWRSRSHUDWLRQ 6'00&B&0' &0' 6'00&B' 5HVSRQVH &0' 'DWDEORFN &5& 'DWDEORFN &5& 'DWDEORFN 5HVSRQVH &5& %ORFNUHDGRSHUDWLRQ 0XOWLSOHEORFNUHDGRSHUDWLRQ )URPKRVWWRFDUG )URPFDUGWRKRVW Note: 06Y9 The Stop Transmission command is not required at the end of a MMC multiple block read with predefined block count. Figure 691. SDMMC (multiple) block write operation 'DWDVWRSRSHUDWLRQ 6'00&B&0' &0' 6'00&B' 5HVSRQVH &0' &5& VWDWXV 'DWDEORFN &5& %XV\ 'DWDEORFN &5& &5& VWDWXV 5HVSRQVH %XV\ %ORFNZULWHRSHUDWLRQ 0XOWLSOHEORFNZULWHRSHUDWLRQ )URPKRVWWRFDUG )URPFDUGWRKRVW 06Y9 Note: The Stop Transmission command is not required at the end of a MMC multiple block write with predefined block count. Note: The SDMMC will not send any data as long as the Busy signal is asserted (SDMMC_D0 pulled low). 2288/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 692. SDMMC (sequential) stream read operation 'DWDVWRSRSHUDWLRQ 6'00&B&0' &0' 5HVSRQVH &0' 6'00&B' 5HVSRQVH 'DWDVWUHDP 6WUHDPUHDGRSHUDWLRQ )URPKRVWWRFDUG )URPFDUGWRKRVW 06Y9 Figure 693. SDMMC (sequential) stream write operation 'DWDVWRSRSHUDWLRQ 6'00&B&0' &0' 5HVSRQVH &0' 6'00&B' 'DWDVWUHDP 5HVSRQVH %XV\ 6WUHDPZULWHRSHUDWLRQ )URPKRVWWRFDUG )URPFDUGWRKRVW 06Y9 Stream data transfer operates only in a 1-bit wide bit bus configuration on SDMMC_D0 in single data rate modes (DS, HS, and SDR). 55.3 SDMMC operation modes Table 425. SDMMC operation modes SD & SDIO Max Bus Speed (3) [MByte/s] Max Clock frequency [MHz] Signal Voltage [V] 12.5 25 3.3 25 50 3.3 SDR12 12.5 25 1.8 SDR25 25 50 1.8 DDR50 50 50 1.8 SDR50 50 100 1.8 SDIO Bus Speed modes(1)(2) DS (Default Speed) HS (High Speed) SDR104 104 (4) 208 1.8 1. SDR single data rate signaling. 2. DDR double data rate signaling. (data is sampled on both SDMMC_CK clock edges). 3. SDIO bus speed with 4bit bus width. 4. Maximum frequency depending maximum allowed I/O speed. DocID029587 Rev 3 2289/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 SDR104 mode requires variable delay support using sampling point tuning. The use of variable delay is optional for SDR50 mode. Table 426. SDMMC operation modes eMMC Max Bus Speed (3) [MByte/s] Max Clock frequency [MHz] Signal Voltage [V] Legacy compatible 26 26 3/1.8/1.2V High speed SDR 52 52 3/1.8/1.2V High speed DDR 104 52 3/1.8/1.2V eMMC Bus Speed modes (1)(2) High speed HS200 200 (4) 200 1.8/1.2V 1. SDR single data rate signaling. 2. DDR double data rate signaling. (data is sampled on both SDMMC_CK clock edges). 3. eMMC bus speed with 8bit bus width. 4. Maximum frequency depending maximum allowed I/O speed 55.4 SDMMC functional description The SDMMC consists of three parts: • The AHB slave interface accesses the SDMMC adapter registers, and generates interrupt signals and IDMA control signals. • The SDMMC adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. • The internal DMA (IDMA) block with its AHB master interface. The DLYB delay block in the device can be used to align the sampling clock on the data received by SDMMC. It is mandatory for SDMMC to support the SDR104 mode. 2290/3178 DocID029587 Rev 3 RM0433 55.4.1 Secure digital input/output MultiMediaCard interface (SDMMC) SDMMC diagram Figure 694 shows the SDMMC block diagram. Figure 694. SDMMC block diagram 6'00&$'$37(5 6'00& 6'00&B'',5 VGPPFBNHUBFN 6'00&B'',5 &RQWURO XQLW $+%,17(5)$&( 6'00&B&',5 ELW$+% VODYHEXV 6'00&B&. VGPPFBLRBLQBFN VGPPFBKFON 5HJLVWHUV 'DWDWUDQVPLW SDWK VGPPFBLW &/. 08; '/<% 'HOD\EORFN VGPPFBIEBFN &RPPDQG SDWK VGPPFBGDWDHQGBWUJ 6'00&B&.,1 ),)2 'DWDUHFHLYH SDWK ELW$+% PDVWHUEXV 6'00&B&0' 5HVSRQVH SDWK ,'0$ 6'00&B'> @ 06Y 9 55.4.2 SDMMC pins and internal signals Table 427 lists the SDMMC internal input/output signals, Table 428 the SDMMC pins (alternate functions). Table 427. SDMMC internal input/output signals Signal name Signal type Description sdmmc_ker_ck Digital input SDMMC kernel clock sdmmc_hclk Digital input AHB clock sdmmc_it Digital output SDMMC global interrupt sdmmc_dataend_trg Digital output SDMMC data end trigger for MDMA sdmmc_io_in_ck Digital input SD/SDIO/MMC card feedback clock. This signal is internally connected to the SDMMC_CK pin (for DS and HS modes). sdmmc_fb_ck Digital input SD/SDIO/MMC card tuned feedback clock after DLYB delay block (for SDR50, DDR50, SDR104) Table 428. SDMMC pins Signal name Signal type SDMMC_CK Digital output Clock to SD/SDIO/MMC card SDMMC_CKIN Digital input Description Clock feedback from an external driver for SD/SDIO/MMC card. (for SDR12, SDR25, SDR50, DDR50) DocID029587 Rev 3 2291/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Table 428. SDMMC pins Signal name Signal type SDMMC_CMD Digital input/output SDMMC_CDIR Digital output SDMMC_D[7:0] Digital input/output SDMMC_D0DIR Digital output SDMMC_D123DIR Digital output 55.4.3 Description SD/SDIO/MMC card bidirectional command/response signal. SD/SDIO/MMC card I/O direction indication for the SDMMC_CMD signal. SD/SDIO/MMC card bidirectional data lines. SD/SDIO/MMC card I/O direction indication for the SDMMC_D0 data line. SD/SDIO/MMC card I/O direction indication for the data lines SDMMC_D[3:1]. General description The SDMMC_D[7:0] lines have different operating modes: • By default, SDMMC_D0 line is used for data transfer. After initialization, the host can change the databus width. • For an MMC, 1-bit (SDMMC_D0), 4-bit (SDMMC_D[3:0]) or 8-bit (SDMMC_D[7:0]) data bus widths can be used. • For an SD or an SDIO card, 1-bit (SDMMC_D0) or 4-bit (SDMMC_D[3:0]) can be used. All data lines operate in push-pull mode. To allow the connection of an external driver (a voltage switch transceiver), the direction of data flow on the data lines is indicated with I/O direction signals. The SDMMC_D0DIR signal indicates the I/O direction for the SDMMC_D0 data line, the SDMMC_D123DIR for the SDMMC_D[3:1] data lines. SDMMC_CMD only operates in push-pull mode: To allow the connection of an external driver (a voltage switch transceiver), the direction of data flow on the SDMMC_CMD line is indicated with the I/O direction signal SDMMC_CDIR. SDMMC_CK clock to the card originates from sdmmc_ker_ck: 2292/3178 • When the sdmmc_ker_ck clock has 50 % duty cycle, it can be used even in bypass mode (CLKDIV = 0). • When the sdmmc_ker_ck duty cycle is not 50 %, the CLKDIV must be used to divide it by 2 or more (CLKDIV > 0). • The phase relation between the SDMMC_CMD / SDMMC_D[7:0] outputs and the SDMMC_CK can be selected through the NEGEDGE bit. The phase relation depends on the CLKDIV, NEGEDGE, and DDR settings. See Figure 695. DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 695. SDMMC Command and data phase relation &/.',9 &/.',9! ''5 1(*('*( &/.',9! ''5 1(*('*( &/.',9! ''5 1(*('*( &/.',9! ''5 1(*('*( 6'00&B&0' 6'00&B'Q 6'00&B&. VGPPFBNHUBFN 06Y 9 CLKDIV DDR NEGEDGE Table 429. SDMMC Command and data phase selection SDMMC_CK 0 x x = sdmmc_ker_ck 0 >0 0 1 1 Data out generated on sdmmc_ker_ck falling edge generated on sdmmc_ker_ck falling edge succeeding the SDMMC_CK rising edge. 0 1 Command out generated on sdmmc_ker_ck rising edge generated on the same sdmmc_ker_ck rising edge that generates the SDMMC_CK falling edge. generated on sdmmc_ker_ck falling edge succeeding the SDMMC_CK rising edge. generated on the same sdmmc_ker_ck rising edge that generates the SDMMC_CK falling edge. generated on sdmmc_ker_ck falling edge succeeding a SDMMC_CK edge. By default, the sdmmc_io_in_ck feedback clock input is selected for sampling incoming data in the SDMMC receive path. It is derived from the SDMMC_CK pin. For tuning the phase of the sampling clock to accommodate the receive data timing, the DLYB delay block available on the device can be connected between sdmmc_io_in_ck signal (DLYB input dlyb_in_ck) and sdmmc_fb_ck clock input of SDMMC (DLYB output dlyb_out_ck). Selecting the sdmmc_fb_ck clock input in the receive path then allows using the phase-tuned sampling clock for the incoming data. This is required for SDMMC to support the SDR104 operating mode and optional for SDR50 and DDR50 modes. When using an external driver (a voltage switch transceiver), the SDMMC_CKIN feedback clock input can be selected to sample the receive data. For an SD/SDIO/MMC card, the clock frequency can vary between 0 and 208 MHz (limited by maximum I/O speed). DocID029587 Rev 3 2293/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Depending on the selected bus mode (SDR or DDR), one bit or two bits are transferred on SDMMC_D[7:0] lines with each clock cycle. The SDMMC_CMD line transfers only one bit per clock cycle. 55.4.4 SDMMC adapter The SDMMC adapter (see Figure 694: SDMMC block diagram) is a multimedia/secure digital memory card bus master that provides an interface to a MultiMediaCard stack or to a secure digital memory card. It consists of the following subunits: Note: • Control unit • Data transmit path • Command path • Data receive path • Response path • Receive data path clock multiplexer. • Adapter register block • Data FIFO • Internal DMA (IDMA) The adapter registers and FIFO use the AHB clock domain (sdmmc_hclk). The control unit, command path and data transmit path use the SDMMC adapter clock domain (sdmmc_ker_ck). The response path and data receive path use the SDMMC adapter feedback clock domain from the sdmmc_io_in_ck, or SDMMC_CKIN, or from the sdmmc_fb_ck generated by DLYB. The DLYB delay block on the device can be used in conjunction with the SDMMC adapter, to tune the phase of the sampling clock for incoming data in SDMMC receive mode. It is required for the SDMMC to support the SDR104 operating mode and optional for SDR50 and DDR50 modes. Adapter register block The adapter register block contains all system control registers, the SDMMC command and response registers and the data FIFO. This block also generates the signals from the corresponding bit location in the SDMMC Clear register that clear the static flags in the SDMMC adapter. Control unit The control unit illustrated in Figure 696, contains the power management functions, the SDMMC_CK clock management with divider, and the I/O direction management. 2294/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 696. Control unit &RQWUROXQLW 5HJLVWHUV 6'00&B'',5 3RZHU PDQDJHPHQW VGPPFBNHUBFN ,2 PDQDJHPHQW 6'00&B'',5 6'00&B&',5 &ORFN PDQDJHPHQW 6'00&B&. 7RFRPPDQGUHVSRQVHDQGGDWDSDWKV 06Y 9 The power management subunit disables the card bus output signals during the power-off and power-up phases. There are three power phases: • power-off • power-up • power-on The clock management subunit uses the sdmmc_ker_ck to generate the SDMMC_CK and provides the division control. It also takes care of stopping the SDMMC_CK for i.e. flow control. The clock outputs are inactive: • after reset • during the power-off or power-up phases • if the power saving mode (register bit PWRSAV) is enabled and the card bus is in the Idle state for eight clock periods. The clock will be stopped eight cycles after both the command/response CPSM and data path DPSM subunits have enter the Idle phase. The clock will be restarted when the command/response CPSM or data path DPSM is activated (enabled). The I/O management subunit takes care of the SDMMC_Dn and SDMMC_CMD I/O direction signals, which controls the external voltage transceiver. Command/Response path The Command/Response path subunit transfers commands and responses on the SDMMC_CMD line. The Command path is clocked on the SDMMC_CK and sends commands to the card,.The Response path is clocked on the sdmmc_rx_ck and receives responses from the card. DocID029587 Rev 3 2295/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Figure 697. Command/Response path 7RFRQWUROXQLW &RPPDQG5HVSRQVH SDWK 5HJLVWHUV 6WDWXV IODJ &RPPDQG WLPHU &RQWURO ORJLF 5HVSRQVH UHJLVWHUV 5HVSRQVH VKLIW UHJLVWHU &5& LQ 6'00&B&0' VGPPFBU[BFN &RPPDQG UHJLVWHUV &RPPDQG VKLIW UHJLVWHU &5& RXW 6'00&B&. 06Y9 Command/Response path state machine (CPSM) • • When the command register is written to and the enable bit is set, command transfer starts. When the command has been sent the CRC is appended and the command path state machine (CPSM) sets the status flags and: – if a response is not required enters the Idle state. – If a response is required, it waits for the response. When the response is received, – for a response with CRC, the received CRC code and the internally generated code are compared, and the appropriate status flag is set according the result. – for a response without CRC, no CRC is checked, and the appropriate status flag is not set. When ever the CPSM is active, i.e. not in the Idle state, the CPSMACT bit is set. 2296/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 698. Command path state machine (CPSM) 5HVHW 6'00&B&0'ZULWH DQG &360(1 DQG DQG :$,73(1' 3HQGLQJ ,GOH 6'00&B&0'ZULWH DQG &360(1 DQG %227(1 '360VHQG&0' RU :$,73(1' %22702'( DQG %227(1 (QGRIUHVSRQVH RU &5&VWDWXVHUURU 6'00&B&0'ZULWH DQG &360(1 DQG :$,73(1' DQG %227(1 5HFHLYH %22702'( DQG %227(1 6WDUWELWGHWHFWHG (QGRI&0' DQG :$,75(63 %RRW :DLW %22702'( 6HQG • • (QGRI&0' DQG :$,75(63 QRW 06Y9 Idle: The command path is inactive. When the command control register is written and the enable bit (CPSMEN) is set, the CPSM will activate the SDMMC_CK clock (when stopped due to power save PWRSAV bit) and moves – to the Send state when WAITPEND = 0 & BOOTEN = 0. – to the Pending state when WAITPEND = 1. – to the boot state when BOOTEN = 1. Send: The command is sent and the CRC is appended. – When CMDTRANS bit is set or when BOOTEN bit is set and BOOTMODE is alternative boot, and the DTDIR = receive, the CPSM DataEnable signal will be issued to the DPSM at the end of the command. – When the CMDTRANS bit is set and the CMDSUSPEND bit is 0 the interrupt period will be terminated at the end of the command. – When CMDSTOP bit is set the CPSM Abort signal will be issue to the DPSM at the end of the command. – If no response is expected (WAITRESP = 00) the CPSM will move to the Idle state and generate the CMDSENT flag. When BOOTMODE = 1 & BOOTEN = 0 the CMDSENT flag is delayed 56 cycles after the command End bit, otherwise the DocID029587 Rev 3 2297/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 CMDSENT flag is generated immediately after the command End bit. The RESPCMDR and RESPxR registers are not modified. – • • • 2298/3178 If a command response is expected (WAITRESP = not 00) the CPSM will move to the Wait state and start the response timeout. Wait: The Command path waits for a response. – When WAITINT bit is 0 the command timer starts running and the CPSM waits for a Start bit. a) If a Start bit is detected before the timeout the CPSM moves to the Receive state. b) If the timeout is reached before the CPSM detect a response start bit, the timeout flag (CTIMEOUT) is set and the CPSM moves to the Idle state. The RESPCMDR and RESPxR registers are not modified. – When WAITINT bit is 1, the timer is disabled and the CPSM waits for an interrupt request (Response Start bit) from one of the cards. a) When a Start bit is detected the CPSM moves to the Receive state. b) When writing WAITINT to 0 (interrupt mode abort), the host will send a response by its self and on detecting the Start bit the CPSM move to the Receive state. Receive: The command response will be received. Depending the response mode bits WAITRESP in the command control register, the response can be either short or long, with CRC or without CRC. The received CRC code when present will be verified against the internally generated CRC code. – When the CMDSUSPEND bit is set and the SDIO Response bit BS = 0 (response bit [39]), the interrupt period will be started after the response. When the CMDSUSPEND bit is cleared, or the CMDSUSPEND bit is 1 and the SDIO Response bit BS = 1 (response bit [39]), there will be no interrupt period started. – When the CMDTRANS bit is set and the CMDSUSPEND bit is set and the SDIO Response bit DF= 1 (response bit [32]) the interrupt period will be terminated after the response. – When the CRC status passes or no CRC is present the CMDREND flag is set, the CPSM moves to the Idle state. The RESPCMDR and RESPxR registers are updated with received response. - When BOOTMODE = 1 & BOOTEN = 0 the CMDREND flag is delayed 56 cycles after the response End bit, otherwise the CMDREND flag is generated immediately after the response End bit. - When CMDTRANS bit is set and the DTDIR = transmit, the CPSM DataEnable signal will be issued to the DPSM at the end of the command response. – When the CRC status fails the CCRCFAIL flag is set and the CPSM moves to the Idle state. The RESPCMDR and RESPxR registers are updated with received response. Pending: According the pending WAITPEND bit in the command register, the CPSM enters the pending state. – When DATALENGTH =< 5 bytes the CPSM moves to the Sent state en generates the DataEnable signal to start the data transfer aligned with the CMD12 Stop Transmission command. – When DATALENGTH > 5 bytes, the CPSM DataEnable signal will be issued to the DPSM to start the data transfer. The CPSM waits for a sendCMD signal from the DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) DPSM before moving to the Sent state. This enables i.e. the CMD12 Stop Transmission command to be sent aligned with the data. – • When writing WAITPEND to 0, the CPSM will move to the Sent state. Boot: If the BOOTEN bit is set in the command register, the CPSM enters the boot state, and when: – BOOTMODE = 0 the SDMMC_CMD line is driven low and when CMDTRANS bit is set and the DTDIR = receive, the CPSM DataEnable signal will be issued to the DPSM. This enables normal boot operation. This state is left at the end of the boot procedure by clearing the register bit BOOTEN, which cause the SDMMC_CMD line to be driven high and the CPSM Abort signal will be issued to the DPSM, before moving to the Idle state.The CMDSENT flag is generated 56 cycles after SDMMC_CMD line is high. – BOOTMODE = 1, move to the Send state. This enables sending of the CMD0 (boot). Clearing BOOTEN has no effect. Note: The CPSM remains in the Idle state for at least eight SDMMC_CK periods to meet the NCC and NRC timing constraints. NCC is the minimum delay between two host commands, and NRC is the minimum delay between the host command and the card response. Note: The response timeout has a fixed value of 64 SDMMC_CK clock periods. A Command is a token that starts an operation. Commands are sent from the host to either a single card (addressed command) or all connected cards (broadcast command are available for MMC V3.31 or previous). Commands are transferred serially on the SDMMC_CMD line. All commands have a fixed length of 48 bits. The general format for a command token for SD-Memory cards, SDIO cards, and MMC cards is shown in Table 430.. The Command token data is taken from 2 registers, one containing a 32-bits argument and the other containing the 6-bits command index (six bits sent to a card). Table 430. Command token format Bit position Width Value Description 47 1 0 Start bit 46 1 1 Transmission bit [45:40] 6 x Command index [39:8] 32 x Argument [7:1] 7 x CRC7 0 1 1 End bit Next to the Command data there are command type (WAITRESP) bits controlling the command path state machine (CPSM). These bits also determine whether the command requires a response, and whether the response is short (48 bit) or long (136 bits) long, and if a CRC is present or not. A Response is a token that is sent from an addressed card or synchronously from all connected cards to the host as an answer to a previous received Command. All responses are sent via the command line SDMMC_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type. Response tokens R1, R2, R3, R4, R5, and R6 have various coding schemes, depending on their content. The general formats for the response tokens DocID029587 Rev 3 2299/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 for SD-Memory cards, SDIO cards, and MMC cards are shown in Table 431, Table 432 and Table 433. A response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the tables below indicates a variable entry. Most responses, except some, are protected by a CRC. Every command code word is terminated by the End bit (always 1). The Response token data is stored in 5 registers, four containing the 32-bits card status, OCR register, argument or 127-bits CID or CSD register including internal CRC, and one register containing the 6-bits command index. Table 431. Short response with CRC token format Bit position Width Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 x Command index (or reserved 111111) [39:8] 32 x Argument [7:1] 7 x CRC7 0 1 1 End bit Table 432. Short response without CRC token format Bit position Width Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 x Command index (or reserved 111111) [39:8] 32 x Argument [7:1] 7 1111111 0 1 1 (reserved 1111111) End bit Table 433. Long response with CRC token format Bit position Width Value 135 1 0 Start bit 134 1 0 Transmission bit [133:128] 6 111111 127:8 x CID or CSD slices 7:1 x CRC7 (included in CID or CSD) 1 1 End bit [127:1] 0 Description Reserved The Command/Response path operates in a half-duplex mode, so that either commands can be sent or responses can be received. If the CPSM is not in the Send state, the 2300/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) SDMMC_CMD output is in the Hi-Z state. Data sent on SDMMC_CMD are synchronous with the SDMMC_CK according the NEGEDGE register bit see Figure 695. The Command and Short Response with CRC, the CRC generator calculates the CRC checksum for all 40 bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). For the Long Response the CRC checksum is calculated only over the 120 bits of R2 CID or CSD. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC calculation. The CRC checksum is a 7-bit value: CRC[6:0] = Remainder [(M(x) * x7) / G(x)] G(x) = x7 + x3 + 1 M(x) = (first bit) * xn + (second bit) * xn-1+... + (last bit before CRC) * x0 Where n = 39 or 119. The CPSM allows to send a number of specific commands to handle various operating modes when CPSMEN is set, see Table 434. VSWITCH BOOTEN BOOTMODE CMDTRANS WAITPEND CMDSTOP WAITINT Table 434. Specific Commands overview 1 x x x x x x Start Voltage Switch Sequence 0 1 x x x x x Start normal boot 0 1 1 x x x x Start alternative boot 0 0 1 x x x x Stop alternative boot. 0 0 0 1 x x x Send command with associated data transfer. 0 0 0 0 1 1 x MMC stream data transfer, command (STOP_TRANSMISSION) pending until end of data transfer. 0 0 0 0 1 0 x MMC stream data transfer, command different from (STOP_TRANSMISSION) pending until end of data transfer. 0 0 0 0 0 1 x Send command (STOP_TRANSMISSION), stopping any ongoing data transmission. 0 0 0 0 0 0 1 Enter MMC wait interrupt (Wait-IRQ) mode. 0 0 0 0 0 0 0 Any other none specific command Description The Command/Response path implements the status flags and associated clear bits shown in Table 435: DocID029587 Rev 3 2301/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Table 435. Command path status flags Flag Description CMDSENT Set at the end of the command without response. (CPSM moves from SEND to IDLE) CMDREND Set at the end of the command response when the CRC is OK. (CPSM moves from RECEIVE to IDLE) CCRCFAIL Set at the end of the command response when the CRC is FAIL. (CPSM moves from RECEIVE to IDLE) CTIMEOUT Set after the command when no response start bit received before the timeout. (CPSM moves from WAIT to IDLE) CKSTOP Set after the voltage switch (VSWITCHEN = 1) command response when the CRC is OK and the SDMMC_CK is stopped. (no impact on CPSM) VSWEND Set after the voltage switch (VSWITCH = 1) timeout of 5ms + 1ms. (no impact on CPSM) CPSMACT Command transfer in progress. (CPSM not in Idle state) The Command path error handling is shown in Table 439: Table 436. Command path error handling Error Timeout CPSM state Wait CRC status Receive Cause Card action Host action CPSM action No start bit in time Unknown Reset or cycle power card(1) Negative status Command ignored Resend command(1) Transmission error Move to Idle Move to Idle Command accepted Resend command (1) 1. When CMDTRANS is set, also a stop_transmission command shall be send to move the DPSM to Idle. Data path The data path subunit transfers data on the SDMMC_D[7:0] lines to and from cards. The data transmit path is clocked on the SDMMC_CK and sends data to the card.The data receive path is clocked on the sdmmc_rx_ck and receives data from the card. Figure 699 shows the data path block diagram. 2302/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 699. Data path 7RFRQWUROXQLW 'DWDSDWK 6WDWXV IODJ 5HJLVWHUV 'DWD WLPHU 2GGUHFHLYH VKLIWUHJLVWHU ),)2 (YHQUHFHLYH VKLIWUHJLVWHU &RQWURO ORJLF LQ 2GG&5& 6'00&B'> @ (YHQ&5& VGPPFBU[BFN 2GGWUDQVPLW VKLIWUHJLVWHU 0X[ 2GG&5& (YHQWUDQVPLW VKLIWUHJLVWHU RXW (YHQ&5& 6'00&B&. 06Y9 The card data bus width can be programmed in the clock control register bits WIDBUS. The supported data bus width modes are: • If the wide bus mode is not enabled, only one bit is transferred over SDMMC_D0. • If the 4-bit wide bus mode is enabled, data is transferred at four bits over SDMMC_D[3:0]. • If the 8-bit wide bus mode is enabled, data is transferred at eight bits over SDMMC_D[7:0]. Next to the data bus width the data sampling mode can be programmed in the clock control register bit DDR. The supported data sampling modes are: Note: • Single data rate signaling (SDR), data is clocked on the rising edge of the clock. • Double data rate signaling (DDR), data is clocked on the both edges of the clock. DDR mode is only supported in wide bus mode (4-bit wide and 8-bit wide). The data sampling mode only applies to the SDMMC_D[7:0] lines. (not applicable to the SDMMC_CMD line.) DocID029587 Rev 3 2303/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 In DDR mode, data is sampled on both edges of the SDMMC_CK according the following rules, see also Figure 700 and Figure 701: • On the rising edge of the clock Odd bytes are sampled. • On the falling edge of the clock Even bytes are sampled. • Data payload size is always a multiple of 2 Bytes. • Two CRC16 are computed per data line – Odd bits CRC16 clocked on the falling edge of the clock. – Even bits CRC16 clocked on the rising edge of the clock. • Start, End bits and idle conditions are full cycle. • CRC status / boot acknowledgment and Busy signaling are full cycle and are only sampled on the rising edge of the clock. In DDR mode the SDMMC_CK clock division shall be >= 2. Figure 700. DDR mode data packet clocking 6'00&B&. %\WH %\WH %\WHQ 6'00&B' VWDUW E E E E E E E E RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ E E E E FUF FUF FUF FUF RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ FUF FUF RGG HYHQ HQG 6'00&B' VWDUW E E E E E E E E RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ E E E E FUF FUF FUF FUF RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ FUF FUF RGG HYHQ HQG 6'00&B' VWDUW E E E E E E E E RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ E E E E FUF FUF FUF FUF RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ FUF FUF RGG HYHQ HQG 6'00&B' VWDUW E E E E E E E E RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ E E E E FUF FUF FUF FUF RGG HYHQ RGG HYHQ RGG HYHQ RGG HYHQ FUF FUF RGG HYHQ HQG %\WH % 0, the DPSM moves to the Idle state when the FIFO is empty and when IDMAEN = 0 reset with FIFORST, and sets the DABORT flag. If DATACOUNT is zero normal operation is continued, there will be no DABORT flag since the transfer has completed normally. – if the DTHOLD bit is set: - When DATACOUNT > 0, the DPSM moves to the Idle state when the receive FIFO is empty and when IDMAEN = 0 reset with FIFORST, and issues the DHOLD flag. When Holding the timeout is disabled. When an CPSM Abort signal is received during Holding, the transfer is Aborted. DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) - When DATACOUNT = 0, the transfer is completed normally and there will be no DHOLD flag. – • • When DPSM has been started with DTEN, after an error (DTIMEOUT) the DPSM moves to the Idle state when the FIFO is empty and when IDMAEN = 0 reset with FIFORST. ReadWait state: the data path ReadWait the bus. – The DPSM moves to the Wait_R state when the ReadWait stop bit (RWSTOP) is set, and start the receive timeout. – If the CPSM Abort signal is set, wait for the FIFO to be empty and when IDMAEN = 0 reset with FIFORST, then moves to the Idle state and sets the DABORT flag. Receive state: the data path receives serial data from a card. Pack the data in bytes and written it to the data FIFO. Depending on the transfer mode selected in the data control register (DTMODE), the data transfer mode can be either block or stream: – In block mode, when the data block size (DBLOCKSIZE) number of data bytes are received, the DPSM waits until it receives the CRC code. – In SDIO multibyte mode, when the data block size (DATALENGTH) number of data bytes are received, the DPSM waits until it receives the CRC code. a) If the received CRC code matches the internally generated CRC code, the DPSM moves to the - Wait_R state when RWSTART= 0 and start the receive timeout. - ReadWait state when RWSTART = 1 and DATACOUNT > zero, and generate the DBCKEND flag. b) If the received CRC code fails the internally generated CRC code any further data reception is prevented. - When not all data has been received (DATACOUNT > 0), the CRC fail status flag (DCRCFAIL) is set and the DPSM stays in the Receive state. - When all data has been received (DATACOUNT = 0), wait for the FIFO to be empty after which the CRC fail status flag (DCRCFAIL) is set and the DPSM moves to the Idle state. – In stream mode, the DPSM receives data while the data counter DATACOUNT > 0. When the counter is zero, the remaining data in the shift register is written to the data FIFO, and the DPSM moves to the Wait_R state. – When a FIFO overrun error occurs, the DPSM sets the FIFO overrun error flag (RXOVERR) and any further data reception is prevented. The DPSM stays in the Receive state. – When an CPSM_Abort signal is received:. - If the CPSM_Abort signal is received before the 2 last bits of the data with DATACOUNT = 0, the transfer is aborted. The remaining data in the shift register is written to the data FIFO, wait for the FIFO to be empty and when IDMAEN = 0 reset with FIFORST, then the DPSM moves to the Idle state and the DABORT flag is set. - If the CPSM_Abort signal is received during or after the 2 last bits of the transfer with DATACOUNT=0, the transfer is completed normally. The DPSM stays in the Receive state no DABORT flag is generated. – When DPSM has been started with DTEN, after an error (DCRCFAIL when DATACOUNT > 0, or RXOVERR) the DPSM moves to the Idle state when the FIFO is empty and when IDMAEN = 0 reset with FIFORST. DocID029587 Rev 3 2307/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) • Note: Wait_S state: the data path waits for data to be available from the FIFO. – If the data counter DATACOUNT > 0, waits until the data FIFO empty flag (TXFIFOE) is de-asserted and DTHOLD is not set, and moves to the Send state. – if the data counter (DATACOUNT) = 0 the DPSM moves to the Idle state and generate the DATAEND flag. – When DTHOLD is set and the DATACOUNT > 0 - When IDMA is enabled, the FIFO will be flushed, then the DPSM will move to the Idle state and issues the DHOLD flag. (The DBCKEND flag will also be set, and can be cleared at the same time as the DHOLD flag.) - When IDMA is disabled generate the DBCKEND flag. wait for the FIFO to be reset with FIFORST, then DPSM will move to the Idle state and issues the DHOLD flag. – When DTHOLD is set and DATACOUNT = 0 the transfer is completed normally. – When receiving the CPSM Abort signal - If the CPSM_Abort signal is received before the 2 last bits of the data with DATACOUNT = 0, the transfer is aborted, wait for the FIFO to be empty and when IDMAEN = 0 reset with FIFORST, then the DPSM moves to the Idle state and sets the DABORT flag. - If the CPSM_Abort signal is received during or after the 2 last bits of the transfer with DATACOUNT=0, normal operation is continued, there will be no DABORT flag since the transfer has completed normally. The DPSM remains in the Wait_S state for at least two clock periods to meet the NWR timing requirements, where NWR is the number of clock cycles between the reception of the card response and the start of the data transfer from the host. • 2308/3178 RM0433 Send state: the DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block, SDIO multibyte or stream: – In block mode, when the data block size (DBLOCKSIZE) number of data bytes are send, the DPSM sends an internally generated CRC code and End bit, and moves to the Busy state and start the transmit timeout. – In SDIO multibyte mode, when the data block size (DATALENGTH) number of data bytes are send, the DPSM sends an internally generated CRC code and End bit, and moves to the Busy state and start the transmit timeout. – In stream mode, the DPSM sends data to a card while the data counter DATACOUNT > 0. When the data counter reaches zero moves to the Busy state and start the transmit timeout. Before sending the last stream Byte according to DATACOUNT, the DPSM issues a trigger on the sendCMD signal. This signal is used by the CPSM to sent any pending command. (i.e. CMD12 Stop Transmission command) – If a FIFO underrun error occurs, the DPSM sets the FIFO under run error flag (TXUNDERR). The DPSM stays in the Send state. – When receiving the CPSM Abort signal - If the CPSM_Abort signal is received before the 2 last bits of the transfer with DATACOUNT=0, the transfer is aborted. The DPSM will sent a last data bit followed by an End bit. The FIFO will be disabled/flushed, and the DPSM moves to the Busy state to wait for not busy before setting the DABORT flag. - If the CPSM_Abort signal is received during or after the 2 last bits of the transfer DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) with DATACOUNT=0, the transfer is completed normally, there will be no DABORT flag. • Busy state: the DPSM waits for the CRC status token when expected, and wait for a not busy signal: – If a CRC status token is expected and indicate “non-erroneous transmission” or when there is no CRC expected: - it moves to the Wait_S state when SDMMC_D0 is not low (the card is not busy). - When the card is busy SDMMC_D0 is low it will remain in the Busy state. – If a CRC status token is expected and indicates “erroneous transmission”. - When not all data has been send (DATACOUNT > 0). The DPSM waits for not busy after which the CRC fail status flag (DCRCFAIL) is set. The FIFO will be disabled/flushed and the DPSM stays in the Busy state. - When all data has been send (DATACOUNT = 0). The DPSM waits for not busy after which the CRC fail status flag (DCRCFAIL) is set and the DPSM moves to the Idle state. – If a CRC status (Ncrc) timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag (DTIMEOUT) and stays in the Busy state. – If a busy timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag (DTIMEOUT) and stays in the Busy state. – When receiving the CPSM Abort signal in the Busy state: - If the CPSM_Abort signal is received before the 2 last bits of the CRC response with DATACOUNT > 0, the data transfer is aborted. The DPSM waits for not busy and the FIFO to be disabled/flushed before moving to the Idle state and the DABORT flag is set. - If the CPSM_Abort signal is received during or after the 2 last bits of the CRC response when DATACOUNT=0 or when no CRC is expected and DATACOUNT = 0 and there has been no DTIMEOUT error, the DPSM stays in the Busy state no DABORT flag is generated, since the transfer may completed normally. - If the CPSM_Abort signal is received when a DTIMEOUT error has occurred the DPSM waits for not busy and the FIFO to be disabled/flushed before moving to the Idle state and the DABORT flag is set. – When entering the Busy state due to an Abort in the Send state, the DPSM waits for not busy before moving to the Idle state and the DABORT flag is set. – When DPSM has been started with DTEN, after an error (DCRCFAIL when DATACOUNT > 0, or DTIMEOUT) the DPSM moves to the Idle state when the FIFO is reset. – When the DPSM has been started due to Busy on SDMMC_D0, waits for not busy after which the Busy end status flag (BUSYD0END) is set and the DPSM moves to the Idle state. DocID029587 Rev 3 2309/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 The data timer (DATATIME) is enabled when the DPSM is in the Wait_R or Busy state 2 cycles after the data block end bit, or data read command end bit, or R1b response, and generates the data timeout error (DTIMEOUT): • • When transmitting data, the timeout occurs – when a CRC status is expected and no start bit is received withing 8 SDMMC_CK cycles, the DTIMEOUT flag is set. – when the Busy state takes longer than the programmed timeout period., the DTIMEOUT flag is set. When receiving data, the timeout occurs – • when there is still data to be received DATACOUNT > 0 and no start bit is received before the programmed timeout period, the DTIMEOUT flag is set. After a R1b response, the timeout occurs – when the Busy state takes longer than the programmed timeout period., the DTIMEOUT flag is set. When DATATIME = 0, • In receive the start bit shall be present 2 cycles after the data block end bit or data read command end bit. • In transmit busy is timed out 2 cycles after the CRC token end bit or stream data end bit. • After a R1b response busy is timed out 2 cycles after the response end bit. Data can be transferred from the card to the host (transmit, send) or vice versa (receive). Data are transferred via the SDMMC_Dn data lines, they are stored in a FIFO. Table 437. Data token format Start bit Data(1) CRC16 End bit DTMODE Block data 0 (DBLOCKSIZE, DATALENGTH) yes 1 00 SDIO multibyte 0 (DATALENGTH) yes 1 01 MMC stream 0 (DATALENGTH) no 1 10 Description 1. The total amount of data to transfer is given by DATALENGTH. Where for Block data the amount of data in each block is given by DBLOCKSIZE. The data token format is selected with register bits DTMODE according. The data path implements the status flags and associated clear bits shown in Table 438: Table 438. Data path status flags and clear bits Flag Description TX DATAEND 2310/3178 Set at the end of the complete data transfer when the CRC is OK and busy has finished. (DATACOUNT = 0). (DPSM moves from WAIT_S to IDLE) RX Set at the end of the complete data transfer when the CRC is OK and all data has been BOOT read, (DATACOUNT = 0 and FIFO is empty). (DPSM moves from WAIT_R to IDLE) DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Table 438. Data path status flags and clear bits (continued) Flag Description TX DCRCFAIL Set at the end of the CRC when FAIL and busy has finished. (DPSM stay in BUSY when there is still data to send and wait for Abort) (DPSM moves from BUSY to IDLE when all data has been sent) or DPSM has been started with DTEN RX Set at the end of the CRC when FAIL and FIFO is empty. (DPSM stays in RECEIVE when there is still data to be received and wait for Abort) (DPSM moves from RECEIVE to IDLE BOOT when all data has been received or DPSM has been started with DTEN) ACKFAIL BOOT Set at the end of the BOOT ACK when FAIL. (DPSM stays in Wait_Ack and wait for Abort) CMD R1b DTIMEOUT TX Set after the command response no end of busy received before the timeout. (DPSM stays in BUSY and wait for Abort) Set when no CRC token start bit received within Ncrc, or no end of busy received before the timeout. (DPSM stays in BUSY and wait for Abort) (When DPSM has been started with DTEN move to IDLE) Note: The DCRCFAIL flag may also be set when CRC failed before the busy timeout. RX Set when no start bit received before the timeout. (DPSM stays in WAIT_R and wait for BOOT Abort) (When DPSM has been started with DTEN move to IDLE) ACKTIMEOUT BOOT TX DBCKEND Set when no start bit received before the timeout. (DPSM stays in Wait_Ack and wait for Abort) When DTHOLD = 1: Set at the end of data block transfer when the CRC is OK and busy has finished, when data transfer is not complete (DATACOUNT >0). (DPSM moves from WAIT_S to IDLE) RX When RWSTART = 1: Set at the end of data block transfer when the CRC is OK, when data transfer is not complete (DATACOUNT > 0). (DPSM moves from RECEIVE to BOOT READWAIT) TX When DTHOLD = 1: Set at the end of data block transfer when the CRC is OK and busy has finished, when data transfer is not complete (DATACOUNT >0). (DPSM moves from WAIT_S to IDLE) RX When DTHOLD = 1: Set at the end of data block transfer when the CRC is OK and all data has been read (FIFO is empty), when data transfer is not complete (DATACOUNT >0). (DPSM moves from WAIT_R to IDLE) DHOLD CMD R1b When Abort event has been sent by the CPSM and busy has finished. (DPSM moves from BUSY to IDLE) TX DABORT RX When Abort event has been sent by the CPSM before the 2 last bits of the transfer. (DPSM moves from Any state to IDLE) BOOT BUSYD0END DPSMACT CMD R1b Set after the command response when end of busy before the timeout. (DPSM moves from BUSY to IDLE) Data transfer in progress. (DPSM not in Idle state) The data path error handling is shown in Table 439: DocID029587 Rev 3 2311/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Table 439. Data path error handling Error DPSM state Cause No Ack in time Wait_Ack Card cycle power unknown Stop data reception Send stop transmission command unknown Stop boot procedure Busy too long (due to data transfer) unknown Stop data reception Send stop transmission command Busy too long (due to R1b) unknown Send reset command Timeout Busy CRC On CPSM_Abort move to Idle Stop data transmission Send stop transmission command On CPSM_Abort move to Idle transmission Send boot data error Stop boot procedure On CPSM_Abort move to Idle Ignore further data transmission wait for further data error Ack status Wait_Ack Stay in Wait_Ack (reset the SDMMC with the RCC.SDMMCxRST register bit) On CPSM_Abort move to Idle Negative status CRC status Busy DPSM action Stop data reception Send stop transmission command transmission Send further data error Receive Host action unknown No Start bit in time Wait_R Card action Overrun Receive FIFO full Send further data Stop data reception Send stop transmission command On CPSM_Abort move to Idle Underrun Send FIFO empty Stop data transmission Receive further data Send stop transmission command On CPSM_Abort move to Idle Data FIFO The data FIFO (first-in-first-out) subunit contains the transmit and receive data buffer. A single FIFO is used for either transmit or receive as selected by the DTDIR bit. The FIFO contain a 32-bit wide, 16-word deep data buffer and control logic. Because the data FIFO operates in the AHB clock domain (sdmmc_hclk), all signals from the subunits in the SDMMC clock domain (SDMMC_CK/sdmmc_rx_ck) are resynchronized. The FIFO can be in one of the following states: 2312/3178 – The transmit FIFO refers to the transmit logic and data buffer when sending data out to the card. (DTDIR = 0) – The receive FIFO refers to the receive logic and data buffer when receiving data in from the card. (DTDIR = 1) DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) The end of a correctly completed SDMMC data transfer from the FIFO is indicated by the DATAEND flags driven by the data path subunit. Any incorrect (aborted) SDMMC data transfer from the FIFO is indicated by one of the error flags (DCRCFAIL, DTIMEOUT, DABORT) driven by the data path subunit, or one of the FIFO error flags (TXUNDERR, RXOVERR) driven by the FIFO control. The data FIFO can be accessed in the following ways, see Table 440. Table 440. Data FIFO access Data FIFO access IDMAEN From FW via AHB slave interface 0 From IDMA via AHB master interface 1 Transmit FIFO: Data can be written to the transmit FIFO when the DPSM has been activated (DPSMACT = 1). When IDMAEN = 1 the FIFO is fully handled by the IDMA. When IDMAEN = 0 the FIFO is controlled by FW via the AHB slave interface. The transmit FIFO is accessible via sequential addresses. The transmit FIFO contains a data output register that holds the data word pointed to by the read pointer. When the data path subunit has loaded its shift register, it increments the read pointer and drives new data out. The transmit FIFO is handled in the following way: 1. Write the data length into DATALENGTH and the block length in DBLOCKSIZE. – 2. Set the SDMMC in transmit mode (DTDIR = 0). – 3. 4. For block data transfer (DTMODE = 0), DATALENGTH shall be an integer multiple of DBLOCKSIZE. Configures the FIFO in transmit mode. Enabled the data transfer – either by sending a Command from the CPSM with the CMDTRANS bit set – or by setting DTEN bit When (DPSMACT = 1) write data to the FIFO. – The DPSM will stay in the Wait_S state until FIFO is full (TXFIFOF = 1), or the number indicated by DATALENGTH. – The SDMMC start sending data as long as FIFO is not empty. 5. When the FIFO is half empty (TXFIFOHE flag), write data to the FIFO until FIFO is full (TXFIFOF = 1), or last data has been written. 6. When last data has been written wait for end of data (DATAEND flag) – SDMMC has completely sent all data and the DPSM is disabled (DPSMACT = 0). In case of a data transfer error or transfer hold when IDMAEN = 0, FW shall stop writing to the FIFO and flush and reset the FIFO with the FIFORST register bit. The transmit FIFO status flags are listed in Table 441. DocID029587 Rev 3 2313/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Table 441. Transmit FIFO status flags Flag Description TXFIFOF Set to high when all transmit FIFO words contain valid data. TXFIFOE Set to high when the transmit FIFO does not contain valid data. TXFIFOHE TXUNDERR Set to high when half or more transmit FIFO words are empty. Set to high when an underrun error occurs. This flag is cleared by writing to the SDMMC Clear register. Receive FIFO: Data can be read from the receive FIFO when the DPSM is activated (DPSMACT = 1). When IDMAEN = 1 the FIFO is fully handled by the IDMA. When IDMAEN = 0 the FIFO is controlled by FW via the AHB slave interface.When the data path subunit receives a word of data, it drives the data on the write databus. The write pointer is incremented after the write operation completes. On the read side, the contents of the FIFO word pointed to by the current value of the read pointer is driven onto the read databus. The receive FIFO is accessible via sequential addresses. The receive FIFO is handled in the following way: 1. Write the data length into DATALENGTH and the block length in DBLOCKSIZE. – 2. Set the SDMMC in receive mode (DTDIR = 1). – 3. 4. For block data transfer (DTMODE = 0), DATALENGTH shall be an integer multiple of DBLOCKSIZE. Configures the FIFO in receive mode. Enable the DPSM transfer – either by sending a command from the CPSM with the CMDTRANS bit set – or by setting DTEN bit. When (DPSMACT = 1) the FIFO is ready to receive data. – The DPSM will write the received data to the FIFO. 5. When the FIFO is half full (RXFIFOHF flag), read data from the FIFO until FIFO is empty (RXFIFOE = 1). 6. When last data has been received end of data (DATAEND flag), read data from the FIFO until FIFO is empty (RXFIFOE = 1). – SDMMC has completely received all data and the DPSM is disabled (DPSMACT = 0). In case of a data transfer hold when IDMAEN = 0, FW shall read the remaining data until the FIFO is empty and reset the FIFO with the FIFORST register bit. This will cause the DPSM to go to the Idle state (DPSMACT = 0). In case of a data transfer error when IDMAEN = 0, FW shall stop reading the FIFO and flush and reset the FIFO with the FIFORST register bit. This will cause the DPSM to go to the Idle state (DPSMACT = 0). The receive FIFO status flags are listed in Table 442. 2314/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Table 442. Receive FIFO status flags Flag Description RXFIFOF Set to high when all receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. RXFIFOHF Set to high when half or more receive FIFO words contain valid data. RXOVERR Set to high when an overrun error occurs. This flag is cleared by writing to the SDMMC Clear register. CLKMUX unit The CLKMUX selects the source for clock sdmmc_rx_ck to be used with the received data and command response. The receive data clock source can be selected by the clock control register bit SELCLKRX, between: • sdmmc_io_in_ck bus master main feedback clock. • SDMMC_CKIN external bus feedback clock. • sdmmc_fb_ck bus tuned feedback clock. The sdmmc_io_in_ck is selected when there is no external driver, with DS and HS. The SDMMC_CKIN is selected when there is an external driver with SDR12, SDR25, SDR50 and DDR50. The sdmmc_fb_ck clock input must be selected when the DLYB block on the device is used with SDR104 and optionally with SDR50 and DDR50 modes. Figure 703. CLKMUX unit &/.08; 5HJLVWHUV VGPPFBLRBLQBFN 08; VGPPFBU[BFON 6'00&B&.,1 VGPPFBIEBFN 06Y 9 The sdmmc_rx_ck source shall be changed when the CPSM and DPSM are in the Idle state. 55.4.5 SDMMC AHB slave interface The AHB slave interface generates the interrupt requests, and accesses the SDMMC adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt logic. SDMMC FIFO The FIFO access is restricted to word access: • In transmit FIFO mode – Data are written to the FIFO in words (32-bits) until all data according DATALENGTH has been transfered. When the DATALENGTH is not an integer DocID029587 Rev 3 2315/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 multiple of 4, the last remaining data (1, 2 or 3 bytes) are written with a word transfer. • In receive FIFO mode – Data are read from the FIFO in words (32-bits) until all data according DATALENGTH has been transfered. When the DATALENGTH is not an integer multiple of 4, the last remaining data (1, 2 or 3 bytes) are read with a word transfer padded with 0 value bytes. When accessing the FIFO with half word or byte accesses an AHB bus fault is generated. SDMMC interrupts The interrupt logic generates an interrupt request signal that is asserted when at least one of the unmasked status flags is active. A mask register is provided to allow selection of the conditions that will generate an interrupt. A status flag generates the interrupt request if a corresponding mask flag is set. Some status flags require an implicit clear in the clear register. 55.4.6 SDMMC AHB master interface The AHB master interface is used to transfer the data between a memory and the FIFO using the SDMMC IDMA. SDMMC IDMA Direct memory access (DMA) is used to provide high-speed transfer between the SDMMC FIFO and the memory. The AHB master optimizes the bandwidth of the system bus. The SDMMC internal DMA (IDMA) provides one channel to be used either for transmit or receive. The IDMA is enabled by the IDMAEN bit and supports burst transfers of 8 beats. • In transmit burst transfer mode: – • Data are fetched in burst from memory whenever the FIFO is empty for the number of burst transfers, until all data according DATALENGTH has been transfered. When the DATALENGTH is not an integer multiple of the burst size the remaining, smaller then burst size data is transfered using single transfer mode. When the DATALENGTH is not an integer multiple of 4, the last remaining data (1, 2 or 3 bytes) are fetched with a word transfer. In receive burst transfer mode: – Data are stored in burst in to memory whenever the FIFO contains the number of burst transfers, until all data according DATALENGTH has been transfered. When the DATALENGTH is not an integer multiple of the burst transfer the remaining, smaller then burst size data, is transfered using single transfer mode. When the DATALENGTH is not an integer multiple of 4, the last remaining data (1, 2 or 3 bytes) are stored with halfword and or byte transfers. In addition the IDMA provides two channel configurations selected by bit IDMABMODE: • single buffered channel • double buffered channel In single buffer configuration the data at the memory side is accessed in a linear matter starting from the base address IDMABASE0. When the IDMA has finished transferring all data the and the DPSM has completed the transfer the DATAEND flag is set. 2316/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) In double buffer configuration the data at the memory side is subsequently accessed from 2 buffers, one located from base address IDMABASE0 and a second located from base address IDMABASE1. This allows firmware to process one memory buffer while the IDMA is accessing the other memory buffer. The size of the memory buffers is defined by IDMABSIZE. The buffer size shall be an integer multiple of the burst size. It is possible to update the base address of the buffers on-the-fly when the channel is enabled, the following rule apply: • When IDMABACT bit is ‘0’ the IDMA hardware uses the IDMABASE0 to access memory. When attempting to write to this register by Firmware the write is discarded, IDMABASE0 data will not be changed. Firmware is allowed to write IDMABASE1. • When IDMABACT bit is ‘1’ the IDMA hardware uses the IDMABASE1 to access memory. When attempting to write to this register by Firmware the write is discarded, IDMABASE1 data will not be changed. Firmware is allowed to write IDMABASE0. When the IDMA has finished transferring the data of one buffer the buffer transfer complete flag (IDMABTC) is set and the IDMABACT bit toggles where after the IDMA continues transferring data from the other buffer. When the IDMA has finished transferring all data and the DPSM has completed the transfer the DATAEND flag is set. The IDMABASEn address shall be word aligned. Error management An IDMA transfer error can occur when reading or writing a reserved address space. On a IDMA transfer error subsequent IDMA transfers are disabled and an IDMATE flag is set. The behavior of the IDMATE flag depend on when the IDMA transfer error occurs during the SDMMC transfer: • • • An IDMA transfer error is detected before any SDMMC transfer error (TXUNDERR, RXOVERR, DCRCFAIL, or DTIMEOUT): – The IDMATE flag is set at the same time as the SDMMC transfer error flag. – The TXUNDERR, RXOVERR, DCRCFAIL, or DTIMEOUT interrupt is generated. An IDMA transfer error is detected during a STOP_TRANSNMISSION command: – The IDMATE flag is set at the same time as the DABORT flag. – The DABORT interrupt is generated. An IDMA transfer error is detected at the end of the SDMMC transfer (HOLD, or DATAEND). – The IDMATE flag is set at the end of the SDMMC transfer. – A SDMMC transfer end interrupt is generated and a HOLD or DATAEND flag is set. The IDMATE will be generated on an other SDMMC transfer interrupt (TXUNDERR. RXOVERR, DCRCFAIL, DTIMEOUT, DABORT, HOLD, or DATAEND). 55.4.7 MDMA request generation The internal trigger line from the SDMMC allows passing direct request to MDMA controller to enable successive transfers from/to different internal RAM addresses without CPU use. When a data transfer from/to the card completes successfully, the DATAEND flag of the status register is set. The event is signaled to an MDMA request input through the sdmmc_dataend_trg output. It can trigger the clearance of the DATAEND and CMDREND DocID029587 Rev 3 2317/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 flags and, eventually, a new transfer start, through MDMA direct access to the SDMMC control and configuration registers, thus without CPU intervention. The action to program in the MDMA according to the SDMMC requests is provided in the following table: Table 443. SDMMC connections to MDMA Trigger signal Event signaled Event occurrence condition MDMA transfer configuration MDMA action sdmmc_ dataend_trg End of successful data transfer DATAEND = 1 single Set DATAENDC 55.4.8 AHB and SDMMC_CK clock relation The AHB shall at least have 3x more bandwidth than the SDMMC bus bandwidth i.e. for SDR50 4-bit mode (50Mbyte/s) the minimum sdmmc_hclk frequency is 37.5MHz (150Mbyte/s). Table 444. AHB and SDMMC_CK clock frequency relation SDMMC bus mode SDMMC bus width Maximum SDMMC_CK [MHz] Minimum AHB clock [MHz] MMC DS 8 26 19.5 MMC HS 8 52 39 MMC DDR52 8 52 78 MMC HS200 8 200 150 SD DS / SDR12 4 25 9.4 SD HS / SDR25 4 50 18.8 SD DDR50 4 50 37.5 SD SDR50 4 100 37.5 SD SDR104 4 208 78 55.5 Card functional description 55.5.1 SD I/O mode The following features are SDMMC specific operations: 2318/3178 • SDIO interrupts • SDIO suspend/resume operation (write and read suspend) • SDIO read wait operation by stopping the clock • SDIO read wait operation by SDMMC_D2 signaling DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) SDIOEN RWMOD RWSTOP RWSTART DTDIR Table 445. SDIO special operation control Interrupt detection 1 X X X X Suspend/Resume operation X X X X X ReadWait SDMMC_CK clock stop (START) X 1 0 1 1 ReadWait SDMMC_CK clock stop (STOP) X 1 1 1 1 ReadWait SDMMC_D2 signaling (START) X 0 0 1 1 ReadWait SDMMC_D2 signaling (STOP) X 0 1 1 1 Operation mode SD I/O interrupts To allow the SD I/O card to interrupt the host, an interrupt function is available on pin 8 (shared with SDMMC_D1 in 4-bit mode) on the SD interface. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt is level-sensitive, which means that the interrupt line must be held active (low) until it is either recognized and acted upon by the host or de-asserted due to the end of the interrupt period. After the host has serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card internal registers. The interrupt output of all SD I/O cards is active low and the application must provide external pull-up resistors on all data lines (SDMMC_D[3:0]). In SD 1-bit mode pin 8 is dedicated to the interrupt function (IRQ), and there are no timing constraints on interrupts. In SD 4-bit mode the host samples the level of pin 8 (SDMMC_D1/IRQ) into the interrupt detector only during the interrupt period. At all other times, the host interrupt ignores this value. The interrupt period begins when interrupts are enabled at the card and SDIOEN bit is set see register settings in Table 445. In 4-bit mode the card can generate a synchronous or asynchronous interrupt as indicated by the card CCCR register SAI and EAI bits. • Synchronous interrupt, require the SDMMC_CK to be active. • Asynchronous interrupt, can be generated when the SDMMC_CK is stopped, 4 cycles after the start of the card interrupt period following the last data block. DocID029587 Rev 3 2319/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Figure 704. Asynchronous interrupt generation 6'00&B&. 'DWDEORFN 6'00&B&0' 6 &RPPDQG ( 6'00&B' 6 /DVWGDWD ( 6 &5& ( 6'00&B' 6 /DVWGDWD ( 6 &5& ( 6'00&B' 6'00&B' 6 /DVWGDWD ( 6 &5& ( 6\QFKURQRXV ,17 'DWD &. $V\QFKURQRXV,17 'DWD 1($, &. ,QWHUUXSWSHULRG 06Y 9 The timing of the interrupt period is depended on the bus speed mode: In DS, HS, SDR12, and SDR25 mode, selected by register bit BUSSPEED, the interrupt period is synchronous to the SD clock. Note: • The interrupt period ends at the next clock from the End bit of a command that transfers data block(s) (Command sent with the CMDTRANS bit is set), or when the DTEN bit is set. • The interrupt period resumes 2 SDMMC_CK after the completion of the data block. • At the data block gap the interrupt period is limited to 2 SDMMC_CK cycles. DTEN shall not be used to start data transfer with SD and eMMC cards. Figure 705. Synchronous interrupt period data read 6'00&B&. 6'00&B&0' 6 &RPPDQGGDWD ( 5 6'00&B' 6 'DWD ( 6 'DWD ( 6'00&B' 6 'DWD ( 6 'DWD ( 6'00&B' 6'00&B' 6 'DWD ( 6 'DWD ( ,QWHUUXSWSHULRG ,54 'DWD ,54 &. 'DWD &. 06Y 9 2320/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 706. Synchronous interrupt period data write 6'00&B&. 6'00&B&0' 6 &RPPDQGGDWD ( : 6 563 ( 6'00&B' 6 'DWD ( 6'00&B' 6 'DWD 6'00&B' 6'00&B' 6 'DWD ,QWHUUXSWSHULRG ,54 6 &5&VWDWXV ( 6 'DWD ( ( 6 'DWD ( ( 6 'DWD ( ,54 'DWD &. 'DWD &. 06Y 9 In SDR50, SDR104, and DDR50, selected by register bit BUSSPEED, due to propagation delay from the card to host, the interrupt period is asynchronous. Note: • The card interrupt period ends after 0 to 2 SDMMC_CK cycles after the End bit of a command that transfers data block(s) (Command sent with the CMDTRANS bit is set), or when the DTEN bit is set. At the host the interrupt period ends after the End bit of a command that transfers data block(s). A card interrupt issued in the 1 to 2 cycles after the command End bit are not detected by the host during this interrupt period. • The card interrupt period resumes 2 to 4 SDMMC_CK after the completion of the last data block. The host will resume the interrupt period always 2 cycles after the last data block. • There is NO interrupt period at the data block gap. DTEN shall not be used to start data transfer with SD and eMMC cards. DocID029587 Rev 3 2321/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Figure 707. Asynchronous interrupt period data read 6'00&B&. VGPPFBIEBFN 6'00&B&0' 6 &RPPDQGGDWD ( 5 W23 6'00&B' 6 'DWD ( 6'00&B' 6 'DWD ( 6 'DWD ( 6'00&B' 6'00&B' W23 ,QWHUUXSWSHULRG ,54 ,54 'DWD &.±&. &. 06Y 9 Figure 708. Asynchronous interrupt period data write 6'00&B&. VGPPFBIEBFN 6'00&B&0' 6 &RPPDQGGDWD ( : 6 563 ( W23 W23 6'00&B' 6 'DWD ( 6'00&B' 6 'DWD ( 6 'DWD ( 6'00&B' 6'00&B' ,QWHUUXSWSHULRG W23 6 &5&VWDWXV ( W23 ,54 ,54 'DWD &.&. &.±&. 06Y 9 When transferring Open-ended multiple block data and using DTMODE “block data transfer ending with STOP_TRANSMISSION command”, the SDMMC will mask the interrupt period after the last data block until the end of the CMD12 STOP_TRANSMISSION command. The interrupt period is applicable for both memory and I/O operations. In 4-bit mode interrupts can be differentiated from other signaling according Table 446. 2322/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Table 446. 4-bit mode Start, interrupt, and CRC-status Signaling detection SDMMC data line Start Interrupt CRC-status SDMMC_D0 0 1 or CRC-status 0 SDMMC_D1 0 0 X SDMMC_D2 0 1 or ReadWait X SDMMC_D3 0 1 X SD I/O suspend and resume This function is NOT supported in SDIO version 4.00 or later. Within a multifunction SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and memory) that share access to the MMC/SD bus. To share access to the host among multiple devices, SD I/O and combo cards optionally implement the concept of suspend/resume. When a card supports suspend/resume, the host can temporarily halt (suspend) a data transfer operation to one function or memory to free the bus for a higher-priority transfer to a different function or memory. After this higher-priority transfer is complete, the original transfer is restarted (resume) where it left off. To perform the suspend/resume operation on the bus, the host performs the following steps: 1. Determines the function currently using the SDMMC_D[3:0] line(s) 2. Requests the lower-priority or slower transaction to suspend 3. Waits for the transaction suspension to complete 4. Begins the higher-priority transaction 5. Waits for the completion of the higher priority transaction 6. Restores the suspended transaction The card receiving a suspend command will respond with its current bus status. Only when the bus has been suspended by the card the bus status will indicated suspension completed. There are different suspend cases conditions: • Suspend request accepted prior to the start of data transfer. • Suspend request not accepted, (due to data being transfered at the same time), the host keeps checking the request until it is accepted. (data transfer has suspended) • Suspend request during write busy. • Suspend request with write multiple. • Suspend request during ReadWait. For the host to know if the bus has been released it shall check the status of the suspend request, suspension completed. When the bus status of the suspend request response indicates suspension completed, the card has released the bus. At this time the state of the suspended operation shall be saved where after an other operation can start. The suspend command shall be sent with the CMDSUSPEND bit set. This allows to start the interrupt period after the suspend command response when the bus is suspended (response bit BS = 0). DocID029587 Rev 3 2323/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 The hardware does not save the number of remaining data to be transfered when resuming the suspended operation. It is up to firmware to determine the data that has been transferred and resume with the correct remaining number of data bytes. While receiving data from the card, the SDMMC can suspend the read operation after the read data block end (DPSM in Wait_R). After receiving the suspend acknowledgment response from the card the following steps shall be taken by firmware: 1. The normal receive process shall be stopped by setting DTHOLD bit. a) 2. The confirmation that all data has been read from the FIFO, and that the suspend is completed is indicated by the DHOLD flag. a) Note: The remaining number of data bytes in the FIFO shall be read until the receive FIFO is empty (RXFIFOE flag is set), and when IDMAEN = 0 the FIFO shall be reset with FIFORST. The remaining number of data bytes (multiple of data blocks) still to be read when resuming the operation shall be determined from the remaining number of bytes indicated by the DATACOUNT. When a DTIMEOUT flag occurs during the suspend procedure, this shall be ignored. To resume receiving data from the card, the following steps shall be taken by firmware: 1. The remaining number of data bytes (multiple of data blocks) shall be programmed in DATALENGTH. 2. The DPSM shall be configured to receive data in the DTDIR bit. 3. The resume command shall be sent from the CPSM, with the CMDTRANS bit set and the CMDSUSPEND bit set, which will end the interrupt period when data transfer is resumed (response bit DF = 1) and enabled the DPSM, after which the card will resume sending data. While sending data to the card, the SDMMC can suspend the write operation after the write data block CRC status end (DPSM in Busy). Before sending the suspend command to the card the following steps shall be taken by firmware: 1. Enable DHOLD flag (and DBCKEND flag when IDMAEN = 0) 2. The DPSM shall be prevented from start sending a new data block by setting DTHOLD. 3. When IDMAEN = 0: When receiving the DBCKEND flag the data transfer is stopped. Firmware can stop filling the FIFO, after which the FIFO shall be reset with FIFORST. Any bytes still in the FIFO need to be rewritten when resuming the operation. 4. When receiving the DHOLD flag the data transfer is stopped. The remaining number of data bytes still to be written when resuming shall be determined from the remaining number of bytes indicated by the DATACOUNT. 5. To suspend the card the suspend command shall be sent by the CPSM with the CMDSUSPEND bit set. This allows to start the interrupt period after the suspend command response when the bus is suspended (response bit BS = 0). To resume sending data to the card, the following steps shall be taken by firmware: 2324/3178 1. The remaining number of data bytes shall be programmed in DATALENGTH. 2. The DPSM shall be configured for transmission with DTDIR set and enabled by having the CPSM send the resume command with the CMDTRANS bit set and the CMDSUSPEND bit set. This will end the interrupt period and start the data transfer. DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) The DPSM will either go to the Wait_S state when SDMMC_D0 does not signal busy, or will go to the Busy state when busy is signaled. 3. When IDMAEN = 1: The DMA needs to be reprogrammed for the remaining bytes to be transfered. 4. When IDMAEN = 0: Firmware shall start filling the FIFO with the remaining data. SD I/O ReadWait There are 2 methods to pause the data transfer during the Block gap: 1. Stopping the SDMMC_CK. 2. Using ReadWait signaling on SDMMC_D2. The SDMMC can perform a ReadWait with register settings according Table 445. Depending the SDMMC operation mode (DS, HS, SDR12, SDR25) or (SDR50, SDR104, DDR) each method has a different characteristic. The timing for pause read operation by stopping the SDMMC_CK for DS, HS, SDR12, and SDR25, the SDMMC_CK may be stopped 2 SDMMC_CK cycles after the End bit. When ready the host resumes by restarting clock, see Figure 709. Figure 709. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25 &. &. &. 6'00&B&. 6'00&B'Q 5HDGGDWD ,QWHUUXSWSHULRG + 5HDGGDWD 06Y 9 The timing for pause read operation by stopping the SDMMC_CK for SDR50, SDR104, and DDR50, the SDMMC_CK may be stopped minimum 2 SDMMC_CK cycles and maximum 5 SDMMC_CK cycles, after the End bit. When ready the host resumes by restarting clock, see Figure 710. (In DDR50 mode the SDMMC_CK shall only be stopped after the falling edge, when the clock line is low.) Figure 710. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 1$&&.PLQ W23 W23 6'00&B&. 6'00&B'Q 5HDG GDWD (QG 6WDUW 5HDG GDWD &.PLQ &.PD[ 06Y 9 DocID029587 Rev 3 2325/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 In ReadWait SDMMC_CK clock stopping, when RWSTART is set, the DSPM stops the clock after the End bit of the current received data block CRC. The clock start again after writing 1 to the RWSTOP bit, where after the DPSM waits for a Start bit from the card. As SDMMC_CK is stopped, no command can be issued to the card. During a ReadWait interval, the SDMMC can still detect SDIO interrupts on SDMMC_D1. The optional ReadWait signaling on SDMMC_D2 (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation allows the host to signal a card that is reading multiple registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the host to send commands to any function within the SD I/O device. To determine when a card supports the ReadWait protocol, the host must test capability bits in the internal card registers. The timing for ReadWait with a SDMMC_CK less then 50MHz (DS, HS, SDR12, SDR25) is based on the interrupt period generated by the card on SDMMC_D1. The host by asserting SDMMC_D2 low during the interrupt period requests the card to enter ReadWait. To exit ReadWait the host shall raise SDMMC_D2 high during one SDMMC_CK cycles before making it Hi-Z, see Figure 711. Figure 711. ReadWait with SDMMC_CK < 50 MHz 6'00&B&. &. 6'00&B' &. 5HDGGDWD 5HDGGDWD &. 6'00&B' 5HDGGDWD 6'00&B' 6'00&B' 5HDGGDWD 5HDGZDLW ,QWSHULRG 6'00&B&0' 5HDGGDWD 5HDGGDWD &0' 06Y 9 For SDR50, SDR104 with a SDMMC_CK more than 50MHz, and DDR50, the card will treat the ReadWait request on SDMMC_D2 as an asynchronous event. The host by asserting SDMMC_D2 low after minimum 2 SDMMC_CK cycles and maximum 5 SDMMC_CK cycles, request the card to enter ReadWait. To exit ReadWait the host shall raise SDMMC_D2 high during one SDMMC_CK cycles before making it Hi-Z. The host shall raise SDMMC_D2 on the SDMMC_CK clock (see Figure 712). 2326/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 712. ReadWait with SDMMC_CK > 50 MHz 1$&&.PLQ W23 W23 6'00&B&. 6'00&B' 5HDGGDWD (QG 6'00&B' 6'00&B' 6'00&B' 5HDGGDWD (QG 5HDGZDLW 5HDGGDWD 6WDUW 5HDGGDWD 6WDUW &.PLQ &.PD[ 06Y 9 In ReadWait SDMMC_D2 signaling, when RWSTART is set, the DPSM drives SDMMC_D2 after the End bit of the current received data block CRC. The ReadWait signaling on SDMMC_D2 will be removed when writing 1 to the RWSTOP bit. The DPSM remains in ReadWait state for two more SDMMC_CK clock cycles to drive SDMMC_D2 to 1 for one clock cycle (in accordance with SDIO specification), where after the DPSM waits for a Start bit from the card. During the ReadWait signaling on SDMMC_D2 commands can be issued to the card. During the ReadWait interval, the SDMMC can detect SDIO interrupts on SDMMC_D1. 55.5.2 CMD12 send timing CMD12 is used to stop/abort the data transfer, the card data transmission is terminated two clock cycles after the End bit of the Stop Transmission command. Table 447. CMD12 use cases Data operation Stop Transmission command CMD12 Description MMC Stream write The data transfer is stopped/aborted by sending the Stop Transmission command. MMC open ended multiple block write The data transfer is stopped/aborted by sending the Stop Transmission command. If the card detects an error, the host must abort the operation by sending the Stop Transmission command. MMC block write with predefined block count The Stop Transmission command is not required at the end of this type of multiple block write. (sending the Stop Transmission command after the card has received the last block is regarded as an illegal command.) If the card detects an error, the host must abort the operation by sending the Stop Transmission command. MMC Stream read The data transfer is stopped/aborted by sending the Stop Transmission command. DocID029587 Rev 3 2327/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Table 447. CMD12 use cases Data operation Stop Transmission command CMD12 Description MMC open ended multiple block read The data transfer is stopped/aborted by sending the Stop Transmission command. If the card detects an error, the host must abort the operation by sending the Stop Transmission command. MMC block read with predefined block count The Stop Transmission command is not required at the end of this type of multiple block read. (sending the Stop Transmission command after the card has transmitted the last block is regarded as an illegal command.) Transaction can be aborted by sending the Stop Transmission command. If the card detects an error, the host must abort the operation by sending the Stop Transmission command. All data write and read commands can be aborted any time by a Stop Transmission command CMD12. The following data abort procedure applies during an ongoing data transfer: 1. Load CMD12 Stop Transmission command in registers and set the CMDSTOP bit. a) 2. 3. 4. 5. This causes the CPSM to generate the Abort signal when the command is sent to the DPSM. Configure the CPSM to send a command immediately (clear WAITPEND bit). a) The card, when sending data, will stop data transfer 2 cycles after the Stop Transmission command End bit. The card when no data is being sent, will not start sending any new data. b) The host, when sending data, will send one last data bit followed by an End bit after the Stop Transmission command End bit. The host when not sending data, will not start sending any new data. When IDMAEN = 0, the FIFO need to be reset with FIFORST. a) When writing data to the card. On the CMDREND flag FW shall stop writing data to the FIFO. Subsequently the FIFO shall be reset with FIFORST, this will flush the FIFO. b) When reading data from the card. On the CMDREND flag FW shall read the remaining data from the FIFO. Subsequently the FIFO shall be reset with FIFORST. When IDMAEN = 1, hardware will take care of the FIFO. a) When writing data to the card. On the Abort signal hardware will stop the IDMA and subsequently the FIFO will be flushed. b) When reading data from the card. On the Abort signal hardware will instruct the IDMA to transfer the remaining data from the FIFO to RAM. When the FIFO is empty/reset the DABORT flag will be generated. Stream operation and CMD12 To stop the stream transfer after the last byte to be transfered, the CMD12 End bit timing shall be sent aligned with the data stream end of last byte. The following write stream data procedure applies: 2328/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 1. Initialize the stream data in the DPSM, DTMODE = MCC stream data transfer. 2. Send the WRITE_DATA_STREAM command from the CPSM with CMDTRANS = 1. 3. Preload CMD12 in command registers, with the CMDSTOP bit shall set. 4. Configure the CPSM to send a command only after a wait pending (WAITPEND = 1) end of last data (according DATALENGTH). 5. Enabling the CPSM to send the STOP_TRANSMISSION command, the stream data End bit and command End bit will be aligned. 6. a) When DATALENGTH > 5 bytes, Command CMD12 will be waited in the CPSM to be aligned with the data transfer End bit. b) When DATALENGHT < 5 bytes, Command CMD12 will be started before and the DPSM will remain in the Wait_S state to align the data transfer end with the CMD12 End bit. The write stream data can be aborted any time by clearing the WAITPEND bit. This will cause the Preloaded CMD12 to be sent immediately and stop the write data stream. Figure 713. CMD12 stream timing 6'00&B&. &0' 6'00&B&0' 6'00&B' ( 6WUHDPGDWDODVWE\WH ( 167 06Y 9 To stop the read stream transfer after the last byte, the CMD12 End bit timing shall occur after the last data stream byte. The following read stream data procedure applies: 1. Wait for all data to be received by the DPSM (DATAEND flag). a) 2. Send CMD12 by the CPSM. a) Note: The DPSM will not receive more data than indicated by DATALENGTH, even if the card is sending more data. CMD12 will stop the card sending data. The SDMMC will not receive any more data from the card when DATACOUNT = 0, even when the card continues sending data. Block operation and CMD12 To stop block transfer at the end of the data, the CMD12 End bit shall be sent after the last block End bit. When writing data to the card the CMD12 End bit shall be sent after the write data block CRC token End bit. This requires the CMD12 sending to be tied to the data block transmission timing. To stop an Open-ended Multiple block write, the following procedure applies: DocID029587 Rev 3 2329/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 1. Before starting the data transfer, set DTMODE to “block data transfer ending with STOP_TRANSMISSION command”. 2. Wait for all data to be sent by the DPSM and the CRC token to be received, (DATAEND flag). a) 3. The DPSM will not send more data than indicated by DATALENGTH. Send CMD12 by the CPSM. a) CMD12 will set the card to Idle mode. When reading data from the card the CMD12 End bit shall be sent earliest at the same time as the card read data block last data bit. This requires the CMD12 sending to be tied to the data block reception timing.The following stop Open-ended Multiple block read data block procedure applies: 1. Before starting the data transfer, set DTMODE to “block data transfer ending with STOP_TRANSMISSION command”. 2. Wait for all data to be received by the DPSM (DATAEND flag). a) 3. The DPSM will not receive more data than indicated by DATALENGTH, even if the card is sending more data. Send CMD12 with CMDSTOP bit set by the CPSM. a) CMD12 will stop the Card sending more data and set the card to Idle mode. Any ongoing block transfer will be aborted by the Card. Note: The SDMMC will not receive any more data from the card when DATACOUNT = 0, even when the card continues sending data. 55.5.3 Sleep (CMD5) The MMC card may be switched between a Sleep state and a Standby state by CMD5. In the Sleep state the power consumption of the card is minimized and the Vcc power supply may be switched off. The CMD5 (SLEEP) is used to initiate the state transition from Standby state to Sleep state. The card indicates Busy, pulling down SDMMC_D0, during the transition phase. The Sleep state is reached when the card stops pulling down the SDMMC_DO line. To set the card into Sleep state the following procedure applies: 1. Enable interrupt on BUSYD0END. 2. Send CMD5 (SLEEP). 3. On BUSYD0END interrupt, card is in Sleep state 4. Vcc power supply is allowed to be switched off The CMD5 (AWAKE) is used to initiate the state transition from Sleep state to Standby state. The card indicates Busy, pulling down SDMMC_D0, during the transition phase. The Standby state is reached when the card stops pulling down the SDMMC_DO line. To set the card into Sleep state the following procedure applies: 1. Switch on Vcc power supply and wait unit minimum operating level is reached. 2. Enable interrupt on BUSYD0END. 3. Send CMD5 (AWAKE). 4. On BUSYD0END interrupt card is in Standby state. The Vcc power supply is allowed to be switched off only after the Sleep state has been reached. The Vcc supply shall be reinstalled before CMD5 (AWAKE) is sent. 2330/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 714. CMD5 Sleep Awake procedure 9&& 6'00&B&0' 6'00&B' 2II &0' VOHHS &0' DZDNH 5(63 5(63 %86< %86< 7UDQVLVWLRQSKDVH 7UDQVLVWLRQSKDVH %86<'(1' 6WDQGE\VWDWH 6OHHSVWDWH 6WDQGE\VWDWH 06Y 9 55.5.4 Interrupt mode (Wait-IRQ) The host and card enter and exit interrupt mode (Wait-IRQ) simultaneously. In interrupt mode there is no data transfer. The only message allowed is an interrupt service request response from the card or the host. For the interrupt mode to work correctly the SDMMC_CK frequency shall be set in accordance with the achievable SDMMC_CMD data rate in Open Drain mode, which depend on the capacitive load and pull-up resistor. The CLKDIV shall be set >1, and the SETCLKRX shall select either the sdmmc_io_in_ck or SDMMC_CLKin source. The host must ensure that the card is in Standby state before issuing the CMD40 (GO_IRQ_STATE). While waiting for an interrupt response the SDMMC_CK clock signal must be kept active. A card in interrupt mode (IRQ state): • is waiting for an internal card interrupt event. Once the event occurs, the card starts to send the interrupt service request response. The response is sent in open-drain mode. • while waiting for the internal card interrupt event, the card also monitors the SDMMC_CMD line for a Start bit. Upon detection of a Start bit the card will abort the interrupt mode and switch to Standby state. The host in interrupt mode (CPSM Wait state waiting for interrupt): • is waiting for a card interrupt service request response (Start bit). • while waiting for a card interrupt service request response the host may abort the interrupt mode (by clearing the WAITINT register bit), which causes the host to send a interrupt service request response R5 with RCA = 0x0000 in open-drain mode. When sending the interrupt service request response, the sender bit-wise monitors the SDMMC_CMD bit stream. The sender whose interrupt service request response bit does not correspond to the bit on the SDMMC_CMD line stops sending. In the case of multiple senders only one will successfully send its full interrupt service request response. i.e. If the host sends simultaneously, it will lose sending after the transmission bit. To handle the interrupt mode, the following procedure applies: DocID029587 Rev 3 2331/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 1. Set the SDMMC_CK frequency in accordance with the achievable SDMMC_CMD data rate in Open-drain mode, CLKDIV shall be set >1, and SETCLKRX shall select the sdmmc_io_in_ck. 2. Load CMD40 (GO_IRQ_STATE) in the command registers. 3. Enable wait for interrupt by setting WAITINT register bit. 4. Configure the CPSM to send a command immediately. a) 5. This will cause the CMD40 to be sent and the CPSM to be halted in the Wait state, waiting for a interrupt service request response. To exit the wait for interrupt state (CPSM Wait state): a) Upon the detection of an interrupt service request response Start bit the CPSM moves to the Receive state where the response is received. The complete reception of the response is indicated by the CMDREND or the command CRC error flags. b) To abort the interrupt mode the host clears the WAITINT register bit, which will cause the host to send an interrupt service request response by its self. Which will move the CPSM to the Receive state.The complete reception of the response is indicated by the CMDREND or the command CRC error flags. Note: On a simultaneous send interrupt service request response Start bit collision the host will lose the bus access after the Transmission bit. 55.5.5 Boot operation In boot operation mode the host can read boot data from the card by either one of the 2 boot operation functions: 1. Normal boot. (keeping CMD line low) 2. Alternative boot (sending CMD0 with argument 0xFFFFFFFA) The boot data can be read according the following configuration options, depending on card register settings: • The partition from which boot data is read (EXT_CSD Byte[179]) • The boot data size (EXT_CSD Byte[226]) • The bus configuration during boot (EXT_CSD Byte[177]) • Receiving boot acknowledgment from the card. (EXT_CSD Byte[179]) If boot acknowledgment is enabled the card send pattern 010 on SDMMC_D0 within 50ms after boot mode has been requested by either CMD line going low or after CMD0 with argument 0xFFFFFFFA. A boot acknowledgment timeout (ACKTIMEOUT) and acknowledgment status (ACKFAIL) is provided. Normal boot operation If the SDMMC_CMD line is held low for at least 74 clock cycles after card power-up or reset, before the first command is issued, the card recognizes that boot mode is being initiated. Within 1 second after the CMD line goes low, the card starts to sent the first boot code data on the SDMMC_Dn line(s). The host must keep the SDMMC_CMD line low until after all boot data has been read. The host can terminate boot mode by pulling the SDMMC_CMD line high. 2332/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Figure 715. Normal boot mode operation 6'00&B&. 6'00&B&0' &0' 6'00&B'Q 6 ( 6 %ORFNUHDG &5& ( 6 5(63 %ORFNUHDG &5& ( PVPD[ F\FOHVPLQ VPD[ %RRWFRPSOHWHG F\FOHV 06Y 9 To perform the normal boot procedure the following steps needed: 1. Reset the card. 2. if a boot acknowledgment is requested enable the BOOTACKEN and set the ACKTIME and enable the ACKFAIL and ACKTIMEOUT interrupt. 3. enable the data reception by setting the DPSM in receive mode (DTDIR) and the number of data bytes to be received in DATALENGTH. 4. Enable the DTIMEOUT, DATAEND, and CMDSENT interrupts for end of boot command confirmation. 5. Select the normal boot operation mode in BOOTMODE, and enable boot in BOOTEN. The boot procedure is started by enabling the CPSM with CPSMEN.This will cause: 6. 7. 8. – the SDMMC_CMD to be driven low. (BOOTMODE = normal boot). – the ACK timeout to start. – DPSM to be enabled. The incorrect reception of the boot acknowledgment can be detected with ACKFAIL flag or ACKTIMEOUT flag when enabled. – when an incorrect boot acknowledgment is received the ACKFAIL flag occurs. – when the boot acknowledgment is not received in time the ACKTIMEOUT flag occurs. when all boot data has been received the DATAEND flag will occur. – when data CRC fails the DCRCFAIL flag is also generated. – when the data timeout occurs the DTIMEOUT flag is also generated. When last data has been received, read data from the FIFO until FIFO is empty (RXFIFOE = 1) after which end of data DATAEND flag is generated. – 9. SDMMC has completely received all data and the DPSM is disabled. The boot procedure will be terminated by FW clearing BOOTEN, which will cause the SDMMC_CMD line to go high. The CMDSENT flag is generated 56 cycles later to indicate that a new command can be sent. a) If the boot procedure is aborted by FW before all data has been received the CPSM Abort signal will stop data reception and disable the DPSM which will generate an DABORT flag when enabled. 10. The CMDSENT flag signals the end of the boot procedure and the card is ready to receive a new command. DocID029587 Rev 3 2333/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Alternative boot operation After card power-up or reset, if the host send CMD0 with the argument 0xFFFFFFFA after 74 clock cycles before CMD0 is issued, the card recognizes that boot mode is being initiated. Within 1 second after the CMD0 with argument 0xFFFFFFFA has been sent, the card starts to send the first boot code data on the SDMMC_Dn line(s). The master terminates boot operation by sending CMD0 (Reset). Figure 716. Alternative boot mode operation 6'00&B&. 6'00&B&0' &0' ERRW 6'00&B'Q &0' UHVHW 6 ( 6 %ORFNUHDG ( &5& 6 &0' 5(63 %ORFNUHDG ( &5& PVPD[ VPD[ F\FOHVPLQ %RRWFRPSOHWHG F\FOHV 06Y 9 To perform the alternative boot procedure the following steps needed: 2334/3178 1. Move the SDMMC to power-off state, and reset the card 2. Move the SDMMC to power-on state. This will guarantee the 74 SCDMMC_CK cycles to be clocked before any command. 3. if a boot acknowledgment is requested enable the BOOTACKEN and set the ACKTIME and enable the ACKTIMEOUT flag. 4. enable the data reception by setting the DPSM in receive mode (DTDIR) and the number of data to be received in DATALENGTH. Enable the DTIMEOUT and DATAEND flags. 5. Select the alternative boot operation mode in BOOTMODE, load the CMD0 with the 0xFFFFFFFA argument in the command registers. Enable CMDSENT flag for end of DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) boot command confirmation, and enable boot in BOOTEN. The boot procedure is started by enabling the CPSM with CPSMEN. This will cause: – the loaded command and argument to be sent out. (BOOTMODE = alternative boot). – the ACK timeout to start. – DPSM to be enabled. 6. When the command has been sent the CMDSENT flag is generated, at which time the BOOTEN bit shall be cleared. 7. the reception of the boot acknowledgment can be detected with ACKFAIL flag when enabled. – 8. 9. when the boot acknowledgment is not received in time the ACKTIMEOUT flag will occur. when all boot data has been received the DATAEND flag will occur. – when data CRC fails the DCRCFAIL flag is also generated. – when the data timeout occurs the DTIMEOUT flag is also generated. When last data has been received, read data from the FIFO until FIFO is empty (RXFIFOE = 1) after which end of data DATAEND flag is generated. – SDMMC has completely received all data and the DPSM is disabled. 10. The BOOTEN bit shall be cleared, before terminating the boot procedure by sending CMD0 (Reset) with BOOTMODE = alternative boot. This will cause the CMDSENT flag to occur 56 cycles after the Command. – if the boot procedure is aborted by FW before all data has been received the CPSM Abort signal will stop the data transfer and disable the DPSM which will generate an DABORT flag when enabled. 11. The CMDSENT flag signals the end of the boot procedure and the card is ready to receive a new command. When the RESET command has been sent successfully, the BOOTMODE control bit has to be cleared to terminate the boot operation. 55.5.6 Response R1b handling When sending commands which have a R1b response the busy signaling is reflected in the BUSYD0 register bit and the release of busy with the BUSYD0END flag. The SDMMC_D0 line is sampled at the end of the R1b response and signaled in the BUSYD0 register bit. The BUSYD0 register bit is reset to not busy when the SDMMC_D0 line release busy, at the same time the BUSYD0END flag is generated. Figure 717. Command response R1b busy signaling 6'00&B&0' 6'00&B' &0' 5E &0' 5(63 %86< 7%86<PD[ %86<' %86<'(1' 06Y 9 DocID029587 Rev 3 2335/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 The expected maximum busy time shall be set in the DATATIME register before sending the command. When enabled, the DTIMEOUT flag will be set when after the R1b response busy stays active longer then the programmed time. To detect the SDMMC_D0 busy signaling when sending a Command with R1b response the following procedure applies: 55.5.7 • Enable CMDREND flag • Send Command through CPSM. • On the CMDREND flag check the BUSYD0 register bit. – If BUSYD0 signals not busy, signal busy release to the Firmware – If BUSYD0 signals busy, wait for BUSYD0END flag • On BUSYD0END flag signal busy released to the firmware. • On DTIMEOUT flag busy is active longer then programmed time. Reset and card cycle power Reset Following reset the SDMMC will be in the reset state. In this state the SDMMC is disabled and no command nor data can be transfered. The SDMMC_D[7:0], and SDMMC_CMD are in HiZ and the SDMMC_CK is driven low. Before moving to the power-on state the SDMMC shall be configured. In the power-on state the SDMMC_CK clock is running. First 74 SDMMC_CK cycles will be clocked after which the SDMMC is enabled and command and data can be transfered. The SDMMC states are controlled by Firmware with the PWRCTL register bits according Figure 718.. Figure 718. SDMMC state control 3:5&75/ 3RZHUF\FOH 6'00&GLVDEOHG 6LJQDOVGULYH 3:5&75/ 3:5&75/ 5HVHW 3RZHURII 6'00&GLVDEOHG 6LJQDOVGULYH 3:5&75/ 5HVHW 6'00&B&.!F\OHV 5HVHW 5HVHW 6'00&GLVDEOHG 6LJQDOV+L= 3RZHURQ 6'00&GLVDEOHG :DLWF\FOHV 5HVHW 3RZHURQ 6'00&HQDEOHG 06Y 9 Card cycle power To perform a card cycle power the following procedure applies: 2336/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 1. Reset the SDMMC with the RCC.SDMMCxRST register bit. This will reset the SDMMC to the reset state and the CPSM and DPSM to the Idle state. 2. Disable the Vcc power to the card. 3. Set the SDMMC in power-cycle state. This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being supplied through the signal lines. 4. After minimum 1ms enable the Vcc power to the card. 5. After the power ramp period set the SDMMC to the power-off state for minimum 1ms. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are set to drive “1”. 6. After the 1ms delay set the SDMMC to power-on state in which the SDMMC_CK clock will be enabled. 7. After 74 SDMMC_CK cycles the first command can be sent to the card. Figure 719. Card cycle power / power up diagram 3RZHUVWDEOH &DUG9FF 9FFPLQ 6'00&B&. 6'00&B&0' 6'00&B'Q 6'00&VWDWH 'ULYHQµ¶ +L= &0' 'ULYHQµ¶ +L= 'ULYHQµ¶ 5HVHW 3RZHUF\FOH PVPLQ PVPLQ 3RZHUUDPSXS 55.6 'ULYHQµ¶ 3RZHURII 3RZHURQ PVPLQ 6'00&B&. FORFNV 06Y 9 Hardware flow control The hardware flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors. The behavior is to stop SDMMC_CK during data transfer and freeze the SDMMC state machines. The data transfer is stalled when the FIFO is unable to transmit or receive data. The data transfer remains stalled until the transmit FIFO is half full or all data according DATALENGHT has been stored, or until the receive FIFO is half empty. Only state machines clocked by SDMMC_CK are frozen, the AHB interfaces are still alive. The FIFO can thus be filled or emptied even if flow control is activated. To enable hardware flow control, the HWFC_EN register bit must be set to 1. After reset hardware flow control is disabled. DocID029587 Rev 3 2337/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Hardware flow control shall only be used when the SDMMC_Dn data is cycle-aligned with the SDMMC_CK. Whenever the sdmmc_fb_ck from the DLYB delay block is used, i.e in the case of SDR104 mode with a tOP and DtOP delay > 1 cycle, hardware flow control can NOT be used. Figure 720. Hardware flow timing )HHGEDFN GHOD\ )HHGEDFN GHOD\ 6'00&B&. VGPPFBIEBFN 6'00&B' 'Q 'Q 'Q 'Q 'Q 'HOWDGHOD\ 06Y 9 55.7 Ultra-high-speed phase I (UHS-I) voltage switch UHS-I mode (SDR12, SDR25, SDR50, SDR104, and DDR50) requires the support for 1.8V signaling. After power up the card starts in 3.3V mode. CMD11 invokes the voltage switch sequence to the 1.8V mode. When the voltage sequence is completed successfully the card enters UHS-I mode with default SDR12 and card input and output timings are changed. Figure 721. CMD11 signal voltage switch sequence 9 6'00&B&. 9 9 6'00&B&0' 9 3URYLGH6'FORFNDW9 3URYLGH6'FORFNDW9 9 PVPLQ &0' 9 5 PLQ PVPD[ 9 6'00&B'> @ 9 9 06Y 9 To perform the signal voltage switch sequence the following steps are needed: 1. Before starting the Voltage Switch procedure, the SDMMC_CK frequency shall be set in the range 100 kHz - 400 kHz. 2. The host starts the Voltage Switch procedure by setting the VSWITCHEN bit before sending the CMD11. 3. The card returns an R1 response. – 2338/3178 if the response CRC is pass, the Voltage Switch procedure continues the host will no longer drive the CMD and SDMMC_D[3:0] signals until completion of the DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) voltage switch sequence. Some cycles after the response the SDMMC_CK will be stopped and the CKSTOP flag will be set. – if the response CRC is fail (CCRCFAIL flag) or no response is received before the timeout (CTIMEOUT flag), the Voltage Switch procedure is stopped. 4. The card drives CMD and SDMMC_D[3:0] to low at the next clock after the R1 response. 5. The host, after having received the R1 response, may monitor the SDMMC_D0 line using the BUSYD0 register bit. The SDMMC_D0 line is sampled two SDMMC_CK clock cycles after the Response. The Firmware may read the BUSYD0 register bit following the CKSTOP flag. – When the BUSYD0 is detected low the host FW will switch the Voltage regulator to 1.8V, after which it instructs the SDMMC to start the timing critical section of the Voltage Switch sequence by setting register bit VSWITCH. The hardware will continue to stop the SDMMC_CK by holding it low for at least 5ms. – When the BUSYD0 is detected high the host will abort the Voltage Switch sequence and cycle power the card. 6. The card after detecting SDMMC_CK low will begin switching signaling voltage to 1.8V. 7. The host SDMMC hardware after at least 5ms will restart the SDMMC_CK. 8. The card within 1ms from detecting SDMMC_CK transition will drive CMD and DAT[3:0] high for at least 1 SDMMC_CK cycle and then stop driving CMD and DAT[3:0]. 9. The host SDMMC hardware, 1ms after the SDMMC_CK has been restarted, the SDMMC_D0 is sampled into BUSYD0 and generate the VSWEND flag. 10. The host, on the VSWEND flag, will check SDMMC_D0 line using the BUSYD0 register bit, to confirm completion of voltage switch sequence: – When BUSYD0 is detected high, Voltage Switch has been completed successfully. – When BUSYD0 is detected low, Voltage Switch has failed, the host will cycle power the card power. The minimum 5ms time to stop the SDMMC_CK is derived from the internal ungated SDMMC_CK clock, which will have a maximum frequency of 25MHz (SD mode), as set by the clock divider CLKDIV. The >5ms time will be counted by 2^12 cycles (10.24ms @ 400 kHz). If a lower SDMMC_CK frequency is selected by the clock divider CLKDIV the time for the SDMMC_CK clock to be stopped will be longer. The maximum 1 ms time for the card to drive the SDMMC_Dn and SDMMC_CMD lines high is derived from the internal ungated SDMMC_CK which will have a maximum frequency of 25MHz (SD mode), as set by the clock divider CLKDIV. The SDMMC will check the lines after >1ms time which will be counted by 2^9 cycles (1.28ms @25MHz). If a lower SDMMC_CK frequency is selected by the clock divider CLKDIV the time to check the lines will be longer. The signal voltage level is supported through an external voltage translation transceiver i.e. ST6G3244ME. DocID029587 Rev 3 2339/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Figure 722. Voltage switch transceiver typical application 6'+RVW 9ROWDJHWUDQVFHLYHU *3,2 *3,2 6'00&B&. 6'00&B&.,1 6'00&B&',5 6'00&B&0' 6'00&B'',5 6'00&B' 6'00&B'',5 6'00&B' 6'00&B' 6'00&B' 6(/ &/.K &/.% &/.I &0'GLU &0'% &0'K '$7GLU '$7K '$7GLU /HYHOFRQYHUWHU 6'00& 6'&DUG (1 '$7% '$7K '$7% '$7K '$7% '$7K '$7% 06Y 9 To interface with an external driver (a voltage switch transceiver), next to the standard signals the SDMMC uses the following signals: SDMMC_CKIN feedback input clock SDMMC_CDIR I/O direction control for the CMD signal. SDMMC_D0DIR I/O direction control for the SDMMC_D0 signal. SDMMC_D123DIR I/O direction control for the SDMMC_D1, SDMMC_D2 and SDMMC_D3 signals. The voltage transceiver signals EN and SEL are to be handled through general-purpose I/O. The polarity of the SDMMC_CDIR, SDMMC_D0DIR and SDMMC_D123DIR signals can be selected through SDMMC_POWER.DIRPOL control bit. 2340/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 55.8 SDMMC registers The device communicates to the system via 32-bit control registers accessible via AHB slave interface. The peripheral registers have to be accessed by words (32-bit). Byte (8-bit) and halfword (16-bit) accesses generate an AHB bus error. 55.8.1 SDMMC power control register (SDMMC_POWER) Address offset: 0x000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DIR POL rw V V SWITC SWITC H H EN rw rw PWRCTRL[1:0] rw rw Bits 31:5 Reserved, must be kept at reset value. Bit 4 DIRPOL: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 0: Voltage transceiver IOs driven as output when direction signal is low. 1: Voltage transceiver IOs driven as output when direction signal is high. DocID029587 Rev 3 2341/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Bit 3 VSWITCHEN: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 0: SDMMC_CK clock kept unchanged after successfully received command response. 1: SDMMC_CK clock stopped after successfully received command response. Bit 2 VSWITCH: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 0: Voltage switch sequence not started and not active. 1: Voltage switch sequence started or active. Bits 1:0 PWRCTRL[1:0]: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL ≠ 11). These bits are used to define the functional state of the SDMMC signals: 00: After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low. When written 00, power-off: the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven high. 01: Reserved. (When written 01, PWRCTRL value will not change) 10: Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low. 11: Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. After the 74 cycles the SDMMC is enabled and the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are controlled according the SDMMC operation. Any further write will be ignored, PWRCTRL value will keep 11. 55.8.2 SDMMC clock control register (SDMMC_CLKCR) Address offset: 0x004 Reset value: 0x0000 0000 The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 Res. PWR SAV Res. Res. WID BUS[1:0] rw rw 2342/3178 rw 21 20 SELCLKRX[1:0] 19 18 17 16 BUS SPEED DDR HWFC_ EN NEG EDGE rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw CLKDIV[9:0] rw rw rw rw DocID029587 Rev 3 rw rw RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 SELCLKRX: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 00: sdmmc_io_in_ck selected as receive clock 01: SDMMC_CKIN feedback clock selected as receive clock 10: sdmmc_fb_ck tuned feedback clock selected as receive clock. 11: Reserved (select sdmmc_io_in_ck) Bit 19 BUSSPEED: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 0: DS, HS, SDR12, SDR25 bus speed mode selected 1: SDR50, DDR50, SDR104 bus speed mode selected. Bit 18 DDR: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) 0: SDR Single data rate signaling 1: DDR double data rate signaling Bit 17 HWFC_EN: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 0: Hardware flow control is disabled 1: Hardware flow control is enabled When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section 55.8.11. Bit 16 NEGEDGE: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: 0: - Command and data changed on the sdmmc_ker_ck falling edge succeeding the rising edge of SDMMC_CK. - SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. 1: - Command and data changed on the same sdmmc_ker_ck rising edge generating the SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 1: 0: - Command changed on the sdmmc_ker_ck falling edge succeeding the rising edge of SDMMC_CK. - Data changed on the sdmmc_ker_ck falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. 1: - Command changed on the same sdmmc_ker_ck rising edge generating the SDMMC_CK falling edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. DocID029587 Rev 3 2343/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Bits 15:14 WIDBUS[1:0]: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 00: Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR) 01: 4-bit wide bus mode: SDMMC_D[3:0] used 10: 8-bit wide bus mode: SDMMC_D[7:0] used Bit 13 Reserved, must be kept at reset value. Bit 12 PWRSAV: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 0: SDMMC_CK clock is always enabled 1: SDMMC_CK is only enabled when the bus is active Bits 11:10 Reserved, must be kept at reset value. Bits 9:0 CLKDIV[9:0]: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (sdmmc_ker_ck) and the output clock (SDMMC_CK): SDMMC_CK frequency = sdmmc_ker_ck / [2 * CLKDIV]. 000: SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR) 001: SDMMC_CK frequency = sdmmc_ker_ck / 2 002: SDMMC_CK frequency = sdmmc_ker_ck / 4 0xx: etc.. 080: SDMMC_CK frequency = sdmmc_ker_ck / 256 xxx: etc.. 3FF: SDMMC_CK frequency = sdmmc_ker_ck / 2046 Note: 1 While the SD/SDIO card or MMC is in identification mode, the SDMMC_CK frequency must be less than 400 kHz. 2 The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. 3 At least seven sdmmc_hclk clock periods are needed between two write accesses to this register. SDMMC_CK can also be stopped during the ReadWait interval for SD I/O cards: in this case the SDMMC_CLKCR register does not control SDMMC_CK. 55.8.3 SDMMC argument register (SDMMC_ARGR) Address offset: 0x008 Reset value: 0x0000 0000 The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 2344/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMDARG[31:16] CMDARG[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 CMDARG[31:0]: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. DocID029587 Rev 3 2345/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) 55.8.4 RM0433 SDMMC command register (SDMMC_CMDR) Address offset: 0x00C Reset value: 0x0000 0000 The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMD SUS PEND Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BOOT EN BOOT MODE DT HOLD CMD STOP CMD TRANS rw rw rw rw rw rw rw rw CPSM WAITP EN END rw rw WAIT INT rw WAITRESP[1:0] rw rw CMDINDEX[5:0] rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 CMDSUSPEND: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. Bit 15 BOOTEN: Enable boot mode procedure. 0: Boot mode procedure disabled 1: Boot mode procedure enabled Bit 14 BOOTMODE: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 0: Normal boot mode procedure selected 1: Alternative boot mode procedure selected. Bit 13 DTHOLD: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. Bit 12 CPSMEN: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. During ReadWait with SDMMC_CK stopped no command will be sent and CPSMEN is kept 0. Bit 11 WAITPEND: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 2346/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bit 10 WAITINT: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. Bits 9:8 WAITRESP[1:0]: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 00: No response, expect CMDSENT flag 01: Short response, expect CMDREND or CCRCFAIL flag 10: Short response, expect CMDREND flag (No CRC) 11: Long response, expect CMDREND or CCRCFAIL flag Bit 7 CMDSTOP: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. Bit 6 CMDTRANS: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. Bits 5:0 CMDINDEX[5:0]: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. Note: 1 At least seven sdmmc_hclk clock periods are needed between two write accesses to this register. 2 MultiMediaCard can send two kinds of response: short responses, 48 bits, or long responses,136 bits. SD card and SD I/O card can send only short responses, the argument can vary according to the type of response: the software will distinguish the type of response according to the send command. 55.8.5 SDMMC command response register (SDMMC_RESPCMDR) Address offset: 0x010 Reset value: 0x0000 0000 The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5 4 3 2 1 0 r r 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RESPCMD[5:0] r DocID029587 Rev 3 r r r 2347/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 RESPCMD[5:0]: Response command index Read-only bit field. Contains the command index of the last command response received. 55.8.6 SDMMC response 1..4 register (SDMMC_RESPxR) (x = 1..4) Address offset: (0x010 + (4 × x)) Reset value: 0x0000 0000 The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CARDSTATUSx[31:16] r r r r r r r 15 14 13 12 11 10 9 r r r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r CARDSTATUSx[15:0] r r r r r r r r r Bits 31:0 CARDSTATUSx[31:0]: see Table 448. The card status size is 32 or 128 bits, depending on the response type. Table 448. Response type and SDMMC_RESPxR registers Register(1) Short response Long response SDMMC_RESP1R Card status[31:0] Card status [127:96] SDMMC_RESP2R all 0 Card status [95:64] SDMMC_RESP3R all 0 Card status [63:32] SDMMC_RESP4R all 0 Card status [31:0](2) 1. The most significant bit of the card status is received first. 2. The SDMMC_RESP4R register LSB is always 0. 55.8.7 SDMMC data timer register (SDMMC_DTIMER) Address offset: 0x024 Reset value: 0x0000 0000 The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 2348/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATATIME[31:16] DATATIME[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DATATIME[31:0]: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. Note: A data transfer must be written to the data timer register and the data length register before being written to the data control register. 55.8.8 SDMMC data length register (SDMMC_DLENR) Address offset: 0x028 Reset value: 0x0000 0000 The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 24 23 22 21 20 rw rw rw rw rw 8 7 6 5 4 rw rw rw 19 18 17 16 rw rw rw rw 3 2 1 0 rw rw rw rw DATALENGTH[24:16] DATALENGTH[15:0] rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bits 24:0 DATALENGTH[24:0]: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. Note: For a block data transfer, the value in the data length register must be a multiple of the block size (see SDMMC_DCTRL). A data transfer must be written to the data timer register and the data length register before being written to the data control register. For an SDMMC multibyte transfer the value in the data length register must be between 1 and 512. DocID029587 Rev 3 2349/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) 55.8.9 RM0433 SDMMC data control register (SDMMC_DCTRL) Address offset: 0x02C Reset value: 0x0000 0000 The SDMMC_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO RST BOOT ACKE N SDIO EN RW MOD RW STOP RW START DTDIR DTEN rw rw rw rw rw rw rw rw Res. Res. DBLOCKSIZE[3:0] rw rw rw DTMODE rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bit 13 FIFORST: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 0: FIFO not affected. 1: Flush any remaining data and reset the FIFO pointers. This bit automatically will be cleared to 0 by hardware when DPSM gets inactive (DPSMACT = 0). Bit 12 BOOTACKEN: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0: Boot acknowledgment disabled, not expected to be received 1: Boot acknowledgment enabled, expected to be received Bit 11 SDIOEN: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. Bit 10 RWMOD: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0: Read Wait control using SDMMC_D2 1: Read Wait control stopping SDMMC_CK Bit 9 RWSTOP: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 0: No read wait stop. 1: Enable for read wait stop when DPSM is in the READ_WAIT state. Bit 8 RWSTART: Read wait start. If this bit is set, read wait operation starts. 2350/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bits 7:4 DBLOCKSIZE[3:0]: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 20 = 1 byte 0001: (1 decimal) lock length = 21 = 2 bytes 0010: (2 decimal) lock length = 22 = 4 bytes 0011: (3 decimal) lock length = 23 = 8 bytes 0100: (4 decimal) lock length = 24 = 16 bytes 0101: (5 decimal) lock length = 25 = 32 bytes 0110: (6 decimal) lock length = 26 = 64 bytes 0111: (7 decimal) lock length = 27 = 128 bytes 1000: (8 decimal) lock length = 28 = 256 bytes 1001: (9 decimal) lock length = 29 = 512 bytes 1010: (10 decimal) lock length = 210 = 1024 bytes 1011: (11 decimal) lock length = 211 = 2048 bytes 1100: (12 decimal) lock length = 212 = 4096 bytes 1101: (13 decimal) lock length = 213 = 8192 bytes 1110: (14 decimal) lock length = 214 = 16384 bytes 1111: (15 decimal) reserved When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) Bits 3:2 DTMODE: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 00: Block data transfer ending on block count. 01: SDIO multibyte data transfer. 10: MMC Stream data transfer. (WIDBUS shall select 1-bit wide bus mode) 11: Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers). Bit 1 DTDIR: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0: From host to card. 1: From card to host. Bit 0 DTEN: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0: Do not start data transfer without CPSM data transfer command. 1: Start data transfer without CPSM data transfer command. 55.8.10 SDMMC data counter register (SDMMC_DCNTR) Address offset: 0x030 Reset value: 0x0000 0000 The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. DocID029587 Rev 3 2351/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) 31 30 29 28 27 Res. Res. Res. Res. Res. 15 14 13 12 11 22 RM0433 26 25 24 23 21 20 19 18 17 16 r r r r r r r r r r r 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r DATACOUNT[24:16] DATACOUNT[15:0] r r r r r r r r r Bits 31:25 Reserved, must be kept at reset value. Bits 24:0 DATACOUNT[24:0]: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. Note: 2352/3178 This register should be read only after the data transfer is complete, or hold. When reading after an error event the read data count value may be different from the real number of data bytes transfered. DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 55.8.11 SDMMC status register (SDMMC_STAR) Address offset: 0x034 Reset value: 0x0000 0000 The SDMMC_STAR register is a read-only register. It contains two types of flag: 31 30 • Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) • Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 29 28 27 IDMA TE 26 CK STOP 25 24 23 22 21 20 19 18 17 16 VSW END ACK TIME OUT ACK FAIL SDIOIT BUSY D0END BUSY D0 RX FIFOE TX FIFOE RX FIFOF TX FIFOF Res. Res. Res. IDMA BTC r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX FIFO HF TX FIFO HE CPSM ACT DPSM ACT D ABOR T DATA END CMD SENT D TIME OUT C TIME OUT DCRC FAIL CCRC FAIL r r r r r r r r r r r DBCK DHOLD END r r TX CMDR RX UNDER END OVERR R r r r Bits 31:29 Reserved, must be kept at reset value. Bit 28 IDMABTC: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 27 IDMATE: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 26 CKSTOP: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 25 VSWEND: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 24 ACKTIMEOUT: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 23 ACKFAIL: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 22 SDIOIT: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 21 BUSYD0END: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0: card SDMMC_D0 signal does NOT signal change from busy to not busy. 1: card SDMMC_D0 signal changed from busy to NOT busy. DocID029587 Rev 3 2353/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Bit 20 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 0: card signals not busy on SDMMC_D0. 1: card signals busy on SDMMC_D0. Bit 19 RXFIFOE: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. Bit 18 TXFIFOE: Transmit FIFO empty This bit is cleared when one FIFO location becomes full. Bit 17 RXFIFOF: Receive FIFO full This bit is cleared when one FIFO location becomes empty. Bit 16 TXFIFOF: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. Bit 15 RXFIFOHF: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. Bit 14 TXFIFOHE: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. Bit 13 CPSMACT: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. Bit 12 DPSMACT: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. Bit 11 DABORT: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 10 DBCKEND: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 9 DHOLD: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 8 DATAEND: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 7 CMDSENT: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 6 CMDREND: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 5 RXOVERR: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 2354/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bit 4 TXUNDERR: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 3 DTIMEOUT: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 2 CTIMEOUT: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Bit 0 CCRCFAIL: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. Note: FIFO interrupt flags shall be masked in SDMMC_MASKR when using IDMA mode. 55.8.12 SDMMC interrupt clear register (SDMMC_ICR) Address offset: 0x038 Reset value: 0x0000 0000 The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 31 30 29 28 27 26 25 24 CK STOP C VSW ENDC ACK TIME OUTC 23 22 21 20 19 18 17 16 ACK FAILC SDIO ITC BUSY D0 ENDC Res. Res. Res. Res. Res. 4 3 2 1 0 D TIME OUTC C TIME OUTC DCRC FAILC CCRC FAILC rw rw rw rw Res. Res. Res. IDMA BTCC IDMA TEC rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. D ABOR TC rw DBCK DHOLD ENDC C rw rw DATA ENDC rw RX TX CMD CMDR OVERR UNDER SENTC ENDC C RC rw rw rw rw Bits 31:39 Reserved, must be kept at reset value. Bit 28 IDMABTCC: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 0: IDMABTC not cleared 1: IDMABTC cleared Bit 27 IDMATEC: IDMA transfer error clear bit Set by software to clear the IDMATE flag. 0: IDMATE not cleared 1: IDMATE cleared Bit 26 CKSTOPC: CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 0: CKSTOP not cleared 1: CKSTOP cleared DocID029587 Rev 3 2355/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) Bit 25 VSWENDC: VSWEND flag clear bit Set by software to clear the VSWEND flag. 0: VSWEND not cleared 1: VSWEND cleared Bit 24 ACKTIMEOUTC: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 0: ACKTIMEOUT not cleared 1: ACKTIMEOUT cleared Bit 23 ACKFAILC: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 0: ACKFAIL not cleared 1: ACKFAIL cleared Bit 22 SDIOITC: SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 0: SDIOIT not cleared 1: SDIOIT cleared Bit 21 BUSYD0ENDC: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 0: BUSYD0END not cleared 1: BUSYD0END cleared Bits 20:12 Reserved, must be kept at reset value. Bit 11 DABORTC: DABORT flag clear bit Set by software to clear the DABORT flag. 0: DABORT not cleared 1: DABORT cleared Bit 10 DBCKENDC: DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 0: DBCKEND not cleared 1: DBCKEND cleared Bit 9 DHOLDC: DHOLD flag clear bit Set by software to clear the DHOLD flag. 0: DHOLD not cleared 1: DHOLD cleared Bit 8 DATAENDC: DATAEND flag clear bit Set by software to clear the DATAEND flag. 0: DATAEND not cleared 1: DATAEND cleared Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared 2356/3178 DocID029587 Rev 3 RM0433 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bit 5 RXOVERRC: RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 0: RXOVERR not cleared 1: RXOVERR cleared Bit 4 TXUNDERRC: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 0: TXUNDERR not cleared 1: TXUNDERR cleared Bit 3 DTIMEOUTC: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 0: DTIMEOUT not cleared 1: DTIMEOUT cleared Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 0: CTIMEOUT not cleared 1: CTIMEOUT cleared Bit 1 DCRCFAILC: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 0: DCRCFAIL not cleared 1: DCRCFAIL cleared Bit 0 CCRCFAILC: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0: CCRCFAIL not cleared 1: CCRCFAIL cleared DocID029587 Rev 3 2357/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) 55.8.13 RM0433 SDMMC mask register (SDMMC_MASKR) Address offset: 0x03C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 31 30 29 28 27 21 20 19 18 17 16 ACK FAILIE SDIO ITIE BUSY D0 ENDIE Res. Res. TX FIFO EIE RX FIFO FIE Res. rw rw 4 3 2 1 0 C TIME OUTIE DCRC FAILIE CCRC FAILIE rw rw rw rw rw rw rw rw rw 12 11 10 9 8 7 6 5 Res. D ABOR T IE 15 14 13 rw rw 22 VSW ENDIE IDMA BTCIE rw 23 CK STOP IE Res. Res. 24 Res. Res. TX FIFO HEIE 25 ACK TIME OUTIE Res. RX FIFO HFIE 26 rw DBCK DHOLD DATA ENDIE IE ENDIE rw rw rw CMD SENTI E rw RX TX D CMDR OVERR UNDER TIME ENDIE IE RIE OUTIE rw rw rw rw Bits 31:29 Reserved, must be kept at reset value. Bit 28 IDMABTCIE: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 0: IDMA buffer transfer complete interrupt disabled 1: IDMA buffer transfer complete interrupt enabled Bit 27 Reserved, must be kept at reset value. Bit 26 CKSTOPIE: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 0: Voltage Switch clock stopped interrupt disabled 1: Voltage Switch clock stopped interrupt enabled Bit 25 VSWENDIE: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 0: Voltage switch critical timing section completion interrupt disabled 1: Voltage switch critical timing section completion interrupt enabled Bit 24 ACKTIMEOUTIE: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 0: Acknowledgment timeout interrupt disabled 1: Acknowledgment timeout interrupt enabled Bit 23 ACKFAILIE: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 0: Acknowledgment Fail interrupt disabled 1: Acknowledgment Fail interrupt enabled 2358/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 0: SDIO Mode interrupt received interrupt disabled 1: SDIO Mode interrupt received interrupt enabled Bit 21 BUSYD0ENDIE: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 0: BUSYD0END interrupt disabled 1: BUSYD0END interrupt enabled Bits 20:19 Reserved, must be kept at reset value. Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 0: Tx FIFO empty interrupt disabled 1: Tx FIFO empty interrupt enabled Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 0: Rx FIFO full interrupt disabled 1: Rx FIFO full interrupt enabled Bit 16 Reserved, must be kept at reset value. Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 0: Rx FIFO half full interrupt disabled 1: Rx FIFO half full interrupt enabled Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 0: Tx FIFO half empty interrupt disabled 1: Tx FIFO half empty interrupt enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 DABORTIE: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 0: Data transfer abort interrupt disabled 1: Data transfer abort interrupt enabled Bit 10 DBCKENDIE: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 0: Data block end interrupt disabled 1: Data block end interrupt enabled Bit 9 DHOLDIE: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 0: Data hold interrupt disabled 1: Data hold interrupt enabled DocID029587 Rev 3 2359/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Bit 8 DATAENDIE: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 0: Data end interrupt disabled 1: Data end interrupt enabled Bit 7 CMDSENTIE: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 0: Command sent interrupt disabled 1: Command sent interrupt enabled Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 0: Rx FIFO overrun error interrupt disabled 1: Rx FIFO overrun error interrupt enabled Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 0: Tx FIFO underrun error interrupt disabled 1: Tx FIFO underrun error interrupt enabled Bit 3 DTIMEOUTIE: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 0: Data timeout interrupt disabled 1: Data timeout interrupt enabled Bit 2 CTIMEOUTIE: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 0: Command timeout interrupt disabled 1: Command timeout interrupt enabled Bit 1 DCRCFAILIE: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 0: Data CRC fail interrupt disabled 1: Data CRC fail interrupt enabled Bit 0 CCRCFAILIE: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0: Command CRC fail interrupt disabled 1: Command CRC fail interrupt enabled 55.8.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) Address offset: 0x040 Reset value: 0x0000 0000 The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. 2360/3178 DocID029587 Rev 3 RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 ACKTIME[24:16] rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ACKTIME[15:0] rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bits 24:0 ACKTIME[24:0]: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. Note: The data transfer must be written to the acknowledgment timer register before being written to the data control register. DocID029587 Rev 3 2361/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) 55.8.15 RM0433 SDMMC data FIFO register (SDMMC_FIFOR) Address offset: 0x080 to 0x0BC Reset value: 0x0000 0000 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIFODATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw FIFODATA[15:0] rw rw Bits 31:0 FIFODATA[31:0]: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT = 1). The FIFO data occupies 16 entries of 32-bit words. 55.8.16 SDMMC DMA control register (SDMMC_IDMACTRLR) Address offset: 0x050 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. IDMAB ACT IDMAB MODE IDMA EN rw rw rw Res. Res. 2362/3178 Res. Res. Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 Res. Res. RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) Bits 31:3 Reserved, must be kept at reset value. Bit 2 IDMABACT: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 0: When IDMA is enabled, uses buffer0 and firmware write access to IDMABASE0 is prohibited. 1: When IDMA is enabled, uses buffer1 and firmware write access to IDMABASE1 is prohibited. Bit 1 IDMABMODE: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0: Single buffer mode. 1: Double buffer mode. Bit 0 IDMAEN: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0: IDMA disabled 1: IDMA enabled 55.8.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) Address offset: 0x054 Reset value: 0x0000 0000 The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 7 6 5 15 14 13 Res. Res. Res. IDMABNDT[7:0] rw rw rw rw rw rw rw 4 3 2 1 0 Res. Res. Res. Res. Res. rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:5 IDMABNDT[7:0]: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). Bits 4:0 Reserved, must be kept at reset value. 55.8.18 SDMMC IDMA buffer 0 base address register (SDMMC_IDMABASE0R) Address offset: 0x058 Reset value: 0x0000 0000 The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. DocID029587 Rev 3 2363/3178 2367 Secure digital input/output MultiMediaCard interface (SDMMC) 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 RM0433 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw r r IDMABASE0[31:16] IDMABASE0[15:0] rw rw rw rw rw rw rw rw Bits 31:0 IDMABASE0[31:0]: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = ‘1’). 55.8.19 SDMMC IDMA buffer 1 base address register (SDMMC_IDMABASE1R) Address offset: 0x05C Reset value: 0x0000 0000 The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDMABASE1[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw r r IDMABASE1[15:0] rw rw rw rw rw rw rw rw Bits 31:0 IDMABASE1[31:0]: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = ‘0’). 2364/3178 DocID029587 Rev 3 RM0433 55.8.20 Secure digital input/output MultiMediaCard interface (SDMMC) SDMMC register map The following table summarizes the SDMMC registers. VSWITCH PWRCTRL[1:0] VSWITCHEN Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDTRANS CLKDIV[9:0] CMDINDEX[5:0] Res. 0 0 CMDSTOP 0 0 Res. SDMMC_ ARGR 0 Res. 0 Res. 0 PWRSAV NEGEDGE 0 Res. HWFC_EN 0 WIDBUS[1:0] DDR 0 RESPCMD[5:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDMMC_ CMDR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CMDSUSPEND BOOTEN BOOTMODE DTHOLD CPSMEN WAITPEND WAITINT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WAITRESP[1:0] Reset value Res. CMDARG[31:0] Res. 0x0C 0 BUSSPEED Reset value 0x08 SELCLKRX[1:0] Res. Res. Res. Res. Res. Res. Res. Res. SDMMC_ CLKCR Res. 0x04 Res. Reset value DIRPOL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC_ POWER Res. 0x00 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 449. SDMMC register map SDMMC_ RESPCMDR Res. 0x10 Res. Reset value Reset value 0x14 SDMMC_ RESP1R Reset value 0x18 0x1C 0x20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS3[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS4[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDMMC_ DTIMER 0 0 0 0 0 0 0 0 0 0 0 SDMMC_ DLENR Res. Res. Res. Res. Res. Res. DATATIME[31:0] Reset value Reset value 0 CARDSTATUS2[31:0] Res. 0x28 0 SDMMC_ RESP4R Reset value 0x24 0 SDMMC_ RESP3R Reset value 0 CARDSTATUS1[31:0] SDMMC_ RESP2R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 DATALENGTH[24:0] 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 2365/3178 2367 2366/3178 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Reserved 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 SDMMC_ IDMABASE0R SDMMC_ IDMABASE1R 0 0 0 DocID029587 Rev 3 0 0 Reset value 0 IDMABNDT[7:0] IDMABASE0[31:0] Res. 0 Res. 0 CCRCFAIL CCRCFAILC DCRCFAIL DCRCFAILC 0 0 0 0 0 ACKTIME[24:0] 0 0 CCRCFAILIE 0 DCRCFAILIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDMABMODE Res. 0 CTIMEOUTIE 0 DTIMEOUTIE 0 Res. DTDIR DTEN 0 Reset value Res. 0 0 Res. SDIOEN RWMOD 0 RWSTOP BOOTACKEN 0 RWSTART FIFORST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 DTMODE DBLOCK SIZE[3:0] IDMAEN CTIMEOUT 0 CTIMEOUTC 0 DTIMEOUTC 0 RXOVERRC 0 TXUNDERRC 0 CMDSENTC 0 CMDRENDC 0 DHOLDC 0 DATAENDC 0 DBCKENDC 0 DABORTC 0 DABORTIE DTIMEOUT Res. RXOVERR Res. TXUNDERR Res. 0 0 Res. Res. Res. Res. CMDSENT Res. CMDREND Res. DHOLD Res. 0 0 IDMABACT Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 DATAEND 0 RXOVERRIE Res. Res. 0 TXUNDERRIE Res. Res. 0 DBCKEND 0 DABORT 0 DPSMACT 0 Res. 0 Res. 0 CPSMACT TXFIFOHE 0 Res. Res. Res. 0 0 Res. RXFIFOHF 0 CMDSENTIE Res. Res. 0 TXFIFOHEIE TXFIFOF 0 CMDRENDIE Res. Res. 0 RXFIFOHFIE RXFIFOF 0 DHOLDIE Res. Res. 0 Res. RXFIFOFIE TXFIFOE 0 DATAENDIE Res. Res. 0 TXFIFOEIE RXFIFOE 0 DBCKENDIE Res. Res. 0 Res. BUSYD0 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. 0 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. BUSYD0END BUSYD0ENDC BUSYD0ENDIE 0 Res. Res. Res. SDIOIT SDIOITC SDIOITIE 0 Res. Res. Res. ACKFAIL ACKFAILC ACKFAILIE ACKTIMEOUT ACKTIMEOUTC 0 ACKTIMEOUTIE VSWEND VSWEDNDC 0 VSWENDIE 0 Res. CKSTOP CKSTOPC 0 CKSTOPIE 0 Res. IDMATE IDMATEC 0 Res. Res. Res. Res. IDMABTC Res. IDMABTCC 0 IDMABTCIE Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Reset value Res. 0 Res. 0 Res. 0 Res. Reset value Res. Reset value Res. 0 Res. SDMMC_ IDMABSIZER Res. Reset value Res. Res. Res. SDMMC_ ACKTIMER Res. Reset value Res. 0 Res. Res. Res. SDMMC_ MASKR Res. Reset value Res. Res. SDMMC_ IDMACTRLR Res. 0x3C Res. SDMMC_ ICR Res. 0x38 Res. SDMMC_ STAR Res. 0x34 Res. Res. 0x30 SDMMC_ DCNTR Res. Res. SDMMC_ DCTRLR Res. Reserved Res. 0x44 - 0x4C Res. 0x2C Res. Reset value Res. 0x60 - 0x7C Res. 0x5C Res. 0x58 Res. 0x54 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 0x50 Res. 0x40 Res. Secure digital input/output MultiMediaCard interface (SDMMC) RM0433 Table 449. SDMMC register map (continued) DATACOUNT[24:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDMABASE1[31:0] RM0433 Secure digital input/output MultiMediaCard interface (SDMMC) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Reserved 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value Res. FIF0Data[31:0] Res. 0x84 - x3FC SDMMC_ FIFOR Res. 0x80 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 449. SDMMC register map (continued) Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 2367/3178 2367 FD Controller Area Network (FDCAN) RM0433 56 FD Controller Area Network (FDCAN) 56.1 Introduction The Controller Area Network (CAN) subsystem (see Figure 723) consists of two CAN modules, a shared Message RAM memory and a clock calibration unit. Refer to the memory map for the base address of each of these four parts. Both modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. In addition, the first CAN module FDCAN1 supports time triggered CAN (TTCAN), specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication. A 10 Kbyte Message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TTCAN). This Message RAM is shared between the FDCAN1 and FDCAN2 modules. The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1. The CAN subsystem I/O signals and pins are detailed, respectively, in Table 450 and Table 451. Table 450. CAN subsystem I/O signals Name fdcan_ker_ck fdcan_pclk Type Digital input fdan1_intr0_it fdan1_intr1_it fdan2_intr0_it CAN subsystem kernel clock input CAN subsystem APB interface clock input FDCAN1 interrupt0 Digital output FDCAN1 interrupt1 FDCAN2 interrupt0 fdan2_intr1_it FDCAN2 interrupt1 fdcan1_swt[0:3] Stop watch trigger input fdcan1_evt[0:3] Digital input Event trigger input fdcan1_ts[0:15] External timestamp vector fdcan1_soc Start of cycle pulse fdcan1_rtp fdcan1_tmp 2368/3178 Description Digital output Register time mark pulse Trigger time mark pulse DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 451. CAN subsystem I/O pins Name Type Description FDCAN1_RX Digital input FDCAN1 receive pin FDCAN1_TX Digital output FDCAN1 transmit pin FDCAN2_RX Digital input FDCAN2 receive pin FDCAN2_TX Digital output FDCAN2 transmit pin DocID029587 Rev 3 2369/3178 2501 FD Controller Area Network (FDCAN) RM0433 Figure 723. CAN subsystem IGFDQBNHUBFN &ORFN &DOLEUDWLRQ 8QLW &&8 &&)*%&& ELW$3%EXV &&)*&',9 IGFDQBLQWUBLW IGFDQBLQWUBLW &DOLEUDWLRQ IGFDQBWTBFN NHUQHOFORFNGRPDLQ ,QWHUUXSWV ,QWHUIDFH IGFDQBLQWUBLW )'&$1B5; &$1FRUH 6\QF IGFDQBLQWUBLW )'&$1B7; ELW$3%EXV )'&$1B5; )'&$1B7; 6\QF &RQWURODQG &RQILJXUDWLRQ UHJLVWHUV 7[5HT 7[6WDWH 5[6WDWH IGFDQBUWS 7;+DQGOHU IGFDQBSFON IGFDQBWPS 7;SULRULWL]DWLRQ )UDPH6\QFKUR IGFDQBVRF IGFDQBVZW>@ 5;+DQGOHU IGFDQBHYW>@ $FFHSWDQFHILOWHU 0HVVDJH5$0 LQWHUIDFH $3%FORFN GRPDLQ )'&$1 IGFDQBWV> @ ELW$3%EXV )'&$1 5$0 &RQWUROOHU$UELWUHU 0HVVDJH5$0 %XIIHUV ),)2V )LOWHUV 069 2370/3178 DocID029587 Rev 3 RM0433 56.2 FD Controller Area Network (FDCAN) FDCAN main features • Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4 • CAN FD with max. 64 data bytes supported • TTCAN protocol level 1 and level 2 completely in hardware (FDCAN1 only) • Event synchronized time-triggered communication supported (FDCAN1 only) • CAN error logging • AUTOSAR and J1939 support • Improved acceptance filtering • Two configurable Receive FIFOs • Separate signaling on reception of High Priority Messages • Up to 64 dedicated Receive Buffers • Up to 32 dedicated Transmit Buffers • Configurable Transmit FIFO /Queue • Configurable Transmit Event FIFO • Both FDCAN1 and FDCAN2 modules share the same Message RAM • Programmable loop-back test mode • Maskable module interrupts • Two clock domains: APB bus interface and CAN core kernel clock • Power-down support DocID029587 Rev 3 2371/3178 2501 FD Controller Area Network (FDCAN) 56.3 RM0433 FDCAN functional description Figure 724. FDCAN block diagram IGFDQBWTBFN .HUQHOFORFNGRPDLQ IGFDQBLQWUBLW ELW$3%EXV )'&$1B5; &$1FRUH 6\QF IGFDQBLQWUBLW ,QWHUUXSWV ,QWHUIDFH )'&$1B7; 6\QF &RQWURODQG &RQILJXUDWLRQ UHJLVWHUV 7[5HT 7[6WDWH 5[6WDWH IGFDQBUWS 7;+DQGOHU IGFDQBWPS 7;SULRULWL]DWLRQ )UDPH6\QFKUR IGFDQBVRF IGFDQBVZW>@ 5;+DQGOHU IGFDQBHYW>@ $FFHSWDQFHILOWHU 0HVVDJH5$0 LQWHUIDFH IGFDQBSFON $3%FORFN GRPDLQ )'&$1 IGFDQBWV> @ 069 Dual interrupt lines The FDCAN peripheral provides two interrupt lines fdcan_intr0_it and fdcan_intr1_it. By programming EINT0 and EINT1 bits in FDCAN_ILE register, the interrupt lines can be enabled or disabled separately. CAN Core The CAN Core contains the Protocol Controller and receive/transmit shift registers. It handles all ISO 11898-1: 2015 protocol functions and supports both 11-bit and 29-bit identifiers. Sync The Sync block synchronizes signals from the APB clock domain to the CAN kernel clock domain and vice versa. 2372/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Tx Handler Controls the message transfer from the Message RAM to the CAN Core. A maximum of 32 Tx Buffers can be configured for transmission. Tx buffers can be used as dedicated Tx Buffers, as Tx FIFO, part of a Tx Queue, or as a combination of them. A Tx Event FIFO stores Tx timestamps together with the corresponding Message ID. Transmit cancellation is also supported. On FDCAN1, the Tx Handler also implements the Frame Synchronization Entity (FSE) which controls time-triggered communication according to ISO11898-4. It synchronizes itself with the reference messages on the CAN bus, controls cycle time and global time, and handles transmissions according to the predefined message schedule, the system matrix. It also handles the time marks of the system matrix that are linked to the messages in the Message RAM. Stop Watch Trigger, Event Trigger, and Time Mark Interrupt are synchronization interfaces. Rx Handler Controls the transfer of received messages from the CAN Core to the external Message RAM. The Rx Handler supports two Receive FIFOs, each of configurable size, and up to 64 dedicated Rx Buffers for storage of all messages that have passed acceptance filtering. A dedicated Rx Buffer, in contrast to a Receive FIFO, is used to store only messages with a specific identifier. An Rx timestamp is stored together with each message. Up to 128 filters can be defined for 11-bit IDs and up to 64 filters for 29-bit IDs. APB Interface Connects the FDCAN to the APB bus. Message RAM Interface Connects the FDCAN access to an external 10 Kbytes Message RAM through a RAM controller/arbiter. 56.3.1 Operating modes Software initialization Software initialization is started by setting INIT bit in FDCAN_CCCR register, either by software or by a hardware reset, or by going Bus_Off. While INIT bit in FDCAN_CCCR register is set, message transfer from and to the CAN bus is stopped, the status of the CAN bus output FDCAN_TX is recessive (high). The counters of the Error Management Logic (EML) are unchanged. Setting INIT bit in FDCAN_CCCR does not change any configuration register. Clearing INIT bit in FDCAN_CCCR finishes the software initialization. Afterwards the Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus_Idle) before it can take part in bus activities and start the message transfer. Access to the FDCAN configuration registers is only enabled when both INIT bit in FDCAN_CCCR register and CCE bit in FDCAN_CCCR register are set. CCE bit in FDCAN_CCCR register can only be set/cleared while INIT bit in FDCAN_CCCR is set. CCE bit in FDCAN_CCCR register is automatically cleared when INIT bit in FDCAN_CCCR is cleared. DocID029587 Rev 3 2373/3178 2501 FD Controller Area Network (FDCAN) RM0433 The following registers are reset when CCE bit in FDCAN_CCCR register is set: • FDCAN_HPMS - High Priority Message Status • FDCAN_ RXF0S - Rx FIFO 0 Status • FDCAN_RXF1S - Rx FIFO 1 Status • FDCAN_TXFQS - Tx FIFO/Queue Status • FDCAN_TXBRP - Tx Buffer Request Pending • FDCAN_TXBTO - Tx Buffer Transmission Occurred • FDCAN_TXBCF - Tx Buffer Cancellation Finished • FDCAN_TXEFS - Tx Event FIFO Status • FDCAN_TTOST - TT Operation Status (FDCAN1 only) • FDCAN_TTLGT - TT Local & Global Time, only Global Time TTLGT.GT is reset (FDCAN1 only) • FDCAN_TTCTC - TT Cycle Time & Count (FDCAN1 only) • FDCAN_TTCSM - TT Cycle Sync Mark (FDCAN1 only) The Timeout Counter value TOC bit in FDCAN_TOCV register is preset to the value configured by TOP bit in FDCAN_TOCC register when CCE bit in FDCAN_CCCR is set. In addition the state machines of the Tx Handler and Rx Handler are held in idle state while CCE bit in FDCAN_CCCR is set. The following registers can be written only when CCE bit in FDCAN_CCCR register is cleared: • TXBAR - Tx Buffer Add Request • TXBCR - Tx Buffer Cancellation Request TEST bit in FDCAN_CCCR and MON bit in FDCAN_CCCR can only be set by software while both INIT bit in CCCR and CCE bit in CCCR register are set. Both bits may be reset at any time. DAR bit in FDCAN_CCCR can only be set/cleared while both INIT bit in FDCAN_CCCR and CCE bit in FDCAN_CCCR are set. Normal operation The FDCAN1 default operating mode after hardware reset is event-driven CAN communication without time triggers (TTOCF[OM] = ‘00’). It is required that both INIT bit and CCE bit in FDCAN_CCCR register are set before the TT Operation Mode can be changed. Once the FDCAN is initialized and INIT bit in FDCAN_CCCR register is cleared, the FDCAN synchronizes itself to the CAN bus and is ready for communication. After passing the acceptance filtering, received messages including Message ID and DLC are stored into a dedicated Rx Buffer or into the Rx FIFO 0 or Rx FIFO 1. For messages to be transmitted dedicated Tx Buffers and/or a Tx FIFO or a Tx Queue can be initialized or updated. Automated transmission on reception of remote frames is not supported. CAN FD operation There are two variants in the FDCAN protocol, first the Long Frame Mode (LFM) where the data field of a CAN frame may be longer that eight bytes. The second variant is the Fast Frame Mode (FFM) where control field, data field, and CRC field of a CAN frame are 2374/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) transmitted with a higher bit rate than the beginning and the end of the frame. Fast Frame Mode can be used in combination with Long Frame Mode. The previously reserved bit in CAN frames with 11-bit identifiers and the first previously reserved bit in CAN frames with 29-bit identifiers will now be decoded as FDF bit. FDF recessive signifies a CAN FD frame, while FDF dominant signifies a classic CAN frame. In a CAN FD frame, the two bits following FDF, res and BRS, decide whether the bit rate inside this CAN FD frame is switched. A CAN FD bit rate switch is signified by res dominant and BRS recessive. The coding of res recessive is reserved for future expansion of the protocol. In case the M_TTCAN receives a frame with FDF recessive and res recessive, it will signal a Protocol Exception Event by setting bit PSR.PXE. When Protocol Exception Handling is enabled (CCCR.PXHD = ‘0’), this causes the operation state to change from Receiver (PSR.ACT = “10”) to Integrating (PSR.ACT = “00”) at the next sample point. In case Protocol Exception Handling is disabled (CCCR.PXHD = ‘1’), the FDCAN will treat a recessive res bit as a form error and will respond with an error frame. CAN FD operation is enabled by programming CCCR.FDOE. In case CCCR.FDOE = ‘1’, transmission and reception of CAN FD frames is enabled. Transmission and reception of Classic CAN frames is always possible. Whether a CAN FD frame or a classic CAN frame is transmitted can be configured via bit FDF in the respective Tx Buffer element. With CCCR.FDOE = ‘0’, received frames are interpreted as classic CAN frames, which leads to the transmission of an error frame when receiving a CAN FD frame. When CAN FD operation is disabled, no CAN FD frames are transmitted even if bit FDF of a Tx Buffer element is set. CCCR.FDOE and CCCR.BRSE can only be changed while CCCR.INIT and CCCR.CCE are both set. With CCCR.FDOE = ‘0’, the setting of bits FDF and BRS is ignored and frames are transmitted in Classic CAN format. With CCCR.FDOE = ‘1’ and CCCR.BRSE = ‘0’, only bit FDF of a Tx Buffer element is evaluated. With CCCR.FDOE = ‘1’ and CCCR.BRSE = ‘1’, transmission of CAN FD frames with bit rate switching is enabled. All Tx Buffer elements with bits FDF and BRS set are transmitted in CAN FD format with bit rate switching. A mode change during CAN operation is only recommended under the following conditions: • The failure rate in the CAN FD data phase is significant higher than in the CAN FD arbitration phase. In this case disable the CAN FD bit rate switching option for transmissions. • During system startup all nodes are transmitting Classic CAN messages until it is verified that they are able to communicate in CAN FD format. If this is true, all nodes switch to CAN FD operation. • Wake-up messages in CAN Partial Networking have to be transmitted in Classic CAN format. • End-of-line programming in case not all nodes are CAN FD capable. Non CAN FD nodes are held in Silent mode until programming has completed. Then all nodes switch back to Classic CAN communication. In the FDCAN format, the coding of the DLC differs from the standard CAN format. The DLC codes 0 to 8 have the same coding as in standard CAN, the codes 9 to 15 (that in standard CAN all code a data field of 8 bytes) are coded according to Table 452. : Table 452. DLC coding in FDCAN DLC 9 10 11 12 13 14 15 Number of data bytes 12 16 20 24 32 48 64 DocID029587 Rev 3 2375/3178 2501 FD Controller Area Network (FDCAN) RM0433 In CAN FD Fast Frames, the bit timing will be switched inside the frame, after the BRS (Bit Rate Switch) bit, if this bit is recessive. Before the BRS bit, in the FDCAN arbitration phase, the standard CAN bit timing is used as defined by the Bit Timing and Prescaler Register BTP. In the following FDCAN data phase, the fast CAN bit timing is used as defined by the Fast Bit Timing and Prescaler Register FBTP. The bit timing is switched back from the fast timing at the CRC delimiter or when an error is detected, whichever occurs first. The maximum configurable bit rate in the CAN FD data phase depends on the FDCAN kernel clock frequency. For example, with a FDCAN kernel clock frequency of 20 MHz and the shortest configurable bit time of four time quanta (tq), the bit rate in the data phase is 5 Mbit/s. In both data frame formats, CAN FD Long Frames and CAN FD Fast Frames, the value of the bit ESI (Error Status Indicator) is determined by the transmitter error state at the start of the transmission. If the transmitter is error passive, ESI is transmitted recessive, else it is transmitted dominant. In CAN FD remote frames the ESI bit is always transmitted dominant, independent of the transmitter error state. The data length code of CAN FD remote frames is transmitted as 0. In case a FDCAN Tx Buffer is configured for FDCAN transmission with DLC > 8, the first 8 bytes are transmitted as configured in the Tx Buffer while the remaining part of the data field is padded with 0xCC. When the FDCAN receives a FDCAN frame with DLC > 8, the first 8 bytes of that frame are stored into the matching Rx Buffer or Rx FIFO. The remaining bytes are discarded. Transceiver delay compensation During the data phase of a FDCAN transmission only one node is transmitting, all others are receivers. The length of the bus line has no impact. When transmitting via pin FDCAN_TX the protocol controller receives the transmitted data from its local CAN transceiver via pin FDCAN_RX. The received data is delayed by the CAN transceiver loop delay. In case this delay is greater than TSEG1 (time segment before sample point), a bit error is detected. Without transceiver delay compensation, the bit rate in the data phase of a FDCAN frame is limited by the transceivers loop delay. The FDCAN implements a delay compensation mechanism to compensate the CAN transceiver loop delay, thereby enabling transmission with higher bit rates during the FDCAN data phase independent of the delay of a specific CAN transceiver. To check for bit errors during the data phase of transmitting nodes, the delayed transmit data is compared against the received data at the Secondary Sample Point SSP. If a bit error is detected, the transmitter will react on this bit error at the next following regular sample point. During arbitration phase the delay compensation is always disabled. The transmitter delay compensation enables configurations where the data bit time is shorter than the transmitter delay, it is described in detail in the new ISO11898-1. It is enabled by setting bit DBTP.TDC. The received bit is compared against the transmitted bit at the SSP. The SSP position is defined as the sum of the measured delay from the FDCAN transmit output pin FDCAN_TX through the transceiver to the receive input pin FDCAN_RX plus the transmitter delay compensation offset as configured by TDCR.TDCO. The transmitter delay compensation offset is used to adjust the position of the SSP inside the received bit (e.g. half of the bit time in the data phase). The position of the secondary sample point is rounded down to the next integer number of mtq (minimum time quantum, that is one period of fdcan_tq_ck clock). 2376/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) PSR.TDCV shows the actual transmitter delay compensation value. PSR.TDCV is cleared when CCCR.INIT is set and is updated at each transmission of an FD frame while DBTP.TDC is set. The following boundary conditions have to be considered for the transmitter delay compensation implemented in the FDCAN: • The sum of the measured delay from m_ttcan_tx to m_ttcan_rx and the configured transmitter delay compensation offset TDCR.TDCO has to be less than 6 bit times in the data phase. • The sum of the measured delay from m_ttcan_tx to m_ttcan_rx and the configured transmitter delay compensation offset TDCR.TDCO has to be less or equal 127 mtq. In case this sum exceeds 127 mtq, the maximum value (127 mtq) is used for transmitter delay compensation. • The data phase ends at the sample point of the CRC delimiter, that stops checking received bits at the SSPs If transmitter delay compensation is enabled by programming DBTP.TDC = ‘1’, the measurement is started within each transmitted CAN FD frame at the falling edge of bit FDF to bit res. The measurement is stopped when this edge is seen at the receive input pin FDCAN_TX of the transmitter. The resolution of this measurement is one mtq. Figure 725. Transceiver delay measurement 5HV )') %56 (6, 7UDQVPLWWHU GHOD\ '/& PBWWFDQBW[ $UELWUDWLRQSKDVH 'DWDSKDVH PBWWFDQBU[ $UELWUDWLRQSKDVH 6WDUW PBWWFDQBFFON 'DWDSKDVH 6WRS 'HOD\ 'HOD\FRXQWHU 663SRVLWLRQ 7'&57'&2 'HOD\FRPSHQVDWLRQRIIVHW 069 To avoid that a dominant glitch inside the received FDF bit ends the delay compensation measurement before the falling edge of the received res bit (resulting in a to early SSP position) the use of a transmitter delay compensation filter window can be enabled by programming TDCR.TDCF. This defines a minimum value for the SSP position. Dominant edges on m_ttcan_rx, that would result in an earlier SSP position are ignored for transmitter delay measurement. The measurement is stopped when the SSP position is at least TDCR.TDCF and FDCAN_RX is low. Restricted Operation Mode In Restricted Operation Mode the node is able to receive data and remote frames and to give acknowledge to valid frames, but it does not send data frames, remote frames, active DocID029587 Rev 3 2377/3178 2501 FD Controller Area Network (FDCAN) RM0433 error frames, or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters (ECR.REC, ECR.TEC) are frozen while Error Logging (ECR.CEL) is active. The software can set the FDCAN into Restricted Operation mode by setting bit CCCR.ASM. The bit can only be set by software when both CCCR.CCE and CCCR.INIT are set to ‘1’. The bit can be cleared by software at any time. Restricted Operation Mode is automatically entered when the Tx Handler was not able to read data from the Message RAM in time. To leave Restricted Operation Mode, the software has to reset CCCR.ASM. The Restricted Operation Mode can be used in applications that adapt themselves to different CAN bit rates. In this case the application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. CCCR.ASM is also controlled by the Clock Calibration Unit. Wen the clock calibration process is enabled, the Restricted Operation Mode is entered and the CCR.ASM bit is set. Once the calibration is completed, CCR.ASM bit is cleared. Note: The Restricted Operation Mode must not be combined with the Loop Back mode (internal or external). Bus Monitoring mode The FDCAN is set in Bus Monitoring Mode by setting CCCR.MON bit or when error level S3 (TTOST[EL] = ‘11’) is entered. In Bus Monitoring Mode (For more details please refer to ISO11898-1, 10.12 Bus monitoring), the FDCAN is able to receive valid data frames and valid remote frames, but cannot start a transmission. In this mode, it sends only recessive bits on the CAN bus, if the FDCAN is required to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the FDCAN monitors this dominant bit, although the CAN bus may remain in recessive state. In Bus Monitoring Mode register TXBRP is held in reset state. The Bus Monitoring Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits. Figure 726 shows the connection of FDCAN_TX and FDCAN_RX signals to the FDCAN in Bus Monitoring Mode. Figure 726. Pin control in Bus Monitoring mode )'&$1B7; )'&$1B5; 7[ 5[ )'&$1 069 2378/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Disabled Automatic Retransmission (DAR) mode According to the CAN Specification (see ISO11898-1, 6.3.3 Recovery Management), the FDCAN provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission. By default automatic retransmission is enabled. To support time-triggered communication as described in ISO 11898-1: 2015, chapter 9.2, the automatic retransmission may be disabled via CCCR[DAR]. Frame transmission in Disabled Automatic Retransmission (DAR) mode In DAR mode all transmissions are automatically canceled after they started on the CAN bus. A Tx Buffer Tx Request Pending bit TXBRP.TRPx is reset after successful transmission, when a transmission has not yet been started at the point of cancellation, has been aborted due to lost arbitration, or when an error occurred during frame transmission. • • • Successful transmission: – Corresponding Tx Buffer Transmission Occurred bit TXBTO[TOx] set – Corresponding Tx Buffer Cancellation Finished bit TXBCF[CFx] not set Successful transmission in spite of cancellation: – Corresponding Tx Buffer Transmission Occurred bit TXBTO[TOx] set – Corresponding Tx Buffer Cancellation Finished bit TXBCF[CFx] set Arbitration loss or frame transmission disturbed: – Corresponding Tx Buffer Transmission Occurred bit TXBTO[TOx] not set – Corresponding Tx Buffer Cancellation Finished bit TXBCF[CFx] set In case of a successful frame transmission, and if storage of Tx events is enabled, a Tx Event FIFO element is written with Event Type ET = ‘10’ (transmission in spite of cancellation). Power down (Sleep mode) The FDCAN can be set into power down mode controlled by clock stop request input via CC Control Register CCCR[CSR]. As long as the clock stop request is active, bit CCCR[CSR] is read as one. When all pending transmission requests have completed, the FDCAN waits until bus idle state is detected. Then the FDCAN sets then CCCR[INIT] to 1 to prevent any further CAN transfers. Now the FDCAN acknowledges that it is ready for power down by setting CCCR[CSA] to 1. In this state, before the clocks are switched off, further register accesses can be made. A write access to CCCR[INIT] will have no effect. Now the module clock inputs may be switched off. To leave power down mode, the application has to turn on the module clocks before resetting CC Control Register flag CCCR.CSR. The FDCAN will acknowledge this by resetting CCCR[CSA]. Afterwards, the application can restart CAN communication by resetting bit CCCR[INIT]. Test modes To enable write access to FDCAN Test Register (see Section 56.4.4 on page 2433), bit CCCR.TEST has to be set to 1, thus enabling the configuration of test modes and functions. DocID029587 Rev 3 2379/3178 2501 FD Controller Area Network (FDCAN) RM0433 Four output functions are available for the CAN transmit pin m_can_tx by programming TEST.TX. Additionally to its default function – the serial data output – it can drive the CAN Sample Point signal to monitor the FDCAN bit timing and it can drive constant dominant or recessive values. The actual value at pin m_can_rx can be read from TEST.RX. Both functions can be used to check the CAN bus physical layer. Due to the synchronization mechanism between CAN kernel clock and APB clock domain, there may be a delay of several APB clock periods between writing to TEST.TX until the new configuration is visible at FDCAN_TX output pin. This applies also when reading FDCAN_RX input pin via TEST.RX. Note: Test modes should be used for production tests or self test only. The software control for FDCAN_TX pin interferes with all CAN protocol functions. It is not recommended to use test modes for application. External Loop Back mode The FDCAN can be set in External Loop Back mode by programming TEST.LBCK to 1. In Loop Back mode, the FDCAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into Rx FIFOs. Figure 727 shows the connection of transmit and receive signals FDCAN_TX and FDCAN_RX to the FDCAN in External Loop Back mode. This mode is provided for hardware self-test. To be independent from external stimulation, the FDCAN ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop Back mode. In this mode the FDCAN performs an internal feedback from its transmit output to its receive input. The actual value of the FDCAN_RX input pin is disregarded by the FDCAN. The transmitted messages can be monitored at the FDCAN_TX transmit pin. Internal Loop Back mode Internal Loop Back mode is entered by programming bits TEST.LBCK and CCCR.MON to 1. This mode can be used for a “Hot Selftest”, meaning the FDCAN can be tested without affecting a running CAN system connected to the FDCAN_TX and FDCAN_RX pins. In this mode, FDCAN_RX pin is disconnected from the FDCAN and FDCAN_TX pin is held recessive. Figure 727 shows the connection of FDCAN_TX and FDCAN_RX pins to the FDCAN in case of Internal Loop Back mode. 2380/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Figure 727. Pin control in Loop Back mode )'&$1[B7[ )'&$1B5[ )'&$1[B7[ )'&$1B5[ 7[ 5[ )'&$1 7[ 5[ )'&$1 ([WHUQDO/RRS%DFNPRGH ,QWHUQDO/RRS%DFNPRGH 069 Application watchdog (FDCAN1 only) The application watchdog is served by reading register TTOST. When the application watchdog is not served in time, bit TTOST.AWE is set, all TTCAN communication is stopped, and the FDCAN1 is set into Bus Monitoring Mode. The TT Application Watchdog can be disabled by programming the Application Watchdog Limit TTOCF[AWL] to 0x00. The TT Application Watchdog should not be disabled in a TTCAN application program Timestamp generation For timestamp generation the FDCAN supplies a 16-bit wrap-around counter. A prescaler TSCC.TCP can be configured to clock the counter in multiples of CAN bit times (1…16). The counter is readable via TSCV[TCV]. A write access to register TSCV resets the counter to 0. When the timestamp counter wraps around interrupt flag IR[TSW] is set. On start of frame reception/transmission the counter value is captured and stored into the timestamp section of a Rx Buffer/Rx FIFO (RXTS[15:0]) or Tx Event FIFO (TXTS[15:0]) element. By programming bit TSCC.TSS, a 16-bit timestamp can be used. Timeout counter To signal timeout conditions for Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO the FDCAN supplies a 16-bit Timeout Counter. It operates as down-counter and uses the same prescaler controlled by TSCC[TCP] as the Timestamp Counter. The Timeout Counter is configured via register TOCC. The actual counter value can be read from TOCV[TOC]. The Timeout Counter can only be started while CCCR[INIT] = ‘0’. It is stopped when CCCR[INIT] = ‘1’, e.g. when the FDCAN enters Bus_Off state. The operation mode is selected by TOCC[TOS]. When operating in Continuous mode, the counter starts when CCCR[INIT] is reset. A write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. DocID029587 Rev 3 2381/3178 2501 FD Controller Area Network (FDCAN) RM0433 When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. Writing to TOCV has no effect. When the counter reaches 0, interrupt flag IR[TOO] is set. In Continuous mode, the counter is immediately restarted at TOCC[TOP]. Note: The clock signal for the Timeout Counter is derived from the CAN core sample point signal. Therefore the point in time where the Timeout Counter is decremented may vary due to the synchronization/re-synchronization mechanism of the CAN core. If the baud rate switch feature in FDCAN is used, the timeout counter is clocked differently in arbitration and data fields. 56.3.2 Message RAM The Message RAM has a width of 32 bits. The FDCAN module can be configured to allocate up to 2560 words in the Message RAM. It is not necessary to configure each of the sections listed in Figure 728, nor is there any restriction with respect to the sequence of the sections. Figure 728. Message RAM configuration 6WDUWDGGUHVV 6,')&)/66$ ;,')&)/(6$ 5;)&)6$ 5;%&5%6$ 7;()&()6$ 7;%&7%6$ 70&706$ HOHPHQWVZRUGV ELWILOWHU HOHPHQWVZRUGV 5[),)2 HOHPHQWVZRUGV 5[),)2 HOHPHQWVZRUGV 5[EXIIHU HOHPHQWVZRUGV 7[HYHQW),)2 HOHPHQWVZRUGV 7[EXIIHUV HOHPHQWVZRUGV 7ULJJHUPHPRU\ HOHPHQWVZRUGV ELWV 0D[ZRUGV 5;)&)6$ ELWILOWHU 069 When the FDCAN addresses the Message RAM it addresses 32-bit words, not single bytes. The configured start addresses are 32-bit word addresses, i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. Note: 2382/3178 The FDCAN does not check for erroneous configuration of the Message RAM. Especially the configuration of the start addresses of the different sections and the number of elements of each section has to be done carefully to avoid falsification or loss of data. DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Rx handling The Rx Handler controls the acceptance filtering, the transfer of received messages to Rx Buffers or to 1 of the two Rx FIFOs, as well as the Rx FIFO Put and Get Indices. Acceptance filter The FDCAN offers the possibility to configure two sets of acceptance filters, one for standard identifiers and one for extended identifiers. These filters can be assigned to Rx buffer, Rx FIFO 0 or Rx FIFO 1. For acceptance filtering each list of filters is executed from element #0 until the first matching element. Acceptance filtering stops at the first matching element. The following filter elements are not evaluated for this message. The main features are: • Each filter element can be configured as – range filter (from - to) – filter for one or two dedicated IDs – classic bit mask filter • Each filter element is configurable for acceptance or rejection filtering • Each filter element can be enabled/disabled individually • Filters are checked sequentially, execution stops with the first matching filter element Related configuration registers are: • Global Filter Configuration (GFC) • Standard ID Filter Configuration (SIDFC) • Extended ID Filter Configuration (XIDFC) • Extended ID AND Mask (XIDAM) Depending on the configuration of the filter element (SFEC/EFEC) a match triggers one of the following actions: • Store received frame in FIFO 0 or FIFO 1 • Store received frame in Rx Buffer • Store received frame in Rx Buffer and generate pulse at filter event pin • Reject received frame • Set High Priority Message interrupt flag IR[HPM] • Set High Priority Message interrupt flag IR[HPM] and store received frame in FIFO 0 or FIFO 1. • Set High Priority Message interrupt flag IR.HPM and store received frame in FIFO 0 or FIFO 1 Acceptance filtering is started after the complete identifier has been received. After acceptance filtering has completed, and if a matching Rx Buffer or Rx FIFO has been found, the Message Handler starts writing the received message data in portions of 32 bit to the matching Rx Buffer or Rx FIFO. If the CAN protocol controller has detected an error condition (e.g. CRC error), this message is discarded with the following impact: • Rx Buffer New Data flag of matching Rx Buffer is not set, but Rx Buffer (partly) overwritten with received data. For error type see PSR.LEC and PSR.DLEC. • Rx FIFO Put index of matching Rx FIFO is not updated, but related Rx FIFO element (partly) DocID029587 Rev 3 2383/3178 2501 FD Controller Area Network (FDCAN) RM0433 overwritten with received data. For error type see PSR.LEC and PSR.DLEC. In case the matching Rx FIFO is operated in overwrite mode, the boundary conditions described in Rx FIFO Overwrite Mode have to be considered. Note: When an accepted message is written to one of the two Rx FIFOs, or into an Rx Buffer, the unmodified received identifier is stored independent of the filter(s) used. The result of the acceptance filter process is strongly depending on the sequence of configured filter elements. Range filter The filter matches for all received frames with Message IDs in the range defined by SF1ID/SF2ID and EF1ID/EF2ID. There are two possibilities when range filtering is used together with extended frames: • EFT = ‘00’: The Message ID of received frames is AND-ed with the Extended ID AND Mask (XIDAM) before the range filter is applied • EFT = ‘11’: The Extended ID AND Mask (XIDAM) is not used for range filtering Filter for dedicated IDs A filter element can be configured to filter for one or two specific Message IDs. To filter for one specific Message ID, the filter element has to be configured with SF1ID=SF2ID and EF1ID=EF2ID. Classic bit mask filter Classic bit mask filtering is intended to filter groups of Message IDs by masking single bits of a received Message ID. With classic bit mask filtering SF1ID/EF1ID is used as Message ID filter, while SF2ID/EF2ID is used as filter mask. A 0 bit at the filter mask will mask out the corresponding bit position of the configured ID filter, e.g. the value of the received Message ID at that bit position is not relevant for acceptance filtering. Only those bits of the received Message ID where the corresponding mask bits are one are relevant for acceptance filtering. In case all mask bits are one, a match occurs only when the received Message ID and the Message ID filter are identical. If all mask bits are 0, all Message IDs match. 2384/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Standard message ID filtering Figure 729 shows the flow for standard Message ID (11-bit Identifier) filtering. The Standard Message ID filter element is described in Section 56.3.19 on page 2426. Figure 729. Standard Message ID filter path valid frame received 11 bit 29 bit 11 / 29 bit identifier yes reject remote frames remote frame no GFC[RRFS] = ‘1’ GFC[RRFS] = ‘0’ receive filter list enabled SIDFC[LSS[7:0]] = 0 SIDFC[LSS[7:0]] > 0 yes match filter element #0 no reject match filter element #SIDFC.LSS yes acceptance/rejection no accept non-matching frames accept GFC[ANFS[1]] = ‘1’ discard frame GFC[ANFS[1]] = ‘0’ target FIFO full yes no append to target FIFO Controlled by the Global Filter Configuration (GFC) and the Standard ID Filter Configuration (SIDFC) Message ID, Remote Transmission Request bit (RTR), and the Identifier Extension bit (IDE) of received frames are compared against the list of configured filter elements. DocID029587 Rev 3 2385/3178 2501 FD Controller Area Network (FDCAN) RM0433 Extended message ID filtering Figure 730 shows the flow for extended Message ID (29-bit Identifier) filtering. The Extended Message ID filter element is described in Section 56.3.20 on page 2428. Figure 730. Extended Message ID filter path valid frame received 11 bit GFC[RRFE] = ‘1’ 11 / 29 bit identifier 29 bit yes reject remote frames remote frame no GFC[RRFE] = ‘0’ receive filter list enabled XIDFC[LSE[6:0]] > 0 match filter element #0 no reject acceptance/rejection match filter element #XIDFC.LSE yes accept no GFC[ANFE[1]] = ‘1’ discard frame XIDFC[LSE[6:0]] = 0 yes accept non-matching frames GFC[ANFE[1]] = ‘0’ yes target FIFO full no append to target FIFO Controlled by the Global Filter Configuration GFC and the Extended ID Filter Configuration XIDFC Message ID, Remote Transmission Request bit (RTR), and the Identifier Extension bit (IDE) of received frames are compared against the list of configured filter elements. The Extended ID AND Mask (XIDAM) is AND-ed with the received identifier before the filter list is executed. 2386/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Rx FIFOs Rx FIFO 0 and Rx FIFO 1 can be configured to hold up to 64 elements each. Configuration of the two Rx FIFOs is done via registers RXF0C and RXF1C. Received messages that passed acceptance filtering are transferred to the Rx FIFO as configured by the matching filter element. For a description of the filter mechanisms available for Rx FIFO 0 and Rx FIFO 1, see Acceptance filter. The Rx buffer and FIFO element is described in Section 56.3.16: FDCAN Rx Buffer and FIFO element. When an Rx FIFO full condition is signaled by IR[RFnF], no further messages are written to the corresponding Rx FIFO until at least one message has been read out and the Rx FIFO Get Index has been incremented. In case a message is received while the corresponding Rx FIFO is full, this message is discarded and interrupt flag IR[RFnL] is set. To avoid an Rx FIFO overflow, the Rx FIFO watermark can be used. When the Rx FIFO fill level reaches the Rx FIFO watermark configured by RXFnC[FnWM], interrupt flag IR[RFnW] is set. When reading from an Rx FIFO, Rx FIFO Get Index RXFnS[FnGI] + FIFO Element Size has to be added to the corresponding Rx FIFO start address RXFnC[FnSA]. Rx FIFO Blocking Mode The Rx FIFO blocking mode is configured by RXFnC.FnOM = ‘0’. This is the default operation mode for the Rx FIFOs. When an Rx FIFO full condition is reached (RXFnS.FnPI = RXFnS.FnGI), no further messages are written to the corresponding Rx FIFO until at least one message has been read out and the Rx FIFO Get Index has been incremented. An Rx FIFO full condition is signaled by RXFnS.FnF = ‘1’. In addition interrupt flag IR.RFnF is set. In case a message is received while the corresponding Rx FIFO is full, this message is discarded and the message lost condition is signaled by RXFnS.RFnL = ‘1’. In addition interrupt flag IR.RFnL is set. Rx FIFO Overwrite Mode The Rx FIFO overwrite mode is configured by RXFnC.FnOM = ‘1’. When an Rx FIFO full condition (RXFnS.FnPI = RXFnS.FnGI) is signaled by RXFnS.FnF = ‘1’, the next message accepted for the FIFO will overwrite the oldest FIFO message. Put and get index are both incremented by one. When an Rx FIFO is operated in overwrite mode and an Rx FIFO full condition is signaled, reading of the Rx FIFO elements should start at least at get index + 1. The reason for that is that it can happen that a received message is written to the Message RAM (put index) while the CPU is reading from the Message RAM (get index). In this case inconsistent data may be read from the respective Rx FIFO element. Adding an offset to the get index when reading from the Rx FIFO avoids this problem. The offset depends on how fast the CPU accesses the Rx FIFO. Figure 732: Example of mixed Configuration Dedicated Tx Buffers / Tx Queue shows an offset of two with respect to the get index when reading the Rx FIFO. In this case the two messages stored in elements 1 and 2 are lost. After reading from the Rx FIFO, the number of the last element read has to be written to the Rx FIFO Acknowledge Index RXFnA.FnA. This increments the get index to that element number. In case the put index has not been incremented to this Rx FIFO element, the Rx FIFO full condition is reset (RXFnS.FnF = ‘0’). DocID029587 Rev 3 2387/3178 2501 FD Controller Area Network (FDCAN) RM0433 Dedicated Rx Buffers The FDCAN supports up to 64 dedicated Rx Buffers. The start address of the dedicated Rx Buffer section is configured via RXBC.RBSA. For each Rx Buffer a Standard or Extended Message ID Filter Element with SFEC/EFEC=‘111’ and SFID2/EFID2[10:9]=‘00’ has to be configured (see Section 56.3.19: FDCAN Standard message ID Filter element and Section 56.3.20: FDCAN Extended message ID filter element). After a received message has been accepted by a filter element, the message is stored into the Rx Buffer in the Message RAM referenced by the filter element. The format is the same as for an Rx FIFO element. In addition the flag IR.DRX (Message stored in Dedicated Rx Buffer) in the interrupt register is set. Table 453. Example of filter configuration for Rx Buffers SFID1[10:0] SFID2[10:9] SFID2[5:0] EFID1[28:0] EFID2[10:9] EFID2[5:0] 0 ID message 1 00 00 0000 1 ID message 2 00 00 0001 2 ID message 3 00 00 0010 Filter element After the last word of a matching received message has been written to the Message RAM, the respective New Data flag in register NDAT1,2 is set. As long as the New Data flag is set, the respective Rx Buffer is locked against updates from received matching frames. The New Data flags have to be reset by the Host by writing a ‘1’ to the respective bit position. While an Rx Buffer New Data flag is set, a Message ID filter element referencing this specific Rx Buffer will not match, causing the acceptance filtering to continue. The following Message ID filter elements may cause the received message to be stored into another Rx Buffer, or into an Rx FIFO, or the message may be rejected, depending on filter configuration. Rx Buffer Handling • Reset interrupt flag IR.DRX • Read New Data registers • Read messages from Message RAM • Reset New Data flags of processed messages Filtering for Debug messages Filtering for debug messages is done by configuring one Standard/Extended Message ID Filter Element for each of the three debug messages. To enable a filter element to filter for debug messages SFEC/EFEC has to be programmed to ‘111’. In this case fields SFID1/SFID2 and EFID1/EFID2 have a different meaning. While SFID2/EFID2[10:9] controls the debug message handling state machine, SFID2/EFID2[5:0] controls the location for storage of a received debug message. When a debug message is stored, neither the respective New Data flag nor IR.DRX are set. The reception of debug messages can be monitored via RXF1S.DMS. 2388/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 454. Example of filter configuration for Debug messages SFID1[10:0] SFID2[10:9] SFID2[5:0] EFID1[28:0] EFID2[10:9] EFID2[5:0] 0 ID debug message A 01 11 1101 1 ID debug message B 10 11 1110 2 ID debug message C 11 11 1111 Filter element Tx handling The Tx Handler handles transmission requests for the dedicated Tx Buffers, the Tx FIFO, and the Tx Queue. It controls the transfer of transmit messages to the CAN core, the Put and Get Indices, and the Tx Event FIFO.Up to 32 Tx Buffers can be set up for message transmission (see Dedicated Tx buffers). Depending on the configuration of the element size (RXESC), between two and sixteen 32-bit words (Rn = 3 ..17) are used for storage of a CAN message data field. Table 455. Possible configurations for Frame transmission CCCR Tx Buffer element Frame transmission Note: BRSE FDOE FDF BRS Ignored 0 Ignored Ignored Classic CAN 0 1 0 Ignored Classic CAN 0 1 1 Ignored FD without bit rate switching 1 1 0 Ignored Classic CAN 1 1 1 0 FD without bit rate switching 1 1 1 1 FD with bit rate switching AUTOSAR requires at least three Tx Queue Buffers and support of transmit cancellation. The Tx Handler starts a Tx scan to check for the highest priority pending Tx request (Tx Buffer with lowest Message ID) when the Tx Buffer Request Pending register TXBRP is updated, or when a transmission has been started. Transmit Pause The transmit pause feature is intended for use in CAN systems where the CAN message identifiers are (permanently) specified to specific values and cannot easily be changed. These message identifiers may have a higher CAN arbitration priority than other defined messages, while in a specific application their relative arbitration priority should be inverse. This may lead to a case where one ECU sends a burst of CAN messages that cause another ECU CAN messages to be delayed because that other messages have a lower CAN arbitration priority. If, as an example, CAN ECU-1 has the feature enabled and is requested by its application software to transmit four messages, it will, after the first successful message transmission, wait for two CAN bit times of bus idle before it is allowed to start the next requested DocID029587 Rev 3 2389/3178 2501 FD Controller Area Network (FDCAN) RM0433 message. If there are other ECUs with pending messages, those messages are started in the idle time, they would not need to arbitrate with the next message of ECU-1. After having received a message, ECU-1 is allowed to start its next transmission as soon as the received message releases the CAN bus. The feature is controlled by TXP bit in CCCR register. If the bit is set, the FDCAN will, each time it has successfully transmitted a message, pause for two CAN bit times before starting the next transmission. This enables other CAN nodes in the network to transmit messages even if their messages have lower prior identifiers. Default is disabled (CCCR.TXP = ‘0’). This feature looses up burst transmissions coming from a single node and it protects against "babbling idiot" scenarios where the application program erroneously requests too many transmissions. Dedicated Tx buffers Dedicated Tx Buffers are intended for message transmission under complete control of the CPU. Each Dedicated Tx Buffer is configured with a specific Message ID. In case that multiple Tx Buffers are configured with the same Message ID, the Tx Buffer with the lowest buffer number is transmitted first. If the data section has been updated, a transmission is requested by an Add Request via TXBAR[ARn]. The requested messages arbitrate internally with messages from an optional Tx FIFO or Tx Queue and externally with messages on the CAN bus, and are sent out according to their Message ID. A Dedicated Tx Buffer allocates four 32-bit words in the Message RAM. Therefore the start address of a Dedicated Tx Buffer in the Message RAM is calculated by adding four times the transmit buffer index (0…31) to the Tx Buffer Start Address TXBC[TBSA]. Table 456. Tx Buffer/FIFO - Queue element size TXESC, TBDS[2;0] Data field (bytes) Element size (RAM words) 000 8 4 001 12 5 010 16 6 011 20 7 100 24 8 101 32 10 110 48 14 111 64 18 Tx FIFO Tx FIFO operation is configured by programming TXBC[TFQM] to ‘0’. Messages stored in the Tx FIFO are transmitted starting with the message referenced by the Get Index TXFQS[TFGI]. After each transmission the Get Index is incremented cyclically until the Tx FIFO is empty. The Tx FIFO enables transmission of messages with the same Message ID from different Tx Buffers in the order these messages have been written to the Tx FIFO. The FDCAN calculates the Tx FIFO Free Level TXFQS[TFFL] as difference between Get and Put Index. It indicates the number of available (free) Tx FIFO elements. 2390/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) New transmit messages have to be written to the Tx FIFO starting with the Tx Buffer referenced by the Put Index TXFQS[TFQPI]. An Add Request increments the Put Index to the next free Tx FIFO element. When the Put Index reaches the Get Index, Tx FIFO Full (TXFQS[TFQF]= ‘1’) is signaled. In this case no further messages should be written to the Tx FIFO until the next message has been transmitted and the Get Index has been incremented. When a single message is added to the Tx FIFO, the transmission is requested by writing a ‘1’ to the TXBAR bit related to the Tx Buffer referenced by the Tx FIFO Put Index. When multiple (n) messages are added to the Tx FIFO, they are written to n consecutive Tx Buffers starting with the Put Index. The transmissions are then requested via TXBAR. The Put Index is then cyclically incremented by n. The number of requested Tx buffers should not exceed the number of free Tx Buffers as indicated by the Tx FIFO Free Level. When a transmission request for the Tx Buffer referenced by the Get Index is canceled, the Get Index is incremented to the next Tx Buffer with pending transmission request and the Tx FIFO Free Level is recalculated. When transmission cancellation is applied to any other Tx Buffer, the Get Index and the FIFO Free Level remain unchanged. A Tx FIFO element allocates four 32-bit words in the Message RAM. Therefore the start address of the next available (free) Tx FIFO Buffer is calculated by adding four times the Put Index TXFQS[TFQPI] (0…31) to the Tx Buffer Start Address TXBC[TBSA]. Tx Queue Tx Queue operation is configured by programming TXBC[TFQM] to ‘1’. Messages stored in the Tx Queue are transmitted starting with the message with the lowest Message ID (highest priority). In case that multiple Queue Buffers are configured with the same Message ID, the Queue Buffer with the lowest buffer number is transmitted first. New messages have to be written to the Tx Buffer referenced by the Put Index TXFQS[TFQPI]. An Add Request cyclically increments the Put Index to the next free Tx Buffer. In case that the Tx Queue is full (TXFQS[TFQF]= ‘1’), the Put Index is not valid and no further message should be written to the Tx Queue until at least one of the requested messages has been sent out or a pending transmission request has been canceled. The application may use register TXBRP instead of the Put Index and may place messages to any Tx Buffer without pending transmission request. A Tx Queue Buffer allocates four 32-bit words in the Message RAM. Therefore the start address of the next available (free) Tx Queue Buffer is calculated by adding four times the Tx Queue Put Index TXFQS[TFQPI] (0…31) to the Tx Buffer Start Address TXBC[TBSA]. Mixed dedicated Tx Buffers / Tx FIFO In this case the Tx Buffers section in the Message RAM is subdivided into a set of Dedicated Tx Buffers and a Tx FIFO. The number of Dedicated Tx Buffers is configured by TXBC[NDTB]. The number of Tx Buffers assigned to the Tx FIFO is configured by TXBC[TFQS]. In case, TXBC[TFQS] is programmed to 0, only Dedicated Tx Buffers are used. DocID029587 Rev 3 2391/3178 2501 FD Controller Area Network (FDCAN) RM0433 Figure 731. Example of mixed Configuration Dedicated Tx Buffers / Tx FIFO 'HGLFDWHG7[%XIIHUV %XIIHULQGH[ 7[VHTXHQFH ,' 7[),)2 ,' ,' ,' ,' ,' 3XW LQGH[ *HW LQGH[ 069 Tx prioritization: • Scan Dedicated Tx Buffers and oldest pending Tx FIFO Buffer (referenced by TXFS[TFGI]) • Buffer with lowest Message ID gets highest priority and is transmitted next Mixed dedicated Tx Buffers / Tx Queue In this case the Tx Buffers section in the Message RAM is subdivided into a set of Dedicated Tx Buffers and a Tx Queue. The number of Dedicated Tx Buffers is configured by TXBC[NDTB]. The number of Tx Queue Buffers is configured by TXBC[TFQS]. In case TXBC[TFQS] is programmed to 0, only dedicated Tx Buffers are used. Figure 732. Example of mixed Configuration Dedicated Tx Buffers / Tx Queue 'HGLFDWHG7[%XIIHUV %XIIHULQGH[ 7[VHTXHQFH ,' 7[4XHXH ,' ,' ,' ,' ,' *HW LQGH[ 3XW LQGH[ 069 Tx priority setting: • Scan all Tx Buffers with activated transmission request • Tx Buffer with lowest Message ID gets highest priority and is transmitted next Transmit cancellation The FDCAN supports transmit cancellation. To cancel a requested transmission from a dedicated Tx Buffer or a Tx Queue Buffer the Host has to write a ‘1’ to the corresponding bit 2392/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) position (=number of Tx Buffer) of register TXBCR. Transmit cancellation is not intended for Tx FIFO operation. Successful cancellation is signaled by setting the corresponding bit of register TXBCF to ‘1’. In case a transmit cancellation is requested while a transmission from a Tx Buffer is already ongoing, the corresponding TXBRP bit remains set as long as the transmission is in progress. If the transmission was successful, the corresponding TXBTO and TXBCF bits are set. If the transmission was not successful, it is not repeated and only the corresponding TXBCF bit is set. Note: In case a pending transmission is canceled immediately before this transmission could have been started, there follows a short time window where no transmission is stared even if another message is pending in this node. This may enable another node to transmit a message that may have a priority lower than that of the second message in this node. Tx Event handling To support Tx event handling the FDCAN has implemented a Tx Event FIFO. After the FDCAN has transmitted a message on the CAN bus, Message ID and timestamp are stored in a Tx Event FIFO element. To link a Tx event to a Tx Event FIFO element, the Message Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element. The Tx Event FIFO can be configured to a maximum of 32 elements. The Tx Event FIFO element is described in Tx FIFO. Depending on the configuration of the element size (TXESC), between two and sixteen 32-bit words (Tn = 3 ..17) are used for storage of a CAN message data field. The purpose of the Tx Event FIFO is to decouple handling transmit status information from transmit message handling i.e. a Tx Buffer holds only the message to be transmitted, while the transmit status is stored separately in the Tx Event FIFO. This has the advantage, especially when operating a dynamically managed transmit queue, that a Tx Buffer can be used for a new message immediately after successful transmission. There is no need to save transmit status information from a Tx Buffer before overwriting that Tx Buffer. When a Tx Event FIFO full condition is signaled by IR[TEFF], no further elements are written to the Tx Event FIFO until at least one element has been read out and the Tx Event FIFO Get Index has been incremented. In case a Tx event occurs while the Tx Event FIFO is full, this event is discarded and interrupt flag IR[TEFL] is set. To avoid a Tx Event FIFO overflow, the Tx Event FIFO watermark can be used. When the Tx Event FIFO fill level reaches the Tx Event FIFO watermark configured by TXEFC[EFWM], interrupt flag IR[TEFW] is set. When reading from the Tx Event FIFO, two times the Tx Event FIFO Get Index TXEFS[EFGI] has to be added to the Tx Event FIFO start address TXEFC[EFSA]. 56.3.3 FIFO acknowledge handling The Get Indices of Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO are controlled by writing to the corresponding FIFO Acknowledge Index, see Section 56.4.28: FDCAN Rx FIFO 0 Acknowledge Register (FDCAN_RXF0A), Section 56.4.32: FDCAN Rx FIFO 1 Acknowledge Register (FDCAN_RXF1A), and Section 56.4.44: FDCAN Tx Event FIFO Configuration Register (FDCAN_TXEFC). Writing to the FIFO Acknowledge Index will set the FIFO Get Index to the FIFO Acknowledge Index plus one and thereby updates the FIFO Fill Level. There are two use cases: DocID029587 Rev 3 2393/3178 2501 FD Controller Area Network (FDCAN) RM0433 1. When only a single element has been read from the FIFO (the one being pointed to by the Get Index), this Get Index value is written to the FIFO Acknowledge Index. 2. When a sequence of elements has been read from the FIFO, it is sufficient to write the FIFO Acknowledge Index only once at the end of that read sequence (value: Index of the last element read), to update the FIFO Get Index. Due to the fact that the CPU has free access to the FDCAN Message RAM, special care has to be taken when reading FIFO elements in an arbitrary order (Get Index not considered). This might be useful when reading a High Priority Message from one of the two Rx FIFOs. In this case the FIFO Acknowledge Index should not be written because this would set the Get Index to a wrong position and also alters the FIFO Fill Level. In this case some of the older FIFO elements would be lost. Note: The application has to ensure that a valid value is written to the FIFO Acknowledge Index. The FDCAN does not check for erroneous values. 56.3.4 Clock calibration on CAN After device reset the Clock Calibration Unit (CCU) does not provide a valid clock signal to the FDCAN1 and FDCAN2. The CCU has to be initialized via CCFG register. The CCFG register can be written only when FDCAN1 has both CCCR.CCE and CCCR.INIT bits set. In consequence the CCU and the FDCAN1 initialization needs to be completed before any FDCAN1 and/or FDCAN2 module can operate. Clock calibration is bypassed when CCFG.BCC = ‘1’ (see Figure 733). Figure 733. Bypass operation ELW$3%EXV IGFDQBNHUBFN &&)*&',9 &&)*%&& &ORFN &DOLEUDWLRQ 8QLW &&8 &DOLEUDWLRQ IGFDQBWTBFN IGFDQBSFON 069 Operating Conditions The Clock Calibration on CAN unit is designed to operate under the following conditions: • a CAN kernel clock frequency fdcan_ker_ck between 80 and 500 MHz • FDCAN bit rates between 125 kbit/s and 1 Mbit/s The Clock Calibration on FDCAN unit generates a calibrated time quanta clock fdcan_tq_ck in the range from 0.5 to 25 MHz. Note: 2394/3178 The FDCAN requires that the CAN time quanta clock is always below or equal to the APB clock (fdcan_tq_ck < fdcan_pclk). This has to be considered when the Clock Calibration on CAN unit is bypassed (CCFG.BCC = ‘1’). DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Calibration Accuracy The calibration accuracy in state Precision_Calibrated depends upon the factors listed below. • Dynamic clock tolerance at the CAN kernel clock input fdcan_ker_ck • Measurement error. For each bit sequence used for calibration measurement, there is a maximum error of one fdcan_pclk period. The number of bits used for measurement of the bit time is 32 or 64-bit, depending on configuration of CCFG.CFL. • Tolerable error in calibration mechanism The distance between two calibration messages has to be chosen to fit the clock tolerance requirements of the FDCAN1 module. Note: Dynamic clock tolerance is the clock frequency variation between two calibration messages e.g. caused by change of temperature or operating voltage. Functional Description Calibration of the time quanta clock fdcan_tq_ck via CAN messages is performed by adapting a clock divider that generates the CAN protocol time quantum tq from the clock fdcan_ker_ck. 1. First step: Basic Calibration The minimum distance between two edges from recessive to dominant is measured, this time to be assumed two CAN bit times, counted in PLL clock periods. The clock divider is updated each time a new measurement finds a smaller distance between edges. Basic calibration is achieved when the CAN protocol controller detects a valid CAN message. 2. Second step: Precision Calibration The calibration state machine measures the length of a longer bit sequence inside a CAN frame by counting the number of fdcan_ker_ck periods. The length of this bit sequence can be configured to 32 or 64 bits via CCFG.CLF. For a calibration field length of 32/64 bit a calibration message with at least 2/6 byte data field is required. Precision calibration is based on the new clock divider value calculated from the measurement of the longer bit sequence. DocID029587 Rev 3 2395/3178 2501 FD Controller Area Network (FDCAN) RM0433 Figure 734. FSM calibration +:UHVHW 7 7 1RWB&DOLEUDWHG &$/6 7 7 7 3UHFLVLRQB&DOLEUDWHG &$/6 7 7 7 %DVLFB&DOLEUDWHG &$/6 7 7 +:UHVHW 7 &KHFNIRUPLQLPXP 7 0HVVDJHUHFHLYHG 7 (YDOXDWHPHVVDJHV 7 4XDUW]PHVVDJHUHFHLYHG 7 (YDOXDWHTXDUW]PHVVDJHV 7 &RQILJXUDWLRQFKDQJHHQDEOHG 7 :DWFKGRJHYHQW QRTXDUW]PHVVDJHUHFHLYHG 7 :DWFKGRJHYHQW QRTXDUW]PHVVDJH UHFHLYHGRUFRQILJXUDWLRQFKDQJHHQDEOHG 06 9 A change of the calibration state also sets interrupt flag CUIR.CSC. If enabled by CUIE.CSCE, interrupt line cu_int is activated (set to high). Interrupt line cu_int remains active until interrupt flag CUIR.CSC is reset. Until precision calibration is achieved, FDCAN1 and FDCAN2 operate in a restricted mode (no frame transmission, no error or overload flag transmission, no error counting). In case calibration of the PLL is done by software by evaluating the calibration status from register CSTAT, FDCAN1 and FDCAN2 have to be set to Restricted Operation Mode (CCCR.ASM = ‘1’) until the Calibration on CAN unit is in state Precision_Calibrated (see Application). Precision calibration may be performed only on valid CAN frames transmitted by a node with a stable, quartz-controlled clock. Calibration frames are detected by the FDCAN1 acceptance filtering A filter element and a Rx Buffer have to be configured in the FDCAN1 to identify and store calibration messages. After reception of a calibration message the Rx Buffer new data flag has to be reset to enable signaling of the next calibration message. In case there is only one CAN transmitter with a quartz clock in the network, this node has to transmit its first message after startup with at least one ‘1010’ sequence in the data field or in the identifier. This assures that the non-quartz nodes can enter state Basic_Calibrated and then acknowledge the quartz node messages. Precision calibration must be repeated in predefined maximum intervals supervised by the calibration watchdog. Note: 2396/3178 When the Clock Calibration on CAN unit transits from state Precision_Calibrated back to Basic_Calibrated, the calibration OK signal is deasserted, the FDCAN1 complete ongoing transmissions, and then enter restricted operation (no frame transmission, no error or overload flag transmission, no error counting). DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Configuration The Clock Calibration on CAN Unit is configured via register CCFG, i.e. when FDCAN1 has CCCR.CCE and CCCR.INIT bits set. For basic calibration the minimum number of oscillator periods between two consecutive falling edges at pin FDCAN1_RX is measured. The number of clock periods depends on the clock frequency applied at input fdcan_ker_ck. In case the measured number of clock periods is below the minimum configured by CCFG.OCPM e.g. due to a glitch on FDCAN1_RX, the value is discarded and measurement continues. It is recommended to configure CCFG.OCPM slightly below two CAN bit times: CCFG.OCPM < ((2 x CAN bit time) / fdcan_ker_ck period) / 32 The length of the bit field used for precision calibration can be configured to 32 or 64 bits via CCFG.CFL. The number of bits used for precision calibration has an impact on calibration accuracy and the maximum distance between two calibration messages. The number of time quanta per bit time configured by CCFG.TQBT is used together with the measured number of oscillator clock periods CSTAT.OCPC to define the number of oscillator clocks per bit time. When the clock calibration is bypassed by configuring CCFG.BCC = ‘1’, the internal clock divider has to be configured via CCFG.CDIV to fulfill the condition fdcan_tq_ck < fdcan_pclk. Note: When clock calibration on CAN is active (CCFG.BCC = ‘0’), the baud rate prescalers of FDCAN1 and FDCAN2 have to be configured to inactive. Status signaling The status of the Clock Calibration on CAN Unit can be monitored by reading register CSTAT. When in state Precision_Calibrated the oscillator clock period counter CSTAT.OCPC signals the number of oscillator clock periods in the calibration field while CSTAT.TQC signals the number of time quanta in the calibration field. The calibration state is monitored by CSTAT.CALS. The duration of a cu_csc pulse is one cu_hclk period. A change of the calibration state also sets interrupt flag CUIR.CSC. If enabled by CUIE.CSCE, interrupt line cu_int is activated (set to high). Interrupt line cu_int remains active until interrupt flag CUIR.CSC is reset. A calibration watchdog event also sets interrupt flag CUIR.CWE. If enabled by CUIE.CWEE, interrupt line cu_int is activated (set to high). Interrupt line cu_int remains active until interrupt flag CUIR.CWE is reset Application Clock calibration bypassed The CCU internal clock divider is configured for division by one (CCFG.CDIV = “0000”). The CCU output signal cu_cok is fixed to ’1’. In this operation mode the input clock fdcan_ker_ck is directly routed to the clock output fdcan_tq_ck. In this case fdcan_tq_ck is independent of configuration and status of FDCAN1and FDCAN2 connected to the CCU. With a fdcan_ker_ck of 20/40/80MHz CAN FD operation is possible. Note: This is the default operation mode after reset in case the reset value of CCFG.BCC is configured to ‘1’ at synthesis via generic parameter. DocID029587 Rev 3 2397/3178 2501 FD Controller Area Network (FDCAN) RM0433 Software calibration The Clock Calibration on CAN unit also supports software calibration of fdcan_ker_ck by trimming of an on-chip oscillator. For calculation of the trimming values the Host has to read the CCU state from CSTAT. In this operation mode the CCU output signal cu_cok is fixed to ’1’, the clock from fdcan_ker_ck is routed to output fdcan_tq_ck (CCFG.BCC = ‘1’). The input clock fdcan_ker_ck must be in the range between 80MHz and 500 MHz. The clock divider of CCU has to be configured via CCFG.CDIV to bring fdcan_tq_ck to a valid range. All other configuration parameters have to be set via CCFG. For correct operation of tFDCAN1and FDCAN2, the APB clock fdcan_pclk needs to be equal or higher than the time quanta clock (fdcan_tq_ck). CAN FD operation is not possible. For startup FDCAN1 and FDCAN2 have to be both configured for Restricted Operation (CCCR.ASM = ‘1’) before CCCR.INIT is reset. The input clock fdcan_ker_ck has to be adjusted until the Clock Calibration on CAN unit has reached state Precision_Calibrated. Now the software can reset CCCR.ASM and the CANFD1 and CANFD2 can start normal operation. During operation the software has to check regularly whether the Clock Calibration on CAN unit is still in state Precision_Calibrated. In case the Clock Calibration on CAN unit has left state Precision_Calibrated due to drift of fdcan_ker_ck, FDCAN1 and FDCAN2 have to be set into Restricted Operation Mode by programming CCCR.INIT, CCCR.CCE, and CCCR.ASM to ‘1’. After fdcan_ker_ck has been adjusted successfully (Clock Calibration on CAN unit is in state Precision_Calibrated), FDCAN1 and FDCAN2 can resume normal operation. Note: Trimming accuracy needs to be to sufficient to meet the CAN clock tolerance requirements for the configured bit rate. Clock calibration active This operation mode is entered by resetting CCFG.BCC to ‘0’. In this operation mode the CCU output signals cu_cok and fdcan_ker_ck are controlled by the CCU. When the CCU is not in state Precision_Calibrated cu_cok is ‘0’. Generation of CCU output signals fdcan_tq_ck and cu_cok depends on the state of the FDCAN1. Input clock fdcan_ker_ck must be in the range between 80 and 500 MHz. Configuration of the CCU and FDCAN1 is required. CAN FD operation is not possible. In case FDCAN1 turns to Bus_Off or when its INIT bit is set by Host command (CCCR.INIT = ’1’), the CCU enters state Not_Calibrated and output cu_cok is reset to ’0’. CANFD1 and CANFD2 enter Restricted Operation Mode. Note: This is the default operation mode after reset in case the reset value of CCFG.BCC is configured to ‘0’ at synthesis via generic parameter. 56.3.5 TTCAN operations (FDCAN1 only) Reference message A reference message is a data frame characterized by a specific CAN identifier. It is received and accepted by all nodes except the Time Master (sender of the reference message). For Level 1 the data length must be at least one; for Level 0, 2 the data length must be at least four; otherwise, the message is not accepted as reference message. The reference 2398/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) message may be extended by other data up to the sum of eight CAN data bytes. All bits of the identifier except the three LSBs characterize the message as a reference message. The last three bits specify the priorities of up to eight potential time masters. Reserved bits are transmitted as logical 0 and are ignored by the receivers. The reference message is configured via register TTRMC. The time master transmits the reference message. If the reference message is disturbed by an error, it is retransmitted immediately. In case of a retransmission, the transmitted Master_Ref_Mark is updated. The reference message is sent periodically, but is allowed to stop the periodic transmission (Next_is_Gap bit) and to initiate transmission eventsynchronized at the start of the next basic cycle by the current time master or by one of the other potential time masters. The node transmitting the reference message is the current time master. The time master is allowed to transmit other messages. If the current time master fails, its function is replicated by the potential time master with the highest priority. Nodes that are neither time master nor potential time master are time-receiving nodes. Level 1 Level 1 operation is configured via TTOCF[OM] = ‘01’ and TTOCF[GEN]. External clock synchronization is not available in Level 1. The information related to the reference message is stored in the first data byte as shown below. Cycle_Count is optional. Table 457. First byte of Level 1 reference message Bits First byte 0 1 2 3 Next_is_ Reserved Gap 4 5 6 7 Cycle_Count[5;0] Level 2 Level 2 operation is configured via TTOCF[OM] = ‘10’ and TTOCF[GEN].The information related to the reference message is stored in the first four data bytes as shown below. Cycle_Count and the lower four bits of NTU_Res are optional. The TTCAN does not evaluate NTU_Res[3:0] from received reference messages, it always transmits these bits as ‘0’. Table 458. First four bytes of Level 2 reference message Bits First byte Second byte 0 1 2 3 Next_is_ Reserved Gap 4 5 6 7 Cycle_Count[5;0] NTU_Res[6:4] NTU_Res[3:0] Third byte Master_Ref_Mark[7:0] Fourth byte Master_Ref_Mark[15:8] DocID029587 Rev 3 Disc_Bit 2399/3178 2501 FD Controller Area Network (FDCAN) RM0433 Level 0 Level 0 operation is configured via TTOCF[OM] = ‘11’. External event-synchronized timetriggered operation is not available in Level 0. The information related to the reference message is stored in the first four data bytes as shown in the table below. In Level 0 Next_is_Gap is always 0. Cycle_Count and the lower four bits of NTU_Res are optional. The TTCAN does not evaluate NTU_Res[3:0] from received reference messages, it always transmits these bits as ‘0’. Table 459. First four bytes of Level 0 reference message Bits First byte 0 2 3 Next_is_ Reserved Gap Second byte 56.3.6 1 4 5 6 7 Cycle_Count[5;0] NTU_Res[6:4] NTU_Res[3:0] Third byte Master_Ref_Mark[7:0] Fourth byte Master_Ref_Mark[15:8] Disc_Bit TTCAN configuration TTCAN timing The Network Time Unit (NTU) is the unit in which all times are measured. The NTU is a constant of the whole network and is defined as a priority by the network system designer. In TTCAN Level 1 the NTU is the nominal CAN bit time. In TTCAN Level 0 and Level 2 the NTU is a fraction of the physical second. The NTU is the time base for the local time. The integer part of the local time (16-bit value) is incremented once each NTU. Cycle time and global time are both derived from local time. The fractional part (3-bit value) of local time, cycle time, and global time is not readable. In TTCAN Level 0 and Level 2 the length of the NTU is defined by the Time Unit Ratio TUR. The TUR is in genral a non-integer number, given by TUR = TURNA[NAV] / TURCF[DC]. The NTU length is given by NTU = CAN Clock Period x TUR. The TUR Numerator Configuration NC is an 18-bit number, TURCF[NCL[15:0]] can be programmed in the range 0x0000–0xFFFF. TURCF[NCH[17:16]] is hard wired to 0b01. When 0xnnnn is written to TURCF[NCL[15:0]], TURNA[NAV] starts with the value 0x10000 + 0x0nnnn = 0x1nnnn. The TUR Denominator Configuration TURCF[DC] is a 14-bit number. TURCF[DC] may be programmed in the range 0x0001 - 0x3FFF (0x0000 is an illegal value). In Level 1, NC must be ≥ 4 x TURCF[DC]. In Level 0 and Level 2 NC must be ≥ 8 x TURCF[DC] to get the 3-bit resolution for the internal fractional part of the NTU. A hardware reset presets TURCF[DC] to 0x1000 and TURCF[NCL] to 0x10000, resulting in an NTU consisting of sixteen CAN clock periods. Local time and application watchdog are not started before either the CCCR[INIT] is reset, or TURCF[ELT is set. TURCF[ELT] may not be set before the NTU is configured. Setting TURCF[ELT] to ‘1’ also locks the write access to register TURCF. 2400/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) At startup TURNA[NAV] is updated from NC (= TURCF[NCL] + 0x10000) when TURCF[ELT] is set. In TTCAN Level 1 there is no drift compensation. TURNA.NAV does not change during operation, it is always equal to NC. In TTCAN Level 0 and Level 2 there are two possibilities for TURNA[NAV] to change. When operating as time slave or backup time master, and when TTOCF[ECC] is set, TURNA[NAV] is updated automatically to the value calculated from the monitored global time speed, as long as the TTCAN is in synchronization state In_Schedule or In_Gap. When it loses synchronization it returns to NC. When operating as the actual time master, and when TTOCF[EECS] is set, the Host may update TURCF[NCL]. When the Host sets TTOCN[ECS], TURNA[NAV] will be updated from the new value of NC at the next reference message. The status flag TTOST[WECS] as is set when TTOCN[ECS] is set and is cleared when TURNA[NAV] is updated. TURCF[NCL] is write locked while TTOST[WECS] is set. In TTCAN Level 0 and Level 2 the clock calibration process adapts TURNA[NAV] in the range of the Synchronization Deviation Limit SDL of NC+/- 2(TTOCF[LDSDL]+5). TURCF[NCL] should be programmed to the largest applicable numerical value in order to achieve the best accuracy in the calculation of TURNA[NAV]. The synchronization deviation SD is the difference between NC and TURNA[NAV] (SD = |NC - TURNA[NAV]|). It is limited by the Synchronization Deviation Limit SDL, which is configured by its dual logarithm TTOCF[LDSDL] (SDL = 2(TTOCF[LDSDL]+5)) and should not exceed the clock tolerance given by the CAN bit timing configuration. SD is calculated at each new Basic Cycle. When the calculated TURNA[NAV] deviates by more than SDL from NC, or if the Disc_Bit in the Reference Message is set, the drift compensation is suspended and TTIR[GTE] is set and TTOSC[QCS] is reset, or in case of the Disc_Bit = ‘1’, TTIR[GTD] is set. Table 460. TUR configuration example TUR NC TURCF.DC 8 10 24 50 510 125000 32.5 0x1FFF8 0x1FFFE 0x1FFF8 0x1FFEA 0x1FFFE 0x1E848 0x1FFE0 0x3FFF 0x3333 0x1555 0x0A3D 0x0101 0x0001 0x0FC0 100/12 529/17 0x19000 0x10880 0x3000 0x0880 TTOCN[ECS] schedules NC for activation by the next reference message. TTOCN[SGT] schedules TTGTP[TP] for activation by the next reference message. Setting of TTOCN[ECS] and TTOCN[SGT] requires TTOCF[EECS] to be set (external clock synchronization enabled) while the FDCAN is actual time master. The TTCAN module provides an application watchdog to verity the function of the application program. The Host has to serve this watchdog regularly, else all CAN bus activity is stopped. The Application Watchdog Limit TTOCF[AWL] specifies the number of NTUs between two times the watchdog has to be served. The maximum number of NTUs is 256. The Application Watchdog is served by reading register TTOST. TTOST[AWE] indicates whether the watchdog has been served in time. In case the application failed to serve the application watchdog, interrupt flag TTIR[AW] is set. For software development, the application watchdog may be disabled by programming TTOCF[AWL] to 0x00, see Section 56.4.49: FDCAN TT Operation Configuration Register (FDCAN_TTOCF). Timing of interface signals The timing events which cause a pulse at output FDCAN trigger time mark interrupt pulse m_ttcan_tmp and FDCAN register time mark interrupt pulsem_ttcan_rtp are generated in DocID029587 Rev 3 2401/3178 2501 FD Controller Area Network (FDCAN) RM0433 the CAN clock domain. There is a clock domain crossing delay to be considered before the same event is visible in the APB clock domain (when TTIR[TTMI] is set or TTIR[RTMI] is set). As an example, the signals can be connected to the timing input(s) of another FDCAN node (fdcan_swt/fdcan_evt), in order to automatically synchronize two TTCAN networks. Output FDCAN start of cyclem_ttcan_soc gets active whenever a reference message is completed (either transmitted or received). The output is controlled in the APB clock domain. 56.3.7 Message scheduling TTOCF[TM] controls whether the TTCAN operates as potential time master or as a time slave. If it is a potential time master, the three LSBs of the reference message identifier TTRMC[RID] define the master priority, 0 giving the highest and 7 giving the lowest. There cannot be two nodes in the network using the same master priority. TTRMC[RID] is used for recognition of reference messages. TTRMC[RMPS] is not relevant for time slaves. The Initial Reference Trigger Offset TTOCF[IRTO] is a 7-bit-value that defines (in NTUs) how long a backup time master waits before it starts the transmission of a reference message when a reference message is expected but the bus remains idle. The recommended value for TTOCF[IRTO] is the master priority multiplied with a factor depending on the expected clock drift between the potential time masters in the network. The sequential order of the backup time masters, when one of them starts the reference message in case the current time master fails, should correspond to their master priority, even with maximum clock drift. TTOCF[OM] decides whether the node operates in TTCAN Level 0, Level 1, or Level 2. In one network, all potential time masters have to operate on the same level. Time slaves may operate on Level 1 in a Level 2 network, but not vice versa. The configuration of the TTCAN operation mode via TTOCF[OM] is the last step in the setup. With TTOCF[OM] = ‘00’ (eventdriven CAN communication), the FDCAN operates according to ISO 11898-1: 2015, without time triggers.With TTOCF[OM] = ‘01’ (Level 1), the FDCAN operates according to ISO 11898-4, but without the possibility to synchronize the basic cycles to external events, the Next_is_Gap bit in the reference message is ignored. With TTOCF[OM] = ‘10’ (Level 2), the TTCAN operates according to ISO 11898-4, including the event-synchronized start of a basic cycle. With TTOCF[OM] = ‘11’ (Level 0), the FDCAN operates as event-driven CAN but maintains a calibrated global time base as in Level 2. TTOCF[EECS] enables the external clock synchronization, allowing the application program of the current time master to update the TUR configuration during time-triggered operation, to adapt the clock speed and (in Levels 0 and Level 2 only) the global clock phase to an external reference. TTMLM[ENTT] in the TT Matrix Limits register specifies the number of expected Tx_Triggers in the system matrix. This is the sum of Tx_Triggers for exclusive, single arbitrating and merged arbitrating windows, excluding the Tx_Ref_Triggers. Note that this is usually not the number of Tx_Trigger memory elements; the number of basic cycles in the system matrix and the trigger repeat factors have to be taken into account. An inaccurate configuration of TTMLM[ENTT] will result in either a TxCount Underflow (TTIR[TXU] = ‘1’ and TTOST[EL] = ‘01’, severity 1) or in a Tx Count Overflow (TTIR[TXO] = ‘1’ and TTOST[EL] = ‘10’, severity 2). Note: 2402/3178 In case the first Reference Message seen by a node does not have Cycle_Count 0, this node may finish its first matrix cycle with its Tx count resulting in a Tx Count Underflow DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) condition. As long as a node is in state Synchronizing its Tx_Triggers will not lead to transmissions. TTMLM[CCM] specifies the number of the last basic cycle in the system matrix. The counting of basic cycles starts at 0. In a system matrix consisting of 8 basic cycles TTMLM[CCM] would be 7. TTMLM[CCM] is ignored by time slaves, a receiver of a reference message considers the received cycle count as the valid cycle count for the actual basic cycle. TTMLM[TXEW] specifies the length of the Tx enable window in NTUs. The Tx enable window is that period of time at the beginning of a time window where a transmission may be started. If a transmission of a message cannot be started inside the Tx enable window because of for example, a slight overlap from the previous time window message, the transmission cannot be started in that time window at all. TTMLM[TXEW] has to be chosen with respect to the network synchronization quality and with respect to the relation between the length of the time windows and the length of the messages. Trigger memory The trigger memory is part of the external Message RAM to which the TTCAN is connected to (see Section 56.4.26: FDCAN Rx FIFO 0 Configuration Register (FDCAN_RXF0C)). It stores up to 64 trigger elements. A trigger memory element consists of Time Mark TM, Cycle Code CC, Trigger Type TYPE, Filter Type FTYPE, Message Number MNR, Message Status Count MSC, Time Mark Event Internal TMIN, Time Mark Event External TMEX (see Section 56.3.21: FDCAN Trigger memory element). The time mark defines at which cycle time a trigger becomes active. The triggers in the trigger memory have to be sorted by their time marks. The trigger element with the lowest time mark is written to the first trigger memory word. Message number and cycle code are ignored for triggers of type Tx_Ref_Trigger, Tx_Ref_Trigger_Gap, Watch_Trigger, Watch_Trigger_Gap, and End_of_List. When the cycle time reaches the time mark of the actual trigger, the FSE switches to the next trigger and starts to read the following trigger from the trigger memory. In case of a transmit trigger, the Tx Handler starts to read the message from the Message RAM as soon as the FSE switches to its trigger. The RAM access speed defines the minimum time step between a transmit trigger and its preceding trigger, the Tx Handler has to be able to prepare the transmission before the transmit trigger time mark is reached. The RAM access speed also limits the number of non-matching (with regard to their cycle code) triggers between two matching triggers, the next matching trigger must be read before its time mar k is reached. If the reference message is n NTU long, a trigger with a time mark lower than n will never become active and will be treated as a configuration error. Starting point of the cycle time is the sample point of the reference message start of frame bit. The next reference message is requested when cycle time reaches the Tx_Ref_Trigger time mark. The FDCAN reacts on the transmission request at the next sample point. A new Sync_Mark is captured at the start of frame bit, but the cycle time is incremented until the reference message is successfully transmitted (or received) and the Sync_Mark is taken as the new Ref_Mark. At that point in time, cycle time is restarted. As a consequence, cycle time can never (with the exception of initialization) be seen at a value lower than n, with n being the length of the reference message measured in NTU. Length of a basic cycle: Tx_Ref_Trigger time mark+1 NTU+1 CAN bit time. DocID029587 Rev 3 2403/3178 2501 FD Controller Area Network (FDCAN) RM0433 The trigger list will be different for all nodes in the FDCAN network. Each node knows only the Tx_Triggers for its own transmit messages, the Rx_Triggers for those receive messages that are processed by this node, and the triggers concerning the reference messages. Trigger types Tx_Ref_Trigger (TYPE = ‘0000’) and Tx_Ref_Trigger_Gap (TYPE = ‘0001’) cause the transmission of a reference message by a time master. A configuration error (TTOST[EL] = ‘11’, severity 3) is detected when a time slave encounters a Tx_Ref_Trigger(_Gap) in its trigger memory. Tx_Ref_Trigger_Gap is only used in external event-synchronized time-triggered operation mode. In that mode, Tx_Ref_Trigger is ignored when the FDCAN synchronization state is In_Gap (TTOST[SY]S = ‘10’). Tx_Trigger_Single (TYPE = ‘0010’), Tx_Trigger_Continuous (TYPE = ‘0011’), Tx_Trigger_Arbitration (TYPE = ‘0100’), and Tx_Trigger_Merged (TYPE = ‘0101’) cause the start of a transmission. They define the start of a time window. Tx_Trigger_Single starts a single transmission in an exclusive time window when the message buffer Transmission Request Pending bit is set. After successful transmission the Transmission Request Pending bit is reset. Tx_Trigger_Continuous starts a transmission in an exclusive time window when the message buffer Transmission Request Pending bit is set. After successful transmission the Transmission Request Pending bit remains set, and the message buffer is transmitted again in the next matching time window. Tx_Trigger_Arbitration starts an arbitrating time window, Tx_Trigger_Merged a merged arbitrating time window. The last Tx_Trigger of a merged arbitrating time window must be of type Tx_Trigger_Arbitration. A Configuration Error (TTOST[EL] = ‘11’, severity 3) is detected when a trigger of type Tx_Trigger_Merged is followed by any other Tx_Trigger than one of type Tx_Trigger_Merged or Tx_Trigger_Arbitration. Several Tx_Triggers may be defined for the same Tx message buffer. Depending on their cycle code, they may be ignored in some basic cycles. The cycle code has to be considered when the expected number of Tx_Triggers (TTMLM[ENTT]) is calculated. Watch_Trigger (TYPE = ‘0110’) and Watch_Trigger_Gap (TYPE = ‘0111’) check for missing reference messages. They are used by both time masters and time slaves. Watch_Trigger_Gap is only used in external event-synchronized time-triggered operation mode. In that mode, a Watch_Trigger is ignored when the FDCAN synchronization state is In_Gap (TTOST[SYS] = ‘10’). Rx_Trigger (TYPE = ‘1000’) is used to check for the reception of periodic messages in exclusive time windows. Rx_Triggers are not active until state In_Schedule or In_Gap is reached. The time mark of an Rx_Trigger shall be placed after the end of that message transmission, independent of time window boundaries. Depending on their cycle code, Rx_Triggers may be ignored in some basic cycles. At the time mark of the Rx_Trigger, it is checked whether the last received message before this time mark and after start of cycle or previous Rx_Trigger had matched the acceptance filter element referenced by MNR. Accepted messages are stored in one of the two receive FIFOs, according to the acceptance filtering, independent of the Rx_Trigger. Acceptance filter elements which are referenced by Rx_Triggers should be placed at the beginning of the filter list to ensure that the filtering is finished before the Rx_Trigger time mark is reached. Time_Base_Trigger (TYPE = ‘1001’) are used to generate internal/external events depending on the configuration of TMIN, and TMEX. 2404/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) End_of_List (TYPE = ‘1010…1111’) is an illegal trigger type, a configuration error (TTOST[EL] = ‘11’, severity 3) is detected when an End_of_List trigger is encountered in the trigger memory before the Watch_Trigger and Watch_Trigger_Gap. Restrictions for the node trigger list There may not be two triggers that are active at the same cycle time and cycle count, but triggers that are active in different basic cycles (different cycle code) may share the same time mark. Rx_Triggers and Time_Base_Triggers may not be placed inside the Tx enable windows of Tx_Trigger_Single/Continuous/Arbitration, but they may be placed after Tx_Trigger_Merged. Triggers that are placed after the Watch_Trigger (or the Watch_Trigger_Gap when TTOST[SYS] = ‘10’) will never become active. The watch triggers themselves will not become active when the reference messages are transmitted on time. All unused trigger memory words (after the Watch_Trigger or after the Watch_Trigger_Gap when TTOST[SYS] = ‘10’) must be set to trigger type End_of_List. A typical trigger list for a potential time master will begin with a number of Tx_Triggers and Rx_Triggers followed by the Tx_Ref_Trigger and the Watch_Trigger. For networks with external event- synchronized time-triggered communication, this is followed by the Tx_Ref_Trigger_Gap and the Watch_Trigger_Gap. The trigger list for a time slave will be the same but without the Tx_Ref_Trigger and the Tx_Ref_Trigger_Gap. At the beginning of each basic cycle, that is at each reception or transmission of a reference message, the trigger list is processed starting with the first trigger memory element. The FSE looks for the first trigger with a cycle code that matches the current cycle count. The FSE waits until cycle time reaches the trigger time mark and activates the trigger. Afterwards the FSE looks for the next trigger in the list with a cycle code that matches the current cycle count. Special consideration is needed for the time around Tx_Ref_Trigger and Tx_Ref_Trigger_Gap. In a time master competing for master ship, the effective time mark of a Tx_Ref_Trigger may be decremented in order to be the first node to start a reference message. In backup time masters the effective time mark of a Tx_Ref_Trigger or Tx_Ref_Trigger_Gap is the sum of its configured time mark and the Reference Trigger Offset TTOCF[IRTO]. In case error level 2 is reached (TTOST[EL] = ‘10’), the effective time mark is the sum of its time mark and 0x127. No other trigger elements should be placed in this range otherwise it may happen that the time marks appear out of order and are flagged as a configuration error. Trigger elements which are coming after Tx_Ref_Trigger may never become active as long as the reference messages come in time. There are interdependencies between the following parameters: • APB clock frequency • Speed and waiting time for Trigger RAM accesses • Length of the acceptance filter list • Number of trigger elements • Complexity of cycle code filtering in the trigger elements • Offset between time marks of the trigger elements DocID029587 Rev 3 2405/3178 2501 FD Controller Area Network (FDCAN) RM0433 Example for trigger handling The example shows how the trigger list is derived from a node system matrix. Assumption is that node A is first time master and has knowledge of the section of the system matrix shown in Table 461. Table 461. System matrix, Node A Cycle count Time Mark 1 2 3 4 5 6 7 0 Tx7 - - - - TxRef Error 1 Rx3 - - TxRef Error 2 - - - - - TxRef Error 3 Tx7 - Rx5 - - TxRef Error 4 Tx7 - - Rx6 - TxRef Error Tx2, Tx4 The cycle count starts with 0 and runs until 0, 1, 3, 7, 15, 31, 63 (the corresponding number of basic cycles in the system matrix is 1, 2, 4, 8, 16, 32, 64). The maximum cycle count is configured by TTMLM.CCM. The Cycle Code CC is composed of repeat factor (= value of most significant ‘1’) and the number of the first basic cycle in the system matrix (= bit field after most significant ‘1’). Example: with a cycle code of 0b0010011 (repeat factor = 16, first basic cycle = 3) and a maximum cycle count of TTMLM.CCM = ‘0x3F’ matches occur at cycle counts 3, 19, 35, 51. A trigger element consists of Time Mark TM, Cycle Code CC, Trigger Type TYPE, and Message Number MNR. For transmission MNR references the Tx Buffer number (0..31). For reception MNR references the number of the filter element (0...127) that matched during acceptance filtering. Depending on the configuration of the Filter Type FTYPE, the 11-bit or 29-bit message ID filter list is referenced. In addition a trigger element can be configured for generation of Time Mark Event Internal TMIN, and Time Mark Event External TMEX. The Message Status Count MSC holds the counter value (0..7) for scheduling errors for periodic messages in exclusive time windows at the point in time when the time mark of the trigger element became active. Table 462. Trigger list, Node A Trigger Time Mark TM[15:0] Cycle Code CC [6:0] Trigger Type TYPE [3:0] Mess No. MNR [6:0] 0 Mark1 0b0000100 Tx_Trigger_Single 7 1 Mark 1 0b1000000 Rx_Trigger 3 2 Mark 1 0b1000011 Tx_Trigger_Single 7 3 Mark 3 0b1000001 Tx_Trigger_Merged 2 4 Mark 3 0b1000011 Rx_Trigger 5 5 Mark 4 0b1000001 Tx_Trigger_Arbitration 4 6 Mark 4 0b1000100 Rx_Trigger 6 7 Mark 6 N/A Tx_Ref_Trigger 0 (Ref) 2406/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 462. Trigger list, Node A Trigger Time Mark TM[15:0] Cycle Code CC [6:0] Trigger Type TYPE [3:0] Mess No. MNR [6:0] 8 Mark 7 N/A Watch_Trigger N/A 9 N/A N/A End_of_List N/A Tx_Trigger_Single, Tx_Trigger_Continuous, Tx_Trigger_Merged, Tx_Trigger_Arbitration, Rx_Trigger, and Time_Base_Trigger are only valid for the specified cycle code. For all other trigger types the cycle code is ignored. The FSE starts the basic cycle with scanning the trigger list starting from 0 until a trigger with time mark higher than cycle time and with its Cycle Code CC matching the actual cycle count is reached, or a trigger of type Tx_Ref_Trigger, Tx_Ref_Trigger_Gap, Watch_Trigger, or Watch_Trigger_Gap is encountered. When the cycle time reached the Time Mark TM, the action defined by Trigger Type TYPE and Message Number MNR is started. There is an error in the configuration when End_of_List is reached. At Mark6 the reference message (always TxRef) is transmitted. After transmission of the reference message the FSE returns to the beginning of the trigger list. When the Watch Trigger at Mark7 is reached, the node was not able to transmit the reference message; error treatment is started. Detection of configuration errors A configuration error is signaled via TTOST[EL] = ‘11’ (severity 3) when: • The FSE comes to a trigger in the list with a cycle code that matches the current cycle count but with a time mark that is less than the cycle time. • The previous active trigger was a Tx_Trigger_Merged and the FSE comes to a trigger in the list with a cycle code that matches the current cycle count but that is neither a Tx_Trigger_Merged nor a Tx_Trigger_Arbitration nor a Time_Base_Trigger nor an Rx_Trigger. • The FSE of a node with TTOCF[TM]=‘0’ (time slave) encounters a Tx_Ref_Trigger or a Tx_Ref_Trigger_Gap. • Any time mark placed inside the Tx enable window (defined by TTMLM[TXEW]) of a Tx_Trigger with a matching cycle code. • A time mark is placed near the time mark of a Tx_Ref_Trigger and the Reference Trigger Offset TTOST[RTO] causes a reversal of their sequential order measured in cycle time. TTCAN schedule initialization The synchronization to the TTCAN message schedule starts when CCCR[INIT] is reset. The TTCAN can operate strictly time-triggered (TTOCF[GEN] = ‘0’) or external event-synchronized time-triggered (TTOCF[GEN] = ‘1’). All nodes start with cycle time 0 at the beginning of their trigger list with TTOST[SYS] = ‘00’ (out of synchronization), no transmission is enabled with the exception of the reference message. Nodes in external event-synchronized time-triggered operation mode will ignore Tx_Ref_Trigger and Watch_Trigger and will use instead Tx_Ref_Trigger_Gap and Watch_Trigger_Gap until the first reference message decides whether a Gap is active. DocID029587 Rev 3 2407/3178 2501 FD Controller Area Network (FDCAN) RM0433 Time slaves After configuration, a time slave will ignore its Watch_Trigger and Watch_Trigger_Gap when it did not receive any message before reaching the Watch_Triggers. When it reaches Init_Watch_Trigger, interrupt flag TTIR[IWT] is set, the FSE is frozen, and the cycle time will become invalid, but the node will still be able to take part in CAN bus communication (to acknowledge or to send error flags). The first received reference message will restart the FSE and the cycle time. Note: Init_Watch_Trigger is not part of the trigger list. It is implemented as an internal counter that counts up to 0xFFFF = maximum cycle time. When a time slave has received any message but the reference message before reaching the Watch_Triggers, it will assume a fatal error (TTOST[EL] = ‘11’, severity 3), set interrupt flag TTIR[WT], switch off its CAN bus output, and enter the bus monitoring mode (CCCR[MON] set to ‘1’). In the bus monitoring mode it is still able to receive messages, but it cannot send any dominant bits and therefore cannot give acknowledge. Note: To leave the fatal error state, the Host has to set CCCR[INIT] = ‘1’. After reset of CCCR[INIT], the node restarts TTCAN communication. When no error is encountered during synchronization, the first reference message sets TTOST[SYS] = ‘01’ (Synchronizing), the second sets the FDCAN synchronization state (depending on its Next_is_Gap bit) to TTOST[SYS] = ‘11’ (In_Schedule) or TTOST[SYS] = ‘10’ (In_Gap), enabling all Tx_Triggers and Rx_Triggers. Potential time masters After configuration, a potential time master will start the transmission of a reference message when it reaches its Tx_Ref_Trigger (or its Tx_Ref_Trigger_Gap when in external event-synchronized time-triggered operation). It will ignore its Watch_Trigger and Watch_Trigger_Gap when it did not receive any message or transmit the reference message successfully before reaching the Watch_Triggers (assumed reason: all other nodes still in reset or configuration, giving no acknowledge). When it reaches Init_Watch_Trigger, the attempted transmission is aborted, interrupt flag TTIR[IWT] is set, the FSE is frozen, and the cycle time will become invalid, but the node will still be able to take part in CAN bus communication (to give acknowledge or to send error flags). Resetting TTIR[IWT] will re-enable the transmission of reference messages until next time the Init_Watch_Trigger condition is met, or another CAN message is received. The FSE will not be restarted by the reception of a reference message. When a potential time master reaches the Watch_Triggers after it has received any message but the reference message, it will assume a fatal error (TTOST[EL] = ‘11’, severity 3), set interrupt flag TTIR[WT], switch off its CAN bus output, and enter the bus monitoring mode (CCCR[MON] set to ‘1’). In bus monitoring mode, it is still able to receive messages, but it cannot send any dominant bits and therefore cannot give acknowledge. When no error is detected during initialization, the first reference message sets TTOST[SYS] = ‘01’ (synchronizing), the second sets the FDCAN synchronization state (depending on its Next_is_Gap bit) to TTOST[SYS] = ‘11’ (In_Schedule) or TTOST[SYS] = ‘10’ (In_Gap), enabling all Tx_Triggers and Rx_Triggers. A potential time master is current time master (TTOST[MS] = ‘11’) when it was the transmitter of the last reference message, else it is backup time master (TTOST[MS] = ‘10’). When all potential time masters have finished configuration, the node with the highest time master priority in the network will become the current time master. 2408/3178 DocID029587 Rev 3 RM0433 56.3.8 FD Controller Area Network (FDCAN) TTCAN gap control All functions related to Gap control apply only when the FDCAN is operated in external event synchronized time-triggered mode (TTOCF[GEN] = ‘1’). In this operation mode the FDCAN message schedule may be interrupted by inserting Gaps between the basic cycles of the system matrix. All nodes connected to the CAN network have to be configured for external event- synchronized time-triggered operation. During a Gap, all transmissions are stopped and the CAN bus remains idle. A Gap is finished when the next reference message starts a new basic cycle. A Gap starts at the end of a basic cycle that itself was started by a reference message with bit Next_is_Gap = ‘1’ e.g. Gaps are initiated by the current time master. The current time master has two options to initiate a Gap. A Gap can be initiated under software control when the application program writes TTOCN[NIG] = ‘1’. The Next_is_Gap bit will be transmitted as ‘1’ with the next reference message. A Gap can also be initiated under hardware control when the application program enables the event trigger input pin fdcan_evt by writing TTOCN[GCS] = ‘1’. When a reference message is started and TTOCN[GCS] is set, a HIGH level at event trigger pin fdcan_evt will set Next_is_Gap = ‘1’. As soon as that reference message is completed, the TTOST[WFE] bit will announce the Gap to the time master as well as to the time slaves. The current basic cycle will continue until its last time window. The time after the last time window is the Gap time. For the actual time master and the potential time masters, TTOST[GSI] will be set when the last basic cycle has finished and the Gap time starts. In nodes that are time slaves, bit TTOST[GSI] will remain at ‘0’. When a potential time master is in synchronization state In_Gap (TTOST[SYS] = ‘10’), it has four options to intentionally finish a Gap: Under software control by writing TTOCN[FGP] = ‘1’. Under hardware control (TTOCN[GCS] = ‘1’) an edge from HIGH to LOW at the event-trigger input pin fdcan_evt sets TTOCN[FGP] and restarts the schedule. The third option is a time-triggered restart. When TTOCN[TMG] = ‘1’, the next register time mark interrupt (TTIR[RTMI] = ‘1’) will set TTOCN[FGP] and start the reference message. Finally any potential time master will finish a Gap when it reaches its Tx_Ref_Trigger_Gap, assuming that the event to synchronize on did not occur in time. Neither of these options can cause a basic cycle to be interrupted with a reference message. Setting of TTOCN[FGP] after the Gap time has started will start the transmission of a reference message immediately and will thereby synchronize the message schedule. When TTOCN[FGP] is set before the Gap time has started (while the basic cycle is still in progress), the next reference message is started at the end of the basic cycle, at the Tx_Ref_Trigger – there will be no Gap time in the message schedule. In strictly time-triggered operation, bit Next_is_Gap = ‘1’ in the reference message will be ignored, as well as the event-trigger input pin fdcan_evt and the bits TTOCN[NIG], TTOCN[FGP], and TTOCN[TMG]. 56.3.9 Stop watch The stop watch function enables capturing of FDCAN internal time values (local time, cycle time, or global time) triggered by an external event. DocID029587 Rev 3 2409/3178 2501 FD Controller Area Network (FDCAN) RM0433 To enable the stop watch function, the application program first has to define local time, cycle time, or global time as stop watch source via TTOCN[SWS]. When TTOCN[SWS] is different from ‘00’ and TT Interrupt Register flag TTIR[SWE] is ‘0’, the actual value of the time selected by TTTOCN[SWS] will be copied into TTCPT[SWV] on the next rising/falling edge (as configured via TTOCN[SWP]) on stop watch trigger pin fdcan_swt. This will set interrupt flag TTIR[SWE]. After the application program has read TTCPT[SWV], it may enable the next stop watch event by resetting TTIR[SWE] to ‘0’. 56.3.10 Local time, cycle time, global time, and external clock synchronization There are two possible levels in time-triggered CAN: Level 1 and Level 2. Level 1 only provides time-triggered operation using cycle time. Level 2 additionally provides increased synchronization quality, global time and external clock synchronization. In both levels, all timing features are based on a local time base - the local time. The local time is a 16-bit cyclic counter, it is incremented once each NTU. Internally the NTU is represented by a 3-bit counter which can be regarded as a fractional part (three binary digits) of the local time. Generally, the 3-bit NTU counter is incremented eight times each NTU. If the length of the NTU is shorter than eight CAN clock periods (as may be configured in Level 1, or as a result of clock calibration in Level 2), the length of the NTU fraction is adapted, and the NTU counter is incremented only four times each NTU. Figure 735 describes the synchronization of the cycle time and global time, performed in the same manner by all FDCAN nodes, including the time master. Any message received or transmitted invokes a capture of the local time taken at the message is frame synchronization event. This frame synchronization event occurs at the sample point of each Start of Frame (SoF) bit and causes the local time to be stored as Sync_Mark. Sync_Marks and Ref_Marks are captured including the 3-bit fractional part. Whenever a valid reference message is transmitted or received, the internal Ref_Mark is updated from the Sync_Mark. The difference between Ref_Mark and Sync_Mark is the Cycle Sync Mark (Cycle Sync Mark = Sync_Mark - Ref_Mark) stored in register TTCSM. The most significant 16 bits of the difference between Ref_Mark and the actual value of the local time is the cycle time (Cycle Time = Local Time - Ref_Mark). 2410/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Figure 735. Cycle Time and Global Time synchronization 178 /RFDOWLPH 5HIHUHQFH0HVVDJH 6\QFB0DUN 0DVWHUB5HIB0DUN 5HIB0DUN )UDPH V\QFKURQL]DWLRQ 6\QFB0DUN 5HIHUHQFH PHVVDJHYDOLG 5HIB0DUN &\FOH 6\QF0DUN /RFDOWLPH &\FOHWLPH /RFDOB2IIVHW *OREDOWLPH 069 The cycle time that can be read from TTCTC[CT] is the difference of the node local time and Ref_Mark, both synchronized into the APB clock domain and truncated to 16 bit. The global time exists for TTCAN Level 0 and Level 2 only, in Level 1 it is invalid. The node view of the global time is the local image of the global time in (local) NTUs. After configuration, a potential time master will use its own local time as global time. The time master establishes its own local time as global time by transmitting its own Ref_Marks as Master_Ref_Marks in the reference message (bytes 3 and 4). The global time that can be read from TTLGT[GT] is the sum of the node local time and its local offset, both synchronized into the APB clock domain and truncated to 16 bit. The fractional part is used for clock synchronization only. A node that receives a reference message calculates its local offset to the global time by comparing its local Ref_Mark with the received Master_Ref_Mark (see Figure 736). The node view of the global time is local time + local offset. In a potential time master that has never received another time master reference message, Local_Offset will be 0. When a node becomes the current time master after first having received other reference messages, Local_Offset will be frozen at its last value. In the time receiving nodes, Local_Offset may be subject to small adjustments, due to clock drift, when another node becomes time master, or when there is a global time discontinuity, signaled by Disc_Bit in the reference message. With the exception of global time discontinuity, the global time provided to the application program by register TTLGT is smoothed by a low-pass filtering to have a continuous monotonic value. DocID029587 Rev 3 2411/3178 2501 FD Controller Area Network (FDCAN) RM0433 Figure 736. TTCAN Level 0 and Level 2 drift compensation DFWXDO 0DVWHUB5HIB0DUN SUHYLRXV 0DVWHUB5HIB0DUN 5HIHUHQFHPHVVDJH DFWXDO 5HIB0DUN SUHYLRXV 5HIB0DUN 6\QFB0DUN · " 6WDUWRIEDVLFF\FOH 785FDOLEUDWLRQ 069 Figure 736 describes how in TTCAN Levels 0 and 2 each time receiving node compensates the drift between its own local clock and the time master clock by comparing the length of a basic cycle in local time and in global time. If there is a difference between the two values and the Disc_Bit in the reference message is not set, a new value for TURNA[NAV] is calculated. If the Synchronization Deviation SD = | NC - TURNA[NAV] | ≤ SDL (Synchronization Deviation Limit), the new value for TURNA[NAV] takes effect. Else the automatic drift compensation is suspended. In TTCAN Level 0 and Level 2, TTOST[QCS] indicates whether the automatic drift compensation is active or suspended. In TTCAN Level 1, TTOST[QCS] is always ‘1’. The current time master may synchronize its local clock speed and the global time phase to an external clock source. This is enabled by bit TTOCF[EECS]. The stop watch function (see Section 56.3.9: Stop watch) may be used to measure the difference in clock speed between the local clock and the external clock. The local clock speed is adjusted by first writing the newly calculated Numerator Configuration Low to TURCF[NCL] (TURCF[DC] cannot be updated during operation). The new value takes effect by writing TTOCN[ECS] to ‘1’. The global time phase is adjusted by first writing the phase offset into the TT Global Time Preset register TTGTP. The new value takes effect by writing TTOCN[SGT] to ‘1’. The first reference message transmitted after the global time phase adjustment will have the Disc_Bit set to ‘1’. 2412/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) TTOST[QGTP] shows whether the node global time is in phase with the time master global time. TTOST[QGTP] is permanently ‘0’ in TTCAN Level 1 and when the Synchronization Deviation Limit is exceeded in TTCAN Level 0,2 (TTOST[QCS] = ‘0’). It is temporarily ‘0’ while the global time is low-pass filtered to supply the application with a continuous monotonic value. There is no low-pass filtering when the last reference message contained a Disc_Bit = ‘1’ or when TTOST[QCS]=‘0’. 56.3.11 TTCAN error level The ISO 11898-4 specifies four levels of error severity: • S0 - No Error • S1 - Warning- Only notification of application, reaction application-specific. • S2 Error- Notification of application. All transmissions in exclusive or arbitrating time windows are disabled (i.e. no data or remote frames may be started). Potential time masters still transmit reference messages with the Reference Trigger Offset TTOST[RTO] set to the maximum value of 127. • S3 - Severe Error • Notification of application. All CAN bus operations are stopped, i.e. transmission of dominant bits is not allowed, and CCCR[MON] is set. The S3 error condition remains active until the application updates the configuration (set CCCR[CCE]). If several errors are detected at the same time, the highest severity prevails. When an error is detected, the application is notified by TTIR[ELC]. The error level is monitored by TTOST[EL]. The TTCAN signals the following error conditions as required by ISO 11898-4: • Config_Error (S3) • Sets Error Level TTOST[EL] to ‘11’ when a merged arbitrating time window is not properly closed or when there is a Tx_Trigger with a time mark beyond the Tx_Ref_Trigger. • Watch_Trigger_Reached (S3) • Sets Error Level TTOST[EL] to ‘11’ when a watch trigger was reached because the reference message is missing. • Application_Watchdog (S3) • Sets Error Level TTOST[EL] to ‘11’ when the application failed to serve the application watchdog.The application watchdog is configured via TTOCF[AWL]. It is served by reading register TTOST.When the watchdog is not served in time, bit TTOST[AWE] and interrupt flag TTIR[AW] are set, all FDCAN communication is stopped, and the FDCAN is set into bus monitoring mode (CCCR[MON] set to ‘1’). • CAN_Bus_Off (S3) • Entering CAN_Bus_Off state sets error level TTOST[EL] to ‘11’. CAN_Bus_Off state is signaled by PSR[BO] = ‘1’ and CCCR[INIT] = ‘1’. • Scheduling_Error_2 (S2) • Sets Error Level TTOST[EL] to ‘10’ if the MSC of one Tx_Trigger has reached 7. In addition interrupt flag TTIR[SE2] is set. The Error Level TTOST[EL] is reset to ‘00’ at DocID029587 Rev 3 2413/3178 2501 FD Controller Area Network (FDCAN) RM0433 the beginning of a matrix cycle when no Tx_Trigger has an MSC of 7 in the preceding matrix cycle. 56.3.12 • Tx_Overflow (S2) • Sets Error Level TTOST[EL] to ‘10’ when the Tx count is equal or higher than the expected number of Tx_T riggers TTMLM[ENTT] and a Tx_Trigger event occurs. In addition interrupt flag TTIR[TXO] is set. The Error Level TTOST[EL] is reset to ‘00’ when the Tx count is no more than TTMLM[ENTT] at the start of a new matrix cycle. • Scheduling_Error_1 (S1) • Sets Error Level TTOST[EL] to ‘01’ if within one matrix cycle the difference between the maximum MSC and the minimum MSC for all trigger memory elements (of exclusive time windows) is larger than two, or if one of the MSCs of an exclusive Rx_Trigger has reached seven. In addition interrupt flag TTIR[SE1] is set. If within one matrix cycle none of these conditions is valid, the Error Level TTOST[EL] is reset to ‘00’. • Tx_Underflow (S1) • Sets Error Level TTOST[EL] to ‘01’ when the Tx count is less than the expected number of Tx_Triggers TTMLM[ENTT] at the start of a new matrix cycle. In addition interrupt flag TTIR[TXU] is set. The Error Level TTOST[EL] is reset to ‘00’ when the Tx count is at least TTMLM[ENTT] at the start of a new matrix cycle. TTCAN message handling Reference message For potential time masters the identifier of the reference message is configured via TTRMC[RID]. No dedicated Tx Buffer is required for transmission of the reference message. When a reference message is transmitted, the first data byte for TTCAN Level 1 (that is, the first four data bytes for TTCAN Level 0 and the first four data bytes for TTCAN Level 2) will be provided by the FSE. In case the Reference Message Payload Select TTRMC[RMPS] is set, the rest of the reference message payload (Level 1: bytes 2-8, Level 0,2: bytes 5-6) is taken from Tx Buffer 0. In this case the data length DLC code from message buffer 0 is used. Table 463. Number of data bytes transmitted with a Reference Message TTRMC.RMPS TXBRP.TRP0 Level 0 Level 1 Level 2 0 0 4 1 4 0 1 4 1 4 1 0 4 1 4 1 1 4+MBO 1+MBO 4+MBO To send additional payload with the reference message in Level 1 a DLC > 1 has to be configured, for Level 0 and Level 2 a DLC > 4 is required. In addition the transmission request pending bit TXBRP[TRP0] of message buffer 0 must be set (see Table 463). In case bit TXBRP[TRP0] is not set when a reference message is started, the reference message is transmitted with the data bytes supplied by the FSE only. For acceptance filtering of reference messages the Reference Identifier TTRMC[RID] is used. 2414/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Message reception Message reception is done via the two Rx FIFOs in the same way as for event-driven CAN communication (see Rx Handler). The Message Status Count MSC is part of the corresponding trigger memory element and has to be initialized to 0 during configuration. It is updated while the TTCAN is in synchronization states In_Gap or In_Schedule. The update happens at the message Rx_Trigger. At this point in time it is checked at which acceptance filter element the latest message received in this basic cycle had matched. The matching filter number is stored as the acceptance filter result. If this is the same the filter number as defined in this trigger memory element, the MSC is decremented by one. If the acceptance filter result is not the same filter number as defined for this filter element, or if the acceptance filter result is cleared, the MSC is incremented by one. At each Rx_Trigger and at each start of cycle, the last acceptance filter result is cleared. The time mark of an Rx_Trigger should be set to a value where it is ensured that reception and acceptance filtering for the targeted message has completed. This has to take into consideration the RAM access time and the order of the filter list. It is recommended, that filters which are used for Rx_Triggers are placed at the beginning of the filter list. It is not recommended to use an Rx_Trigger for the reference message. Message transmission For time-triggered message transmission the TTCAN supplies 32 dedicated Tx buffers (see Transmit Pause). A Tx FIFO or Tx queue is not available when the FDCAN is configured for time-triggered operation (TTOCF[OM] = ‘01’ or ‘10’). Each Tx_Trigger in the trigger memory points to a particular Tx buffer containing a specific message. There may be more than one Tx_Trigger for a given Tx buffer if that Tx buffer contains a message that is to be transmitted more than once in a basic cycle or matrix cycle. The application program has to update the data regularly and on time, synchronized to the cycle time. The Host CPU is responsible that no partially updated messages are transmitted. To assure this the Host has to proceed in the following way: Tx_Trigger_Single / Tx_Trigger_Merged / Tx_Trigger_Arbitration • Check whether the previous transmission has completed by reading TXBTO • Update the Tx buffer configuration and/or payload • Issue an Add Request to set the Tx Buffer Request Pending bit Tx_Trigger_Continous • Issue a Cancellation Request to reset the Tx Buffer Request Pending bit • Check whether the cancellation has finished by reading TXBCF • Update Tx buffer configuration and/or payload • Issue an Add Request to set the Tx Buffer Request Pending bit The message MSC stored with the corresponding Tx_Trigger provides information on the success of the transmission. The MSC is incremented by one when the transmission could not be started because the CAN bus was not idle within the corresponding transmit enable window or when the message was started and could not be completed successfully. The MSC is decremented by one when the message was transmitted successfully or when the message could have DocID029587 Rev 3 2415/3178 2501 FD Controller Area Network (FDCAN) RM0433 been started within its transmit enable window but was not started because transmission was disabled (TTCAN in Error Level S2 or Host has disabled this particular message). The Tx buffers may be managed dynamically, i.e. several messages with different identifiers may share the same Tx buffer element. In this case the Host has to assure that no transmission request is pending for the Tx buffer element to be reconfigured by checking TXBRP. If a Tx buffer with pending transmission request should be updated, the Host first has to issue a cancellation request and check whether the cancellation has completed by reading TXBCF before it starts updating. The Tx Handler will transfer a message from the Message RAM to its intermediate output buffer at the trigger element which becomes active immediately before the Tx_Trigger element which defines the beginning of the transmit window. During and after the transfer time the transmit message may not be updated and its TXBRP bit may not be changed. To control this transfer time, an additional trigger element may be placed before the Tx_Trigger. This may be example of a Time_Base_Trigger which need not cause any other action. The difference in time marks between the Tx_Trigger and the preceding trigger has to be large enough to guarantee that the Tx Handler can read four words from the Message RAM even at high RAM access load from other modules. Transmission in exclusive time windows A transmission is started time-triggered when the cycle time reaches the time mark of a Tx_Trigger_Single or Tx_Trigger_Continuous. There is no arbitration on the bus with messages from other nodes. The MSC is updated according the result of the transmission attempt. After successful transmission started by a Tx_Trigger_Single the respective Tx Buffer Request Pending bit is reset. After successful transmission started by a Tx_Trigger_Continuous the respective Tx Buffer Request Pending remains set. When the transmission was not successful due to disturbances, it will be repeated next time (one of) its Tx_Trigger(s) become(s) active. Transmission in arbitrating time windows A transmission is started time-triggered when the cycle time reaches the time mark of a Tx_Trigger_Arbitration. Several nodes may start to transmit at the same time. In this case the message has to arbitrate with the messages from other nodes. The MSC is not updated. When the transmission was not successful (lost arbitration or disturbance), it will be repeated next time (one of) its Tx_Trigger(s) become(s) active. Transmission in merged arbitrating time windows The purpose of a merged arbitrating time window is, to enable multiple nodes to send a limited number of frames which are transmitted in immediate sequence, the order given by CAN arbitration. It is not intended for burst transmission by a node. Since the node does not have exclusive access within this time window, it may happen that not all requested transmissions are successful. Messages which have lost arbitration or were disturbed by an error, may be re-transmitted inside the same merged arbitrating time window. The re-transmission will not be started if the corresponding Transmission Request Pending flag was reset by a successful Tx cancellation. In single transmit windows, the Tx Handler transmits the message indicated by the message number of the trigger element. In merged arbitrating time windows, it can handle up to three 2416/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) message numbers from the trigger list. Their transmissions will be attempted in the sequence defined by the trigger list. If the time mark of a fourth message is reached before the first is transmitted (or canceled by the Host), the four the request will be ignored. The transmission inside a merged arbitrating time window is not time-triggered. The transmission of a message may start before its time mark, or after the time mark if the bus was not idle. The messages transmitted by a specific node inside a merged arbitrating time window will be started in the order of their Tx_Triggers, so a message with low CAN priority may prevent the successful transmission of a following message with higher priority, if their is compelling bus traffic. This has to be considered for the configuration of the trigger list. Time_Base_Triggers may be placed between consecutive Tx_Triggers to define the time until the data of the corresponding Tx Buffer needs to be updated. 56.3.13 TTCAN interrupt and error handling The TT Interrupt Register TTIR consists off our segments. Each interrupt can be enabled separately by the corresponding bit in the TT Interrupt Enable register TTIE. The flags remain set until the Host clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. The first segment consists of flags CER, AW, WT, and IWT. Each flag indicates a fatal error condition where the CAN communication is stopped. With the exception of IWT, these error conditions require a re-configuration of the FDCAN module before the communication can be restarted. The second segment consists of flags ELC, SE1, SE2, TXO, TXU, and GTE. Each flag indicates an error condition where the CAN communication is disturbed. If they are caused by a transient failure, e.g. by disturbances on the CAN bus, they will be handled by the FDCAN protocol failure handling and do not require intervention by the application program. The third segment consists of flags GTD, GTW, SWE, TTMI, and RTMI. The first two flags are controlled by global time events (Level 0,2 only) that require a reaction by the application program. With a Stop Watch Event triggered by a rising edge on pin fdcan_swt internal time values are captured. The Trigger Time Mark Interrupt notifies the application that a specific Time_Base_Trigger is reached. The Register Time Mark Interrupt signals that the time referenced by TTOCN[TMC] (Cycle, Local, or Global) equals time mark TTTMK[TM]. It can also be used to finish a Gap. The fourth segment consists of flags SOG, CSM, SMC, and SBC. These flags provide a means to synchronize the application program to the communication schedule. 56.3.14 Level 0 TTCAN Level 0 is not part of ISO11898-4. This operation mode makes the hardware, that in TTCAN Level 2 maintains the calibrated global time base, also available for event-driven CAN according to ISO11898-1. Level 0 operation is configured via TTOCF[OM] = ‘11’. In this mode the FDCAN operates in event driven CAN communication, there is no fixed schedule, the configuration of TTOCF[GEN] is ignored. External event-synchronized operation is not available in Level 0. A synchronized time base is maintained by transmission of reference messages. In Level 0 the trigger memory is not active and therefore needs not to be configured. The time mark interrupt flag (TTIR[TTMI]) is set when the cycle time has reached TTOCF[IRTO] DocID029587 Rev 3 2417/3178 2501 FD Controller Area Network (FDCAN) RM0433 ´ 0x200, it reminds the Host to set a transmission request for message buffer 0. The Watch_Trigger interrupt flag (TTIR[WT]) is set when the cycle time has reached 0xFF00. These values were chosen to have enough margin for a stable clock calibration. There are no further TT-error-checks. Register time mark interrupts (TTIR[RTMI]) are also possible. The reference message is configured as for Level 2 operation. Received reference messages are recognized by the identifier configured in register TTRMC. For the transmission of reference messages only message buffer 0 may be used. The node transmits reference messages any time the Host sets a transmission request for message buffer 0, there is no reference trigger offset. Level 0 operation is configured via: • TTRMC • TTOCF except EVTP, AWL, GEN • TTMLM except ENTT, TXEW • TURCF Level 0 operation is controlled via: • TTOCN except NIG, TMG, FGP, GCS, TTMIE • TTGTP • TTTMK • TTIR excluding bits CER, AW, IWT SE2, SE1, TXO, TXU, SOG (no function) • TTIR the following bits have changed function – TTMI not defined by trigger memory - activated at cycle time TTOCF[IRTO] 0x200 – WT not defined by trigger memory - activated at cycle time 0xFF00 Level 0 operation is signaled via: • TTOST excluding bits AWE, WFE, GSI, GFI, RTO (no function) Synchronizing Figure 737 describes the states and the state transitions in TTCAN Level 0 operation. Level 0 has no In_Gap state. 2418/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Figure 737. Level 0 schedule synchronization state machine +:UHVHW RU,QLWVWDWH RU(UURUVWDWH6 7 6\QFB2II 7 6\QFKURQL]LQJ 7 ,QB6FKHGXOH 7 7UDQVLWLRQFRQGLWLRQDOZD\VWDNLQJSUHYDOHQFH 7 ,QLWVWDWHOHIWF\FOHWLPHLV 7 $WOHDVWWZRFRQVHFXWLYHUHIHUHQFHPHVVDJHVREVHUYHG ODVWUHIHUHQFHPHVVDJHGLGQ¶WFRQWDLQDVHW'LVFB%LWRU1H[WBLVB*DSELW 069 Handling of error levels During Level 0 operation only the following error conditions may occur: • Watch_Trigger_Reached (S3), reached cycle time 0xFF00 • CAN_Bus_Off (S3) Since no S1 and S2 errors are possible, the error level can only switch between S0 (No Error) and S3 (Severe Error). In TTCAN Level 0 an S3 error is handled differently. When error level S3 is reached, both TTOST[SYS] and TTOST[MS] are reset, and interrupt flags TTIR[GTE] and TTIR[GTD] are set. When error level S3 (TTOST[EL] = ‘11’) is entered, bus monitoring mode is (contrary to TTCAN Level 1 and Level 2) not entered. S3 error level is left automatically after transmission (time master) or reception (time slave) of the next reference message. Master slave relation Figure 738 describes the master slave relation in TTCAN Level 0. In case of an S3 error the FDCAN returns to state Master_Off. DocID029587 Rev 3 2419/3178 2501 FD Controller Area Network (FDCAN) RM0433 Figure 738. Level 0 master to slave relation +:UHVHWRU,QLWVWDWH RU(UURUVWDWH6 7 0DVWHUB2II 7 6ODYH 7 7 7 7 7 &XUUHQWB0DVWHU 7 %DFNXSB0DVWHU 7 7 7UDQVLWLRQFRQGLWLRQDOZD\VWDNLQJSUHYDOHQFH 7 5HIHUHQFHPHVVDJHREVHUYHGZKHQQRWSRWHQWLDOWLPHPDVWHU 7 5HIHUHQFHPHVVDJHREVHUYHGZLWKPDVWHUSULRULW\GLIIHUHQWIURPRZQPDVWHUSULRULW\(UURUVWDWH6 7 5HIHUHQFHPHVVDJHREVHUYHGZLWKPDVWHUSULRULW\HTXDOWRRZQPDVWHUSULRULW\(UURUVWDWH6 7 5HIHUHQFHPHVVDJHREVHUYHGZLWKRZQPDVWHUSULRULW\ 7 5HIHUHQFHPHVVDJHREVHUYHGZLWKPDVWHUSULRULW\KLJKHUWKDQRZQPDVWHUSULRULW\ 7 (UURUVWDWH6 7 (UURUVWDWH6 7 (UURUVWDWH6 069 56.3.15 Synchronization to external time schedule This feature can be used to synchronize the phase of the FDCAN schedule to an external schedule (e.g. that of a second TTCAN network or FlexRay network). It is applicable only when the FDCAN is current time master (TTOST[MS] = ‘11’). External synchronization is controlled by event trigger input pin fdcan_evt. If bit TTOCN[ESCN] is set, a rising edge at event trigger pin fdcan_evt the FDCAN compares its actual cycle time with the target phase value configured by TTGTP[CTP]. Before setting TTOCN[ESCN] the Host has to adapt the phases of the two time schedules e.g. by using the FDCAN gap control (see Section 56.3.8: TTCAN gap control). When the Host sets TTOCN[ESCN], TTOST[SPL] is set. If the difference between the cycle time and the target phase value TTGTP[CTP] at the rising edge at event trigger pin fdcan_evt is greater than 9 NTU, the phase lock bit TTOST[SPL] is reset, and interrupt flag TTIR[CSM] is set. TTOST[SPL] is also reset (and TTIR[CSM] is set), when another node becomes time master. If both TTOST[SPL] and TTOCN[ESCN] are set, and if the difference between the cycle time and the target phase value TTGTP[CTP] at the rising edge at event trigger pin fdcan_evt is lower or equal to nine NTU, the phase lock bit TTOST[SPL] remains set, and the measured difference is used as reference trigger offset value to adjust the phase at the next transmitted reference message. 2420/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Note: The rising edge detection at event trigger pin fdcan_evt is enabled with the start of each basic cycle. The first rising edge triggers the compare of the actual cycle time with TTGTP[CTP]. All further edges until the beginning of the next basic cycle are ignored. 56.3.16 FDCAN Rx Buffer and FIFO element Up to 64 Rx Buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx FIFO section can be configured to store up to 64 received messages. The structure of a Rx Buffer / FIFO element is shown in Table 464, the description is provided in Table 465. Table 464. Rx Buffer and FIFO element Bit 31 R0 ESI R1 ANMF 24 23 XTD 16 15 RTR FIDX[6:0] 8 7 0 ID[28:0] Res. FDF BRS DLC[3:0] RXTS[15:0] DB0[7:0] R3 DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Rn DBm[7:0] DBm-1[7:0] ... DB1[7:0] ... DB2[7:0] ... DB3[7:0] ... R2 DBm-2[7:0] DBm-3[7:0] The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register RXESC. Table 465. Rx Buffer and FIFO element description Field Description R0 Bit 31 ESI Error State Indicator 0: Transmitting node is error active 1: Transmitting node is error passive R0 Bit 30 XTD Extended Identifier Signals to the Host whether the received frame has a standard or extended identifier. 0: 11-bit standard identifier 1: 29-bit extended identifier R0 Bit 29 RTR Remote Transmission Request Signals to the Host whether the received frame is a data frame or a remote frame. 0: Received frame is a data frame 1: Received frame is a remote frame Identifier R0 Bits 28:0 Standard or extended identifier depending on bit XTD. A standard identifier is stored ID[28:0] into ID[28:18]. R1 Bit 31 ANMF Accepted Non-matching Frame Acceptance of non-matching frames may be enabled via GFC[ANFS] and GFC[ANFE]. 0: Received frame matching filter index FIDX 1: Received frame did not match any Rx filter element DocID029587 Rev 3 2421/3178 2501 FD Controller Area Network (FDCAN) RM0433 Table 465. Rx Buffer and FIFO element description (continued) Field Description Filter Index R1 Bits 30:24 0-127=Index of matching Rx acceptance filter element (invalid if ANMF = ‘1’). FIDX[6:0] Range is 0 to SIDFC[LSS] - 1 or XIDFC[LSE] - 1. R1 Bit 21 FDF FD Format 0: Standard frame format 1: FDCAN frame format (new DLC-coding and CRC) R1 Bit 20 BRS Bit Rate Switch 0: Frame received without bit rate switching 1: Frame received with bit rate switching Data Length Code R1 Bits 19:16 0-8: CAN + CAN FD: received frame has 0-8 data bytes DLC[3:0] 9-15: CAN: received frame has 8 data bytes 9-15: CAN FD: received frame has 12/16/20/24/32/48/64 data bytes Rx Timestamp R1 Bits 15:0 Timestamp Counter value captured on start of frame reception. Resolution depending RXTS[15:0] on configuration of the Timestamp Counter Prescaler TSCC[TCP]. R2 Bits 31:24 Data Byte 3 DB3[7:0] R2 Bits 23:16 Data Byte 2 DB2[7:0] R2 Bits 15:8 Data Byte 1 DB1[7:0] R2 Bits 7:0 DB0[7:0] Data Byte 0 R3 Bits 31:24 Data Byte 7 DB7[7:0] R3 Bits 23:16 Data Byte 6 DB6[7:0] R3 Bits 15:8 Data Byte 5 DB5[7:0] ... Data Byte 4 ... R3 Bits 7:0 DB4[7:0] Rn Bits 31:24 Data Byte m DBm[7:0] Rn Bits 23:16 Data Byte m-1 DBm-1[7:0] 2422/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 465. Rx Buffer and FIFO element description (continued) Field Description Rn Bits 15:8 Data Byte m-2 DBm-2[7:0] Rn Bits 7:0 DBm-3[7:0] FDCAN Tx Buffer element The Tx Buffers section can be configured to hold dedicated Tx Buffers as well as a Tx FIFO / Tx Queue. In case that the Tx Buffers section is shared by dedicated Tx buffers and a Tx FIFO / Tx Queue, the dedicated Tx Buffers start at the beginning of the Tx Buffers section followed by the buffers assigned to the Tx FIFO or Tx Queue. The Tx Handler distinguishes between dedicated Tx Buffers and Tx FIFO / Tx Queue by evaluating the Tx Buffer configuration TXBC.TFQS and TXBC.NDTB. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register TXESC. Table 466. Tx Buffer and FIFO element Bit 31 T0 ESI 24 23 XTD 16 15 RTR 8 7 0 ID[28:0] Res. T2 DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0] T3 DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] ... EFC Res. FDF BPS DLC[3:0] ... MM[7:0] ... T1 ... 56.3.17 Data Byte m-3 Tn DBm[7:0] DBm-1[7:0] DBm-2[7:0] DBm-3[7:0] Table 467. Tx Buffer element description Field Description T0 Bit 31 ESI(1) Error State Indicator 0: ESI bit in CAN FD format depends only on error passive flag 1: ESI bit in CAN FD format transmitted recessive T0 Bit 30 XTD Extended Identifier 0: 11-bit standard identifier 1: 29-bit extended identifier T0 Bit 29 RTR(2) Remote Transmission Request 0: Transmit data frame 1: Transmit remote frame Identifier T0 Bits 28:0 Standard or extended identifier depending on bit XTD. A standard identifier has to be ID[28:0] written to ID[28:18]. DocID029587 Rev 3 2423/3178 2501 FD Controller Area Network (FDCAN) RM0433 Table 467. Tx Buffer element description (continued) Field Description Message Marker T1 Bits 31:24 Written by CPU during Tx Buffer configuration. Copied into Tx Event FIFO element for MM[7:0] identification of Tx message status. T1 Bit 23 EFC Event FIFO Control 0: Don’t store Tx events 1: Store Tx events T1 Bit 21 FDF FD Format 0: Frame transmitted in Classic CAN format 1: Frame transmitted in CAN FD format T1 Bit 20 BRS(3) Bit Rate Switching 0: CAN FD frames transmitted without bit rate switching 1: CAN FD frames transmitted with bit rate switching Data Length Code T1 Bits 19:16 0 - 8: CAN + CAN FD: received frame has 0-8 data bytes DLC[3:0] 9 - 15: CAN: received frame has 8 data bytes 9 - 15: CAN FD: received frame has 12/16/20/24/32/48/64 data bytes T2 Bits 31:24 Data Byte 3 DB3[7:0] T2 Bits 23:16 Data Byte 2 DB2[7:0] T2 Bits 15:8 Data Byte 1 DB1[7:0] T2 Bits 7:0 DB0[7:0] Data Byte 0 T3 Bits 31:24 Data Byte 7 DB7[7:0] T3 Bits 23:16 Data Byte 6 DB6[7:0] T3 Bits 15:8 Data Byte 5 DB5[7:0] ... Data Byte 4 ... T3 Bits 7:0 DB4[7:0] Tn Bits 31:24 Data Byte m DBm[7:0] Tn Bits 23:16 Data Byte m-1 DBm-1[7:0] 2424/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 467. Tx Buffer element description (continued) Field Description Tn Bits 15:8 Data Byte m-2 DBm-2[7:0] Tn Bits 7:0 DBm-3[7:0] Data Byte m-3 1. The ESI bit of the transmit buffer is OR-ed with the error passive flag to decide the value of the ESI bit in the transmitted FD frame. As required by the CAN FD protocol specification, an error active node may optionally transmit the ESI bit recessive, but an error passive node will always transmit the ESI bit recessive. 2. When RTR = 1, the FDCAN transmits a remote frame according to ISO11898-1, even if CCCR.FDOE enables the transmission in CAN FD format. 3. Bits ESI, FDF, and BRS are only evaluated when CAN FD operation is enabled CCCR.FDOE = 1’. Bit BRS is only evaluated when in addition CCCR.BRSE = ‘1’. 56.3.18 FDCAN Tx Event FIFO element Each element stores information about transmitted messages. By reading the Tx Event FIFO the Host CPU gets this information in the order the messages were transmitted. Status information about the Tx Event FIFO can be obtained from register TXEFS. Table 468. Tx Event FIFO element Bit 31 E0 24 23 ESI XTD E1 16 15 RTR MM[7:0] 8 7 0 ID[28:0] ET[1:0] EDL BRS DLC[3:0] TXTS[15:0] Table 469. Tx Event FIFO element description Field Description E0 Bit 31 ESI Error State Indicator 0: Transmitting node is error active 1: Transmitting node is error passive E0 Bit 30 XTD Extended Identifier 0: 11-bit standard identifier 1: 29-bit extended identifier E0 Bit 29 RTR Remote Transmission Request 0: Transmit data frame 1: Transmit remote frame Identifier E0 Bits 28:0 Standard or extended identifier depending on bit XTD. A standard identifier has to be ID[28:0] written to ID[28:18]. Message Marker E1 Bits 31:24 Copied from Tx Buffer into Tx Event FIFO element for identification of Tx message MM[7:0] status. DocID029587 Rev 3 2425/3178 2501 FD Controller Area Network (FDCAN) RM0433 Table 469. Tx Event FIFO element description (continued) Field Description Event Type 00: Reserved E1 Bits 23:22 01: Tx event EFC 10: Transmission in spite of cancellation (always set for transmissions in DAR mode) 11: Reserved E1 Bit 21 EDL Extended Data Length 0: Standard frame format 1: FDCAN frame format (new DLC-coding and CRC) E1 Bit 20 BRS Bit Rate Switching 0: Frame transmitted without bit rate switching 1: Frame transmitted with bit rate switching Data Length Code T1 Bits 19:16 0 - 8: Frame with 0-8 data bytes transmitted DLC[3:0] 9-15: Frame with 8 data bytes transmitted Tx Timestamp E1 Bits 15:0 Timestamp counter value captured on start of frame transmission. Resolution TXTS[15:0] depending on configuration of the Timestamp Counter Prescaler TSCC[TCP]. 56.3.19 FDCAN Standard message ID Filter element Up to 128 filter elements can be configured for 11-bit standard IDs. When accessing a Standard Message ID Filter element, its address is the Filter List Standard Start Address SIDFC.FLSSA plus the index of the filter element (0…127). Table 470. Standard Message ID Filter element 2426/3178 Bit 31 S0 SFT[1:0] 24 23 SFEC[2:0] 16 15 SFID1[10:0] DocID029587 Rev 3 Res. 8 7 SFID2[10:0] 0 RM0433 FD Controller Area Network (FDCAN) Table 471. Standard Message ID Filter element Field description Field Description Bit 31:30 SFT[1:0](1) Standard Filter Type 00: Range filter from SFID1 to SFID2 01: Dual ID filter for SFID1 or SFID2 10: Classic filter: SFID1 = filter, SFID2 = mask 11: Filter element disabled Bit 29:27 SFEC[2:0] Standard Filter Element Configuration All enabled filter elements are used for acceptance filtering of standard frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached. If SFEC = “100”, “101”, or “110” a match sets interrupt flag IR.HPM and, if enabled, an interrupt is generated. In this case register HPMS is updated with the status of the priority match. 000: Disable filter element 001: Store in Rx FIFO 0 if filter matches 010: Store in Rx FIFO 1 if filter matches 011: Reject ID if filter matches 100: Set priority if filter matches 101: Set priority and store in FIFO 0 if filter matches 110: Set priority and store in FIFO 1 if filter matches 111:= Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored Bits 26:16 SFID1[10:0] Standard Filter ID 1 First ID of standard ID filter element. When filtering for Rx Buffers or for debug messages this field defines the ID of a standard message to be stored. The received identifiers must match exactly, no masking mechanism is used. Standard Filter ID 2 This bit field has a different meaning depending on the configuration of SFEC: SFID2[15:10] – SFEC = ‘001’...‘110’ Second ID of standard ID filter element – SFEC = ‘111’ Filter for Rx Buffers or for debug messages Bits 15:0 Decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence. 00: Store message into an Rx Buffer SFID2[10:9] 01: Debug Message A 10: Debug Message B 11: Debug Message C SFID2[8:6] Is used to control the filter event pins at the Extension Interface. A ‘1’ at the respective bit position enables generation of a pulse at the related filter event pin with the duration of one m_ttcan_hclk period in case the filter matches. SFID2[8] is used by the calibration unit. SFID2[5:0] Defines the offset to the Rx Buffer Start Address RXBC.RBSA for storage of a matching message. 1. With SFT = “11” the filter element is disabled and the acceptance filtering continues (same behavior as with SFEC = “000”). Note: In case a reserved value is configured, the filter element is considered disabled. DocID029587 Rev 3 2427/3178 2501 FD Controller Area Network (FDCAN) 56.3.20 RM0433 FDCAN Extended message ID filter element Up to 64 filter elements can be configured for 29-bit extended IDs. When accessing an Extended Message ID Filter element, its address is the Filter List Extended Start Address XIDFC[FLESA] plus two times the index of the filter element (0…63). Table 472. Extended Message ID Filter element Bit 31 F0 24 23 16 15 EFEC[2:0] F1 EFTI[1:0] 8 7 0 EFID1[28:0] Res. EFID2[28:0] Table 473. Extended Message ID Filter element field description Field Description F0 Bits 31:29 EFEC[2:0] Extended Filter Element Configuration All enabled filter elements are used for acceptance filtering of extended frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached. If EFEC = ‘100’, ‘101’, or ‘110’ a match sets interrupt flag IR[HPM] and, if enabled, an interrupt is generated. In this case register HPMS is updated with the status of the priority match. 000: Disable filter element 001: Store in Rx FIFO 0 if filter matches 010: Store in Rx FIFO 1 if filter matches 011: Reject ID if filter matches 100: Set priority if filter matches 101: Set priority and store in FIFO 0 if filter matches 110: Set priority and store in FIFO 1 if filter matches 111: Store into Rx Buffer, configuration of EFT[1:0] ignored F0 Bits 28:0 EFID1[28:0] Extended Filter ID 1 First ID of extended ID filter element. When filtering for Rx Buffers or for debug messages this field defines the ID of an extended message to be stored. The received identifiers must match exactly, only XIDAM masking mechanism. F1 Bits 31:30 EFT[1:0] Extended Filter Type 00: Range filter from EF1ID to EF2ID (EF2ID ≥ EF1ID) 01: Dual ID filter for EF1ID or EF2ID 10: Classic filter: EF1ID = filter, EF2ID = mask 11: Range filter from EF1ID to EF2ID (EF2ID ≥ EF1ID), XIDAM mask not applied 2428/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 473. Extended Message ID Filter element field description (continued) Field Description Extended Filter ID 2 This bit field has a different meaning depending on the configuration of EFEC: EFID2[10:0] – SFEC = ‘001’...‘110’ Second ID of extended ID filter element – SFEC = ‘111’ Filter for Rx Buffers or for debug messages F1 Bits 28:0 56.3.21 Decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence. 00: Store message into an Rx Buffer EFID2[10:9] 01: Debug Message A 10: Debug Message B 11: Debug Message C EFID2[8:6] Is used to control the filter event pins at the Extension Interface. A ‘1’ at the respective bit position enables generation of a pulse at the related filter event pin with the duration of one m_ttcan_hclk period in case the filter matches. EFID2[8] interface is used by the calibration unit. EFID2[5:0] Defines the offset to the Rx Buffer Start Address RXBC.RBSA for storage of a matching message. FDCAN Trigger memory element Up to 64 trigger memory elements can be configured. When accessing a Trigger Memory element, its address is the Trigger Memory Start Address TTTMC[TMSA] plus the index of the trigger memory element (0…63). Table 474. Trigger Memory element Bit 31 24 23 T0 T1 16 15 TM[15:0] Res. FTYPE 8 7 0 Res. CC[6:0] Res. MNR[6:0] DocID029587 Rev 3 TMIN TMEX Res. TYPE[3:0] MSC[2:0] 2429/3178 2501 FD Controller Area Network (FDCAN) RM0433 Table 475. Trigger Memory element description Field Description T0 Bits 31:16 Time Mark TM[15:0] Cycle time for which the trigger becomes active. T0 Bit 14:8 CC[6:0] 2430/3178 Cycle Code Cycle count for which the trigger is valid. Ignored for trigger types Tx_Ref_Trigger, Tx_Ref_Trigger_Gap, Watch_Trigger, Watch_Trigger_Gap, End_of_List. 0b000000x valid for all cycles 0b000001c valid every 2nd cycle at cycle count mod2 = c 0b00001cc valid every 4th cycle at cycle count mod4 = cc 0b0001ccc valid every 8th cycle at cycle count mod8 = ccc 0b001cccc valid every 16th cycle at cycle count mod16 = cccc 0b01ccccc valid every 32nd cycle at cycle count mod32 = ccccc 0b1cccccc valid every 64th cycle at cycle count mod64 = cccccc T0 Bit 5 TMIN Time Mark Event Internal 0: No action 1: TTIR.TTMI is set when trigger memory element becomes active T0 Bit 4 TMEX Time Mark Event External 0: No action 1: Pulse at output m_ttcan_tmp with the length of one period is generated when the time ark of the trigger memory element becomes active and TTOCN.TTMIE = ‘1’ T0 Bit 3:0 TYPE[3:0] Trigger Type 0000 Tx_Ref_Trigger - valid when not in Gap 0001 Tx_Ref_Trigger_Gap - valid when in Gap 0010 Tx_Trigger_Single - starts a single transmission in an exclusive time window 0011 Tx_Trigger_Continuous - starts continuous transmission in an exclusive time window 0100 Tx_Trigger_Arbitration - starts a transmission in an arbitrating time window 0101 Tx_Trigger_Merged - starts a merged arbitration window 0110 Watch_Trigger - valid when not in Gap 0111 Watch_Trigger_Gap - valid when in Gap 1000 Rx_Trigger - check for reception 1001 Time_Base_Trigger - only control TMIN, TMEX 1010…1111=End_of_List - illegal type, causes configuration error T1 Bit 23FTYPE Filter Type 0: 11-bit standard message ID 1: 29-bit extended message ID DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Table 475. Trigger Memory element description (continued) Field Description Message Number – Transmission: Trigger is valid for configured Tx Buffer number. Valid values are 0 to T1 Bit 22:16 31. (1) MNR[6:0] – Reception: Trigger is valid for standard/extended message ID filter element number. Valid values are, respectively 0 to 63 and 0 to 127. T1 Bits 2:0 MSC[2:0] Message Status Count Counts scheduling errors for periodic messages in exclusive time windows. It has no function for arbitrating messages and in event-driven CAN communication (ISO11898-1). 0-7= Actual status 1. The trigger memory elements have to be written when the FDCAN is in INIT state.Write access to the trigger memory elements outside INIT state is not allowed.There is an exception for TMIN and TMEX when they are defined as part of a trigger memory element of TYPE Tx_Ref_Trigger. In this case they become active at the time mark modified by the actual Reference Trigger Offset (TTOST[RTO]). 56.4 FDCAN registers 56.4.1 FDCAN Core Release Register (FDCAN_CREL) Address offset: 0x0000 Reset value: 0xrrd dddd 31 30 29 28 27 REL[3:0] 26 25 24 23 STEP[3:0] 22 21 20 19 SUBSTEP[3:0] 18 14 13 12 11 10 16 YEAR[3:0] r 15 17 d 9 8 7 MON[7:0] 6 5 4 3 2 1 0 DAY[7:0] d Bits 31: 28 REL: Core release One digit, BCD Bits 27: 24 STEP: Step of Core release One digit, BCD Bits 23: 20 SUBSTEP: Sub-step of Core release One digit, BCD Bits 19: 16 YEAR: Timestamp Year One digit, BCD Bits 15: 8 YEAR: Timestamp Month Two digits, BCD Bits 7: 0 YEAR: Timestamp Day Two digits, BCD DocID029587 Rev 3 2431/3178 2501 FD Controller Area Network (FDCAN) 56.4.2 RM0433 FDCAN Core Release Register (FDCAN_ENDN) Address offset: 0x0004 Reset value: 0x8765_4321 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ETV[31:0] r 15 14 13 12 11 10 9 8 7 ETV[15:0] r Bits 31: 0 ETV: Endiannes Test Value The endianness test value is 0x8765 4321. 56.4.3 FDCAN Data Bit Timing and Prescaler Register (FDCAN_DBTP) Address offset: 0x000C Reset value: 0x0000 0A33 This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. TDC Res. Res. r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. r r r DTSEG1[4:0] DTSEG2[3:0] rw Bits 31: 24 Reserved Bit 23 TDC: Transceiver Delay Compensation 0: Transceiver Delay Compensation disabled 1: Transceiver Delay Compensation enabled Bits 22: 21 Reserved 2432/3178 DocID029587 Rev 3 20 19 18 17 16 1 0 DBRP[4:0] rw 4 3 2 DSJW[3:0] RM0433 FD Controller Area Network (FDCAN) Bits 20: 16 DBRP: Data BIt Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 1023. The hardware interpreters this value as the value programmed plus 1. Bits 15: 13 Reserved Bits 12: 8 DTSEG1: Data time segment before sample point Valid values are 1 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Bits 7: 4 DTSEG1: Data time segment after sample point Valid values are 1 to 7. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Bits 3: 0 DSJW: Synchronization Jump Width Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With a FDCAN clock of 8 MHz, the reset value of 0x00000A33 configures the FDCAN for a fast bit rate of 500 kbit/s. 56.4.4 FDCAN Test Register (FDCAN_TEST) Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to ‘1’. All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from ‘00’ may disturb the message transfer on the CAN bus. Address: 0x0010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. RX LBCK Res. Res. Res. Res. r r r r r r r r rw rw r r r r TX[1:0] rw DocID029587 Rev 3 rw 2433/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bits 31: 8 Reserved Bit 7 RX: Receive Pin Monitors the actual value of transmit pin FDCANx_RX 0: The CAN bus is dominant (FDCANx_RX = ‘0’) 1: The CAN bus is recessive (FDCANx_RX = ‘1’) Bits 6: 5 TX: Control of Transmit Pin 00: Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time 01: Sample point can be monitored at pin FDCANx_TX 10: Dominant (‘0’) level at pin FDCANx_TX 11: Recessive (‘1’) at pin FDCANx_TX Bit 4 LBCK: Loop Back mode 0: Reset value, Loop Back mode is disabled 1: Loop Back mode is enabled (see Test modes) Bits 3: 0 Reserved 56.4.5 FDCAN RAM Watchdog Register (FDCAN_RWD) The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. Address: 0x0014 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw WDV[7:0] r r r r r WDC[7:0] r r r rw rw rw rw rw Bits 31: 16 Reserved Bits 15: 8 WDV: Watchdog value Actual Message RAM Watchdog Counter Value. Bits 7: 0 WDC: Watchdog configuration Start value of the Message RAM Watchdog Counter. With the reset value of ‘00’ the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. 2434/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.6 FDCAN CC Control Register (FDCAN_CCCR) Address: 0x0018 Reset value: 0x0000 0001 For details about setting and resetting of single bits see Software initialization. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NISO TXP EFBI PHXD Res. Res. BRSE FDOE TEST DAR MON CSR CSA ASM CCE INIT rw rw rw rw rw rw rw rw rw rw rw rw rw rw r Bits 31: 16 Reserved Bit 15 NISO: Non ISO Operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0: CAN FD frame format according to ISO11898-1 1: CAN FD frame format according to Bosch CAN FD Specification V1.0 Bit 14 TXP If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 0: disabled 1: enabled Bit 13 EFBI: Edge Filtering during Bus Integration 0: Edge filtering disabled 1: Two consecutive dominant tq required to detect an edge for hard synchronization Bit 12 PXHD: Protocol Exception Handling Disable 0: Protocol exception handling enabled 1: Protocol exception handling disabled Bits 11: 10 Reserved Bit 9 BSE: FDCAN Bit Rate Switching 0: Bit rate switching for transmissions disabled 1: Bit rate switching for transmissions enabled Bit 8 FDOE: FD Operation Enable 0: FD operation disabled 1: FD operation enabled Bit 7 TEST: Test Mode Enable 0: Normal operation, register TEST holds reset values 1: Test Mode, write access to register TEST enabled Bit 6 DAR: Disable Automatic Retransmission 0: Automatic retransmission of messages not transmitted successfully enabled 1: Automatic retransmission disabled DocID029587 Rev 3 2435/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 5 MON: Bus Monitoring Mode Bit MON can only be set by software when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. 0: Bus Monitoring Mode is disabled 1: Bus Monitoring Mode is enabled Bit 4 CSR: Clock Stop Request 0: No clock stop is requested 1: Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. Bit 3 CSA: Clock Stop Acknowledge 0: No clock stop acknowledged 1: FDCAN may be set in power down by stopping APB clock and kernel clock Bit 2 ASM: ASM Restricted Operation Mode The Restricted Operation Mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to ‘1’. The bit can be reset by the software at any time. If the FDCAN is connected to a Clock Calibration on CAN unit, ASM bit is set by hardware as long as the calibration is not completed. 0: Normal CAN operation 1: Restricted Operation Mode active Bit 1 CCE: Configuration Change Enable 0: The CPU has no write access to the protected configuration registers 1: The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) Bit 0 INIT: Initialization 0: Normal Operation 1: Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. 56.4.7 FDCAN Nominal Bit Timing and Prescaler Register (FDCAN_NBTP) Address: 0x001C Reset value: 0x0000 0A33 This register is only writable if bits CCCR[CCE] and CCCR[INIT] are set. The CAN bit time may be programed in the range of 4 to 81 tq. The CAN time quantum may be programmed in the range of [1…1024] FDCAN kernel clock periods. 2436/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) tq = (BRP + 1) FDCAN clock period m_ttcan_cclk NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [NTSEG1 + NTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 31 30 29 28 27 26 25 24 23 22 21 NSJW[6:0] 20 19 18 17 16 NBRP[8:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw NTSEG1[7:0] rw rw rw rw rw Res. rw rw rw rw TSEG2[6:0] rw rw rw rw Bits 31: 25 NSJW: Nominal (Re)Synchronization Jump Width Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 24: 16 NBRP: Bit Rate Prescaler Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 8 NTSEG1: Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 7 Reserved Bits 6: 0 TSEG2: Nominal Time segment after sample point Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note: With a CAN kernel clock of 8 MHz, the reset value of 0x00000A33 configures the FDCAN for a bit rate of 500 kbit/s. 56.4.8 FDCAN Timestamp Counter Configuration Register (FDCAN_TSCC) Address: 0x0020 Reset value: 0x0000 0000 DocID029587 Rev 3 2437/3178 2501 FD Controller Area Network (FDCAN) RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TCP[3:0] TSS[1:0] rw rw Bits 31: 20 Reserved Bits 19: 16 TCP: Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = ‘10’). These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 Reserved Bits 1: 0 TSS: Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 7 Reserved Bits 6: 0 TSS: Timestamp Select 00: Timestamp counter value always 0x0000 01: Timestamp counter value incremented according to TCP 10: External timestamp counter from TIM3 value used (tim3_cnt[0:15]) 11: Same as ‘00’. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. 56.4.9 FDCAN Timestamp Counter Value Register (FDCAN_TSCV) Address: 0x0024 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w1c w1c w1c w1c w1c w1c w1c TSC[15:0] w1c w1c 2438/3178 w1c w1c w1c w1c w1c w1c w1c DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 31: 16 Reserved Bits 15: 0 TSC: Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = ‘01’, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = ‘10’, TSC reflects the external Timestamp Counter value. A write access has no impact. Note: A “wrap around” is a change of the Timestamp Counter value from non-0 to 0 that is not caused by write access to TSCV. 56.4.10 FDCAN Timeout Counter Configuration Register (FDCAN_TOCC) Address: 0x0028 Reset value: 0xFFFF 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TOP[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TOS[1:0] rw ETOC rw rw Bits 31: 16 TOP: Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Bits 15: 3 Reserved Bits 2: 1 TOS: Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. 00: Continuous operation 01: Timeout controlled by Tx Event FIFO 10: Timeout controlled by Rx FIFO 0 11: Timeout controlled by Rx FIFO 1 These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 0 ETOC: Enable Timeout Counter 0: Timeout Counter disabled 1: Timeout Counter enabled This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. For more details see Timeout counter. 56.4.11 FDCAN Timeout Counter Value Register (FDCAN_TOCV) Address: 0x002C DocID029587 Rev 3 2439/3178 2501 FD Controller Area Network (FDCAN) RM0433 Reset value: 0x0000 FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w1c w1c w1c w1c w1c w1c w1c TOC[15:0] w1c w1c w1c w1c w1c w1c w1c w1c w1c Bits 31: 16 Reserved Bits 15: 0 TOC: Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. 56.4.12 FDCAN Error Counter Register (FDCAN_ECR) Address: 0x0040 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 RP r 23 22 21 r r r 19 18 17 16 CEL[7:0] r r r r r r r r 7 6 5 4 3 2 1 0 r r r TREC[6:0] r 20 TEC[7:0] r r r r r r r r Bits 31: 24 Reserved Bits 23: 16 CEL: CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read. Bit 15 RP: Receive Error Passive 0: The Receive Error Counter is below the error passive level of 128 1: The Receive Error Counter has reached the error passive level of 128 Bits 14: 8 TREC: Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127. Bits 7: 0 TEC: Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 2440/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.13 FDCAN Protocol Status Register (FDCAN_PSR) Address: 0x0044 Reset value: 0x0000 0707 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 Res. PXE REDL RBRS RESI BO EW EP rw rw rw rw rw rw rw DLEC[2:0] rw rw rw 22 21 20 19 18 17 16 rw rw rw rw 3 2 1 0 TDCV[6:0] ACT[1:0] rw rw LEC[2:0] rw rw rw Bits 31: 23 Reserved Bits 22: 16 TDCV: Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. Bit 15 Reserved Bit 14 PXE: Protocol Exception Event 0: No protocol exception event occurred since last read access 1: Protocol exception event occurred Bit 13 REDL: Received FDCAN Message This bit is set independent of acceptance filtering. 0: Since this bit was reset by the CPU, no FDCAN message has been received 1: Message in FDCAN format with EDL flag set has been received Access type is RX: reset on read. Bit 12 RBRS: BRS flag of last received FDCAN Message This bit is set together with REDL, independent of acceptance filtering. 0: Last received FDCAN message did not ha ve its BRS flag set 1: Last received FDCAN message had its BRS flag set Access type is RX: reset on read. Bit 11 RESI: ESI flag of last received FDCAN Message This bit is set together with REDL, independent of acceptance filtering. 0: Last received FDCAN message did not ha ve its ESI flag set 1: Last received FDCAN message had its ESI flag set Access type is RX: reset on read. Bits 10: 8 DLEC: Data Last Error Code Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read. DocID029587 Rev 3 2441/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 7 BO: Bus_Off Status 0: The FDCAN is not Bus_Off 1: The FDCAN is in Bus_Off state Bit 6 EW: Warning Status 0: Both error counters are below the Error_Warning limit of 96 1: At least one of error counter has reached the Error_Warning limit of 96 Bit 5 EP: Error Passive 0: The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1: The FDCAN is in the Error_Passive state Bits 4: 3 ACT: Activity Monitors the module’s CAN communication state. 00: Synchronizing: node is synchronizing on CAN communication 01: Idle: node is neither receiver nor transmitter 10: Receiver: node is operating as receiver 11: Transmitter: node is operating as transmitter Bits 2: 0 LEC: Last Error Code The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error. 000: No Error: No error occurred since LEC has been reset by successful reception or transmission. 001: Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 010: Form Error: A fixed format part of a received frame has the wrong format. 011: AckError: The message transmitted by the FDCAN was not acknowledged by another node. 100: Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. 101: Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 110: CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 111: NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Access type is RS: set on read. Note: When a frame in FDCAN format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in FLEC instead of LEC. An error in a fixed stuff bit of a FDCAN CRC sequence will be shown as a Form Error, not Stuff Error Note: The Bus_Off recovery sequence (see CAN Specification Rev. 2.0 or ISO11898-1) cannot be shortened by setting or resetting CCCR[INIT]. If the device goes Bus_Off, it will set CCCR.INIT of its own, stopping all bus activities. Once CCCR[INIT] has been cleared by the 2442/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) CPU, the device will then wait for 129 occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the reset of CCCR[INIT], each time a sequence of 11 recessive bits has been monitored, a Bit0 Error code is written to PSR[LEC], enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR[REC] is used to count these sequences. 56.4.14 FDCAN Transmitter Delay Compensation Register (FDCAN_TDCR) Address: 0x0048 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r Res. TDCO[6:0] r r r r Res. r r r TDCF[6:0] r r r r Bits 31: 15 Reserved Bits 14: 8 TDCO: Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. Bit 7 Reserved Bits 6: 0 TDCF: Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. 56.4.15 FDCAN Interrupt Register (FDCAN_IR) The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ‘0’ has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. Address: 0x0050 Reset value: 0x0000 0000 DocID029587 Rev 3 2443/3178 2501 FD Controller Area Network (FDCAN) RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. ARA PED PEA WDI BO EW EP ELO Res. Res. DRX TOO MRAF TSW rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEFL TEFF TEFW TEFN TFE TCF TC HPM RF1L RF1F RF1W RF1N RF0L RF0F RF0W RF0N rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 30 Reserved Bit 29 ARA: Access to Reserved Address 0: No access to reserved address occurred 1: Access to reserved address occurred Bit 28 PED: Protocol Error in Data Phase (Data Bit Time is used) 0: No protocol error in data phase 1: Protocol error in data phase detected (PSR.DLEC different from 0,7) Bit 27 PEA: Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0: No protocol error in arbitration phase 1: Protocol error in arbitration phase detected (PSR.LEC different from 0,7) Bit 26 WDI: Watchdog Interrupt 0: No Message RAM Watchdog event occurred 1: Message RAM Watchdog event due to missing READY Bit 25 BO: Bus_Off Status 0: Bus_Off status unchanged 1: Bus_Off status changed Bit 24 EW: Warning Status 0: Error_Warning status unchanged 1: Error_Warning status changed Bit 23 EP: Error Passive 0: Error_Passive status unchanged 1: Error_Passive status changed Bit 22 ELO: Error Logging Overflow 0: CAN Error Logging Counter did not overflow 1: Overflow of CAN Error Logging Counter occurred Bits 21: 20 Reserved Bit 19 DRX: Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0: No Rx Buffer updated 1: At least one received message stored into a Rx Buffer Bit 18 TOO: Timeout Occurred 0: No timeout 1: Timeout reached 2444/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bit 17 MRAF: Message RAM Access Failure The flag is set when the Rx Handler l Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. l Was unable to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated or the New Data flag for a dedicated Rx Buffer is not set. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_TTCAN is switched into Restricted Operation Mode (see Restricted Operation Mode). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0: No Message RAM access failure occurred 1: Message RAM access failure occurred Bit 16 TSW: Timestamp Wraparound 0: No timestamp counter wrap-around 1: Timestamp counter wrapped around Bit 15 TEFL: Tx Event FIFO Element Lost 0: No Tx Event FIFO element lost 1: Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero Bit 14 TEFF: Tx Event FIFO Full 0: Tx Event FIFO not full 1: Tx Event FIFO full Bit 13 TEFW: Tx Event FIFO Watermark Reached 0: Tx Event FIFO fill level below watermark 1: Tx Event FIFO fill level reached watermark Bit 12 TEFN: Tx Event FIFO New Entry 0: Tx Event FIFO unchanged 1: Tx Handler wrote Tx Event FIFO element Bit 11 TFE: Tx FIFO Empty 0: Tx FIFO non-empty 1: Tx FIFO empty Bit 10 TCF: Transmission Cancellation Finished 0: No transmission cancellation finished 1: Transmission cancellation finished Bit 9 TC: Transmission Completed 0: No transmission completed 1: Transmission completed Bit 8 HPM: High Priority Message 0: No high priority message received 1: High priority message received DocID029587 Rev 3 2445/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 7 RF1L: Rx FIFO 1 Message Lost 0: No Rx FIFO 1 message lost 1: Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Bit 6 RF1F: Rx FIFO 1 Full 0: Rx FIFO 1 not full 1: Rx FIFO 1 full Bit 5 RF1W: Rx FIFO 1 Watermark Reached 0: Rx FIFO 1 fill level below watermark 1: Rx FIFO 1 fill level reached watermark Bit 4 RF1N: Rx FIFO 1 New Message 0: No new message written to Rx FIFO 1 1: New message written to Rx FIFO 1 Bit 3 RF0L: Rx FIFO 0 Message Lost 0: No Rx FIFO 0 message lost 1: Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Bit 2 RF0F: Rx FIFO 0 Full 0: Rx FIFO 0 not full 1: Rx FIFO 0 full Bit 1 RF0W: Rx FIFO 0 Watermark Reached 0: Rx FIFO 0 fill level below watermark 1: Rx FIFO 0 fill level reached watermark Bit 0 RF0N: Rx FIFO 0 New Message 0: No new message written to Rx FIFO 0 1: New message written to Rx FIFO 0 56.4.16 FDCAN Interrupt Enable Register (FDCAN_IE) The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. Address: 0x0054 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. ARAE PEDE PEAE WDIE BOE EWE EPE ELOE BEUE BECE DRXE rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFEE TCFE TCE HPME rw rw rw rw TEFLE TEFFE TEFWE TEFNE rw rw rw rw 17 16 TOOE MRAFE TSWE RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE rw rw rw Bits 31: 30 Reserved Bit 29 ARAE: Access to Reserved Address Enable Bit 28 PEDE: Protocol Error in Data Phase Enable Bit 27 PEAE: Protocol Error in Arbitration Phase Enable 2446/3178 18 DocID029587 Rev 3 rw rw rw rw rw RM0433 FD Controller Area Network (FDCAN) Bit 26 WDIE: Watchdog Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 25 BOE: Bus_Off Status 0: Interrupt disabled 1: Interrupt enabled Bit 24 EWE: Warning Status Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 23 EPE: Error Passive Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 22 ELOE: Error Logging Overflow Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 21 BEUE: Bit Error Uncorrected Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 20 BECE: Bit Error Corrected Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 19 DRXE: Message stored to Dedicated Rx Buffer Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 18 TOOE: Timeout Occurred Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 17 MRAFE: Message RAM Access Failure Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 16 TSWE: Timestamp Wraparound Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 15 TEFLE: Tx Event FIFO Element Lost Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 14 TEFFE: Tx Event FIFO Full Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 13 TEFWE: Tx Event FIFO Watermark Reached Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled DocID029587 Rev 3 2447/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 12 TEFNE: Tx Event FIFO New Entry Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 11 TFEE: Tx FIFO Empty Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 10 TCFE: Transmission Cancellation Finished Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 9 TCE: Transmission Completed Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 8 HPME: High Priority Message Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 7 RF1LE: Rx FIFO 1 Message Lost Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 6 RF1FE: Rx FIFO 1 Full Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 5 RF1WE: Rx FIFO 1 Watermark Reached Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 4 RF1NE: Rx FIFO 1 New Message Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 3 RF0LE: Rx FIFO 0 Message Lost Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 2 RF0FE: Rx FIFO 0 Full Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 1 RF0WE: Rx FIFO 0 Watermark Reached Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled Bit 0 RF0NE: Rx FIFO 0 New Message Interrupt Enable 0: Interrupt disabled 1: Interrupt enabled 2448/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.17 FDCAN Interrupt Line Select Register (FDCAN_ILS) The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. Address: 0x0058 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. ARAL PEDL PEAL WDIL BOL EWL EPL ELOL BEUL BECL DRXL TOOL MRAFL TSWL rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFEL TCFL TCL HPML RF1LL rw rw rw rw rw TEFLL rw TEFFL TEFWL TEFNL rw rw rw RF1FL RF1WL RF1NL rw rw rw RF0LL rw RF0FL RF0WL RF0NL rw rw rw Bits 31: 30 Reserved Bit 29 ARAL: Access to Reserved Address Line Bit 28 PEDL: Protocol Error in Data Phase Line Bit 27 PEAL: Protocol Error in Arbitration Phase Line Bit 26 WDIL: Watchdog Interrupt Line Bit 25 BOL: Bus_Off Status Bit 24 EWL: Warning Status Interrupt Line Bit 23 EPL: Error Passive Interrupt Line Bit 22 ELOL: Error Logging Overflow Interrupt Line Bit 21 BEUL: Bit Error Uncorrected Interrupt Line Bit 20 BECL: Bit Error Corrected Interrupt Line Bit 19 DRXL: Message stored to Dedicated Rx Buffer Interrupt Line Bit 18 TOOL: Timeout Occurred Interrupt Line Bit 17 MRAFL: Message RAM Access Failure Interrupt Line Bit 16 TSWL: Timestamp Wraparound Interrupt Line Bit 15 TEFLL: Tx Event FIFO Element Lost Interrupt Line Bit 14 TEFFL: Tx Event FIFO Full Interrupt Line Bit 13 TEFWL: Tx Event FIFO Watermark Reached Interrupt Line Bit 12 TEFNL: Tx Event FIFO New Entry Interrupt Line Bit 11 TFEL: Tx FIFO Empty Interrupt Line Bit 10 TCFL: Transmission Cancellation Finished Interrupt Line Bit 9 TCL: Transmission Completed Interrupt Line Bit 8 HPML: High Priority Message Interrupt Line Bit 7 RF1LL: Rx FIFO 1 Message Lost Interrupt Line DocID029587 Rev 3 2449/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 6 RF1FL: Rx FIFO 1 Full Interrupt Line Bit 5 RF1WL: Rx FIFO 1 Watermark Reached Interrupt Line Bit 4 RF1NL: Rx FIFO 1 New Message Interrupt Line Bit 3 RF0LL: Rx FIFO 0 Message Lost Interrupt Line Bit 2 RF0FL: Rx FIFO 0 Full Interrupt Line Bit 1 RF0WL: Rx FIFO 0 Watermark Reached Interrupt Line Bit 0 RF0NL: Rx FIFO 0 New Message Interrupt Line 56.4.18 FDCAN Interrupt Line Enable Register (FDCAN_ILE) Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. Address: 0x005C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EINT1 EINT0 rw rw Bits 31: 2 Reserved Bit 1 EINT1: Enable Interrupt Line 1 0: Interrupt line fdcan_intr0_it disabled 1: Interrupt line fdcan_intr0_it enabled Bit 0 EINT0: Enable Interrupt Line 0 0: Interrupt line fdcan_intr1_it disabled 1: Interrupt line fdcan_intr1_it enabled 2450/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.19 FDCAN Global Filter Configuration Register (FDCAN_GFC) Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure 729: Standard Message ID filter path and Figure 730: Extended Message ID filter path. Address: 0x0080 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RRFS RRFE rw rw ANFS[1:0] ANFE[1:0] rw rw rw rw Bits 31: 6 Reserved Bits 5: 4 ANFS: Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00: Accept in Rx FIFO 0 01: Accept in Rx FIFO 1 10: Reject 11: Reject These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 3: 2 ANFE: Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00: Accept in Rx FIFO 0 01: Accept in Rx FIFO 1 10: Reject 11: Reject These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 1 RRFS: Reject Remote Frames Standard 0: Filter remote frames with 11-bit standard IDs 1: Reject all remote frames with 11-bit standard IDs These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 0 RRFE: Reject Remote Frames Extended 0: Filter remote frames with 29-bit standard IDs 1: Reject all remote frames with 29-bit standard IDs These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. DocID029587 Rev 3 2451/3178 2501 FD Controller Area Network (FDCAN) 56.4.20 RM0433 FDCAN Standard ID Filter Configuration Register (FDCAN_SIDFC) Settings for 11-bit standard Message ID filtering.The Standard ID Filter Configuration controls the filter path for standard messages as described in Figure 729: Standard Message ID filter path. Address: 0x0084 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 LSS[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. FLSSA[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 24 Reserved Bits 23: 16 LSS: List Size Standard 0: No standard Message ID filter 1-128: Number of standard Message ID filter elements >128: Values greater than 128 are interpreted as 128. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 FLSSA: Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Table 470: Standard Message ID Filter element).These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved 56.4.21 FDCAN Extended ID Filter Configuration Register (FDCAN_XIDFC) Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages as described in Figure 730: Extended Message ID filter path. Address: 0x0088 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 LSE[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. FLESA[13:0] rw rw 2452/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 rw rw rw rw RM0433 FD Controller Area Network (FDCAN) Bits 31: 24 Reserved Bits 23: 16 LSE: List Size Extended 0: No standard Message ID filter 1-128: Number of standard Message ID filter elements >128: Values greater than 128 are interpreted as 128. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 FLESA: Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Table 472: Extended Message ID Filter element). These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved 56.4.22 FDCAN Extended ID and Mask Register (FDCAN_XIDAM) Address: 0x0090 Reset value: 0x1FFF FFFF 31 30 29 Res. Res. Res. 15 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 EIDM[28:16] rw rw rw rw rw rw rw rw rw rw rw rw rw 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw EIDM[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 29 Reserved Bits 28: 0 EIDM: Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. DocID029587 Rev 3 2453/3178 2501 FD Controller Area Network (FDCAN) 56.4.23 RM0433 FDCAN High Priority Message Status Register (FDCAN_HPMS) This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. Address: 0x0094 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r FLST FIDX[6:0] r r r r r MSI[1:0] r r r r BIDX[5:0] r r r r r Bits 31: 16 Reserved Bit 15 FLST: Filter List Indicates the filter list of the matching filter element. 0: Standard Filter List 1: Extended Filter List Bits 14: 8 FIDX: Filter Index Index of matching filter element. Range is 0 to SIDFC[LSS] - 1 or XIDFC[LSE] - 1. Bits 7: 6 MSI: Message Storage Indicator 00: No FIFO selected 01: FIFO overrun 10: Message stored in FIFO 0 11: Message stored in FIFO 1 Bits 5: 0 BIDX: Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. 56.4.24 FDCAN New Data 1 Register (FDCAN_NDAT1) Address: 0x0098 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ND31 ND30 ND29 ND28 ND27 ND26 ND25 ND24 ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND15 ND14 ND13 ND12 ND11 ND10 ND9 ND8 ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 2454/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 31: 0 NDn: New Data[31:0] The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0: Rx Buffer not updated 1: Rx Buffer updated from new message 56.4.25 FDCAN New Data 2 Register (FDCAN_NDAT2) Address: 0x009C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ND63 ND62 ND61 ND60 ND59 ND58 ND57 ND56 ND55 ND54 ND53 ND52 ND51 ND50 ND49 ND48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40 ND39 ND38 ND37 ND36 ND35 ND34 ND33 ND32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 0 NDn: New Data[63:32] The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0: Rx Buffer not updated 1: Rx Buffer updated from new message 56.4.26 FDCAN Rx FIFO 0 Configuration Register (FDCAN_RXF0C) Address: 0x00A0 Reset value: 0x0000 0000 31 30 29 28 F0OM 15 27 26 25 24 F0WM[7:0] 23 22 21 20 Res. rw rw rw rw rw rw rw 14 13 12 11 10 9 8 19 18 17 16 F0S[7:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 Res. Res. 7 F0SA[13:0] rw rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 rw rw rw rw 2455/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 31 F0OM: FIFO 0 Operation mode FIFO 0 can be operated in blocking or in overwrite mode. 0: FIFO 0 blocking mode 1: FIFO 0 overwrite mode Bits 30: 24 F0WM: FIFO 0 Watermark 0: Watermark interrupt disabled 1-64: Level for Rx FIFO 0 watermark interrupt (IR[RF0W]) >64: Watermark interrupt disabled These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 23 Reserved Bits 22: 16 F0S:Rx FIFO 0 Size 0: No Rx FIFO 0 1-64: Number of Rx FIFO 0 elements >64: Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1. Bits 15: 2 F0SA:Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 728: Message RAM configuration). Bits 1: 0 Reserved 56.4.27 FDCAN Rx FIFO 0 Status Register (FDCAN_RXF0S) Address: 0x00A4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. RF0L F0F Res. Res. rw rw 15 14 13 12 11 10 9 8 7 6 Res. Res. F0GI[5:0] rw rw rw rw 21 20 rw 18 17 16 F0PI[5:0] rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw Res. rw 19 F0FL[6:0] rw rw rw rw Bits 31: 26 Reserved Bit 25 RF0L: Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset. 0: No Rx FIFO 0 message lost 1: Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Bit 24 F0F: Rx FIFO 0 Full 0: Rx FIFO 0 not full 1: Rx FIFO 0 full Bits 23: 22 Reserved Bits 21: 16 F0PI: Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63. 2456/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 15: 14 Reserved Bits 13: 8 F0GI: Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63. Bit 7 Reserved Bits 6: 0 F0FL: Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64. 56.4.28 FDCAN Rx FIFO 0 Acknowledge Register (FDCAN_RXF0A) Address: 0x00A8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw F0AI[5:0] rw rw rw rw Bits 31: 6 Reserved Bit 25 FA01: Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 Fill Level RXF0S[F0FL]. 56.4.29 FDCAN Rx Buffer Configuration Register (FDCAN_RXBC) Address: 0x00AC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. RBSA[13:0] rw rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 rw rw rw rw 2457/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bits 31: 16 Reserved Bits 15: 2 RBSA: Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). Also used to reference debug messages A,B,C. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved 56.4.30 FDCAN Rx FIFO 1 Configuration Register (FDCAN_RXF1C) Address: 0x00B0 Reset value: 0x0000 0000 31 30 29 28 F1OM 15 27 26 25 24 F1WM[7:0] 23 22 21 20 Res. rw rw rw rw rw rw rw 14 13 12 11 10 9 8 19 18 17 16 F1S[7:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 Res. Res. 7 F1SA[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 F1OM: FIFO 1Operation mode FIFO 1 can be operated in blocking or in overwrite mode. 0: FIFO 1 blocking mode 1: FIFO 1 overwrite mode Bits 30: 24 F1WM: Rx FIFO 1 Watermark 0: Watermark interrupt disabled 1-64: Level for Rx FIFO 1 watermark interrupt (IR[RF1W]) >64: Watermark interrupt disabled. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 23 Reserved Bits 22: 16 F1S: Rx FIFO 1 Size 0: No Rx FIFO 1 1-64: Number of Rx FIFO 1 elements >64: Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 F1SA: Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 728: Message RAM configuration). These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved 2458/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.31 FDCAN Rx FIFO 1 Status Register (FDCAN_RXF1S) Address: 0x00B4 Reset value: 0x0000 0000 31 30 DMS[1:0] r r 15 14 Res. Res. 29 28 27 26 25 24 23 22 Res. Res. Res. Res. RF1L F1F Res. Res. r r 13 12 11 10 9 8 7 6 F1GI[6:0] r r r r 21 20 r 18 17 16 F1PI[6:0] r r r r r r 5 4 3 2 1 0 r r r Res. r 19 F1FL[7:0] r r r r Bits 31: 30 DMS: Debug Message Status 00: Idle state, wait for reception of debug messages, DMA request is cleared 01: Debug message A received 10: Debug messages A, B received 11: Debug messages A, B, C received, DMA request is set Bits 29: 26 Reserved Bit 25 RF1L: Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset. 0: No Rx FIFO 1 message lost 1: Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. Bits 30: 24 F1F: Rx FIFO 1 Full 0: Rx FIFO 1 not full 1: Rx FIFO 1 full Bits 23: 22 Reserved Bits 21: 16 F1PI: Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. Bits 15: 14 Reserved Bits 13: 8 F1GI: Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. Bit 7 Reserved Bits 6: 0 F1FL: Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64 DocID029587 Rev 3 2459/3178 2501 FD Controller Area Network (FDCAN) 56.4.32 RM0433 FDCAN Rx FIFO 1 Acknowledge Register (FDCAN_RXF1A) Address: 0x00B8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw F1AI[5:0] rw rw rw rw Bits 31: 6 Reserved Bits 5: 0 F1AI: Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]. 56.4.33 FDCAN Rx Buffer Element Size Configuration Register (FDCAN_RXESC) Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. Address: 0x00BC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. RBDS[2:0] r r Res. r Bits 31: 11 Reserved Bits 10: 8 RBDS: Rx Buffer Data Field Size: 000: 8 byte data field 001: 12 byte data field 010: 16 byte data field 011: 20 byte data field 100: 24 byte data field 101: 32 byte data field 110: 48 byte data field 111: 64 byte data field 2460/3178 DocID029587 Rev 3 F1DS[2:0] r r Res. r F0DS[2:0] r r r RM0433 FD Controller Area Network (FDCAN) Bit 7 Reserved Bits 6: 4 F1DS: Rx FIFO 0 Data Field Size: 000: 8 byte data field 001: 12 byte data field 010: 16 byte data field 011: 20 byte data field 100: 24 byte data field 101: 32 byte data field 110: 48 byte data field 111: 64 byte data field Bit 3 Reserved Bits 2: 0 F0DS: Rx FIFO 1 Data Field Size: 000: 8 byte data field 001: 12 byte data field 010: 16 byte data field 011: 20 byte data field 100: 24 byte data field 101: 32 byte data field 110: 48 byte data field 111: 64 byte data field 56.4.34 FDCAN Tx Buffer Configuration Register (FDCAN_TXBC) Address: 0x00C0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. TFQM rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 TFQS[5:0] 23 22 Res. Res. 7 6 21 20 19 18 rw rw rw rw rw rw rw rw rw 16 NTDB[5:0] rw rw rw rw rw rw 5 4 3 2 1 0 Res. Res. TBSA[13:0] rw 17 rw rw rw rw Bit 31 Reserved Bit 30 TFQM: Tx FIFO/Queue Mode. 0: Tx FIFO operation 1: Tx Queue operation. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 29: 24 TFQS: Transmit FIFO/Queue Size. 0: No Tx FIFO/Queue 1-32: Number of Tx Buffers used for Tx FIFO/Queue >32: Values greater than 32 are interpreted as 32. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. DocID029587 Rev 3 2461/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bits 23: 22 Reserved Bits 21: 16 NDTB: Number of Dedicated Transmit Buffers. 0: No Dedicated Tx Buffers 1-32: Number of Dedicated Tx Buffers >32: Values greater than 32 are interpreted as 32. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 [TBSA: Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 728). These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved Note: The sum of TFQS and NDTB cannot be larger than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. 56.4.35 FDCAN Tx FIFO/Queue Status Register (FDCAN_TXFQS) The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). Address: 0x00C4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TFQF 15 14 13 12 Res. Res. Res. 11 10 9 8 TFGI[4:0] r r r r 7 6 Res. Res. r 20 19 18 17 16 TFQPI[4:0] r r r r r r 5 4 3 2 1 0 r r TFFL[5:0] r r r r Bit 31: 22 Reserved Bit 21 TFQF: Tx FIFO/Queue Full 0 Tx FIFO/Queue not full 1 Tx FIFO/Queue full Bits 20: 16 TFQPI: Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31 Bits 15: 13 Reserved Bits 12: 8 [TFGI: Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) 2462/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 7: 6 Reserved Bits 5: 0 TFFL: Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC[TFQM] = ‘1’). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Index indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. For example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 56.4.36 FDCAN Tx Buffer Element Size Configuration Register (FDCAN_TXESC) Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes >8 bytes are intended for CAN FD operation only. Address: 0x00C8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TBDS[2:0] r r r Bit 31: 3 Reserved Bit 21 TBDS: Tx Buffer Data Field Size: 000: 8 byte data field 001: 12 byte data field 010: 16 byte data field 011: 20 byte data field 100: 24 byte data field 101: 32 byte data field 110: 48 byte data field 111: 64 byte data field DocID029587 Rev 3 2463/3178 2501 FD Controller Area Network (FDCAN) 56.4.37 RM0433 FDCAN Tx Buffer Request Pending Register (FDCAN_TXBRP) Address: 0x00C8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TRP[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r TRP[15:0] r r r r r r r r r Bits 31: 0 TRP:Transmission Request Pending. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Filtering for Debug messages) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF – after successful transmission together with the corresponding TXBTO bit – when the transmission has not yet been started at the point of cancellation – when the transmission has been aborted due to lost arbitration – when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0: No transmission request pending 1: Transmission request pending Note: 2464/3178 TXBRP bits set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is canceled immediately, the corresponding TXBRP bit is reset. DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.38 FDCAN Tx Buffer Add Request Register (FDCAN_TXBAR) Address: 0x00D0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw AR[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 AR:Add Request Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0: No transmission request added 1: Transmission requested added. Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), the request is ignored. 56.4.39 FDCAN Tx Buffer Cancellation Request Register (FDCAN_TXBCR) Address: 0x00D4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CR[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 CR: Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding TXBRP bit is reset. 0: No cancellation pending 1: Cancellation pending DocID029587 Rev 3 2465/3178 2501 FD Controller Area Network (FDCAN) 56.4.40 RM0433 FDCAN Tx Buffer Transmission Occurred Register (FDCAN_TXBTO) Address: 0x00D8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TO[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r TO[15:0] r r r r r r r r r Bits 31: 0 TO: Transmission Occurred. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0: No transmission occurred 1: Transmission occurred 56.4.41 FDCAN Tx Buffer Cancellation Finished Register (FDCAN_TXBCF) Address: 0x00DC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CF[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CF[15:0] r r r r r r r r r Bits 31: 0 CF: Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0: No transmit buffer cancellation 1: Transmit buffer cancellation finished 2466/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.42 FDCAN Tx Buffer Transmission Interrupt Enable Register (FDCAN_TXBTIE) Address: 0x00E0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIE[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TIE[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 TIE: Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0: Transmission interrupt disabled 1: Transmission interrupt enable 56.4.43 FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register (FDCAN_ TXBCIE) Address: 0x00E4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFIE[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CFIE[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 CF: Cancellation Finished Interrupt Enable. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0: Cancellation finished interrupt disabled 1: Cancellation finished interrupt enabled DocID029587 Rev 3 2467/3178 2501 FD Controller Area Network (FDCAN) 56.4.44 RM0433 FDCAN Tx Event FIFO Configuration Register (FDCAN_TXEFC) Address: 0x00F0 Reset value: 0x0000 0000 31 30 Res. Res. 15 14 29 28 27 26 25 24 EFWM[5:0] rw rw rw rw rw rw 13 12 11 10 9 8 23 22 Res. Res. 7 6 21 20 19 18 rw rw rw rw rw rw rw rw rw 16 EFS[5:0] rw rw rw rw rw rw 5 4 3 2 1 0 Res. Res. EFSA[15:0] rw 17 rw rw rw rw Bits 31: 30 Reserved Bits 29: 24 EFWM: Event FIFO Watermark 0: Watermark interrupt disabled 1-32: Level for Tx Event FIFO watermark interrupt (IR[TEFW]) >32: Watermark interrupt disabled These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 23: 22 Reserved Bits 21: 16 EFS: Event FIFO Size. 0: Tx Event FIFO disabled 1-32: Number of Tx Event FIFO elements >32: Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS-1. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 EFSA: Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 728: Message RAM configuration). These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved 2468/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.45 FDCAN Tx Event FIFO Status Register (FDCAN_TXEFS) Address: 0x00F4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. TEFL EFF Res. Res. Res. r r 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. EFGI[4:0] r r r r 20 19 18 17 16 EFPI[4:0] r r r r r 4 3 2 1 0 r r EFFL[5:0] r r r r r Bits 31: 26 Reserved Bit 25 TEFL: Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. Bit 24 EFF: Event FIFO Full. 0: Tx Event FIFO not full 1: Tx Event FIFO full Bits 23: 21 Reserved Bits 20: 16 EFPI: Event FIFO Put Index. Tx Event FIFO write index pointer, range 0 to 31. Bits 15: 13 Reserved Bits 12: 8 EFGI: Event FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31. Bits 7: 6 Reserved Bits 5: 0 EFFL: Event FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 31. 56.4.46 FDCAN Tx Event FIFO Acknowledge Register (FDCAN_TXEFA) Address: 0x00F8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw EFAI[4:0] rw DocID029587 Rev 3 rw rw 2469/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bits 31: 5 Reserved Bit 25 EFAI: Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO, it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS[EFGI] to EFAI + 1 and update the FIFO 0 Fill Level TXEFS[EFFL]. 56.4.47 FDCAN TT Trigger Memory Configuration Register (FDCAN_TTTMC) Address: 0x100 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 22 21 20 19 18 17 16 TME[6:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 Res. Res. TMSA[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 23 Reserved Bits 22: 16 TME: Trigger Memory Elements. 0: No Trigger Memory 1-64: Number of Trigger Memory elements >64: Values greater than 64 are interpreted as 64 These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 2 TMSA: Trigger Memory Start Address. Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 728: Message RAM configuration). These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 1: 0 Reserved 2470/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.48 FDCAN TT Reference Message Configuration Register (FDCAN_TTRMC) Address: 0x0104 Reset value: 0x0000 0000 31 30 29 RMPS XTD Res. rw rw 15 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 RID[29:16] rw rw rw rw rw rw rw rw rw rw rw rw rw 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw RID[15:0] rw rw rw rw rw rw rw rw rw Bit 31 RMPS: Reference Message Payload Select Ignored in case of time slaves. 0: Reference message has no additional payload 1: The following elements are taken from Tx Buffer 0: Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB (Level 1: bytes 2-8, Level 0, 2: bytes 5-8) These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 30 XTD: Extended Identifier 0: 11-bit standard identifier 1: 29-bit extended identifier These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 29 Reserved Bits 28: 0 RID: Reference Identifier. Identifier transmitted with Reference message and used for Reference message filtering. Standard or extended reference identifier depending on bit XTD. A standard identifier has to be written to ID[28:18]. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. DocID029587 Rev 3 2471/3178 2501 FD Controller Area Network (FDCAN) 56.4.49 RM0433 FDCAN TT Operation Configuration Register (FDCAN_TTOCF) Address: 0x0108 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. EVTP ECC EGTF rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 EECS rw 23 rw rw rw 21 LDSDL[2:0] rw rw rw 20 19 18 17 16 rw rw rw rw 3 2 1 0 TM GEN Res. rw rw AWL[7:0] IRTO[6:0] rw 22 rw rw rw OM[1:0] rw rw Bits 31: 27 Reserved Bit 26 EVTP: Event Trigger Polarity. 0: Rising edge trigger 1: Falling edge trigger These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 25 ECC: Enable Clock Calibration. 0: Automatic clock calibration in FDCAN Level 0, 2 is disabled 1: Automatic clock calibration in FDCAN Level 0, 2 is enabled These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 24 EGTF: Enable Global Time Filtering. 0: Global time filtering in FDCAN Level 0, 2 is disabled 1: Global time filtering in FDCAN Level 0, 2 is enabled These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 23: 16 AWL: Application Watchdog Limit. The application watchdog can be disabled by programming AWL to 0x00. 0x00–FF: Maximum time after which the application has to serve the application watchdog. The application watchdog is incremented once each 256 NTUs. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 15 EECS: Enable External Clock Synchronization If enabled, TUR configuration (TURCF[NCL] only) may be updated during FDCAN operation. 0: External clock synchronization in FDCAN Level 0,2 disabled 1: External clock synchronization in FDCAN Level 0,2 enabled These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 14: 8 IRTO: Initial Reference Trigger Offset. 0x00–7F Positive offset, range from 0 to 127 These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. 2472/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 7:5 LDSDL: LD of Synchronization Deviation Limit. The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL= 2*(LDSDL + 5). SDL is comprised between 32 and 4096. It should not exceed the clock tolerance given by the CAN bit timing configuration. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 4 TM: Time Master. 0: Time Master function disabled 1: Potential Time Master These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 3 GEN: Gap Enable. 0: Strictly time-triggered operation 1: External event-synchronized time-triggered operation These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 2 Reserved Bits 1: 0 OM: Operation Mode. 00: Event-driven CAN communication, default 01: TTCAN level 1 10: TTCAN level 2 11: TTCAN level 0 These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. 56.4.50 FDCAN TT Matrix Limits Register (FDCAN_TTMLM) Address: 0x010C Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 ENTT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw TXEW[3:0] rw rw CSS[1:0] rw rw rw rw CCM[5:0] rw rw rw rw Bits 31: 28 Reserved Bits 27: 16 ENTT: Expected Number of Tx Triggers 0x000–FFF Expected number of Tx Triggers in one Matrix Cycle. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 12 Reserved DocID029587 Rev 3 2473/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bits 11: 8 TXEW: Tx Enable Window 0x0–F Length of Tx enable window, 1-16 NTU cycles These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 7: 6 CSS: Cycle Start Synchronization Enables sync pulse output . 00: No sync pulse 01: Sync pulse at start of basic cycle 10: Sync pulse at start of matrix cycle 11: Reserved These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bit 5: 0 CCM: Cycle Count Max 0x00: 1 Basic Cycle per Matrix Cycle 0x01: 2 Basic Cycles per Matrix Cycle 0x03: 4 Basic Cycles per Matrix Cycle 0x07: 8 Basic Cycles per Matrix Cycle 0x0F: 16 Basic Cycles per Matrix Cycle 0x1F: 32 Basic Cycles per Matrix Cycle 0x3F: 64 Basic Cycles per Matrix Cycle Others: Reserved These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Note: ISO 11898-4, Section 5.2.1 requires that only the listed cycle count values are configured. Other values are possible, but may lead to inconsistent matrix cycles. 56.4.51 FDCAN TUR Configuration Register (FDCAN_TURCF) The length of the NTU is given by: NTU = CAN Clock Period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for TURNA[NAV[15:0]]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. • Level 1: NC 4 × DC and NTU = CAN bit time • Levels 0 and 2: NC 8 × DC The actual value of TUR may be changed by the clock drift compensation function of TTCAN Level 0 and Level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, TURNA[NAV] may be adjusted around NC in the range of the Synchronization Deviation Limit given by TTOCF[LDSDL]. NC and DC should be programmed to the largest suitable values in order to allow the best computational accuracy for the drift compensation process. Address: 0x0110 Reset value: 0x1000 0000 2474/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 31 30 ELT Res. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DC[14:0] rw r rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NCL[15:0] rw rw rw rw rw rw rw rw rw Bit 31 ELT: Enable Local Time. 0: Local time is stopped, default 1: Local time is enabled These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Note: The local time is started by setting ELT. It remains active until ELT is reset or until the next hardware reset. TURCF[DC] is locked when TURCF[ELT] = ‘1’. If ELT is written to ‘0’, the readable value will stay at ‘1’ until the new value has been synchronized into the CAN clock domain. During this time write access to the other bits of the register remains locked. Bit 30 Reserved Bits 29: 16 DC: Denominator Configuration. 0x0000: Illegal value 0x0001 to 3FFF: Denominator Configuration These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Bits 15: 0 NCL: Numerator Configuration Low. Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF[ELT] = ‘0’ or if TTOCF[EECS] (external clock synchronization enabled) is set. When a new value for NCL is written outside TT Configuration Mode, the new value takes effect when TTOST.WECS is cleared to ‘0’. NCL is locked TTOST[WECS] is ‘1’. 0x0000–FFFF Numerator Configuration Low These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to ‘1’. Note: If NC < 7 × DC in TTCAN Level 1, then it is required that subsequent Time Marks in the Trigger Memory must differ by at least two NTUs. DocID029587 Rev 3 2475/3178 2501 FD Controller Area Network (FDCAN) 56.4.52 RM0433 FDCAN TT Operation Control Register (FDCAN_TTOCN) Address: 0x0114 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCKC Res. ESCN NIG TMG FGP GCS TTIE SWP ECS SGT rw rw rw rw rw rw rw rw rw r TMC[1:0] rw rw RTIE rw SWS[1:0] rw rw Bits 31: 16 Reserved Bit 15 LCKC: TT Operation Control Register Locked. Set by a write access to register TTOCN. Reset when the updated configuration has been synchronized into the CAN clock domain. 0: Write access to TTOCN enabled 1: Write access to TTOCN locked Bit 14 Reserved Bit 13 ESCN: External Synchronization Control If enabled the FDCAN synchronizes its cycle time phase to an external event signaled by a rising edge at Event Trigger pin (Section 0.1.17, Synchronization to external time schedule). 0: External synchronization disabled 1: External synchronization enabled Bit 12 NIG: Next is Gap. This bit can only be set when the FDCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF[GEN] = ‘1’) 0: No action, reset by reception of any Reference message 1: Transmit next Reference Message with Next_is_Gap = ‘1’ Bit 11 TMG: Time Mark Gap. 0: Reset by each Reference message 1: Next Reference message started when Register Time Mark interrupt TTIR[RTMI] is activated Bit 10 FGP: Finish Gap. Set by the CPU, reset by each reference message 0: No reference message requested 1: Application requested start of reference message DBit 9 GCS: Gap Control Select 0: Gap control independent from Event trigger 1: Gap control by input Event trigger pin 2476/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bit 8 TTIE: Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX. A trigger time mark interrupt pulse is generated when the trigger memory element becomes active, and the FDCAN is in synchronization state In_Schedule or In_Gap. 0: Trigger Time Mark Interrupt output m_ttcan_tmp disabled 1: Trigger Time Mark Interrupt output m_ttcan_tmp enabled Bits 7: 6 TMC: Register Time Mark Compare. 00: No Register Time Mark Interrupt generated 01: Register Time Mark Interrupt if Time Mark = cycle time 10: Register Time Mark Interrupt if Time Mark = local time 11: Register Time Mark Interrupt if Time Mark = global time Note: When changing the time mark reference (cycle, local, global time), it is recommended to first write TMC = ‘00’, then reconfigure TTTMK, and finally set TMC to the intended time reference. Bit 5 RTIE: Register Time Mark Interrupt Pulse Enable. Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse with the length of one m_ttcan_clk period is generated when time referenced by TTOCN[TMC] (cycle, local, or global) equals TTTMK[TM], independent of the synchronization state. 0: Register Time Mark Interrupt output disabled 1: Register Time Mark Interrupt output enabled Bits 4: 3 SWS: Stop Watch Source. 00: Stop Watch disabled 01: Actual value of cycle time is copied to TTCPT[SWV] 10: Actual value of local time is copied to TTCPT[SWV] 11: Actual value of global time is copied to TTCPT[SWV] Bit 2 SWP: Stop Watch Polarity. 0: Rising edge trigger 1: Falling edge trigger Bit 1 ECS: External Clock Synchronization. Writing a ‘1’ to ECS sets TTOST[WECS] if the node is the actual Time Master. ECS is reset after one APB clock period. The external clock synchronization takes effect at the start of the next basic cycle. Bit 0 SGT: Set Global time. Writing a ‘1’ to SGT sets TTOST[WGDT] if the node is the actual Time Master. SGT is reset after one APB clock period. The global time preset takes effect when the node transmits the next Reference message with the Master_Ref_Mark modified by the preset value written to TTGTP. 56.4.53 FDCAN TT Global Time Preset Register (CAN_TTGTP) If TTOST.WGDT is set, the next Reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = ‘1’, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a Reference message with Disc_Bit = ‘1’ becomes valid or if the node is not the current Time Master. TP is locked while TTOST[WGTD] = ‘1’ after setting TTOCN[SGT] until the Reference message with Disc_Bit = ‘1’ becomes valid or until the node is no longer the current Time Master. DocID029587 Rev 3 2477/3178 2501 FD Controller Area Network (FDCAN) RM0433 Address: 0x0118 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CTP[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TP[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 16 CTP: Cycle Time Target Phase. CTP is write-protected while TTOCN[ESCN] or TTOST[SPL] are set (see Section 56.3.15: Synchronization to external time schedule). 0x0000–FFFF Defines target value of cycle time when a rising edge of event trigger is expected Bits 15: 0 NCL: Time Preset. TP is write-protected while TTOST[WGTD] is set. 0x0000–7FFF Next Master Reference Mark = Master Reference Mark + TP 0x8000 reserved 0x8001–FFFF Next Master Reference Mark = Master Reference Mark - (0x10000 - TP). 56.4.54 FDCAN TT Time Mark Register (FDCAN_TTTMK) A time mark interrupt (TTIR[TMI] = ‘1’) is generated when the time base indicated by TTOCN[TMC] (cycle time, local time, or global time) has the same value as TM. Address: 0x011C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 LCKM Res. Res. Res. Res. Res. Res. Res. Res. 22 21 20 19 18 17 16 TICC[6:0] r r r r r r r r r rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TM[15:0] rw rw rw rw rw rw rw rw rw Bit 31 LCKM: TT Time Mark Register Locked. Always set by a write access to registers TTOCN. Set by write access to register TTTMK when TTOCN[TMC] ‘00’. Reset when the registers have been synchronized into the CAN clock domain. 0: Write access to TTTMK enabled 1: Write access to TTTMK locked Bits 30: 23 Reserved 2478/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 22: 16 TICC: Time Mark Cycle Code. Cycle count for which the time mark is valid. 0b000000x valid for all cycles 0b000001c valid every second cycle at cycle count mod2 = c 0b00001cc valid every fourth cycle at cycle count mod4 = cc 0b0001ccc valid every eighth cycle at cycle count mod8 = ccc 0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc 0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc 0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc Bits 15: 0 TM: Time Mark. 0x0000–FFFF Time Mark Note: When using byte access to register TTTMK it is recommended to first disable the time mark compare function (TTOCN[TMC] = ‘00’) to avoid compares on inconsistent register values. 56.4.55 FDCAN TT Interrupt Register (FDCAN_TTIR) The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ‘0’ has no effect. A hard reset will clear the register. Address: 0x0120 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CER AW WT rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IWT ELC SE2 SE1 TXO TXU GTE GTD GTW SWE TTMI RTMI SOG CSM SMC SBC rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 19 Reserved Bit 18 CER: Configuration Error. Trigger out of order. 0: No error found in trigger list 1: Error found in trigger list Bit 17 AW: Application Watchdog. 0: Application watchdog served in time 1: Application watchdog not served in time Bit 16 WT: Watch Trigger. 0: No missing Reference message 1: Missing Reference message (Level 0: cycle time 0xFF00) Bit 15 IWTG: Initialization Watch Trigger. The initialization is restarted by resetting IWT. 0 No missing Reference message during system startup 1 No system startup due to missing Reference message DocID029587 Rev 3 2479/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 14 ELC: Error Level Changed. Not set when error level changed during initialization. 0: No change in error level 1: Error level changed Bit 13 SE2: Scheduling Error 2. 0: No scheduling error 2 1: Scheduling error 2 occurred Bit 12 SE1: Scheduling Error 1. 0: No scheduling error 1 1: Scheduling error 1 occurred Bit 11 TXO: Tx Count Overflow. 0: Number of Tx Trigger as expected 1: More Tx trigger than expected in one cycle Bit 10 TXU: Tx Count Underflow. 0: Number of Tx Trigger as expected 1: Less Tx trigger than expected in one cycle Bit 9 GTE: Global Time Error. Synchronization deviation SD exceeds limit specified by TTOCF[LDSDL], TTCAN Level 0, 2 only. 0: Synchronization deviation within limit 1: Synchronization deviation exceeded limit Bit 8 GTD: Global Time Discontinuity. 0: No discontinuity of global time 1: Discontinuity of global time Bit 7 GTW: Global Time Wrap 0: No global time wrap occurred 1: Global time wrap from 0xFFFF to 0x0000 occurred Bit 6 SWE: Stop Watch Event 0: No rising/falling edge at stop watch trigger pin detected 1 :Rising/falling edge at stop watch trigger pin detected Bit 5 TTMI: Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 56.3.21: FDCAN Trigger memory element). Set when the trigger memory element becomes active, and the FDCAN is in synchronization state In_Gap or In_Schedule. 0: Time mark not reached 1: Time mark reached (Level 0: cycle time TTOCF[RTO] x 0x200) Bit 4 RTMI: Register Time Mark Interrupt. Set when time referenced by TTOCN[TMC] (cycle, local, or global) equals TTTMK[TM], independently from the synchronization state. 0: Time mark not reached 1: Time mark reached BIt 3 SOG: Start of Gap 0 No reference message seen with Next_is_Gap bit set 1 Reference message with Next_is_Gap bit set becomes valid 2480/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bit 2 CSM: Change of Synchronization Mode. 0: No change in master to slave relation or schedule synchronization 1: Master to slave relation or schedule synchronization changed, also set when TTOST[SPL] is reset Bit 1 SMC: Start of Matrix Cycle. 0: No Matrix Cycle started since bit has been reset 1: Matrix Cycle started Bit 0 SBC: Start of Basic Cycle. 0: No Basic Cycle started since bit has been reset 1: Basic Cycle started 56.4.56 FDCAN TT Interrupt Enable Register (FDCAN_TTIE) The settings in the TT Interrupt Enable register determine which status changes in the TT Interrupt Register will result in an interrupt. Address: 0x0124 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CERE AWE WTE rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IWTE ELCE SE2E SE1E TXOE TXUE GTEE GTDE GTWE SWEE TTMIE RTMIE SOGE CSME SMCE SBCE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 19 Reserved Bit 18 CERE: Configuration Error Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 17 AWE: Application Watchdog Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 16 WTE: Watch Trigger Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 15 IWTGE: Initialization Watch Trigger Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 14 ELCE: Change Error Level Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled DocID029587 Rev 3 2481/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 13 SE2E: Scheduling Error 2 Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 12 SE1E: Scheduling Error 1 Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 11 TXOE: Tx Count Overflow Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 10 TXUE: Tx Count Underflow Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 9 GTEE: Global Time Error Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 8 GTDE: Global Time Discontinuity Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 7 GTWE: Global Time Wrap Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 6 SWEE: Stop Watch Event Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 5 TTMIE: Trigger Time Mark Event Internal Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 4 RTMIE: Register Time Mark Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled BIt 3 SOGE: Start of Gap Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 2 CSME: Change of Synchronization Mode Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 1 SMCE: Start of Matrix Cycle Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled Bit 0 SBCE: Start of Basic Cycle Interrupt Enable 0: TT interrupt disabled 1: TT interrupt enabled 2482/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.4.57 FDCAN TT Interrupt Line Select Register (FDCAN_TTILS) The TT Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the TT Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. Address: 0x0128 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CERL AWL WTL rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IWTL ELCL SE2L SE1L TXOL TXUL GTEL GTDL GTWL SWEL TTMIL RTMIL SOGL CSML SMCL SBCL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 19 Reserved Bit 18 CERL: Configuration Error Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 17 AWL: Application Watchdog Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 16 WTL: Watch Trigger Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 15 IWTGL: Initialization Watch Trigger Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 14 ELCL: Change Error Level Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 13 SE2L: Scheduling Error 2 Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 12 SE1L: Scheduling Error 1 Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 11 TXOL: Tx Count Overflow Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 10 TXUL: Tx Count Underflow Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 DocID029587 Rev 3 2483/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 9 GTEL: Global Time Error Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 8 GTDL: Global Time Discontinuity Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 7 GTWL: Global Time Wrap Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 6 SWEL: Stop Watch Event Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 5 TTMIL: Trigger Time Mark Event Internal Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 4 RTMIL: Register Time Mark Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 BIt 3 SOGL: Start of Gap Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 2 CSML: Change of Synchronization Mode Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 1 SMCL: Start of Matrix Cycle Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 Bit 0 SBCL: Start of Basic Cycle Interrupt Line 0: TT interrupt assigned to Interrupt line 0 1: TT interrupt assigned to Interrupt line 1 56.4.58 FDCAN TT Operation Status Register (FDCAN_TTOST) Address: 0x012C Reset value: 0x0000 0080 31 30 29 28 27 SPL WECS AWE WFE GSI 26 25 24 TMP[2:0] 23 22 21 20 19 18 17 16 GFI WGTD Res. Res. Res. Res. Res. Res. 5 4 3 2 1 0 r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 QCS QGTP r r RTO[7:0] r r 2484/3178 r r r r r r DocID029587 Rev 3 SYS[1:0] r r MS[1:0] r EL[1:0] r r r RM0433 FD Controller Area Network (FDCAN) Bit 31 SPL: Schedule Phase Lock. The bit is valid only when external synchronization is enabled (TTOCN[ESCN] = ‘1’). In this case it signals that the difference between cycle time configured by TTGTP[CTP] and the cycle time at the rising edge at event trigger pin is less or equal 9 NTU (see Section 56.3.15: Synchronization to external time schedule). 0: Phase outside range 1: Phase inside range Bit 30 WECS: Wait for External Clock Synchronization. 0: No external clock synchronization pending 1: Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle. Bit 29 AWE: Application Watchdog Event. The application watchdog is served by reading TTOST. When the watchdog is not served in time, bit AWE is set, all FDCAN communication is stopped, and the FDCAN is set into Bus Monitoring Mode. 0: Application Watchdog served in time 1: Failed to serve Application Watchdog in time Bit 28 WFE: Wait for Event. 0: No Gap announced, reset by a Reference Message with Next_is_Gap = ‘0’ 1: Reference Message with Next_is_Gap = ‘1’ received Bit 27 GSI: Gap Started Indicator. 0: No Gap in schedule, reset by each reference message and for all time slaves 1: Gap time after Basic Cycle has started Bits 26: 24 TMP: Time Master Priority. 0x0-7 Priority of actual Time Master Bit 23 GFI: Gap Finished Indicator. Set when the CPU writes TTOCN[FGP], or by a Time Mark Interrupt if TMG = ‘1’, or via input pin (event trigger) if TTOCN[GCS] = ‘1’. Not set by Ref_Trigger_Gap or when Gap is finished by another node sending a reference message. 0: Reset at the end of each reference message 1: Gap finished by FDCAN Bit 22 WGTD: Wait for Global Time Discontinuity. 0: No global time preset pending 1: Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a Reference message with Disc_Bit = ‘1’ or after it received a Reference message. Bits 21: 16 Reserved Bits 15: 8 Reference Trigger Offset. The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). There is no notification when the lower limit of-127 is reached. In case the FDCAN becomes Time Master (MS[1:0] = ‘11’), the reset of RTO is delayed due to synchronization between Host and CAN clock domain. For time slaves the value configured by TTOCF[IRTO] is read. 0x00-FF Actual Reference Trigger offset value DocID029587 Rev 3 2485/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 7 QCS: Quality of Clock Speed. Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to ‘1’. 0: Local clock speed not synchronized to Time Master clock speed 1: Synchronization Deviation ≤ SDL Bit 6 GTP: Quality of Global Time Phase. Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to ‘0’. 0: Global time not valid 1: Global time in phase with Time Master Bits 5: 4 SYS: Synchronization State. 00: Out of Synchronization 01: Synchronizing to FDCAN communication 10: Schedule suspended by Gap (In_Gap) 11: Synchronized to schedule (In_Schedule) Bits 3: 2 MS: Master State. 00: Master_Off, no master properties relevant 01: Operating as Time Slave 10: Operating as Backup Time Master 11: Operating as current Time Master BIts 1: 0 EL: Error Level. 00: Severity 0 - No Error 01: Severity 1 - Warning 10: Severity 2 - Error 11: Severity 3 - Severe Error 56.4.59 FDCAN TUR Numerator Actual Register (FDCAN_TURNA) There is no drift compensation in TTCAN Level 1 (NAV = NC). In TTCAN Level 0 and Level 2, the drift between the node local clock and the time master local clock is calculated. The drift is compensated when the Synchronization Deviation (difference between NC and the calculated NAV) is no more than 2*(TTOCF[LDSDL] + 5). With TTOCF[LDSDL] 7, this results in a maximum range for NAV of (NC - 0x1000) ≤ NAV ≤ (NC + 0x1000). Address: 0x0130 Reset value: 0x0001 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 17 16 NAV[17:16] r r 6 5 4 3 2 1 0 r r r r r r r NAV[15:0] r r 2486/3178 r r r r r r r DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 31: 18 Reserved Bits 17: 0 NAV: Numerator Actual Value. 0x0EFFF Illegal value 0x0F000–20FFF Actual numerator value 0x21000 Illegal value 56.4.60 FDCAN TT Local and Global Time Register (FDCAN_TTLGT) Address: 0x0134 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GT[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r LT[15:0] r r r r r r r r r Bits 31: 16 GT: Global Time. Non-fractional part of the sum of the node’s local time and its local offset (see Section 56.3.10: Local time, cycle time, global time, and external clock synchronization). 0x0000–FFFF Global time value of FDCAN network Bits 15: 0 LT: Local Time. Non-fractional part of local time, incremented once each local NTU (see Section 56.3.10: Local time, cycle time, global time, and external clock synchronization). 0x0000–FFFF Local time value of FDCAN node 56.4.61 FDCAN TT Cycle Time and Count Register (FDCAN_TTCTC) Address: 0x0138 Reset value: 0x003F 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r GT[5:0] CT[15:0] r r r r r r r r r DocID029587 Rev 3 2487/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bits 31: 22 Reserved Bits 21: 16 CC: Cycle Count. 0x00–3F Number of actual Basic Cycle in the System Matrix Bits 15: 0 CT: Cycle Time Non-fractional part of the difference of the node’s local time and Ref_Mark (see Section 56.3.10: Local time, cycle time, global time, and external clock synchronization). 0x0000–FFFF Cycle time value of FDCAN Basic Cycle 56.4.62 FDCAN TT Capture Time Register (FDCAN_TTCPT) Address: 0x013C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SWV[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: r r CCV[5:0] r r r r Bits 31: 16 SWV: Stop Watch Value. On a rising/falling edge (as configured via TTOCN[SWP]) at the Stop Watch Trigger pin, when TTOCN[SWS] is different from ‘00’ and TTIR[SWE] is ‘0’, the actual time value as selected by TTOCN[SWS] (cycle, local, global) is copied to SWV and TTIR[SWE] will be set to ‘1’.Capturing of the next stop watch value is enabled by resetting TTIR[SWE]. 0x0000–FFFF Captured Stop Watch value Bits 15: 6 Reserved Bits 5: 0 CT: Cycle Count Value Cycle count value captured together with SWV. 0x00–3F Captured cycle count value 56.4.63 FDCAN TT Cycle Sync Mark Register (FDCAN_TTCSM) Address: 0x0140 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CSM[15:0] r r 2488/3178 r r r r r r r DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 31: 16 Reserved Bits 15: 0 CSM: Cycle Sync Mark. The Cycle Sync Mark is measured in cycle time. It is updated when the reference message becomes valid and retains its value until the next reference message becomes valid. 0x0000–FFFF Captured cycle time 56.4.64 FDCAN TT Trigger Select Register (FDCAN_TTTS) The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. Address: 0x0300 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: Res: EVTSEL[1:0] rw rw SWTDEL[1:0] rw rw Bits 31: 6 Reserved Bits 5: 4 EVTSEL: Event trigger input selection These bits are used to select the input to be used as event trigger 00: fdcan1_swt0 01: fdcan1_swt1 10: fdcan1_swt2 11: fdcan1_swt3 Bits 3: 2 Reserved Bits 1: 0 SWTDEL: Stop watch trigger input selection These bits are used to select the input to be used as stop watch trigger 00: fdcan1_evt0 01: fdcan1_evt1 10: fdcan1_evt2 11: fdcan1_evt3 DocID029587 Rev 3 2489/3178 2501 FD Controller Area Network (FDCAN) 56.4.65 RM0433 FDCAN register map and reset value table Offset 0x0000 Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 476. FDCAN register map and reset values REL [3:0] FDCAN_CREL STEP [3:0] SUBSTEP [3:0] YEAR [3:0] MON [7:0] DAY [7:0] Reset value 1 1 0 0 1 0 0 0 0 1 Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_DBTP Res. Res. Res. Res. Res. Res. Res. Res. TDC Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 FDCAN_TEST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RX Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_RWD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _CCCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. NISO TXP EFBI PXHD Res. Res. BRSE FDOE TEST DAR MON Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_TSCV Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FDCAN_TOCV Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_ECR Res. Res. Res. Res. TOP[15:0] Reset value 0 0 0 0 0 0 0 0 CAT CAM TAT TAM CSA LBCK CSR TX[1:0] Res. INT 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 TSS[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETOC 0 CCE 0 1 TOS[1:0] 0 ASM 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 1 0 Res. Res. 0 1 NTSEG2[6:0] Res. Res. 0 1 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 NBRP[3:0] 0 Res. Res. 0 0 Res. Res. Reset value Res. 0 0 Res. FDCAN_TSCC Res. 0 0 Res. 0 0 Res. 0 1 Res. 0 0 Res. 0 1 Res. 0 0 Res. 0 1 Res. 0 1 Res. 0 0 Res. 0 1 0 Res. 0 1 1 Res. 0 1 Res. 0 0 DSJW[3:0] WDC[7:0] NTSEG1[7:0] Reset value FDCAN_TOCC DTSEG2[3:0] WDV[7:0] NBRP[8:0] 0 DTSEG1[4:0] Res. DBRP[4:0] Res. 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 TOC[15:0] 1 1 1 1 1 1 1 1 1 1 Reserved Reset value 2490/3178 RP 0x0040 0 Res. 0x0030 to 0x003F 0 Res. 0x002C 0 Res. 0x0028 0 Res. 0x0024 NSJW[6:0] 0 Res. 0x0020 FDCAN_NBTP 0 Res. 0x001C 0 Res. 0x0018 Res. 0 Res. 0 Res. 0 Res. 0 Res. 1 Res. 0 Res. 1 Res. 1 Res. 1 Res. 0 Res. 0 Res. 1 Res. 1 Res. 0 Res. 1 Res. 1 Res. 1 Res. 0 Res. 0 Res. 0 Res. 0x0014 0 Res. 0x0010 1 Res. 0x000C ETV[31:0] Reset value Res. 0x0008 FDCAN_ENDN Res. 0x0004 TDCV[7:0] 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 REC[6:0] 0 0 0 0 0 TEC[7:0] 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_IR Res. Res. ARA PED PEA WDI BO EW EP ELO BEU BEC DRX TOO MRAF TSW TEFL TEFF TEFW TEFN TFE TCF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_IE Res. Res. ARAE PEDE PEAE WDIE BOE EWE EPE ELOE BEUE BECE DRXE TOOE MRAFE TSWE TEFLE TEFFE TEFWE TEFNE TFEE TCFE TCE HPME RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_ILS ARAL PEDL PEAL WDIL BOL EWL EPL ELOL BEUL BECL DRXL TOOL MRAFL TSWL TEFLL TEFFL TEFWL TEFNL TFEL TCFL TCL HPML RF1LL RF1FL RF1WL RF1NL RF0LL RF0FL RF0WL RF0NL Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_ILE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_GFC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _SIDFC Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 FDCAN_ILS Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 FDCAN _XIDAM Res. Reset value 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FDCAN _HPMS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLST Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _NDAT1 ND29 ND28 ND27 ND26 ND25 ND24 ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16 ND15 ND14 ND13 ND12 ND11 ND10 ND9 ND8 ND7 ND6 ND5 ND4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 1 0 LSE[6:0] FLESA[13:0] 0 EIDM[28:0] 1 FIDX[6:0] Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 ND0 0 Res. 0 ND1 0 ND2 0 ND3 0 0 0 0 0 0 0 0 MSI[1:0] LSS[7:0] 0 FLSSA[13:0] 0 EINT0 0 1 0 0 0 0 0 0 0 0 0 0 RRFE 0 Res. 0 EINT1 0 Res. 0 0 RRFS 0 LEC[2;0] ACT[1:0] EP 0 ANFE[1:0] BO EW 0 Res. 0 ANFS[1:0] TDCO[6:0] Res. RESI 0 Res. RBRS DLEC[2:0] PXE REDL 0 Res. 0 0 0 0 0 0 0 0 RF0N Res. 0 RF0F Res. 0 0 RF0W Res. 0 0 RF0L Res. Res. 0 0 Res. Res. Res. Reset value 0 RF1N Res. FDCAN_TDCR 0 RF1W Res. 0 Res. Res. 0 Res. Res. 0 RF1L Res. 0 RF1F Res. 0 TDCV[6:0] TC Res. 0 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name HPM Res. 0 Res. 0x0098 0 Res. 0x0094 0 Res. 0x0090 0 Res. 0x0088 0 Res. 0x0084 0 Res. 0x0080 0 Res. 0x0060 to 0x007F 0 Res. 0x005C 0 Res. 0x0058 0 Res. 0x0054 0 Res. 0x0050 Reset value Res. 0x0048 FDCAN_PSR Res. 0x0044 ND30 Offset ND31 RM0433 FD Controller Area Network (FDCAN) Table 476. FDCAN register map and reset values (continued) 1 1 TDCF[6:0] 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 Reset value 0 0 0 0 BIDX[5:0] 2491/3178 2501 FD Controller Area Network (FDCAN) RM0433 ND53 ND52 ND51 ND50 ND49 ND48 ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _RXF0C F0OM Reset value 0 0 0 0 0 0 0 0 0 0 FDCAN _RXF0S Res. Res. Res. Res. Res. Res. RF0L F0F Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _RXF0A Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_RXBC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _RXF1C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. RF1L F1F Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _RXF1A Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _RXESC Res. Res. Reset value 0 0 0 0 0 0 0 FDCAN_TXBC Reset value 0 0 0 0 0 0 0 0 0 FDCAN _TXFQS Res. Res. Res. Res. Res. TFQF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXESC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXBRP TRP26 TRP25 TRP24 TRP23 TRP22 TRP21 TRP20 TRP19 TRP18 TRP17 TRP16 TRP15 TRP14 TRP13 TRP12 TRP11 TRP10 TRP9 TRP8 TRP7 TRP6 TRP5 TRP4 TRP3 TRP2 TRP1 TRP0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2492/3178 Res. Res. Res. Res. 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFQPI[4:0] DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFGI[4:0] 0 0 0 0 0 0 0 0 TFFL[5:0] 0 F0DS[2:0] 0 Res. 0 0 0 TBSA[13:0] Res. NDTB[5:0] Res. TFQS[5:0] 0 0 Res. Res. 0 F1FL[5:0] F0DS[2:0] Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 F1DS[2:0] Res. 0 0 Res. Res. 0 Res. Res. 0 ReF1FL[6:0] Res. Res. 0 RBDS[2:0] Res. ReF1GI[5:0] Res. ReF1PI[5:0] Res. Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 TRP27 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 TRP28 0 0 F0FL[5:0] F1SA[13:0] 0 0 F0FL[6:0] RBSA[13:0] 0 0 Res. F0GI[5:0] 0 TRP29 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. 0 0 TFQM 0 0 Res. 0 0 Res. 0 Res. Res. 0 0 Res. Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0x00CC 0 0 Res. 0x00C8 0 0 TRP30 0x00C4 0 F1S[6:0] 0 0 0 0x00B8 0x00C0 0 0 Reset value FDCAN _RXF1S 0x00B4 0x00BC F1WM[6:0] 0 TRP31 0x00B0 0 Res. 0x00AC 0 Res. 0x00A8 0 0 F0SA[13:0] F0PI[5:0] Res. 0x00A4 0 ND32 ND54 0 ND33 ND55 0 Res. ND56 0 ND34 ND57 0 Res. ND58 0 0 ND35 ND59 0 0 ND36 ND60 0 F0S[6:0] ND37 ND61 0 F0WM[6:0] ND38 ND62 0 0x00A0 ND39 ND63 Reset value 0x009C Res. FDCAN _NDAT2 F1OM Register name DMS[1:0] Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 476. FDCAN register map and reset values (continued) AR28 AR27 AR26 AR25 AR24 AR23 AR22 AR21 AR20 AR19 AR18 AR17 AR16 AR15 AR14 AR13 AR12 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXBTO TO31 TO30 TO29 TO28 TO27 TO26 TO25 TO24 TO23 TO22 TO21 TO20 TO19 TO18 TO17 TO16 TO15 TO14 TO13 TO12 TO11 TO10 TO9 TO8 TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXBCF CF31 CF30 CF29 CF28 CF27 CF26 CF25 CF24 CF23 CF22 CF21 CF20 CF19 CF18 CF17 CF16 CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXBTIE TIE31 TIE30 TIE29 TIE28 TIE27 TIE26 TIE25 TIE24 TIE23 TIE22 TIE21 TIE20 TIE19 TIE18 TIE17 TIE16 TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 TIE1 TIE0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXBCIE CFIE29 CFIE28 CFIE27 CFIE26 CFIE25 Reset value 0 0 0 0 0 0 0 FDCAN _TXEFC Reset value 0 0 0 0 0 0 0 0 0 FDCAN _TXEFS Res. Res. Res. Res. TEFL EFF Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXEFA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TTTMC Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 FDCAN _TTRMC Res. Reset value 0 0 0 0 0 0 0 0 0 FDCAN _TTOCF Res. Res. Res. Res. EVTP ECC EGTF Reset value 0 0 0 0 0 0 0 0 0 FDCAN _TTMLM Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFIE11 CFIE10 CFIE9 CFIE8 0 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWL[7:0] 1 ENTT[11:0] 0 DocID029587 Rev 3 Res. Res. 0 0 0 TME[6:0] TMSA[15:2] 0 0 0 0 0 RID[28:0] 0 IRTO[6:0] 0 0 0 0 0 0 0 0 Res. CFIE12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEW[3:0] 0 CFIE3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. EFFL[5:0] Res. CFIE0 CFIE4 0 CFIE1 CFIE5 0 CFIE2 CFIE6 0 Res. EFG[4:0] CFIE7 0 0 Res. EFSA[15:2] 0 OM[1:0] CFIE13 0 Res. EFPI[4:0] Res. CFIE14 0 0 Res. CFIE15 0 0 GEN CFIE16 0 0 TM CFIE17 0 EFS[5:0] LDSDL[2:0] CFIE18 0 CSS[1:0] CFIE19 0 0 Res. CFIE20 0 0 Res. CFIE21 0 0 Res. CFIE22 0 0 EECS CFIE23 0 0 Res. CFIE24 EFWM[5:0] 0 Res. AR29 0 Res. AR30 0 CFIE30 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. AR31 0 CFIE31 0x010C 0 Res. 0x0108 0 Res. 0x0104 0 Res. 0x0100 0 Res. 0x00F8 0 Res. 0x00F4 0 Res. 0x00F0 0 Res. 0x00E4 0 Res. 0x00E0 0 XTD 0x00DC 0 FDCAN _TXBCR RMPS 0x00D8 Reset value Res. 0x00D4 FDCAN _TXBAR Res. 0x00D0 Res. Offset Res. RM0433 FD Controller Area Network (FDCAN) Table 476. FDCAN register map and reset values (continued) 0 0 0 0 0 0 0 EFAI[4:0] 0 0 CCM[5:0] 0 0 0 0 2493/3178 2501 FD Controller Area Network (FDCAN) RM0433 ELT Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TXBCIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKC Res. ESCN NIG TMG FGP GCS TTIE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTIE SBC 0 ECS SWS[1:0] TMC[1:0] 0 0 0 0 0 0 0 0 FDCAN _TTTMK LCKM Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_TTIR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CER AW WT IWT ELC SE2 SE1 TXO TXU GTE GTD GTW SWE TTMI RTMI SOG CSM SMC SBC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_TTIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CERE AWE WTE IWTE ELCE SE2E SE1E TXOE TXUE GTEE GTDE GTWE SWEE TTMIE RTMIE SOGE CSME SMCE SBCE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN_TTILS Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 FDCAN _TTOST SPL AWE WFE GSI Reset value 0 0 0 0 0 0 0 0 FDCAN _TURNA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TP[15:0] 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 RTO[7:0] 0 0 0 0 0 0 0 SBCL WGTD 0 0 0 0 0 0 0 EL[1:0] SE2L GFI 0 0 0 SMCL ELCL 0 CSML IWTL 0 SOGL WTL 0 MS[1:0] AWL 0 TTMIL CERL 0 RTMIL Res. 0 SYS[1:0] Res. 0 TXUL Res. 0 GTEL Res. 0 SE1L Res. 0 TXOL Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NAV[17:0] 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC[5:0] 0 0 0 0 0 0 CT[15:0] 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDCAN _TTCSM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWV[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Reset value DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 Res. FDCAN _TTCTC 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. LT[15:0] Res. GT[15:0] FDCAN _TTCTP 0 TM[15:0] 0 0 2494/3178 0 SWEL 0 QGTP 0 GTDL 0 TICC[6:0] Reset value 0x013C 0 GTWL 0 QCS FDCAN _TTLGT 0x0138 0x0144 to 0x01FC 0 0 0x0134 0x0140 0 Reset value 0x012C 0x0130 0 0 WECS 0x0128 0 Res. 0x0124 CTP[15:0] 0 Res. 0x0120 NCL[15:0] SWP FDCAN _TTGTP 0x0118 0x011C DC[13:0] TMP[2:0] 0x0114 FDCAN _TURCF Res. 0x0110 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 476. FDCAN register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 CCV[5:0] 0 0 0 0 0 0 0 0 0 0 0 0 CSM[15:0] 0 0 0 0 0 0 0 0 0 0 RM0433 FD Controller Area Network (FDCAN) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 SWTSEL[1:0] Res. 0 Res. Res. 0 Res. Res. Reset value EVTSEL[1:0] FDCAN _TTTS Res. 0x0300 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 476. FDCAN register map and reset values (continued) 0 0 2495/3178 2501 FD Controller Area Network (FDCAN) RM0433 56.5 CCU registers 56.5.1 Clock Calibration Unit Core Release Register (CCU_CREL) Address offset: 0x0000 Reset value: 0xrrrd dddd 31 30 29 28 27 REL[3:0] 26 25 24 23 STEP[3:0] 22 21 20 19 SUBSTEP[3:0] 18 17 16 YEAR[3:0] r r r r r r r r r r r r d d d d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d d d d 19 18 17 16 MON[7:0] d d d d d DAY[7:0] d d d d d d d Bits 31: 28 REL: Core Release One digit, BCD. Bits 27: 24 STEP: Step of Core Release One digit, BCD. Bits 23: 20 SUBSTEP: Sub-step of Core Release One digit, BCD. Bits 19: 16 YEAR: Time Stamp Year One digit, BCD. Bits 15: 8 MON: Time Stamp Month Two digits, BCD. Bits 7: 0 DAY: Time Stamp Day Two digits, BCD. 56.5.2 Calibration Configuration Register (CCU_CCFG) Address offset: 0x0004 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 SWR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw 15 14 13 12 11 10 9 8 OCPM[7:0] rw rw 2496/3178 rw rw rw rw rw rw 7 6 5 CFL BCC Res. rw rw DocID029587 Rev 3 4 CDIV[3:0] rw rw rw rw 3 2 1 0 rw rw TQBT[5:0] rw rw rw RM0433 FD Controller Area Network (FDCAN) Bit 31 SWR: Software Reset Writing a ‘1’ to this bit will reset the calibration FSM to state Not_Calibrated (CSTAT.CALS = ‘00’). The Calibration Watchdog value CWD.WDV is also reset. Registers CCFG, CSTAT and the Calibration Watchdog configuration CWD.WDC are unchanged. The bit remains set until reset is completed. Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the M_CAN control bits CCCR.CCE = ‘1’ AND CCCR.INIT = ‘1’. Bits 30: 20 Reserved Bits 19: 16 CDIV: Clock Divider The clock divider has to be configured when the clock calibration is bypassed (BCC = ‘1’) to ensure that the M_CAN requirement is fulfilled. 0000: Divide by 1 0001: Divide by 2 0010: Divide by 4 0011: Divide by 6 0100: Divide by 8 0101: Divide by 10 0110: Divide by 12 0111: Divide by 14 1000: Divide by 16 1001: Divide by 18 1010: Divide by 20 1011: Divide by 22 1100: Divide by 24 1101: Divide by 26 1110: Divide by 28 1111: Divide by 30 Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the M_CAN control bits CCCR.CCE = ‘1’ AND CCCR.INIT = ‘1’. Bits 15: 8 OCPM: Oscillator Clock Periods Minimum Configures the minimum number of periods in two CAN bit times. OCPM is used in Basic Calibration to avoid false measurements in case of glitches on the bus line. The configured number of periods is OCPM × 32. The configuration depends on the frequency (from 80 to 500 MHz) and the bit rate configured in FDCAN1 and FDCAN2 (from 125 kbit/s up to 1 Mbit/s). It is recommended to configure a value slightly below two CAN bit times. The reset value is 1.6 bit times at 80 MHz fdcan_ker_ck and 1 Mbit/s CAN bit rate. Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the M_CAN control bits CCCR.CCE = ‘1’ AND CCCR.INIT = ‘1’. Bit 7 CFL: Calibration Field Length 0: Calibration field length is 32 bits 1: Calibration field length is 64 bits Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the M_CAN control bits CCCR.CCE = ‘1’ AND CCCR.INIT = ‘1’. DocID029587 Rev 3 2497/3178 2501 FD Controller Area Network (FDCAN) RM0433 Bit 6 BCC: Bypass Clock Calibration If this bit is set, the clock input fdcan_ker_ck is routed to the time quanta clock through a clock divider configurable via CDIV, cu_cok is always ‘1’. In this case the baud rate prescaler of the connected M_CANs has to be configured to generate the M_CAN internal time quanta clock. 0: Clock calibration unit generates time quanta clock 1: Clock calibration unit bypassed (default configuration) Note: As long as fdcan_ker_ck is equal or above 80 MHz the Clock Calibration on CAN unit is functional, even when BCC = ‘1’. The calibration state can be read from register CSTAT. Bit 5 Reserved Bits 4: 0 TQBT: Time Quanta per Bit Time Configures the number of time quanta per bit time. Same value as configured in FDCAN1 and FDCAN2. The range of the resulting time quanta clock fdcan_tq_ck is from 0.5 MHz (bit rate of 125 kbit/s with 4 tq per bit time) to 25 MHz (bit rate of 1 Mbit/s with 25 tq per bit time). Valid values are 4 to 25. Configured values below 4 are interpreted as 4, values above 25 are interpreted as 25. Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the M_CAN control bits CCCR.CCE = ‘1’ AND CCCR.INIT = ‘1’. 56.5.3 Calibration Status Register (CCU_CSTAT) Address offset: 0x0008 Reset value: 0x0203 FFFF 31 30 29 28 27 26 25 24 CALS[1:0] 23 22 21 20 19 18 TQC[11:0] 17 16 OCPC[17:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r OCPC[15:0] r r r r r r r r r Bits 31: 30 CALS: Calibration State 00: Not_Calibrated 01: Basic_Calibrated 10: Precision_Calibrated 11: Reserved Bit 29 Reserved Bits 28: 18 TQC: Time Quanta Counter Captured number of time quanta in calibration field (32 or 64 bits). Only valid when the clock calibration unit is in state Precision_Calibrated. Bits 17: 0 OCPC: Oscillator Clock Period Counter Captured number of oscillator clock periods in calibration field (32 or 64 bits). Only valid when the clock calibration unit is in state Precision_Calibrated. 2498/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) 56.5.4 Calibration Watchdog Register (CCU_CWD) Address offset: 0x000C Reset value: 0x0000 0000 The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CSTAT.CALS = ‘00’). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CSTAT.CALS = ‘00’), the counter is reloaded with RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CSTAT.CALS = ‘01’), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CSTAT.CALS = ‘00’), the counter is reloaded with RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CSTAT.CALS = ‘10’) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CSTAT.CALS = ‘01’). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CUIR.CWE. If enabled by CUIE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CUIR.CWE is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDV[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw WDC[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 16 WDV: Watchdog Value Actual Calibration Watchdog Counter Value. Bits 15: 0 WDC: WDC Watchdog Configuration Start value of the CalibrationWatchdog Counter. With the reset value of ‘00’ the counter is disabled. Write access by the Host CPU to registers/bits marked with “P=Protected Write” is possible only when the M_CAN control bits CCCR.CCE = ‘1’ AND CCCR.INIT = ‘1’. DocID029587 Rev 3 2499/3178 2501 FD Controller Area Network (FDCAN) 56.5.5 RM0433 Clock Calibration Unit Interrupt Register (CCU_IR) The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. The configuration of CUIE controls whether an interrupt is generated. Address offset: 0x0010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSC CWE rw rw Bits 31: 2 Reserved Bit 1 CSC: Calibration State Changed 0: Calibration State unchanged 1: Calibration State has changed Bit 0 CWE: Calibration Watchdog Event 0: No Calibration Watchdog Event 1: Calibration Watchdog Event occurred 56.5.6 Clock Calibration Unit Interrupt Enable Register (CCU_IE) Address offset: 0x0014 Reset value: 0x0000 0000 The settings in the CU Interrupt Enable register determine whether a status change in the CU Interrupt Register will be signaled on an interrupt line. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSCE CWEE rw rw 2500/3178 DocID029587 Rev 3 RM0433 FD Controller Area Network (FDCAN) Bits 31: 2 Reserved Bit 1 CSCE: Calibration State Changed Enable 0: Interrupt disabled 1: Interrupt enabled Bit 0 CWEE: Calibration Watchdog Event Enable 0: Interrupt disabled 1: Interrupt enabled 56.5.7 CCU register map and reset value table 0 0 0 0 0 0 0 0 CCU _CCFG SWR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 CDIV[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TQBT[4:0] 0 0 CCU_IR Res. Res. Res. Res. Res. Res. CSCE CWEE 0 0 0 0 0 0 0 0 0 0 0 0 0 CWE 0 Res. 0 Res. 0 Res. 0 CSC 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value Res. 0 Res. CCU_IR Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. OCPC[17:0] Res. 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCU_CWD 0 0 CSM[7:0] TQC[10:0] 0 0 Res. 0x0014 0 Res. CCU _CSTAT 0 Res. 0 DAY[7:0] CFL 0 MON[7:0] BCC 0 CALS[1:0] 0 YEAR[3:0] Res. 0x0010 SUBSTEP[3:0] Reset value Reset value 0x000C STEP[3:0] Res. 0x0008 REL[3:0] Res. 0x0004 CCU_CREL Res. 0x0000 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 477. CCU register map and reset values 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDV[15:0] 0 0 WDC[15:0] DocID029587 Rev 3 2501/3178 2501 USB on-the-go high-speed (OTG_HS) RM0433 57 USB on-the-go high-speed (OTG_HS) 57.1 Introduction Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission. This section presents the architecture and the programming model of the OTG_HS controller. The following acronyms are used throughout the section: FS Full-speed LS Low-speed HS High-speed MAC Media access controller OTG On-the-go PFC Packet FIFO controller PHY Physical layer USB Universal serial bus UTMI USB 2.0 Transceiver Macrocell interface (UTMI) UTMI USB Transceiver Macrocell Interface ULPI UTMI+ Low Pin Interface LPM Link power management BCD Battery charging detector HNP Host negotiation protocol SRP Session request protocol References are made to the following documents: • USB On-The-Go Supplement, Revision 2.0 • Universal Serial Bus Revision 2.0 Specification • USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification, July 16, 2007 • Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007 • Battery Charging Specification, Revision 1.2 The USB OTG is a dual-role device (DRD) controller that supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0 Specification. It can also be configured as a host-only or device-only controller, fully compliant with the USB 2.0 Specification. OTG_HS supports the speeds defined in the Table 478: OTG_HS speeds supported below.The USB OTG supports both HNP and SRP. The only external device required is a charge pump for VBUS in OTG mode. 2502/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Table 478. OTG_HS speeds supported 57.2 HS (480 Mb/s) FS (12 Mb/s) LS (1.5 Mb/s) Host mode X X X Device mode X X - OTG main features The main features can be divided into three categories: general, host-mode and devicemode features. DocID029587 Rev 3 2503/3178 2669 USB on-the-go high-speed (OTG_HS) 57.2.1 RM0433 General features The OTG_HS interface general features are the following: • It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0 • OTG_HS supports the following PHY interfaces: • • • 2504/3178 – An on-chip full-speed PHY – An I2C interface for external full-speed I2C PHY – An ULPI interface for external high-speed PHY It includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Rev 2.0 specification – Integrated support for A-B Device Identification (ID line) – Integrated support for host Negotiation Protocol (HNP) and Session Request Protocol (SRP) – It allows host to turn VBUS off to conserve battery power in OTG applications – It supports OTG monitoring of VBUS levels with internal comparators – It supports dynamic host-peripheral switch of role It is software-configurable to operate as: – SRP capable USB HS Peripheral (B-device) – SRP capable USB HS/LS host (A-device) – USB On-The-Go Full-Speed Dual Role device It supports HS SOF and LS Keep-alives with – SOF pulse PAD connectivity – SOF pulse internal connection to timer (TIMx) – Configurable framing period – Configurable end of frame interrupt • OTG_HS embeds an internal DMA with shareholding support and software selectable AHB burst type in DMA mode. • It includes power saving features such as system stop during USB Suspend, switch-off of clock domains internal to the digital core, PHY and DFIFO power management. • It features a dedicated RAM of 4 Kbytes with advanced FIFO control: – Configurable partitioning of RAM space into different FIFOs for flexible and efficient use of RAM – Each FIFO can hold multiple packets – Dynamic memory allocation – Configurable FIFO sizes that are not powers of 2 to allow the use of contiguous memory locations • It guarantees max USB bandwidth for up to one frame (1 ms) without system intervention. • It supports charging port detection as described in Battery Charging Specification Revision 1.2 on the FS PHY transceiver only. DocID029587 Rev 3 RM0433 57.2.2 USB on-the-go high-speed (OTG_HS) Host-mode features The OTG_HS interface main features and requirements in host-mode are the following: • External charge pump for VBUS voltage generation. • Up to 16 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer. • Built-in hardware scheduler holding: • 57.2.3 – Up to 16 interrupt plus isochronous transfer requests in the periodic hardware queue – Up to 16 control plus bulk transfer requests in the non-periodic hardware queue Management of a shared Rx FIFO, a periodic Tx FIFO and a nonperiodic Tx FIFO for efficient usage of the USB data RAM. Peripheral-mode features The OTG_HS interface main features in peripheral-mode are the following: • 1 bidirectional control endpoint0 • 8 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous transfers • 8 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers • Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data RAM • Management of up to 9 dedicated Tx-IN FIFOs (one for each active IN EP) to put less load on the application • Support for the soft disconnect feature. DocID029587 Rev 3 2505/3178 2669 USB on-the-go high-speed (OTG_HS) 57.3 RM0433 OTG Implementation Table 479. OTG Implementation for STM32H7(1) OTG_HS1(2) USB features OTG_HS2(3) Device bidirectional endpoints (including EP0) 9 Host mode channels 16 Size of dedicated SRAM 4 KB USB 2.0 Link Power Management (LPM) support X OTG revision supported 2.0 Attach Detection Protocol (ADP) support - Battery Charging Detection (BCD) support X ULPI available to primary IOs via, muxing X - 1. “X” = supported, “-” = not supported. 2. Compatible with High Speed operation. 3. Incompatible with High Speed operation. 57.4 OTG functional description 57.4.1 OTG block diagram In STM32H7, two instances of OTG_HS are present (OTG_HS1 and OTG_HS2). Although both can potentially be programmed for HS operation, only OTG_HS1 has an accessible ULPI interface which will allow High Speed operation using an external HS transceiver. 2506/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Figure 739. OTG high-speed block diagram (OTG_HS1) (;7, ,QWHUUXSW DV\QFZDNHXS ,QWHUUXSW (3RXW ,QWHUUXSW (3LQ ,QWHUUXSW JOREDO $+% DSSOLFDWLRQEXV &38 0HPRU\ 3HULSKHUDO 19,& 8/3,B&. 8/3,B',5 8/3,B673 8/3,B1;7 8/3,B' 86%27*+6FRUH 27*B+6 8/3,LQWHUIDFH SLQV $+%PDVWHU LQWHUIDFH 27* )6 VHULDO $+%VODYH LQWHUIDFH 3+< 8/3,3+< H[WHUQDO FRPSRQHQW 86% '' 27*B+6B'3 27*B+6B'0 8QLYHUVDO6HULDO%XV 27*B+6B,' 27*B+6B9%86 'DWD),)2 5$0LQWHUIDFH 3HULSKHUDO 27*B+6B62) 'DWD),)2 VLQJOHSRUW5$0 635$0 06Y9 Figure 740. OTG high-speed block diagram (OTG_HS2) (;7, ,QWHUUXSW DV\QFZDNHXS ,QWHUUXSW (3RXW ,QWHUUXSW (3LQ ,QWHUUXSW JOREDO 0HPRU\ 3HULSKHUDO $+% DSSOLFDWLRQEXV &38 $+%PDVWHU LQWHUIDFH 86%27*+6FRUH 27*B+6 7KLVLQVWDQFHFDQQRW EHXVHGLQ+6PRGH IRUSLQQLQJUHDVRQV 27* )6 $+%VODYH LQWHUIDFH VHULDO 3+< 27*B)6B'3 27*B)6B'0 8QLYHUVDO6HULDO%XV 27*B)6B,' 27*B)6B9%86 'DWD),)2 5$0LQWHUIDFH 3HULSKHUDO 19,& 27*B)6B62) 'DWD),)2 VLQJOHSRUW5$0 635$0 06Y9 DocID029587 Rev 3 2507/3178 2669 USB on-the-go high-speed (OTG_HS) 57.4.2 RM0433 USB OTG pin and internal signals Table 480. OTG_FS/OTG_HS input/output signals Signal name Signal type Description usb_hclk Digital input usb_sof_evt Digital output USB OTG start-of-frame event for on chip peripherals usb_wkup Digital output USB OTG wakeup event output usb_gbl_it Digital output USB OTG global interrupt usb_ep1_in_it Digital output USB OTG endpoint 1 in interrupt usb_ep1_out_it Digital output USB OTG endpoint 1 out interrupt USB OTG interface clock Table 481. OTG_FS/OTG_HS input/output pins 57.4.3 Signal name Signal type Description OTG_[HS/FS]_DP Digital input/output USB OTG Data plus line OTG_[HS/FS]_DM Digital input/output USB OTG Data minus line OTG_[HS/FS]_ID Digital Input USB OTG ID OTG_[HS/FS]_VBUS Digital Bidirectionnel OTG_[HS/FS]_SOF Digital Input USB OTG Start Of Frame event output on GPIO OTG_HS_ULPI_CK Digital Input USB OTG ULPI Clock OTG_HS_ULPI_DIR Digital Input USB OTG ULPI data bus direction control OTG_HS_ULPI_STP Digital output USB OTG ULPI data stream stop OTG_HS_ULPI_NXT Digital input USB OTG ULPI next data stream request OTG_HS_ULPI_D[0..7] Digital input/output USB OTG ULPI 8-bit bi-directional data bus USB OTG Bus Power OTG core The USB OTG receives the 48 MHz clock from the reset and clock controller (RCC). The USB clock is used for driving the 48 MHz domain at full-speed (12 Mbit/s) and must be enabled prior to configuring the OTG core. The CPU reads and writes from/to the OTG core registers through the AHB peripheral bus. It is informed of USB events through the single USB OTG interrupt line described in Section 57.12: OTG_HS interrupts. 2508/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) The CPU submits data over the USB by writing 32-bit words to dedicated OTG locations (push registers). The data are then automatically stored into Tx-data FIFOs configured within the USB data RAM. There is one Tx FIFO push register for each in-endpoint (peripheral mode) or out-channel (host mode). The CPU receives the data from the USB by reading 32-bit words from dedicated OTG addresses (pop registers). The data are then automatically retrieved from a shared Rx FIFO configured within the 4-Kbyte USB data RAM. There is one Rx FIFO pop register for each out-endpoint or in-channel. The USB protocol layer is driven by the serial interface engine (SIE) and serialized over the USB by the transceiver module within the on-chip physical layer (PHY)or external OTG_HSPHY or external OTG_FS PHY using I2C interface. 57.4.4 Embedded full speed OTG PHY The full-speed OTG PHY includes the following components: • FS/LS transceiver module used by both host and device. It directly drives transmission and reception on the single-ended USB lines. • integrated ID pull-up resistor used to sample the ID line for A/B device identification. • DP/DM integrated pull-up and pull-down resistors controlled by the OTG_HS core depending on the current role of the device. As a peripheral, it enables the DP pull-up resistor to signal full-speed peripheral connections as soon as VBUS is sensed to be at a valid level (B-session valid). In host mode, pull-down resistors are enabled on both DP/DM. Pull-up and pull-down resistors are dynamically switched when the peripheral role is changed via the host negotiation protocol (HNP). • Pull-up/pull-down resistor ECN circuit. The DP pull-up consists of 2 resistors controlled separately from the OTG_HS as per the resistor Engineering Change Notice applied to USB Rev2.0. The dynamic trimming of the DP pull-up strength allows to achieve a better noise rejection and Tx/Rx signal quality. • VBUS sensing comparators with hysteresis used to detect VBUS Valid, A-B Session Valid and session-end voltage thresholds. They are used to drive the session request protocol (SRP), detect valid startup and end-of-session conditions, and constantly monitor the VBUS supply during USB operations. To guarantee a correct operation for the USB OTG_HS peripheral, the AHB frequency should be higher than 30 MHz. 57.4.5 High-speed OTG PHY The USB OTG_HS core includes an ULPI interface to connect an external HS PHY. ULPI interface is only available on OTG HS1 (see Section 57.4.1: OTG block diagram). 57.4.6 External Full-speed OTG PHY using the I2C interface The USB OTG_HS core embeds an I2C interface allowing to connect an external FS PHY. DocID029587 Rev 3 2509/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 57.5 OTG dual role device (DRD) 57.5.1 ID line detection The host or peripheral (the default) role is assumed depending on the ID input pin. The ID line status is determined on plugging in the USB cable, depending on whether a MicroA or MicroB plug is connected to the micro-AB receptacle. 57.5.2 • If the B-side of the USB cable is connected with a floating ID wire, the integrated pullup resistor detects a high ID level and the default peripheral role is confirmed. In this configuration the OTG_HS complies with the standard FSM described in section 4.2.4: ID pin of the On-the-Go specification Rev2.0, supplement to the USB2.0. • If the A-side of the USB cable is connected with a grounded ID, the OTG_HS issues an ID line status change interrupt (CIDSCHG bit in OTG_GINTSTS) for host software initialization, and automatically switches to the host role. In this configuration the OTG_HS complies with the standard FSM described by section 4.2.4: ID pin of the Onthe-Go specification Rev2.0, supplement to the USB2.0. HNP dual role device The HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_ GUSBCFG) enables the OTG_HS core to dynamically change its role from A-host to Aperipheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the host negotiation protocol (HNP). The current device status can be read by the combined values of the Connector ID Status bit in the Global OTG control and status register (CIDSTS bit in OTG_GOTGCTL) and the current mode of operation bit in the global interrupt and status register (CMOD bit in OTG_GINTSTS). The HNP program model is described in detail in Section 57.15: OTG_HS programming model. 57.5.3 SRP dual role device The SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG) enables the OTG_HS core to switch off the generation of VBUS for the Adevice to save power. Note that the A-device is always in charge of driving VBUS regardless of the host or peripheral role of the OTG_HS. The SRP A/B-device program model is described in detail in Section 57.15: OTG_HS programming model. 2510/3178 DocID029587 Rev 3 RM0433 57.6 USB on-the-go high-speed (OTG_HS) USB peripheral This section gives the functional description of the OTG_HS in the USB peripheral mode. The OTG_HS works as an USB peripheral in the following circumstances: • OTG B-Peripheral – • – • OTG A-device state after the HNP switches the OTG_HS to its peripheral role B-device – • OTG B-device default state if B-side of USB cable is plugged in OTG A-Peripheral If the ID line is present, functional and connected to the B-side of the USB cable, and the HNP-capable bit in the Global USB Configuration register (HNPCAP bit in OTG_GUSBCFG) is cleared. Peripheral only – The force device mode bit (FDMOD) in the Section 57.14.4: OTG USB configuration register (OTG_GUSBCFG) is set to 1, forcing the OTG_HS core to work as an USB peripheral-only. In this case, the ID line is ignored even if it is present on the USB connector. Note: To build a bus-powered device implementation in case of the B-device or peripheral-only configuration, an external regulator has to be added, that generates the necessary powersupply from VBUS. 57.6.1 SRP-capable peripheral The SRP capable bit in the Global USB configuration register (SRPCAP bit in OTG_GUSBCFG) enables the OTG_HS to support the session request protocol (SRP). In this way, it allows the remote A-device to save power by switching off VBUS while the USB session is suspended. The SRP peripheral mode program model is described in detail in the B-device session request protocol section. 57.6.2 Peripheral states Powered state The VBUS input detects the B-Session valid voltage by which the USB peripheral is allowed to enter the powered state (see USB2.0 section 9.1). The OTG_HS then automatically connects the DP pull-up resistor to signal full-speed device connection to the host and generates the session request interrupt (SRQINT bit in OTG_GINTSTS) to notify the powered state. The VBUS input also ensures that valid VBUS levels are supplied by the host during USB operations. If a drop in VBUS below B-session valid happens to be detected (for instance because of a power disturbance or if the host port has been switched off), the OTG_HS automatically disconnects and the session end detected (SEDET bit in OTG_GOTGINT) interrupt is generated to notify that the OTG_HS has exited the powered state. In the powered state, the OTG_HS expects to receive some reset signaling from the host. No other USB operation is possible. When a reset signaling is received the reset detected interrupt (USBRST in OTG_GINTSTS) is generated. When the reset signaling is complete, the enumeration done interrupt (ENUMDNE bit in OTG_GINTSTS) is generated and the OTG_HS enters the Default state. DocID029587 Rev 3 2511/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Soft disconnect The powered state can be exited by software with the soft disconnect feature. The DP pullup resistor is removed by setting the soft disconnect bit in the device control register (SDIS bit in OTG_DCTL), causing a device disconnect detection interrupt on the host side even though the USB cable was not really removed from the host port. Default state In the Default state the OTG_HS expects to receive a SET_ADDRESS command from the host. No other USB operation is possible. When a valid SET_ADDRESS command is decoded on the USB, the application writes the corresponding number into the device address field in the device configuration register (DAD bit in OTG_DCFG). The OTG_HS then enters the address state and is ready to answer host transactions at the configured USB address. Suspended state The OTG_HS peripheral constantly monitors the USB activity. After counting 3 ms of USB idleness, the early suspend interrupt (ESUSP bit in OTG_GINTSTS) is issued, and confirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in OTG_GINTSTS). The device suspend bit is then automatically set in the device status register (SUSPSTS bit in OTG_DSTS) and the OTG_HS enters the suspended state. The suspended state may optionally be exited by the device itself. In this case the application sets the remote wakeup signaling bit in the device control register (RWUSIG bit in OTG_DCTL) and clears it after 1 to 15 ms. When a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in OTG_GINTSTS) is generated and the device suspend bit is automatically cleared. 57.6.3 Peripheral endpoints The OTG_HS core instantiates the following USB endpoints: • • 2512/3178 Control endpoint 0: – Bidirectional and handles control messages only – Separate set of registers to handle in and out transactions – Proper control (OTG_DIEPCTL0/OTG_DOEPCTL0), transfer configuration (OTG_DIEPTSIZ0/OTG_DOEPTSIZ0), and status-interrupt (OTG_DIEPINT0/)OTG_DOEPINT0) registers. The available set of bits inside the control and transfer size registers slightly differs from that of other endpoints 8 IN endpoints – Each of them can be configured to support the isochronous, bulk or interrupt transfer type – Each of them has proper control (OTG_DIEPCTLx), transfer configuration (OTG_DIEPTSIZx), and status-interrupt (OTG_DIEPINTx) registers – The Device IN endpoints common interrupt mask register (OTG_DIEPMSK) is available to enable/disable a single kind of endpoint interrupt source on all of the IN endpoints (EP0 included) – Support for incomplete isochronous IN transfer interrupt (IISOIXFR bit in OTG_GINTSTS), asserted when there is at least one isochronous IN endpoint on DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_GINTSTS/EOPF). • 8 OUT endpoints – Each of them can be configured to support the isochronous, bulk or interrupt transfer type – Each of them has a proper control (OTG_DOEPCTLx), transfer configuration (OTG_DOEPTSIZx) and status-interrupt (OTG_DOEPINTx) register – Device Out endpoints common interrupt mask register (OTG_DOEPMSK) is available to enable/disable a single kind of endpoint interrupt source on all of the OUT endpoints (EP0 included) – Support for incomplete isochronous OUT transfer interrupt (INCOMPISOOUT bit in OTG_GINTSTS), asserted when there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_GINTSTS/EOPF). Endpoint control • The following endpoint controls are available to the application through the device endpoint-x IN/OUT control register (OTG_DIEPCTLx/OTG_DOEPCTLx): – Endpoint enable/disable – Endpoint activate in current configuration – Program USB transfer type (isochronous, bulk, interrupt) – Program supported packet size – Program Tx FIFO number associated with the IN endpoint – Program the expected or transmitted data0/data1 PID (bulk/interrupt only) – Program the even/odd frame during which the transaction is received or transmitted (isochronous only) – Optionally program the NAK bit to always negative-acknowledge the host regardless of the FIFO status – Optionally program the STALL bit to always stall host tokens to that endpoint – Optionally program the SNOOP mode for OUT endpoint not to check the CRC field of received data Endpoint transfer The device endpoint-x transfer size registers (OTG_DIEPTSIZx/OTG_DOEPTSIZx) allow the application to program the transfer size parameters and read the transfer status. Programming must be done before setting the endpoint enable bit in the endpoint control register. Once the endpoint is enabled, these fields are read-only as the OTG_HS core updates them with the current transfer status. The following transfer parameters can be programmed: • Transfer size in bytes • Number of packets that constitute the overall transfer size Endpoint status/interrupt The device endpoint-x interrupt registers (OTG_DIEPINTx/OTG_DOPEPINTx) indicate the status of an endpoint with respect to USB- and AHB-related events. The application must read these registers when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in DocID029587 Rev 3 2513/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 the core interrupt register (OEPINT bit in OTG_GINTSTS or IEPINT bit in OTG_GINTSTS, respectively) is set. Before the application can read these registers, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers The peripheral core provides the following status checks and interrupt generation: 57.7 • Transfer completed interrupt, indicating that data transfer was completed on both the application (AHB) and USB sides • Setup stage has been done (control-out only) • Associated transmit FIFO is half or completely empty (in endpoints) • NAK acknowledge has been transmitted to the host (isochronous-in only) • IN token received when Tx FIFO was empty (bulk-in/interrupt-in only) • Out token received when endpoint was not yet enabled • Babble error condition has been detected • Endpoint disable by application is effective • Endpoint NAK by application is effective (isochronous-in only) • More than 3 back-to-back setup packets were received (control-out only) • Timeout condition detected (control-in only) • Isochronous out packet has been dropped, without generating an interrupt USB host This section gives the functional description of the OTG_HS in the USB host mode. The OTG_HS works as a USB host in the following circumstances: • OTG A-host – • OTG B-host • A-device – – • 2514/3178 OTG B-device after HNP switching to the host role If the ID line is present, functional and connected to the A-side of the USB cable, and the HNP-capable bit is cleared in the Global USB Configuration register (HNPCAP bit in OTG_GUSBCFG). Integrated pull-down resistors are automatically set on the DP/DM lines. Host only – Note: OTG A-device default state when the A-side of the USB cable is plugged in The force host mode bit in the 57.14.4 global USB configuration register (FHMOD bit in OTG_GUSBCFG) forces the OTG_HS core to work as a USB host-only. In this case, the ID line is ignored even if present on the USB connector. Integrated pull-down resistors are automatically set on the DP/DM lines. On-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch must be added externally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO output. This is required for the OTG A-host, A-device and host-only configurations. DocID029587 Rev 3 RM0433 57.7.1 USB on-the-go high-speed (OTG_HS) SRP-capable host SRP support is available through the SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG). With the SRP feature enabled, the host can save power by switching off the VBUS power while the USB session is suspended. The SRP host mode program model is described in detail in the A-device session request protocol) section. 57.7.2 USB host states Host port power On-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch, must be added externally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO output or via an I2C interface connected to an external PMIC (power management IC). When the application decides to power on VBUS, it must also set the port power bit in the host port control and status register (PPWR bit in OTG_HPRT). VBUS valid When HNP or SRP is enabled the VBUS sensing pin should be connected to VBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold (4.4 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in OTG_GOTGINT). The application is then required to remove the VBUS power and clear the port power bit. When HNP and SRP are both disabled, the VBUS sensing pin does not need to be connected to VBUS . The charge pump overcurrent flag can also be used to prevent electrical damage. Connect the overcurrent flag output from the charge pump to any GPIO input and configure it to generate a port interrupt on the active level. The overcurrent ISR must promptly disable the VBUS generation and clear the port power bit. Host detection of a peripheral connection If SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any time, the OTG_HS will not detect any bus connection until VBUS is no longer sensed at a valid level (5 V). When VBUS is at a valid level and a remote B-device is attached, the OTG_HS core issues a host port interrupt triggered by the device connected bit in the host port control and status register (PCDET bit in OTG_HPRT). When HNP and SRP are both disabled, USB peripherals or B-device are detected as soon as they are connected. The OTG_HS core issues a host port interrupt triggered by the device connected bit in the host port control and status (PCDET bit in OTG_HPRT). Host detection of peripheral a disconnection The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit in OTG_GINTSTS). DocID029587 Rev 3 2515/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Host enumeration After detecting a peripheral connection the host must start the enumeration process by sending USB reset and configuration commands to the new peripheral. Before starting to drive a USB reset, the application waits for the OTG interrupt triggered by the debounce done bit (DBCDNE bit in OTG_GOTGINT), which indicates that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). The application drives a USB reset signaling (single-ended zero) over the USB by keeping the port reset bit set in the host port control and status register (PRST bit in OTG_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes care of the timing count and then of clearing the port reset bit. Once the USB reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (PENCHNG bit in OTG_HPRT). This informs the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and status register (PSPD bit in OTG_HPRT) and that the host is starting to drive SOFs (FS) or Keep alives (LS). The host is now ready to complete the peripheral enumeration by sending peripheral configuration commands. Host suspend The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register (PSUSP bit in OTG_HPRT). The OTG_HS core stops sending SOFs and enters the suspended state. The suspended state can be optionally exited on the remote device’s initiative (remote wakeup). In this case the remote wakeup interrupt (WKUPINT bit in OTG_GINTSTS) is generated upon detection of a remote wakeup signaling, the port resume bit in the host port control and status register (PRES bit in OTG_HPRT) self-sets, and resume signaling is automatically driven over the USB. The application must time the resume window and then clear the port resume bit to exit the suspended state and restart the SOF. If the suspended state is exited on the host initiative, the application must set the port resume bit to start resume signaling on the host port, time the resume window and finally clear the port resume bit. 57.7.3 Host channels The OTG_HS core instantiates 16 host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 16 transfer requests at the same time. If more than 16 transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts. Each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. Each host channel makes us of proper control (OTG_HCCHARx), transfer configuration (OTG_HCTSIZx) and status/interrupt (OTG_HCINTx) registers with associated mask (OTG_HCINTMSKx) registers. 2516/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Host channel control • The following host channel controls are available to the application through the host channel-x characteristics register (OTG_HCCHARx): – Channel enable/disable – Program the HS/FS/LS speed of target USB peripheral – Program the address of target USB peripheral – Program the endpoint number of target USB peripheral – Program the transfer IN/OUT direction – Program the USB transfer type (control, bulk, interrupt, isochronous) – Program the maximum packet size (MPS) – Program the periodic transfer to be executed during odd/even frames Host channel transfer The host channel transfer size registers (OTG_HCTSIZx) allow the application to program the transfer size parameters, and read the transfer status. Programming must be done before setting the channel enable bit in the host channel characteristics register. Once the endpoint is enabled the packet count field is read-only as the OTG_HS core updates it according to the current transfer status. • The following transfer parameters can be programmed: – transfer size in bytes – number of packets making up the overall transfer size – initial data PID Host channel status/interrupt The host channel-x interrupt register (OTG_HCINTx) indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read these register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read these registers, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. DocID029587 Rev 3 2517/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 The mask bits for each interrupt source of each channel are also available in the OTG_HCINTMSKx register. • 57.7.4 The host core provides the following status checks and interrupt generation: – Transfer completed interrupt, indicating that the data transfer is complete on both the application (AHB) and USB sides – Channel has stopped due to transfer completed, USB transaction error or disable command from the application – Associated transmit FIFO is half or completely empty (IN endpoints) – ACK response received – NAK response received – STALL response received – USB transaction error due to CRC failure, timeout, bit stuff error, false EOP – Babble error – frame overrun – data toggle error Host scheduler The host core features a built-in hardware scheduler which is able to autonomously re-order and manage the USB transaction requests posted by the application. At the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions to achieve the higher level of priority granted to the isochronous and interrupt transfer types by the USB specification. The host processes the USB transactions through request queues (one for periodic and one for nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a pending transaction request from the application, and holds the IN or OUT channel number along with other information to perform a transaction on the USB. The order in which the requests are written to the queue determines the sequence of the transactions on the USB interface. At the beginning of each frame, the host processes the periodic request queue first, followed by the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt (IPXFR bit in OTG_GINTSTS) if an isochronous or interrupt transaction scheduled for the current frame is still pending at the end of the current frame. The OTG_HS core is fully responsible for the management of the periodic and nonperiodic request queues.The periodic transmit FIFO and queue status register (OTG_HPTXSTS) and nonperiodic transmit FIFO and queue status register (OTG_HNPTXSTS) are read-only registers which can be used by the application to read the status of each request queue. They contain: • The number of free entries currently available in the periodic (nonperiodic) request queue (8 max) • Free space currently available in the periodic (nonperiodic) Tx FIFO (out-transactions) • IN/OUT token, host channel number and other status information. As request queues can hold a maximum of 8 entries each, the application can push to schedule host transactions in advance with respect to the moment they physically reach the SB for a maximum of 8 pending periodic transactions plus 8 pending non-periodic transactions. To post a transaction request to the host scheduler (queue) the application must check that there is at least 1 entry available in the periodic (nonperiodic) request queue by reading the 2518/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) PTXQSAV bits in the OTG_HNPTXSTS register or NPTQXSAV bits in the OTG_HNPTXSTS register. 57.8 SOF trigger Figure 741. SOF connectivity (SOF trigger output to TIM and ITR1 connection) 62)SXOVHRXWSXWWR H[WHUQDODXGLRFRQWURO 9%86 ,75 62)SXOVH ' ' 7,0 62)JHQ ,' 86%PLFUR$%FRQQHFWRU 670 966 06Y 9 The OTG_HS core provides means to monitor, track and configure SOF framing in the host and peripheral, as well as an SOF pulse output connectivity feature. Such utilities are especially useful for adaptive audio clock generation techniques, where the audio peripheral needs to synchronize to the isochronous stream provided by the PC, or the host needs to trim its framing rate according to the requirements of the audio peripheral. 57.8.1 Host SOFs In host mode the number of PHY clocks occurring between the generation of two consecutive SOF (HS/FS) or Keep-alive (LS) tokens is programmable in the host frame interval register (HFIR), thus providing application control over the SOF framing period. An interrupt is generated at any start of frame (SOF bit in OTG_GINTSTS). The current frame number and the time remaining until the next SOF are tracked in the host frame number register (HFNUM). A SOF pulse signal, is generated at any SOF starting token and with a width of 12 system clock cycles.The SOF pulse is also internally connected to the input trigger of the timer, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. 57.8.2 Peripheral SOFs In device mode, the start of frame interrupt is generated each time an SOF token is received on the USB (SOF bit in OTG_GINTSTS). The corresponding frame number can be read from the device status register (FNSOF bit in OTG_DSTS). A SOF pulse signal with a width of 12 system clock cycles is also generated.The SOF pulse signal is also internally connected to the TIM input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. DocID029587 Rev 3 2519/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 The end of periodic frame interrupt (OTG_GINTSTS/EOPF) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (PFIVL bit in OTG_DCFG). This feature can be used to determine if all of the isochronous traffic for that frame is complete. 57.9 Power options The power consumption of the OTG PHY is controlled by two or three bits in the general core configuration register, depending on OTG revision supported. • PHY power down (OTG_GCCFG/PWRDWN) It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily set to allow any USB operation • VBUS detection enable (OTG_GCCFG/VBDEN) It switches on/off the VBUS sensing comparators associated with OTG operations Power reduction techniques are available while in the USB suspended state, when the USB session is not yet valid or the device is disconnected. • Stop PHY clock (STPPCLK bit in OTG_PCGCCTL) When setting the stop PHY clock bit in the clock gating control register, most of the 48 MHz clock domain internal to the OTG full-speed core is switched off by clock gating. The dynamic power consumption due to the USB clock switching activity is cut even if the 48 MHz clock input is kept running by the application Most of the transceiver is also disabled, and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive. • Gate HCLK (GATEHCLK bit in OTG_PCGCCTL) When setting the Gate HCLK bit in the clock gating control register, most of the system clock domain internal to the OTG_HS core is switched off by clock gating. Only the register read and write interface is kept alive. The dynamic power consumption due to the USB clock switching activity is cut even if the system clock is kept running by the application for other purposes. • USB system stop When the OTG_HS is in the USB suspended state, the application may decide to drastically reduce the overall power consumption by a complete shut down of all the clock sources in the system. USB System Stop is activated by first setting the Stop PHY clock bit and then configuring the system deep sleep mode in the power control system module (PWR). The OTG_HS core automatically reactivates both system and USB clocks by asynchronous detection of remote wakeup (as an host) or resume (as a device) signaling on the USB. To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_HS core. 57.10 Dynamic update of the OTG_HFIR register The USB core embeds a dynamic trimming capability of micro-SOF framing period in host mode allowing to synchronize an external device with the micro-SOF frames. 2520/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) When the OTG_HFIR register is changed within a current micro-SOF frame, the SOF period correction is applied in the next frame as described in Figure 742. Figure 742. Updating OTG_HFIR dynamically KůĚKd'ͺ,/&ZǀĂůƵĞ сϰϬϬƉĞƌŝŽĚƐ Kd'ͺ,/&ZǀĂůƵĞ сϰϱϬƉĞƌŝŽĚƐн,/&ZǁƌŝƚĞůĂƚĞŶĐLJ EĞǁKd'ͺ,/&ZǀĂůƵĞ сϰϱϬƉĞƌŝŽĚƐ ^K& ƌĞůŽĂĚ >ĂƚĞŶĐLJ ͙ ͙ ͙ ͙ ϭ Ϭ ϰϱϬ ϰϰϵ ϰϱϬ ϭ Ϭ ϰϱϬ ϰϰϵ &ƌĂŵĞ ƚŝŵĞƌ ϰϬϬ ϰϱϬ ϰϰϵ ǀĂůƵĞ ϭ Ϭ ϰϬϬ ϯϵϵ Kd'ͺ,&/Z ǁƌŝƚĞ ϭ Ϭ ϰϬϬ ϯϵϵ Kd'ͺ,&/Z ͙ ĂŝϭϴϰϰϬ 57.11 USB data FIFOs The USB system features 4 Kbytes of dedicated RAM with a sophisticated FIFO control mechanism. The packet FIFO controller module in the OTG_HS core organizes RAM space into Tx FIFOs into which the application pushes the data to be temporarily stored before the USB transmission, and into a single Rx FIFO where the data received from the USB are temporarily stored before retrieval (popped) by the application. The number of instructed FIFOs and how these are organized inside the RAM depends on the device’s role. In peripheral mode an additional Tx FIFO is instructed for each active IN endpoint. Any FIFO size is software configured to better meet the application requirements. DocID029587 Rev 3 2521/3178 2669 USB on-the-go high-speed (OTG_HS) 57.11.1 RM0433 Peripheral FIFO architecture Figure 743. Device-mode FIFO address mapping and AHB FIFO access mapping 6LQJOHGDWD ),)2 ,1HQGSRLQW7[),)2[ '),)2SXVKDFFHVV IURP$+% 'HGLFDWHG7[ ),)2[FRQWURO RSWLRQDO 0$&SRS ,1HQGSRLQW7[),)2 '),)2SXVKDFFHVV IURP$+% 'HGLFDWHG7[ ),)2FRQWURO RSWLRQDO 7[),)2[ SDFNHW 27*B',(37;)[> @ 27*B',(37;)[> @ 7[),)2 SDFNHW 27*B',(37;)> @ 27*B',(37;)> @ 0$&SRS ,1HQGSRLQW7[),)2 '),)2SXVKDFFHVV IURP$+% 'HGLFDWHG7[ ),)2FRQWURO RSWLRQDO 7[),)2 SDFNHW 27*B',(37;)> @ 27*B',(37;)> @ 0$&SRS $Q\287HQGSRLQW '),)2SRSDFFHVV IURP$+% 'HGLFDWHG7[ ),)2FRQWURO RSWLRQDO 0$&SXVK 5[SDFNHWV 27*B*5;)6,=> @ $ 5[VWDUWDGGUHVVIL[HG WR 06Y 9 Peripheral Rx FIFO The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT endpoints. Received packets are stacked back-to-back until free space is available in the Rx FIFO. The status of the received packet (which contains the OUT endpoint destination number, the byte count, the data PID and the validity of the received data) is also stored by the core on top of the data payload. When no more space is available, host transactions are NACKed and an interrupt is received on the addressed endpoint. The size of the receive FIFO is configured in the receive FIFO Size register (OTG_GRXFSIZ). The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in the receive RAM buffer: • All OUT endpoints share the same RAM buffer (shared FIFO) • The OTG_HS core can fill in the receive FIFO up to the limit for any host sequence of OUT tokens The application keeps receiving the Rx FIFO non-empty interrupt (RXFLVL bit in OTG_GINTSTS) as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register (OTG_GRXSTSP) and finally pops data off the receive FIFO by reading from the endpoint-related pop address. 2522/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Peripheral Tx FIFOs The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the endpoint 0 transmit FIFO size register (OTG_DIEPTXF0) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (OTG_DIEPTXFx) for IN endpoint-x. 57.11.2 Host FIFO architecture Figure 744. Host-mode FIFO address mapping and AHB FIFO access mapping 6LQJOHGDWD ),)2 $Q\SHULRGLFFKDQQHO '),)2SXVKDFFHVV IURP$+% 3HULRGLF7[),)2 FRQWURO RSWLRQDO 3HULRGLF7[ SDFNHWV 27*B+37;)6,=> @ 27*B+37;)6,=> @ 0$&SRS $Q\QRQSHULRGLF FKDQQHO'),)2SXVK DFFHVVIURP$+% 1RQSHULRGLF7[ ),)2FRQWURO 1RQSHULRGLF 7[SDFNHWV 27*B+137;)6,=> @ 27*B+137;)6,=> @ 0$&SRS 5[SDFNHWV $Q\FKDQQHO'),)2SRS DFFHVVIURP$+% 27*B*5;)6,=> @ 5[),)2FRQWURO 5[VWDUWDGGUHVVIL[HGWR $ 0$&SXVK 06Y 9 Host Rx FIFO The host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is used as a receive buffer to hold the received data (payload of the received packet) from the USB until it is transferred to the system memory. Packets received from any remote IN endpoint are stacked back-to-back until free space is available. The status of each received packet with the host channel destination, byte count, data PID and validity of the received data are also stored into the FIFO. The size of the receive FIFO is configured in the receive FIFO size register (OTG_GRXFSIZ). The single receive FIFO architecture makes it highly efficient for the USB host to fill in the receive data buffer: • All IN configured host channels share the same RAM buffer (shared FIFO) • The OTG_HS core can fill in the receive FIFO up to the limit for any sequence of IN tokens driven by the host software The application receives the Rx FIFO not-empty interrupt as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register and finally pops the data off the receive FIFO. DocID029587 Rev 3 2523/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Host Tx FIFOs The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the host periodic (nonperiodic) transmit FIFO size OTG_HPTXFSIZ / OTG_HNPTXFSIZ) register. The two Tx FIFO implementation derives from the higher priority granted to the periodic type of traffic over the USB frame. At the beginning of each frame, the built-in host scheduler processes the periodic request queue first, followed by the nonperiodic request queue. The two transmit FIFO architecture provides the USB host with separate optimization for periodic and nonperiodic transmit data buffer management: • All host channels configured to support periodic (nonperiodic) transactions in the OUT direction share the same RAM buffer (shared FIFOs) • The OTG_HS core can fill in the periodic (nonperiodic) transmit FIFO up to the limit for any sequence of OUT tokens driven by the host software The OTG_HS core issues the periodic Tx FIFO empty interrupt (PTXFE bit in OTG_GINTSTS) as long as the periodic Tx FIFO is half or completely empty, depending on the value of the periodic Tx FIFO empty level bit in the AHB configuration register (PTXFELVL bit in OTG_GAHBCFG). The application can push the transmission data in advance as long as free space is available in both the periodic Tx FIFO and the periodic request queue. The host periodic transmit FIFO and queue status register (OTG_HPTXSTS) can be read to know how much space is available in both. OTG_HS core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty depending on the non periodic Tx FIFO empty level bit in the AHB configuration register (TXFELVL bit in OTG_GAHBCFG). The application can push the transmission data as long as free space is available in both the nonperiodic Tx FIFO and nonperiodic request queue. The host nonperiodic transmit FIFO and queue status register (OTG_HNPTXSTS) can be read to know how much space is available in both. 57.11.3 FIFO RAM allocation Device mode Receive FIFO RAM allocation: the application should allocate RAM for SETUP Packets: 2524/3178 • 10 locations must be reserved in the receive FIFO to receive SETUP packets on control endpoint. The core does not use these locations, which are reserved for SETUP packets, to write any other data. • One location is to be allocated for Global OUT NAK. • Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous endpoints are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet. • Along with the last packet for each endpoint, transfer complete status information is also pushed to the FIFO. One location for each OUT endpoint is recommended. DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Device RxFIFO = (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK Example: The MPS is 1,024 bytes for a periodic USB packet and 512 bytes for a nonperiodic USB packet. There are three OUT endpoints, three IN endpoints, one control endpoint, and three host channels. Device RxFIFO = (4 * 1 + 6) + ((1,024 / 4) +1) + (2 * 4) + 1 = 276 Transmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint. Note: More space allocated in the transmit IN Endpoint FIFO results in better performance on the USB. Host mode Receive FIFO RAM allocation: Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet. Along with the last packet in the host channel, transfer complete status information is also pushed to the FIFO. So one location must be allocated for this. Host RxFIFO = (largest USB packet used / 4) + 1 for status information + 1 transfer complete Example: Host RxFIFO = ((1,024 / 4) + 1) + 1 = 258 Transmit FIFO RAM allocation: The minimum amount of RAM required for the host Non-periodic Transmit FIFO is the largest maximum packet size among all supported non-periodic OUT channels. Typically, two Largest Packet Sizes worth of space is recommended, so that when the current packet is under transfer to the USB, the CPU can get the next packet. Non-Periodic TxFIFO = largest non-periodic USB packet used / 4 Example: Non-Periodic TxFIFO = (512 / 4) = 128 The minimum amount of RAM required for host periodic Transmit FIFO is the largest maximum packet size out of all the supported periodic OUT channels. If there is at least one Isochronous OUT endpoint, then the space must be at least two times the maximum packet size of that channel. Host Periodic TxFIFO = largest periodic USB packet used / 4 Example: Host Periodic TxFIFO = (1,024 / 4) = 256 Note: More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB. DocID029587 Rev 3 2525/3178 2669 USB on-the-go high-speed (OTG_HS) 57.12 RM0433 OTG_HS interrupts When the OTG_HS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the OTG_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. Figure 745 shows the interrupt hierarchy. Figure 745. Interrupt hierarchy /2 ENDP?MULTI?PROC?INTRPT !.$ )NTERRUPT /2 ENDP?INTERRUPT;= 'LOBAL INTERRUPT MASK "IT !(" CONFIGURATION REGISTER !.$ #ORE INTERRUPT MASK REGISTER #ORE INTERRUPT REGISTER $EVICE ALL ENDPOINTS INTERRUPT REGISTER /54 ENDPOINTS ). ENDPOINTS )NTERRUPT SOURCES $EVICE )./54 ENDPOINT INTERRUPT REGISTERS TO /4' INTERRUPT REGISTER $EVICE ALL ENDPOINTS INTERRUPT MASK REGISTER $EVICE )./54 ENDPOINTS COMMON INTERRUPT MASK REGISTER $EVICE EACH ENDPOINT INTERRUPT REGISTER %0/54 %0). $EVICE EACH ENDPOINT INTERRUPT MASK REGISTER $EVICE EACH )./54 ENDPOINT INTERRUPT MASK REGISTER (OST PORT CONTROL AND STATUS REGISTER (OST ALL CHANNELS INTERRUPT REGISTER (OST CHANNELS INTERRUPT REGISTERS TO (OST ALL CHANNELS INTERRUPT MASK REGISTER (OST CHANNELS INTERRUPT MASK REGISTERS TO -3V6 1. The core interrupt register bits are shown in OTG core interrupt register (OTG_GINTSTS) on page 2542. 57.13 OTG_HS control and status registers By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_HS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. The OTG_HS registers must be accessed by words (32 bits). 2526/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) CSRs are classified as follows: • Core global registers • Host-mode registers • Host global registers • Host port CSRs • Host channel-specific registers • Device-mode registers • Device global registers • Device endpoint-specific registers • Power and clock-gating registers • Data FIFO (DFIFO) access registers Only the Core global, Power and clock-gating, Data FIFO access, and host port control and status registers can be accessed in both host and device modes. When the OTG_HS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the OTG_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. 57.13.1 CSR memory map The host and device mode registers occupy different addresses. All registers are implemented in the AHB clock domain. Global CSR map These registers are available in both host and device modes. Table 482. Core global control and status registers (CSRs) Acronym Address offset Register name OTG_GOTGCTL 0x000 Section 57.14.1: OTG control and status register (OTG_GOTGCTL) OTG_GOTGINT 0x004 Section 57.14.2: OTG interrupt register (OTG_GOTGINT) OTG_GAHBCFG 0x008 Section 57.14.3: OTG AHB configuration register (OTG_GAHBCFG) OTG_GUSBCFG 0x00C Section 57.14.4: OTG USB configuration register (OTG_GUSBCFG) OTG_GRSTCTL 0x010 Section 57.14.5: OTG reset register (OTG_GRSTCTL) OTG_GINTSTS 0x014 Section 57.14.6: OTG core interrupt register (OTG_GINTSTS) OTG_GINTMSK 0x018 Section 57.14.7: OTG interrupt mask register (OTG_GINTMSK) OTG_GRXSTSR 0x01C OTG_GRXSTSP 0x020 Section 57.14.8: OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP) OTG_GRXFSIZ 0x024 Section 57.14.9: OTG Receive FIFO size register (OTG_GRXFSIZ) OTG_HNPTXFSIZ/ OTG_DIEPTXF0(1) 0x028 Section 57.14.10: OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) DocID029587 Rev 3 2527/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Table 482. Core global control and status registers (CSRs) (continued) Acronym Address offset Register name OTG_HNPTXSTS 0x02C Section 57.14.11: OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) OTG_GI2CCTL 0x030 Section 57.14.12: OTG I2C access register (OTG_GI2CCTL) OTG_GCCFG 0x038 Section 57.14.13: OTG general core configuration register (OTG_GCCFG) OTG_CID 0x03C Section 57.14.14: OTG core ID register (OTG_CID) OTG_GLPMCFG 0x54 Section 57.14.15: OTG core LPM configuration register (OTG_GLPMCFG) OTG_HPTXFSIZ 0x100 Section 57.14.16: OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) OTG_DIEPTXFx 0x104 0x124 ... 0x1B4 Section 57.14.17: OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..8, where x is the FIFO_number) 1. The general rule is to use OTG_HNPTXFSIZ for host mode and OTG_DIEPTXF0 for device mode. Host-mode CSR map These registers must be programmed every time the core changes to host mode. Table 483. Host-mode control and status registers (CSRs) Acronym Offset address Register name OTG_HCFG 0x400 Section 57.14.19: OTG Host configuration register (OTG_HCFG) OTG_HFIR 0x404 Section 57.14.20: OTG Host frame interval register (OTG_HFIR) OTG_HFNUM 0x408 Section 57.14.21: OTG Host frame number/frame time remaining register (OTG_HFNUM) OTG_HPTXSTS 0x410 Section 57.14.22: OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) OTG_HAINT 0x414 Section 57.14.23: OTG Host all channels interrupt register (OTG_HAINT) OTG_HAINTMSK 0x418 Section 57.14.24: OTG Host all channels interrupt mask register (OTG_HAINTMSK) OTG_HPRT 0x440 Section 57.14.25: OTG Host port control and status register (OTG_HPRT) OTG_HCCHARx 0x500 0x520 ... 0x6E0 Section 57.14.26: OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..15, where x = Channel_number) 2528/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Table 483. Host-mode control and status registers (CSRs) (continued) Acronym Offset address Register name OTG_HCSPLTx 0x504 0x524 .... 0x6E4 Section 57.14.27: OTG Host channel-x split control register (OTG_HCSPLTx) (x = 0..15, where x = Channel_number) OTG_HCINTx 0x508 0x528 .... 0x6E8 Section 57.14.28: OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..15, where x = Channel_number) OTG_HCINTMSKx 0x50C 0x52C .... 0x6EC Section 57.14.29: OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..15, where x = Channel_number) OTG_HCTSIZx 0x510 0x530 .... 0x6F0 Section 57.14.30: OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..15, where x = Channel_number) OTG_HCDMAx 0x514 0x534 .... 0x6F4 Section 57.14.31: OTG Host channel-x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel_number) Device-mode CSR map These registers must be programmed every time the core changes to device mode. Table 484. Device-mode control and status registers Acronym Offset address Register name OTG_DCFG 0x800 Section 57.14.33: OTG device configuration register (OTG_DCFG) OTG_DCTL 0x804 Section 57.14.34: OTG device control register (OTG_DCTL) OTG_DSTS 0x808 Section 57.14.35: OTG device status register (OTG_DSTS) OTG_DIEPMSK 0x810 Section 57.14.36: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) OTG_DOEPMSK 0x814 Section 57.14.37: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) OTG_DAINT 0x818 Section 57.14.38: OTG device all endpoints interrupt register (OTG_DAINT) OTG_DAINTMSK 0x81C Section 57.14.39: OTG all endpoints interrupt mask register (OTG_DAINTMSK) DocID029587 Rev 3 2529/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Table 484. Device-mode control and status registers (continued) Acronym Offset address Register name OTG_DVBUSDIS 0x828 Section 57.14.40: OTG device VBUS discharge time register (OTG_DVBUSDIS) OTG_DVBUSPULSE 0x82C Section 57.14.41: OTG device VBUS pulsing time register (OTG_DVBUSPULSE) OTG_DTHRCTL 0x0830 Section 57.14.42: OTG Device threshold control register (OTG_DTHRCTL) OTG_DIEPEMPMSK 0x834 Section 57.14.43: OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) OTG_DEACHINT 0x838 Section 57.14.44: OTG device each endpoint interrupt register (OTG_DEACHINT) OTG_DEACHINTMSK 0x83C Section 57.14.45: OTG device each endpoint interrupt register mask (OTG_DEACHINTMSK) OTG_DIEPCTLx 0x900 0x920 ... 0x9E0 Section 57.14.46: OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 0..8, where x = Endpoint_number) OTG_DIEPINTx 0x908 0x928 ... 0x9E8 Section 57.14.49: OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..8, where x = Endpoint_number) OTG_DIEPTSIZ0 0x910 Section 57.14.51: OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) OTG_DIEPDMAx 0x914 Section 57.14.52: OTG Device channel-x DMA address register (OTG_DIEPDMAx) (x = 0..15, where x= Channel_number) OTG_DTXFSTSx 0x918 0x938 ..... 0x9F8 Section 57.14.56: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..8, where x = Endpoint_number) OTG_DIEPTSIZx 0x930 0x950 ... 0x9F0 Section 57.14.55: OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..8, where x= Endpoint_number) OTG_DOEPCTL0 0xB00 Section 57.14.47: OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) OTG_DOEPDMAx 0xB14 Section 57.14.52: OTG Device channel-x DMA address register (OTG_DIEPDMAx) (x = 0..15, where x= Channel_number) OTG_DOEPCTLx 0xB20 0xB40 ... 0xBE0 Section 57.14.48: OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..8, where x = Endpoint_number) 2530/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Table 484. Device-mode control and status registers (continued) Acronym Offset address Register name OTG_DOEPINTx 0xB08 0XB28 ... 0xBE8 Section 57.14.50: OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..8, where x = Endpoint_number) OTG_DOEPTSIZ0 0xB10 Section 57.14.53: OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) OTG_DOEPTSIZx 0xB30 0xB50 .. 0xBF0 Section 57.14.57: OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..8, where x = Endpoint_number) Data FIFO (DFIFO) access register map These registers, available in both host and device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel. Table 485. Data FIFO (DFIFO) access register map FIFO access register section Address range Access Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access 0x1000–0x1FFC w r Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access 0x2000–0x2FFC w r ... ... ... Device IN Endpoint x(1)/Host OUT Channel x(1): DFIFO Write Access 0xX000–0xXFFC Device OUT Endpoint x(1)/Host IN Channel x(1): DFIFO Read Access w r 1. Where x is 8 in device mode and 15 in host mode. Power and clock gating CSR map There is a single register for power and clock gating. It is available in both host and device modes. Table 486. Power and clock gating control and status registers Register name Acronym Offset address: 0xE00–0xFFF Power and clock gating control register PCGCCTL 0xE00-0xE04 Reserved - 0xE05–0xFFF DocID029587 Rev 3 2531/3178 2669 USB on-the-go high-speed (OTG_HS) 57.14 RM0433 OTG_HS registers These registers are available in both host and device modes, and do not need to be reprogrammed when switching between these modes. Bit values in the register descriptions are expressed in binary unless otherwise specified. 57.14.1 OTG control and status register (OTG_GOTGCTL) Address offset: 0x000 Reset value: 0x0X01 0000 The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG VER 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. EHEN HNP RQ HNG SCS rw r rw DHNP HSHNP EN EN rw rw 19 18 BSVLD ASVLD rw rw 16 DBCT CID STS rw r r r r 4 3 2 1 0 SRQ SRQ SCS rw r BVALO BVALO AVALO AVALO VBVAL VBVAL VAL EN VAL EN OVAL OEN rw 17 rw rw rw Bits 31:21 Reserved, must be kept at reset value. Bit 20 OTGVER: OTG version Selects the OTG revision. 0:OTG Version 1.3. OTG1.3 is obsolete for new product development. 1:OTG Version 2.0. In this version the core supports only Data line pulsing for SRP. Bit 19 BSVLD: B-session valid Indicates the device mode transceiver status. 0: B-session is not valid. 1: B-session is valid. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: Only accessible in device mode. Bit 18 ASVLD: A-session valid Indicates the host mode transceiver status. 0: A-session is not valid 1: A-session is valid Note: Only accessible in host mode. Bit 17 DBCT: Long/short debounce time Indicates the debounce time of a detected connection. 0: Long debounce time, used for physical connections (100 ms + 2.5 µs) 1: Short debounce time, used for soft connections (2.5 µs) Note: Only accessible in host mode. 2532/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 16 CIDSTS: Connector ID status Indicates the connector ID status on a connect event. 0: The OTG_HS controller is in A-device mode 1: The OTG_HS controller is in B-device mode Note: Accessible in both device and host modes. Bits 15:13 Reserved, must be kept at reset value. Bit 12 EHEN: Embedded host enable It is used to select between OTG A device state machine and embedded Host state machine. 0: OTG A device state machine is selected 1: Embedded host state machine is selected Bit 11 DHNPEN: Device HNP enabled The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host. 0: HNP is not enabled in the application 1: HNP is enabled in the application Note: Only accessible in device mode. Bit 10 HSHNPEN: host set HNP enable The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device. 0: Host Set HNP is not enabled 1: Host Set HNP is enabled Note: Only accessible in host mode. Bit 9 HNPRQ: HNP request The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared. 0: No HNP request 1: HNP request Note: Only accessible in device mode. Bit 8 HNGSCS: Host negotiation success The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPRQ) bit in this register is set. 0: Host negotiation failure 1: Host negotiation success Note: Only accessible in device mode. Bit 7 BVALOVAL: B-peripheral session valid override value. This bit is used to set override value for Bvalid signal when BVALOEN bit is set. 0: Bvalid value is '0' when BVALOEN = 1 1: Bvalid value is '1' when BVALOEN = 1 Note: Only accessible in device mode. Bit 6 BVALOEN: B-peripheral session valid override enable. This bit is used to enable/disable the software to override the Bvalid signal using the BVALOVAL bit. 0:Override is disabled and Bvalid signal from the respective PHY selected is used internally by the core 1:Internally Bvalid received from the PHY is overridden with BVALOVAL bit value Note: Only accessible in device mode. DocID029587 Rev 3 2533/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 5 AVALOVAL: A-peripheral session valid override value. This bit is used to set override value for Avalid signal when AVALOEN bit is set. 0: Avalid value is '0' when AVALOEN = 1 1: Avalid value is '1' when AVALOEN = 1 Note: Only accessible in host mode. Bit 4 AVALOEN: A-peripheral session valid override enable. This bit is used to enable/disable the software to override the Avalid signal using the AVALOVAL bit. 0:Override is disabled and Avalid signal from the respective PHY selected is used internally by the core 1:Internally Avalid received from the PHY is overridden with AVALOVAL bit value Note: Only accessible in host mode. Bit 3 VBVALOVAL: VBUS valid override value. This bit is used to set override value for vbusvalid signal when VBVALOEN bit is set. 0: vbusvalid value is '0' when VBVALOEN = 1 1: vbusvalid value is '1' when VBVALOEN = 1 Note: Only accessible in host mode. Bit 2 VBVALOEN: VBUS valid override enable. This bit is used to enable/disable the software to override the vbusvalid signal using the VBVALOVAL bit. 0: Override is disabled and vbusvalid signal from the respective PHY selected is used internally by the core 1: Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value Note: Only accessible in host mode. Bit 1 SRQ: Session request The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared. If you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, the application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this register (BSVLD bit in OTG_GOTGCTL) is cleared. This discharge time varies between different PHYs and can be obtained from the PHY vendor. 0: No session request 1: Session request Note: Only accessible in device mode. Bit 0 SRQSCS: Session request success The core sets this bit when a session request initiation is successful. 0: Session request failure 1: Session request success Note: Only accessible in device mode. 57.14.2 OTG interrupt register (OTG_GOTGINT) Address offset: 0x04 Reset value: 0x0000 0000 The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 2534/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID CHNG DBC DNE ADTO CHG HNG DET Res. rc_w1 rc_w1 rc_w1 rc_w1 15 Res. 14 13 Res. Res. 12 Res. 11 Res. 10 9 8 7 6 5 4 3 2 1 0 Res. HNSS CHG SRSS CHG Res. Res. Res. Res. Res. SEDET Res. Res. rc_w1 rc_w1 rc_w1 Bits 31:21 Reserved, must be kept at reset value. Bit 20 IDCHNG: This bit when set indicates that there is a change in the value of the ID input pin. Bit 19 DBCDNE: Debounce done The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the OTG_GUSBCFG register (HNPCAP bit or SRPCAP bit in OTG_GUSBCFG, respectively). Note: Only accessible in host mode. Bit 18 ADTOCHG: A-device timeout change The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. Note: Accessible in both device and host modes. Bit 17 HNGDET: Host negotiation detected The core sets this bit when it detects a host negotiation request on the USB. Note: Accessible in both device and host modes. Bits 16:10 Reserved, must be kept at reset value. Bit 9 HNSSCHG: Host negotiation success status change The core sets this bit on the success or failure of a USB host negotiation request. The application must read the host negotiation success bit of the OTG_GOTGCTL register (HNGSCS bit in OTG_GOTGCTL) to check for success or failure. Note: Accessible in both device and host modes. Bits 7:3 Reserved, must be kept at reset value. Bit 8 SRSSCHG: Session request success status change The core sets this bit on the success or failure of a session request. The application must read the session request success bit in the OTG_GOTGCTL register (SRQSCS bit in OTG_GOTGCTL) to check for success or failure. Note: Accessible in both device and host modes. Bit 2 SEDET: Session end detected The core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a B-Peripheral session when VBUS < 0.8 V. Note: Accessible in both device and host modes. Bits 1:0 Reserved, must be kept at reset value. 57.14.3 OTG AHB configuration register (OTG_GAHBCFG) Address offset: 0x008 Reset value: 0x0000 0000 DocID029587 Rev 3 2535/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. PTXFE LVL TXFE LVL rw rw Res. Res. Res. Res. Res. Res. Res. DMAEN rw HBSTLEN rw rw rw 0 GINT MSK rw rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 PTXFELVL: Periodic Tx FIFO empty level Indicates when the periodic Tx FIFO empty interrupt bit in the OTG_GINTSTS register (PTXFE bit in OTG_GINTSTS) is triggered. 0: PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty 1: PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty Note: Only accessible in host mode. Bit 7 TXFELVL: Tx FIFO empty level In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in OTG_DIEPINTx) is triggered: 0:The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN Endpoint Tx FIFO is half empty 1:The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN Endpoint Tx FIFO is completely empty In host mode, this bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) is triggered: 0:The NPTXFE (in OTG_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is half empty 1:The NPTXFE (in OTG_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is completely empty Bit 6 Reserved, must be kept at reset value. 2536/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 5 DMAEN: DMA enabled 0: The core operates in slave mode 1: The core operates in DMA mode Bits 4:1 HBSTLEN: Burst length/type 0000 Single: Bus transactions use single 32 bit accesses (not recommended) 0001 INCR: Bus transactions use unspecified length accesses (not recommended, uses the INCR AHB bus command) 0011 INCR4: Bus transactions target 4x 32 bit accesses 0101 INCR8: Bus transactions target 8x 32 bit accesses 0111 INCR16: Bus transactions based on 16x 32 bit accesses Others: Reserved Bit 0 GINTMSK: Global interrupt mask The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit’s setting, the interrupt status registers are updated by the core. 0: Mask the interrupt assertion to the application. 1: Unmask the interrupt assertion to the application. Note: Accessible in both device and host modes. 57.14.4 OTG USB configuration register (OTG_GUSBCFG) Address offset: 0x00C Reset value: 0x0000 1400 This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. 31 30 29 28 27 26 25 24 23 22 Res. FD MOD FH MOD Res. Res. Res. ULPI IPD PTCI PCCI TSDPS rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 TRDT HNP CAP SRP CAP Res. PHY SEL Res. rw rw rw PHYL PC rw Res. rw DocID029587 Rev 3 21 20 19 18 17 16 ULPI CSM ULPI AR ULPI FSL Res. rw rw rw rw 4 3 2 1 Res. Res. ULPIE ULPIE VBUSI VBUSD 0 TOCAL rw 2537/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 31 Reserved, must be kept at reset value. Bit 30 FDMOD: Force device mode Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin. 0: Normal mode 1: Force device mode After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. Bit 29 FHMOD: Force host mode Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin. 0: Normal mode 1: Force host mode After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. Bits 28:26 Reserved, must be kept at reset value for USB OTG HS and FS. Bit 25 ULPIIPD: ULPI interface protect disable This bit controls the circuitry built in the PHY to protect the ULPI interface when the link tristates stp and data. Any pull-up or pull-down resistors employed by this feature can be disabled. Refer to the ULPI specification for more details. 0: Enables the interface protection circuit 1: Disables the interface protection circuit Bit 24 PTCI: Indicator pass through This bit controls whether the complement output is qualified with the internal VBUS valid comparator before being used in the VBUS state in the RX CMD. Refer to the ULPI specification for more details. 0: Complement Output signal is qualified with the Internal VBUS valid comparator 1: Complement Output signal is not qualified with the Internal VBUS valid comparator Bit 23 PCCI: Indicator complement This bit controls the PHY to invert the ExternalVbusIndicator input signal, and generate the complement output. Refer to the ULPI specification for more details. 0: PHY does not invert the ExternalVbusIndicator signal 1: PHY inverts ExternalVbusIndicator signal Bit 22 TSDPS: TermSel DLine pulsing selection This bit selects utmi_termselect to drive the data line pulse during SRP (session request protocol). 0: Data line pulsing using utmi_txvalid (default) 1: Data line pulsing using utmi_termsel Bit 21 ULPIEVBUSI: ULPI external VBUS indicator This bit indicates to the ULPI PHY to use an external VBUS overcurrent indicator. 0: PHY uses an internal VBUS valid comparator 1: PHY uses an external VBUS valid comparator Bit 20 ULPIEVBUSD: ULPI External VBUS Drive This bit selects between internal or external supply to drive 5 V on VBUS, in the ULPI PHY. 0: PHY drives VBUS using internal charge pump (default) 1: PHY drives VBUS using external supply. 2538/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 19 ULPICSM: ULPI Clock SuspendM This bit sets the ClockSuspendM bit in the interface control register on the ULPI PHY. This bit applies only in the serial and carkit modes. 0: PHY powers down the internal clock during suspend 1: PHY does not power down the internal clock Bit 18 ULPIAR: ULPI Auto-resume This bit sets the AutoResume bit in the interface control register on the ULPI PHY. 0: PHY does not use AutoResume feature 1: PHY uses AutoResume feature Bit 17 ULPIFSLS: ULPI FS/LS select The application uses this bit to select the FS/LS serial interface for the ULPI PHY. This bit is valid only when the FS serial transceiver is selected on the ULPI PHY. 0: ULPI interface 1: ULPI FS/LS serial interface Bit 16 Reserved, must be kept at reset value . Bit 15 PHYLPCS: PHY Low-power clock select This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48 MHz clock to save power. 0: 480 MHz internal PLL clock 1: 48 MHz external clock In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates at 48 MHz in FS and LS modes. Bit 14 Reserved, must be kept at reset value. Bits 13:10 TRDT: USB turnaround time These bits allows to set the turnaround time in PHY clocks. They must be configured according to or Table 488: TRDT values (HS), depending on the application AHB frequency. Higher TRDT values allow stretching the USB response time to IN tokens in order to compensate for longer AHB read access latency to the Data FIFO. Note: Only accessible in device mode. Bit 9 HNPCAP: HNP-capable The application uses this bit to control the OTG_HS controller’s HNP capabilities. 0: HNP capability is not enabled. 1: HNP capability is enabled. Note: Accessible in both device and host modes. Bit 8 SRPCAP: SRP-capable The application uses this bit to control the OTG_HS controller’s SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate VBUS and start a session. 0: SRP capability is not enabled. 1: SRP capability is enabled. Note: Accessible in both device and host modes. Bit 7 Reserved, must be kept at reset value. Bit 6 PHYSEL: Full Speed serial transceiver select 0: USB 2.0 external ULPI high-speed PHY 1: USB 1.1 full-speed serial transceiver. DocID029587 Rev 3 2539/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 5 Reserved, must be kept at reset value . Bit 4 Reserved, must be kept at reset value Bit3 Reserved, must be kept at reset value if UTMI interface is present. Bits 2:0 TOCAL: FS timeout calibration The number of PHY clocks that the application programs in this field is added to the fullspeed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the line state condition can vary from one PHY to another. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock is 0.25 bit times. Table 487. TRDT values AHB frequency range (MHz) TRDT minimum value Min Max 14.2 15 0xF 15 16 0xE 16 17.2 0xD 17.2 18.5 0xC 18.5 20 0xB 20 21.8 0xA 21.8 24 0x9 24 27.5 0x8 27.5 32 0x7 32 - 0x6 Table 488. TRDT values (HS) AHB frequency range (MHz) TRDT minimum value 57.14.5 Min Max 30 - 0x9 OTG reset register (OTG_GRSTCTL) Address offset: 0x10 Reset value: 0x8000 0000 The application uses this register to reset various hardware features inside the core. 2540/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AHB IDL DMAR EQ Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r 15 14 13 12 11 10 9 8 7 6 1 0 Res. Res. Res. Res. Res. 5 4 3 2 TXFNUM TXF FLSH RXF FLSH Res. Res. rw rs rs PSRST CSRST rs rs Bit 31 AHBIDL: AHB master idle Indicates that the AHB master state machine is in the Idle condition. Note: Accessible in both device and host modes. Bit 30 DMAREQ: DMA request signal enabled This bit indicates that the DMA request is in progress. Used for debug. Bits 29:11 Reserved, must be kept at reset value. Bits 10:6 TXFNUM: Tx FIFO number This is the FIFO number that must be flushed using the Tx FIFO Flush bit. This field must not be changed until the core clears the Tx FIFO Flush bit. 00000: – Non-periodic Tx FIFO flush in host mode – Tx FIFO 0 flush in device mode 00001: – Periodic Tx FIFO flush in host mode – Tx FIFO 1 flush in device mode 00010: Tx FIFO 2 flush in device mode ... 01111: Tx FIFO 15 flush in device mode 10000: Flush all the transmit FIFOs in device or host mode. Note: Accessible in both device and host modes. Bit 5 TXFFLSH: Tx FIFO flush This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the Tx FIFO nor reading from the Tx FIFO. Verify using these registers: Read—NAK Effective Interrupt ensures the core is not reading from the FIFO Write—AHBIDL bit in OTG_GRSTCTL ensures the core is not writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk. Note: Accessible in both device and host modes. Bit 4 RXFFLSH: Rx FIFO flush The application can flush the entire Rx FIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the Rx FIFO nor writing to the Rx FIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks (slowest of PHY or AHB clock) to clear. Note: Accessible in both device and host modes. DocID029587 Rev 3 2541/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 3 Reserved, must be kept at reset value. Bit 2 Reserved, must be kept at reset value . Bit 1 PSRST: Partial soft reset Resets the internal state machines but keeps the enumeration info. Could be used to recover some specific PHY errors. Note: Accessible in both device and host modes. Bit 0 CSRST: Core soft reset Resets the HCLK and PHY clock domains as follows: Clears the interrupts and all the CSR register bits except for the following bits: – GATEHCLK bit in OTG_PCGCCTL – STPPCLK bit in OTG_PCGCCTL – FSLSPCS bits in OTG_HCFG – DSPD bit in OTG_DCFG – SDIS bit in OTG_DCTL – OTG_GCCFG register All module state machines (except for the AHB slave unit) are reset to the Idle state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soon as possible, after completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit has been cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). The software must also check that bit 31 in this register is set to 1 (AHB Master is Idle) before starting any operation. Typically, the software reset is used during software development and also when you dynamically change the PHY selection bits in the above listed USB configuration registers. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation. Note: Accessible in both device and host modes. 57.14.6 OTG core interrupt register (OTG_GINTSTS) Address offset: 0x014 Reset value: 0x1400 0020 This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 2542/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 31 30 29 28 WKUP INT SRQ INT DISC INT CIDS CHG rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 27 Res. 11 26 25 PTXFE HCINT 24 HPRT INT 23 22 21 20 19 18 17 16 Res. DATAF SUSP IPXFR/ IN COMP ISO OUT IISOI XFR OEP INT IEPINT Res. Res. rc_w1 rc_w1 rc_w1 r r r r r 10 9 8 7 6 5 4 3 2 1 0 Res. GO NAK EFF GI NAK EFF NPTXF E RXF LVL SOF OTG INT MMIS CMOD r r r r rc_w1 r rc_w1 r EOPF ISOO DRP ENUM DNE USB RST USB SUSP ESUSP rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Res. Bit 31 WKUPINT: Resume/remote wakeup detected interrupt Wakeup interrupt during suspend(L2) or LPM(L1) state. – During suspend(L2): In device mode, this interrupt is asserted when a resume is detected on the USB. In host mode, this interrupt is asserted when a remote wakeup is detected on the USB. – During LPM(L1): This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB. Note: Accessible in both device and host modes. Bit 30 SRQINT: Session request/new session detected interrupt In host mode, this interrupt is asserted when a session request is detected from the device. In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral device. Accessible in both device and host modes. Bit 29 DISCINT: Disconnect detected interrupt Asserted when a device disconnect is detected. Note: Only accessible in host mode. Bit 28 CIDSCHG: Connector ID status change The core sets this bit when there is a change in connector ID status. Note: Accessible in both device and host modes. Bit 27 Reserved, must be kept at reset value . Bit 26 PTXFE: Periodic Tx FIFO empty Asserted when the periodic transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. The half or completely empty status is determined by the periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (PTXFELVL bit in OTG_GAHBCFG). Note: Only accessible in host mode. Bit 25 HCINT: Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_HCINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the OTG_HCINTx register to clear this bit. Note: Only accessible in host mode. DocID029587 Rev 3 2543/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 24 HPRTINT: Host port interrupt The core sets this bit to indicate a change in port status of one of the OTG_HS controller ports in host mode. The application must read the OTG_HPRT register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_HPRT register to clear this bit. Note: Only accessible in host mode. Bit 23 Reserved, must be kept at reset value . Bit 22 DATAFSUSP: Data fetch suspended This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or request queue space. This interrupt is used by the application for an endpoint mismatch algorithm. For example, after detecting an endpoint mismatch, the application: – Sets a global nonperiodic IN NAK handshake – Disables IN endpoints – Flushes the FIFO – Determines the token sequence from the IN token sequence learning queue – Re-enables the endpoints Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an “IN token received when FIFO empty” interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the “IN token received when FIFO empty” interrupt when clearing a global IN NAK handshake. Bit 21 IPXFR: Incomplete periodic transfer In host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. INCOMPISOOUT: Incomplete isochronous OUT transfer In device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. Bit 20 IISOIXFR: Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. Note: Only accessible in device mode. Bit 19 OEPINT: OUT endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding OTG_DOEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DOEPINTx register to clear this bit. Note: Only accessible in device mode. 2544/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 18 IEPINT: IN endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred, and then read the corresponding OTG_DIEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DIEPINTx register to clear this bit. Note: Only accessible in device mode. Bits 17:16 Reserved, must be kept at reset value. Bit 15 EOPF: End of periodic frame interrupt Indicates that the period specified in the periodic frame interval field of the OTG_DCFG register (PFIVL bit in OTG_DCFG) has been reached in the current frame. Note: Only accessible in device mode. Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the Rx FIFO because the Rx FIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint. Note: Only accessible in device mode. Bit 13 ENUMDNE: Enumeration done The core sets this bit to indicate that speed enumeration is complete. The application must read the OTG_DSTS register to obtain the enumerated speed. Note: Only accessible in device mode. Bit 12 USBRST: USB reset The core sets this bit to indicate that a reset is detected on the USB. Note: Only accessible in device mode. Bit 11 USBSUSP: USB suspend The core sets this bit to indicate that a suspend was detected on the USB. The core enters the Suspended state when there is no activity on the data lines for an extended period of time. Note: Only accessible in device mode. Bit 10 ESUSP: Early suspend The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms. Note: Only accessible in device mode. Bits 9:8 Reserved, must be kept at reset value. Bit 7 GONAKEFF: Global OUT NAK effective Indicates that the Set global OUT NAK bit in the OTG_DCTL register (SGONAK bit in OTG_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_DCTL register (CGONAK bit in OTG_DCTL). Note: Only accessible in device mode. DocID029587 Rev 3 2545/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 6 GINAKEFF: Global IN non-periodic NAK effective Indicates that the Set global non-periodic IN NAK bit in the OTG_DCTL register (SGINAK bit in OTG_DCTL), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear global non-periodic IN NAK bit in the OTG_DCTL register (CGINAK bit in OTG_DCTL). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit. Note: Only accessible in device mode. Bit 5 NPTXFE: Non-periodic Tx FIFO empty This interrupt is asserted when the non-periodic Tx FIFO is either half or completely empty, and there is space for at least one entry to be written to the non-periodic transmit request queue. The half or completely empty status is determined by the non-periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). Note: Accessible in host mode only. Bit 4 RXFLVL: Rx FIFO non-empty Indicates that there is at least one packet pending to be read from the Rx FIFO. Note: Accessible in both host and device modes. Bit 3 SOF: Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the OTG_DSTS register to get the current frame number. This interrupt is seen only when the core is operating in FS. Note: This register may return '1' if read immediately after power on reset. If the register bit reads '1' immediately after power on reset it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode). The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit. Note: Accessible in both host and device modes. Bit 2 OTGINT: OTG interrupt The core sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (OTG_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_GOTGINT register to clear this bit. Note: Accessible in both host and device modes. Bit 1 MMIS: Mode mismatch interrupt The core sets this bit when the application is trying to access: – A host mode register, when the core is operating in device mode – A device mode register, when the core is operating in host mode The register access is completed on the AHB with an OKAY response, but is ignored by the core internally and does not affect the operation of the core. Note: Accessible in both host and device modes. Bit 0 CMOD: Current mode of operation Indicates the current mode. 0: Device mode 1: Host mode Note: Accessible in both host and device modes. 2546/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.7 OTG interrupt mask register (OTG_GINTMSK) Address offset: 0x018 Reset value: 0x0000 0000 This register works with the Core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the Core Interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set. 31 30 WUIM SRQIM rw rw 15 14 EOPF M ISOOD RPM rw rw 29 28 DISCIN CIDSC T HGM 27 26 LPMIN PTXFE TM M 25 24 IISOIX FRM 19 RSTDE TM FSUS PM rw rw rw rw rw 7 6 5 4 3 rw rw r 13 12 11 10 9 8 rw 20 PRTIM rw rw 21 HCIM rw rw 22 IPXFR M/IISO OXFR M rw ENUM USBRS USBSU ESUSP DNEM T SPM M 23 Res. Res. rw GONA GINAK NPTXF RXFLV KEFFM EFFM EM LM rw rw rw rw 18 OEPIN IEPINT T SOFM rw 17 16 Res. Res. 1 0 rw 2 OTGIN MMISM T rw Res. rw Bit 31 WUIM: Resume/remote wakeup detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 30 SRQIM: Session request/new session detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 29 DISCINT: Disconnect detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 28 CIDSCHGM: Connector ID status change mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 27 LPMINTM: LPM interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 26 PTXFEM: Periodic Tx FIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. Bit 25 HCIM: Host channels interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. DocID029587 Rev 3 2547/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 24 PRTIM: Host port interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. Bit 23 RSTDETM: Reset detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 22 FSUSPM: Data fetch suspended mask 0: Masked interrupt 1: Unmasked interrupt Only accessible in peripheral mode. Bit 21 IPXFRM: Incomplete periodic transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. IISOOXFRM: Incomplete isochronous OUT transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 20 IISOIXFRM: Incomplete isochronous IN transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 19 OEPINT: OUT endpoints interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 18 IEPINT: IN endpoints interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bits 17:16 Reserved, must be kept at reset value. Bit 15 EOPFM: End of periodic frame interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 13 ENUMDNEM: Enumeration done mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. 2548/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 12 USBRST: USB reset mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 11 USBSUSPM: USB suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 10 ESUSPM: Early suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bits 9:8 Reserved, must be kept at reset value. Bit 7 GONAKEFFM: Global OUT NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 6 GINAKEFFM: Global non-periodic IN NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 5 NPTXFEM: Non-periodic Tx FIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Host mode. Bit 4 RXFLVLM: Receive FIFO non-empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 3 SOFM: Start of frame mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 2 OTGINT: OTG interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 1 MMISM: Mode mismatch interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 0 Reserved, must be kept at reset value. DocID029587 Rev 3 2549/3178 2669 USB on-the-go high-speed (OTG_HS) 57.14.8 RM0433 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP) Address offset for Read: 0x01C Address offset for Pop: 0x020 Reset value: 0x0000 0000 A read to the Receive status debug read register returns the contents of the top of the Receive FIFO. A read to the Receive status read and pop register additionally pops the top data entry out of the Rx FIFO. The receive status contents must be interpreted differently in host and device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x0000 0000. The application must only pop the Receive Status FIFO when the Receive FIFO non-empty bit of the Core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted. Host mode: 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 DPID r 9 8 7 6 5 20 19 18 PKTSTS r r r r r DPID r r r r 4 3 2 1 0 CHNUM r r r r r r r Bits 31:21 Reserved, must be kept at reset value. Bits 20:17 PKTSTS: Packet status Indicates the status of the received packet 0010: IN data packet received 0011: IN transfer completed (triggers an interrupt) 0101: Data toggle error (triggers an interrupt) 0111: Channel halted (triggers an interrupt) Others: Reserved Bits 16:15 DPID: Data PID Indicates the Data PID of the received packet 00: DATA0 10: DATA1 01: DATA2 11: MDATA Bits 14:4 BCNT: Byte count Indicates the byte count of the received IN data packet. Bits 3:0 CHNUM: Channel number Indicates the channel number to which the current received packet belongs. 2550/3178 16 r BCNT r 17 DocID029587 Rev 3 r r RM0433 USB on-the-go high-speed (OTG_HS) Device mode: 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 DPID 9 24 23 22 21 20 FRMNUM 19 18 PKTSTS r r r r r r 16 DPID r r r r r r r r r 8 7 6 5 4 3 2 1 0 BCNT r 17 EPNUM r r r r r r r r r Bits 31:25 Reserved, must be kept at reset value. Bits 24:21 FRMNUM: Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. Bits 20:17 PKTSTS: Packet status Indicates the status of the received packet 0001: Global OUT NAK (triggers an interrupt) 0010: OUT data packet received 0011: OUT transfer completed (triggers an interrupt) 0100: SETUP transaction completed (triggers an interrupt) 0110: SETUP data packet received Others: Reserved Bits 16:15 DPID: Data PID Indicates the Data PID of the received OUT data packet 00: DATA0 10: DATA1 01: DATA2 11: MDATA Bits 14:4 BCNT: Byte count Indicates the byte count of the received data packet. Bits 3:0 EPNUM: Endpoint number Indicates the endpoint number to which the current received packet belongs. 57.14.9 OTG Receive FIFO size register (OTG_GRXFSIZ) Address offset: 0x024 Reset value: 0x0000 0400 The application can program the RAM size that must be allocated to the Rx FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw RXFD rw rw rw rw rw rw rw rw DocID029587 Rev 3 2551/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RXFD: Rx FIFO depth This value is in terms of 32-bit words. Maximum value is 1024 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. 57.14.10 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) Address offset: 0x028 Reset value: 0x0200 0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NPTXFD/TX0FD rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NPTXFSA/TX0FSA rw rw rw rw rw rw rw rw rw Host mode Bits 31:16 NPTXFD: Non-periodic Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. Bits 15:0 NPTXFSA: Non-periodic transmit RAM start address This field configures the memory start address for non-periodic transmit FIFO RAM. Device mode Bits 31:16 TX0FD: Endpoint 0 Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address This field configures the memory start address for the endpoint 0 transmit FIFO RAM. 2552/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) Address offset: 0x02C Reset value: 0x0008 0400 Note: In Device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. 31 30 29 28 Res. 15 27 26 25 24 23 22 21 NPTXQTOP 20 19 18 17 16 NPTQXSAV r r r r r r r r r r r r r r r 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r NPTXFSAV r r r r r r r r r Bit 31 Reserved, must be kept at reset value. Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Bits 30:27: Channel/endpoint number Bits 26:25: 00: IN/OUT token 01: Zero-length transmit packet (device IN/host OUT) 11: Channel halt command Bit 24: Terminate (last entry for selected channel/endpoint) Bits 23:16 NPTQXSAV: Non-periodic transmit request queue space available Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests. 0: Non-periodic transmit request queue is full 1: 1 location available 2: locations available n: n locations available (0 ≤ n ≤ 8) Others: Reserved Bits 15:0 NPTXFSAV: Non-periodic Tx FIFO space available Indicates the amount of free space available in the non-periodic Tx FIFO. Values are in terms of 32-bit words. 0: Non-periodic Tx FIFO is full 1: 1 word available 2: 2 words available n: n words available (where 0 ≤ n ≤ 512) Others: Reserved 57.14.12 OTG I2C access register (OTG_GI2CCTL) Address offset: 0x030 Reset value: 0x0000 0000 DocID029587 Rev 3 2553/3178 2669 USB on-the-go high-speed (OTG_HS) 31 30 29 28 BSY DNE RW. Res. I2CD ATSE rw rw 15 14 13 27 26 I2CDEVADR rw rw rw 12 11 10 RM0433 25 24 23 Res. ACK I2CEN rw rw rw rw rw 8 7 6 5 4 9 22 21 rw rw rw rw 19 18 17 16 rw rw rw rw 3 2 1 0 rw rw rw ADDR REGADDR rw 20 RWDATA rw rw rw rw rw rw rw rw Bit 31 BSYDNE: I2C Busy/Done The application sets this bit to 1 to start a request on the I2C interface. When the transfer is complete, the core deasserts this bit to 0. As long as the bit is set indicating that the I2C interface is busy, the application cannot start another request on the interface. Bit 30 RW: Read/Write Indicator This bit indicates whether a read or write register transfer must be performed on the interface. 0: Write 1: Read Note: Read/write bursting is not supported for registers. Bit 29 Reserved, must be kept at reset value. Bit 28 I2CDATSE0: I2C DatSe0 USB mode This bit is used to select the full-speed interface USB mode. 0: VP_VM USB mode 1: DAT_SE0 USB mode Bits 27:26 I2CDEVADR: I2C Device Address This bit selects the address of the I2C slave on the USB 1.1 full-speed serial transceiver corresponding to the one used by the core for OTG signalling. Bit 25 Reserved, must be kept at reset value. Bit 24 ACK: I2C ACK This bit indicates whether an ACK response was received from the I2C slave. It is valid when BSYDNE is cleared by the core, after the application has initiated an I2C access. 0: NAK 1: ACK Bit 23 I2CEN: I2C Enable This bit enables the I2C master to initiate transactions on the I2C interface. Bits 22:16 ADDR: I2C Address This is the 7-bit I2C device address used by the application to access any external I2C slave, including the I2C slave on a USB 1.1 OTG full-speed serial transceiver. Bits 15:8 REGADDR: I2C Register Address These bits allow to program the address of the register to be read from or written to. Bits 7:0 RWDATA: I2C Read/Write Data After a register read operation, these bits hold the read data for the application. During a write operation, the application can use this register to program the data to be written to a register. 2554/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.13 OTG general core configuration register (OTG_GCCFG) Address offset: 0x038 Reset value: 0x0000 XXX0 31 Res. 15 Res. 30 Res. 14 Res. 29 Res. 13 Res. 28 Res. 12 Res. 27 Res. 11 Res. 26 Res. 10 Res. 25 Res. 9 24 Res. 23 Res. 8 Res. Res. 22 Res. 7 Res. 6 Res. 21 20 19 18 17 16 BCDEN PWR DWN VBDEN SDEN PDEN DCD EN rw rw rw rw rw rw 5 4 3 2 1 0 Res. PS2 DET SDET PDET DCDET r r r r Res. Bits 31:22 Reserved, must be kept at reset value. Bit 21 VBDEN: USB VBUS detection enable Enables VBUS sensing comparators to detect VBUS valid levels on the VBUS PAD for USB host and device operation. If HNP and/or SRP support is enabled, VBUS comparators are automatically enabled independently of VBDEN value. 0 = VBUS Detection Disabled 1 = VBUS Detection Enabled Bit 20 SDEN: Secondary detection (SD) mode enable This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly Bit 19 PDEN: Primary detection (PD) mode enable This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. Bit 18 DCDEN: Data contact detection (DCD) mode enable This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. (TO BE CLARIFIED) Bit 17 BCDEN: Battery charging detector (BCD) enable This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to ‘0’ in order to allow the normal USB operation. Bit 16 PWRDWN: Power down control Used to activate the transceiver in transmission/reception. When reset, the transceiver is kept in power-down. When set, the BCD function must be off (BCDEN=0). 0 = USB FS transceiver disabled 1 = USB FS transceiver enabled Bits 15:4 Reserved, must be kept at reset value. DocID029587 Rev 3 2555/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 3 PS2DET: DM pull-up detection status This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. 0: Normal port detected (connected to SDP, CDP or DCP) 1: PS2 port or proprietary charger detected Bit 2 SDET: Secondary detection (SD) status This bit gives the result of SD. 0: CDP detected 1: DCP detected Bit 1 PDET: Primary detection (PD) status This bit gives the result of PD. 0: no BCD support detected (connected to SDP or proprietary device). 1: BCD support detected (connected to CDP or DCP). Bit 0 DCDET: Data contact detection (DCD) status This bit gives the result of DCD. 0: data lines contact not detected 1: data lines contact detected 57.14.14 OTG core ID register (OTG_CID) Address offset: 0x03C Reset value: 0x0000 3100 This is a read only register containing the Product ID. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PRODUCT_ID rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw 18 17 PRODUCT_ID rw rw rw rw rw rw rw rw rw Bits 31:0 PRODUCT_ID: Product ID field Application-programmable ID field. 57.14.15 OTG core LPM configuration register (OTG_GLPMCFG) Address offset: 0x54 Reset value: 0x0000 0000 31 Res. 30 Res. 29 28 Res. EN BESL rw 2556/3178 27 26 25 LPMRCNTSTS r r 24 23 SND LPM r rs 22 21 20 LPMRCNT rw rw DocID029587 Rev 3 19 LPMCHIDX rw rw rw rw 16 L1RSM OK rw r RM0433 15 SLP STS r USB on-the-go high-speed (OTG_HS) 14 13 LPMRSP r r 12 11 L1DS EN rw 10 9 8 BESLTHRS rw rw rw rw 7 6 L1SS EN REM WAKE rw rw/r 5 4 3 2 BESL rw/r rw/r rw/r rw/r 1 0 LPM ACK LPM EN rw rw Bits 31:29 Reserved, must be kept at reset value. Bit 28 ENBESL: Enable best effort service latency This bit enables the BESL feature as defined in the LPM errata: 0:The core works as described in the following document: USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification, July 16, 2007 1:The core works as described in the LPM Errata: Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007 Note: Only the updated behavior (described in LPM Errata) is considered in this document and so the ENBESL bit should be set to '1' by application SW. Bits 27:25 LPMRCNTSTS: LPM retry count status Number of LPM host retries still remaining to be transmitted for the current LPM sequence. Note: Accessible only in host mode. Bit 24 SNDLPM: Send LPM transaction When the application software sets this bit, an LPM transaction containing two tokens, EXT and LPM is sent. The hardware clears this bit once a valid response (STALL, NYET, or ACK) is received from the device or the core has finished transmitting the programmed number of LPM retries. Note: This bit must be set only when the host is connected to a local port. Note: Accessible only in host mode. Bits 23:21 LPMRCNT: LPM retry count When the device gives an ERROR response, this is the number of additional LPM retries that the host performs until a valid device response (STALL, NYET, or ACK) is received. Note: Accessible only in host mode. Bits 20:17 LPMCHIDX: LPM Channel Index The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. Based on the LPM channel index, the core automatically inserts the device address and endpoint number programmed in the corresponding channel into the LPM transaction. Note: Accessible only in host mode. Bit 16 L1RSMOK: Sleep State Resume OK Indicates that the device or host can start resume from Sleep state. This bit is valid in LPM sleep (L1) state. It is set in sleep mode after a delay of 50 μs (TL1Residency). This bit is reset when SLPSTS is 0. 1: The application or host can start resume from Sleep state 0: The application or host cannot start resume from Sleep state DocID029587 Rev 3 2557/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 15 SLPSTS: Port sleep status Device mode: This bit is set as long as a Sleep condition is present on the USB bus. The core enters the Sleep state when an ACK response is sent to an LPM transaction and the TL1TokenRetry timer has expired. To stop the PHY clock, the application must set the STPPCLK bit in OTG_PCGCCTL, which asserts the PHY Suspend input signal. The application must rely on SLPSTS and not ACK in LPMRSP to confirm transition into sleep. The core comes out of sleep: – When there is any activity on the USB linestate – When the application writes to the RWUSIG bit in OTG_DCTL or when the application resets or soft-disconnects the device. Host mode: The host transitions to Sleep (L1) state as a side-effect of a successful LPM transaction by the core to the local port with ACK response from the device. The read value of this bit reflects the current Sleep status of the port. The core clears this bit after: – The core detects a remote L1 Wakeup signal, – The application sets the PRST bit or the PRES bit in the OTG_HPRT register, or – The application sets the L1Resume/ Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register (WKUPINT or DISCINT bit in OTG_GINTSTS, respectively). 0: Core not in L1 1: Core in L1 Bits 14:13 LPMRST: LPM response Device mode: The response of the core to LPM transaction received is reflected in these two bits. Host mode: Handshake response received from local device for LPM transaction 11: ACK 10: NYET 01: STALL 00: ERROR (No handshake response) Bit 12 L1DSEN: L1 deep sleep enable Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. 2558/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bits11:8 BESLTHRS: BESL threshold Device mode: The core puts the PHY into deep low power mode in L1 when BESL value is greater than or equal to the value defined in this field BESL_Thres[3:0]. Host mode: The core puts the PHY into deep low power mode in L1. BESLTHRS[3:0] specifies the time for which resume signaling is to be reflected by host (TL1HubDrvResume2) on the USB bus when it detects device initiated resume. BESLTHRS must not be programmed with a value greater than 1100b in host mode, because this exceeds maximum TL1HubDrvResume2. Thres[3:0]Host mode resume signaling time (μs) 0000:75 0001:100 0010:150 0011:250 0100:350 0101:450 0110:950 All other values:reserved Bit 7 L1SSEN: L1 Shallow Sleep enable Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. Bit 6 REMWAKE: bRemoteWake value Host mode: The value of remote wake up to be sent in the wIndex field of LPM transaction. Device mode (read-only): This field is updated with the received LPM token bRemoteWake bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. DocID029587 Rev 3 2559/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bits 5:2 BESL: Best effort service latency Host mode: The value of BESL to be sent in an LPM transaction. This value is also used to initiate resume for a duration TL1HubDrvResume1 for host initiated resume. Device mode (read-only): This field is updated with the received LPM token BESL bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. BESL[3:0]TBESL (μs) 0000:125 0001:150 0010:200 0011:300 0100:400 0101:500 0110:1000 0111:2000 1000:3000 1001:4000 1010:5000 1011:6000 1100:7000 1101:8000 1110:9000 1111:10000 Bit 1 LPMACK: LPM token acknowledge enable Handshake response to LPM token preprogrammed by device application software. 1:ACK Even though ACK is preprogrammed, the core Device responds with ACK only on successful LPM transaction. The LPM transaction is successful if: – No PID/CRC5 Errors in either EXT token or LPM token (else ERROR) – Valid bLinkState = 0001B (L1) received in LPM transaction (else STALL) – No data pending in transmit queue (else NYET). 0:NYET The preprogrammed software bit is over-ridden for response to LPM token when: – The received bLinkState is not L1 (STALL response), or – An error is detected in either of the LPM token packets because of corruption (ERROR response). Note: Accessible only in device mode. Bit 0 LPMEN: LPM support enable The application uses this bit to control the OTG_HS core LPM capabilities. If the core operates as a non-LPM-capable host, it cannot request the connected device or hub to activate LPM mode. If the core operates as a non-LPM-capable device, it cannot respond to any LPM transactions. 0: LPM capability is not enabled 1: LPM capability is enabled 2560/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.16 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) Address offset: 0x100 Reset value: 0x0200 0400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PTXFSIZ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw PTXSA rw rw rw rw rw rw rw rw Bits 31:16 PTXFD: Host periodic Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Bits 15:0 PTXSA: Host periodic Tx FIFO start address This field configures the memory start address for periodic transmit FIFO RAM. 57.14.17 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..8, where x is the FIFO_number) Address offset: 0x104 + (FIFO_number – 1) × 0x04 Reset values: FIFO_number = 8: 0x0200 0200 + (8 31 30 29 28 27 26 25 24 * 0x200) 23 22 21 20 19 18 17 16 INEPTXFD rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INEPTXSA rw rw rw rw rw rw rw rw rw Bits 31:16 INEPTXFD: IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 57.14.18 Host-mode registers Bit values in the register descriptions are expressed in binary unless otherwise specified. DocID029587 Rev 3 2561/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Host-mode registers affect the operation of the core in the host mode. Host mode registers must not be accessed in device mode, as the results are undefined. Host mode registers can be categorized as follows: 57.14.19 OTG Host configuration register (OTG_HCFG) Address offset: 0x400 Reset value: 0x0000 0000 This register configures the core after power-on. Do not make changes to this register after initializing the host. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. FSLSS Res. r FSLSPCS rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 Reserved, must be kept at reset value. Bit 22:3 Reserved, must be kept at reset value. Bit 2 FSLSS: FS- and LS-only support The application uses this bit to control the core’s enumeration speed. Using this bit, the application can make the core enumerate as an FS host, even if the connected device supports HS traffic. Do not make changes to this field after initial programming. Bits 1:0 FSLSPCS: FS/LS PHY clock select When the core is in FS host mode 01: PHY clock is running at 48 MHz Others: Reserved When the core is in LS host mode 00: Reserved 01: Select 48 MHz PHY clock frequency 10: Select 6 MHz PHY clock frequency 11: Reserved Note: The FSLSPCS must be set on a connection event according to the speed of the connected device (after changing this bit, a software reset must be performed). 57.14.20 OTG Host frame interval register (OTG_HFIR) Address offset: 0x404 Reset value: 0x0000 EA60 This register stores the frame interval information for the current speed to which the OTG_HS controller has enumerated. 2562/3178 DocID029587 Rev 3 rw RM0433 USB on-the-go high-speed (OTG_HS) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RLD CTRL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw FRIVL rw rw rw rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 RLDCTRL: Reload control This bit allows dynamic reloading of the HFIR register during run time. 0: The HFIR cannot be reloaded dynamically 1: The HFIR can be dynamically reloaded during runtime. This bit needs to be programmed during initial configuration and its value must not be changed during runtime. Bits 15:0 FRIVL: Frame interval The value that the application programs to this field, specifies the interval between two consecutive micro-SOFs (HS) or Keep-Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application can write a value to this register only after the Port enable bit of the host port control and status register (PENA bit in OTG_HPRT) has been set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY Clock Select field of the host configuration register (FSLSPCS in OTG_HCFG). Do not change the value of this field after the initial configuration, unless the RLDCTRL bit is set. In such case, the FRIVL is reloaded with each SOF event. 57.14.21 OTG Host frame number/frame time remaining register (OTG_HFNUM) Address offset: 0x408 Reset value: 0x0000 3FFF This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FTREM r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r FRNUM r r r r r r r r r Bits 31:16 FTREM: Frame time remaining Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This field decrements on each PHY clock. When it reaches zero, this field is reloaded with the value in the Frame interval register and a new SOF is transmitted on the USB. Bits 15:0 FRNUM: Frame number This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when it reaches 0x3FFF. DocID029587 Rev 3 2563/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 57.14.22 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) Address offset: 0x410 Reset value: 0x0008 0100 This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. 31 30 29 28 27 26 25 24 23 22 21 PTXQTOP 20 19 18 17 16 PTXQSAV r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r PTXFSAVL r r r r r r r r r Bits 31:24 PTXQTOP: Top of the periodic transmit request queue This indicates the entry in the periodic Tx request queue that is currently being processed by the MAC. This register is used for debugging. Bit 31: Odd/Even frame 0: send in even frame 1: send in odd frame Bits 30:27: Channel/endpoint number Bits 26:25: Type 00: IN/OUT 01: Zero-length packet 11: Disable channel command Bit 24: Terminate (last entry for the selected channel/endpoint) Bits 23:16 PTXQSAV: Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. 00: Periodic transmit request queue is full 01: 1 location available 10: 2 locations available bxn: n locations available (0 ≤ n ≤ 8) Others: Reserved Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available Indicates the number of free locations available to be written to in the periodic Tx FIFO. Values are in terms of 32-bit words 0000: Periodic Tx FIFO is full 0001: 1 word available 0010: 2 words available bxn: n words available (where 0 ≤ n ≤ PTXFD) Others: Reserved 57.14.23 OTG Host all channels interrupt register (OTG_HAINT) Address offset: 0x414 2564/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Reset value: 0x0000 000 When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the Core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure 745. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r HAINT r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 HAINT: Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 57.14.24 OTG Host all channels interrupt mask register (OTG_HAINTMSK) Address offset: 0x418 Reset value: 0x0000 0000 The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw HAINTM rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 HAINTM: Channel interrupt mask 0: Masked interrupt 1: Unmasked interrupt One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 57.14.25 OTG Host port control and status register (OTG_HPRT) Address offset: 0x440 Reset value: 0x0000 0000 DocID029587 Rev 3 2565/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure 745. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POCA PEN CHNG PENA r rc_w1 rc_w1 PTCTL rw rw PPWR rw rw PLSTS r Res. r PRST PSUSP PRES POC CHNG rw rs rw rc_w1 18 17 PSPD 16 PTCTL PCDET PCSTS rc_w1 r Bits 31:19 Reserved, must be kept at reset value. Bits 18:17 PSPD: Port speed Indicates the speed of the device attached to this port. 01: Full speed 10: Low speed 11: Reserved 00: High speed Bits 16:13 PTCTL: Port test control The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. 0000: Test mode disabled 0001: Test_J mode 0010: Test_K mode 0011: Test_SE0_NAK mode 0100: Test_Packet mode 0101: Test_Force_Enable Others: Reserved Bit 12 PPWR: Port power The application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. 0: Power off 1: Power on Bits 11:10 PLSTS: Port line status Indicates the current logic level USB data lines Bit 10: Logic level of OTG_DP Bit 11: Logic level of OTG_DM Bit 9 Reserved, must be kept at reset value. 2566/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 8 PRST: Port reset When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. 0: Port not in reset 1: Port in reset The application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the USB standard. High speed: 50 ms Full speed/Low speed: 10 ms Bit 7 PSUSP: Port suspend The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is set. To stop the PHY clock, the application must set the Port clock stop bit, which asserts the suspend input pin of the PHY. The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the Port reset bit or Port resume bit in this register or the Resume/remote wakeup detected interrupt bit or Disconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in OTG_GINTSTS, respectively). 0: Port not in Suspend mode 1: Port in Suspend mode Bit 6 PRES: Port resume The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port resume/remote wakeup detected interrupt bit of the Core interrupt register (WKUINT bit in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently driving resume signaling. 0: No resume driven 1: Resume driven When LPM is enabled and the core is in L1 state, the behavior of this bit is as follow: 1. The application sets this bit to drive resume signaling on the port. 2. The core continues to drive the resume signal until a predetermined time specified in BESLTHRS[3:0] field of OTG_GLPMCFG register. 3. If the core detects a USB remote wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected Interrupt bit of the core Interrupt register (WKUPINT in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit at the end of resume.This bit can be set or cleared by both the core and the application. This bit is cleared by the core even if there is no device connected to the host. Bit 5 POCCHNG: Port overcurrent change The core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register changes. Bit 4 POCA: Port overcurrent active Indicates the overcurrent condition of the port. 0: No overcurrent condition 1: Overcurrent condition Bit 3 PENCHNG: Port enable/disable change The core sets this bit when the status of the Port enable bit 2 in this register changes. DocID029587 Rev 3 2567/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 2 PENA: Port enable A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port. This bit does not trigger any interrupt to the application. 0: Port disabled 1: Port enabled Bit 1 PCDET: Port connect detected The core sets this bit when a device connection is detected to trigger an interrupt to the application using the host port interrupt bit in the Core interrupt register (HPRTINT bit in OTG_GINTSTS). The application must write a 1 to this bit to clear the interrupt. Bit 0 PCSTS: Port connect status 0: No device is attached to the port 1: A device is attached to the port 57.14.26 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..15, where x = Channel_number) Address offset: 0x500 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 CHENA CHDIS 29 28 27 26 ODD FRM 25 24 23 22 21 DAD 20 19 MCNT 18 EPTYP 17 16 LSDEV Res. rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw EPDIR rw EPNUM rw rw rw MPSIZ rw rw rw rw rw rw rw Bit 31 CHENA: Channel enable This field is set by the application and cleared by the OTG host. 0: Channel disabled 1: Channel enabled Bit 30 CHDIS: Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. Bit 29 ODDFRM: Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 0: Even frame 1: Odd frame Bits 28:22 DAD: Device address This field selects the specific device serving as the data source or sink. 2568/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bits 21:20 MCNT: Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used 00: Reserved. This field yields undefined results 01: 1 transaction 10: 2 transactions per frame to be issued for this endpoint 11: 3 transactions per frame to be issued for this endpoint Note: This field must be set to at least 01. Bits 19:18 EPTYP: Endpoint type Indicates the transfer type selected. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Bit 17 LSDEV: Low-speed device This field is set by the application to indicate that this channel is communicating to a lowspeed device. Bit 16 Reserved, must be kept at reset value. Bit 15 EPDIR: Endpoint direction Indicates whether the transaction is IN or OUT. 0: OUT 1: IN Bits 14:11 EPNUM: Endpoint number Indicates the endpoint number on the device serving as the data source or sink. Bits 10:0 MPSIZ: Maximum packet size Indicates the maximum packet size of the associated endpoint. 57.14.27 OTG Host channel-x split control register (OTG_HCSPLTx) (x = 0..15, where x = Channel_number) Address offset: 0x504 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 SPLIT EN 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP LSPLT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw 15 XACTPOS rw rw HUBADDR rw rw rw rw PRTADDR rw rw rw rw DocID029587 Rev 3 rw rw rw 2569/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 31 SPLITEN: Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. Bits 30:17 Reserved, must be kept at reset value. Bit 16 COMPLSPLT: Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. Bits 15:14 XACTPOS: Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 11: All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 01: End. This is the last payload of this transaction (which is larger than 188 bytes) Bits 13:7 HUBADDR: Hub address This field holds the device address of the transaction translator’s hub. Bits 6:0 PRTADDR: Port address This field is the port number of the recipient transaction translator. 57.14.28 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..15, where x = Channel_number) Address offset: 0x508 + (Channel_number × 0x20) Reset value: 0x0000 0000 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure 745. The application must read this register when the host channels interrupt bit in the Core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTERR FRM OR CHH XFRC rc_w1 rc_w1 rc_w1 rc_w1 Res. Res. Res. Res. Res. BBERR TXERR rc_w1 rc_w1 NYET ACK NAK STALL AHBE RR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:11 Reserved, must be kept at reset value. Bit 10 DTERR: Data toggle error. Bit 9 FRMOR: Frame overrun. Bit 8 BBERR: Babble error. 2570/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 7 TXERR: Transaction error. Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP Bit 6 NYET: Not yet ready response received interrupt. Bit 5 ACK: ACK response received/transmitted interrupt. Bit 4 NAK: NAK response received interrupt. Bit 3 STALL: STALL response received interrupt. Bit 2 AHBERR: AHB error This error is generated only in Internal DMA mode when an AHB error occurs during an AHB read/write operation. The application can read the corresponding DMA channel address register to get the error address. Bit 1 CHH: Channel halted. Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. – Bit 0 XFRC: Transfer completed. Transfer completed normally without any errors. 57.14.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..15, where x = Channel_number) Address offset: 0x50C + (Channel_number × 0x20) Reset value: 0x0000 0000 This register reflects the mask for each channel status described in the previous section. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DTERR M FRM ORM AHBE RRM CHHM XFRC M rw rw rw rw rw Res. Res. Res. Res. BBERR TXERR M M rw rw NYET ACKM NAKM STALL M rw rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 DTERRM: Data toggle error mask. 0: Masked interrupt 1: Unmasked interrupt Bit 9 FRMORM: Frame overrun mask. 0: Masked interrupt 1: Unmasked interrupt Bit 8 BBERRM: Babble error mask. 0: Masked interrupt 1: Unmasked interrupt DocID029587 Rev 3 2571/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 7 TXERRM: Transaction error mask. 0: Masked interrupt 1: Unmasked interrupt Bit 6 NYET: response received interrupt mask0: Masked interrupt 1: Unmasked interrupt Bit 5 ACKM: ACK response received/transmitted interrupt mask. 0: Masked interrupt 1: Unmasked interrupt Bit 4 NAKM: NAK response received interrupt mask. 0: Masked interrupt 1: Unmasked interrupt Bit 3 STALLM: STALL response received interrupt mask. 0: Masked interrupt 1: Unmasked interrupt Bit 2 AHBERRM: AHB error0: Masked interrupt 1: Unmasked interrupt Bit 1 CHHM: Channel halted mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed mask 0: Masked interrupt 1: Unmasked interrupt 57.14.30 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..15, where x = Channel_number) Address offset: 0x510 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 Res. 15 29 28 27 26 25 DPID 24 23 22 21 20 19 18 PKTCNT 17 16 XFRSIZ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw XFRSIZ rw rw 2572/3178 rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 31 Reserved, must be kept at reset value. Bits 30:29 DPID: Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 00: DATA0 01: DATA2 10: DATA1 11: SETUP (control) / MDATA (non-control) Bits 28:19 PKTCNT: Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. Bits 18:0 XFRSIZ: Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). DocID029587 Rev 3 2573/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 57.14.31 OTG Host channel-x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel_number) Address offset: 0x514 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAADDR rw rw rw rw rw rw rw rw rw Bits 31:0 DMAADDR: DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 57.14.32 Device-mode registers These registers must be programmed every time the core changes to device mode 57.14.33 OTG device configuration register (OTG_DCFG) Address offset: 0x800 Reset value: 0x0220 0000 This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 ERRAT IM XCVR DLY Res. rw rw 2574/3178 25 24 PERSCHIVL rw rw 9 8 PFIVL rw 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 Res. NZLSO HSK DAD rw rw rw rw rw rw DocID029587 Rev 3 rw rw rw DSPD rw rw RM0433 USB on-the-go high-speed (OTG_HS) Bits 31:26 Reserved, must be kept at reset value. Bits 25:24 PERSCHIVL: Periodic schedule interval This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data. Based on the number of periodic endpoints, this value must be specified as 25, 50 or 75% of the (micro) frame. – When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data – When no periodic endpoint is active, then the internal DMA engine services nonperiodic endpoints, ignoring this field – After the specified time within a (micro) frame, the DMA switches to fetching nonperiodic endpoints 00: 25% of (micro)frame 01: 50% of (micro)frame 10: 75% of (micro)frame 11: Reserved Bits 23:16 Reserved, must be kept at reset value. Bit 15 ERRATIM: Erratic error interrupt mask 1: Mask early suspend interrupt on erratic error 0: Early suspend interrupt is generated on erratic error Bit 14 XCVRDLY: Transceiver delay Enables or disables delay in ULPI timing during device chirp. 0: Disable delay (use default timing) 1: Enable delay to default timing, necessary for some ULPI PHYs Bit 13 Reserved, must be kept at reset value. Bits 12:11 PFIVL: Periodic frame interval Indicates the time within a frame at which the application must be notified using the end of periodic frame interrupt. This can be used to determine if all the isochronous traffic for that frame is complete. 00: 80% of the frame interval 01: 85% of the frame interval 10: 90% of the frame interval 11: 95% of the frame interval Bits 10:4 DAD: Device address The application must program this field after every SetAddress control command. DocID029587 Rev 3 2575/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 3 Reserved, must be kept at reset value. Bit 2 NZLSOHSK: Non-zero-length status OUT handshake The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer’s Status stage. 1:Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. 0:Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device endpoint control register. Bits 1:0 DSPD: Device speed Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected. 00: High speed 01: Full speed using HS 10: Reserved 11: Full speed using internal FS PHY 57.14.34 OTG device control register (OTG_DCTL) Address offset: 0x804 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DS BESL RJCT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. PO PRG DNE CGO NAK SGO NAK CGI NAK SGI NAK GON STS GIN STS SDIS RWU SIG rw w w w w r r rw rw rw TCTL rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 DSBESLRJCT: Deep sleep BESL reject Core rejects LPM request with BESL value greater than BESL threshold programmed. NYET response is sent for LPM tokens with BESL value greater than BESL threshold. By default, the deep sleep BESL reject feature is disabled. Bits 17:12 Reserved, must be kept at reset value. Bit 11 POPRGDNE: Power-on programming done The application uses this bit to indicate that register programming is completed after a wakeup from power down mode. Bit 10 CGONAK: Clear global OUT NAK A write to this field clears the Global OUT NAK. 2576/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 9 SGONAK: Set global OUT NAK A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints. The application must set the this bit only after making sure that the Global OUT NAK effective bit in the Core interrupt register (GONAKEFF bit in OTG_GINTSTS) is cleared. Bit 8 CGINAK: Clear global IN NAK A write to this field clears the Global IN NAK. Bit 7 SGINAK: Set global IN NAK A write to this field sets the Global non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The application must set this bit only after making sure that the Global IN NAK effective bit in the Core interrupt register (GINAKEFF bit in OTG_GINTSTS) is cleared. Bits 6:4 TCTL: Test control 000: Test mode disabled 001: Test_J mode 010: Test_K mode 011: Test_SE0_NAK mode 100: Test_Packet mode 101: Test_Force_Enable Others: Reserved Bit 3 GONSTS: Global OUT NAK status 0:A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. 1:No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. Bit 2 GINSTS: Global IN NAK status 0:A handshake is sent out based on the data availability in the transmit FIFO. 1:A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. Bit 1 SDIS: Soft disconnect The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. 0:Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. 1:The core generates a device disconnect event to the USB host. Bit 0 RWUSIG: Remote wakeup signaling When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it. If LPM is enabled and the core is in the L1 (sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 µs (TL1DevDrvResume) after being set by the application. The application must not set this bit when bRemoteWake from the previous LPM transaction is zero (refer to REMWAKE bit in GLPMCFG register). DocID029587 Rev 3 2577/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Table 489 contains the minimum duration (according to device state) for which the Soft disconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is recommended that the application add some extra delay to the specified minimum duration. Table 489. Minimum duration for soft disconnect Operating speed Device state Minimum duration Full speed Suspended 1 ms + 2.5 µs Full speed Idle 2.5 µs Full speed Not Idle or Suspended (Performing transactions) 2.5 µs High speed Not Idle or Suspended (Performing transactions) 125 µs 57.14.35 OTG device status register (OTG_DSTS) Address offset: 0x808 Reset value: 0x0000 0010 This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register. 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 14 13 12 11 10 9 8 FNSOF r r r r 7 Res. r r r 6 Res. r Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 DEVLNSTS: Device line status Indicates the current logic level USB data lines. Bit [23]: Logic level of D+ Bit [22]: Logic level of DBits 21:8 FNSOF: Frame number of the received SOF Bits 7:4 Reserved, must be kept at reset value. 2578/3178 20 19 DEVLNSTS r 15 21 DocID029587 Rev 3 18 17 16 r FNSOF r r r r r 5 4 3 2 1 Res. Res. EERR r ENUMSPD r r 0 SUSP STS r RM0433 USB on-the-go high-speed (OTG_HS) Bit 3 EERR: Erratic error The core sets this bit to report any erratic errors. Due to erratic errors, the OTG_HS controller goes into Suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_GINTSTS register (ESUSP bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. Bits 2:1 ENUMSPD: Enumerated speed Indicates the speed at which the OTG_HS controller has come up after speed detection through a chirp sequence. 01: Reserved 10: Reserved 11: Full speed (PHY clock is running at 48 MHz) Others: reserved Bit 0 SUSPSTS: Suspend status In device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when there is no activity on the USB data lines for a period of 3 ms. The core comes out of the suspend: – When there is an activity on the USB data lines – When the application writes to the Remote wakeup signaling bit in the OTG_DCTL register (RWUSIG bit in OTG_DCTL). 57.14.36 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) Address offset: 0x810 Reset value: 0x0000 0000 This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5 4 3 2 1 0 EPDM XFRC M rw rw / 15 Res. 14 Res. 13 NAKM rw 12 Res. 11 Res. 10 Res. 9 8 BMA TXFU RM rw rw 7 6 Res. INEPN EM rw INEPN ITTXFE MM MSK rw rw TOM rw Res. Bits 31:14 Reserved, must be kept at reset value. Bit 13 NAKM: NAK interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bits 12:10 Reserved, must be kept at reset value . DocID029587 Rev 3 2579/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 9 BIM: BNA interrupt mask mask 0: Masked interrupt 1: Unmasked interrupt Bit 8 TXFURM: FIFO underrun mask 0: Masked interrupt 1: Unmasked interrupt Bit 7 Reserved, must be kept at reset value . Bit 6 INEPNEM: IN endpoint NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Bit 5 INEPNMM: IN token received with EP mismatch mask 0: Masked interrupt 1: Unmasked interrupt Bit 4 ITTXFEMSK: IN token received when Tx FIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints) 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved, must be kept at reset value. Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask 0: Masked interrupt 1: Unmasked interrupt 57.14.37 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) Address offset: 0x814 Reset value: 0x0000 0000 This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. NYET MSK Res. Res. Res. Res. BOIM TXFU RM Res. B2B STUP Res. Res. EPDM XFRC M rw rw rw rw rw 2580/3178 rw DocID029587 Rev 3 OTEPD STUPM M rw rw RM0433 USB on-the-go high-speed (OTG_HS) Bits 31:15 Reserved, must be kept at reset value . Bit 14 NYET: NYET interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bits 13:10 Reserved, must be kept at reset value . Bit 9 BOIM: BNA interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 8 TXFURM: FIFO underrun mask 0: Masked interrupt 1: Unmasked interrupt Bit 7 Reserved, must be kept at reset value . Bit 6 B2BSTUP: Back-to-back SETUP packets received mask. Applies to control OUT endpoints only. This is . 0: Masked interrupt 1: Unmasked interrupt Bit 5 Reserved, must be kept at reset value. Bit 4 OTEPDM: OUT token received when endpoint disabled mask. Applies to control OUT endpoints only. 0: Masked interrupt 1: Unmasked interrupt Bit 3 STUPM: STUPM: SETUP phase done mask. Applies to control endpoints only. 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved, must be kept at reset value. Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask 0: Masked interrupt 1: Unmasked interrupt 57.14.38 OTG device all endpoints interrupt register (OTG_DAINT) Address offset: 0x818 Reset value: 0x0000 0000 When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx). DocID029587 Rev 3 2581/3178 2669 USB on-the-go high-speed (OTG_HS) 31 30 29 28 27 26 RM0433 25 24 23 22 21 20 19 18 17 16 OEPINT r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r IEPINT r r r r r r r r Bits 31:16 OEPINT: OUT endpoint interrupt bits One bit per OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. Bits 15:0 IEPINT: IN endpoint interrupt bits One bit per IN endpoint: Bit 0 for IN endpoint 0, bit 3 for endpoint 3. 57.14.39 OTG all endpoints interrupt mask register (OTG_DAINTMSK) Address offset: 0x81C Reset value: 0x0000 0000 The OTG_DAINTMSK register works with the Device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OEPM rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw IEPM rw rw rw rw rw rw rw rw Bits 31:16 OEPM: OUT EP interrupt mask bits One per OUT endpoint: Bit 16 for OUT EP 0, bit 19 for OUT EP 3 0: Masked interrupt 1: Unmasked interrupt Bits 15:0 IEPM: IN EP interrupt mask bits One bit per IN endpoint: Bit 0 for IN EP 0, bit 3 for IN EP 3 0: Masked interrupt 1: Unmasked interrupt 57.14.40 OTG device VBUS discharge time register (OTG_DVBUSDIS) Address offset: 0x0828 2582/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Reset value: 0x0000 17D7 This register specifies the VBUS discharge time after VBUS pulsing during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw VBUSDT rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 VBUSDT: Device VBUS discharge time Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals: VBUS discharge time in PHY clocks / 1 024 Depending on your VBUS load, this value may need adjusting. 57.14.41 OTG device VBUS pulsing time register (OTG_DVBUSPULSE) Address offset: 0x082C Reset value: 0x0000 05B8 This register specifies the VBUS pulsing time during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DVBUSP rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DVBUSP: Device VBUS pulsing time. This feature is only relevant to OTG1.3. Specifies the VBUS pulsing time during SRP. This value equals: VBUS pulsing time in PHY clocks / 1 024 57.14.42 OTG Device threshold control register (OTG_DTHRCTL) Address offset: 0x0830 Reset value: 0x0000 0000 31 Res. 30 Res. 29 Res. 28 Res. 27 ARPEN rw 26 25 24 23 22 Res. 21 20 19 18 17 RXTHRLEN rw rw rw rw DocID029587 Rev 3 rw 16 RXTH REN rw rw rw rw rw 2583/3178 2669 USB on-the-go high-speed (OTG_HS) 15 14 13 12 11 Res. Res. Res. Res. Res. rw rw rw rw rw 10 RM0433 9 8 7 6 5 4 3 2 TXTHRLEN rw rw rw rw rw rw rw rw 1 0 ISOT HREN NONIS OTH REN rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bit 27 ARPEN: Arbiter parking enable This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled. Bit 26 Reserved, must be kept at reset value. Bits 25: 17 RXTHRLEN: Receive threshold length This field specifies the receive thresholding size in DWORDS. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight DWORDS. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). Bit 16 RXTHREN: Receive threshold enable When this bit is set, the core enables thresholding in the receive direction. Bits 15: 11 Reserved, must be kept at reset value. Bits 10:2 TXTHRLEN: Transmit threshold length This field specifies the transmit thresholding size in DWORDS. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight DWORDS. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). Bit 1 ISOTHREN: ISO IN endpoint threshold enable When this bit is set, the core enables thresholding for isochronous IN endpoints. Bit 0 NONISOTHREN: Nonisochronous IN endpoints threshold enable When this bit is set, the core enables thresholding for nonisochronous IN endpoints. 57.14.43 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) Address offset: 0x834 Reset value: 0x0000 0000 This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2584/3178 DocID029587 Rev 3 RM0433 15 USB on-the-go high-speed (OTG_HS) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw 18 17 16 Res. INEPTXFEM rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits These bits act as mask bits for OTG_DIEPINTx. TXFE interrupt one bit per IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 0: Masked interrupt 1: Unmasked interrupt 57.14.44 OTG device each endpoint interrupt register (OTG_DEACHINT) Address offset: 0x0838 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OEP1 INT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IEP1 INT Res. r r Bits 31:18 Reserved, must be kept at reset value. Bit 17 OEP1INT: OUT endpoint 1 interrupt bit Bits 16:2 Reserved, must be kept at reset value. Bit 1 IEP1INT: IN endpoint 1interrupt bit Bit 0 Reserved, must be kept at reset value. 57.14.45 OTG device each endpoint interrupt register mask (OTG_DEACHINTMSK) Address offset: 0x083C Reset value: 0x0000 0000 There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT. 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 17 16 Res. OEP1 INTM Res. rw DocID029587 Rev 3 2585/3178 2669 USB on-the-go high-speed (OTG_HS) 15 Res. 14 Res. 13 Res. 12 Res. 11 Res. 10 Res. RM0433 9 8 Res. Res. 7 Res. 6 Res. 5 Res. 4 Res. 3 Res. 2 1 0 Res. IEP1I NTM Res. rw Bits 31:18 Reserved, must be kept at reset value. Bit 17 OEP1INTM: OUT Endpoint 1 interrupt mask bit Bits 16:2 Reserved, must be kept at reset value. Bit 1 IEP1INTM: IN Endpoint 1 interrupt mask bit Bit 0 Reserved, must be kept at reset value. 57.14.46 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 0..8, where x = Endpoint_number) Address offset: 0x900 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 31 30 EPENA EPDIS 29 28 27 26 SODD FRM SD0 PID/ SEVN FRM SNAK CNAK 25 24 23 22 TXFNUM 21 20 STALL Res. rs rs w w w w rw rw rw rw rw/rs 15 14 13 12 11 10 9 8 7 6 5 USBA EP Res. Res. Res. Res. rw 19 18 EPTYP 17 16 NAK STS EO NUM/ DPID rw rw r r 4 3 2 1 0 rw rw rw rw rw MPSIZ rw rw rw rw rw rw Bit 31 EPENA: Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: – SETUP phase done – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is already set for this endpoint. Bit 29 SODDFRM: Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 2586/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 28 SD0PID: Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. SEVNFRM: Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, or after a SETUP is received on the endpoint. Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 TXFNUM: Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. Bit 21 STALL: STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 20 Reserved, must be kept at reset value. Bits 19:18 EPTYP: Endpoint type This is the transfer type supported by this logical endpoint. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Bit 17 NAKSTS: NAK status It indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. DocID029587 Rev 3 2587/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 16 EONUM: Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 0: Even frame 1: Odd frame DPID: Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. 0: DATA0 1: DATA1 Bit 15 USBAEP: USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. Bits 14:11 Reserved, must be kept at reset value. Bits 10:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 57.14.47 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) Address offset: 0xB00 Reset value: 0x0000 8000 This section describes the OTG_DOEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3. 31 30 EPENA EPDIS 29 28 27 Res. Res. SNAK 26 CNAK 25 24 23 22 Res. Res. Res. Res. 21 20 STALL SNPM 19 18 EPTYP 17 16 NAK STS Res. w r w w rs rw r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 USBA EP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r 2588/3178 MPSIZ r DocID029587 Rev 3 0 r RM0433 USB on-the-go high-speed (OTG_HS) Bit 31 EPENA: Endpoint enable The application sets this bit to start transmitting data on endpoint 0. The core clears this bit before setting any of the following interrupts on this endpoint: – SETUP phase done – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application cannot disable control OUT endpoint 0. Bits 29:28 Reserved, must be kept at reset value. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP is received on the endpoint. Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 Reserved, must be kept at reset value. Bit 21 STALL: STALL handshake The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 20 SNPM: Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. Bits 19:18 EPTYP: Endpoint type Hardcoded to 2’b00 for control. Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 16 Reserved, must be kept at reset value. Bit 15 USBAEP: USB active endpoint This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. Bits 14:2 Reserved, must be kept at reset value. Bits 1:0 MPSIZ: Maximum packet size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes DocID029587 Rev 3 2589/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 57.14.48 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..8, where x = Endpoint_number) Address offset for OUT endpoints: 0xB00 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 31 30 EPENA EPDIS 29 28 27 26 25 24 23 22 21 20 SD1 PID/ SODD FRM SD0 PID/ SEVN FRM SNAK CNAK Res. Res. Res. Res. STALL SNPM rw/rs rw rw 5 4 rw rs rs w w w w 15 14 13 12 11 10 USBA EP Res. Res. Res. Res. rw 9 8 7 6 19 18 17 16 NAK STS EO NUM/ DPID rw r r 3 2 1 0 rw rw rw rw EPTYP MPSIZ rw rw rw rw rw rw Bit 31 EPENA: Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: – SETUP phase done – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is already set for this endpoint. Bit 29 SD1PID: Set DATA1 PID Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. SODDFRM: Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. Bit 28 SD0PID: Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. SEVNFRM: Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a Transfer Completed interrupt, or after a SETUP is received on the endpoint. 2590/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 Reserved, must be kept at reset value. Bit 21 STALL: STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 20 SNPM: Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. Bits 19:18 EPTYP: Endpoint type This is the transfer type supported by this logical endpoint. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 16 EONUM: Even/odd frame Applies to isochronous IN and OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 0: Even frame 1: Odd frame DPID: Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. 0: DATA0 1: DATA1 DocID029587 Rev 3 2591/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 15 USBAEP: USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. Bits 14:11 Reserved, must be kept at reset value. Bits 10:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 57.14.49 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..8, where x = Endpoint_number) Address offset: 0x908 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure 745. The application must read this register when the IN endpoints interrupt bit of the Core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the Device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BNA TXFIF OUD RN TXFE INEP NE Res. ITTXFE TOC Res. EP DISD XFRC rc_w1 rc_w1 r r rc_w1 rc_w1 rc_w1 rc_w1 Res. Res. NAK BERR PKTD RPSTS rc_w1 rc_w1 rc_w1 Res. Bits 31:14 Reserved, must be kept at reset value Bit 13 NAK: NAK input for USB OTG HS The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the Tx FIFO. Bit 12 BERR: Babble error interrupt Bit 11 PKTDRPSTS: Packet dropped status This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. Bit 10 Reserved, must be kept at reset value . Bit 9 BNA: Buffer not available interrupt The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as host busy or DMA done. 2592/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Bit 8 TXFIFOUDRN: Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. Dependency: This interrupt is valid only when Thresholding is enabled Bit 7 TXFE: Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). Bit 6 INEPNE: IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. Bit 5 Reserved, must be kept at reset value. Bit 4 ITTXFE: IN token received when Tx FIFO is empty Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated Tx FIFO (periodic/nonperiodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. Bit 3 TOC: Timeout condition Applies only to Control IN endpoints. Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. Bit 2 Reserved, must be kept at reset value. Bit 1 EPDISD: Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the application’s request. Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 57.14.50 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..8, where x = Endpoint_number) Address offset: 0xB08 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure 745. The application must read this register when the OUT Endpoints Interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. DocID029587 Rev 3 2593/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. B2B STUP STSPH SRX OTEP DIS STUP Res. EP DISD XFRC rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 STPK TRX Res. Res. Res. Res. Res. Res. Res. rc_w1 Bits 31:16 Reserved, must be kept at reset value. Bit 15 STPKTRX: Setup packet received. Applicable for Control OUT Endpoints in only in the Buffer DMA Mode. Set by the OTG_HS, this bit indicates that this buffer holds 8 bytes of setup data. There is only one Setup packet per buffer. On receiving a Setup packet, the OTG_HS closes the buffer and disables the corresponding endpoint after SETUP_COMPLETE status is seen in the Rx FIFO. OTG_HS puts a SETUP_COMPLETE status into the Rx FIFO when it sees the first IN or OUT token after the SETUP packet for that particular endpoint. The application must then re-enable the endpoint to receive any OUT data for the Control Transfer and reprogram the buffer start address. Because of the above behavior, OTG_HS can receive any number of back to back setup packets and one buffer for every setup packet is used. Bits 14:7 Reserved, must be kept at reset value. Bit 6 B2BSTUP: Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. Bit 5 STSPHSRX: Status Phase Received For Control Write (StsPhseRcvd). This interrupt is valid only for Control OUT endpoints. This interrupt is generated only after OTG_HS/ has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a Control Write transfer. The application can use this interrupt to ACK or STALL the Status phase, after it has decoded the data phase. Bit 4 OTEPDIS: OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. Bit 3 STUP: SETUP phase done Applies to control OUT endpoint only. Indicates that the SETUP phase for the control endpoint is complete and no more back-toback SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. Bit 2 Reserved, must be kept at reset value. Bit 1 EPDISD: Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the application’s request. Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 2594/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.51 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) Address offset: 0x910 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (EPENA in OTG_DIEPCTL0), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. Nonzero endpoints use the registers for endpoints 1–3. 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 6 5 20 19 PKTCNT rw rw 4 3 18 17 16 Res. Res. Res. 2 1 0 rw rw rw XFRSIZ rw rw rw rw Bits 31:21 Reserved, must be kept at reset value. Bits 20:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. Bits 18:7 Reserved, must be kept at reset value. Bits 6:0 XFRSIZ: Transfer size Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 57.14.52 OTG Device channel-x DMA address register (OTG_DIEPDMAx) (x = 0..15, where x= Channel_number) Address offset: 0x914 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAADDR rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 2595/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bits 31:0 DMAADDR: DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 57.14.53 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) Address offset: 0xB10 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the Endpoint enable bit in the OTG_DOEPCTL0 registers (EPENA bit in OTG_DOEPCTL0), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. 31 Res. 30 29 STUPCNT 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. PKTCNT Nonzero endpoints use the registers for endpoints 1–8. Res. Res. Res. 6 5 4 2 1 0 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 rw Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 XFRSIZ rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bits 30:29 STUPCNT: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bits 28:20 Reserved, must be kept at reset value. Bit 19 PKTCNT: Packet count This field is decremented to zero after a packet is written into the Rx FIFO. Bits 18:7 Reserved, must be kept at reset value. Bits 6:0 XFRSIZ: Transfer size Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 2596/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.54 OTG Device channel-x DMA address register (OTG_DOEPDMAx) (x = 0..15, where x= Channel_number) Address offset: 0xB14 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAADDR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAADDR rw rw rw rw rw rw rw rw rw Bits 31:0 DMAADDR: DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched. This register is incremented on every AHB transaction. 57.14.55 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..8, where x= Endpoint_number) Address offset: 0x910 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the Endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. 31 30 Res. 15 29 28 27 26 25 MCNT 24 23 22 21 20 19 18 PKTCNT 17 16 XFRSIZ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw XFRSIZ rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 2597/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Bit 31 Reserved, must be kept at reset value. Bits 30:29 MCNT: Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 01: 1 packet 10: 2 packets 11: 3 packets Bits 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. Bits 18:0 XFRSIZ: Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 57.14.56 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..8, where x = Endpoint_number) Address offset for IN endpoints: 0x918 + (Endpoint_number × 0x20) This read-only register contains the free space information for the Device IN endpoint Tx FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r INEPTFSAV r r r r r r r r r 31:16 Reserved, must be kept at reset value. 15:0 INEPTFSAV: IN endpoint Tx FIFO space available Indicates the amount of free space available in the Endpoint Tx FIFO. Values are in terms of 32-bit words: 0x0: Endpoint Tx FIFO is full 0x1: 1 word available 0x2: 2 words available 0xn: n words available Others: Reserved 2598/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 57.14.57 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..8, where x = Endpoint_number) Address offset: 0xB10 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. 31 Res. 15 30 29 28 27 26 25 RXDPID/ STUPCNT 24 23 22 21 20 19 18 PKTCNT 17 16 XFRSIZ r/rw r/rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw XFRSIZ rw rw rw rw rw rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bits 30:29 RXDPID: Received data PID Applies to isochronous OUT endpoints only. This is the data PID received in the last packet for this endpoint. 00: DATA0 01: DATA2 10: DATA1 11: MDATA STUPCNT: SETUP packet count Applies to control OUT Endpoints only. This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bits 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. Bits 18:0 XFRSIZ: Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. DocID029587 Rev 3 2599/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 57.14.58 OTG power and clock gating control register (OTG_PCGCCTL) Address offset: 0xE00 Reset value: 0x0x200B 8000 This register is available in host and device modes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SUSP PHY SLEEP ENL1 GTG PHY SUSP Res. GATE HCLK STPP CLK r r rw r rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:8 Reserved, must be kept at reset value. Bit 7 SUSP: Deep Sleep This bit indicates that the PHY is in Deep Sleep when in L1 state. Bit 6 PHYSLEEP: PHY in Sleep This bit indicates that the PHY is in the Sleep state. Bit 5 ENL1GTG: Enable Sleep clock gating When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep state. Bit 4 PHYSUSP: PHY Suspended Indicates that the PHY has been Suspended. This bit is updated once the PHY is Suspended after the application has set the STPPCLK bit. Bits 3:2 Reserved, must be kept at reset value. Bit 1 GATEHCLK: Gate HCLK The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. Bit 0 STPPCLK: Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. 57.14.59 OTG_HS register map The table below gives the USB OTG register map and reset values. 2600/3178 DocID029587 Rev 3 0x01C OTG_ GRXSTSR (Device mode) Reset value PRTIM RSTDETM FSUSPM IPXFRM/IISOOXFRM IISOIXFRM OEPINT IEPINT 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. 0 0 1 HPRTINT Res. DATAFSUSP IPXFR/INCOMPISOOUT IISOIXFR OEPINT IEPINT 1 0 0 0 0 0 0 0 0 Reset value 0 FRMNUM 0 0 0 0 0 0 0 0 PKTSTS 0 0 PKTSTS 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 DPID 0 DPID 0 0 0 0 0 OTGINT MMIS CMOD 0 0 1 0 0 0 0 0 OTGINT MMISM Res. 0 0 0 0 0 0 0 1 BCNT 0 0 0 0 0 BCNT 0 Res. Res. Res. 0 0 0 0 0 0 CSRST BVALOEN AVALOVAL AVALOEN VBVALOVAL VBVALOEN SRQ SRQSCS 0 0 0 0 Res. Res. DMAEN Res. Res. Res. Res. Res. Res. SEDET Res. Res. 0 Res. BVALOVAL 0 TXFELVL 0 0 PSRST Res. 0 0 PHYSEL HNPRQ HNGSCS 0 SRSSCHG 0 HNSSCHG DHNPEN HSHNPEN 0 Res. EHEN HBSTLEN 0 GINTMSK Res. Res. Res. 0 Res. Res. Res. Res. DBCT CIDSTS Res. 0 PTXFELVL Res. Res. Res. Res. Res. Res. Res. Res. ASVLD HNGDET Res. BSVLD DBCDNE ADTOCHG Res. 0 0 Res. 0 SOF 0 RXFLVL 0 SOFM 0 RXFLVLM 0 NPTXFE 0 NPTXFEM 0 GINAKEFF 0 GONAKEFF SRPCAP 0 GINAKEFFM Res. PHYLPC Reset value GONAKEFFM RXFFLSH TXFNUM TXFFLSH 0 HNPCAP 1 Res. 0 Res. ESUSP 0 ESUSPM 1 Res. Res. Res. 0 Res. USBSUSP 0 USBSUSPM Res. 0 TRDT Res. USBRST 0 USBRST ULPIFSL 0 ENUMDNE ULPIAR 0 Res. 1 ENUMDNEM ULPICSM 0 Res. Res. Res. OTGVER IDCHNG 0 Res. Res. Res. 0 EOPF ULPIEVBUSD 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 ISOODRP ULPIEVBUSI 0 Res. Res. Res. Res. 0 EOPFM TSDPS 0 Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_ GOTGCTL Res. Register name 0 ISOODRPM PCCI 0 Res. Res. Res. Res. 0 Res. PTCI 0 Res. Res. Res. Res. 0 Res. ULPIIPD 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. HCINT Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Reset value Res. HCIM 0 Res. 0 PTXFE Res. 1 Res. PTXFEM 0 Res. AHBIDL DMAREQ Reset value Res. FHMOD OTG_ GRSTCTL Res. 0 Res. LPMINTM 0 OTG_ GRXSTSR (host mode) Res. DISCINT Reset value CIDSCHG 0 Res. FDMOD Reset value Res. DISCINT CIDSCHGM Reset value Res. OTG_ GINTMSK Res. OTG_ GINTSTS SRQINT OTG_ GUSBCFG Res. 0x018 OTG_ GAHBCFG Res. 0x014 OTG_ GOTGINT WKUINT 0x010 WUIM 0x00C SRQIM 0x008 Res. 0x004 Res. 0x000 Res. Offset Res. RM0433 USB on-the-go high-speed (OTG_HS) Table 490. OTG_HS register map and reset values 0 0 0 TOCAL 0 0 0 0 0 0 0 0 0 CHNUM 0 0 EPNUM 0 2601/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Res. 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. 1 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 PWRDWN 1 1 BCDEN 0 0 0 0 0 0 0 ADDR REGADDR RWDATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM RCNT 0 0 0 0 0 0 0 LPMCHIDX 0 0 0 0 0 0 0 0 0 1 0 LPM RSP 0 0 0 0 0 0 0 BESLTHRS 0 0 0 0 0 PTXFSIZ 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . 0x244 OTG_ DIEPTXF7 0 0 0 0 0 1 1 0 0 0 0 1 1 0 INEPTXFD 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA . . . . 0 0 BESL INEPTXSA INEPTXFD 0 0 PTXSA INEPTXFD 0 0 0 LPMEN LPMR CNTSTS 0 LPMACK 0 L1DSEN 0 0 0 SLPSTS 0 0 . . . . 2602/3178 0 PDEN 0 . . . . Reset value 0 NPTXFSAV L1RSMOK 0 OTG_ DIEPTXF2 Reset value 0 REMWAKE 0x108 0 0 SNDLPM 0 OTG_ DIEPTXF1 Reset value 0 0 L1SSEN 0x104 0 DCDEN 0 OTG_ HPTXFSIZ Reset value 0 SDEN 0 Res. 0 Reset value 0x100 0 VBDEN Res. 0 ENBESL 0 Res. OTG_ GLPMCFG 0 Res. I2CD EVAD R 0 0 PRODUCT_ID Res. 0x054 0 I2CEN 0 0 EPNUM Res. 0 0 ACK 0 0 Res. 0 0 BCNT NPTQXSAV Res. 0 Res. 0 0 Res. 0 0 0 PDET 1 0 DCDET 0 0 NPTXFSA/TX0FSA OTG_CID Reset value 0 SDET 0 Reset value 0x03C 0 Res. 0 Res. OTG_ GCCFG RW 0x038 BSYDNE Reset value 0 Res. OTG_ GI2CCTL 0 NPTXQTOP Res. Reset value 0 I2CDATSE 0 OTG_ HNPTXSTS Res. Reset value 0x030 0 NPTXFD/TX0FD Res. 0x02C 0 Res. 0x028 0 CHNUM RXFD Reset value OTG_ HNPTXFSIZ/ OTG_ DIEPTXF0 BCNT DPID Res. PKTSTS 0 Res. Res. Res. Res. FRMNUM 0 DPID PS2DET Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x024 Res. Reset value OTG_ GRXFSIZ PKTSTS 0 Res. OTG_ GRXSTSPR (Device mode) Res. Reset value Res. 0x020 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_ GRXSTSR (host mode) Offset Res. Register name Res. Table 490. OTG_HS register map and reset values (continued) 0 0 0 INEPTXSA 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 RM0433 USB on-the-go high-speed (OTG_HS) Reset value 0 0 0 0 0 1 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 LSDEV 0 0 0 0 0 0 0 0 0 Res. EPDIR 0 0 Res. 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM 0 0 0 XAC TPOS 0 0 0 0 0 0 0 0 0 MPSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. DTERR FRMOR BBERR TXERR Res. Res. PRTADDR Res. HUBADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ HCDMA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHHM 0 XFRCM 0 STALLM 0 NAKM 0 ACKM 0 NYET 0 TXERRM 0 BBERRM 0 FRMORM 0 DTERRM 0 Res. XFRSIZ Res. PKTCNT 0 Res. Res. 1 0 0 0 0 0 0 0 0 0 ODDFRM Reset value 0 0 0 0 0 0 0 0 0 DAD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPDIR OTG_ HCCHAR1 0 Res. 0 LSDEV 0 EPTYP 0 MCNT Reset value CHDIS DMAADDR CHENA 0x520 0 0 Reset value 0x514 1 Res. OTG_ HCINTMSK0 1 Res. 0x50C Res. Reset value DPID 1 Res. 0x510 1 0 Reset value OTG_ HCTSIZ0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 COMPLSPLT 0 Res. EPTYP 0 Res. 0 Res. MCNT 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. ODDFRM 1 CHH Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DAD Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHDIS OTG_ HCINT0 1 HAINTM 0 0 Res. 0x508 SPLITEN CHENA Reset value 0 PTCTL PSPD 0 0 0 HAINT 0 Res. OTG_ HCSPLT0 0 0 0 0 PCSTS 0 0 0 PCDET 0 0 0 PTXFSAVL 0 Res. 0x504 0 PTXQSAV 0 0 0 XFRC 0 0 0 1 PENA 0 0 0 1 PENCHNG 0 0 Reset value 0 STALL 0 0 OTG_ HCCHAR0 0 POCA 0 Reset value 0x500 1 NAK 0 0 Res. OTG_ HPRT 0 POCCHNG 0 Reset value 0x440 1 ACK 0 PTXQTOP Res. 0x418 0 PRES 0 Reset value OTG_ HAINTMSK 1 PSUSP 0 0 PRST 0 0 Res. 0 Res. OTG_ HAINT 1 PLSTS 0 Res. 0x414 0 0 FRNUM Res. Reset value 1 FTREM OTG_ HPTXSTS FSLS PCS FRIVL PPWR Reset value 0x410 0 OTG_ HFNUM Res. 0x408 RLDCTRL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ HFIR Res. 0x404 Res. Reset value FSLSS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ HCFG Res. 0x400 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 490. OTG_HS register map and reset values (continued) 0 DocID029587 Rev 3 0 0 0 0 0 EPNUM 0 0 0 MPSIZ 0 0 0 0 0 0 0 0 2603/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . 0x6E0 OTG_ HCCHAR15 Reset value 0 0 0 0 0 0 0 0 0 LSDEV MCNT 0 0 0 0 0 0 2604/3178 CHH XFRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. NAK STALL TXERR ACK BBERR Res. FRMOR 0 0 0 0 0 MPSIZ 0 0 0 0 0 0 0 0 COMPLSPLT 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. DTERRM FRMORM PRTADDR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HUBADDR 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM STALLM 0 CHHM NAKM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ACKM Reset value 0 0 NYET OTG_ HCTSIZ15 0 TXERRM 0x6F0 0 0 0 0 0 . . . . Res. . . . . 0 EPNUM Reset value . . . . FRMORM Res. 0 XACT POS 0 Res. OTG_ HCINTMSK15 0 0 . . . . Res. 0x6EC Res. 0 . . . . Res. Reset value . . . . Res. OTG_ HCSPLT15 0 0 . . . . Res. 0x6E4 DAD 0 EPDIR . . . . Res. . . . . EPTYP . . . . SPLITEN . . . . 0 0 XFRCM 0 . . . . . . . . 0 CHHM 0 . . . . . . . . 0 Res. 0 0 STALLM 0 0 NAKM 0 0 0 ACKM 0 0 0 NYET 0 0 TXERRM 0 . . . . ODDFRM 0 0 XFRSIZ CHDIS 0 PKTCNT CHENA Reset value DPID 0 BBERRM 0x530 0 BBERRM OTG_ HCTSIZ1 Res. Reset value DTERR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ HCINTMSK1 Res. 0x52C Res. Reset value DTERRM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ HCINT1 0x528 Res. Register name Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 490. OTG_HS register map and reset values (continued) DPID 0 0 PKTCNT 0 0 0 0 0 0 XFRSIZ 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0x82C OTG_DVB USPULSE 0 0 0 0 0 OTG_ DVBUSDIS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. OEPM 0 Res. Reset value Reset value DocID029587 Rev 3 Reset value 0 0 0 0 0 0 0 0 0 NAKM Reset value 0 0 Res. Res. Res. Res. 1 0 0 OEPINT 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 XFRCM SDIS 0 0 0 0 0 0 0 0 0 RWUSIG 0 0 0 0 1 0 SUSPSTS DSPD 0 0 Res. XFRC 0 0 CHH 0 NZLSOHSK 0 XFRCM GINSTS NAK STALL Res. 0 ENUMSPD 0 EERR ACK 0 Res. 0 Res. TXERR Res. BBERR 0 EPDM GONSTS 0 TCTL DAD 0 FRMOR 0 DTERR 0 0 0 0 Res. EPDM 0 STUPM TOM 0 ITTXFEMSK FNSOF 0 OTEPDM 0 Res. 0 Res. 0 SGINAK Res. 0 0 INEPNMM 0 Res. Res. 0 Res. Res. 0 0 Res. 0 CGINAK PFIVL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 INEPNEM 0 0 0 B2BSTUP 0 SGONAK 0 CGONAK 0 POPRGDNE 0 Res. Res. Res. Res. XCVRDLY 0 Res. 0 Res. ERRATIM Reset value Res. 0 Res. DEV LN STS 0 Res. Res. OTG_ HCINT15 0 BOIM 0 Res. Res. Res. 0x7A8 0 TXFURM 0 Res. Res. Res. . . . . 0 Res. 0 Res. DSBESLRJCT Res. . . . . 0 Res. 0 Res. Res. Res. . . . . Res. 0 Res. Res. Res. Res. Res. . . . . Res. 0 Res. 0 Res. Res. Res. . . . . NYETMSK 0 Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. . . . . Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Reset value 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. Reset value 0 0 Res. 0 0 Res. 0 Res. Res. Reset value Res. OTG_ DAINTMSK Res. Res. Res. Res. Res. Res. Res. Res. PERS CHI VL Res. OTG_ DAINT 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. OTG_ DOEPMSK 0 Res. 0x828 0 Res. Reset value Res. 0x81C OTG_ DIEPMSK 0 Res. 0x818 OTG_ DSTS 0 Res. 0x814 OTG_ DCTL Res. 0x810 OTG_ DCFG Res. 0x808 Res. 0x804 Res. 0x800 0 Res. Reset value Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0433 USB on-the-go high-speed (OTG_HS) Table 490. OTG_HS register map and reset values (continued) . . . . . . . . . . . . 0x6F4 OTG_ HCDMA15 DMAADDR 0 0 0 0 0 0 0 IEPINT IEPM VBUSDT DVBUSP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 0 0 2605/3178 2669 0x930 2606/3178 SNAK CNAK Reset value 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. 0x928 OTG_ DIEPCTL1 SD0PID/SEVNFRM 0x920 SODDFRM/SD1PID OTG_ DIEPINT1 OTG_ DIEPTSIZ1 Reset value 0 0 0 0 0 MCNT 0 0 0 TXFNUM 0 0 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 PKTCNT 0 0 0 0 1 0 0 0 Reset value 0 0 0 Res. Res. Res. 0 0 0 0 0 0 0 0 0 Res. TXFE INEPNE Res. 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ 1 0 0 0 ITTXFE 0 TOC Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARPEN Res. Res. Res. Res. Res. Res. RXTHREN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. ISOTHREN 0 NONISOTHREN 0 Res. 0 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. INEPTXFEM 0 IEP1INT 0 IEP1INTM 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 1 0 0 0 XFRC 0 Res. Res. Res. Res. 0 Res. Res. OEP1INT 0 EPDISD 0 Res. Res. Res. Res. Res. Res. Res. OEP1INTM Res. Res. Res. Res. Res. Res. Res. Res. 0 XFRC 0 Res. USBAEP Res. Res. EONUM/DPID Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. OTG_ DTHRCTL TXTHRLEN EPDISD 0 Res. 0 Res. Res. Reset value 0 TOC 0 0 0 ITTXFE 0 Res. 0 0 INEPNE 0 0 TXFE 0 Res. 0 Res. Reset value 0 Res. 0 Res. 0 Res. NAKSTS Res. EPTYP Res. Res. STALL 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. OTG_ DIEPDMA Res. Res. 0 Res. 0 0 Res. Res. Res. Res. Res. Reset value Res. Res. Reset value Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Reset value Res. Res. Res. Res. Register name RXTHRLEN Res. 0 Res. Reset value PKT CNT Res. 0 USBAEP 0 Res. 0 Res. 0 Res. 0 Res. 0 EONUM/DPID 0 Res. Res. 0 Res. 0 Res. Res. 0 NAKSTS 0 Res. Res. Res. CNAK 0 Res. 0 Res. SNAK 0 EPTYP 0 Res. Res. Res. SD0PID/SEVNFRM 0 Res. 0 Res. SODDFRM/SD1PID 0 Res. 0 Res. Res. Res. 0 TXFNUM Res. 0 Res. OTG_ DIEPTSIZ0 Res. EPDIS OTG_DEACHI NTMSK Res. 0 OTG_ DTXFSTS0 Res. EPENA Reset value Res. Reset value STALL Reset value Res. 0x918 Res. 0x914 Res. 0x910 OTG_ DIEPINT0 OTG_ DIEPCTL0 Res. OTG_ DEACHINT Res. OTG_DIE PEMPMSK Res. 0x908 Res. 0x900 Res. 0x83C EPDIS 0x838 EPENA 0x834 Res. 0x830 Res. Offset Res. USB on-the-go high-speed (OTG_HS) RM0433 Table 490. OTG_HS register map and reset values (continued) 0 0 MPSIZ 0 0 XFRSIZ DMAADDR INEPTFSAV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ 0 0 0 0 RM0433 USB on-the-go high-speed (OTG_HS) Res. 0x9E0 OTG_ DIEPCTL7 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC 0 0 EPDISD 0 TOC 1 ITTXFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. . . . . Res. OTG_ DTXFSTS7 0 Res. 0x9F8 0 Res. . . . . 0 INEPNE Reset value . . . . PKTCNT MCNT Res. OTG_ DIEPTSIZ7 Res. 0x9F0 0 . . . . Res. . . . . 0 MPSIZ Reset value . . . . 0 TXFE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ DIEPINT7 0 Res. 0x9E8 0 EPTY P 0 . . . . Res. . . . . Res. . . . . TXFNUM USBAEP . . . . EONUM/DPID . . . . NAKSTS . . . . Res. . . . . STALL . . . . CNAK . . . . SNAK . . . . SODDFRM . . . . SD0PID/SEVNFRM . . . . 0 Res. Res. 0 . . . . 0 Res. Res. 0 Res. 0 0 Res. 0 0 MPSIZ Res. 0 1 Res. 0 . . . . 0 Res. 0 . . . . Res. 0 0 Res. 0 0 Res. 0 EONUM/DPID 0 NAKSTS 0 EPTYP CNAK 0 Res. SNAK 0 STALL SODDFRM 0 SD0PID/SEVNFRM EPDIS 0 0 EPDIS Reset value TXFNUM 0 EPENA OTG_ DIEPCTL2 EPENA Reset value 0x940 0 Res. INEPTFSAV USBAEP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ DTXFSTS1 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x938 Register name Res. Offset Res. Table 490. OTG_HS register map and reset values (continued) Reset value INEPTFSAV 0 DocID029587 Rev 3 0 0 0 0 0 1 0 0 0 2607/3178 2669 2608/3178 0 0 0 0 0 . . . . . . . . . . . . . . . . 0xBE0 OTG_ DOEPCTL7 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 SNPM NAKSTS EONUM/DPID USBAEP 0 0 0 0 0 Res. Res. 0 0 0 0 0 0 Res. 0 Res. Res. 0 0 0 0 0 Res. 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 PKTCNT 0 PKTCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 Reset value XFRSIZ XFRSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ 0 0 0 0 XFRC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTEPDIS STUP 0 0 0 0 XFRC 1 EPDISD Res. STSPHSRX Res. Res. Res. Res. Res. Res. Res. Res. Res. B2BSTUP Reset value EPDISD 0 STUP Res. 0 OTEPDIS Res. 0 STSPHSRX 0 B2BSTUP 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. SNPM Res. MPSIZ Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USBAEP Res. NAKSTS EPTYP STALL Res. Res. Res. Res. Res. Res. Res. Res. CNAK Res. Res. Res. SNAK Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. OTG_ DOEPINT0 Res. 0 Res. EPDIS 0 0 Res. Res. Res. PKTCNT Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPENA Reset value 0 Res. STALL Res. Res. 0 Res. Res. Res. Res. 0 EP TYP Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 USBAEP 0 0 NAKSTS 0 Res. 0 Res. OTG_ DOEPDMA EONUM/DPID 0 0 EPTYP Res. 0 SNPM Res. 0 0 STALL Res. CNAK Res. 0 0 Res. Reset value 0 0 Res. Reset value STUP CNT Res. OTG_ DOEPTSIZ2 Res. OTG_ DOEPCTL0 0 Res. OTG_ DOEPINT1 0 SNAK 0 0 SODDFRM Reset value 0 SD0PID/SEVNFRM OTG_ DOEPCTL1 0 EPDIS Register name 0 Res. OTG_ DOEPTSIZ1 0 CNAK 0xB50 0 EPENA Reset value SNAK 0xB30 0 Res. 0xB28 Reset value Res. 0xB14 Res. 0xB20 OTG_ DOEPTSIZ0 RXDPID/ STUPCNT 0xB10 Res. 0xB08 RXDPID/ STUPCNT 0xB00 SODDFRM . . . . EPDIS Offset SD0PID/SEVNFRM . . . . EPENA USB on-the-go high-speed (OTG_HS) RM0433 Table 490. OTG_HS register map and reset values (continued) 0 0 0 0 XFRSIZ DMAADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 USB on-the-go high-speed (OTG_HS) XFRC STUP 0 Res. OTEPDIS 0 EPDISD STSPHSRX Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUSP PHYSLEEP ENL1GTG PHYSUSP Res. Res. GATEHCLK STPPCLK XFRSIZ Res. PKTCNT Res. OTG_ PCGCCTL Res. Reset value 0xE00 0 Res. Res. OTG_ DOEPTSIZ7 RXDPID/ STUPCNT 0xBF0 0 . . . . Res. . . . . B2BSTUP Reset value . . . . Res. Res. STPKTRX Res. Res. Res. OTG_ DOEPINT7 Res. 0xBE8 Res. . . . . Res. . . . . Res. . . . . Res. . . . . Res. . . . . Res. . . . . Res. . . . . Res. . . . . Res. . . . . Res. Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 490. OTG_HS register map and reset values (continued) 0 0 0 0 0 0 Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID029587 Rev 3 2609/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 57.15 OTG_HS programming model 57.15.1 Core initialization The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the OTG_GINTSTS (CMOD bit in OTG_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when an “A” plug is connected or device mode when a “B” plug is connected. This section explains the initialization of the OTG_HS controller after power-on. The application must follow the initialization sequence irrespective of host or device mode operation. All core global registers are initialized according to the core’s configuration: 1. 2. 3. Program the following fields in the OTG_GAHBCFG register: – Global interrupt mask bit GINTMSK = 1 – Rx FIFO non-empty (RXFLVL bit in OTG_GINTSTS) – Periodic Tx FIFO empty level Program the following fields in the OTG_GUSBCFG register: – HNP capable bit – SRP capable bit – OTG_HS timeout calibration field – USB turnaround time field The software must unmask the following bits in the OTG_GINTMSK register: OTG interrupt mask Mode mismatch interrupt mask 4. 2610/3178 The software can read the CMOD bit in OTG_GINTSTS to determine whether the OTG_HS controller is operating in host or device mode. DocID029587 Rev 3 RM0433 57.15.2 USB on-the-go high-speed (OTG_HS) Host initialization To initialize the core as host, the application must perform the following steps: 1. Program the HPRTINT in the OTG_GINTMSK register to unmask 2. Program the OTG_HCFG register to select full-speed host 3. Program the PPWR bit in OTG_HPRT to 1. This drives VBUS on the USB. 4. Wait for the PCDET interrupt in OTG_HPRT0. This indicates that a device is connecting to the port. 5. Program the PRST bit in OTG_HPRT to 1. This starts the reset process. 6. Wait at least 10 ms for the reset process to complete. 7. Program the PRST bit in OTG_HPRT to 0. 8. Wait for the PENCHNG interrupt in OTG_HPRT. 9. Read the PSPD bit in OTG_HPRT to get the enumerated speed. 10. Program the HFIR register with a value corresponding to the selected PHY clock 1 11. Program the FSLSPCS field in the OTG_HCFG register following the speed of the device detected in step 9. If FSLSPCS has been changed a port reset must be performed. 12. Program the OTG_GRXFSIZ register to select the size of the receive FIFO. 13. Program the OTG_HNPTXFSIZ register to select the size and the start address of the Non-periodic transmit FIFO for non-periodic transactions. 14. Program the OTG_HPTXFSIZ register to select the size and start address of the periodic transmit FIFO for periodic transactions. To communicate with devices, the system software must initialize and enable at least one channel. 57.15.3 Device initialization The application must perform the following steps to initialize the core as a device on powerup or after a mode change from host to device. 1. 2. 3. Program the following fields in the OTG_DCFG register: – Device speed – Non-zero-length status OUT handshake Program the OTG_GINTMSK register to unmask the following interrupts: – USB reset – Enumeration done – Early suspend – USB suspend – SOF Wait for the USBRST interrupt in OTG_GINTSTS. It indicates that a reset has been detected on the USB that lasts for about 10 ms on receiving this interrupt. Wait for the ENUMDNE interrupt in OTG_GINTSTS. This interrupt indicates the end of reset on the USB. On receiving this interrupt, the application must read the OTG_DSTS register to determine the enumeration speed and perform the steps listed in Endpoint initialization on enumeration completion on page 2644. DocID029587 Rev 3 2611/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0. 57.15.4 DMA mode The OTG host uses the AHB master interface to fetch the transmit packet data (AHB to USB) and receive the data update (USB to AHB). The AHB master uses the programmed DMA address (OTG_HCDMAx register in host mode and OTG_DIEPDMAx/OTG_DOEPDMAx register in peripheral mode) to access the data buffers. Scatter/Gather DMA mode TBC. 57.15.5 Host programming model Channel initialization The application must initialize one or more channels before it can communicate with connected devices. To initialize and enable a channel, the application must perform the following steps: 1. 2. Program the OTG_GINTMSK register to unmask the following: Channel interrupt – Non-periodic transmit FIFO empty for OUT transactions (applicable when operating in pipelined transaction-level with the packet count field programmed with more than one). – Non-periodic transmit FIFO half-empty for OUT transactions (applicable when operating in pipelined transaction-level with the packet count field programmed with more than one). 3. Program the OTG_HAINTMSK register to unmask the selected channels’ interrupts. 4. Program the OTG_HCINTMSK register to unmask the transaction-related interrupts of interest given in the host channel interrupt register. 5. Program the selected channel’s OTG_HCTSIZx register with the total transfer size, in bytes, and the expected number of packets, including short packets. The application must program the PID field with the initial data PID (to be used on the first OUT transaction or to be expected from the first IN transaction). 6. Program the OTG_HCCHARx register of the selected channel with the device’s endpoint characteristics, such as type, speed, direction, and so forth. (The channel can be enabled by setting the channel enable bit to 1 only when the application is ready to transmit or receive any packet). 7. Program the selected channels in the OTG_HCSPLTx register(s) with the hub and port addresses (split transactions only). 8. Program the selected channels in the OTG_HCDMAx register(s) with the buffer start address (DMA transactions only). Halting a channel The application can disable any channel by programming the OTG_HCCHARx register with the CHDIS and CHENA bits set to 1. This enables the OTG_HS host to flush the posted requests (if any) and generates a channel halted interrupt. The application must wait for the 2612/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) CHH interrupt in OTG_HCINTx before reallocating the channel for other transactions. The OTG_HS host does not interrupt the transaction that has already been started on the USB. To disable a channel in DMA mode operation, the application does not need to check for space in the request queue. The OTG_HS host checks for space to write the disable request on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are dropped from the request queue when the CHDIS bit in OTG_HCCHARx is set to 1. Before disabling a channel, the application must ensure that there is at least one free space available in the non-periodic request queue (when disabling a non-periodic channel) or the periodic request queue (when disabling a periodic channel). The application can simply flush the posted requests when the Request queue is full (before disabling the channel), by programming the OTG_HCCHARx register with the CHDIS bit set to 1, and the CHENA bit cleared to 0. The application is expected to disable a channel on any of the following conditions: 1. When an STALL, TXERR, BBERR or DTERR interrupt in OTG_HCINTx is received for an IN or OUT channel. The application must be able to receive other interrupts (DTERR, Nak, Data, TXERR) for the same channel before receiving the halt. 2. When an XFRC interrupt in OTG_HCINTx is received during a non periodic IN transfer or high-bandwidth interrupt IN transfer 3. When a DISCINT (Disconnect Device) interrupt in OTG_GINTSTS is received. (The application is expected to disable all enabled channels). 4. When the application aborts a transfer before normal completion. Ping protocol When the OTG_HS host operates in high speed, the application must initiate the ping protocol when communicating with high-speed bulk or control (data and status stage) OUT endpoints.The application must initiate the ping protocol when it receives a NAK/NYET/TXERR interrupt. When the OTG_HS host receives one of the above responses, it does not continue any transaction for a specific endpoint, drops all posted or fetched OUT requests (from the request queue), and flushes the corresponding data (from the transmit FIFO).This is valid in slave mode only. In Slave mode, the application can send a ping token either by setting the DOPING bit in OTG_HCTSIZx before enabling the channel or by just writing the OTG_HCTSIZx register with the DOPING bit set when the channel is already enabled. This enables the OTG_HS host to write a ping request entry to the request queue. The application must wait for the response to the ping token (a NAK, ACK, or TXERR interrupt) before continuing the transaction or sending another ping token. The application can continue the data transaction only after receiving an ACK from the OUT endpoint for the requested ping. In DMA mode operation, the application does not need to set the DOPING bit in OTG_HCTSIZx for a NAK/NYET response in case of Bulk/Control OUT. The OTG_HS host automatically sets the DOPING bit in OTG_HCTSIZx, and issues the ping tokens for Bulk/Control OUT. The OTG_HS host continues sending ping tokens until it receives an ACK, and then switches automatically to the data transaction. DocID029587 Rev 3 2613/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Operational model The application must initialize a channel before communicating to the connected device. This section explains the sequence of operation to be performed for different types of USB transactions. • Writing the transmit FIFO The OTG_HS host automatically writes an entry (OUT request) to the periodic/nonperiodic request queue, along with the last DWORD write of a packet. The application must ensure that at least one free space is available in the periodic/non-periodic request queue before starting to write to the transmit FIFO. The application must always write to the transmit FIFO in DWORDs. If the packet size is non-DWORD aligned, the application must use padding. The OTG_HS host determines the actual packet size based on the programmed maximum packet size and transfer size. Figure 746. Transmit FIFO write task ^ƚĂƌƚ 5HDG27*B+37;67627*B+137;676 UHJLVWHUVIRUDYDLODEOH),)2DQGTXHXH VSDFHV :DLWIRU137;)(37;)(LQWHUUXSWLQ 27*B*,17676 1R ϭDW^ Žƌ>W^&/&KƐƉĂĐĞ ĂǀĂŝůĂďůĞ͍ ZRUGBFQWB@ UGBU[ILIR UGBGDWD(3180 ZRUGBFQW ZRUGBFQW %&17> @ %&17>@_%&17>@ DLE SETUP transactions This section describes how the core handles SETUP packets and the application’s sequence for handling SETUP transactions. • Application requirements 1. To receive a SETUP packet, the STUPCNT field (OTG_DOEPTSIZx) in a control OUT endpoint must be programmed to a non-zero value. When the application programs the STUPCNT field to a non-zero value, the core receives SETUP packets and writes them to the receive FIFO, irrespective of the NAK status and EPENA bit setting in OTG_DOEPCTLx. The STUPCNT field is decremented every time the control endpoint receives a SETUP packet. If the STUPCNT field is not programmed to a proper value before receiving a SETUP packet, the core still receives the SETUP packet and DocID029587 Rev 3 2647/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 decrements the STUPCNT field, but the application may not be able to determine the correct number of SETUP packets received in the Setup stage of a control transfer. – 2. The application must always allocate some extra space in the Receive data FIFO, to be able to receive up to three SETUP packets on a control endpoint. – The space to be reserved is 10 Words. Three Words are required for the first SETUP packet, 1 Word is required for the Setup stage done Word and 6 Words are required to store two extra SETUP packets among all control endpoints. – 3 Words per SETUP packet are required to store 8 bytes of SETUP data and 4 bytes of SETUP status (Setup packet pattern). The core reserves this space in the receive data. – FIFO to write SETUP data only, and never uses this space for data packets. 3. The application must read the 2 Words of the SETUP packet from the receive FIFO. 4. The application must read and discard the Setup stage done Word from the receive FIFO. • Internal data flow 1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without checking for available space in the receive FIFO and irrespective of the endpoint’s NAK and STALL bit settings. – 2. The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which the SETUP packet was received. For every SETUP packet received on the USB, 3 Words of data are written to the receive FIFO, and the STUPCNT field is decremented by 1. – The first Word contains control information used internally by the core – The second Word contains the first 4 bytes of the SETUP command – The third Word contains the last 4 bytes of the SETUP command 3. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry (Setup stage done Word) to the receive FIFO, indicating the completion of the Setup stage. 4. On the AHB side, SETUP packets are emptied by the application. 5. When the application pops the Setup stage done Word from the receive FIFO, the core interrupts the application with an STUP interrupt (OTG_DOEPINTx), indicating it can process the received SETUP packet. 6. The core clears the endpoint enable bit for control OUT endpoints. • Application programming sequence 1. Program the OTG_DOEPTSIZx register. – STUPCNT = 3 2. Wait for the RXFLVL interrupt (OTG_GINTSTS) and empty the data packets from the receive FIFO. 3. Assertion of the STUP interrupt (OTG_DOEPINTx) marks a successful completion of the SETUP Data Transfer. – 2648/3178 STUPCNT = 3 in OTG_DOEPTSIZx On this interrupt, the application must read the OTG_DOEPTSIZx register to determine the number of SETUP packets received and process the last received SETUP packet. DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Figure 761. Processing a SETUP packet :DLWIRU673LQ27*B'2(3,17[ UHPBVXSFQW UGBUHJ 27*B'2(376,=[ VHWXSBFPG> PHP>± UHPBVXSFQW@ VHWXSBFPG> @ PHP>± UHPBVXSFQW@ )LQGVHWXSFPGW\SH 5HDG FWUOBUGZUVWDJH :ULWH VWDJH VHWXSBQSBLQBSNW 'DWD,1SKDVH VHWXSBQSBLQBSNW 6WDWXV,1SKDVH UFYBRXWBSNW 'DWD287SKDVH 06Y9 • Handling more than three back-to-back SETUP packets Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send more than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 specification does not limit the number of back-to-back SETUP packets a host can send to the same endpoint. When this condition occurs, the OTG_HS controller generates an interrupt (B2BSTUP in OTG_DOEPINTx). • Setting the global OUT NAK Internal data flow: 1. When the application sets the Global OUT NAK (SGONAK bit in OTG_DCTL), the core stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the space availability in the receive FIFO, non-isochronous OUT tokens receive a NAK handshake response, and the core ignores isochronous OUT data packets 2. The core writes the Global OUT NAK pattern to the receive FIFO. The application must reserve enough receive FIFO space to write this data pattern. 3. When the application pops the Global OUT NAK pattern Word from the receive FIFO, the core sets the GONAKEFF interrupt (OTG_GINTSTS). 4. Once the application detects this interrupt, it can assume that the core is in Global OUT NAK mode. The application can clear this interrupt by clearing the SGONAK bit in OTG_DCTL. Application programming sequence: DocID029587 Rev 3 2649/3178 2669 USB on-the-go high-speed (OTG_HS) 1. RM0433 To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field: – SGONAK = 1 in OTG_DCTL 2. Wait for the assertion of the GONAKEFF interrupt in OTG_GINTSTS. When asserted, this interrupt indicates that the core has stopped receiving any type of data except SETUP packets. 3. The application can receive valid OUT packets after it has set SGONAK in OTG_DCTL and before the core asserts the GONAKEFF interrupt (OTG_GINTSTS). 4. The application can temporarily mask this interrupt by writing to the GONAKEFFM bit in the OTG_GINTMSK register. – 5. Whenever the application is ready to exit the Global OUT NAK mode, it must clear the SGONAK bit in OTG_DCTL. This also clears the GONAKEFF interrupt (OTG_GINTSTS). – 6. CGONAK = 1 in OTG_DCTL If the application has masked this interrupt earlier, it must be unmasked as follows: – • GONAKEFFM = 0 in the OTG_GINTMSK register GONAKEFFM = 1 in OTG_GINTMSK Disabling an OUT endpoint The application must use this sequence to disable an OUT endpoint that it has enabled. Application programming sequence: 1. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core. – SGONAK = 1 in OTG_DCTL 2. Wait for the GONAKEFF interrupt (OTG_GINTSTS) 3. Disable the required OUT endpoint by programming the following fields: 4. 5. – EPDIS = 1 in OTG_DOEPCTLx – SNAK = 1 in OTG_DOEPCTLx Wait for the EPDISD interrupt (OTG_DOEPINTx), which indicates that the OUT endpoint is completely disabled. When the EPDISD interrupt is asserted, the core also clears the following bits: – EPDIS = 0 in OTG_DOEPCTLx – EPENA = 0 in OTG_DOEPCTLx The application must clear the Global OUT NAK bit to start receiving data from other non-disabled OUT endpoints. – • SGONAK = 0 in OTG_DCTL Generic non-isochronous OUT data transfers This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt). Application requirements: 2650/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 1. Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer. 2. For OUT transfers, the transfer size field in the endpoint’s transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the Word boundary. 3. – transfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4)) – packet count[EPNUM] = n – n>0 On any OUT endpoint interrupt, the application must read the endpoint’s transfer size register to calculate the size of the payload in the memory. The received payload size can be less than the programmed transfer size. – Payload size in memory = application programmed initial transfer size – core updated final transfer size – Number of USB packets in which this payload was received = application programmed initial packet count – core updated final packet count Internal data flow: 1. The application must set the transfer size and packet count fields in the endpointspecific registers, clear the NAK bit, and enable the endpoint to receive the data. 2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the packet count field for that endpoint by 1. – OUT data packets received with bad data CRC are flushed from the receive FIFO automatically. – After sending an ACK for the packet on the USB, the core discards nonisochronous OUT data packets that the host, which cannot detect the ACK, resends. The application does not detect multiple back-to-back data OUT packets on the same endpoint with the same data PID. In this case the packet count is not decremented. – If there is no space in the receive FIFO, isochronous or non-isochronous data packets are ignored and not written to the receive FIFO. Additionally, nonisochronous OUT tokens receive a NAK handshake reply. – In all the above three cases, the packet count is not decremented because no data are written to the receive FIFO. 3. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or nonisochronous data packets are ignored and not written to the receive FIFO, and nonisochronous OUT tokens receive a NAK handshake reply. 4. After the data are written to the receive FIFO, the application reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint. 5. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet. 6. The OUT data transfer completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions: – The transfer size is 0 and the packet count is 0 – The last OUT data packet written to the receive FIFO is a short packet (0 ≤ packet size < maximum packet size) DocID029587 Rev 3 2651/3178 2669 USB on-the-go high-speed (OTG_HS) 7. RM0433 When either the application pops this entry (OUT data transfer completed), a transfer completed interrupt is generated for the endpoint and the endpoint enable is cleared. Application programming sequence: 1. Program the OTG_DOEPTSIZx register for the transfer size and the corresponding packet count. 2. Program the OTG_DOEPCTLx register with the endpoint characteristics, and set the EPENA and CNAK bits. 3. – EPENA = 1 in OTG_DOEPCTLx – CNAK = 1 in OTG_DOEPCTLx Wait for the RXFLVL interrupt (in OTG_GINTSTS) and empty the data packets from the receive FIFO. – This step can be repeated many times, depending on the transfer size. 4. Asserting the XFRC interrupt (OTG_DOEPINTx) marks a successful completion of the non-isochronous OUT data transfer. 5. Read the OTG_DOEPTSIZx register to determine the size of the received data payload. • Generic isochronous OUT data transfer This section describes a regular isochronous OUT data transfer. Application requirements: 1. All the application requirements for non-isochronous OUT data transfers also apply to isochronous OUT data transfers. 2. For isochronous OUT data transfers, the transfer size and packet count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more. Isochronous OUT data transfers cannot span more than 1 frame. 3. The application must read all isochronous OUT data packets from the receive FIFO (data and status) before the end of the periodic frame (EOPF interrupt in OTG_GINTSTS). 4. To receive data in the following frame, an isochronous OUT endpoint must be enabled after the EOPF (OTG_GINTSTS) and before the SOF (OTG_GINTSTS). Internal data flow: 1. The internal data flow for isochronous OUT endpoints is the same as that for nonisochronous OUT endpoints, but for a few differences. 2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core receives data on an isochronous OUT endpoint in a particular frame only if the following condition is met: – 3. EONUM (in OTG_DOEPCTLx) = FNSOF[0] (in OTG_DSTS) When the application completely reads an isochronous OUT data packet (data and status) from the receive FIFO, the core updates the RXDPID field in OTG_DOEPTSIZx with the data PID of the last isochronous OUT data packet read from the receive FIFO. Application programming sequence: 2652/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 1. Program the OTG_DOEPTSIZx register for the transfer size and the corresponding packet count 2. Program the OTG_DOEPCTLx register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits. 3. – EPENA = 1 – CNAK = 1 – EONUM = (0: Even/1: Odd) Wait for the RXFLVL interrupt (in OTG_GINTSTS) and empty the data packets from the receive FIFO – This step can be repeated many times, depending on the transfer size. 4. The assertion of the XFRC interrupt (in OTG_DOEPINTx) marks the completion of the isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory are good. 5. This interrupt cannot always be detected for isochronous OUT transfers. Instead, the application can detect the INCOMPISOOUT interrupt in OTG_GINTSTS. 6. Read the OTG_DOEPTSIZx register to determine the size of the received transfer and to determine the validity of the data received in the frame. The application must treat the data received in memory as valid only if one of the following conditions is met: – RXDPID = DATA0 (in OTG_DOEPTSIZx) and the number of USB packets in which this payload was received = 1 – RXDPID = DATA1 (in OTG_DOEPTSIZx) and the number of USB packets in which this payload was received = 2 RXDPID = D2 (in OTG_DOEPTSIZx) and the number of USB packets in which this payload was received = 3The number of USB packets in which this payload was received = Application programmed initial packet count – Core updated final packet count The application can discard invalid data packets. • Incomplete isochronous OUT data transfers This section describes the application programming sequence when isochronous OUT data packets are dropped inside the core. Internal data flow: 1. 2. For isochronous OUT endpoints, the XFRC interrupt (in OTG_DOEPINTx) may not always be asserted. If the core drops isochronous OUT data packets, the application could fail to detect the XFRC interrupt (OTG_DOEPINTx) under the following circumstances: – When the receive FIFO cannot accommodate the complete ISO OUT data packet, the core drops the received ISO OUT data – When the isochronous OUT data packet is received with CRC errors – When the isochronous OUT token received by the core is corrupted – When the application is very slow in reading the data from the receive FIFO When the core detects an end of periodic frame before transfer completion to all isochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt (INCOMPISOOUT in OTG_GINTSTS), indicating that an XFRC interrupt (in OTG_DOEPINTx) is not asserted on at least one of the isochronous OUT endpoints. At DocID029587 Rev 3 2653/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the USB. Application programming sequence: 1. Asserting the INCOMPISOOUT interrupt (OTG_GINTSTS) indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer. 2. If this occurs because isochronous OUT data is not completely emptied from the endpoint, the application must ensure that the application empties all isochronous OUT data (data and status) from the receive FIFO before proceeding. – 3. When all data are emptied from the receive FIFO, the application can detect the XFRC interrupt (OTG_DOEPINTx). In this case, the application must re-enable the endpoint to receive isochronous OUT data in the next frame. When it receives an INCOMPISOOUT interrupt (in OTG_GINTSTS), the application must read the control registers of all isochronous OUT endpoints (OTG_DOEPCTLx) to determine which endpoints had an incomplete transfer in the current microframe. An endpoint transfer is incomplete if both the following conditions are met: – EONUM bit (in OTG_DOEPCTLx) = FNSOF[0] (in OTG_DSTS) – EPENA = 1 (in OTG_DOEPCTLx) 4. The previous step must be performed before the SOF interrupt (in OTG_GINTSTS) is detected, to ensure that the current frame number is not changed. 5. For isochronous OUT endpoints with incomplete transfers, the application must discard the data in the memory and disable the endpoint by setting the EPDIS bit in OTG_DOEPCTLx. 6. Wait for the EPDISD interrupt (in OTG_DOEPINTx) and enable the endpoint to receive new data in the next frame. – • Because the core can take some time to disable the endpoint, the application may not be able to receive the data in the next frame after receiving bad isochronous data. Stalling a non-isochronous OUT endpoint This section describes how the application can stall a non-isochronous endpoint. 1. 2. Put the core in the Global OUT NAK mode. Disable the required endpoint – When disabling the endpoint, instead of setting the SNAK bit in OTG_DOEPCTL, set STALL = 1 (in OTG_DOEPCTL). The STALL bit always takes precedence over the NAK bit. 3. When the application is ready to end the STALL handshake for the endpoint, the STALL bit (in OTG_DOEPCTLx) must be cleared. 4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint. Examples This section describes and depicts some fundamental transfer types and scenarios. • 2654/3178 Bulk OUT transaction DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Figure 762 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB and describes the events involved in the process. Figure 762. Bulk OUT transaction +RVW 86% 'HYLFH $SSOLFDWLRQ LQLW BRXWBHS ;)56,= 3.7&17 E\WHV :UBUHJ 27*B'2(376,=[ 2 87 :UBUHJ 27*B'2(3&7/[ (3(1$ &1 $. E\WHV [DFWB $& . 5;)/9/ LLQWU 27*B'2 (3&7/[ 3.7&1 7 1$. ;)56,= U 28 7 1$ . LGOH XQWLO LQWU UFYBRXW BSNW ;) LQW U 5& 2Q QHZ [IHU RU 5[),)2 QRWHP SW\ LGOH XQWLO LQWU 06 9 After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints by setting CNAK = 1 and EPENA = 1 (in OTG_DOEPCTLx), and setting a suitable XFRSIZ and PKTCNT in the OTG_DOEPTSIZx register. 1. host attempts to send data (OUT token) to an endpoint. 2. When the core receives the OUT token on the USB, it stores the packet in the Rx FIFO because space is available there. 3. After writing the complete packet in the Rx FIFO, the core then asserts the RXFLVL interrupt (in OTG_GINTSTS). 4. On receiving the PKTCNT number of USB packets, the core internally sets the NAK bit for this endpoint to prevent it from receiving any more packets. 5. The application processes the interrupt and reads the data from the Rx FIFO. 6. When the application has read all the data (equivalent to XFRSIZ), the core generates an XFRC interrupt (in OTG_DOEPINTx). 7. The application processes the interrupt and uses the setting of the XFRC interrupt bit (in OTG_DOEPINTx) to determine that the intended transfer is complete. IN data transfers • Packet write This section describes how the application writes data packets to the endpoint FIFO when dedicated transmit FIFOs are enabled. DocID029587 Rev 3 2655/3178 2669 USB on-the-go high-speed (OTG_HS) 1. 2. RM0433 The application can either choose the polling or the interrupt mode. – In polling mode, the application monitors the status of the endpoint transmit data FIFO by reading the OTG_DTXFSTSx register, to determine if there is enough space in the data FIFO. – In interrupt mode, the application waits for the TXFE interrupt (in OTG_DIEPINTx) and then reads the OTG_DTXFSTSx register, to determine if there is enough space in the data FIFO. – To write a single non-zero length data packet, there must be space to write the entire packet in the data FIFO. – To write zero length packet, the application must not look at the FIFO space. Using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet, the application must first write into the endpoint control register, before writing the data into the data FIFO. Typically, the application, must do a read modify write on the OTG_DIEPCTLx register to avoid modifying the contents of the register, except for setting the Endpoint Enable bit. The application can write multiple packets for the same endpoint into the transmit FIFO, if space is available. For periodic IN endpoints, the application must write packets only for one microframe. It can write packets for the next periodic transaction only after getting transfer complete for the previous transaction. • Setting IN endpoint NAK Internal data flow: 1. When the application sets the IN NAK for a particular endpoint, the core stops transmitting data on the endpoint, irrespective of data availability in the endpoint’s transmit FIFO. 2. Non-isochronous IN tokens receive a NAK handshake reply – Isochronous IN tokens receive a zero-data-length packet reply 3. The core asserts the INEPNE (IN endpoint NAK effective) interrupt in OTG_DIEPINTx in response to the SNAK bit in OTG_DIEPCTLx. 4. Once this interrupt is seen by the application, the application can assume that the endpoint is in IN NAK mode. This interrupt can be cleared by the application by setting the CNAK bit in OTG_DIEPCTLx. Application programming sequence: 1. To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed. – 2. Wait for assertion of the INEPNE interrupt in OTG_DIEPINTx. This interrupt indicates that the core has stopped transmitting data on the endpoint. 3. The core can transmit valid IN data on the endpoint after the application has set the NAK bit, but before the assertion of the NAK Effective interrupt. 4. The application can mask this interrupt temporarily by writing to the INEPNEM bit in OTG_DIEPMSK. – 5. 2656/3178 SNAK = 1 in OTG_DIEPCTLx INEPNEM = 0 in OTG_DIEPMSK To exit Endpoint NAK mode, the application must clear the NAK status bit (NAKSTS) in OTG_DIEPCTLx. This also clears the INEPNE interrupt (in OTG_DIEPINTx). DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) – 6. If the application masked this interrupt earlier, it must be unmasked as follows: – • CNAK = 1 in OTG_DIEPCTLx INEPNEM = 1 in OTG_DIEPMSK IN endpoint disable Use the following sequence to disable a specific IN endpoint that has been previously enabled. Application programming sequence: 1. 2. The application must stop writing data on the AHB for the IN endpoint to be disabled. The application must set the endpoint in NAK mode. – SNAK = 1 in OTG_DIEPCTLx 3. Wait for the INEPNE interrupt in OTG_DIEPINTx. 4. Set the following bits in the OTG_DIEPCTLx register for the endpoint that must be disabled. 5. – EPDIS = 1 in OTG_DIEPCTLx – SNAK = 1 in OTG_DIEPCTLx Assertion of the EPDISD interrupt in OTG_DIEPINTx indicates that the core has completely disabled the specified endpoint. Along with the assertion of the interrupt, the core also clears the following bits: – EPENA = 0 in OTG_DIEPCTLx – EPDIS = 0 in OTG_DIEPCTLx 6. The application must read the OTG_DIEPTSIZx register for the periodic IN EP, to calculate how much data on the endpoint were transmitted on the USB. 7. The application must flush the data in the Endpoint transmit FIFO, by setting the following fields in the OTG_GRSTCTL register: – TXFNUM (in OTG_GRSTCTL) = Endpoint transmit FIFO number – TXFFLSH in (OTG_GRSTCTL) = 1 The application must poll the OTG_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point. • Generic non-periodic IN data transfers Application requirements: 1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer are part of a single buffer. 2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer. – To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: Transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp If (sp > 0), then packet count[EPNUM] = x + 1. Otherwise, packet count[EPNUM] = x – To transmit a single zero-length data packet: DocID029587 Rev 3 2657/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Transfer size[EPNUM] = 0 Packet count[EPNUM] = 1 – To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer into two parts. The first sends maximum-packet-size data packets and the second sends the zerolength data packet alone. First transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n; Second transfer: transfer size[EPNUM] = 0; packet count = 1; 3. Once an endpoint is enabled for data transfers, the core updates the Transfer size register. At the end of the IN transfer, the application must read the Transfer size register to determine how much data posted in the transmit FIFO have already been sent on the USB. 4. Data fetched into transmit FIFO = Application-programmed initial transfer size – coreupdated final transfer size – Data transmitted on USB = (application-programmed initial packet count – Core updated final packet count) × MPSIZ[EPNUM] – Data yet to be transmitted on USB = (Application-programmed initial transfer size – data transmitted on USB) Internal data flow: 1. The application must set the transfer size and packet count fields in the endpointspecific registers and enable the endpoint to transmit the data. 2. The application must also write the required data to the transmit FIFO for the endpoint. 3. Every time a packet is written into the transmit FIFO by the application, the transfer size for that endpoint is decremented by the packet size. The data is fetched from the memory by the application, until the transfer size for the endpoint becomes 0. After writing the data into the FIFO, the “number of packets in FIFO” count is incremented (this is a 3-bit count, internally maintained by the core for each IN endpoint transmit FIFO. The maximum number of packets maintained by the core at any time in an IN endpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, without any data in the FIFO. 4. Once the data are written to the transmit FIFO, the core reads them out upon receiving an IN token. For every non-isochronous IN data packet transmitted with an ACK handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. 5. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the packet count field. 6. If there are no data in the FIFO for a received IN token and the packet count field for that endpoint is zero, the core generates an “IN token received when Tx FIFO is empty” (ITTXFE) Interrupt for the endpoint, provided that the endpoint NAK bit is not set. The core responds with a NAK handshake for non-isochronous endpoints on the USB. 7. The core internally rewinds the FIFO pointers and no timeout interrupt is generated. 8. When the transfer size is 0 and the packet count is 0, the transfer complete (XFRC) interrupt for the endpoint is generated and the endpoint enable is cleared. Application programming sequence: 2658/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) 1. Program the OTG_DIEPTSIZx register with the transfer size and corresponding packet count. 2. Program the OTG_DIEPCTLx register with the endpoint characteristics and set the CNAK and EPENA (Endpoint Enable) bits. 3. When transmitting non-zero length data packet, the application must poll the OTG_DTXFSTSx register (where x is the FIFO number associated with that endpoint) to determine whether there is enough space in the data FIFO. The application can optionally use TXFE (in OTG_DIEPINTx) before writing the data. • Generic periodic IN data transfers This section describes a typical periodic IN data transfer. Application requirements: 1. Application requirements 1, 2, 3, and 4 of Generic non-periodic IN data transfers on page 2657 also apply to periodic IN data transfers, except for a slight modification of requirement 2. – The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer, the following conditions must be met: transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp (where x is an integer ≥ 0, and 0 ≤ sp < MPSIZ[EPNUM]) If (sp > 0), packet count[EPNUM] = x + 1 Otherwise, packet count[EPNUM] = x; MCNT[EPNUM] = packet count[EPNUM] – The application cannot transmit a zero-length data packet at the end of a transfer. It can transmit a single zero-length data packet by itself. To transmit a single zerolength data packet: – transfer size[EPNUM] = 0 packet count[EPNUM] = 1 MCNT[EPNUM] = packet count[EPNUM] 2. 3. The application can only schedule data transfers one frame at a time. – (MCNT – 1) × MPSIZ ≤ XFERSIZ ≤ MCNT × MPSIZ – PKTCNT = MCNT (in OTG_DIEPTSIZx) – If XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short packet. – Note that: MCNT is in OTG_DIEPTSIZx, MPSIZ is in OTG_DIEPCTLx, PKTCNT is in OTG_DIEPTSIZx and XFERSIZ is in OTG_DIEPTSIZx The complete data to be transmitted in the frame must be written into the transmit FIFO by the application, before the IN token is received. Even when 1 Word of the data to be transmitted per frame is missing in the transmit FIFO when the IN token is received, the core behaves as when the FIFO is empty. When the transmit FIFO is empty: – A zero data length packet would be transmitted on the USB for isochronous IN endpoints – A NAK handshake would be transmitted on the USB for interrupt IN endpoints Internal data flow: DocID029587 Rev 3 2659/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 1. The application must set the transfer size and packet count fields in the endpointspecific registers and enable the endpoint to transmit the data. 2. The application must also write the required data to the associated transmit FIFO for the endpoint. 3. Every time the application writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data are fetched from application memory until the transfer size for the endpoint becomes 0. 4. When an IN token is received for a periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data payload (complete packet, in dedicated FIFO mode) for the frame is not present in the FIFO, then the core generates an IN token received when Tx FIFO empty interrupt for the endpoint. 5. 6. – A zero-length data packet is transmitted on the USB for isochronous IN endpoints – A NAK handshake is transmitted on the USB for interrupt IN endpoints The packet count for the endpoint is decremented by 1 under the following conditions: – For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted – For interrupt endpoints, when an ACK handshake is transmitted – When the transfer size and packet count are both 0, the transfer completed interrupt for the endpoint is generated and the endpoint enable is cleared. At the “Periodic frame Interval” (controlled by PFIVL in OTG_DCFG), when the core finds non-empty any of the isochronous IN endpoint FIFOs scheduled for the current frame non-empty, the core generates an IISOIXFR interrupt in OTG_GINTSTS. Application programming sequence: 1. Program the OTG_DIEPCTLx register with the endpoint characteristics and set the CNAK and EPENA bits. 2. Write the data to be transmitted in the next frame to the transmit FIFO. 3. Asserting the ITTXFE interrupt (in OTG_DIEPINTx) indicates that the application has not yet written all data to be transmitted to the transmit FIFO. 4. If the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on the next IN token attempt. 5. Asserting the XFRC interrupt (in OTG_DIEPINTx) with no ITTXFE interrupt in OTG_DIEPINTx indicates the successful completion of an isochronous IN transfer. A read to the OTG_DIEPTSIZx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the USB. 6. Asserting the XFRC interrupt (in OTG_DIEPINTx), with or without the ITTXFE interrupt (in OTG_DIEPINTx), indicates the successful completion of an interrupt IN transfer. A read to the OTG_DIEPTSIZx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the USB. 7. Asserting the incomplete isochronous IN transfer (IISOIXFR) interrupt in OTG_GINTSTS with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic IN token in the current frame. • Incomplete isochronous IN data transfers This section describes what the application must do on an incomplete isochronous IN data transfer. 2660/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Internal data flow: 1. An isochronous IN transfer is treated as incomplete in one of the following conditions: a) The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In this case, the application detects an incomplete isochronous IN transfer interrupt (IISOIXFR in OTG_GINTSTS). b) The application is slow to write the complete data payload to the transmit FIFO and an IN token is received before the complete data payload is written to the FIFO. In this case, the application detects an IN token received when Tx FIFO empty interrupt in OTG_DIEPINTx. The application can ignore this interrupt, as it eventually results in an incomplete isochronous IN transfer interrupt (IISOIXFR in OTG_GINTSTS) at the end of periodic frame. The core transmits a zero-length data packet on the USB in response to the received IN token. 2. The application must stop writing the data payload to the transmit FIFO as soon as possible. 3. The application must set the NAK bit and the disable bit for the endpoint. 4. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for the endpoint. Application programming sequence: 1. The application can ignore the IN token received when Tx FIFO empty interrupt in OTG_DIEPINTx on any isochronous IN endpoint, as it eventually results in an incomplete isochronous IN transfer interrupt (in OTG_GINTSTS). 2. Assertion of the incomplete isochronous IN transfer interrupt (in OTG_GINTSTS) indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints. 3. The application must read the Endpoint Control register for all isochronous IN endpoints to detect endpoints with incomplete IN data transfers. 4. The application must stop writing data to the Periodic Transmit FIFOs associated with these endpoints on the AHB. 5. Program the following fields in the OTG_DIEPCTLx register to disable the endpoint: 6. – SNAK = 1 in OTG_DIEPCTLx – EPDIS = 1 in OTG_DIEPCTLx The assertion of the Endpoint Disabled interrupt in OTG_DIEPINTx indicates that the core has disabled the endpoint. – • At this point, the application must flush the data in the associated transmit FIFO or overwrite the existing data in the FIFO by enabling the endpoint for a new transfer in the next microframe. To flush the data, the application must use the OTG_GRSTCTL register. Stalling non-isochronous IN endpoints This section describes how the application can stall a non-isochronous endpoint. Application programming sequence: DocID029587 Rev 3 2661/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 1. Disable the IN endpoint to be stalled. Set the STALL bit as well. 2. EPDIS = 1 in OTG_DIEPCTLx, when the endpoint is already enabled – STALL = 1 in OTG_DIEPCTLx – The STALL bit always takes precedence over the NAK bit 3. Assertion of the Endpoint Disabled interrupt (in OTG_DIEPINTx) indicates to the application that the core has disabled the specified endpoint. 4. The application must flush the non-periodic or periodic transmit FIFO, depending on the endpoint type. In case of a non-periodic endpoint, the application must re-enable the other non-periodic endpoints that do not need to be stalled, to transmit data. 5. Whenever the application is ready to end the STALL handshake for the endpoint, the STALL bit must be cleared in OTG_DIEPCTLx. 6. If the application sets or clears a STALL bit for an endpoint due to a SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the STALL bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint. Special case: stalling the control OUT endpoint The core must stall IN/OUT tokens if, during the data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet. In this case, the application must enable the ITTXFE interrupt in OTG_DIEPINTx and the OTEPDIS interrupt in OTG_DOEPINTx during the data stage of the control transfer, after the core has transferred the amount of data specified in the SETUP packet. Then, when the application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt. 57.15.7 Worst case response time When the OTG_HS controller acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT. This worst case response time depends on the AHB clock frequency. The core registers are in the AHB domain, and the core does not accept another token before updating these register values. The worst case is for any token following an isochronous OUT, because for an isochronous transaction, there is no handshake and the next token could come sooner. This worst case value is 7 PHY clocks when the AHB clock is the same as the PHY clock. When the AHB clock is faster, this value is smaller. If this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK and drops isochronous and SETUP tokens. The host interprets this as a timeout condition for SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete isochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer interrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were dropped. Choosing the value of TRDT in OTG_GUSBCFG The value in TRDT (OTG_GUSBCFG) is the time it takes for the MAC, in terms of PHY clocks after it has received an IN token, to get the FIFO status, and thus the first data from the PFC block. This time involves the synchronization delay between the PHY and AHB clocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. In this case, the delay is 5 clocks. 2662/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) Once the MAC receives an IN token, this information (token received) is synchronized to the AHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from the SPRAM and writes them into the dual clock source buffer. The MAC then reads the data out of the source buffer (4 deep). If the AHB is running at a higher frequency than the PHY, the application can use a smaller value for TRDT (in OTG_GUSBCFG). Figure 763 has the following signals: • tkn_rcvd: Token received information from MAC to PFC • dynced_tkn_rcvd: Doubled sync tkn_rcvd, from PCLK to HCLK domain • spr_read: Read to SPRAM • spr_addr: Address to SPRAM • spr_rdata: Read data from SPRAM • srcbuf_push: Push to the source buffer • srcbuf_rdata: Read data from the source buffer. Data seen by MAC To calculate the value of TRDT, refer to Table 488: TRDT values (HS). Figure 763. TRDT max timing case NS NS NS NS NS (#,+ 0#,+ TKN?RCVD DSYNCED?TKN?RCVD SPR?READ ! SPR?ADDR $ SPR?RDATA SRCBUF?PUSH SRCBUF?RDATA $ #LOCKS AI DocID029587 Rev 3 2663/3178 2669 USB on-the-go high-speed (OTG_HS) 57.15.8 RM0433 OTG programming model The OTG_HS controller is an OTG device supporting HNP and SRP. When the core is connected to an “A” plug, it is referred to as an A-device. When the core is connected to a “B” plug it is referred to as a B-device. In host mode, the OTG_HS controller turns off VBUS to conserve power. SRP is a method by which the B-device signals the A-device to turn on VBUS power. A device must perform both data-line pulsing and VBUS pulsing, but a host can detect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the Bdevice negotiates and switches to host role. In Negotiated mode after HNP, the B-device suspends the bus and reverts to the device role. A-device session request protocol The application must set the SRP-capable bit in the Core USB configuration register. This enables the OTG_HS controller to detect SRP as an A-device. Figure 764. A-device SRP 3USPEND $26?6"53 6"53?6!,)$ 6"53 PULSING !?6!,)$ $ $ $ATA LINE PULSING #ONNECT ,OW AI 1. DRV_VBUS = VBUS drive signal to the PHY VBUS_VALID = VBUS valid signal from PHY A_VALID = A-peripheral VBUS level signal to PHY D+ = Data plus line D- = Data minus line The following points refer and describe the signal numeration shown in the Figure 764: 2664/3178 1. To save power, the application suspends and turns off port power when the bus is idle by writing the port suspend and port power bits in the host port control and status register. 2. PHY indicates port power off by deasserting the VBUS_VALID signal. 3. The device must detect SE0 for at least 2 ms to start SRP when VBUS power is off. 4. To initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The OTG_HS controller detects data-line pulsing. 5. The device drives VBUS above the A-device session valid (2.0 V minimum) for VBUS pulsing. The OTG_HS controller interrupts the application on detecting SRP. The Session DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) request detected bit is set in Global interrupt status register (SRQINT set in OTG_GINTSTS). 6. The application must service the Session request detected interrupt and turn on the port power bit by writing the port power bit in the host port control and status register. The PHY indicates port power-on by asserting the VBUS_VALID signal. 7. When the USB is powered, the device connects, completing the SRP process. B-device session request protocol The application must set the SRP-capable bit in the Core USB configuration register. This enables the OTG_HS controller to initiate SRP as a B-device. SRP is a means by which the OTG_HS controller can request a new session from the host. Figure 765. B-device SRP 3USPEND 6"53?6!,)$ "?6!,)$ $)3#(2'?6"53 3%33?%.$ $0 $ATA LINE PULSING $- #ONNECT ,OW 6"53 PULSING #(2'?6"53 AI 1. VBUS_VALID = VBUS valid signal from PHY B_VALID = B-peripheral valid session to PHY DISCHRG_VBUS = discharge signal to PHY SESS_END = session end signal to PHY CHRG_VBUS = charge VBUS signal to PHY DP = Data plus line DM = Data minus line The following points refer and describe the signal numeration shown in the Figure 765: 1. To save power, the host suspends and turns off port power when the bus is idle. The OTG_HS controller sets the early suspend bit in the Core interrupt register after 3 ms of bus idleness. Following this, the OTG_HS controller sets the USB suspend bit in the Core interrupt register. The OTG_HS controller informs the PHY to discharge VBUS. 2. The PHY indicates the session’s end to the device. This is the initial condition for SRP. The OTG_HS controller requires 2 ms of SE0 before initiating SRP. For a USB 1.1 full-speed serial transceiver, the application must wait until VBUS discharges to 0.2 V after BSVLD (in OTG_GOTGCTL) is deasserted. This discharge DocID029587 Rev 3 2665/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 time can be obtained from the transceiver vendor and varies from one transceiver to another. 3. The OTG_HS core informs the PHY to speed up VBUS discharge. 4. The application initiates SRP by writing the session request bit in the OTG Control and status register. The OTG_HS controller perform data-line pulsing followed by VBUS pulsing. 5. The host detects SRP from either the data-line or VBUS pulsing, and turns on VBUS. The PHY indicates VBUS power-on to the device. 6. The OTG_HS controller performs VBUS pulsing. The host starts a new session by turning on VBUS, indicating SRP success. The OTG_HS controller interrupts the application by setting the session request success status change bit in the OTG interrupt status register. The application reads the session request success bit in the OTG control and status register. 7. When the USB is powered, the OTG_HS controller connects, completing the SRP process. A-device host negotiation protocol HNP switches the USB host role from the A-device to the B-device. The application must set the HNP-capable bit in the Core USB configuration register to enable the OTG_HS controller to perform HNP as an A-device. Figure 766. A-device HNP /4' CORE (OST $EVICE 3USPEND $0 (OST 2ESET $- 4RAFFIC #ONNECT 4RAFFIC $005,,$/7. $-05,,$/7. AI 1. DPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY. DMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY. The following points refer and describe the signal numeration shown in the Figure 766: 1. 2666/3178 The OTG_HS controller sends the B-device a SetFeature b_hnp_enable descriptor to enable HNP support. The B-device’s ACK response indicates that the B-device supports HNP. The application must set host Set HNP Enable bit in the OTG Control DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) and status register to indicate to the OTG_HS controller that the B-device supports HNP. 2. When it has finished using the bus, the application suspends by writing the Port suspend bit in the host port control and status register. 3. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP. The B-device initiates HNP only when it must switch to the host role; otherwise, the bus continues to be suspended. The OTG_HS controller sets the host negotiation detected interrupt in the OTG interrupt status register, indicating the start of HNP. The OTG_HS controller deasserts the DM pull down and DM pull down in the PHY to indicate a device role. The PHY enables the OTG_DP pull-up resistor to indicate a connect for B-device. The application must read the current mode bit in the OTG Control and status register to determine device mode operation. 4. The B-device detects the connection, issues a USB reset, and enumerates the OTG_HS controller for data traffic. 5. The B-device continues the host role, initiating traffic, and suspends the bus when done. The OTG_HS controller sets the early suspend bit in the Core interrupt register after 3 ms of bus idleness. Following this, the OTG_HS controller sets the USB Suspend bit in the Core interrupt register. 6. In Negotiated mode, the OTG_HS controller detects the suspend, disconnects, and switches back to the host role. The OTG_HS controller asserts the DM pull down and DM pull down in the PHY to indicate its assumption of the host role. 7. The OTG_HS controller sets the Connector ID status change interrupt in the OTG Interrupt Status register. The application must read the connector ID status in the OTG Control and Status register to determine the OTG_HS controller operation as an Adevice. This indicates the completion of HNP to the application. The application must read the Current mode bit in the OTG control and status register to determine host mode operation. 8. The B-device connects, completing the HNP process. B-device host negotiation protocol HNP switches the USB host role from B-device to A-device. The application must set the HNP-capable bit in the Core USB configuration register to enable the OTG_HS controller to perform HNP as a B-device. DocID029587 Rev 3 2667/3178 2669 USB on-the-go high-speed (OTG_HS) RM0433 Figure 767. B-device HNP 27*FRUH 'HYLFH +RVW 6XVSHQG '3 'HYLFH 5HVHW '0 7UDIILF &RQQHFW 7UDIILF '338//'2:1 '038//'2:1 DLE 1. DPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY. DMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY. The following points refer and describe the signal numeration shown in the Figure 767: 1. The A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. The OTG_HS controller’s ACK response indicates that it supports HNP. The application must set the device HNP enable bit in the OTG Control and status register to indicate HNP support. The application sets the HNP request bit in the OTG Control and status register to indicate to the OTG_HS controller to initiate HNP. 2. When it has finished using the bus, the A-device suspends by writing the Port suspend bit in the host port control and status register. The OTG_HS controller sets the Early suspend bit in the Core interrupt register after 3 ms of bus idleness. Following this, the OTG_HS controller sets the USB suspend bit in the Core interrupt register. The OTG_HS controller disconnects and the A-device detects SE0 on the bus, indicating HNP. The OTG_HS controller asserts the DP pull down and DM pull down in the PHY to indicate its assumption of the host role. The A-device responds by activating its OTG_DP pull-up resistor within 3 ms of detecting SE0. The OTG_HS controller detects this as a connect. The OTG_HS controller sets the host negotiation success status change interrupt in the OTG Interrupt status register, indicating the HNP status. The application must read the host negotiation success bit in the OTG Control and status register to determine 2668/3178 DocID029587 Rev 3 RM0433 USB on-the-go high-speed (OTG_HS) host negotiation success. The application must read the current Mode bit in the Core interrupt register (OTG_GINTSTS) to determine host mode operation. 3. The application sets the reset bit (PRST in OTG_HPRT) and the OTG_HS controller issues a USB reset and enumerates the A-device for data traffic. 4. The OTG_HS controller continues the host role of initiating traffic, and when done, suspends the bus by writing the Port suspend bit in the host port control and status register. 5. In Negotiated mode, when the A-device detects a suspend, it disconnects and switches back to the host role. The OTG_HS controller deasserts the DP pull down and DM pull down in the PHY to indicate the assumption of the device role. 6. The application must read the current mode bit in the Core interrupt (OTG_GINTSTS) register to determine the host mode operation. 7. The OTG_HS controller connects, completing the HNP process. DocID029587 Rev 3 2669/3178 2669 Ethernet (ETH): media access control (MAC) with DMA controller 58 Ethernet (ETH): media access control (MAC) with DMA controller 58.1 Ethernet introduction RM0433 Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission. The Ethernet peripheral enables the devices to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard. The Ethernet provides a configurable, flexible peripheral to meet the needs of various applications and customers. It supports two industry standard interfaces to the external physical layer (PHY): the default media independent interface (MII) defined in the IEEE 802.3 specifications and the reduced media independent interface (RMII). It can be used in number of applications such as switches and network interface cards. In addition to the default interfaces defined in the IEEE 802.3 specifications, the Ethernet peripheral supports several industry standard interfaces to the PHY. It is compliant with the following standards: 58.2 • IEEE 802.3-2008 for Ethernet MAC, Media Independent Interface (MII) • IEEE 1588-2008 for precision networked clock synchronization (PTP) • IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic • IEEE 802.3az-2010 for Energy Efficient Ethernet (EEE) • AMBA 2.0 for AHB master and AHB slave ports • RMII specification version 1.2 from RMII consortium Ethernet main features Ethernet peripheral embeds a dedicated DMA for direct memory interface, a media access controller (MAC) and a PHY interface block supporting several formats. 58.2.1 MAC core features Interfaces 2670/3178 • Separate transmission, reception, and control interfaces to the application • 32-bit data transfer interface on the application side • 10, 100 data transfer rates with the following PHY interfaces: – IEEE 802.3-compliant MII (default) interface to communicate with an external Fast Ethernet PHY – RMII interface to communicate with an external Fast Ethernet PHY • MDIO (Clause 22 and Clause 45) master interface for PHY device configuration and management • Supports mandatory network statistics with RMON counters (RFC2819/RFC2665) DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Main operations • Support of both full-duplex and half-duplex operations: – CSMA/CD protocol for half-duplex operation – IEEE 802.3x flow control for full-duplex operation – Optional forwarding of received pause control frames to the user application in fullduplex operation – Back-pressure in half-duplex operation – Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation • Full-duplex flow control operations (IEEE 802.3x Pause packets and Priority flow control) • Preamble and start-of-frame data (SFD) insertion in Transmit mode, and deletion in Receive paths • Automatic CRC and pad generation controllable on a per-frame basis • Programmable packet length to support Standard or up to 16 Kbyte Jumbo Ethernet packets • Programmable Inter Packet Gap • Layer 3/Layer 4 checksum offload for received packets • Calculation and insertion of IPv4 header checksum and TCP, UDP, or ICMP checksum in frames transmitted in Store-and-Forward mode • Two sets of FIFOs: a 2048-byte Transmit FIFO with programmable threshold capability, and a 2048-byte Receive FIFO with a configurable threshold • Store-and-Forward mechanism or threshold mode (cut-through) for transmission to the MAC • Programmable Rx queue threshold (or cut-through) mode • Internal loopback from Tx to Rx on MII for debugging. VLAN management • Source Address field insertion or replacement, as well as VLAN insertion, replacement, and deletion in transmitted packets with per-packet or static-global control • Insertion, replacement or deletion of up to two VLAN tags • IEEE 802.1Q VLAN tag detection and possibility to delete the VLAN tags in received packets • Stripping of up to two VLAN tags and providing the tags in the status. DocID029587 Rev 3 2671/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Packet filtering • • Flexible address filtering modes: – 3 additional 48-bit perfect destination address (DA) filters with masks for each byte – 3 additional 48-bit source address (SA) comparison check with masks for each byte – 64 bit Hash filter for multicast and unicast (DA) addresses – Option to pass all multicast addressed packets – Promiscuous mode to pass all packets without any filtering for network monitoring – Pass all incoming packets (as per filter) with a status report Additional packet filtering: – VLAN tag-based: perfect match and Hash-based filtering with filtering based either on the outer or inner VLAN tag – Layer 3 and Layer 4-based: TCP or UDP over IPv4 or IPv6 IEEE 1588-2008/PTPv2 • Ethernet packet time-stamping as described in IEEE 1588-2002 and IEEE 1588-2008 specifications (64-bit timestamps given in the Tx or Rx status of PTP packet). Both onestep and two-step timestamping is supported in Tx direction. • Flexibility to control the Pulse-Per-Second (PPS) output signal (ptp_pps_o) Low-power modes 2672/3178 • Standard IEEE 802.3az-2010 for Energy Efficient Ethernet in MII PHYs. • Module to detect remote wakeup packets and AMD Magic packets DocID029587 Rev 3 RM0433 58.2.2 Ethernet (ETH): media access control (MAC) with DMA controller DMA features The DMA block exchanges data between the peripheral and the system memory. DMA transfers are driven by software descriptors structure. The application can use a set of registers (see Section 58.11.2: Ethernet DMA registers) to control the DMA operations. The DMA block supports the following features: 58.2.3 • 32-bit data transfers • Separate DMA in Transmit path and receive paths • Optimization for packet-oriented DMA transfers with packet delimiters • Byte-aligned addressing for data buffer support • Dual-buffer (ring) descriptor support • Descriptor architecture allowing large blocks of data transfer with minimum CPU intervention (each descriptor can transfer up to 32 Kbytes of data) • Comprehensive status reporting normal operation and transfer errors • Individual programmable burst length for Tx DMA and Rx DMA engines for optimal host bus utilization • Programmable interrupt options for different operational conditions • Per-packet Transmit or Receive Complete Interrupt control • Round-robin or fixed-priority arbitration between the Receive and Transmit engines • Start and Stop modes • Separate ports for host control (AHB) access and host data interface • Tx DMA channel with TCP Segmentation Offload (TSO) feature enabled Bus interface features AHB master interface The AHB master interface features as the following: • Interfaces with the application through AHB • Little-endian mode • 32-bit data on the AHB master port • Split, Retry, and Error AHB responses • AHB 1K boundary burst splitting • Software-selected type of AHB burst (fixed burst, indefinite burst, or mix of both) The AHB master interface does not generate the following: • Wrap burst • Locked or protected transfers AHB slave interface The AHB slave interface supports the following features: • Interfaces with the application through AHB • Little-endian mode • AHB slave interface (32-bit) for CSR access • All AHB burst types DocID029587 Rev 3 2673/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 The AHB slave interface does not generate the following responses: 58.3 • Split • Retry • Error Ethernet pins and internal signals Table 491 lists the Ethernet inputs and output signals connected to package pins or balls, while Table 492 shows the internal Ethernet signals. Table 491. Ethernet peripheral pins 2674/3178 Pin name Alternate function name (mapped on AF11) PA0 ETH_MII_CRS PA1 ETH_MII_RX_CLK/ETH_RMII_REF_CLK PA2 ETH_MDIO PA3 ETH_MII_COL PA7 ETH_MII_RX_DV/ETH_RMII_CRS_DV PA9 ETH_TX_ER PB0 ETH_MII_RXD2 PB1 ETH_MII_RXD3 PB2 ETH_TX_ER PB5 ETH_PPS_OUT PB8 ETH_MII_TXD3 PB10 ETH_MII_RX_ER PB11 ETH_MII_TX_EN/ETH_RMII_TX_EN PB12 ETH_MII_TXD0/ETH_RMII_TXD0 PB13 ETH_MII_TXD1/ETH_RMII_TXD1 PC1 ETH_MDC PC2 ETH_MII_TXD2 PC3 ETH_MII_TX_CLK PC4 ETH_MII_RXD0/ETH_RMII_RXD0 PC5 ETH_MII_RXD1/ETH_RMII_RXD1 PE2 ETH_MII_TXD3 PG8 ETH_PPS_OUT PG11 ETH_MII_TX_EN/ETH_RMII_TX_EN DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 491. Ethernet peripheral pins (continued) Pin name Alternate function name (mapped on AF11) PG12 ETH_MII_TXD1/ETH_RMII_TXD1 PG13 ETH_MII_TXD0/ETH_RMII_TXD0 PG14 ETH_MII_TXD1/ETH_RMII_TXD1 PH2 ETH_MII_CRS PH3 ETH_MII_COL PH6 ETH_MII_RXD2 PH7 ETH_MII_RXD3 PI10 ETH_MII_RX_ER PI12 ETH_TX_ER Table 492. Ethernet internal input/output signals Signal name Signal type Description eth_hclk Digital input eth_sbd_intr_it Digital output Main Ethernet interrupt lpi_intr_o Digital output Sideband signal generated when the transmitter or receiver enters or exits the LPI state. pmt_intr_o Digital output Sideband signal generated when a valid remote wakeup packet is received eth_mii_tx_clk Digital input MII Tx kernel clock eth_mii_rx_clk Digital input MII Rx kernel clock eth_rmii_ref_clk Digital input RMII reference kernel clock AHB clock DocID029587 Rev 3 2675/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.4 RM0433 Ethernet architecture The Ethernet peripheral is composed of 4 main functional modules: • The control and status register module (CSR) that controls the registers access through AHB 32-bit slave interface • The direct memory access interface (DMA) This is the logical DMA module with one physical channel for reception and 1 for transmission. It controls the data transfers between MAC and system memory through the AMBA AHB 32-bit master interface. • The media access control module (MAC) in charge of implementing the Ethernet protocol • The mac transaction layer (MTL) in charge of controlling the data flow between application and MAC. A protocol adaption module is added to support the RMII PHY Media Independent Interfaces. Figure 768. Ethernet high-level block diagram (7+(51(70$& ELW$+% 6ODYH '0$ 7[ .%7[ ),)2 &RQWURO 0$& 7[ '0$ 5[ .%5[ ),)2 &RQWURO 0$& 5[ '0$ 07/ HWKBPLLBW[BFON 0,, 50,, 6HOHFW '0$$UELWUHU ELW$+% 0DVWHU HWKBKFON 3+<,) HWKBUPLLBUHIBFON HWKBPLLBU[BFON 0$& &56 HWKBVEGBLQWUBLW OSLBLQWUBR SPWBLQWUBR 06Y9 1. For a definition of the internal signals, refer to Table 492. 2. Refer to RCC chapter "Clock distribution for Ethernet" for a detailed description of the Ethernet clock architecture. 2676/3178 DocID029587 Rev 3 RM0433 58.4.1 Ethernet (ETH): media access control (MAC) with DMA controller DMA controller The DMA has independent Transmit (Tx) and Receive (Rx) engines. The Tx engine transfers data from the system memory to the MAC Transaction Layer (MTL), whereas the Rx engine transfers data from the device port (PHY) to the system memory. The controller uses descriptors to efficiently move data from source to destination with minimal application CPU intervention. The DMA is designed for packet-oriented data transfers such as packets in Ethernet. The controller can be programmed to interrupt the application CPU for situations such as Packet Transmit and Receive Transfer completion, and other normal or error conditions. DMA data structures The DMA and the application communicate through the following two data structures: • Control and Status registers (CSR) • Descriptor lists and data buffers The DMA transfers the data packets received by the MAC to the Rx buffer in system memory and Tx data packets from the Tx buffer in the system memory. The descriptors that reside in the system memory contain the pointers to these buffers. The base address of each list is written to the respective Tx and Rx registers: Channel Tx descriptor list address register (ETH_DMACTxDLAR)) and Channel Rx descriptor list address register (ETH_DMACRxDLAR)). The descriptor list is forward linked and the next descriptor is always considered at a fixed offset to the current one. The number of descriptors in the list is programmed in the respective Tx/Rx, Channel Tx descriptor ring length register (ETH_DMACTxRLR) and Channel Rx descriptor ring length register (ETH_DMACRxRLR)). Once the DMA processes the last descriptor in the list, it automatically jumps back to the descriptor in the List address register to create a descriptor ring. The descriptor lists reside in the physical memory address space of the application. Each descriptor can point to a maximum of two buffers. This enables two buffers to be used and physically addressed, rather than contiguous buffers in memory. A data buffer resides in the application physical memory space and consists of an entire packet or part of a packet, but cannot exceed a single packet. Buffers contain only data. The buffer status is saved in the descriptor. Data chaining refers to packets that span multiple data buffers. However, a single descriptor cannot span multiple packets. The DMA skips to the data buffer of next packet when EOP is detected. Descriptors are specified in Section 58.10: Descriptors. DMA arbitration The DMA module incorporates an arbiter that performs the arbitration between the Tx and Rx channels accesses from the AHB master interface. The following two types of arbitrations are supported and can be selected through DMA mode register (ETH_DMAMR): • Round-robin arbitration: the arbiter allocates the data bus between Rx and Tx in ratio set by Bits [14:12] of ETH_DMAMR. • Fixed-priority arbitration: by default Rx DMA always gets priority over Tx DMA for data access. Setting bit 11 of ETH_DMAMR register gives priority to the Tx DMA. DocID029587 Rev 3 2677/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 DMA transmission in default mode The Tx DMA engine in default mode proceeds as follows: 1. The application sets up the Transmit descriptor (TDES0–TDES3) and sets the Own bit (TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Packet data. 2. The application shifts the Descriptor tail pointer offset value of the Transmit channel. 3. The DMA fetches the descriptor from the application memory. 4. If the DMA detects one of the following conditions, the transmission from that channel is suspended, bit 2 and 16 of the corresponding DMA channel Status register are set, and the Tx engine proceeds to step 11: – The descriptor is flagged as owned by the application (TDES3 [31] = 0). – The descriptor tail pointer is equal to the current descriptor pointer in Ring Descriptor list mode. – An error condition occurs. 5. If the acquired descriptor is flagged as owned by the DMA (TDES3[31] = 1), the DMA decodes the Transmit Data Buffer address from the acquired descriptor. 6. The DMA fetches the Transmit data from the system memory and transfers the data to the MTL for transmission. 7. If an Ethernet packet is stored over data buffers in multiple descriptors, the DMA closes the intermediate descriptor and fetches the next descriptor. Steps 3 through 7 are repeated until the end-of-Ethernet-packet data is transferred to the MTL. 8. When packet transmission is complete, if IEEE 1588 timestamp feature was enabled for the packet (as indicated in the Tx status), the timestamp value obtained from MTL is written to the Tx descriptor (TDES0 and TDES1) that contains the EOP buffer. The status information is written to this Tx descriptor (TDES3). The application now owns this descriptor because the Own bit is cleared during this step. If the timestamp feature is disabled for this packet, the DMA does not alter TDES0 and TDES1 contents. 9. Bit 0 of Channel status register (ETH_DMACSR)) is set after completing transmission of a packet that has Interrupt on Completion (TDES2[31]) set in its Last Descriptor. The DMA engine returns to step 3. 10. In the Suspend state, the DMA tries to acquire the descriptor again (and thereby return to step 3). A poll demand command is triggered by writing any value to the Channel Tx descriptor tail pointer register (ETH_DMACTxDTPR) when it receives a Transmit Poll demand and the Underflow Interrupt Status bit is cleared. If the application stopped the DMA by clearing Bit 0 of Transmit control register of corresponding DMA channel, the DMA enters the Stop state. 2678/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Figure 769. DMA transmission flow (standard mode) 6WDUW7['0$ 6WDUW 6WDUW7['0$ 5H IHWFKQH[W GHVFULSWRUIURP 7[4XHXH 1R 2ZQELWVHW" represented in binary. For example, if the required correction value is -5 ns, then the programmed value must be 0xBB9A_C9FB. – When TSCTRLSSR bit in ETH_MACTSCR register is reset, the accuracy is of ~0.466 ns: it is represented by setting bit 31 to 1 and bits 30:0 containing 2^31 represented in binary. Egress correction In the Transmit side the timestamp captured at the internal snapshot point is corrected for latency and synchronization by adding the correction value (Egress correction value) programmed in the Egress Correction register. The value that needs to be programmed in the egress correction register is calculated as follows: 1. The timestamp correction because of synchronization is compensated by adding EGRESS_SYNC_CORR to the synchronized timestamp value as follows: When Enable one step timestamp feature is selected, EGRESS_SYNC_CORR = (1*PTP_CLK_PER + 4*TX_CLK_PER) Otherwise, EGRESS_SYNC_CORR = -(2*PTP_CLK_PER) 2. The egress latency correction between the recommended capture point and the internal timestamp snapshot point is obtained by adding the latency value (EGRESS_LATENCY) to the captured timestamp as follows: Egress Correction = EGRESS_SYNC_CORR + EGRESS_LATENCY 3. Egress correction is performed by programming the TSEC field in the MAC Timestamp Egress correction register. The egress correction can be positive or negative. It is expressed in nanoseconds. Negative values are represented in complement form as follows: – When TSCTRLSSR bit in Timestamp control Register (ETH_MACTSCR) is set, the accuracy is of 1 ns. If the correction is positive, it is represented by setting bit 31 to 0 and bits 30:0 containing represented in binary. The value must not exceed 0x 3B9A_C9FF. If the correction is negative, it is represented by setting bit 31 to 1 and bits 30:0 containing 10^9 - represented in binary. For example, if the required correction value is -5 ns, then the programmed value should be 0xBB9A_C9FB. – When TSCTRLSSR bit in Timestamp control Register (ETH_MACTSCR) is reset, the accuracy is of ~0.466 ns. If the correction is positive, it is represented by setting bit 31 to 0 and bits 30:0 containing represented in binary. The maximum value is 0x7FFF_FFFF. If the correction is negative, it is represented by setting bit 31 to 1 and bits 30:0 containing 2^31 - represented in binary. DocID029587 Rev 3 2709/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 One-step timestamp The MAC supports the one-step timestamp feature: It identifies the offset in the packet and inserts the timestamp received from the application at that offset. You can enable the one-step timestamp feature for a packet by setting bit 20 (OSTC) in ATI Control Word. The inserted timestamp consists of the 64-bit TSSL and TSSH received from the application. The one-step timestamp feature is supported only for the PTP over Ethernet packets. It is not supported for PTP over IPv4/IPv6 packets. PTP offload function This feature enables the automatic generation of specific PTP packets to be performed, when the MAC operates as a specific node in the PTP network. These packets can be generated periodically or triggered by the host software. In other modes, this feature can parse the incoming PTP packets on the receiver, and automatically generate and respond to the required PTP packets. It helps to offload certain PTP node functions with better accuracy and lower response latency. Depending on the programmed mode, the MAC generates PTP Ethernet messages periodically or from the application, or based on reception of a particular PTP message. Table 502 indicates the PTP message generation criteria. Table 502. PTP message generation criteria Programming SNAPTYPSEL TSMSTRENA TSEVNTENA 00 0 1 00 01 2710/3178 1 0 1 1 Mode Criteria for generation of PTP messages PTP message type generated Ordinary or Boundary Slave SYNC message reception Delay_Req Periodic or on trigger from application SYNC Delay_Req message reception Delay_Resp Periodic or on trigger from application Pdelay_Req Pdelay_Req message reception Pdelay_Resp SYNC message reception Delay_Req Ordinary or Boundary Master Transparent Slave DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 502. PTP message generation criteria (continued) Programming Mode SNAPTYPSEL TSMSTRENA 01 TSEVNTENA 1 11 X 1 X Transparent Master Peer-to-Peer Transparent Criteria for generation of PTP messages PTP message type generated Periodic or on trigger from application Pdelay_Req Pdelay_Req message reception Pdelay_Resp Periodic or on trigger from application SYNC Delay_Req message reception Delay_Resp Periodic or on trigger from application Pdelay_Req Pdelay_Req message reception Pdelay_Resp All other programming combinations are invalid for PTP Offload feature. The PTP offload feature is configured through PTP Offload control register (ETH_MACPOCR) register. 80 bits-PTP node identity is given in the three following registers: PTP Source Port Identity 0 Register (ETH_MACSPI0R), PTP Source port identity 1 register (ETH_MACSPI1R) and PTP Source port identity 2 register (ETH_MACSPI2R). 58.5.5 IPv4 ARP offload The MAC supports the Address Recognition Protocol (ARP) Offload for IPv4 packets. This feature allows to process the IPv4 ARP request packet in the receive path and to generate the corresponding ARP response packet in the transmit path. The MAC generates the ARP reply packets for appropriate ARP request packets. ARP packets for IPv4 are L2 layer packets with Length/Type of 0x0806. The ARP offloading sequence is as follows: 1. The MAC receiver gets an ARP request if the request Target Protocol Address matches the IPv4 address programmed in the MAC L3 register. 2. The MAC generates an ARP reply packet. 3. The MAC copies the Sender Hardware Address field in the ARP request to the following fields: – DA field of the Ethernet packet header – Target Hardware Address field of the ARP reply packet DocID029587 Rev 3 2711/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.5.6 RM0433 4. The MAC copies the Sender Protocol Address field in the ARP request to the Target Protocol Address field in the ARP reply packet. 5. The MAC places its MAC address in the following fields: – SA field of the Ethernet packet header – Sender Hardware Address field of the ARP reply packet 6. The MAC copies the Target Protocol Address field in the ARP request to the Sender Protocol Address field in the ARP reply packet. 7. The MAC sets the opcode field in ARP reply packet to 2 indicating ARP reply. 8. The MAC recalculates the CRC and performs padding for the generated ARP reply packet. 9. The MAC transmitter sends the ARP reply TCP segmentation offload The MAC supports the TCP segmentation offload (TSO) feature in which the DMA splits a large TCP packet into multiple small packets and passes these packets to the MTL as shown in Figure 778. This feature is enabled by programming the TSE bit of corresponding ETH_DMACCR register (see Channel control register (ETH_DMACCR)). It is only supported when the MAC operates in full-duplex mode. For detailed programming steps, refer to Section 58.9.10: Programming guidelines for TSO. Figure 778. TCP segmentation offload overview 7&3 SDFNHW 76' HQJLQH 6HJ1 6HJ 6HJ 07/7[ TXHXH '0$7[ *0,, &KDQQHO 06Y9 2712/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Enabling the TSO feature To enable segmentation for a packet, the application must set the TSE bit of TDES3 of first normal descriptor (see Section 58.10.3: Transmit descriptor). The application must program the length of the TCP packet payload in TDES3[17:0] and the TCP header in TDES3[22:19]. The maximum length of TCP packet payload that can be segmented is 256 Kbytes. The header of the packet including Ethernet header, L3 header and L4 header should be provided in Buffer1 of the first normal descriptor of the TSO packet. Only buffer 1 of the first normal descriptor of a packet enabled for TSO is taken as the buffer containing the header. The TCP payload can begin from buffer 2 of the first normal descriptor and continue to buffer1 and buffer 2 of second normal descriptor and subsequent descriptors. The TCP payload may span across multiple buffers and multiple descriptors. The size of buffers containing the TCP payload should add up to be equal to the TCP payload length provided in TDES3[17:0] of the first normal descriptor. The MAC always calculates and appends CRC and inserts Padding (if required) for all packets segmented by the DMA. If the TSE bit of TDES3 is enabled, the CRC PAD Control (CPC) field of TDES3 is reserved. To determine the size of a TCP packet after segmentation, the DMA uses the Maximum Segment Size (MSS) provided by the application through context descriptor. The DMA segments only those packets which have payload size greater than MSS. The application must provide the MSS by either programming the MSS value in ETH_DMACCR (see Channel control register (ETH_DMACCR)) or by providing a context descriptor. The DMA uses the last programmed value of MSS or the last MSS value provided through context (whichever is provided later). The header length plus the MSS size (which is equal to the size of each TCP segment) should not exceed 16383 bytes otherwise the MAC transmitter truncates the packet after 16383 bytes causing a CRC error. The header length plus MSS size plus programmed PBL value in ETH_DMACTxCR register (see Channel transmit control register (ETH_DMACTxCR)) should be lesser than the Tx queue size programmed in TQS field of ETH_MTLTxQOMR register (see Tx queue operating mode Register (ETH_MTLTxQOMR)). A MSS plus header equal to half the programmed Tx queue size is recommended. If the TCP packet has a VLAN tag, then the same tag is used for all the segments irrespective of the VLAN tag type provided (C-VLAN or S-VLAN). The VLAN tag insert/replace control bits are used for all segments. If the Double VLAN feature is selected, then the DMA passes both tags for all segments irrespective of the VLAN tag types provided (C-VLAN or S-VLAN). The VLAN tag Insert/Replace control bits for both tags is applicable to all segments. If the Double VLAN feature is not selected, then the application must not set the TSE bit in TDES3 for a TCP/IP packet with two tags. The DMA behavior in this scenario is unpredictable. DocID029587 Rev 3 2713/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 TCP/IP header fields While segmenting a TCP packet, the DMA automatically updates the TCP/IP header fields. Table 503 describes how the TCP and IP headers are updated. Table 503. TSO: TCP and IP header fields Packet sequence TCP header 1. 2. First packet 3. 1. Subsequent packets 2. 3. 1. 2. Last packet 2714/3178 3. IP header The sequence number is not updated. The value provided in the header is used. If set, the FIN and PSH flags are cleared. The TCP checksum is calculated again. IPv4 Header – Total Length = MSS + TCP Header Length + IP Header Length – Identification field is not modified. It is sent as per the header provided by the software. – IPv4 Header Checksum is recalculated. IPv6 Header – Payload Length = MSS + TCP Header Length + IP Extension Header Length The sequence number is updated. The MSS value is added to the sequence number value of previous segment. If set, the FIN and PSH flags are cleared. The TCP checksum is calculated again. IPv4 Header – Total Length = MSS + TCP Header Length + IP Header Length – Identification field = Previous Identification Field + 1 – IPv4 Header Checksum is recalculated IPv6 Header – Payload Length = MSS + TCP Header Length + IP Extension Header Length The sequence number is updated. The MSS value is added to the sequence number value of previous segment. If FIN and PSH flags were set in original header, these flags are set. The TCP checksum is calculated again. DocID029587 Rev 3 IPv4 Header – Total Length = Remaining Payload + TCP Header Length + IP Header Length – Identification Field = Previous Identification Field + 1 – IPv4 header Checksum is recalculated IPv6 Header – Payload Length = Remaining Payload Length + TCP Header Length + IP Extension Header Length RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Header and payload fields of segmented packets After segmentation, the split packets use the same header as the parent TCP packet for header fields other than the ones described in Table 503: TSO: TCP and IP header fields. Figure 779: Header and payload fields of segmented packets shows how same header is used for the header fields of segmented packets. The application must create the header in Buffer 1 of the first descriptor of the packet to be segmented and provide the header length in TDES2 of the first descriptor (FD = 1). When the FD bit is set, the DMA reads the header from the header buffer to which the TDES0 is pointing. Buffer 2 of the first descriptor can be used for payload and TDES0 and TDES1 of subsequent descriptors. For subsequent descriptors (FD = 0), the address to which the TDES0 and TDES1 are pointing is treated as payload buffer address of the same packet. Figure 779. Header and payload fields of segmented packets +HDGHU + 6LQJOHKHDGHU LQ7[EXIIHU 7&3SD\ORDG 3 + + 3 3 3 + 3 + 39 + 6HJPHQWHGSD\RDG LQ7[EXIIHU 39 06Y9 Context descriptor sequence The context descriptor can provide the maximum segment size (MSS) value for segmentation. The application must provide the context descriptor before the normal descriptor to be used for the corresponding TCP packet. If the application needs to provide a new MSS, it must create the context descriptor in the descriptor list before the first normal descriptor of the packet to be segmented with the new MSS value. The MSS value in the context descriptor is valid only if the TCMSSV bit of TDES3 in context descriptor is set and the OSTC bit is reset (refer to Section 58.10.3: Transmit descriptor). When the application provides a context descriptor with a valid MSS value, the DMA internally stores the MSS value and uses this value for all subsequent packets for which the TSO is enabled through the TSE bit of TDES3 normal descriptor. DocID029587 Rev 3 2715/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 If the application places a context descriptor in the middle of a packet (between the first and last descriptors of a packet), the DMA does the following: 1. The DMA ignores the context and closes the descriptor. 2. The DMA indicates the error in descriptor status. 3. The DMA generates an interrupt if the CDEE bit is set in the Interrupt enable register corresponding to a DMA channel (see Channel interrupt enable register (ETH_DMACIER)). The application can read the interrupt status through CDE bit of Status register corresponding to a DMA channel (see Channel status register (ETH_DMACSR)). 58.5.7 Loopback The MAC supports the Loopback of transmitted packets to its receiver. By default, the MAC Loopback function is disabled, but it can be enabled by programming the LM bit of the Operating mode configuration register (ETH_MACCR) register. The Loopback function is available for all PHY interfaces. The data is always looped back on the MII interface irrespective of which PHY interface is selected. 58.5.8 Flow control This section describes the flow control for Transmit and Receive paths. Transmit flow control The Transmit Flow Control is enabled when TFE bit is set in Tx Queue flow control register (ETH_MACQTxFCR). Flow control trigger The Transmit Flow Control involves transmitting Pause packets in full-duplex mode and backpressure in half-duplex mode to control the flow of packets from the remote end. The application can request the MAC to send a Pause packet or initiate backpressure by using setting the FCB bit in the corresponding Tx Queue flow control register (ETH_MACQTxFCR). Flow control in full-duplex mode: pause packets control In full-duplex mode, the MAC uses IEEE 802.3x Pause packets for flow control. Table 504 describes the fields of a Pause packet. Table 504. Pause packet fields 2716/3178 Field Description DA Contains the special multicast address SA Contains the MAC address 0 Type Contains 8808 MAC Control opcode Contains 0001 for IEEE 802.3x Pause Control packets; 0101 for PFC packets PT Contains Pause time specified in the PT field of the Tx Queue flow control register (ETH_MACQTxFCR) DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller When the FCB bit is set, the MAC generates and transmits a single Pause packet. If the FCB bit is set again after the Pause packet transmission is complete, the MAC sends another Pause packet irrespective of whether the pause time is complete or not. To extend the pause or terminate the pause prior to the time specified in the previously-transmitted Pause packet, the application should program the Pause Time register with appropriate value and then again set the FCB bit. Flow control in half-duplex mode In half-duplex mode, the MAC uses the deferral mechanism for the flow control (backpressure). When the application requests to stop receiving packets, the MAC sends a JAM pattern of 32 bytes when it senses a packet reception, provided the transmit flow control is enabled. This results in a collision and the remote station backs off. If the application requests a packet to be transmitted, it is scheduled and transmitted even when the backpressure is activated. If the backpressure is kept activated for a long time (and more than 16 consecutive collision events occur), the remote stations abort the transmission because of excessive collisions. Table 505 describes the flow control in the Tx path based on the setting of the following bits: • EHFC bit of Rx queue operating mode register (ETH_MTLRxQOMR) • TFE bit of Tx Queue flow control register (ETH_MACQTxFCR) • DM bit of Operating mode configuration register (ETH_MACCR) Flow control is similar for all queues. Table 505. Tx MAC flow control EFC TFE DM Description x 0 x The MAC transmitter does not perform the flow control or backpressure operation. 0 1 0 The MAC transmitter performs backpressure when Bit 0 of Tx Queue flow control register (ETH_MACQTxFCR) is set. 1 1 0 The MAC transmitter performs backpressure when Bit 0 of Tx Queue flow control register (ETH_MACQTxFCR) is set. In addition, the MAC Tx performs backpressure when Rx queue level crosses the threshold set by Bits[10:8] of Rx queue operating mode register (ETH_MTLRxQOMR). 0 1 1 The MAC transmitter sends the Pause packet when Bit 0 of Tx Queue flow control register (ETH_MACQTxFCR) is set. 1 The MAC transmitter sends the Pause packet when Bit 0 of Tx Queue flow control register (ETH_MACQTxFCR) is set. In addition, the MAC Tx sends a Pause packet when Rx queue level crosses the threshold set by Bits[10:8] of Rx queue operating mode register (ETH_MTLRxQOMR). 1 1 Receive flow control In the Receive path, the flow control is functional only in full-duplex mode. If any Pause packet is received in half-duplex mode, the packet is considered as a normal control packet. DocID029587 Rev 3 2717/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 You can enable the Pause flow control by setting the RFE bit in the Rx flow control register (ETH_MACRxFCR). Table 506 describes the flow control in the Rx path based on the setting of the following bits: • RFE bit of Rx flow control register (ETH_MACRxFCR) • DM bit of Operating mode configuration register (ETH_MACCR) Table 506. Rx MAC Flow Control RFE DM Description 0 x The MAC receiver does not detect the received Pause packets. 1 0 The MAC receiver does not detect the received Pause packets but recognizes such packets as Control packets. 1 1 The MAC receiver detects or processes the Pause packets and responds to such packets by stopping the MAC transmitter. The following sequence describes the Rx flow control: 58.5.9 1. The MAC checks the destination address of the received Pause packet for either multicast or unicast destination address. 2. The MAC decodes the Type (0x8808) and Opcode (0x0001: Pause packet) fields of the received packet. The Pause time (for Pause packet) is captured to determine the time for which transmitter needs to be blocked. 3. If the byte count of the status indicates 64 bytes and there is no CRC error, the MAC pauses the transmission of any data packet for the duration of the decoded Pause Time value multiplied by the slot time (64 byte times). Checksum offload engine Communication protocols such as TCP and UDP implement checksum fields, which help determine the integrity of data transmitted over a network. The most widespread use of Ethernet is to encapsulate TCP and UDP over IP datagrams. The MAC has a Checksum Offload Engine (COE) to support checksum calculation and insertion in the Transmit path, as well as error detection in the Receive path. Transmit checksum offload engine The COE module supports two types of checksum calculation and insertion. The checksum engine can be controlled for each packet by setting the CIC bits (TDES3 bits[17:16]). Note: The checksum for TCP, UDP, or ICMP is calculated over a complete packet, and then inserted into its corresponding header field. Because of this requirement the Tx FIFO automatically operates in the store-and-forward mode even if the MAC is configured for Threshold (cut-through) mode. IP header checksum engine In IPv4 datagrams, the integrity of the header fields is indicated by the 16-bit Header Checksum field (the eleventh and twelfth bytes of the IPv4 datagram). The COE detects an IPv4 datagram when the Type field of Ethernet packet has the value 0x0800 and the Version field of IP datagram has the value 0x4. The checksum field of the input packet is ignored during calculation and replaced with the calculated value. 2718/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller IPv6 headers do not have a checksum field. Therefore, the COE does not modify the IPv6 header fields. The result of this IP header checksum calculation is indicated by the IP Header Error status it in the Transmit status (bit 0 in Table 520: TDES3 normal descriptor (write-back format)). TCP/UDP/ICMP checksum engine The TCP/UDP/ICMP Checksum Engine processes the IPv4 or IPv6 header (including extension headers) and determines whether the encapsulated payload is TCP, UDP, or ICMP. The checksum is calculated for the TCP, UDP, or ICMP payload and inserted into its corresponding field in the header. The Tx COE can work in the following two modes: Note: • The TCP, UDP, or ICMPv6 pseudo-header is not included in the checksum calculation and is assumed to be present in the Checksum field of the input packet. This engine includes the Checksum field in the checksum calculation, and then replaces the Checksum field with the final calculated checksum. • The engine ignores the Checksum field, includes the TCP, UDP, or ICMPv6 pseudoheader data into the checksum calculation, and overwrites the checksum field with the final calculated value. For ICMP-over-IPv4 packets, the Checksum field in the ICMP packet must always be 0x0000 in both modes, because pseudo-headers are not defined for such packets. If it does not equal 0x0000, an incorrect checksum may be inserted into the packet. The result of this operation is indicated by the Payload Checksum Error status bit in the Transmit Status vector (bit 12 in Table 520: TDES3 normal descriptor (write-back format)). This engine sets the Payload Checksum Error status bit when it detects that the packet has been forwarded to the MAC Transmitter engine in the store-and-forward mode without the end of packet (EOP) being written to the FIFO, or when the packet ends before the number of bytes indicated by the Payload Length field in the IP Header is received. When the packet is longer than the indicated payload length, the COE ignores them as stuff bytes, and no error is reported. When this engine detects the first type of error, it does not modify the TCP, UDP, or ICMP header. For the second error type, it still inserts the calculated checksum into the corresponding header field. Table 507 describes the functions supported by Transmit Checksum Offload engine based on the packet type. When the MAC does not insert the checksum, it is indicated as “No” in the table. DocID029587 Rev 3 2719/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 507. Transmit checksum offload engine functions for different packet types Hardware IP header checksum insertion Hardware TCP/UDP checksum insertion Non-IPv4 or IPv6 packet No No IPv4 with TCP, UDP, or ICMP Yes Yes IPv4 packet has IP options (IP header is longer than 20 bytes) Yes Yes Packet is an IPv4 fragment Yes No Packet type IPv6 packet with the following next header fields in main or extension headers: – Hop-by-hop options (in IPv6 main header) – Hop-by-hop options (in IPv6 extension header) – Destinations options – Routing (with segment left 0) – Routing (with segment left > 0) – TCP, UDP, or ICMP – Authentication – Any other next header field in main or extension headers – – – – – – – – Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable IPv4 packet has TCP header with Options fields – – – – – – – – Yes No Yes No No Yes Yes No Yes Yes IPv4 Tunnels: – IPv4 packet in an IPv4 tunnel – IPv6 packet in an IPv4 tunnel – Yes (IPv4 tunnel header) – Yes (IPv4 tunnel header) – No – No IPv6 Tunnels: – IPv4 packet in an IPv6 tunnel – IPv6 packet in an IPv6 tunnel – Not applicable – Not applicable – No – No IPv4 packet has 802.3ac tag (with C-VLAN tag or S-VLAN Tag when enabled). Yes Yes IPv6 packet has 802.3ac tag (with C-VLAN tag or S-VLAN Tag when enabled). Not applicable Yes IPv4 frames with security features (such as encapsulated security payload) Yes No IPv6 frames with security features (such as encapsulated security payload) Not applicable No 2720/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Receive checksum offload engine You can enable the Receive Checksum Offload Engine (Rx COE) by selecting the Enable Receive TCP/IP Checksum Check option and setting the IPC bit of Operating mode configuration register (ETH_MACCR). When this option is selected, both IPv4 and IPv6 packet in the received Ethernet packets are detected and processed for data integrity. The MAC receiver identifies IPv4 or IPv6 packets by checking for value 0x0800 or 0x86DD, respectively, in the Type field of the received Ethernet packet. This identification is applicable to single VLAN-tagged packets. It is also applicable to double VLAN-tagged packets when the Enable Double VLAN Processing option is selected and the EDVLP bit of the VLAN tag register (ETH_MACVTR) is set. The Rx COE calculates the IPv4 header checksums and checks that they match the received IPv4 header checksums. The result of this operation (pass or fail) is given to the RFC module for insertion into the receive status word. The IP Header Error bit is set for any mismatch between the indicated payload type (Ethernet Type field) and the IP header version, or when the received packet does not have enough bytes, as indicated by the Length field of the IPv4 header (or when fewer than 20 bytes are available in an IPv4 or IPv6 header). This engine also identifies a TCP, UDP, or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the TCP, UDP, or ICMP specifications. This engine includes the TCP, UDP, or ICMPv6 pseudoheader bytes for checksum calculation and checks whether the received checksum field matches the calculated value. The result of this operation is given as a Payload Checksum Error bit in the receive status word. This status bit is also set if the length of the TCP, UDP, or ICMP payload does not match the expected payload length given in the IP header. Table 508: Receive checksum offload engine functions for different packet types describes the functions supported by the Rx COE based on the packet type. When the payload of an IP packet is not processed (indicated as "No" in the table), the information (whether the checksum engine is bypassed or not) is given in the receive status. Note: The MAC does not append any payload checksum bytes to the received Ethernet packets. Table 508. Receive checksum offload engine functions for different packet types Hardware IP header checksum checking Hardware TCP/UDP/ICMP checksum checking Non-IPv4 or IPv6 No No IPv4 with TCP, UDP, or ICMP Yes Yes IPv4 header's protocol field contains a protocol other than TCP, UDP, or ICMP Yes No IPv4 packet has IP options (IP header is longer than 20 bytes) Yes Yes Packet is an IPv4 fragment Yes No Packet type DocID029587 Rev 3 2721/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 508. Receive checksum offload engine functions for different packet types (continued) Hardware IP header checksum checking Packet type IPv6 packet with the following next header fields in main or extension headers: – Hop-by-hop options (in IPv6 main header) – Hop-by-hop options (in IPv6 extension header) – Destinations options – Routing (with segment left 0) – Routing (with segment left > 0) – TCP, UDP, or ICMP – Any other next header field in main or extension headers – – – – – – – Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable IPv4 packet has TCP header with Options fields Hardware TCP/UDP/ICMP checksum checking – – – – – – – Yes No Yes Yes No Yes No Yes Yes IPv4 Tunnels: – IPv4 packet in an IPv4 tunnel – IPv6 packet in an IPv4 tunnel – Yes (IPv4 tunnel header) – Yes (IPv4 tunnel header) – No – No IPv6 Tunnels: – IPv4 packet in an IPv6 tunnel – IPv6 packet in an IPv6 tunnel – Not applicable – Not applicable – No – No IPv4 packet has 802.3ac tag (with C-VLAN Tag or S-VLAN Tag when enabled). Yes Yes IPv6 packet has 802.3ac tag (with C-VLAN Tag or S-VLAN Tag when enabled). Not applicable Yes IPv4 frames with security features (such as encapsulated security payload) Yes No IPv6 frames with security features (such as encapsulated security payload) Not applicable No 2722/3178 DocID029587 Rev 3 RM0433 58.5.10 Ethernet (ETH): media access control (MAC) with DMA controller MAC management counters The counters in the MAC Management Counters (MMC) module can be viewed as an extension of the register address space of the CSR module. The MMC module maintains a set of registers for gathering statistics on the received and transmitted packets. The register set includes a control register for controlling the behavior of the registers, two 32-bit registers containing interrupts generated (receive and transmit), and two 32-bit registers containing masks for the Interrupt register (receive and transmit). These registers are accessible from the Application through the AHB slave interface in the same way the CSR registers are accessed. The organization of these registers is shown in Section 58.11.4: Ethernet MAC and MMC registers. The MMC counters are free running. There is no separate enable for the counters to start. A particular MMC counter starts counting when corresponding packet is received or transmitted. In addition to control registers, two sets of registers are implemented: 58.5.11 • 6 registers used for collision, error and good packets counters • 4 registers to record LPI mode transition Interrupts generated by the MAC Interrupts can be generated from the MAC as a result of various events. These interrupt events are combined with the events in the DMA on the eth_sbd_intr_it signal. The MAC interrupts are of level type, that is, the interrupt remains asserted (high) until it is cleared by the application or software. The Interrupt status register (ETH_MACISR) describes the events that can cause an interrupt from the MAC. The MAC interrupts are enabled by default. Each event can be prevented from asserting the interrupt on the eth_sbd_intr_it signals by setting the corresponding mask bits in the Interrupt enable register (ETH_MACIER). The interrupt register bits only indicate the block from which the event is reported. You must read the corresponding status registers and other registers to clear the interrupt. 58.5.12 MAC and MMC register descriptions Refer to Section 58.11.4: Ethernet MAC and MMC registers. DocID029587 Rev 3 2723/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.6 RM0433 Ethernet functional description: PHY interfaces The Ethernet peripheral support several PHY interfaces. The root interface is the MII one. All other interfaces are derived from it as shown in Figure 780. Figure 780. Supported PHY interfaces 0$&7[ 50,, 3+<,) 6HOHFW 0$&5[ 0,, 0$& 06Y9 This section describes the SMA module used for PHY control and different PHY interfaces. It contains the following sections: 58.6.1 • Station management agent (SMA) • Media Independent Interface (MII) • Reduced media independent interface (RMII) Station management agent (SMA) The application can access the PHY registers through the station management agent (SMA) module. The SMA includes a two-wire station management interface (MIM). The SMA module supports accessing up to 32 PHYs. The application can address one of the 32 registers from any 32 PHYs. Only one register in one PHY can be addressed at a time. The application sends the control data to the PHY and receives status information from the PHY through the SMA module, as shown in Figure 781. 2724/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller 6700&8 -!# Figure 781. SMA Interface block 0'& 0',2 ([WHUQDO 3+< DLE SMA functional overview The MAC initiates the management write or read operation with respect to the MDC clock. The MDC clock is derived from the CSR clock. The division factor depends on the clock range setting in the MDIO address register (ETH_MACMDIOAR) register. The MDC clock is selected as follows: Table 509. MCD clock selection Selection CSR clock MDC clock 0000 60–100 MHz CSR clock/42 0001 100–150 MHz CSR clock/62 0010 20–35 MHz CSR clock/16 0011 35–60 MHz CSR clock/26 0100 150–250 MHz CSR clock/102 0101 250–300 MHz CSR clock/124 0110, 0111 Reserved - The data exchange between the MAC and the PHY is performed through mdi_i, mdo_o and mdo_oe signals. This signal group is passed through a three-state buffer and brought out as MDIO line connected to the PHY. The following figure shows the structure of a packet on the MDIO packet while Table 510 provides a detailed description of the packet fields. Figure 782. MDIO packet structure ,'/( 35($0%/( 67$57 23&2'( 3+<$''5 5(*$''5 7$ '$7$ 06Y9 DocID029587 Rev 3 2725/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 510. MDIO packet field description Field Description IDLE The MDIO line is three-state; there is no clock on ETH_MDC. PREAMBLE 32 continuous bits of value 1 START Start of packet is 2’01 OPCODE 2’b10 for Read and 2’b01 for Write PHY ADDR 5-bit address select for one of 32 PHYs REG ADDR Register address in the selected PHY TA Turnaround is 2’bZ0 for Read and 2’b10 for Write DATA Any 16-bit value. In a Write operation, the MAC drives MDIO. In a Read operation, the PHY drives it. MII management write operations When bit[3:2] are set to 01 and bit 0 to 1 in the MDIO address register (ETH_MACMDIOAR), the MAC CSR module transfers the PHY address, the register address in PHY, and the write data (MDIO data register (ETH_MACMDIODR)) to the SMA to initiate a Write operation into the PHY registers. At this point, the SMA module starts a Write operation on the MII Management Interface using the Management Packet Format specified in the MII specifications (as per IEEE 802.3-2002 specifications, Section 22.2.4.5). When the SMA module starts a Write operation, the write data packet is transmitted on the MDIO line. The MAC drives the MDIO line for complete duration of the packet. The Busy bit is set high until the write operation is complete. The CSR ignores the Write operations performed to the MDIO address register (ETH_MACMDIOAR) or the MDIO data register (ETH_MACMDIODR) during this period (the Busy bit is high). When the Write operation is complete, the SMA module indicates this to the CSR, and the CSR resets the Busy bit. The packet format for the Write operation is as follows: Figure 783. Write data packet ,'/( 35($0%/( 67$57 23&2'( 3+<$''5 5(*$''5 = $$$$$ 55555 7$ '$7$ ,'/( '''''' = 06Y9 2726/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller MII management read operation When bit[3:2] are set to 11 and bit 0 to 1 in the MDIO address register (ETH_MACMDIOAR), the MAC CSR module transfers the PHY address and the register address in PHY to the SMA to initiate a Read operation in the PHY registers. At this point, the SMA module starts a Read operation on the MII Management Interface using the Management Packet Format specified in the MII specifications (as per IEEE 802.3-2002 specifications, Section 22.2.4.5). When the SMA module starts a Read operation on the MDIO, the CSR ignores the Write operations to the MDIO address register (ETH_MACMDIOAR) or MDIO data register (ETH_MACMDIODR) register during this period (the Busy bit is high) and the transaction is completed without any error on the MCI interface. When the Read operation is complete, the SMA indicates this to the CSR. The CSR resets the Busy bit and updates the MDIO data register (ETH_MACMDIODR) with the data read from the PHY. The MAC drives the MDIO line for the complete duration of the frame except during the Data fields when the PHY is driving the MDIO line. For more information about the communication from the application to the PHYs, see the Reconciliation Sublayer and Media Independent Interface Specifications sections of the IEEE 802.3z, 1000BASE Ethernet. The packet format for the Read operation is as follows: Figure 784. Read data packet ,'/( 35($0%/( 67$57 23&2'( 3+<$''5 5(*$''5 = $$$$$ 55555 7$ '$7$ ,'/( = '''''' = 06Y9 DocID029587 Rev 3 2727/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.6.2 RM0433 Media Independent Interface (MII) The media-independent interface (MII) defines the interconnection between the MAC sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s. MII signals are given in Figure 785: Media independent interface (MII) signals. Figure 785. Media independent interface (MII) signals 7;B&/. 7;'> @ 670 0&8 0$& 7;B(1 5;B&/. 5;'> @ ([WHUQDO3+< 5;B(5 5;B'9 &56 &2/ 06Y 9 • TX_CLK: continuous clock that provides the timing reference for Tx data transfers. The nominal frequency is 2.5 MHz at 10 Mbit/s and 25 MHz at 100 Mbit/s. • RX_CLK: continuous clock that provides the timing reference for Rx data transfers. The nominal frequency is 2.5 MHz at 10 Mbit/s, 25 MHz at 100 Mbit/s. • TX_EN: transmission enable signal indicating that the MAC is presenting nibbles on the MII for transmission. It must be asserted synchronously (TX_CLK) with the first nibble of the preamble and must remain asserted while all nibbles to be transmitted are presented to the MII. • TXD[3:0]: transmit data. TXD is a bundle of 4 data signals driven synchronously by the MAC sub-layer and qualified (valid data) on the assertion of the TX_EN signal. TXD[0] is the least significant bit, TXD[3] is the most significant bit. While TX_EN is deasserted the transmit data must have no effect upon the PHY. • CRS: carrier sense. This signal is asserted by the PHY when either transmit or receive medium is non idle. It shall be deasserted by the PHY when both transmit and receive media are idle. The PHY must ensure that the CS signal remains asserted throughout the duration of a collision condition. This signal is not required to transition synchronously with respect to the Tx and Rx clocks. In full duplex mode the state of this signal is don’t care for the MAC sub-layer. 2728/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller • COL: collision detection signal This signal must be asserted by the PHY upon detection of a collision on the medium and must remain asserted while the collision condition persists. This signal is not required to transition synchronously with respect to the Tx and Rx clocks. In full-duplex mode the state of this signal is don’t care for the MAC sub-layer. • RXD[3:0]: reception data RXD is a bundle of 4 data signals driven synchronously by the PHY and qualified (valid data) on the assertion of the RX_DV signal. RXD[0] is the least significant bit, RXD[3] is the most significant bit. While RX_EN is deasserted and RX_ER is asserted, a specific RXD[3:0] value is used to transfer specific information from the PHY (see Table 511). • RX_DV: receive data valid This signal indicates that the PHY is presenting recovered and decoded nibbles on the MII for reception. It must be asserted synchronously (RX_CLK) with the first recovered nibble of the frame and must remain asserted through the final recovered nibble. It must be deasserted prior to the first clock cycle that follows the final nibble. In order to receive the frame correctly, the RX_DV signal must encompass the frame, starting no later than the SFD field. • RX_ER: receive error This signal must be asserted for one or more clock periods (RX_CLK) to indicate to the MAC sub-layer that an error was detected somewhere in the frame. This error condition must be qualified by RX_DV assertion as described in Table 511. Table 511. RX interface signal encoding 58.6.3 RX_DV RX_ERR RXD[3:0] Description 0 0 0000 through 1111 Normal inter-frame 0 1 0000 Normal inter-frame 0 1 0001 through 1101 0 1 1110 False carrier indication 0 1 1111 Reserved 1 0 0000 through 1111 Normal data reception 1 1 0000 through 1111 Data reception with errors Reserved Reduced media independent interface (RMII) The Reduced media independent interface (RMII) specification reduces the pin count between Ethernet PHYs and STM32 MCU . According to the IEEE 802.3u, an MII contains 16 pins for data and control. RMII specification reduces the pin count to 7. Part of the Ethernet peripheral, the RMII module is instantiated at the MAC output. This helps in translating the MII of the MAC into the RMII. The RMII block has the following characteristics: • Supports 10 Mbps and 100 Mbps operating rates. It does not support the 1000 Mbps operation. • Provides independent 2-bits wide Transmit and Receive paths by sourcing two clock references externally. DocID029587 Rev 3 2729/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 RMII block diagram Figure 786: RMII block diagram shows the position of the RMII block relative to the MAC and RMII PHY. The RMII block is placed in front of the MAC to translate the MII signals to RMII signals. Figure 786. RMII block diagram 50,,B&/. 0$& 7;'> @ 670 0&8 7;B(1 50,,%ORFN ([WHUQDO3+< 0,, 5;'> @ 5;B'9 06Y9 Transmit bit order Each nibble from the MII interface must be transmitted on the RMII interface di-bit at a time with the order of di-bit transmission shown in Figure 787: Transmission bit order. The lower order bits (D1 and D0) are transmitted first followed by higher order bits (D2 and D3). /6% ' /6% PLLBW[G> @ Figure 787. Transmission bit order 06% ' 'LELW VWUHDP ' ' PLLBW[G> @ 06% ' ' 1LEEOH VWUHDP 2730/3178 DocID029587 Rev 3 06Y9 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Receive bit order Each nibble is transmitted to the MII interface from the di-bit received from the RMII interface in the nibble transmission order shown in Figure 788: Receive bit order. The lower order bits (D0 and D1) are received first, followed by the higher order bits (D2 and D3). Figure 788. Receive bit order ' /6% PLLBU[G> @ /6% 06% ' 'LELW VWUHDP ' ' PLLBU[G> @ ' 06% ' 1LEEOH VWUHDP DocID029587 Rev 3 06Y9 2731/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.7 Ethernet low-power modes 58.7.1 Energy Efficient Ethernet RM0433 Energy Efficient Ethernet (EEE) is an operating mode that enables the MAC sub-layer along with a family of Physical layers to operate in Low-power Idle (LPI) mode. The EEE mode supports operations at 100 Mbps. The LPI mode allows power saving to be achieved by switching off some of the communication device functions when there is no data to be transmitted and received. The MAC controls whether the system should enter or exit the LPI mode and communicates this to the PHY interface. The EEE specifies the negotiation methods that the link partners can use to determine whether EEE is supported, and then select the set of parameters that are common to both devices. Note: The EEE feature is not supported when the MAC is configured to use the RMII single PHY interface. Even if the MAC supports multiple PHY interfaces, the EEE mode should be activate only when the MAC operates with the MII interface. The LPI mode is supported only in full-duplex mode. Transmit path functions In the Transmit path, the software must set the LPIEN bit of the LPI control status register (ETH_MACLCSR) to request the MAC to stop transmission and initiate the LPI protocol. To exit the PHY from the LPI state, the MAC performs the following tasks: 1. Stops transmitting the LPI pattern and starts transmitting the IDLE pattern. 2. Starts the LPI TW TIMER: The MAC cannot start the transmission until the wakeup time specified for the PHY expires. The auto-negotiated wakeup interval is programmed in the TWT field of the LPI control status register (ETH_MACLCSR). 3. Updates the LPI exit status (TLPIEX bit of the LPI control status register (ETH_MACLCSR)) and generates an interrupt. Refer to Section : Entering and exiting Tx LPI mode for programming guideline of LPI mode. Automatically entering/exiting LPI mode in Tx path The MAC transmitter can be programmed to enter/exit LPI mode automatically based on whether it is IDLE for a specific period of time or has a packet to transfer. These modes are enabled and controlled by LPI control status register (ETH_MACLCSR). When LPITXA (bit19) and LPITXEN (bit16) of LPI control status register (ETH_MACLCSR) are set, the MAC transmitter enters LPI IDLE state when the MAC transmit path (including the MTL layers and DMA layers) are idle. The MAC transmitter will exit the LPI IDLE state and clear the LPITXEN bit as soon as any of functions in the Tx path (DMA, MTL or MAC) becomes non-idle due to initiation of a packet transfer. In addition to the above, when Bit[20] (LPIATE) is also set, the MAC transmitter will enter LPI IDLE state only if the Transmit path remains in idle state (no activity) for the time period indicated by the value in LPI entry timer register (ETH_MACLETR). In this mode also, the MAC transmitter will exit the LPI IDLE state as soon as any of the functions becomes nonidle. However, the LPITXEN bit is not cleared but remains active so that re-entry to LPI IDLE state is possible without any software intervention when the MAC becomes idle again. 2732/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller When both LPIATE and LPITXA bits are cleared, you can directly control the entry and exit of LPI IDLE state by programming the LPITXEN bit. Receive path functions In the receive path, when the PHY receives the signals from the link partner to enter into the LPI state, the PHY goes in LPI mode and MAC updates the RLPIEN bit of the LPI control status register (ETH_MACLCSR) and immediately generates an interrupt. When the PHY receives signals from the link partner to exit the LPI state, the PHY goes out of the LPI mode and MAC updates the RLPIEX bit of the LPI control status register (ETH_MACLCSR). An interrupt is generated immediately. LPI Interrupt The MAC generates the LPI interrupt when the Tx or Rx side enters or exits the LPI state. The LPI interrupt can be cleared by reading the LPI control status register (ETH_MACLCSR). A sideband signal, lpi_intr_o, is generated together with the interrupt. This signal is used by the wakeup mechanism. It is ORed with pmt_intr_o signal (see Section : PMT interrupts) and tied to the EXTI peripheral (line 86). 58.7.2 Power management The power management (PMT) block supports the reception of network (remote) wakeup packets and magic packets. The PMT block generates interrupts for remote wakeup packets and magic packets that the MAC receives. When the power-down mode is enabled in the PMT block, the MAC drops all received packets and does not forward any packet to the RxFIFO or the application. The MAC comes out of the power-down mode only when a magic packet or a remote wakeup packet is received and the corresponding detection is enabled. The PMT block is available in the receive path of MAC. Both types of power management packet (remote wakeup packet and magic packet) can be selected. RWKPKTEN and MGKPKTEN bits of the PMT control status register (ETH_MACPCSR) can be set to generate power management events. The following are the PMT block registers: • PMT control status register (ETH_MACPCSR) • Remove wakeup packet filter register (ETH_MACRWKPFR) Remote wakeup packet detection When the MAC is in sleep mode and the remote wakeup bit is enabled in the PMT control status register (ETH_MACPCSR), the normal operation is resumed after a remote wakeup packet is received. Remote wakeup frame filter register The PMT block supports 16 programmable filters that allow support of different receive packet patterns. If the incoming packet passes the address filtering of Filter Command, and if Filter CRC-16 matches the CRC of the incoming pattern, the MAC identifies the packet as a wakeup packet. DocID029587 Rev 3 2733/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Remove wakeup packet filter register (ETH_MACRWKPFR) define the filtering management: • Filter Byte Mask: determines which bytes of the packet must be examined • Filter Offset: determines the offset from which the packet is to be examined • Filter CRC-16 The remote wakeup CRC block determines the CRC value that is compared with Filter CRC-16. The remote wakeup packet is checked only for length error, FCS error, dribble bit error, receive error and collision. In addition, the remote wakeup packet is checked to ensure that it is not a runt packet. Even if the remote wakeup packet is more than 512 bytes long, if the packet has a valid CRC value, it is considered valid. The remote wakeup packet detection is updated in the PMT Control and Status register for every remote wakeup packet received. A PMT interrupt to the application triggers a Read to the PMT Control and Status register to determine reception of a remote wakeup packet. Magic packet detection The magic packet is based on a method that uses the magic packet technology from Advanced Micro Device to power up the sleeping device on the network. The MAC receives a specific packet of information, called a magic packet, addressed to the node on the network. The MAC checks only those magic packets that are addressed to the MAC or a multicast address (including broadcast address) to determine whether these packets meet the wakeup requirements. The magic packets that pass the address filtering (unicast or multicast (including broadcast) address) are checked to determine whether they meet the remote wakeup packet data format of 6 bytes of all ones followed by a Unicast MAC Address (that matches the value in MAC Address 0) appearing 16 times. The application enables the magic packet wakeup by writing 1 to the MGKPKTEN bit of the PMT control status register (ETH_MACPCSR). The PMT block constantly monitors each packet addressed to the node for a specific magic packet pattern. Each packet received is checked for a 48’hFF_FF_FF_FF_FF_FF pattern following the destination and source address field. The PMT block then checks the packet for 16 repetitions of the MAC address without any breaks or interruptions. In case of a break in the 16 repetitions of the address, the PMT block again scans the 48’hFF_FF_FF_FF_FF_FF pattern in the incoming packet. The 16 repetitions can be anywhere in the packet, but must be preceded by the synchronization stream (48’hFF_FF_FF_FF_FF_FF). The device can also accept a multicast packet, as long as the 16 duplications of the MAC address are detected. If the number of repetitions of 8'hFF are more than 6, the PMT block checks for 16 repetitions of the MAC address without any breaks or interruptions, after the last 6 repetitions of 8'hFF. If the MAC address of a node is 48'h00_11_22_33_44_55, the MAC scans for the following data sequence: Destination Address Source Address ……………….. FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC The MAC checks the remote wakeup packet only for length error, FCS error, dribble bit error, receive or collision error. In addition, the remote wakeup packet is checked to ensure 2734/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller that it is not a runt packet. Even if the remote wakeup packet is more than 512 bytes long, if the packet has a valid CRC value, MAC considers it a valid packet. The magic packet detection is updated in the PMT control status register (ETH_MACPCSR) for the received magic packet. A PMT interrupt to the Application triggers a read to the PMT control status register (ETH_MACPCSR) to determine whether a magic packet has been received. PMT interrupts The PMT interrupt signal is asserted when a valid remote wakeup packet is received. When software resets the PWRDWN bit in Remove wakeup packet filter register (ETH_MACRWKPFR), the MAC comes out of the power-down mode. This event does not generate the PMT interrupt. As for EEE mode, a sideband signal, pmt_intr_o, is generated together with the wakeup interrupt. It is ORed with lpi_intr_o signal (see Section : LPI Interrupt) and tied to the EXTI peripheral (line 86). 58.7.3 Power-down and wakeup sequence The recommended Power-down and wakeup sequence is as follows. 1. Disable the Transmit DMA and wait for any previous packet transmissions to complete. These transmissions can be detected when Transmit Interrupt (bit 0 of the ETH_DMACSR register) is received. 2. Disable the MAC transmitter and MAC receiver by clearing the corresponding bits (0 and 1) in the MAC Configuration register (ETH_MACCR). 3. Wait until the Receive DMA empties all the packets from the Rx FIFO to system memory. This can be done by reading the corresponding Debug register bits in the DMA (ETH_DMADSR) and MTL (ETH_MTLTxQDR and ETH_MTLRxQDR). 4. Enable Power-down mode by appropriately configuring the PMT registers ETH_MACPCSR and ETH_MACRWKPFR. 5. Enable the MAC Receiver and enter Power-down mode. 6. When receiving a valid remote wakeup packet, the Ethernet peripheral asserts the pmt_intr_o signal and exits Power-down mode. 7. Read the PMT Status register to clear the interrupt, then enable the other modules in the system and resume normal operation. DocID029587 Rev 3 2735/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.8 RM0433 Ethernet interrupts The Ethernet peripheral generates a single interrupt signal (eth_sbd_intr_it). This signal can be raised as a result of various events. These events are captured in status registers and interrupt enables are provided for each source of interrupt such that the interrupt signal is asserted for an event only when the corresponding interrupt enable is set. The interrupt status and corresponding enable registers are organized in a hierarchical manner so that it is easier for software to traverse and identify the source of interrupt event quickly. When interrupt is asserted, the Interrupt status register (ETH_DMAISR) register is first level that indicates the major blocks for the interrupt event source. This register is readonly, and it contains bits corresponding to each DMA channel (TX & RX pair), the MTL, and the MAC. The software application must then read one (or more) of the following registers corresponding to the bits that are set: 58.8.1 • ETH_DMACSR: Channel Status (see Channel status register (ETH_DMACSR))) • ETH_MTLISR: Interrupt Status (see Interrupt status Register (ETH_MTLISR)) • ETH_MACISR: Interrupt Status (see Interrupt status register (ETH_MACISR)) DMA interrupts Interrupt registers description The ETH_DMACSR: Channel Status register (see Channel status register (ETH_DMACSR)) captures all the interrupt events of that TxDMA and RxDMA channel. The ETH_DMACIER: Channel Interrupt Enable register (see Channel interrupt enable register (ETH_DMACIER)) contains the corresponding enable bits for each of the interrupt event. There are two groups of interrupts in the DMA channel namely Normal and Abnormal interrupts.They are indicated by Bits[15:14] of ETH_DMACSR register respectively. The normal group is for events that happen during the normal transfer of packets (TI: transmit interrupt, RI: receive interrupt, TBU: Transmit buffer unavailable) while the abnormal interrupt events are for error events. Interrupts are not queued. If the same interrupt event occurs again before the driver responds to the previous one, no additional interrupts are generated. An interrupt is generated only once for multiple events. The driver must scan the Interrupt status register (ETH_DMAISR) for the cause of the interrupt and clear the source in the respective Status register. The interrupt is cleared only when all the bits of Interrupt status register (ETH_DMAISR) are cleared. Periodic scheduling of Transmit and Receive Interrupt It is not preferable to generate interrupts for every packet transferred by DMA (RI and TI) for system throughput performance reasons. The Ethernet peripheral gives the flexibility to schedule the interrupt at regular intervals using two methods: 2736/3178 1. Set Interrupt on Completion bit in Transmit descriptor (TDES2[31] in Table 515: TDES2 normal descriptor (read format)) once for every “required” number of packets to be transmitted. 2. Similarly, set the IOC (RDES3[30] inTable 528: RDES3 normal descriptor (read format)) bit only at some specific intervals of Receive descriptors. This way, whenever a received packet transfer to system memory is complete and any of the descriptors used for that packet transfer has the IOC bit set, only then the RI event is generated. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller In addition to above, an interrupt timer (ETH_DMACRxIWTR: Channel Rx Interrupt Watchdog Timer) is given for flexible control and periodic scheduling of Receive Interrupt. When this interrupt timer is programmed with a nonzero value, it gets activated as soon as the Rx DMA completes a transfer of a received packet to system memory without asserting the Receive Interrupt because the corresponding interrupt of completion IOC bit (RDES3[30] inTable 528: RDES3 normal descriptor (read format)) is not set. When this timer runs out as per the programmed value, RI bit is set and the interrupt is asserted if the corresponding RIE is enabled in ETH_DMACIER register (see Channel interrupt enable register (ETH_DMACIER)). The timer is stopped and cleared before it expires, if the RI is set for a packet transfer whose descriptor’s IOC was set. The timer is reactivated automatically after the next packet transfer is complete without the RI event being generated. Channel Transfer Complete Interrupt The Transmit Transfer complete interrupt (TI) and Receive Transfer complete interrupt (RI) is reflected in the Channel Status register (Channel status register (ETH_DMACSR)). The TI bit is set whenever the Tx DMA channel closes the descriptor in which the IOC bit is set (Interrupt On Completion - TDES2[31]). Similarly, the RI bit is set whenever the Rx DMA channel closes the descriptor with the LD bit set and, in any of the descriptors used for transferring that packet, IOC bit is set (Interrupt Enable on completion - RDES3[30])). The interrupt signal is asserted for the Transfer complete interrupts only when the corresponding interrupts are enabled in the channel interrupt enable register (Channel interrupt enable register (ETH_DMACIER)). The behavior of the RI/TI interrupts changes depending on the settings of INTM field (bit[17:16]) in the ETH_DMAMR register (DMA mode register (ETH_DMAMR)). Table 512 explains the behavior of the Transfer Complete interrupt. Table 512. Transfer complete interrupt behavior Interrupt Mode Behavior of TI/RI and interrupt signal INTM=0 The TI/RI status signals are set whenever the Transfer complete event is detected. These bits are cleared whenever the software driver writes 1 to these bits. The interrupt signal is asserted whenever the corresponding interrupts are also enabled in ETH_DMACIER register. INTM=1 The TI/RI is set as explained above. However, the interrupt is not asserted for any RI/TI event. INTM=2 The RI/TI status bits are set whenever the Transfer Complete event is detected and are reset whenever software driver clears them by writing 1. However, if another Transfer complete event is detected before it is cleared (serviced) by the software, then these status bits are automatically set again. However, the interrupt is not generated based on TI/RI. 58.8.2 MTL interrupts MTL interrupt events are combined with the events in the DMA to generate the interrupt signal. DocID029587 Rev 3 2737/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 The register Interrupt status Register (ETH_MTLISR) report the queue number responsible for the event. ETH_MTLQICSR: Queue Interrupt Control Status shall be read for event description. The MTL interrupts are enabled by default. Each event can be prevented from asserting the interrupt by setting the corresponding mask bits in the Interrupt status Register (ETH_MTLISR) register. MTL interrupt signal is driven by one of these events: 58.8.3 • Receive Queue Overflow Interrupt • Transmit Queue Underflow MAC Interrupts MAC interrupt events are combined with the events in the DMA to generate the interrupt signal. The MAC interrupts are of level type, that is, the interrupt remains asserted (high) until it is cleared by the application or software. The Interrupt status register (ETH_MACISR) describes the events that can cause an interrupt from the MAC. The MAC interrupts are enabled by default. Each event can be prevented from asserting the interrupt by setting the corresponding mask bits in the Interrupt status register (ETH_MACISR). The interrupt register bits only indicate the block from which the event is reported. You must read the corresponding status registers and other registers to clear the interrupt. MAC interrupt signal is driven by one of these events: Note: 2738/3178 • Receive Status Interrupt • Transmit Status Interrupt • Timestamp Interrupt Status • MMC Interrupt Status – MMC Receive Checksum Offload Interrupt Status – MMC Transmit Interrupt Status – MMC Receive Interrupt Status • LPI Interrupt Status • PMT Interrupt Status • PHY Interrupt Two sidebands signals are generated together with LPI and PMT interrupts: lpi_intr_o and pmt_intr_o. They are used for wakeup event detection at EXTI level. DocID029587 Rev 3 RM0433 58.9 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet programming model This chapter provides the instructions for initializing the DMA or MAC registers in the proper sequence. It contains the following sections: 58.9.1 • DMA initialization (see Section 58.9.1) • MTL initialization (see Section 58.9.2) • MAC initialization (see Section 58.9.3) • Performing Normal Receive and Transmit Operation (see Section 58.9.4) • Stopping and Starting Transmission (see Section 58.9.5) • Programming Guidelines for MII Link State Transitions (see Section 58.9.6) • Programming Guidelines for IEEE 1588 Timestamping (see Section 58.9.7) • Programming Guidelines for Energy Efficient Ethernet (see Section 58.9.8) • Programming Guidelines for flexible pulse-per-second (PPS) output (see Section 58.9.9) • Programming Guidelines for TSO (see Section 58.9.10) • Programming Guidelines for VLAN filtering on Receive (see Section 58.9.11) DMA initialization Complete the following steps to initialize the DMA: 1. Provide a software reset to reset all MAC internal registers and logic (bit 0 of DMA mode register (ETH_DMAMR)). 2. Wait for the completion of the reset process (poll bit 0 of the DMA mode register (ETH_DMAMR), which is cleared when the reset operation is completed). 3. Program the following fields to initialize the System bus mode register (ETH_DMASBMR): 4. Note: a) AAL b) Fixed burst or undefined burst c) Burst mode values in case of AHB bus interface. d) If fixed length value is enabled, select the maximum burst length possible on the AXI Bus (bits [7:1]) Create a transmit and a receive descriptor list. In addition, ensure that the receive descriptors are owned by the DMA (set bit 31 of TDES3/RDES3 descriptor). For more information on descriptors, refer to Section 58.10: Descriptors. Descriptor address from start to end of the ring should not cross the 4GB boundary. 5. Program ETH_DMACTxRLR and ETH_DMACRxRLR registers (see Channel Tx descriptor ring length register (ETH_DMACTxRLR) and Channel Rx descriptor ring length register (ETH_DMACRxRLR)). The programmed ring length must be at least 4. 6. Initialize receive and transmit descriptor list address with the base address of transmit and receive descriptor (Channel Tx descriptor list address register (ETH_DMACTxDLAR), Channel Rx descriptor list address register (ETH_DMACRxDLAR)). In addition, program the transmit and receive tail pointer registers that inform the DMA about the available descriptors (see Channel Tx DocID029587 Rev 3 2739/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 descriptor tail pointer register (ETH_DMACTxDTPR) and Channel Rx descriptor tail pointer register (ETH_DMACRxDTPR)). 58.9.2 7. Program ETH_DMACCR, ETH_DMACTxCR and ETH_DMACRxCR registers (see Channel control register (ETH_DMACCR) and Channel transmit control register (ETH_DMACTxCR)) to configure the parameters such as the maximum burst-length (PBL) initiated by the DMA, descriptor skip lengths, OSP for TxDMA, RBSZ for RxDMA. 8. Enable the interrupts by programming the ETH_DMACIER register (see Channel interrupt enable register (ETH_DMACIER)). 9. Start the Receive and Transmit DMAs by setting SR (bit 0) of Channel receive control register (ETH_DMACRxCR) and ST (bit 0) of the ETH_DMACTxCR (see Channel transmit control register (ETH_DMACTxCR)). MTL initialization Complete the following steps to initialize the MTL registers: 1. 2. 58.9.3 Program the following fields to initialize the operating mode in the ETH_MTLTxQOMR (see Tx queue operating mode Register (ETH_MTLTxQOMR)). a) Transmit Store And Forward (TSF) or Transmit Threshold Control (TTC) if the Threshold mode is used. b) Transmit Queue Enable (TXQEN) to value 2‘b10 to enable Transmit Queue 0. c) Transmit Queue Size (TQS). Program the following fields to initialize the operating mode in the ETH_MTLRxQOMR register (see Rx queue operating mode register (ETH_MTLRxQOMR)): a) Receive Store and Forward (RSF) or RTC if Threshold mode is used. b) Flow Control Activation and De-activation thresholds for MTL Receive FIFO (RFA and RFD). c) Error Packet and undersized good Packet forwarding enable (FEP and FUP). d) Receive Queue Size (RQS). MAC initialization The following MAC Initialization operations can be performed after DMA initialization. If the MAC initialization is complete before the DMA is configured, enable the MAC receiver (last step in the following sequence) only after the DMA is active. Otherwise, received frames fill the Rx FIFO and overflow. 1. Provide the MAC address registers: Address x low register (ETH_MACAxLR) and Address 0 high register (ETH_MACA0HR). If more than one MAC address is enabled in your configuration (up to 3 additional addresses), program the MAC addresses appropriately. 2. Program the following fields to set the appropriate filters for the incoming frames in the Packet filtering control register (ETH_MACPFR): 3. 2740/3178 a) Receive All. b) Promiscuous mode. c) Hash or Perfect Filter. d) Unicast, multicast, broadcast, and control frames filter settings. Program the following fields for proper flow control in the Tx Queue flow control register (ETH_MACQTxFCR): DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller a) Pause time and other Pause frame control bits. b) Transmit Flow control bits. c) Flow Control Busy. 4. Program the Interrupt enable register (ETH_MACIER) as required, if it is applicable for your configuration. 5. Program the appropriate fields in the Operating mode configuration register (ETH_MACCR) register. For example: Inter-packet gap while transmission and jabber disable. 6. 58.9.4 Set bit 0 and 1 in Operating mode configuration register (ETH_MACCR) register to start the MAC transmitter and receiver. Performing normal receive and transmit operation For normal operation, complete the following steps: 1. For normal transmit and receive interrupts, read the interrupt status. Then, poll the descriptor by reading the status of the descriptor owned by the Host (either transmit or receive). 2. Set the descriptors to appropriate values. Make sure that transmit and receive descriptors are owned by the DMA to resume the transmission and reception of data. 3. If the descriptors are not owned by the DMA (or no descriptor is available), the DMA goes into Suspend state. The transmission or reception can be resumed by freeing the descriptors and writing the ETH_DMACTxDTPR (see Channel Tx descriptor tail pointer register (ETH_DMACTxDTPR) and ETH_DMACRxDTPR (see Channel Rx descriptor tail pointer register (ETH_DMACRxDTPR)). 4. In debug mode, the values of the current host transmitter or receiver descriptor address pointer can be read in ETH_DMACCATxDR and ETH_DMACCARxDR registers (see Channel current application transmit descriptor register (ETH_DMACCATxDR) and Channel current application receive descriptor register (ETH_DMACCARxDR)). 5. In debug mode, the values of the current host transmit buffer address pointer and receive buffer address pointer can be read in ETH_DMACCATxDR and ETH_DMACCARxDR registers (see Channel current application transmit descriptor register (ETH_DMACCATxDR) and Channel current application receive descriptor register (ETH_DMACCARxDR)). DocID029587 Rev 3 2741/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.9.5 RM0433 Stopping and starting transmission Complete the following steps to pause the transmission for some time : 58.9.6 1. Disable the Transmit DMA (if applicable) by clearing Bit 0 (ST) of ETH_DMACTxCR register (see Channel transmit control register (ETH_DMACTxCR)). 2. Wait for any previous frame transmissions to complete. You can check this by reading the appropriate bits of ETH_MTLTxQDR register (TRCSTS is not 01 and TXQSTS=0). 3. Disable the MAC transmitter and MAC receiver by clearing Bit (RE) and Bit 1(TE) of the Operating mode configuration register (ETH_MACCR) Register. 4. Disable the Receive DMA (if applicable), after making sure that the data in the Rx FIFO is transferred to the system memory (by reading the appropriate bits of Tx queue debug Register (ETH_MTLTxQDR), PRXQ=0 and RXQSTS=00). 5. Make sure that both Tx queue and Rx queue are empty (TXQSTS is 0 in Tx queue debug Register (ETH_MTLTxQDR) and RXQSTS is set to 0. 6. To restart the operation, first start the DMAs, and then enable the MAC Transmitter and Receiver. Programming guidelines for MII link state transitions Transmit and Receive clocks are running when the link is down Complete the following steps when the link is down while the Transmit and Receive clocks are running: 1. Disable the Transmit DMA (if applicable) by clearing bit 0 (ST) of Channel control register (ETH_DMACCR). 2. Disable the MAC receiver by clearing bit 2 (RE) of Operating mode configuration register (ETH_MACCR). 3. Wait for any previous frame transmissions to complete. You can check this by reading the appropriate bits of Tx queue debug Register (ETH_MTLTxQDR) (TRCSTS is not 01). or Flush the Tx FIFO for faster empty operation. 4. Disable the MAC transmitter by clearing Bit 1(TE) of the Operating mode configuration register (ETH_MACCR) Register. 5. Make sure that both Tx and Rx queues are empty (TXQSTS is set to 0 in Tx queue debug Register (ETH_MTLTxQDR) and RXQSTS to 0 in Rx queue debug register (ETH_MTLRxQDR)). 6. After the link is up, read the PHY registers to identify the latest configuration and program the MAC registers accordingly. 7. Restart the operation by starting the Tx DMA. Then enable the MAC Transmitter and Receiver. The Rx DMA does not need to be enabled: since the Receiver is disabled, there are no data in the Rx FIFO. 2742/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Transmit and Receive clocks are stopped when the link is down Complete the following steps when the link is down and the Transmit and Receive clocks are stopped : 58.9.7 1. Disable the MAC Transmitter and Receiver by clearing RE and TE bits in the Operating mode configuration register (ETH_MACCR). This will not take immediate effect as the clocks are absent. 2. Wait till the link is up and the clocks are restored. 3. Wait until the transfer of any partial frame is complete if any was ongoing when the Transmit/Receive clock is stopped. This can be checked by reading the Debug register (ETH_MACDR) (all bits should be set to 0). Some old packets may still remain in the TXFIFO as the MAC Transmitter is stopped. 4. Read the PHY registers to identify the latest operating mode and program the MAC registers accordingly. 5. Restart the MAC Transmitter and Receiver by setting RE and TE bits. Programming guidelines for IEEE 1588 timestamping Initializing the System time generation The timestamp feature can be enabled by setting bit 0 of the Timestamp control Register (ETH_MACTSCR). However, it is essential that the timestamp counter is initialized after this bit is set. Complete the following steps to perform the peripheral initialization: 1. Mask the Timestamp Trigger interrupt by clearing bit 16 of Interrupt enable register (ETH_MACIER). 2. Set bit 0 of Timestamp control Register (ETH_MACTSCR) to enable timestamping. 3. Program Sub-second increment register (ETH_MACSSIR) based on the PTP clock frequency. 4. If you use the Fine Correction method, program Timestamp addend register (ETH_MACTSAR) and set bit 5 of Timestamp control Register (ETH_MACTSCR). 5. Poll the Timestamp control Register (ETH_MACTSCR) until bit 5 is cleared. 6. Program bit 1 of Timestamp control Register (ETH_MACTSCR) to select the Fine Update method (if required). 7. Program System time seconds update register (ETH_MACSTSUR) and System time nanoseconds update register (ETH_MACSTNUR) with the appropriate time value. 8. Set bit 2 in Timestamp control Register (ETH_MACTSCR). The timestamp counter starts as soon as it is initialized with the value written in the Timestamp Update registers. If one-step timestamping is required: 9. Note: a) Enable one-step timestamping by programming bit 27 of the TDES3 Context Descriptor. b) Program Timestamp Ingress asymmetric correction register (ETH_MACTSIACR) to update the correction field in PDelay_Req PTP messages. Enable the MAC receiver and transmitter for proper timestamping. If timestamp operation is disabled by clearing bit 0 of Timestamp control Register (ETH_MACTSCR), repeat all these steps to restart the timestamp operation. DocID029587 Rev 3 2743/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 System time correction To synchronize or update the system time in one shot (coarse correction method), complete the following steps: 1. Set the offset (positive or negative) in the Timestamp Update registers (System time seconds update register (ETH_MACSTSUR) and System time nanoseconds update register (ETH_MACSTNUR)). 2. Set bit 3 (TSUPDT) of the Timestamp control Register (ETH_MACTSCR). The value in the Timestamp Update registers is added to or subtracted from the system time when the TSUPDT bit is cleared. To synchronize or update the system time to reduce system-time jitter (fine correction method), complete the following steps: 58.9.8 1. With the help of the algorithm described in Section : System time register module, calculate at which rate you intend increment or decrement the system time. 2. Update the Timestamp addend register (ETH_MACTSAR) with the new value and set bit 5 of the Timestamp control Register (ETH_MACTSCR) Register. 3. Wait for the time during which you want the new value of the Addend register to be active. This can be done by enabling the Timestamp Trigger interrupt after the system time reaches the target value. 4. Program the required target time in PPS target time seconds register (ETH_MACPPSTTSR) and PPS target time nanoseconds register (ETH_MACPPSTTNR). 5. Enable the Timestamp interrupt in bit 12 of Interrupt enable register (ETH_MACIER). 6. Set bit 4 in Register Timestamp control Register (ETH_MACTSCR). 7. When this trigger generates an interrupt, read Interrupt status register (ETH_MACISR). 8. Reprogram Timestamp addend register (ETH_MACTSAR) with the old value and set bit 5 again. Programming guidelines for Energy Efficient Ethernet (EEE) Entering and exiting Tx LPI mode Complete the following steps during MAC initialization: 2744/3178 1. Read the PHY register through the MDIO interface and check if the remote end has the EEE capability. Then negotiate the timer values. 2. Program the PHY registers through the MDIO interface (including the RX_CLK_stoppable bit that indicates to the PHY whether to stop Rx clock in LPI mode or not). 3. Program bits 25 to 16 and bits 1 to 0 in LPI timers control register (ETH_MACLTCR). 4. Read the PHY link status by using the MDIO interface and update bit 17 of LPI control status register (ETH_MACLCSR). 5. Update LPI control status register (ETH_MACLCSR) accordingly. This update should be done whenever the link status in the PHY chip changes. 6. Program 1-microsecond-tick counter register (ETH_MAC1USTCR) as per the frequency of the clock used for accessing the CSR slave port. 7. Program the LPIET bit in the LPI entry timer register (ETH_MACLETR) with the IDLE time for which the MAC should wait before entering the LPI state on its own. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller 8. Set LPITE and LPITXA (bits 20 to 19) of LPI control status register (ETH_MACLCSR). 9. Update LPI control status register (ETH_MACLCSR) to enable LPI auto-entry and MAC auto-exit from LPI state. 10. Program the 1-microsecond-tick counter register (ETH_MAC1USTCR) according to the frequency of the clock used to access the CSR slave port. 11. Program the LPIET bit in LPI entry timer register (ETH_MACLETR) register with the IDLE time for which the MAC should wait before entering the LPI state on its own. 12. Set LPITE and LPITXA (bits 20 and 19) of LPI control status register (ETH_MACLCSR) to enable LPI auto-entry and MAC auto-exit from LPI state. 13. Set bit 16 of LPI control status register (ETH_MACLCSR) to put the MAC transmitter in LPI state. The MAC enters the LPI state when all scheduled packets are completed. It remains IDLE for the time indicated by LPIET bits. It sets the TLPIEN (bit 0) after entering LPI state. 14. When a packet transmission is scheduled (when the TxDMA exits IDLE state or when a packet is presented at ATI or MTI interface), the MAC Transmitter automatically exits LPI state. It waits for TWT time before setting the TLPIEX interrupt status bit and then resume the packet transmission. 15. The MAC Transmitter enters again LPI state if it remains IDLE for LPIET time. It then sets the TLPIEN bit and the entry-exit cycle continues. 16. Reset LPITXEN bit if the application needs to override the auto-entry/exit modes and directly exit the MAC Transmitter from LPI state. 58.9.9 Programming guidelines for flexible pulse-per-second (PPS) output Generating a single pulse on PPS To generate a single pulse on PPS: 1. Program TRGTMODSEL bit to 11 or 10 (for interrupt) in PPS control register (ETH_MACPPSCR). This instructs the MAC to use the Target Time registers (register 736 and 737) as start time of PPS signal output. 2. Program the start time value in the Target Time registers (register 736 and 737). 3. Program the width of the PPS signal output in PPS width register (ETH_MACPPSWR) Register. 4. Program PPSCMD of PPS control register (ETH_MACPPSCR) to 0001. This instructs the MAC to generate a single pulse on the PPS signal output at the time programmed in the Target Time registers. When the PPSCMD is executed (PPSCMD bits = 0), you can cancel the pulse generation by giving the Cancel Start Command (PPSCMD=0011) before the programmed start time has elapsed. You can also program the behavior of the next pulse in advance. To program the next pulse: 1. Program the start time for the next pulse in the Target Time registers. This time should be higher than the time at which the falling edge occurs for the previous pulse. 2. Program the width of the next PPS signal output in PPS width register (ETH_MACPPSWR). 3. Program PPSCMD bits of PPS control register (ETH_MACPPSCR) to generate a single pulse after the previous pulse is de-asserted. This instructs the MAC to generate DocID029587 Rev 3 2745/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 a single pulse on the PPS signal output at the time programmed in Target Time registers. If this command is given before the previous pulse becomes low, then the new command overwrites the previous command and the QOS may generate only 1 extended pulse. Generating a pulse train on PPS To generate a pulse train on PPS: 1. Program TRGTMODSEL bits to 11 or 10 (for interrupt) in PPS control register (ETH_MACPPSCR). This instructs the MAC to use the Target Time registers (register 736 and 737) for start time of the PPS signal output. 2. Program the start time value in the Target Time registers (register 736 and 737). 3. Program the interval value between the train of pulses on the PPS signal output in PPS interval register (ETH_MACPPSIR). 4. Program the width of the PPS signal output in PPS width register (ETH_MACPPSWR). 5. Program PPSCMD bits in PPS control register (ETH_MACPPSCR) to 0010. This instructs the MAC to generate a train of pulses on the PPS signal output at the start time programmed in Target Time registers. By default, the PPS pulse train is free-running unless it is stopped by issuing a ‘STOP Pulse train at time’ or ‘STOP Pulse Train immediately’ commands. 6. Program the stop value in the Target Time registers. Ensure that TSTRBUSY bit in PPS target time nanoseconds register (ETH_MACPPSTTNR) is reset before programming the Target Time registers again. 7. Program the PPSCMD bits in PPS control register (ETH_MACPPSCR) to 0100 to stop the train of pulses on PPS signal output after the programmed stop time specified at step 6 has elapsed. The pulse train can be stopped at any time by programming 0101 in the PPSCMD field. Similarly, the Stop Pulse train command (given in Step 5) can be canceled by programming PPSCMD bits to 0110 before the time (programmed at step 6) has elapsed. The pulse train generation can be stopped by programming PPSCMD to 0011 before the start time programmed at step 2) has elapsed. 2746/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Generating an interrupt without affecting the PPS TRGTMODSEL bits in PPS control register (ETH_MACPPSCR) enable you to program the Target Time registers (register 736 and 737) to do any one of the following: • Generate only interrupts. • Generate interrupts and the PPS start and stop time. • Generate only PPS start and stop time. To program the Target Time registers to generate only interrupt event: 1. Program TRGTMODSEL bits of PPS control register (ETH_MACPPSCR) to 00 (for interrupt). This instructs the MAC to use the Target Time registers for target time interrupt. 2. Program a target time value in the Target Time registers. This instructs the MAC to generate an interrupt when the target time elapses. If TRGTMODSEL bits are changed (for example, to control the PPS), then the interrupt generation is overwritten with the new mode and new programmed Target Time register value. 58.9.10 Programming guidelines for TSO Follow the steps below to program TSO: 1. Program TSE bit of the corresponding ETH_DMACTxCR register to enable TCP packet segmentation in that DMA. 2. In addition to the normal transfer descriptor setting, the following descriptor fields must be programmed to enable TSO for the current packet: a) Enable TSE of TDES3 (bit 18). b) Program the length of the unsegmented TCP/IP packet payload in bits 17 to 0 of TDES3, and the TCP header in bits 22 to 19 of TDES3. c) Program the maximum size of the segment in: – MSS of ETH_DMACCR – or MSS in the context descriptor If MSS field is programmed in both ETH_DMACCR and in the context descriptor, the latest software programmed sequence is considered. 3. Caution: The unsegmented TCP/IP packet header should be stored in Buffer 1 of the first descriptor. This buffer must not hold any payload bytes. The payload is allocated to Buffer 2 and the buffers of the subsequent descriptors. If TSE is enabled in TDES3 for a non-TCP-IP packet, the result is unpredictable. DocID029587 Rev 3 2747/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.9.11 RM0433 Programming guidelines to perform VLAN filtering on the receive Follow the sequence below to perform VLAN filtering on the receiver: 1. Program VLAN tag register (ETH_MACVTR) for the following bit to select the filtering method: – ETV: Enable 12-bit VLAN Tag Comparison or 16-bit VLAN Tag comparison. – VTHM: VLAN Tag Hash Table Match Enable. – ERIVLT: Enable inner VLAN Tag or outer VLAN Tag (to enable the inner or outer VLAN Tag filtering, Double VLAN Processing should enabled by setting EDVLP) – ERSVLM: Enable Receive S-VLAN Match or C-VLAN match (for S-VLAN processing to be enabled, set ESVL) – DOVLTC: Ignores VLAN Type for Tag Match – VTIM: to enable VLAN Tag Inverse Match instead of the normal VLAN Tag matching 2. Program VL bit in VLAN tag register (ETH_MACVTR) for the 12-bit or 16-bit VLAN tag. 3. If VLAN tag Hash filtering is enabled, program VLAN Hash table register (ETH_MACVHTR). The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of '1000 selects bit 8 of the VLAN Hash table. 58.10 Descriptors 58.10.1 Descriptor overview In the Ethernet peripheral, the DMA transfers data based on a linked list of descriptors. The application creates the descriptors in the system memory (SRAM). The following two types of descriptors are supported: • Normal descriptors The normal descriptors are used for packet data and to provide control information applicable to the packets to be transmitted. • Context descriptors The context descriptors are used to provide control information applicable to the packet to be transmitted. Each normal descriptor contains two buffers and two address pointers. These buffers enable the adapter port to be compatible with various types of memory management schemes. There is no limit to the number of descriptors that can be used for a single packet. 2748/3178 DocID029587 Rev 3 RM0433 58.10.2 Ethernet (ETH): media access control (MAC) with DMA controller Descriptor structure The Ethernet peripheral supports the ring structure for DMA descriptors. Figure 789. Descriptor ring structure %XIIHU 'HVFULSWRU %XIIHU %XIIHU 'HVFULSWRU %XIIHU 'HVFULSWRU %XIIHU %XIIHU « %XIIHU 'HVFULSWRU1 %XIIHU 06Y 9 In a ring structure, descriptors are separated by the 32-bit word number programmed in the DSL field of the Channel control register (ETH_DMACCR)). The application needs to program the total ring length, that is the total number of descriptors in ring span, in the following registers of a DMA channel: • Channel Tx descriptor ring length register (ETH_DMACTxRLR)) • Channel Rx descriptor ring length register (ETH_DMACRxRLR)) The Channel Tx descriptor tail pointer register (ETH_DMACTxDTPR) or Channel Rx descriptor tail pointer register (ETH_DMACRxDTPR) contains the pointer to the descriptor address (N). The base address and the current descriptor pointer decide the address of the current descriptor that the DMA can process. The descriptors up to one location less than the one indicated by the descriptor tail pointer (N – 1) are owned by the DMA. The DMA continues to process the descriptors until the following condition occurs: Current Descriptor Pointer == Descriptor Tail Pointer; The DMA enters the Suspend state when this condition occurs. The application must perform a write operation to the Descriptor tail pointer register and update the tail pointer so that the following condition is met: Current Descriptor Pointer < Descriptor Tail Pointer; DocID029587 Rev 3 2749/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 The DMA automatically wraps around the base address when the end of ring is reached, as shown in Figure 790: DMA descriptor ring. Figure 790. DMA descriptor ring 'HVFULSWRUEDVHDGGUHVV /DVWGHVFULSWRURZQHGE\WKH'0$ 'HVFULSWRUWDLOSRLQWHU 'HVFULSWRUULQJOHQJWK 1XPEHURIGHVFULSWRU :UDSDURXQGWKHEDVHDGGUHVV WRVWDUWRIWKHULQJ &XUUHQWGHVFULSWRUSRLQWHU 'HVFULSWRURZQHGE\WKH'0$ 'HVFULSWRURZQHGE\WKHDSSOLFDWLRQ 06Y 9 For descriptors owned by the application, the OWN bit of DES3 is reset to 0. For descriptors owned by the DMA, the OWN bit is set to 1. At the beginning, if the application has only one descriptor, it sets the last descriptor address (tail pointer) to Descriptor Base Address + 1. The DMA then processes the first descriptor and waits for the application to increment the tail pointer. 2750/3178 DocID029587 Rev 3 RM0433 Transmit descriptor The Ethernet peripheral DMA requires at least one descriptor for a transmit packet. In addition to two buffers, two byte-count buffers, and two address pointers, the transmit descriptor features control fields which can be used to manage the MAC operation on per-transmit packet basis. The Transmit normal descriptor has the following two formats: Read format and Write-back format Transmit normal descriptor (read format) Figure 791 shows the Read format for Transmit normal descriptor. Table 513 to Table 516 provide a detailed description of all Transmit normal descriptors (read format). Figure 791. Transmit descriptor (read format) 7'(6 +HDGHURU%XIIHU$GGUHVV> @ 7'(6 7'(6 %XIIHU/HQJWK> @ &RQWURO> @ &RQWURO> @ 97,5 776( ,2& 7'(6 %XIIHU$GGUHVV> @RU%XIIHU$GGUHVV> @ 2:1 58.10.3 Ethernet (ETH): media access control (MAC) with DMA controller +HDGHURU%XIIHU/HQJWK> @ )UDPHOHQJWK> @ 3D\ORDGOHQJWK> @ 06Y 9 • TDES0 normal descriptor (read format) Table 513. TDES0 normal descriptor (read format) Bit 31:0 Name Description BUF1AP Buffer 1 Address Pointer or TSO Header Address Pointer These bits indicate either the physical address of Buffer 1 or the TSO Header Address pointer when the following bits are set: – TSE bit of TDES3 – FD bit of TDES3 DocID029587 Rev 3 2751/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller • RM0433 TDES1 normal descriptor (read format) Table 514. TDES1 normal descriptor (read format) • Bit Name Description 31:0 BUF2AP Buffer 2 or Buffer 1 Address Pointer: These bits indicate the physical address of Buffer 2 when a descriptor ring structure is used. There is no limitation to the buffer address alignment. TDES2 normal descriptor (read format) 31 30 29:16 15:14 13:0 IOC TTSE B2L VTIR HL or B1L Table 515. TDES2 normal descriptor (read format) Bits Name Description 31 IOC Interrupt on Completion: This bit sets the TI bit in the Channel status register (ETH_DMACSR)) when the present packet transmission is complete. 30 TTSE 29:16 B2L Buffer 2 Length The driver sets this field. When set, this field indicates Buffer 2 length. VTIR VLAN Tag Insertion or Replacement: These bits request the MAC to perform VLAN tagging or untagging before transmitting the packets. The application must set the CRC Pad Control bits appropriately when VLAN tag insertion, replacement, or deletion is enabled for the packet. The values of these bits are as follows: – 00: Do not add a VLAN tag. – 01: Remove the VLAN tag from the packets before transmission. This option should be used only with the VLAN packets. – 10: Insert a VLAN tag with the tag value programmed in the VLAN inclusion register (ETH_MACVIR) or context descriptor. – 11: Replace the VLAN tag in packets with the tag value programmed in the VLAN inclusion register (ETH_MACVIR) or context descriptor. This option should be used only with the VLAN packets. 15:14 13:0 2752/3178 Transmit Timestamp Enable Header Length or Buffer 1 Length For Header length, only bits [9:0] are taken into account. Bits 13 to 0 are applicable only to buffer 1 length. If the TCP Segmentation Offload feature is enabled through the TSE bit of TDES3, this field is equal to the header length. When the TSE bit is set in HL or B1L TDES3, the header length includes the length (expressed in bytes) from Ethernet Source address till the end of the TCP header. The maximum header length supported for TSO feature is 1023 bytes. The maximum header length supported for TSO feature is 1023 bytes. If the TCP Segmentation Offload feature is not enabled, this field is equal to Buffer 1 length. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller • TDES3 normal descriptor (read format) 31 30 29 28 OWN CTXT FD LD 15 14 13 12 27 26 25 CPC 11 24 23 22 21 SAIC 10 9 8 20 19 THL 7 6 5 18 17 TSE 4 3 2 16 TPL 1 0 FT/L Table 516. TDES3 normal descriptor (Read format) Bits Name Description 31 OWN Own bit – 1: the DMA owns the descriptor. – 0: the application owns the descriptor. The DMA clears this bit after it completes the transfer of data given in the associated buffer(s). 30 CTXT Context Type This bit should be set to 0 for normal descriptor. 29 FD First Descriptor When this bit is set, it indicates that the buffer contains the first segment of a packet. 28 LD Last Descriptor When this bit is set, it indicates that the buffer contains the last segment of the packet. B1L or B2L field should have a non-zero value. CRC Pad Control This field controls the CRC and Pad Insertion for Tx packet. It is valid only when the first descriptor bit (TDES3[29]) is set. The values of bits[27:26] are the following: 27:26 CPC – 00: CRC and Pad Insertion The MAC appends the cyclic redundancy check (CRC) at the end of the transmitted packets whose length greater than or equal to 60 bytes. The MAC automatically appends padding and CRC to a packet with length less than 60 bytes. – 01: CRC Insertion (Disable Pad Insertion) The MAC appends the CRC at the end of the transmitted packet but it does not append padding. The application should ensure that the padding bytes are present in the packet being transferred from the Transmit buffer, that is, the packet being transferred from the Transmit Buffer is of length greater than or equal to 60 bytes. – 10: Disable CRC Insertion The MAC does not append the CRC at the end of the transmitted packet. The application should ensure that the padding and CRC bytes are present in the packet being transferred from the Transmit Buffer. – 11: CRC Replacement The MAC replaces the last four bytes of the transmitted packet with recalculated CRC bytes. The application should ensure that the padding and CRC bytes are present in the packet being transferred from the Transmit Buffer. Note: When the TSE bit is set, the MAC ignores this field because the CRC and pad insertion is always done for segmentation. DocID029587 Rev 3 2753/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 516. TDES3 normal descriptor (Read format) (continued) Bits Name Description 25:23 SAIC SA Insertion Control These bits request the MAC to add or replace the Source Address field in the Ethernet packet with the value given in the MAC Address 0 register. The application must appropriately set the CRC Pad Control bits when SA Insertion Control is enabled for the packet. Bit 25 specifies the MAC Address Register (1 or 0) value that is used for Source Address insertion or replacement. The following list describes the values of Bits[24:23]: – 00: Do not include the source address – 01: Include or insert the source address. For reliable transmission, the application must provide frames without source addresses. – 10: Replace the source address. For reliable transmission, the application must provide frames with source addresses. – 11: Reserved These bits are valid when the First Segment control bit (TDES3 [29]) is set. 22:19 THL THL: TCP Header Length If the TSE bit is set, this field contains the length of the TCP header. The minimum value of this field must be 5. 18 TSE TCP Segmentation Enable When this bit is set, the DMA performs the TCP segmentation for a packet. This bit is valid only if the FD bit is set. CIC/TPL Checksum Insertion Control or TCP Payload Length These bits control the checksum calculation and insertion. They can take the following values: – 00: Checksum insertion disabled. – 01: Only IP header checksum calculation and insertion are enabled. – 10: IP header checksum and payload checksum calculation and insertion are enabled, but pseudo-header checksum is not calculated in hardware. – 11: IP header checksum and payload checksum calculation and insertion are enabled, and pseudo-header checksum is calculated in hardware. This field is valid when the TSE bit is reset.When the TSE bit is set, it contains the upper bits [17:16] of the TCP Payload length. This allows the TCP packet length field to be spanned across TDES3[17:0] to provide 256 Kbyte packet length support. 17:16 2754/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 516. TDES3 normal descriptor (Read format) (continued) Bits Name Description 15 TPL Reserved or TCP Payload Length When the TSE bit is reset, this bit is reserved. When the TSE bit is set, this is bit 15 of the TCP payload length [17:0]. FL/TPL Packet Length or TCP Payload Length This field is equal to the length of the packet to be transmitted (expressed in bytes). When the TSE bit is not set, this field is equal to the total length of the packet to be transmitted: Ethernet Header Length + TCP /IP Header Length – Preamble Length – SFD Length + Ethernet Payload Length When the TSE bit is set, this field is equal to the lower 15 bits of the TCP payload length. This length does not include Ethernet header or TCP/IP header length. 14:0 Transmit normal descriptor (write-back format) The write-back format is applicable only for the last descriptor of the corresponding packet. The LD bit (TDES3[28]) is set in the descriptor where the DMA writes back the status and timestamp information for the corresponding Transmit packet. Figure 792 shows the write-back format for Transmit normal descriptors. Table 517 to Table 520 provide a detailed description of all Transmit Normal descriptors (Write-Back Format). Figure 792. Transmit descriptor write-back format 7'(6 7LPHVWDPS/RZ 7LPHVWDPSKLJK 7'(6 5HVHUYHG 7'(6 2:1 7'(6 6WDWXV> @ 06Y 9 DocID029587 Rev 3 2755/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller • RM0433 TDES0 normal descriptor (write-back format) Table 517. DES0 normal descriptor (write-back format)(1) Bit 31:0 Name Description Transmit Packet Timestamp Low The DMA updates this field with least significant 32 bits of the timestamp captured TTSL for the corresponding Transmit packet. The DMA writes the timestamp only if TTSE bit of TDES2 is set in the first descriptor of the packet. This field holds the timestamp only if the Last Segment bit (LS) in the descriptor is set and the Timestamp status (TTSS) bit is set. 1. This format is only applicable to the last descriptor of a packet. • TDES1 normal descriptor (write-back format) Table 518. TDES1 normal descriptor (write-back format)(1) Bit 31:0 Name Description Transmit Packet Timestamp High The DMA updates this field with the most significant 32 bits of the timestamp TTSH captured for corresponding Receive packet. The DMA writes the timestamp only if the TTSE bit of TDES2 is set in the first descriptor of the packet. This field has the timestamp only if the Last Segment bit (LS) in the descriptor is set and Timestamp status (TTSS) bit is set. 1. This format is only applicable to the last descriptor of a packet. • TDES2 normal descriptor (write-back format) Table 519. TDES2 normal descriptor (write-back format)(1) Bit Description 31:0 Reserved 1. This format is only applicable to the last descriptor of a packet. • 2756/3178 TDES3 normal descriptor (write-back format) 31 30 29 28 OWN CTXT FD LD 27 26 25 24 23 22 21 20 19 18 Reserved 15 14 13 12 11 10 9 8 ES JT FF PCE LoC NC LC EC 7 DocID029587 Rev 3 6 5 CC 4 17 16 TTSS Res. 3 2 1 0 ED UF DB IHE RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 520. TDES3 normal descriptor (write-back format)(1) Bit Name Description 31 OWN Own bit When this bit is set, it indicates that the DMA owns the descriptor. The DMA clears this bit when it completes the packet transmission. After the write-back is complete, this bit is set to 0. 30 CTXT Context Type This bit should be set to 0 for normal descriptors. 29 FD First Descriptor This bit indicates that the buffer contains the first segment of a packet. 28 LD Last Descriptor This bit is set 1 for last descriptor of a packet. The DMA writes the status fields only in the last descriptor of the packet. 27:18 Reserved 17 TTSS 16 Reserved Tx Timestamp Status This status bit indicates that a timestamp has been captured for the corresponding transmit packet. When this bit is set, TDES2 and TDES3 have timestamp values that were captured for the Transmit packet. This field is valid only when the Last Segment control bit (TDES3 [28]) in a descriptor is set. ES Error Summary: This bit indicates the logical OR of the following bits: – TDES3[0]: IP Header Error – TDES3[14]: Jabber Timeout – TDES3[13]: Packet Flush – TDES3[12]: Payload Checksum Error – TDES3[11]: Loss of Carrier – TDES3[10]: No Carrier – TDES3[9]: Late Collision – TDES3[8]: Excessive Collision – TDES3[3]: Excessive Deferral – TDES3[2]: Underflow Error 14 JT Jabber Timeout This bit indicates that the MAC transmitter has experienced a jabber timeout. This bit is set only when the JD bit of the Operating mode configuration register (ETH_MACCR) is not set. 13 FF Packet Flushed This bit indicates that the DMA or MTL flushed the packet because of a software flush command given by the CPU. 15 DocID029587 Rev 3 2757/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 520. TDES3 normal descriptor (write-back format)(1) (continued) Bit Name Description PCE Payload Checksum Error This bit indicates that the Checksum Offload engine had a failure and did not insert any checksum into the encapsulated TCP, UDP, or ICMP payload. This failure can be either caused by insufficient bytes, as indicated by the Payload Length field of the IP Header, or by the MTL starting to forward the packet to the MAC transmitter in Store-andForward mode without the checksum having been calculated yet. This second error condition only occurs when the Transmit FIFO depth is less than the length of the Ethernet packet being transmitted to avoid deadlock, the MTL starts forwarding the packet when the FIFO is full, even in the store-and-forward mode. 11 LoC Loss of Carrier This bit indicates that Loss of Carrier occurred during packet transmission (that is, the ETH_CRS signal was inactive for one or more transmit clock periods during packet transmission). This is valid only for the packets transmitted without collision and when the MAC operates in the half-duplex mode. 10 NC No Carrier This bit indicates that the carrier sense signal form the PHY was not asserted during transmission. LC Late Collision This bit indicates that packet transmission was aborted because a collision occurred after the collision window (64 byte times including Preamble. This bit is not valid if Underflow Error is set. EC Excessive Collision This bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the Operating mode configuration register (ETH_MACCR), this bit is set after first collision and the transmission of the packet is aborted. CC Collision Count This 4-bit counter value indicates the number of collisions occurred before the packet was transmitted. The count is not valid when the EC bit is set. ED Excessive Deferral This bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times if DC bit is set in the Operating mode configuration register (ETH_MACCR). 12 9 8 7:4 3 2758/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 520. TDES3 normal descriptor (write-back format)(1) (continued) Bit Name Description 2 UF Underflow Error This bit indicates that the MAC aborted the packet because the data arrived late from the system memory. The underflow error can occur because of either of the following conditions: – The DMA encountered an empty Transmit Buffer while transmitting the packet – The application filled the MTL Tx FIFO slower than the MAC transmit rate The transmission process enters the Suspend state and sets the underflow bit corresponding to a queue in the ETH_MTLISR register. 1 DB Deferred Bit This bit indicates that the MAC deferred before transmitting because of presence of carrier. This bit is valid only in the half-duplex mode. IHE IP Header Error When IP Header Error is set, this bit indicates that the Checksum Offload engine detected an IP header error. This bit is valid only when Tx Checksum Offload is enabled. Otherwise, it is reserved. If COE detects an IP header error, it still inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload. 0 1. This format is only applicable to the last descriptor of a packet. Transmit context descriptor The Transmit context descriptor can be provided any time before a packet descriptor. The context is valid for the current packet and subsequent packets. The context descriptor is used to provide the timestamps for one-step timestamp correction, VLAN Tag ID for VLAN insertion feature, and SA insertion bit for SA insertion. Write-back is only done on a context descriptor to reset the OWN bit. Note: The VLAN tag IDs and MSS values, which are provided by the application in a context descriptor with their corresponding Valid bits set, are stored internally by the DMA. When the outer or inner VLAN tag is provided with the Valid bit set, the DMA always passes the last valid VLAN tag to the MTL. The application cannot invalidate the valid VLAN tag stored by the DMA. The VLAN tag is inserted or replaced based on the control inputs provided for the packet. The Inner VLAN Tag Control input is used only for the packet that immediately follows the context descriptor. The application must provide a context descriptor before the normal descriptor of each packet for which the DMA should use the inner VLAN Tag control input. Figure 793 shows the format for Transmit context descriptors. Table 521 to Table 524 provide a detailed description of all Transmit context descriptors. DocID029587 Rev 3 2759/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Figure 793. Transmit context descriptor format 7'(6 7LPHVWDPS/RZ> @ 7'(6 ,QQHU9/$1WDJ> @ 7'(6 2:1 7'(6 5HV 7LPHVWDPS+LJK> @ &RQWURO> @ 0D[LPXPVHJPHQWVL]H> @ 9/$1WDJ> @ 06Y 9 • TDES0 context descriptor (read format) Table 521. TDES0 context descriptor Bit 31:0 • Name Description Transmit Packet Timestamp Low For one-step correction, the driver can provide the lower 32 bits of timestamp in TTSL this descriptor word. The DMA uses this value as the low word for doing one-step timestamp correction. This field is valid only if the OSTC and TCMSSV bits of TDES3 context descriptor are set. TDES1 context descriptor (read format) Table 522. TDES1 context descriptor Bit 31:0 2760/3178 Name Description TTSH Transmit Packet Timestamp High For one-step correction, the driver can provide the upper 32 bits of timestamp in this descriptor. The DMA uses this value as the high word for doing one-step timestamp correction. This field is valid only if the OSTC and TCMSSV bits of TDES3 context descriptor are set. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller • TDES2 context descriptor (read format) Table 523. TDES2 context descriptor Bit Name Description IVT Inner VLAN Tag When the IVLTV bit of TDES3 context descriptor is set and the TCMSSV and OSTC bits of TDES3 context descriptor are reset, TDES2[31:16] contains the inner VLAN Tag to be inserted in the subsequent Transmit packets. 31:16 15:14 Reserved 13:0 • Maximum Segment Size This segment size is used while segmenting the TCP/IP payload. This field is valid only if the TCMSSV bit of TDES3 context descriptor is set and the OSTC bit of the TDES3 context descriptor is reset. MSS TDES3 context descriptor (read format) 31 30 OWN CTXT 15 14 29 28 Reserved 13 27 26 TCMS OSTC SV 12 11 10 25 24 23 Reserved 9 22 21 CDE 8 7 20 19 18 Reserved 6 5 4 3 2 17 16 IVLTV VLTV 1 0 VT Table 524. TDES3 context descriptor Bit Name Description 31 OWN Own bit – 1: the DMA owns the descriptor. – 0: the application owns the descriptor. The DMA clears this bit when either of the following conditions is true: – The DMA completes the packet reception. – The buffers associated with the descriptor are full. 30 CTXT Context Type This bit should be set to 1 for context descriptor. 29:28 27 26 25:24 Reserved OSTC One-Step Timestamp Correction Enable When this bit is set, the DMA performs a one-step timestamp correction with reference to the timestamp values provided in TDES0 and TDES1. TCMSSV One-Step Timestamp Correction Input or MSS Valid When this bit and the OSTC bit are set, it indicates that the Timestamp Correction input provided in TDES0 and TDES1 is valid. When the OSTC bit is reset and this bit and the TSE bit of TDES3 are set in subsequent normal descriptor, it indicates that the MSS input in TDES2 is valid. Reserved DocID029587 Rev 3 2761/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 524. TDES3 context descriptor (continued) Bit 23 22:20 Description CDE Context Descriptor Error When this bit is set, it indicates that the context descriptor was provided in the incorrect sequence and the DMA ignored it. The DMA sets this bit during write-back while closing the context descriptor. Reserved 19:18 IVTIR Inner VLAN Tag Insert or Replace When these bits are set, they request the MAC to perform Inner VLAN tagging or untagging before transmitting the packets. If the packet is modified for VLAN tags, the MAC automatically recalculates and replaces the CRC bytes. This bitfield has the following values: – 00: Do not add the inner VLAN tag. – 01: Remove the inner VLAN tag from the packets before transmission. This option should be used only with the VLAN frames. – 10: Insert an inner VLAN tag with the tag value programmed in the Inner VLAN inclusion register (ETH_MACIVIR) or context descriptor. – 11: Replace the inner VLAN tag in packets with the tag value programmed in the Inner VLAN inclusion register (ETH_MACIVIR) or context descriptor. This option should be used only with the VLAN frames. 17 IVLTV Inner VLAN Tag Valid When this bit is set, it indicates that the IVT field of TDES2 is valid. 16 VLTV VLAN Tag Valid When this bit is set, it indicates that the VT field of TDES3 is valid. 15:0 2762/3178 Name VT VLAN Tag This field contains the VLAN Tag to be inserted or replaced in the packet. This field is used as VLAN Tag only when the VLTI bit of the VLAN inclusion register (ETH_MACVIR) is reset. DocID029587 Rev 3 RM0433 58.10.4 Ethernet (ETH): media access control (MAC) with DMA controller Receive descriptor The DMA in the Ethernet peripheral attempts to read a descriptor only if the Tail pointer is different from the Base pointer or current pointer. It is recommended to have a descriptor ring with a length that can accommodate at least two complete packets received by the MAC; otherwise, the performance of the DMA is greatly impacted because of the unavailability of the descriptors. In such a situation, the MTL RxFIFO becomes full and starts dropping packets. The following Receive descriptors are present: • Normal descriptors with read and write-back formats • Context descriptors All received descriptors are prepared by the software and given to the DMA as “normal” descriptors (see Figure 794: Receive normal descriptor (read format) for a description of their content). The DMA reads this descriptor and, after transferring a received packet (or part of it) to the buffers indicated by the descriptor, the Rx DMA closes the descriptor with the corresponding packet status. The status format is given in Figure 795: Receive normal descriptor (write-back format). For some packets, the normal descriptor bits are not sufficient to write the complete status. For such packets, the Rx DMA will write the extended status to the next descriptor (without processing or using the Buffers pointers embedded in that descriptor). The format and content of this write-back descriptor is described in Figure 796: Receive context descriptor. Receive normal descriptor (read format) Figure 794 shows the read format for Receive normal descriptors. Table 525 to Table 528 provide a detailed description of all Receive normal descriptors (read format). Figure 794. Receive normal descriptor (read format) 5'(6 %XIIHU$GGUHVV> @ 5'(6 5HVHUYHGRU+HDGHU%XIIHU$GGUHVV> @ 3D\ORDGRU%XIIHU$GGUHVV> @ ,2& 5'(6 2:1 5'(6 5HVHUYHG> @RU%XIIHU$GGUHVV> @ 06Y9 Note: In the Receive descriptor (read format), if the Buffer Address field contains only 0s, the MAC does not transfer data to this buffer and skips to the next buffer or next descriptor. DocID029587 Rev 3 2763/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller • RM0433 RDES0 normal descriptor (read format) Table 525. RDES0 normal descriptor (read format) Bit 31:0 • Name Description BUF1AP Header or Buffer 1 Address Pointer The application can program a byte-aligned address for this buffer, which means that the LS bits of this field can be non-zero. However, while transferring the start of packet, the DMA performs a write operation with RDES0[1:0] (or RDES0[2:0]/[3:0] in case of 64-/128-bit configuration) as zero. However, the packet data is shifted by the actual offset as given in the buffer address pointer. If the address pointer points to a buffer where the middle or last part of the packet is stored, the DMA ignores the offset address and writes to the full location as indicated by the data-width. RDES1 normal descriptor (read format) Table 526. RDES1 normal descriptor (read format) Bit Name 31:0 Reserved • Description Field reserved. RDES2 normal descriptor (read format) Table 527. RDES2 normal descriptor (read format) Bit 31:0 • Name Description Buffer 2 Address Pointer These bits indicate Buffer 2 physical address. BUF2AP The RxDMA uses the LS bits of the pointer address only while transferring the start bytes of a packet. If the BUF2AP is giving the address of a buffer in which the middle or last part of a packet is stored, the DMA ignores RDES2[1:0]=0 and writes to the complete location. RDES3 normal descriptor (read format) 31 30 OWN IOC 15 14 29 28 27 26 Reserved 13 12 11 25 24 10 9 8 Reserved 2764/3178 23 22 21 BUF2V BUF1V DocID029587 Rev 3 20 19 18 17 16 2 1 0 Reserved 7 6 5 4 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 528. RDES3 normal descriptor (read format) Bit Name Description 31 OWN Own bit When this bit is set, it indicates that the DMA owns the descriptor. When this bit is reset, it indicates that the application owns the descriptor. The DMA clears this bit when either of the following conditions is true: – The DMA completes the packet reception – The buffers associated with the descriptor are full 30 IOC 29:26 Reserved Interrupt Enabled on Completion When this bit is set, an interrupt is issued to the application when the DMA closes this descriptor. BUF2V Buffer 2 Address Valid When this bit is set, it indicates to the DMA that the buffer 1 address specified in RDES0 is valid. The application must set this bit so that the DMA can use the address to which the Buffer 2 address in RDES0 is pointing, to write received packet data. 24 BUF1V Buffer 1 Address Valid When set, this indicates to the DMA that the buffer 1 address specified in RDES1 is valid. The application must set this value if the address to which Buffer 1 address points in RDES1, can be used by the DMA to write received packet data. 23:0 Reserved 25 DocID029587 Rev 3 2765/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Receive normal descriptor (write-back format) Figure 795 shows the write-back format for Receive normal descriptors. Table 529 to Table 532 provide a detailed description of all Receive normal descriptors (write-back format). Figure 795. Receive normal descriptor (write-back format) 5'(6 2$0FRGHRU0$&FRQWURO2SFRGH > @ ([WHQGHGVWDWXV 5'(6 0$&ILOWHUVWDWXV> @ 5'(6 6WDWXV> @ 9) 5'(6 $53 5HV VWDWXV +HDGHUOHQJWK> @ > @ > @ (6 2XWHU9/$1WDJ> @ 2:1 &7;7 )' /' ,QQHU9/$1WDJ> @ 3DFNHWOHQJWK> @ 06Y 9 • RDES0 normal descriptor (write-back format) Table 529. RDES0 normal descriptor (write-back format) 2766/3178 Bit Name Description 31:16 IVT Inner VLAN Tag This field contains the Inner VLAN tag of the received packet if the RS0V bit of RDES3 is set. 15:0 OVT Outer VLAN Tag This field contains the Outer VLAN tag of the received packet if the RS0V bit of RDES3 is set. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller • RDES1 normal descriptor (write-back format) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 IPCE IPCB IPV6 IPV4 IPHE OPC 15 14 13 12 TD TSA PV PFT 11 10 9 PMT 8 PT Table 530. RDES1 normal descriptor (write-back format)(1) Bit Name Description 31:16 OPC OAM Sub-Type Code, or MAC Control Packet opcode OAM Sub-Type Code If bits[18:16] of RDES3 are set to 111, this field contains the OAM subtype and code fields. MAC Control Packet opcode If bits[18:16] of RDES3 are set to 110, this field contains the MAC Control packet opcode field. 15 TD Timestamp Dropped This bit indicates that the timestamp was captured for this packet but got dropped in the MTL Rx FIFO because of overflow. 14 TSA Timestamp Available When Timestamp is present, this bit indicates that the timestamp value is available in a context descriptor word 2 (RDES2) and word 1(RDES1). This is valid only when the Last Descriptor bit (RDES3 [28]) is set. The context descriptor is written in the next descriptor just after the last normal descriptor for a packet. 13 PV PTP Version 1: Received PTP message in IEEE 1588 version 2 format 0: Received PTP message in IEEE 1588 version 1 format 12 PFT PTP Packet Type This bit indicates that the PTP message is sent directly over Ethernet. PMT PTP Message Type These bits are encoded to give the type of the message received: – 0000: No PTP message received – 0001: SYNC (all clock types) – 0010: Follow_Up (all clock types) – 0011: Delay_Req (all clock types) – 0100: Delay_Resp (all clock types) – 0101: Pdelay_Req (in peer-to-peer transparent clock) – 0110: Pdelay_Resp (in peer-to-peer transparent clock) – 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) – 1000: Announce – 1001: Management – 1010: Signaling – 1011–1110: Reserved – 1111: PTP packet with Reserved message type These bits are available only when you select the timestamp feature. 11:8 DocID029587 Rev 3 2767/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 530. RDES1 normal descriptor (write-back format)(1) (continued) Bit Name Description 7 IPCE IP Payload Error When this bit is set, it indicates either of the following: – The 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) calculated by the MAC does not match the corresponding checksum field in the received segment. – The TCP, UDP, or ICMP segment length does not match the payload length value in the IP Header field. – The TCP, UDP, or ICMP segment length is less than minimum allowed segment length for TCP, UDP, or ICMP. Bit 15 (ES) of RDES3 is not set when this bit is set. 6 IPCB IP Checksum Bypassed This bit indicates that the checksum offload engine is bypassed. 5 IPV6 IPv6 header Present This bit indicates that an IPV6 header is detected. 4 IPV4 IPV4 Header Present This bit indicates that an IPV4 header is detected. IPHE IP Header Error When this bit is set, it indicates either of the following: – The 16-bit IPv4 header checksum calculated by the MAC does not match the received checksum bytes. – The IP datagram version is not consistent with the Ethernet Type value. – Ethernet packet does not have the expected number of IP header bytes. This bit is valid when either bit 5 or bit 4 is set. PT Payload Type These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive Checksum Offload Engine (COE): – 000: Unknown type or IP/AV payload not processed – 001: UDP – 010: TCP – 011: ICMP – Others: reserved. If the COE does not process the payload of an IP datagram because there is an IP header error or fragmented IP, it sets these bits to 3'b000. 3 2:0 1. The Status fields in write-back format are valid only for the last descriptor (RDES3[28] is set). • RDES2 normal descriptor (write-back format) 31 30 29 L3L4FM 15 VF 2768/3178 14 28 27 26 25 24 L4FM L3FM 13 12 Reserved 11 23 22 21 20 19 MADRM 10 9 8 ARPRN DocID029587 Rev 3 7 6 5 4 Reserved 3 18 17 16 HF DAF SAF 2 1 0 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 531. RDES2 normal descriptor (write-back format) Bit Name Description L3L4FM Layer 3 and Layer 4 Filter Number Matched These bits indicate the number of the Layer 3 and Layer 4 Filter that matched the received packet: – 000: Filter 0 – 001: Filter 1 – 010: Filter 2 – 011: Filter 3 – 100: Filter 4 – 101: Filter 5 – 110: Filter 6 – 111: Filter 7 This field is valid only when bit 28 or bit 27 is set high. When more than one filter matches, these bits give the number of lowest filter. L4FM Layer 4 Filter Match When this bit is set, it indicates that the received packet matches one of the enabled Layer 4 Port Number fields. This status is given only when one of the following conditions is true: – Layer 3 fields are not enabled and all enabled Layer 4 fields match – All enabled Layer 3 and Layer 4 filter fields match When more than one filter matches, this bit gives the layer 4 filter status of filter indicated by bits[31:29]. L3FM Layer 3 Filter Match When this bit is set, it indicates that the received packet matches one of the enabled Layer 3 IP Address fields. This status is given only when one of the following conditions is true: – All enabled Layer 3 fields match and all enabled Layer 4 fields are bypassed – All enabled filter fields match When more than one filter matches, this bit gives the layer 3 filter status of filter indicated by bits[31:29]. 26:19 MADRM MAC Address Match or Hash Value When the HF bit is reset, this field contains the MAC address register number that matched the Destination address of the received packet. This field is valid only if the DAF bit is reset. When the HF bit is set, this field contains the Hash value computed by the MAC. A packet passes the Hash filter when the bit corresponding to the Hash value is set in the Hash filter register. 18 HF Hash Filter Status When this bit is set, it indicates that the packet passed the MAC address Hash filter. its[26:19] indicate the Hash value. 17 DAF Destination Address Filter Fail When this bit is set, it indicates that the packet failed the DA Filter in the MAC. 31:29 28 27 DocID029587 Rev 3 2769/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 531. RDES2 normal descriptor (write-back format) (continued) Bit Name 16 SAF 15 VF 14:11 Reserved • Description SA Address Filter Fail When this bit is set, it indicates that the packet failed the SA Filter in the MAC. VLAN Filter Status When this bit is set, it indicates that the VLAN Tag of received packet passed the VLAN filter. 10 ARPNR 9:0 Reserved ARP Reply Not Generated When this bit is set, it indicates that the MAC did not generate the ARP Reply for received ARP Request packet. This bit is set when the MAC is busy transmitting ARP reply to earlier ARP request (only one ARP request is processed at a time). RDES3 normal descriptor (write-back format) 31 30 29 28 27 26 25 24 23 22 21 20 19 OWN CTXT FD LD RS2V RS1V RS0V CE GP RWT OE RE DE 15 14 13 12 11 10 9 8 7 6 5 4 3 ES 18 17 16 LT 2 1 0 PL Table 532. RDES3 normal descriptor (write-back format) Bit Description OWN Own bit 1: The DMA owns the descriptor. 0: The application owns the descriptor. The DMA clears this bit when either of the following conditions is true: – The DMA completes the packet reception – The buffers associated with the descriptor are full CTXT Receive Context Descriptor When this bit is set, it indicates that the current descriptor is a context type descriptor. The DMA writes 0 to this bit for normal receive descriptor. 29 FD First Descriptor When this bit is set, it indicates that this descriptor contains the first buffer of the packet. If the size of the first buffer is 0, the second buffer contains the beginning of the packet. If the size of the second buffer is also 0, the next descriptor contains the beginning of the packet. 28 LD Last Descriptor When this bit is set, it indicates that the buffers to which this descriptor is pointing are the last buffers of the packet. 31 30 2770/3178 Name DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 532. RDES3 normal descriptor (write-back format) (continued) Bit 27 26 25 24 23 22 Name Description RS2V Receive Status RDES2 Valid When this bit is set, it indicates that the status in RDES2 is valid and it is written by the DMA. This bit is valid only when the LD bit of RDES3 is set. RS1V Receive Status RDES1 Valid When this bit is set, it indicates that the status in RDES1 is valid and it is written by the DMA. This bit is valid only when the LD bit of RDES3 is set. RS0V Receive Status RDES0 Valid When this bit is set, it indicates that the status in RDES0 is valid and it is written by the DMA. This bit is valid only when the LD bit of RDES3 is set. CE CRC Error When this bit is set, it indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received packet. This field is valid only when the LD bit of RDES3 is set. GP Giant Packet When this bit is set, it indicates that the packet length exceeds the specified maximum Ethernet size of 1518, 1522, or 2000 bytes (9018 or 9022 bytes if jumbo packet enable is set). Note: Giant packet indicates only the packet length. It does not cause any packet truncation. RWT Receive Watchdog Timeout When this bit is set, it indicates that the Receive Watchdog Timer has expired while receiving the current packet. The current packet is truncated after watchdog timeout. 21 OE Overflow Error When this bit is set, it indicates that the received packet is damaged because of buffer overflow in Rx FIFO. Note: This bit is set only when the DMA transfers a partial packet to the application. This happens only when the Rx FIFO is operating in the threshold mode. In the store-and-forward mode, all partial packets are dropped completely in Rx FIFO. 20 RE Receive Error When this bit is set, it indicates that the ETH_RX_ER signal is asserted while the ETH_RX_DV signal is asserted during packet reception. DE Dribble Bit Error When this bit is set, it indicates that the received packet has a noninteger multiple of bytes (odd nibbles). This bit is valid only in the MII Mode. 19 DocID029587 Rev 3 2771/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 532. RDES3 normal descriptor (write-back format) (continued) Bit 18:16 15 14:0 2772/3178 Name Description LT Length/Type Field This field indicates if the packet received is a length packet or a type packet. The encoding of the 3 bits is as follows: – 000: The packet is a length packet – 001: The packet is a type packet. – 011: The packet is a ARP Request packet type – 100: The packet is a type packet with VLAN Tag – 101: The packet is a type packet with Double VLAN Tag – 110: The packet is a MAC Control packet type – 111: The packet is a OAM packet type – 010: Reserved ES Error Summary – When this bit is set, it indicates the logical OR of the following bits: – RDES3[24]: CRC Error – RDES3[19]: Dribble Error – RDES3[20]: Receive Error – RDES3[22]: Watchdog Timeout – RDES3[21]: Overflow Error – RDES3[23]: Giant Packet This field is valid only when the LD bit of RDES3 is set. PL Packet Length These bits indicate the byte length of the received packet that was transferred to system memory (including CRC). This field is valid when the LD bit of RDES3 is set and either the Descriptor Error (RDES3[13]) or Overflow Error bits are reset. The packet length also includes the two bytes appended to the Ethernet packet when IP checksum calculation is enabled and the received packet is not a MAC control packet. This field is valid when the LD bit of RDES3 is set. When the Last Descriptor and Error Summary bits are not set, this field indicates the accumulated number of bytes that have been transferred for the current packet. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Receive context descriptor This descriptor is read-only for the application. This descriptor can be written only by the DMA. The context descriptor provides information about the extended status related to the last received packet. Bit 30 of RDES3 indicates the context type descriptor. Figure 796 shows the format for Receive context descriptors. Table 533 to Table 536 provide a detailed description of all Receive context descriptors. Figure 796. Receive context descriptor 5'(6 7LPHVWDPS/RZ> @ 5'(6 7LPHVWDPS+LJK> @ 5HVHUYHG &7;7 5'(6 2:1 5'(6 5HVHUYHG> @ 06Y 9 • RDES0 context descriptor Table 533. RDES0 context descriptor Bit 31:0 Name Description Receive Packet Timestamp Low RTSL The DMA updates this field with least significant 32 bits of the timestamp captured for corresponding Receive packet. When this field and the RTSH field of RDES1 show all-ones value, the timestamp must be considered as corrupt. DocID029587 Rev 3 2773/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller • RM0433 RDES1 context descriptor Table 534. RDES1 context descriptor Bit 31:0 • Field Description Receive Packet Timestamp High RTSH The DMA updates this field with most significant 32 bits of the timestamp captured for corresponding receive packet. When this field and the RTSL field of RDES0 show all-ones value, the timestamp must be considered as corrupt. RDES2 context descriptor Table 535. RDES2 context descriptor • Bit Description 31:0 Reserved RDES3 context descriptor Table 536. RDES3 context descriptor Bit Description 31 OWN Own Bit 1; The DMA owns the descriptor 0: The application owns the descriptor. The DMA clears this bit when either of the following conditions is true: – The DMA completes the packet reception – The buffers associated with the descriptor are full 30 CTXT Receive Context Descriptor When this bit is set, it indicates that the current descriptor is a context descriptor. The DMA writes 1'b1 to this bit for context descriptor. 29:0 2774/3178 Name Reserved DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller 58.11 Ethernet registers 58.11.1 Ethernet registers maps This section provides the following register maps: 58.11.2 • DMA registers (see Section 58.11.2: Ethernet DMA registers) • MTL registers (see Section 58.11.3: Ethernet MTL registers) • MAC registers including MMC register (see Section 58.11.4: Ethernet MAC and MMC registers) Ethernet DMA registers DMA mode register (ETH_DMAMR) Address offset: 0x1000 Reset value: 0x0000 0000 The DMA mode register establishes the bus operating modes for the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17 16 INTM[1:0] rw 15 Res. 14 13 12 11 10 9 8 7 6 5 PR[2:0] TXPR Res. Res. Res. Res. Res. Res. r r 4 3 Res. 2 1 0 DA SWR r rw Bits 31:18 Reserved, must be kept at reset value. Bits 17:16 INTM[1:0]: Interrupt Mode This field defines the interrupt mode of the Ethernet peripheral. The behavior of the interrupt signal and of the RI/TI bits in the ETH_DMACSR register changes depending on the INTM value (refer to Table 512: Transfer complete interrupt behavior). Bit 15 Reserved, must be kept at reset value. DocID029587 Rev 3 2775/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 14:12 Bit 11 Bits 10:2 2776/3178 RM0433 PR[2:0]: Priority ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. 000: The priority ratio is 1:1 001: The priority ratio is 2:1 010: The priority ratio is 3:1 011: The priority ratio is 4:1 100: The priority ratio is 5:1 101: The priority ratio is 6:1 110: The priority ratio is 7:1 111: The priority ratio is 8:1 TXPR: Transmit priority When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus. Reserved, must be kept at reset value. Bit 1 DA: DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: 0: Weighted Round-Robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit. 1: Fixed priority The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path. Bit 0 SWR: Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all clock domains. Before reprogramming any register, a value of zero should be read in this bit. Note: The reset operation is complete only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller System bus mode register (ETH_DMASBMR) Address offset: 0x1004 Reset value: 0x0101 0000 The System bus mode register controls the behavior of the AHB master. It mainly controls burst splitting and number of outstanding requests. 31 30 29 28 27 26 25 Res. Res. Res. Res. 15 14 13 12 11 10 9 RB MB Res. AAL Res. Res. Res. r r 24 23 22 21 20 Res. Res. Res. Res. 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. rw 19 18 17 16 2 1 0 Res. Res. FB Res. rw Bit 31 Reserved, must be kept at reset value. Bits 29:28 Reserved, must be kept at reset value. Bits 23:16 Reserved, must be kept at reset value. Bit 15 RB: Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. Bit 14 MB: Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the AHB master performs fixed burst transfers (INCRx and SINGLE). Bit 13 Bit 12 Bits 11:1 Bit 0 Reserved, must be kept at reset value. AAL: Address-Aligned Beats When this bit is set to 1, the master performs address-aligned burst transfers on Read and Write channels. Reserved, must be kept at reset value. FB: Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers of specified length (INCRx or SINGLE). When this bit is set to 0, the AHB master will initiate transfers of unspecified length (INCR) or SINGLE transfers. DocID029587 Rev 3 2777/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Interrupt status register (ETH_DMAISR) Address offset: 0x1008 Reset value: 0x0000 0000 The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels, MTL queues, and the MAC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MACIS MTLIS r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DC0IS r Bits 31:18 Bit 17 MACIS: MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. Bit 16 MTLIS: MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. Bits 15:1 Bit 0 2778/3178 Reserved Reserved, must be kept at reset value. DC0IS: DMA Channel Interrupt Status This bit indicates an interrupt event in DMA Channel. To reset this bit to 0, the software must read the corresponding register in DMA Channel to get the exact cause of the interrupt and clear its source. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Debug status register (ETH_DMADSR) Address offset: 0x100C Reset value: 0x0000 0000 The Debug status register gives the Receive and Transmit process status for DMA Channel for debugging purpose. 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 TPS0[3:0] RPS0[3:0] r r Bits 31:16 Bits 15:12 Bits 11:8 Bits 7:1 23 22 21 20 19 18 Res. 17 16 Res. 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. AXW HSTS r Reserved, must be kept at reset value. TPS0[3:0]: DMA Channel Transmit Process State This field indicates the Tx DMA FSM state for Channel: 000: Stopped (Reset or Stop Transmit Command issued) 001: Running (Fetching Tx Transfer Descriptor) 010: Running (Waiting for status) 011: Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 100: Timestamp write state 101: Reserved for future use 110: Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 111: Running (Closing Tx Descriptor) The MSB of this field always returns 0. This field does not generate an interrupt. RPS0[3:0]: DMA Channel Receive Process State This field indicates the Rx DMA FSM state for Channel: 000: Stopped (Reset or Stop Receive Command issued) 001: Running (Fetching Rx Transfer Descriptor) 010: Reserved for future use 011: Running (Waiting for Rx packet) 100: Suspended (Rx Descriptor Unavailable) 101: Running (Closing the Rx Descriptor) 110: Timestamp write state 111: Running (Transferring the received packet data from the Rx buffer to the system memory) The MSB of this field always returns 0. This field does not generate an interrupt. Reserved, must be kept at reset value. DocID029587 Rev 3 2779/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bit 0 RM0433 AXWHSTS: AHB Master Write Channel When high, this bit indicates that the write channel of the AHB master FMSs are in nonidle state. Channel control register (ETH_DMACCR) Address offset: 0x1100 Reset value: 0x0000 0000 The DMA Channel Control register specifies the MSS value for segmentation, length to skip between two descriptors, and also the features such as header splitting and 8xPBL mode. 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20 19 18 DSL[2:0] 17 16 Res. PBL X8 rw 15 14 13 Res. Res. 12 11 10 9 8 7 6 5 4 3 rw 2 1 0 MSS[13:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:21 Reserved, must be kept at reset value. Bits 20:18 Bit 17 Bit 16 Bits 15:14 Bits 13:0 2780/3178 DSL[2:0]: Descriptor Skip Length This bit specifies the 32-bit word number to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous. Reserved, must be kept at reset value. PBLX8: 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in ETH_DMACTxCR is multiplied eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. Reserved, must be kept at reset value. MSS[13:0]: Maximum Segment Size This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of ETH_DMACTxCR register is set. The value programmed in this field must be more than the configured Data width in bytes. It is recommended to use a MSS value of 64 bytes or more. This field is reserved when the Enable TCP Segmentation Offloading for TCP/IP Packets option is not selected. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Channel transmit control register (ETH_DMACTxCR) Address offset: 0x1104 Reset value: 0x0000 0000 The DMA Channel Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights. 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 Res. 23 22 Res. Res. 21 20 19 18 17 16 1 0 TXPBL[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. TSE Res. Res. Res. Res. Res. Res. Res. OSF rw rw Bits 31:22 Bits 21:16 Bits 15:13 Bit 12 Bits 11:5 Bit 4 Bits 3:1 rw 3 2 Res. ST rw Reserved, must be kept at reset value. TXPBL[5:0]: Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: 1. Set the PBLx8 mode in ETH_DMACCR. 2. Set the PBL. Reserved, must be kept at reset value. TSE: TCP Segmentation Enabled When this bit is set, the DMA performs the TCP segmentation for packets in Channel i. The TCP segmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor. When this bit is set, the TxPBL value must be greater than or equal to 4. This field is reserved if Enable TCP Segmentation Offloading for TCP/IP Packets option is not selected. Reserved, must be kept at reset value. OSF: Operate on Second Packet When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. Reserved, must be kept at reset value. DocID029587 Rev 3 2781/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bit 0 2782/3178 RM0433 ST: Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the following positions: – The current position in the list: this is the base address of the Transmit list set by the ETH_DMACTxDLAR register. – The position at which the transmission was previously stopped If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the ETH_DMACSR is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the ETH_DMACTxDLAR register, the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program ETH_DMACTxDLAR register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Channel receive control register (ETH_DMACRxCR) Address offset: 0x1108 Reset value: 0x0000 0000 The DMA Channel Receive Control register controls the Rx features such as PBL, buffer size, and extended status. 31 30 29 28 RPF Res. Res. Res. 27 26 25 24 Res. 23 22 Res. Res. 21 20 19 17 16 1 0 RXPBL[5:0] rw 15 18 rw 14 13 Res. Bit 31 Bits 30:22 Bits 21:16 Bit 15 Bits 14:4 12 11 10 9 8 7 6 5 4 3 2 RBSZ SR rw rw RPF: DMA Rx Channel Packet Flush When this bit is set to 1, the DMA will automatically flush the packet from the Rx queues destined to DMA Rx Channel when the DMA Rx Channel is stopped after a system bus error has occurred. The flushing happens on the Read side of the Rx queue. When this bit is set to 0 the EQOS will not flush the packet in the Rx queue destined to DMA Rx Channel after the DMA is stopped due to a system bus error. Reserved, must be kept at reset value. RXPBL[5:0]: Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: 1. Set the PBLx8 mode in the ETH_DMACCR. 2. Set the PBL. Reserved, must be kept at reset value. RBSZ: Receive Buffer size This field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16 Kbytes. The buffer size is applicable to payload buffers when split headers are enabled. Note: The buffer size must be a multiple of 4, 8, or 16 depending on the bus widths (32, 64, or 128 respectively). This is required even if the value of buffer address pointer is not aligned to bus width. If the buffer size is not a multiple of 4, 8, or 16, it may result into undefined behavior. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and the DMA internally takes the LSB bits as all-zero. Therefore, these LSB bits are readonly (RO). DocID029587 Rev 3 2783/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 3:1 Bit 0 2784/3178 RM0433 Reserved, must be kept at reset value. SR: Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: – The current position in the list: this is the address set by the ETH_DMACRxDLAR register. – The position at which the Rx process was previously stopped If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the ETH_DMACSR is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the ETH_DMACRxDLAR register, the DMA behavior is unpredictable. When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Channel Tx descriptor list address register (ETH_DMACTxDLAR) Address offset: 0x1114 Reset value: 0x0000 0000 Channel Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be word-aligned. The DMA internally converts it to bus width aligned address by making the corresponding LSB to low. You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in ETH_DMACiTxCR register. When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address. If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDESLA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. TDESLA rw rw rw Bits 31:2 Bits 1:0 rw rw rw rw rw rw rw rw rw rw rw TDESLA: Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). The width of this field depends on the configuration: 31:2 for 32-bit configuration Reserved, must be kept at reset value. DocID029587 Rev 3 2785/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Channel Rx descriptor list address register (ETH_DMACRxDLAR) Address offset: 0x111C Reset value: 0x0000 0000 The Channel Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory space of the application and must be word-aligned. The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given. You can write to this register only when Rx DMA has stopped, that is, SR bit is set to zero in ETH_DMACRxCR register. When stopped, this register can be written with a new descriptor list address. When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDESLA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. RDESLA rw rw rw Bits 31:2 Bits 1:0 2786/3178 rw rw rw rw rw rw rw rw rw rw rw RDESLA[28:0]: Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO). The width of this field depends on the configuration: 31:2 for 32-bit configuration Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Channel Tx descriptor tail pointer register (ETH_DMACTxDTPR) Address offset: 0x1120 Reset value: 0x0000 0000 The ChannelTx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. TDT rw rw rw Bits 31:2 Bits 1:0 rw rw rw rw rw rw rw rw rw rw rw TDT: Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers. The width of this field depends on the configuration: 31:2 for 32-bit configuration Reserved, must be kept at reset value. DocID029587 Rev 3 2787/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Channel Rx descriptor tail pointer register (ETH_DMACRxDTPR) Address offset: 0x1128 Reset value: 0x0000 0000 The Channel Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res . Res . RDT rw Bits 31:2 Bits 1:0 rw rw rw rw rw rw rw rw rw rw rw rw rw RDT: Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors referenced between the head and the tail pointer registers. The width of this field depends on the configuration: 31:2 for 32-bit configuration Reserved, must be kept at reset value. Channel Tx descriptor ring length register (ETH_DMACTxRLR) Address offset: 0x112C Reset value: 0x0000 0000 The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. TDRL[9:0] rw Bits 31:10 2788/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 9:0 TDRL[9:0]: Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. Channel Rx descriptor ring length register (ETH_DMACRxRLR) Address offset: 0x1130 Reset value: 0x0000 0000 The Channel Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. RDRL[9:0] rw Bits 31:10 Bits 9:0 Reserved, must be kept at reset value. RDRL[9:0]: Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Channel interrupt enable register (ETH_DMACIER) Address offset: 0x1134 Reset value: 0x0000 0000 The Channel Interrupt Enable register enables the interrupts reported by the Status register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res . Res . Res . Res. Res. Re s. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NIE AIE CDEE FBEE ERIE ETIE RWTE RSE RBUE RIE Res . Res . Res . TBUE TXSE TIE rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. DocID029587 Rev 3 2789/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bit 15 NIE: Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the ETH_DMACSR: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt When this bit is reset, the normal interrupt summary is disabled. Bit 14 AIE: Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the ETH_DMACSR: Bit 1: Transmit Process Stopped Bit 7: Rx Buffer Unavailable Bit 8: Receive Process Stopped Bit 9: Receive Watchdog Timeout Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error When this bit is reset, the abnormal interrupt summary is disabled. Bit 13 CDEE: Context Descriptor Error Enable When this bit is set along with the AIE bit, the Context Descriptor error interrupt is enabled. When this bit is reset, the Context Descriptor error interrupt is disabled. Bit 12 FBEE: Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled. Bit 11 ERIE: Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled. Bit 10 ETIE: Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled. Bit 9 RWTE: Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled. Bit 8 RSE: Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled. Bit 7 RBUE: Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled. Bit 6 RIE: Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. Bits 5:3 2790/3178 RM0433 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 2 TBUE: Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled. Bit 1 TXSE: Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled. Bit 0 TIE: Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. DocID029587 Rev 3 2791/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Figure 797. Generation of ETH_DMAISR flags 45;2 $1' 45;2,( 07/,6 25 47;8 $1' 47;8,( 00&5;,6 00&7;,6 00&5;,3,6 *3,,6 *3,,( 5;676,6 5;676,( 7;676,6 7;676,( 76,6 76,( /3,,6 /3,,( 3076,6 3076,( 3+<,6 3+<,( 00&,6 25 00&,( $1' $1' $1' $1' $1' 0$&,6 $1' $1' 3&6$1&,( $1' 3&6/&+*,6 $1' 3&6/&+*,( 5*60,,,6 $1' 5*60,,,( 7, (5( $1' (5, 25 1,6 1,( $1' $1' '&,6 736 76( )%( 25 $1' )%, VEGBLQWUBR $1' 3&6$1&,6 7,( 25 25 $1' 25 $,6 $,( $1' 06Y9 2792/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Channel Rx interrupt watchdog timer register (ETH_DMACRxIWTR) Address offset: 0x1138 Reset value: 0x0000 0000 The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value, it enables the watchdog timer for the RI bit of the ETH_DMACSR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. RWT[7:0] rw Bits 31:8 Bits 7:0 Reserved, must be kept at reset value. RWT[7:0]: Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the ETH_DMACSR, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet. Channel current application transmit descriptor register (ETH_DMACCATxDR) Address offset: 0x1144 Reset value: 0x0000 0000 The Channel Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CURTDESAPTR r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CURTDESAPTR r r r r r r r r r DocID029587 Rev 3 2793/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:0 RM0433 CURTDESAPTR[31:0]: Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset. Channel current application receive descriptor register (ETH_DMACCARxDR) Address offset: 0x114C Reset value: 0x0000 0000 The Channel Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CURRDESAPTR r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CURRDESAPTR r r r Bits 31:0 r r r r r r CURRDESAPTR[31:0]: Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset. Channel current application transmit buffer register (ETH_DMACCATxBR) Address offset: 0x1154 Reset value: 0x0000 0000 The Channel Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CURTBUFAPTR r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CURTBUFAPTR r r r Bits 31:0 2794/3178 r r r r r r CURTBUFAPTR[31:0]: Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Channel current application receive buffer register (ETH_DMACCARxBR) Address offset: 0x115C Reset value: 0x0000 0000 The Channel Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CURRBUFAPTR r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CURRBUFAPTR r r r Bits 31:0 r r r r r r CURRBUFAPTR[31:0]: Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset. Channel status register (ETH_DMACSR) Address offset: 0x1160 Reset value: 0x0000 0000 The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 REB[2:0] TEB[2:0] r r 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NIS AIS CDE FBE ERI ETI RWT RPS RBU RI Res. Res. Res. TBU TPS TI rw rw rw rw rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 2795/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 31:22 Reserved, must be kept at reset value. Bits 21:19 REB[2:0]: Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. Bit 21 1: Error during data transfer by Rx DMA 0: No Error during data transfer by Rx DMA Bit 20 1: Error during descriptor access 0: Error during data buffer access Bit 19 1: Error during read transfer 0: Error during write transfer This field is valid only when the FBE bit is set. This field does not generate an interrupt. Bits 18:16 TEB[2:0]: Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. Bit 18 1: Error during data transfer by Tx DMA 0: No Error during data transfer by Tx DMA Bit 17 1: Error during descriptor access 0: Error during data buffer access Bit 16 1: Error during read transfer 0: Error during write transfer This field is valid only when the FBE bit is set. This field does not generate an interrupt. Bit 15 2796/3178 NIS: Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the ETH_DMACIER register: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in ETH_DMACIER register) affect the Normal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 14 AIS: Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMACIER register: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. Bit 13 CDE: Context Descriptor Error This bit indicates that the DMA Tx engine received a context descriptor in the middle of a packet (in an intermediate descriptor), and the DMA Tx engine ignored it. Bit 12 FBE: Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. Bit 11 ERI: Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet. The RI bit of this register automatically clears this bit. Bit 10 ETI: Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. Bit 9 RWT: Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. Bit 8 RPS: Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Bit 7 RBU: Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. Bit 6 RI: Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES1 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. The reception remains in the Running state. Bits 5:3 Reserved, must be kept at reset value. DocID029587 Rev 3 2797/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 2 TBU: Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit Process state transitions. To resume processing the Transmit descriptors, the application should do the following: 1. Change the ownership of the descriptor by setting Bit 31 of TDES3. 2. Issue a Transmit Poll Demand command. For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel. Bit 1 TPS: Transmit Process Stopped This bit is set when the transmission is stopped. Bit 0 TI: Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. Channel missed frame count register (ETH_DMACMFCR) Address offset: 0x116C Reset value: 0x0000 0000 This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programing RPF field in ETH_DMACRxCR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFCO Res. Res. Res. Res. r r r r r r MFC[10:0] r Bits 31:16 Bit 15 Bits 14:11 Bits 10:0 2798/3178 r r r r r Reserved, must be kept at reset value. MFCO: Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Reserved, must be kept at reset value. MFC[10:0]: Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in ETH_DMACRxCR register. The counter gets cleared when this register is read. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA register map and reset values DA SWR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 0 0 0 0 0 0 0 0 0x1010 0x101C AXWHSTS Res. Res. Res. Res. Res. Res. Res. TPS0 RPS0 0 Res. Res. ETH_DMADSR Res. Res. Res. Res. Res. Res. Res. Res. 0 0 DC0IS 0 FB TXPR PR[2:0] AAL Res. RB MB 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETH_DMAISR Reset value 0x100C 0 0 0 0 0 0 0 1 0 0 MACIS MTLIS Reset value 0x1008 RD_OSR_LMT[1:0] Res. Res. Res. Res. ETH_DMASBMR Res. 0x1004 0 0 Res. Res. Res. Res. Reset value Res. INTM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETH_DMAMR Res. 0x1000 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 537. ETH_DMA common register map and reset values 0 Reserved *** 0x110C 01110 Res. Res. PBLX8 Res. Res. Res. Res. Res. Res. Res. Res. OSF 0 0 RXPBL[5:0] 0 0 0 0 0 0 R e s . RBSZ[10:0] 0 0 0 0 0 0 0 0 0 0 0 ST 0 0 0 0 0 0 0 0 TXPBL[5:0] Res. RPF Reset value Res. Res. Res. ETH_ DMACRxCR R e s . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. TSE Res. R e s . 0 MSS IPBL Res. Reset value 0x1108 DSL 0 0 0 Res. Res. 0x1104 ETH_ DMACTxCR Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. ETH_DMACCR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1100 Register name Res. Offset Res. Table 538. ETH_DMA_CH register map and reset values R e s . R e S s R . 0 0 R e s . Reserved DocID029587 Rev 3 2799/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Register name 0x1114 ETH_ DMACTxDLAR Reset value 0x1118 RDESLA Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_ DMACTxDTPR TDT Reset value Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved RDT Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 Reserved 0x1140 ETH_ DMACCATxDR Reset value 0x1148 0x0114C ETH_ DMACCARxDR Reset value 0x1150 0x1154 ETH_ DMACCATxBR Reset value 0x1158 0x115C 0x1160 ETH_ DMACCARxBR Reset value ETH_DMACSR Reset value 2800/3178 0 0 0 RWT[7:0] 0 0 0 0 0 0 0 0 CURTDESAPTR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved CURRDESAPTR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved CURTBUFAPTR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved CURRBUFAPTR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x1144 Res. Res. Res. Res. Res. Res. Res. Res. ETH_ DMACRxIWTR RWTU[1:0] 0x1138 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value REB[2: 0] TEB[2: 0] NIS AIS CDE FBE ERI ETI RWT RPS RBU RI ETH_DMACIER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x1134 0 0 0 0 0 0 0 0 0 0 NIE AIE CDEE FBEE ERIE ETIE RWTE RSE RBUE RIE Reset value RDRL[9:0] TBUE TXSE TIE 0x1130 ETH_ DMACRxDRLR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value TDRL[9:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID029587 Rev 3 TBU TPS TI ETH_ DMACTxDRLR Res. Res. ETH_ DMACRxDTPR Res. Res. Res. 0x112C Res. Res. ETH_ DMACRxDLAR 0x1124 0x1128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Res. Res. Res. 0x1120 TDESLA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x111C Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 538. ETH_DMA_CH register map and reset values (continued) 0 0 0 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Register name 0x1164 0x1168 Reset value 0 Res. Res. Res. Res. ETH_ DMACMFCR MFCO 0x116C Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 538. ETH_DMA_CH register map and reset values (continued) MFC[10:0] 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 2801/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller 58.11.3 RM0433 Ethernet MTL registers Operating mode Register (ETH_MTLOMR) Address offset: 0x0C00 Reset value: 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. CNTPRST Res. Res. Res. Res. DTXSTS Res. rw rw Bits 31:10 2802/3178 Res. 31 CNTCLR The Operating Mode register establishes the Transmit and Receive operating modes and commands. rw Reserved, must be kept at reset value. Bit 9 CNTCLR: Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. If this bit is set along with CNT_PRESET bit, CNT_PRESET has precedence. Bit 8 CNTPRST: Counters Preset When this bit is set: – ETH_MTLTxQUR register is initialized/preset to 0x7F0. – Missed Packet and Overflow Packet counters in ETH_MTLRxQMPOCR register is initialized/preset to 0x7F0 Bit 7 Reserved, must be kept at reset value. Bits 6:2 Reserved, must be kept at reset value. Bit 1 DTXSTS: Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset, the Tx packet status received from the MAC is forwarded to the application. This bit is reserved and read-only when the Disable Transmit Status in MTL feature is selected while configuring the core. Bit 0 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Interrupt status Register (ETH_MTLISR) Address offset: 0x0C20 Reset value: 0x0000 0000 The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Q0IS r Bits 31:1 Bit 0 Reserved, must be kept at reset value. Q0IS: Queue interrupt status This bit indicates that an interrupt has been generated by Queue. To reset this bit, read ETH_MTLQICSR register to identify the interrupt cause and clear the source. Tx queue operating mode Register (ETH_MTLTxQOMR) Address offset: 0x0D00 Reset value: 0x0007 0008 The Queue Transmit Operating Mode register establishes the Transmit queue operating modes and commands. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 24 23 22 21 20 19 18 17 16 TQS rw rw rw rw rw rw rw rw rw 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 TTC[2:0] TXQEN[1:0] TSF FTQ rw r rw rw 2803/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 31:25 Reserved, must be kept at reset value. Bits 24:16 TQS: Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The sixteenth bit is the starting bit of this field. The width of this field depends on the Tx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits: LOG2(2048/256) = LOG2(8) = 3 bits TQS = 0 corresponds to 256 bytes. Bits 15:7 2804/3178 Reserved, must be kept at reset value. Bits 6:4 TTC[2:0]: Transmit Threshold Control These bits control the threshold level of the MTL Tx queue. The transmission starts when the packet size within the MTL Tx queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. 000: 32 001: 64 010: 96 011: 128 100: 192 101: 256 110: 384 111: 512 Bits 3:2 TXQEN[1:0]: Transmit Queue Enable This field is used to enable/disable the transmit queue. 00: Not enabled 01: Reserved 10: Enabled 11: Reserved Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field. Bit 1 TSF: Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped. Bit 0 FTQ: Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the ETH_MTLTxQOMR register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (eth_mii_tx_clk) should be active. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Tx queue underflow register (ETH_MTLTxQUR) Address offset: 0x0D04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. UFCNTOVF The Queue Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush UFFRMCNT[10:0] r r Bits 31:12 Reserved, must be kept at reset value. Bit 11 UFCNTOVF: Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened. Bits 10:0 UFFRMCNT[10:0]: Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read with mci_be_i[0] at 1'b1. DocID029587 Rev 3 2805/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Tx queue debug Register (ETH_MTLTxQDR) Address offset: 0x0D08 Reset value: 0x0000 0000 The Queue Transmit Debug register gives the debug status of various blocks related to the Transmit queue. 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 22 21 20 STXSTSF[2:0] 19 18 17 Res. 16 PTXQ[2:0] r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXSTS FSTS TXQ STS TWC STS TRCSTS[1:0] TXQPA USED r r r r r Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 STXSTSF[2:0]: Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. This field is reserved when the Disable Transmit Status in MTL feature is selected while configuring the core. When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of status words in Tx Status FIFO. Bit 19 Bits 18:16 Bits 15:6 2806/3178 Reserved, must be kept at reset value. PTXQ[2:0]: Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx queue. This field is reserved when the Disable Transmit Status in MTL feature is selected while configuring the core. When the DTXSTS bit of ETH_MTLOMR register is set to 1, this field does not reflect the number of packets in the Transmit queue. Reserved, must be kept at reset value. Bit 5 TXSTSFSTS: MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission. This field is reserved when the Disable Transmit Status in MTL feature is selected while configuring the core. Bit 4 TXQSTS: MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx queue is not empty and some data is left for transmission. Bit 3 TWCSTS: MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx queue Write Controller is active, and it is transferring the data to the Tx queue. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 2:1 Bit 0 TRCSTS[1:0]: MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the Packet Abort request from the MAC TXQPAUSED: Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx queue is in the Pause condition (in the full-duplex only mode) because of the following: – Reception of the PFC packet for the priorities assigned to the Tx queue when PFC is enabled – Reception of 802.3x Pause packet when PFC is disabled DocID029587 Rev 3 2807/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Queue interrupt control status Register (ETH_MTLQICSR) Address offset: 0x0D2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. RXOIE Res. Res. Res. Res. Res. Res. Res. RXOVFIS This register contains the interrupt enable and status bits for the queue interrupts. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. TXUIE Res. Res. Res. Res. Res. Res. Res TXUNFIS rw Res. rw rw rw rw rw Bits 31:25 Bit 24 Bits 23:17 Bit 16 Bits 15:9 Bit 8 Bits 7:1 Bit 0 2808/3178 Reserved, must be kept at reset value. RXOIE: Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled. Reserved, must be kept at reset value. RXOVFIS: Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit. Reserved, must be kept at reset value. TXUIE: Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled. Reserved, must be kept at reset value. TXUNFIS: Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Rx queue operating mode register (ETH_MTLRxQOMR) Address offset: 0x0D30 Reset value: 0x0070 0000 The Queue Receive operating Mode register establishes the Receive queue operating modes and command. 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 RFD1 RF0 Res. Res. Res. rw rw 10 22 21 20 RQS 19 18 17 16 Res. Res. Res. RFD2 r r r 7 6 5 4 3 2 RFA FUP 27 FEP 28 RSF 29 DIS_TCP_EF 30 EHFC 31 Res. rw rw rw rw rw rw 9 8 rw 1 0 RTC[1:0] rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 RQS[2:0]: Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx queues more than one and the reset value is 0x0. Bits 19:17 Reserved, must be kept at reset value. Bits 16:14 RFD[2:0]: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is deasserted after activation: 0: Full minus 1 Kbyte, that is, FULL 1 Kbyte 1: Full minus 1.5 Kbyte, that is, FULL 1.5 Kbyte 2: Full minus 2 Kbytes, that is, FULL 2 Kbytes 3: Full minus 2.5 Kbytes, that is, FULL 2.5 Kbytes 4: Full minus 2.5 Kbytes, that is, FULL 3 Kbytes 5: Full minus 2.5 Kbytes, that is, FULL 3.5 Kbytes The de-assertion is effective only after flow control is asserted. Note: The value must be programmed in such a way to make sure that the threshold is a positive number. When the EHFC is set high, these values are applicable only when the Rx queue size determined by the RQS field of this register, is equal to or greater than 4 Kbytes. For a given queue size, the values ranges between 0 and the encoding for FULL minus (QSIZE - 0.5 Kbyte) and all other values are illegal. Here the term FULL and QSIZE refers to the queue size determined by the RQS field of this register. Bits 13:11 Reserved, must be kept at reset value. DocID029587 Rev 3 2809/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 10:8 RFA[2:0]: Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field, see RFD. Bit 7 EHFC: Enable Hardware Flow Control When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx queue is less than 4 Kbytes. Bit 6 DIS_TCP_EF: Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC. When this bit is reset, all error packets are dropped if the FEP bit is reset. Bit 5 RSF: Receive Queue Store and Forward When this bit is set, the Ethernet peripheral reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register. Bit 4 FEP: Forward Error Packets When this bit is reset, the Rx queue drops packets with error status (CRC error, receive error, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped. When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA. Bit 3 FUP: Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01. Bit 2 Bits 1:0 2810/3178 RM0433 Reserved, must be kept at reset value. RTC[1:0]: Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): 00: 64 01: 32 10: 96 11: 128 The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred. This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Rx queue missed packet and overflow counter register (ETH_MTLRxQMPOCR) Address offset: 0x=0D34 Reset value: 0x0000 0000 The Queue missed packet and overflow counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow. 31 30 29 28 27 26 Res. Res. Res. Res. MISCN TOVF MISPKTCNT[10:0] r r 6 21 5 20 12 11 Res. Res. Res. Res. OVFCN TOVF OVFPKTCNT[10:0] r r Bits 15:12 7 22 13 Bits 26:16 8 23 14 Bit 27 9 24 15 Bits 31:28 10 25 4 19 18 17 16 3 2 1 0 Reserved, must be kept at reset value. MISCNTOVF: Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. MISPKTCNT[10:0]: Missed Packet Counter This field indicates the number of packets missed by the Ethernet peripheral because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability. Reserved, must be kept at reset value. Bit 11 OVFCNTOVF: Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Bits 10:0 OVFPKTCNT[10:0]: Overflow Packet Counter This field indicates the number of packets discarded by the Ethernet peripheral because of Receive queue overflow. This counter is incremented each time the Ethernet peripheral discards an incoming packet because of overflow. This counter is reset when this register is read with mci_be_i[0] at 1. DocID029587 Rev 3 2811/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Rx queue debug register (ETH_MTLRxQDR) Address offset: 0x0D38 Reset value: 0x0000 0000 The Queue Receive Debug register gives the debug status of various blocks related to the Receive queue. 31 30 Res. Res. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 PRXQ[13:0] 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r Bits 31:30 Bits 29:16 Bits 15:6 Bits 5:4 Bit 3 Bits 2:1 Bit 0 2812/3178 Res. RWCSTS 14 RRCSTS[1:0] 15 RXQSTS[1:0] r r r Reserved, must be kept at reset value. PRXQ[13:0]: Number of Packets in Receive Queue This field indicates the current number of packets in the Rx queue. The theoretical maximum value for this field is 256Kbyte/16bytes = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size. Reserved, must be kept at reset value. RXQSTS[1:0]: MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx queue: 00: Rx queue empty 01: Rx queue fill-level below flow-control deactivate threshold 10: Rx queue fill-level above flow-control activate threshold 11: Rx queue full Reserved, must be kept at reset value. RRCSTS[1:0]: MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: Flushing the packet data and status RWCSTS: MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx queue. DocID029587 Rev 3 0x0D08 0x0D2C ETH_MTLTxQD R 0x0D0C 0x0D14 0x0D18 0x0D28 Reset value ETH_MTLQICS R Reset value 0 0 0 PTXQ 0 0 0 0 DocID029587 Rev 3 0 0 0 TSF FTQ 0 0 Reset value TXQPAUSED 0 1 1 1 TTC [2:0] TXQEN[1:0] Reset value TRCSTS[1:0] TQS[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0C24 0x0CFC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXSTSFSTS TXQSTS TWCSTS Reset value ETH_MTLTxQU 0x0D04 R Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Q0TXOIE 0x0C04 0x0C1C Res. ETH_ MTLTxQOMR STXSTSF[2:0] 0x0D00 ETH_MTLISR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0C20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETH_MTLOMR DTXSTS Res. Res. Res. Res. Res. Register name Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNTCLR CNTPRST Res. 0x0C00 Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. RXOIE Res. Res. Res. Res. Res. Res. Res. RXOVFIS Res. Res. Res. Res. Res. Res. Res. TXUIE Res. Res. Res. Res. Res. Res. Res. TXUNFIS RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MTL register map and reset values Table 539. ETH_MTL register map and reset values 0 Reserved 0 Reserved 0 0 0 1 0 0 0 UFFRMCNT[10:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Reserved 0 0 2813/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0D30 ETH_ MTLRxQOMR Reset value 0xD3C to 0xD7C 0x0D68 Res. Res. Res. Res. OVFCNTOVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Reserved Refer to Section 2.2.2 on page 105 for the register boundary addresses. 2814/3178 DocID029587 Rev 3 0 0 RTC RWCSTS 0 0 0 0 0 0 0 0 0 0 0 0 RRCSTS[1:0] PRXQ[13:0] 0 0 OVFPKTCNT[10:0] Res. ETH_ MTLRxQDR 0 0 0 0 0 0 0 0 RXQSTS[1:0] 0x0D38 MISPKTCNT[10:0] 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Reset value 0 0 0 RFA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0D34 ETH_ MTLRxQMPOC R 1 1 1 Res. Res. Res. Res. MISCNTOVF Reset value RFD EHFC DIS_TCP_EF RSF FEP FUP Res. Register name Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. RQS2 RQS1 RQS0 Res. Res. Res. Table 539. ETH_MTL register map and reset values (continued) 0 0 0 RM0433 Ethernet MAC and MMC registers Operating mode configuration register (ETH_MACCR) Address offset: 0x0000 Reset value: 0x0000 0000 16 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 rw rw rw rw rw rw rw IPG[2:0] DocID029587 Rev 3 BL[1:0] rw rw DC rw 2 PRELEN[1:0] rw IPC rw ARPEN rw SARC[2:0] rw rw JE 17 JD 18 WD 19 ACS 20 CST 21 S2KP 22 GPSLCE 23 Res. 24 DR 25 DCRS 26 DO 27 ECRSFD 28 LM 29 DM 30 FES 31 Res. The MAC Configuration Register establishes the operating mode of the MAC. Res. 58.11.4 Ethernet (ETH): media access control (MAC) with DMA controller rw rw 1 0 TE RE rw rw 2815/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 31 ARPEN: ARP Offload Enable When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It will forward the ARP packet to the application and also indicate the events in the RxStatus. When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the RxStatus. This bit is available only when the Enable IPv4 ARP Offload is selected. Bits 30:28 SARC[2:0]: Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[29:28]: 0x: The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. 10: – If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (MAC registers 192 and 193) in the SA field of all transmitted packets. – If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected while configuring the core, the MAC inserts the content of the MAC Address 1 registers (MAC registers 194 and 195) in the SA field of all transmitted packets. 11: – If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (MAC registers 192 and 193) in the SA field of all transmitted packets. – If Bit 30 is set to 1 and the MAC Address Register 1 is enabled, the MAC replaces the content of the MAC Address 1 registers (MAC registers 194 and 195) in the SA field of all transmitted packets. Note: Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. These bits are reserved and RO when the Enable SA and VLAN Insertion on Tx feature is not selected while configuring the core. Bit 27 IPC: Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled. If the IP Checksum Offload feature is not enabled while configuring the core, this bit is reserved and RO (with default value). The Layer 3 and Layer 4 Packet Filter and Enable Split Header features automatically selects the IPC Full Checksum Offload Engine on the Receive side. When any of these features are enabled, you must set the IPC bit. 2816/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 26:24 IPG[2:0]: Inter-Packet Gap These bits control the minimum IPG between packets during transmission. 000: 96 bit times 001: 88 bit times 010: 80 bit times ... 111: 40 bit times This range of minimum IPG is valid in full-duplex mode. In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IPG. The above function (IPG less than 96 bit times) is valid only when EIPGEN bit in ETH_MACECR register is reset. When EIPGEN is set, then the minimum IPG (greater than 96 bit times) is controlled as per the description given in EIPG field in ETH_MACECR register. Bit 23 GPSLCE: Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the value in GPSL field in ETH_MACECR register to declare a received packet as Giant packet. This field must be programmed to more than 1,518 bytes. Otherwise, the MAC considers 1,518 bytes as giant packet limit. When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1,518 bytes (1522 bytes for tagged packet). The watchdog timeout limit, Jumbo Packet Enable and 2K Packet Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9,018 bytes (9,022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2,000 bytes with 2K Packet Enabled. The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status. Bit 22 S2KP: IEEE 802.3as Support for 2K Packets When this bit is set, the MAC considers all packets with up to 2,000 bytes length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2K bytes as Giant packets. When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1,518 bytes (1,522 bytes for tagged) as giant packets. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see Gaint Packet Status based on S2KP and JE Bits. Note: When the JE bit is set, setting this bit has no effect on the giant packet status. Bit 21 CST: CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. Note: For information about how the settings of the ACS bit and this bit impact the packet length, see Packet Length based on the CST and ACS Bits. DocID029587 Rev 3 2817/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 20 ACS: Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. All received packets with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming packets to the application, without any modification. Note: For information about how the settings of CST bit and this bit impact the packet length, see the Table, Packet Length based on the CST and ACS Bit. Bit 19 WD: Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes. When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes. Bit 18 Reserved, must be kept at reset value. Bit 17 JD: Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes. When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet. Bit 16 JE: Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. Bit 18 Reserved, must be kept at reset value. Bit 14 FES: MAC Speed This bit selects the speed in the 10/100 Mbps mode: 0: 10 Mbps 1: 100 Mbps In the 1000 Mbps-only configurations, this bit is read-only with the reset value. In the 10 or 100 Mbps-only or default 10/100 Mbps configurations, this bit is read-write. The mac_speed_o[0] signal reflects the value of this bit. Bit 13 DM: Duplex Mode When this bit is set, the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configurations. Bit 12 LM: Loopback Mode When this bit is set, the MAC operates in the loopback mode at MII. The MII Rx clock input (eth_mii_rx_clk) is required for the loopback to work properly. This is because the Tx clock is not internally looped back. Bit 11 ECRSFD: Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low. When this bit is reset, the MAC transmitter ignores the status of the CRS signal. 2818/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 10 DO: Disable Receive Own When this bit is set, the MAC disables the reception of packets when the ETH_TX_EN is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets given by the PHY. This bit is not applicable in the full-duplex mode. This bit is reserved and read-only (RO) with default value in the full-duplex-only configurations. Bit 9 DCRS: Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission. When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission. This bit is reserved and read-only (RO) in the full-duplex-only configurations. Bit 8 DR: Disable Retry When this bit is set, the MAC attempts only one transmission. When a collision occurs on the MII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status. When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the half-duplex mode. This bit is reserved and read-only (RO) in the fullduplex-only configurations. Bit 7 Reserved, must be kept at reset value. Bits 6:5 BL[1:0]: Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. 00: k= min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where - = retransmission attempt The random integer r takes the value in the range 0 <= r < 2^k This bit is applicable only in the half-duplex mode. This bit is reserved and read-only (RO) in the full-duplex-only configurations. Bit 4 DC: Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288 bit times in 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in the half-duplex mode. This bit is reserved and read-only (RO) in the full-duplex-only configurations. DocID029587 Rev 3 2819/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 3:2 PRELEN[1:0]: Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. 00: 7 bytes of preamble 01: 5 bytes of preamble 10: 3 bytes of preamble 11: Reserved Bit 1 TE: Transmitter Enable When this bit is set, the Tx state machine of the MAC is enabled for transmission on the MII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets. Bit 0 RE: Receiver Enable When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the MII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the MII interface. Table 540 shows how the settings of S2KP and JE bits of the ETH_MACCR register impact the giant packet status. Table 540. Giant Packet Status based on S2KP and JE Bits Length/Type Field Untagged packet VLAN tagged packet Received Packet Length S2KP JE Giant Packet Status > 1,518 0 0 1 > 2,000 1 0 1 > 9,018 x 1 1 > 1,522 0 0 1 > 2,000 1 0 1 > 9,022 x 1 1 Note: For all other combinations, the Giant Packet status is 0. Table 541 shows how the settings of the CST and ACS bits of the ETH_MACCR register impact whether CRC length is included in the packet length. 2820/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 541. Packet Length based on the CST and ACS bits Receive Checksum Offload Engine Received Packet Length IPCHKSUM_EN = 0 and IPC_FULL_OFFLOAD = 0 or IPCHKSUM_EN = 1 and IPC_FULL_OFFLOAD = 1 < 1,536 >= 1,536 < 1,536 IPCHKSUM_EN = 1 and IPC_FULL_OFFLOAD = 0 >= 1,536 CST ACS FCS Stripping Done x 0 No x 1 Yes (for Ethernet packets) 0 x No 1 x Yes (for Type packets) x 0 No x 1 Yes (for Ethernet packets) x x No Extended operating mode configuration register (ETH_MACECR) Address offset: 0x0004 Reset value: 0x0000 0000 10 9 EIPG[4:0] rw 13 12 11 24 23 22 rw 8 21 20 19 18 17 16 r 7 6 5 4 3 DCRCC 25 SPEN 26 USP Res. 27 Res. 14 28 RESERVED_HDSMS[2:0] Res. 15 29 Res. Res. 30 Res. 31 EIPGEN The MAC Extended Configuration Register establishes the operating mode of the MAC. rw rw rw 2 1 0 GPSL[13:0] rw DocID029587 Rev 3 2821/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 EIPG[4:0]: Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits), along with IPG field in ETH_MACCR, gives the minimum IPG greater than 96 bit times in steps of 8 bit times: {EIPG, IPG} 0x00:104 bit times 0x01: 112 bit times 0x02: 120 bit times .. 0xFF: 2144 bit times Bit 24 EIPGEN: Extended Inter-Packet Gap Enable When this bit is set, the MAC interprets EIPG field and IPG field in ETH_MACCR together as minimum IPG greater than 96 bit times in steps of 8 bit times. When this bit is reset, the MAC ignores EIPG field and interprets IPG field in ETH_MACCR as minimum IPG less than or equal to 96 bit times in steps of 8 bit times. Note: The extended Inter-Packet Gap feature must be enabled when operating in Full-Duplex mode only. There may be undesirable effects on back-pressure function and frame transmission if it is enabled in Half-Duplex mode. Bit 23 Reserved, must be kept at reset value. Bits 22:20 RESERVED_HDSMS[2:0]: Reserved. Bit 19 Reserved, must be kept at reset value. Bit 18 USP: Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the ETH_MACA0HR and ETH_MACA0LR registers. The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-0000-02). When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2008, Section 5. Bit 17 SPEN: Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types. When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets. Bit 16 DCRCC: Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets. Bits 15:14 Reserved, must be kept at reset value. Bits 13:0 GPSL[13:0]: Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1,518 bytes. Any other programmed value is considered as 1,518 bytes. For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. When the Enable Double VLAN Processing option is selected, the MAC adds 8 bytes to the programmed value for double VLAN tagged packets. The value in this field is applicable when the GPSLCE bit is set in ETH_MACCR register. 2822/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Packet filtering control register (ETH_MACPFR) Address offset: 0x0008 Reset value: 0x0000 0000 19 18 17 16 RA rw rw rw rw rw rw Res. rw Res. rw 9 8 SAF PR Res. PM 10 HPF PCF[1:0] Res. 0 11 Res. 1 Res. 2 12 Res. 3 Res. 4 13 Res. 5 Res. rw 6 14 Res. rw 7 15 Res. Res. 20 HUC 21 Res. 22 HMC 23 Res. 24 DAIF 25 IPFE 26 DNTU 27 DBF 28 Res. 29 Res. 30 SAIF 31 VTFE The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets. rw rw rw rw Bit 31 RA: Receive All When this bit is set, the MAC Receiver module passes all received packets to the application, irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bit in the Rx Status Word. When this bit is reset, the Receiver module passes only those packets to the application that pass the SA or DA address filter. Bits 30:22 Reserved, must be kept at reset value. Bit 21 DNTU: Drop Non-TCP/UDP over IP Packets When this bit is set, the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset, the MAC forwards all non-TCP or UDP over IP packets. If the Enable Layer 3 and Layer 4 Packet Filter option is not selected, this bit is reserved (RO with default value). Bit 20 IPFE: Layer 3 and Layer 4 Filter Enable When this bit is set, the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When this bit is reset, the MAC forwards all packets irrespective of the match status of the Layer 3 and Layer 4 fields. If the Enable Layer 3 and Layer 4 Packet Filter option is not selected, this bit is reserved (RO with default value). Bits 19:17 Reserved, must be kept at reset value. Bit 16 VTFE: VLAN Tag Filter Enable When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset, the MAC forwards all packets irrespective of the match status of the VLAN Tag. Bits 15:11 Reserved, must be kept at reset value. DocID029587 Rev 3 2823/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 10 HPF: Hash or Perfect Filter When this bit is set, the address filter passes a packet if it matches either the perfect filtering or Hash filtering as set by the HMC or HUC bit. When this bit is reset and the HUC or HMC bit is set, the packet is passed only if it matches the Hash filter. This bit is reserved (and RO) if the Enable Address Filter Hash Table option is not selected. Bit 9 SAF: Source Address Filter Enable When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the packet. When this bit is reset, the MAC forwards the received packet to the application with updated SAF bit of the Rx Status depending on the SA address comparison. Note: According to the IEEE specification, Bit 47 of the SA is reserved. However, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA. Bit 8 SAIF: SA Inverse Filtering When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers, it is marked as failing the SA Address filter. When this bit is reset, if the SA of a packet does not match the values programmed in the SA registers, it is marked as failing the SA Address filter. Bits 7:6 PCF[1:0]: Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets). 00: The MAC filters all control packets from reaching the application. 01: The MAC forwards all control packets except Pause packets to the application even if they fail the Address filter. 10: The MAC forwards all control packets to the application even if they fail the Address filter. 11: The MAC forwards the control packets that pass the Address filter. Bit 5 DBF: Disable Broadcast Packets When this bit is set, the AFM module blocks all incoming broadcast packets. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast packets. Bit 4 PM: Pass All Multicast When this bit is set, it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset, filtering of multicast packet depends on HMC bit. Bit 3 DAIF: DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset, normal filtering of packets is performed. 2824/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 2 HMC: Hash Multicast When this bit is set, the MAC performs the destination address filtering of received multicast packets according to the Hash table. When this bit is reset, the MAC performs the perfect destination address filtering for multicast packets, that is, it compares the DA field with the values programmed in DA registers. If the Enable Address Filter Hash Table option is not selected, this bit is reserved (and RO). Bit 1 HUC: Hash Unicast When this bit is set, the MAC performs the destination address filtering of unicast packets according to the Hash table. When this bit is reset, the MAC performs a perfect destination address filtering for unicast packets, that is, it compares the DA field with the values programmed in DA registers. If the Enable Address Filter Hash Table option is not selected, this bit is reserved (and RO). Bit 0 PR: Promiscuous Mode When this bit is set, the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set. DocID029587 Rev 3 2825/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Watchdog timeout register (ETH_MACWTR) Address offset: 0x000C Reset value: 0x0000 0000 The Watchdog Timeout register controls the watchdog timeout for received packets. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. 16 PWE 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 rw WTO[3:0] rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 PWE: Programmable Watchdog Enable When this bit is set and the WD bit of the ETH_MACCR register is reset, the WTO field is used as watchdog timeout for a received packet. When this bit is cleared, the watchdog timeout for a received packet is controlled by setting of WD and JE bits in ETH_MACCR register. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 WTO[3:0]: Watchdog Timeout When the PWE bit is set and the WD bit of the ETH_MACCR register is reset, this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field, such packet is terminated and declared as an error packet. Encoding is as follows: 0x0: 2 Kbytes 0x1: 3 Kbytes 0x2: 4 Kbytes 0x3: 5 Kbytes .. 0xC: 14 Kbytes 0xD: 15 Kbytes 0xE: 16383 Bytes 0xF: Reserved Note: When the PWE bit is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE 802.3-specified valid tagged packets are declared as error packets and then dropped. 2826/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Hash Table 0 register (ETH_MACHT0R) Address offset: 0x0010 Reset value: 0x0000 0000 The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HT31T0[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw HT31T0[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 HT31T0[31:0]: MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. DocID029587 Rev 3 2827/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Hash Table 1 register (ETH_MACHT1R) Address offset: 0x0014 Reset value: 0x0000 0000 The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HT63T32[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw HT63T32[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 HT63T32[31:0]: MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. 2828/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller VLAN tag register (ETH_MACVTR) Address offset: 0x0050 Reset value: 0x0000 0000 rw 9 8 EVLS [1:0] rw 7 6 5 20 19 18 17 16 ETV rw 10 21 VTIM rw 11 22 ESVL rw 23 Res. 24 ERSVLM 12 25 DOVLTC 13 26 EVLRXS rw 14 27 VTHM rw 15 28 EDVLP 29 EIVLS[1:0] 30 Res. EIVLRXS 31 ERIVLT The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets. rw rw rw rw rw 4 3 2 1 0 VL[15:0] rw Bit 31 EIVLRXS: Enable Inner VLAN Tag in Rx Status When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status. Bit 30 Reserved Bits 29:28 EIVLS[1:0]: Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet: 00: Do not strip 01: Strip if VLAN filter passes 10: Strip if VLAN filter fails 11: Always strip Bit 27 ERIVLT: Enable Inner VLAN Tag When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present). The ERSVLM bit determines which VLAN type is enabled for filtering or matching. Bit 26 EDVLP: Enable Double VLAN Processing When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present). Bit 25 VTHM: VLAN Tag Hash Table Match Enable When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the ETH_MACVLANHTR register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN Hash table. When the ETV bit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison. When this bit is reset, the VLAN Hash Match operation is not performed. If the VLAN Hash feature is not enabled, this bit is reserved (RO with default value). Bit 24 EVLRXS: Enable VLAN Tag in Rx status When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status. Bit 23 Reserved, must be kept at reset value. DocID029587 Rev 3 2829/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 22:21 EVLS[1:0]: Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet: 00: Do not strip 01: Strip if VLAN filter passes 10: Strip if VLAN filter fails 11: Always strip Bit 20 DOVLTC: Disable VLAN Type Check When this bit is set, the MAC does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN. When this bit is reset, the MAC filters or matches the VLAN Tag specified by the ERIVLT bit only when VLAN Tag type is similar to the one specified by the ERSVLM bit. Bit 19 ERSVLM: Enable Receive S-VLAN Match When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset, the MAC receiver enables filtering or matching for CVLAN (Type = 0x8100) packets. The ERIVLT bit determines the VLAN tag position considered for filtering or matching. Bit 18 ESVL: Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. Bit 17 VTIM: VLAN Tag Inverse Match Enable When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched. Bit 16 ETV: Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits[11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet. Similarly, when enabled, only 12 bits of the VLAN tag in the received packet are used for Hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN packet are used for comparison and VLAN Hash filtering. Bits 15:0 VL[15:0]: VLAN Tag Identifier for Receive Packets This field contains the 802.1Q VLAN tag to identify the VLAN packets. This VLAN tag identifier is compared to the 15th and 16th bytes of the packets being received for VLAN packets. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag When the ETV bit is set, only the VID is used for comparison. If this field ([11:0] if ETV is set) is all zeros, the MAC does not check the 15th and 16th bytes for VLAN tag comparison and declares all packets with Type field value of 0x8100 or 0x88a8 as VLAN packets. 2830/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller VLAN Hash table register (ETH_MACVHTR) Address offset: 0x0058 Reset value: 0x0000 0000 When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). 2. Perform bitwise reversal for the value obtained in step 1. 3. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the MII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written. 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw VLHT[15:0] rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 VLHT[15:0]: VLAN Hash Table This field contains the 16-bit VLAN Hash Table. DocID029587 Rev 3 2831/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 VLAN inclusion register (ETH_MACVIR) Address offset: 0x0060 Reset value: 0x0000 0000 The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls. 19 18 17 16 rw rw 4 3 2 1 0 rw rw rw rw rw rw rw Res. rw Res. VLP 20 CSVL 21 VLTI 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 15 14 13 12 11 10 9 8 7 6 5 VLC [1:0] rw VLT[15:0] rw Bits 31:21 rw rw rw rw rw rw rw rw Reserved, must be kept at reset value. Bit 20 VLTI: VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor. Bit 19 CSVL: C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. Bit 18 VLP: VLAN Priority Control When this bit is set, the control bits[17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used and bits[17:16] are ignored. Bits 17:16 VLC[1:0]: VLAN Tag Control in Transmit Packets 00: No VLAN tag deletion, insertion, or replacement 01: VLAN tag deletion. The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags. 10: VLAN tag insertion. The MAC inserts VLT in bytes 15 and 16 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 13 and 14. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag. 11: VLAN tag replacement. The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted packets (Bytes 13 and 14 are 0x8100 or 0x88a8). Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. Bits 15:0 VLT[15:0]: VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority field, Bit 12 is the CFI/DEI field, and Bits[11:0] are the VID field in the VLAN tag. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag 2832/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Inner VLAN inclusion register (ETH_MACIVIR) Address offset: 0x0064 Reset value: 0x0000 0000 The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls. 19 18 17 16 rw rw 4 3 2 1 0 rw rw rw rw rw rw rw Res. rw Res. VLP 20 CSVL 21 VLTI 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 15 14 13 12 11 10 9 8 7 6 5 VLC [1:0] rw VLT[15:0] rw Bits 31:21 rw rw rw rw rw rw rw rw Reserved, must be kept at reset value. Bit 20 VLTI: VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from the Tx descriptor Bit 19 CSVL: C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets. DocID029587 Rev 3 2833/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 18 VLP: VLAN Priority Control When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used and the VLC field is ignored. Bits 17:16 VLC[1:0]: VLAN Tag Control in Transmit Packets 00: No VLAN tag deletion, insertion, or replacement 01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags. 10: VLAN tag insertion The MAC inserts VLT in bytes 19 and 20 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 17 and 18. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag. 11: VLAN tag replacement The MAC replaces VLT in bytes 19 and 20 of all VLAN-type transmitted packets (Bytes 17 and 18 are 0x8100 or 0x88a8). Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value. Bits 15:0 VLT[15:0]: VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority field, Bit 12 is the CFI/DEI field, and Bits[11:0] are the VID field in the VLAN tag. The following list describes the bits of this field: Bits[15:13]: User Priority Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) Bits[11:0]: VLAN Identifier (VID) field of VLAN tag Tx Queue flow control register (ETH_MACQTxFCR) Address offset: 0x0070 Reset value: 0x0000 0000 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. DZPQ 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 FCB_BPA 28 Res. 20 TFE 29 Res. 21 Res. 30 Res. 22 Res. 31 Res. The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register. 23 rw rw PT[15:0] rw 2834/3178 DocID029587 Rev 3 PLT[2:0] rw rw rw RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:16 PT[15:0]: Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain, consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. Bits 15:8 Reserved, must be kept at reset value. Bit 7 DZPQ: Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or mti_flowctrl_i). When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled. Bits 6:4 PLT[2:0]: Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot times), and PLT = 001, a second Pause packet is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256-28) slot times after the first Pause packet is transmitted. The following list provides the threshold values for different values: 000: Pause Time minus 4 Slot Times (PT -4 slot times) 001: Pause Time minus 28 Slot Times (PT -28 slot times) 010: Pause Time minus 36 Slot Times (PT -36 slot times) 011: Pause Time minus 144 Slot Times (PT -144 slot times) 100: Pause Time minus 256 Slot Times (PT -256 slot times) 101: Pause Time minus 512 Slot Times (PT -512 slot times) 110-111: Reserved The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface. This (approximate) computation is based on the packet size (64, 1518, 2000, 9018, 16384, or 32768) + 2 Pause Packet Size + IPG in Slot Times. Bits 3:2 Reserved, must be kept at reset value. Bit 1 TFE: Transmit Flow Control Enable Full-Duplex Mode: when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets. Half-Duplex Mode: when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. Bit 0 FCB_BPA: Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. Full-Duplex Mode: this bit should be read as 0 before writing to this register. To initiate a Pause packet, the application must set this bit to 1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 0. You should not write to this register until this bit is cleared. Half-Duplex Mode: When this bit is set (and TFE bit is set) in the half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. DocID029587 Rev 3 2835/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Rx flow control register (ETH_MACRxFCR) Address offset: 0x0090 Reset value: 0x0000 0000 The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. UP RFE 16 RESERVED_PFCE 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 rw rw r Bits 31:2 Reserved, must be kept at reset value. Bit 1 UP: Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set, the MAC can also detect Pause packets with unicast address of the station. This unicast address should be as specified in ETH_MACA0HR and ETH_MACA0LR. When this bit is reset, the MAC only detects Pause packets with unique multicast address. Note: The MAC does not process a Pause packet if the multicast address is different from the unique multicast address. This is also applicable to the received PFC packet when the Priority Flow Control (PFC) is enabled. The unique multicast address (0x01_80_C2_00_00_01) is as specified in IEEE 802.1 Qbb-2011. Bit 0 RFE: Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in half-duplex mode, the decode function of the Pause packet is disabled. When PFC is enabled, flow control is enabled for PFC packets. The MAC decodes the received PFC packet and disables the Transmit queue, with matching priorities, for a duration of received Pause time. 2836/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Interrupt status register (ETH_MACISR) Address offset: 0x00B0 Reset value: 0x0000 0000 The Interrupt Status register contains the status of interrupts. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. LPIIS PMTIS PHYIS RESERVED_PCSANCIS RESERVED_PCSLCHGIS Res. 16 MMCIS 17 Res. 18 MMCRXIS 19 Res. 20 MMCTXIS 21 Res. 22 RESERVED_MMCRXIPIS 23 Res. 24 TSIS 25 Res. 26 TXSTSIS 27 Res. 28 RXSTSIS 29 Res. 30 RESERVED_GPIIS 31 r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bit 15 RESERVED_GPIIS: Reserved. Bit 14 RXSTSIS: Receive Status Interrupt This bit indicates the status of received packets. This bit is set when the RWT bit is set in the ETH_MACISR register. This bit is cleared when the corresponding interrupt source bit is read in the ETH_MACISR register. Bit 13 TXSTSIS: Transmit Status Interrupt This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the ETH_MACISR register: – Excessive Collision (EXCOL) – Late Collision (LCOL) – Excessive Deferral (EXDEF) – Loss of Carrier (LCARR) – No Carrier (NCARR) – Jabber Timeout (TJT) This bit is cleared when the corresponding interrupt source bit is read in the ETH_MACISR register. DocID029587 Rev 3 2837/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 12 TSIS: Timestamp Interrupt Status If the Timestamp feature is enabled, this bit is set when any of the following conditions is true: – The system time value is equal to or exceeds the value specified in the Target Time High and Low registers. – There is an overflow in the Seconds register. – The Target Time Error occurred, that is, programmed target time already elapsed. If the Auxiliary Snapshot feature is enabled, this bit is set when the auxiliary snapshot trigger is asserted. When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the ETH_MACTxTSSNR and ETH_MACTxTSSSR registers. When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the ETH_MACTxTSSNR and ETH_MACTxTSSSR registers, for PTO generated Delay Request and Pdelay request packets. This bit is cleared when the corresponding interrupt source bit is read in the ETH_MACTSSR register. Bit 11 RESERVED_MMCRXIPIS: Reserved. Bit 10 MMCTXIS: MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable MAC Management Counters (MMC) option. Bit 9 MMCRXIS: MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable MAC Management Counters (MMC) option. Bit 8 MMCIS: MMC Interrupt Status This bit is set high when Bit 11, Bit 10, or Bit 9 is set high. This bit is cleared only when all these bits are low. This bit is valid only when you select the Enable MAC Management Counters (MMC) option. Bits 7:6 Reserved, must be kept at reset value. Bit 5 LPIIS: LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the TLPIEN bit of ETH_MACLCSR register is read. In all other modes, this bit is reserved. Bit 4 PMTIS: PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in ETH_MACPCSR register). This bit is cleared when Bits[6:5] are cleared because of a Read operation to the ETH_MACPCSR register. This bit is valid only when you select the Enable Power Management option. Bit 3 PHYIS: PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input. This bit is cleared when this register is read. Bits 2:0 2838/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Interrupt enable register (ETH_MACIER) Address offset: 0x00B4 Reset value: 0x0000 0000 The Interrupt Enable register contains the masks for generating the interrupts. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. LPIIE PMTIE PHYIE RESERVED_PCSANCIE RESERVED_PCSLCHGIE Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 TSIE 25 Res. 26 TXSTSIE 27 Res. 28 RXSTSIE 29 Res. 30 Res. 31 rw rw rw rw rw rw r r Bits 31:15 Reserved, must be kept at reset value. Bit 14 RXSTSIE: Receive Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the ETH_MACISR register. Bit 13 TXSTSIE: Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the ETH_MACISR register. Bit 12 TSIE: Timestamp Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of TSIS bit in ETH_MACISR register. This bit is valid only when the Enable IEEE 1588 Timestamp Support option is selected. Otherwise, this bit is reserved. Bits 11:6 Reserved, must be kept at reset value. Bit 5 LPIIE: LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of LPIIS bit in ETH_MACISR register. This bit is valid only when the Enable Energy Efficient Ethernet (EEE) option is selected. Otherwise, this bit is reserved. Bit 4 PMTIE: PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PMTIS bit in ETH_MACISR register. Bit 3 PHYIE: PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in ETH_MACISR register. Bits 2:0 Reserved, must be kept at reset value. DocID029587 Rev 3 2839/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Rx Tx status register (ETH_MACRxTxSR) Address offset: 0x00B8 Reset value: 0x0000 0000 The Receive Transmit Status register contains the Receive and Transmit Error status. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. EXCOL LCOL EXDEF LCARR NCARR TJT 16 RWT 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 r r r r r r r Bits 31:9 Reserved, must be kept at reset value. Bit 8 RWT: Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the ETH_MACCR register. This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the ETH_MACCR register. Bits 7:6 Reserved, must be kept at reset value. Bit 5 EXCOL: Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the ETH_MACCR register, this bit is set after the first collision and the packet transmission is aborted. Bit 4 LCOL: Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode. This bit is not valid if the Underflow error occurs. Bit 3 EXDEF: Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the ETH_MACCR register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000 Mbps mode or when Jumbo packet is enabled). 2840/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 2 LCARR: Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. Bit 1 NCARR: No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Bit 0 TJT: Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the ETH_MACCR register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the ETH_MACCR register. DocID029587 Rev 3 2841/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 PMT control status register (ETH_MACPCSR) Address offset: 0x00C0 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RWKPKTEN MGKPKTEN PWRDWN 16 Res. 17 Res. 18 MGKPRCVD 19 Res. 20 RWKPRCVD 21 Res. 22 Res. 23 Res. 24 GLBLUCAST 25 RWKPFE 26 Res. Res. 27 Res. Res. 28 Res. 29 Res. 30 Res. 31 RWKFILTRST The PMT Control and Status Register is present only when you select the PMT module in coreConsultant. rw rw r r rw rw rw rw RWKPTR[4:0] r r r r r Bit 31 RWKFILTRST: Remote wakeup Packet Filter Register Pointer Reset When this bit is set, the remote wakeup packet filter register pointer is reset to 3'b000. It is automatically cleared after 1 clock cycle. Bits 30:29 Reserved, must be kept at reset value. Bits 28:24 RWKPTR[4:0]: Remote wakeup FIFO Pointer This field gives the current value (0 to 7) of the Remote wakeup Packet Filter register pointer. When the value of this pointer is equal to 7, the contents of the Remote wakeup Packet Filter Register are transferred to the eth_mii_rx_clk domain when a Write occurs to that register. Bits 23:11 Reserved, must be kept at reset value. Bit 10 RWKPFE: Remote wakeup Packet Forwarding Enable When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected wakeup frame. All frames after that event including the received wakeup frame are forwarded to application. This bit is then self-cleared on receiving the wakeup packet. The application can also clear this bit before the expected wakeup frame is received. In such cases, the MAC reverts to the default behavior where packets received are forwarded to the application. This bit must only be set when RWKPKTEN is set high and PWRDWN is set low. The setting of this bit has no effect when PWRDWN is set high. Note: If Magic Packet Enable and wakeup Frame Enable are both set along with setting of this bit and Magic Packet is received prior to wakeup frame, this bit is self-cleared on receiving Magic Packet, the received Magic packet is dropped, and all frames after received Magic Packet are forwarded to application. Bit 9 GLBLUCAST: Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wakeup packet. Bits 8:7 2842/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 6 RWKPRCVD: Remote wakeup Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a remote wakeup packet. This bit is cleared when this register is read. Bit 5 MGKPRCVD: Magic Packet Received When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read. Bits 4:3 Reserved, must be kept at reset value. Bit 2 RWKPKTEN: Remote wakeup Packet Enable When this bit is set, a power management event is generated when the MAC receives a remote wakeup packet. Bit 1 MGKPKTEN: Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. Bit 0 PWRDWN: Power Down When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wakeup packet. This bit is then self-cleared and the powerdown mode is disabled. The software can clear this bit before the expected magic packet or remote wakeup packet is received. The packets received by the MAC after this bit is cleared are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote wakeup Packet Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. DocID029587 Rev 3 2843/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Remove wakeup packet filter register (ETH_MACRWKPFR) Address offset: 0x00C4 Reset value: 0x0000 0000 The wkuppktfilter_reg register at address 0C4H loads the wakeup Packet Filter register. To load values in a wakeup Packet Filter register, the entire register (wkuppktfilter_reg) must be written. The wkuppktfilter_reg register is loaded by sequentially loading the eight, sixteen or thirty two register values in address (0C4H) for wkuppktfilter_reg0, wkuppktfilter_reg1, wkuppktfilter_reg31, respectively. The wkuppktfilter_reg register is read in a similar way. The Ethernet peripheral updates the wkuppktfilter_reg register current pointer value in Bits[26:24] of ETH_MACPCSR register. Table 542. Remote Wakeup packet filter register ETH_MACRWKPFR +# Field 0 Filter 0 Byte Mask 1 Filter 1 Byte Mask 2 Filter 2 Byte Mask 3 Filter 3 Byte Mask 4 5 Reserved Filter 3 Cmd Filter 3 Offset Reserved Filter 2 Cmd Filter 2 Offset Reserved Filter 1 Cmd Filter 1 Offset Reserved Filter 0 Offset 6 Filter 1 CRC-16 Filter 0 CRC-16 7 Filter 3 CRC-16 Filter 2 CRC-16 8 Filter 4 Byte Mask 9 Filter 5 Byte Mask 10 Filter 6 Byte Mask 11 Filter 7 Byte Mask 12 13 Reserved Filter 7 Cmd Filter 7 Offset Reserved Filter 6 Cmd Filter 6 Offset Reserved Filter 5 Cmd Filter 5 Offset Reserved Filter 5 CRC-16 Filter 4 CRC-16 15 Filter 7 CRC-16 Filter 6 CRC-16 Filter 8 Byte Mask 17 Filter 9 Byte Mask 18 Filter 10 Byte Mask 19 Filter 11 Byte Mask 20 21 22 2844/3178 Reserved Filter 11 Cmd Filter 11 Offset Reserved Filter 10 Cmd Filter 10 Offset Filter 9 CRC-16 DocID029587 Rev 3 Reserved Filter 9 Cmd Filter 9 Offset Filter 4 Cmd Filter 4 Offset 14 16 Filter 0 Cmd Reserved Filter 8 Cmd Filter 8 Offset Filter 8 CRC-16 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 542. Remote Wakeup packet filter register (continued) ETH_MACRWKPFR +# Field 23 Filter 11 CRC-16 Filter 10 CRC-16 24 Filter 12 Byte Mask 25 Filter 13 Byte Mask 26 Filter 14 Byte Mask 27 Filter 15 Byte Mask Reserved 28 29 Filter 15 Cmd Filter 15 Offset Reserved Filter 14 Cmd Filter 14 Offset Reserved Filter 13 Cmd Filter 13 Offset Reserved Filter 12 Offset 30 Filter 13 CRC-16 Filter 12 CRC-16 31 Filter 15 CRC-16 Filter 14 CRC-16 DocID029587 Rev 3 Filter 12 Cmd 2845/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 543. ETH_MACRWKPFR Register Description Filter i Byte Mask The filter i byte mask register defines the bytes of the packet that are examined by filter i (0, 1, 2, 3,…,15) to determine whether or not a packet is a wakeup packet. The MSB (31st bit) must be zero. Bit j[30:0] is the byte mask. If Bit j (byte number) of the byte mask is set, the CRC block processes the Filter i Offset + j of the incoming packet; otherwise Filter i Offset + j is ignored. Filter i Command The 4-bit filter i command controls the filter i operation. – Bit 3 specifies the address type, defining the destination address type of the pattern. When the bit is set, the pattern applies to only multicast packets; when the bit is reset, the pattern applies only to unicast packet. – Bit 2 (Inverse Mode), when set, reverses the logic of the CRC16 Hash function signal, to reject a packet with matching CRC_16 value. Bit 2, along with Bit 1, allows a MAC to reject a subset of remote wakeup packets by creating filter logic such as "Pattern 1 AND NOT Pattern 2". – Bit 1 (And_Previous) implements the Boolean logic. When set, the result of the current entry is logically ANDed with the result of the previous filter. This AND logic allows a filter pattern longer than 32 bytes by splitting the mask among two, three, or four filters. This depends on the number of filters that have the And_Previous bit set. The And_Previous bit is applicable for more than one filter operation, where the filter result is ANDed with the previous filter result. For example, if And_Previous bit is set in Filter 1, the Remote Wakeup packet is detected and PMT interrupt generated only if both Filter 0 and Filter 1 satisfy the Remote Wakeup packet detection and interrupt generation criteria mentioned in Table 544. Note: The And_Previous bit setting is applicable within a set of 4 filters. Note: Setting of And_Previous bit of filter that is not enabled has no effect. In other words, setting And_Previous bit of lowest number filter in the set of 4 filters has no effect. For example, setting of And_Previous bit of Filter 0 has no effect. Note: If And_Previous bit is set for filter to form AND chained filter, the AND chain breaks at the point any filter is not enabled. For example: If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set) but Filter 1 is not enabled (bit 0 of in Filter 1 command is reset), then only Filter 2 result is considered. If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 3 And_Previous bit is set (bit 1 of Filter 3 command is set), but Filter 1 is not enabled (bit 0 of in Filter 1 command is reset), then only Filter 2 result ANDed with Filter 3 result is considered. If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 3 And_Previous bit is set (bit 1 of Filter 3 command is set), but Filter 2 is not enabled (bit 0 of in Filter 2 command is reset), then since setting of Filter 2 And_Previous bit has no effect only Filter 1 result ORed with Filter 3 result is considered. Note: If filters chained by And_Previous bit setting have complementary programming, then a frame may never pass the AND chained filter. For example, if Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 1 Address_Type bit is set (bit 3 of Filter 1 command is set) indicating multicast detection and Filter 2 Address_Type bit is reset (bit 3 of Filter 2 command is reset) indicating unicast detection or vice versa, a remote wakeup frame does not pass the AND chained filter as a remote wakeup frame cannot be of both unicast and multicast address type. – Bit 0 is the enable for filter i. If Bit 0 is not set, filter i is disabled. 2846/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 543. ETH_MACRWKPFR (continued) Register Description Filter i Offset This filter i offset register defines the offset (within the packet) from which the filter i examines the packets. This 8-bit pattern-offset is the offset for the filter i first byte to be examined. The minimum allowed offset is 12, which refers to the 13th byte of the packet. The offset value 0 refers to the first byte of the packet. Filter i CRC-16 This filter i CRC-16 register contains the CRC_16 value calculated from the pattern and also the byte mask programmed to the wakeup filter register block. The 16-bit CRC calculation uses the following polynomial: G(x) = x^16 + x^15 + x^2 + 1 Each mask, used in the Hash function calculation, is compared with a 16-bit value associated with that mask. Each filter has the following: – 32-bit Mask: Each bit in this mask corresponds to one byte in the detected packet. If the bit is 1', the corresponding byte is taken into the CRC16 calculation. – 8-bit Offset Pointer: Specifies the byte to start the CRC16 computation. The pointer and the mask are used together to locate the bytes to be used in the CRC16 calculations. Next table lists the Remote Wakeup scenarios in which PMT interrupt is generated. Table 544. Remote Wakeup Packet and PMT Interrupt Generation(1) Filter i Command Frame Type and CRC Status Interrupt Generation CAST INV EN Received Frame Cast Type CRC Status RWK INTR 0 0 1 Unicast MATCH Remote Wakeup packet is detected and PMT interrupt is generated 0 1 1 Unicast MISMATCH Remote Wakeup packet is detected and PMT interrupt is generated 1 0 1 Multicast MATCH Remote Wakeup packet is detected and PMT interrupt is generated 1 1 1 Multicast MISMATCH Remote Wakeup packet is detected and PMT interrupt is generated 1. In all other combinations, the Remote Wakeup packet is not detected and PMT interrupt is not generated. DocID029587 Rev 3 2847/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 LPI control status register (ETH_MACLCSR) Address offset: 0x00D0 Reset value: 0x0000 0000 The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. Res. Res. Res. LPITCSE LPITE LPITXA PLSEN PLS LPIEN rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. RLPIEX RLPIEN TLPIEX TLPIEN 16 TLPIST 17 Res. 18 RLPIST 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 r r r r r r Bits 31:22 Reserved, must be kept at reset value. Bit 21 LPITCSE: LPI Tx Clock Stop Enable When this bit is set, the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. When this bit is reset, the MAC does not assert sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode. Bit 20 LPITE: LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPITE, LPITXA and LPITXEN bits are set, the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for a period indicated by the ETH_MACLETR register. After entering LPI state, if the data path becomes non-IDLE (due to a new packet being accepted for transmission), the Transmitter exits LPI state but does not clear LPITXEN bit. This enables the re-entry into LPI state when it is IDLE again. When LPITE is 0, the LPI Auto timer is disabled and MAC Transmitter enters LPI state based on the settings of LPITXA and LPITXEN bit descriptions. Bit 19 LPITXA: LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding packets (in the core) and pending packets (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any packet for transmission or the application issues a Tx FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If Tx FIFO Flush is set in the FTQ bit of ETH_MTLTxQOMR, when the MAC is in the LPI mode, it exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. 2848/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 18 PLSEN: PHY Link Status Enable This bit enables the link status received on the Receive paths to be used for activating the LPI LS TIMER. When this bit is set, the MAC uses the PLS bit for the LPI LS Timer trigger. When this bit is reset, the MAC ignores the link-status bits of the ETH_MACPHYCSR register and takes only the PLS bit. This bit is RO and reserved if you have not selected the PHY interface. Bit 17 PLS: PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. When this bit is set, the link is considered to be okay (UP) and when this bit is reset, the link is considered to be down. Bit 16 LPIEN: LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. When this bit is reset, it instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. Bits 15:10 Reserved, must be kept at reset value. Bit 9 RLPIST: Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface. Bit 8 TLPIST: Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface. Bits 7:4 Reserved, must be kept at reset value. Bit 3 RLPIEX: Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. Bit 2 RLPIEN: Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock. Bit 1 TLPIEX: Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. Bit 0 TLPIEN: Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. DocID029587 Rev 3 2849/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 LPI timers control register (ETH_MACLTCR) Address offset: 0x00D4 Reset value: 0x03E8 0000 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. 15 14 13 12 11 10 25 24 23 22 21 20 19 18 17 16 LST[9:0] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TWT[15:0] rw Bits 31:26 rw rw rw rw rw rw rw rw Reserved, must be kept at reset value. Bits 25:16 LST[9:0]: LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. Bits 15:0 TWT[15:0]: LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. 2850/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller LPI entry timer register (ETH_MACLETR) Address offset: 0x00D8 Reset value: 0x0000 0000 22 21 20 Res. Res. Res. Res. Res. 15 14 13 12 11 10 19 Bits 31:20 rw rw rw rw rw 17 16 rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw LPIET[16:13] LPIET[12:0] rw 18 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 Res. The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds. rw Reserved, must be kept at reset value. Bits 19:3 LPIET[16:0]: LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter LPI mode, after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1. Bits [2:0] are read-only so that the granularity of this timer is in steps of 8 micro-seconds. Bits 2:0 Reserved, must be kept at reset value. 1-microsecond-tick counter register (ETH_MAC1USTCR) Address offset: 0x00DC Reset value: 0x0000 0000 This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw TIC_1US_CNTR[11:0] rw Bits 31:12 Res. 12 Res. 13 Res. 14 Res. 15 Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 rw rw rw rw rw rw Reserved, must be kept at reset value. Bits 11:0 TIC_1US_CNTR[11:0]: 1 µs tick Counter The application must program this counter so that the number of clock cycles of CSR clock is 1 µs. (Subtract 1 from the value before programming). For example if the CSR clock is 100 MHz then this field needs to be programmed to 100 - 1 = 99 (which is 0x63). This is required to generate the 1 µs events that are used to update some of the EEE related counters. DocID029587 Rev 3 2851/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Version register (ETH_MACVR) Address offset: 0x0110 Reset value: 0x0000 3041 Res. Res. 12 11 10 9 8 7 6 5 USERVER[7:0] r Bits 31:16 r r r r 20 19 18 17 16 4 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 13 26 Res. Res. 14 27 Res. Res. 15 28 Res. 29 Res. 30 Res. 31 Res. The version register identifies the version of the Ethernet peripheral. This register contains two bytes: one that Synopsys uses to identify the core release number, and the other that the application can set while configuring the core. 3 2 1 0 r r r r 18 17 16 SNPSVER[7:0] r r r r r r r Reserved, must be kept at reset value. Bits 15:8 USERVER[7:0]: User-defined Version (configured with coreConsultant) Bits 7:0 SNPSVER[7:0]: Synopsys-defined Version (3.7) Debug register (ETH_MACDR) Address offset: 0x0114 Reset value: 0x0000 0000 Res. Res. Res. Res. 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. r r r 2 1 0 r 2852/3178 DocID029587 Rev 3 TPESTS Res. 13 RPESTS Res. 14 RFCFCSTS[1:0] Res. 15 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 TFCSTS[1:0] The Debug register provides the debug status of various MAC blocks. r r RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:19 Reserved, must be kept at reset value. Bits 18:17 TFCSTS[1:0]: MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module: 00: Idle state 01: Waiting for one of the following: – Status of the previous packet OR – IPG or backoff period to be over 10: Generating and transmitting a Pause control packet (in full-duplex mode) 11: Transferring input packet for transmission Bit 16 TPESTS: MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC MII transmit protocol engine is actively transmitting data, and it is not in the Idle state. Bits 15:3 Reserved, must be kept at reset value. Bits 2:1 RFCFCSTS[1:0]: MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module. Bit 0 RPESTS: MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC MII receive protocol engine is actively receiving data, and it is not in the Idle state. HW feature 1 register (ETH_MACHWF1R) Address offset: 0x0120 Reset value: 0x1184 1904 19 18 17 16 DCBEN OSTEN r r 8 20 SPHEN PTOEN r r 9 21 TSOEN ADVTHWORD r 10 22 DBGMEMA r 11 23 7 6 TXFIFOSIZE[4:0] r r r r DocID029587 Rev 3 AVSEL r 12 24 Res. 25 r r r r r 5 4 3 2 1 0 Res. r 13 ADDR64[1:0] r 14 r 26 Res. 27 HASHTBLSZ[1:0] 28 L3L4FNUM[3:0] 15 r 29 Res. 30 Res. 31 Res. This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. r RXFIFOSIZE[4:0] r r r r r 2853/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 31 Reserved, must be kept at reset value. Bits 30:27 L3L4FNUM[3:0]: Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: 0000: No L3 or L4 Filter 0001: 1 L3 or L4 Filter 0010: 2 L3 or L4 Filters .. 1000: 8 L3 or L4 Bit 26 Reserved, must be kept at reset value. Bits 25:24 HASHTBLSZ[1:0]: Hash Table Size This field indicates the size of the Hash table: 00: No Hash table 01: 64 10: 128 11: 256 Bits 23:21 Reserved, must be kept at reset value. Bit 20 AVSEL: AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. Bit 19 DBGMEMA: DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected Bit 18 TSOEN: TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected Bit 17 SPHEN: Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected Bit 16 DCBEN: DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADVTHWORD: IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected Bit 12 PTOEN: PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. Bit 11 OSTEN: One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. 2854/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 10:6 TXFIFOSIZE[4:0]: MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: 00000: 128 bytes 00001: 256 bytes 00010: 512 bytes 00011: 1,024 bytes 00100: 2,048 bytes 00101: 4,096 bytes 00110: 8,192 bytes 00111: 16,384 bytes 01000: 32 Kbytes 01001: 64 Kbytes 01010: 128 Kbytes 01011-11111: Reserved Bit 5 Reserved, must be kept at reset value. Bits 4:0 RXFIFOSIZE[4:0]: MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: 00000: 128 bytes 00001: 256 bytes 00010: 512 bytes 00011: 1,024 bytes 00100: 2,048 bytes 00101: 4,096 bytes 00110: 8,192 bytes 00111: 16,384 bytes 01000: 32,767 bytes 01000: 32 Kbytes 01001: 64 Kbytes 01010: 128 Kbytes 01011: 256 Kbytes 01100-11111: Reserved DocID029587 Rev 3 2855/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 HW feature 2 register (ETH_MACHWF2R) Address offset: 0x0124 Reset value: 0x4100 0000 Bit 31 r r 8 7 6 TXQCNT[3:0] r r r r r r r 4 3 2 r Reserved, must be kept at reset value. Reserved, must be kept at reset value. Reserved, must be kept at reset value. Bits 21:18 TXCHCNT[3:0]: Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: 0000: 1 DMA Tx Channel 0001: 2 DMA Tx Channels .. 0111: 8 DMA Tx Bits 17:16 2856/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 18 5 Bits 26:24 PPSOUTNUM[2:0]: Number of PPS Outputs This field indicates the number of PPS outputs: 000: No PPS output 001: 1 PPS output 010: 2 PPS outputs 011: 3 PPS outputs 100: 4 PPS outputs 101-111: Reserved Bits 23:22 19 TXCHCNT[3:0] Bits 30:28 AUXSNAPNUM[2:0]: Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: 000: No auxiliary input 001: 1 auxiliary input 010: 2 auxiliary inputs 011: 3 auxiliary inputs 100: 4 auxiliary inputs 101-111: Reserved Bit 27 20 17 16 Res. r 9 21 Res. r 10 22 Res. r 11 23 Res. 24 Res. r 12 25 Res. r 13 r 26 Res. r 14 RXCHCNT[3:0] r 27 PPSOUTNUM[2:0] 28 Res. 15 29 AUXSNAPNUM[2:0] 30 Res. 31 Res. This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 1 0 RXQCNT[3:0] r r r r RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 15:12 RXCHCNT[3:0]: Number of DMA Receive Channels This field indicates the number of DMA Receive channels: 0000: 1 DMA Rx Channel 0001: 2 DMA Rx Channels .. 0111: 8 DMA Rx Bits 11:10 Reserved, must be kept at reset value. Bits 9:6 TXQCNT[3:0]: Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: 0000: 1 MTL Tx queue 0001: 2 MTL Tx queues .. 0111: 8 MTL Tx Bits 5:4 Reserved, must be kept at reset value. Bits 3:0 RXQCNT[3:0]: Number of MTL Receive Queues This field indicates the number of MTL Receive queues: 0000: 1 MTL Rx queue 0001: 2 MTL Rx queues .. 0111: 8 MTL Rx MDIO address register (ETH_MACMDIOAR) Address offset: 0x0200 Reset value: 0x0000 0000 Res. PSE BTB 13 12 rw 21 20 19 PA[4:0] 18 17 16 RDA[4:0] rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 MB rw rw rw rw rw CR[3:0] rw 22 rw NTC[2:0] rw 23 C45E Res. 14 24 GOC_0 Res. 15 25 GOC_1 26 SKAP 27 Res. 28 Res. 29 Res. 30 Res. 31 Res. The MDIO Address register controls the management cycles to external PHY through a management interface. rw rw rw rw DocID029587 Rev 3 2857/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:28 RM0433 Reserved, must be kept at reset value. Bit 27 PSE: Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit preamble and transmit MDIO frames with only 1 preamble bit. When this bit is 0, the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications. Bit 26 BTB: Back to Back transactions When this bit is set and the NTC has value greater than 0, then the MAC will inform the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus initiate the next command which will be executed immediately irrespective of the number trailing clocks generated for the previous frame. When this bit is reset, then the read/write command completion (MII busy is cleared) only after the trailing clocks are generated. In this mode, it is ensured that the NTC is always generated after each frame. This bit must not be set when NTC=0. Bits 25:21 PA[4:0]: Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing. Bits 20:16 RDA[4:0]: Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY. Bit 15 Reserved, must be kept at reset value. Bits 14:12 NTC[2:0]: Number of Training Clocks This field controls the number of trailing clock cycles generated on ETH_MDC after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 3'h3 indicates that there are additional three clock cycles on the MDC line after the end of MDIO frame transfer. 2858/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 11:8 CR[3:0]: CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 0010: CSR clock = 20-35 MHz; MDC clock = CSR clock/16 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 0101: CSR clock = 250-300 MHz; MDC clock = CSR clock/124 0110, 0111: Reserved The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, the resultant MDC clock is of 12.5 MHz which is above the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks: 1000: CSR clock/4 1001: CSR clock/6 1010: CSR clock/8 1011: CSR clock/10 1100: CSR clock/12 1101: CSR clock/14 1110: CSR clock/16 1111: CSR clock/18 Bits 7:5 Reserved, must be kept at reset value. Bit 4 SKAP: Skip Address Packet When this bit is set, the SMA does not send the address packets before read, write, or postread increment address packets. This bit is valid only when C45E is set. DocID029587 Rev 3 2859/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 3:2 GOC: MII Operation Command This bit indicates the operation command to the PHY. 00: Reserved 01: Write 10: Post Read Increment Address for Clause 45 PHY 11: Read When Clause 22 PHY is enabled, only Write and Read commands are valid. Bit 1 C45E: Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO. Bit 0 MB: MII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIOS. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in ETH_MACMDIOAR and ETH_MACMDIODR registers as long as this bit is set. For write transfers, the application must first write 16-bit data in the MD field (and also RA field when C45E is set) in ETH_MACMDIODR register before setting this bit. When C45E is set, it should also write into the RA field of ETH_MACMDIODR register before initiating a read transfer. When a read transfer is completed (MII busy=0), the data read from the PHY register is valid in the MD field of the ETH_MACMDIODR register. Note: Even if the addressed PHY is not present, there is no change in the functionality of this bit. MDIO data register (ETH_MACMDIODR) Address offset: 0x0204 Reset value: 0x0000 0000 The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw RA[15:0] MD[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 RA[15:0]: Register Address This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for. Bits 15:0 MD[15:0]: MII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. 2860/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller ARP address register (ETH_MACARPAR) Address offset: 0x0AE0 Reset value: 0x0000 0000 The ARP Address register contains the IPv4 Destination Address of the MAC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ARPPA[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARPPA[15:0] rw Bits 31:0 rw rw rw rw rw rw rw rw ARPPA[31:0]: ARP Protocol Address This field contains the IPv4 Destination Address of the MAC. This address is used for perfect match with the Protocol Address of Target field in the received ARP packet. This field is available only when the Enable IPv4 ARP Offload option is selected. Address 0 high register (ETH_MACA0HR) Address offset: 0x0300 Reset value: 0x8000 FFFF The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. 16 AE 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw r ADDRHI[15:0] rw rw Bit 31 AE: Address Enable This bit is always set to 1. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 ADDRHI[15:0]: MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. DocID029587 Rev 3 2861/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Address x low register (ETH_MACAxLR) Address offset: 0x0304 + x*0x8 (where x = 0 to 3) Reset value: 0xFFFF FFFF The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDRLO[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ADDRLO[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 ADDRLO[31:0]: MAC Address x [31:0] (x = 0 to 3) This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets. Address x high register (ETH_MACAxHR) Address offset: 0x0308 + (x-1)*0x8 (where x = 1 to 3) Reset value: 0x0000 FFFF The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. rw MBC[5:0] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Res. 24 Res. 25 Res. 26 Res. 27 Res. SA 28 Res. AE 29 Res. 30 Res. 31 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ADDRHI[15:0] rw 2862/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 31 AE: Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. Bit 30 SA: Source Address When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address x[47:0] is used to compare with the DA fields of the received packet. Bits 29:24 MBC[5:0]: Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: Bit 29: Register 194[15:8] Bit 28: Register 194[7:0] Bit 27: Register 195[31:24] .. Bit 24: Register 195[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. Bits 23:16 Reserved, must be kept at reset value. Bits 15:0 ADDRHI[15:0]: MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address. DocID029587 Rev 3 2863/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 MMC control register (MMC_CONTROL) Address offset: 0x0700 Reset value: 0x0000 0000 This register configures the MMC operating mode. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. CNTPRSTLVL CNTPRST CNTFREEZ RSTONRD CNTSTOPRO CNTRST 16 UCDBC 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 rw rw rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 UCDBC: Update MMC Counters for Dropped Broadcast Packets The CNTRST bit has a higher priority than the CNTPRST bit. Therefore, when the software tries to set both bits in the same write cycle, all counters are cleared and the CNTPRST bit is not set. When set, the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of ETH_MACPFR register. When reset, the MMC Counters are not updated for dropped Broadcast packets. Bits 7:6 Reserved, must be kept at reset value. Bit 5 CNTPRSTLVL: Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2Kbytes) and all packet-counters get preset to 0x7FFF_FFF0 (Half 16). When this bit is high and the CNTPRST bit is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (Full 2Kbytes) and all packet-counters get preset to 0xFFFF_FFF0 (Full 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and packet counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. Bit 4 CNTPRST: Counters Preset When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle. This bit, along with the CNTPRSTLVL bit, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. Bit 3 CNTFREEZ: MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. 2864/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 2 RSTONRD: Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. Bit 1 CNTSTOPRO: Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. Bit 0 CNTRST: Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. MMC Rx interrupt register (MMC_RX_INTERRUPT) Address offset: 0x0704 Reset value: 0x0000 0000 This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: • Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). • Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXUCGPIS Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. RXALGNERPIS RXCRCERPIS Res. Res. Res. Res. Res. r Res. r Res. r Res. RXLPIUSCIS 30 RXLPITRCIS 31 Res. When the Counter Stop Rollover is set, interrupts are set but the counter remains at allones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. r r Bits 31:28 Reserved, must be kept at reset value. Bit 27 RXLPITRCIS: MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Bit 26 RXLPIUSCIS: MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Bits 25:18 Reserved, must be kept at reset value. DocID029587 Rev 3 2865/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 17 RXUCGPIS: MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. Bits 16:7 Reserved, must be kept at reset value. Bit 6 RXALGNERPIS: MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. Bit 5 RXCRCERPIS: MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. Bits 4:0 Reserved, must be kept at reset value. MMC Tx interrupt register (MMC_TX_INTERRUPT) Address offset: 0x0708 Reset value: 0x0000 0000 This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at allones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. 2866/3178 Res. Res. TXGPKTIS Res. Res. Res. Res. Res. r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 TXLPITRCIS 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 TXSCOLGPIS 29 Res. 30 TXMCOLGPIS 31 TXLPIUSCIS The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. r r r DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:28 Reserved, must be kept at reset value. Bit 27 TXLPITRCIS: MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Bit 26 TXLPIUSCIS: MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Bits 25:22 Reserved, must be kept at reset value. Bit 21 TXGPKTIS: MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value. Bits 20:16 Reserved, must be kept at reset value. Bit 15 TXMCOLGPIS: MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. Bit 14 TXSCOLGPIS: MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. Bits13:0 Reserved, must be kept at reset value. DocID029587 Rev 3 2867/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 MMC Rx interrupt mask register (MMC_RX_INTERRUPT_MASK) Address offset: 0x070C Reset value: 0x0000 0000 Res. Res. Res. Res. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXCRCERPIM Res. Res. Res. Res. Res. Res. Res. rw 14 RXALGNERPIM RXUCGPIM Res. r 15 Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 RXLPITRCIM 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 RXLPIUSCIM The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values. rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bit 27 RXLPITRCIM: MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Bit 26 RXLPIUSCIM: MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Bits 25:18 Reserved, must be kept at reset value. Bit 17 RXUCGPIM: MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. Bits16:7 Reserved, must be kept at reset value. Bit 6 RXALGNERPIM: MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. Bit 5 RXCRCERPIM: MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. Bits 4:0 Reserved, must be kept at reset value. 2868/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller MMC Tx interrupt mask register (MMC_TX_INTERRUPT_MASK) Address offset: 0x0710 Reset value: 0x0000 0000 This register maintains the masks for interrupts generated from all Transmit statistics counters. Res. Res. Res. Res. Res. Res. rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. TXGPKTIM Res. r 15 Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 TXLPITRCIM 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 TXSCOLGPIM 29 Res. 30 TXMCOLGPIM 31 TXLPIUSCIM The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration. rw rw Bits 31:28 rw Reserved, must be kept at reset value. Bit 27 TXLPITRCIM: MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Bit 26 TXLPIUSCIM: MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Bits 25:21 Reserved, must be kept at reset value. Bit 21 TXGPKTIM: MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value. Bits 20:16 RESERVED_TXGOCTIM: Reserved. Bit 15 TXMCOLGPIM: MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. Bit 14 TXSCOLGPIM: MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. Bits 13:0 Reserved, must be kept at reset value. DocID029587 Rev 3 2869/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Tx single collision good packets register (TX_SINGLE_COLLISION_GOOD_PACKETS) Address offset: 0x074C Reset value: 0x0000 0000 This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXSNGLCOLG[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r TXSNGLCOLG[151:0] r r Bits 31:0 TXSNGLCOLG[31:0]: Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode. Tx multiple collision good packets register (TX_MULTIPLE_COLLISION_GOOD_PACKETS) Address offset: 0x0750 Reset value: 0x0000 0000 This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXMULTCOLG[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r TXMULTCOLG[15:0] r r Bits 31:0 TXMULTCOLG[31:0]: Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode. Tx packet count good register (TX_PACKET_COUNT_GOOD) Address offset: 0x0768 Reset value: 0x0000 0000 This register provides the number of good packets transmitted by Ethernet peripheral. 2870/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r TXPKTG[31:16] TXPKTG[15:0] r r r r r r r r r Bits 31:0 TXPKTG[31:0]: Tx Packet Count Good This field indicates the number of good packets transmitted. Rx CRC error packets register (RX_CRC_ERROR_PACKETS) Address offset: 0x0794 Reset value: 0x0000 0000 This register provides the number of packets received by Ethernet peripheral with CRC error. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXCRCERR[31:16] r r r r r r r 15 14 13 12 11 10 9 r r r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r RXCRCERR[15:0] r r r r r r r r r Bits 31:0 RXCRCERR[31:0]: Rx CRC Error Packets This field indicates the number of packets received with CRC error. Rx alignment error packets register (RX_ALIGNMENT_ERROR_PACKETS) Address offset: 0x0798 Reset value: 0x0000 0000 This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RXALGNERR[31:16] RXALGNERR[15:0] r r r r r r r r r Bits 31:0 RXALGNERR[31:0]: Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode. DocID029587 Rev 3 2871/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Rx unicast packets good register (RX_UNICAST_PACKETS_GOOD) Address offset: 0x07C4 Reset value: 0x0000 0000 This register provides the number of good unicast packets received by Ethernet peripheral. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXUCASTG[31:16] r r r r r r r 15 14 13 12 11 10 9 r r r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r 17 16 RXUCASTG[15:0] r r r r r r r r r Bits 31:0 RXUCASTG[31:0]: Rx Unicast Packets Good This field indicates the number of good unicast packets received. Tx LPI microsecond timer register (TX_LPI_USEC_CNTR) Address offset: 0x07EC Reset value: 0x0000 0000 This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r TXLPIUSC[31:16] TXLPIUSC[15:0] r r r r r r r r r Bits 31:0 TXLPIUSC[31:0]: Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. Tx LPI transition counter register (TX_LPI_TRAN_CNTR) Address offset: 0x07F0 Reset value: 0x0000 0000 This register provides the number of times Ethernet peripheral has entered Tx LPI. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXLPITRC[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r TXLPITRC[15:0] 2872/3178 r r DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:0 TXLPITRC[31:0]: Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register), the counter will increment. Rx LPI microsecond counter register (RX_LPI_USEC_CNTR) Address offset: 0x07F4 Reset value: 0x0000 0000 This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RXLPIUSC[31:16] RXLPIUSC[15:0] r r r r r r r r r Bits 31:0 RXLPIUSC[31:0]: Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond. Rx LPI transition counter register (RX_LPI_TRAN_CNTR) Address offset: 0x07F8 Reset value: 0x0000 0000 This register provides the number of times Ethernet peripheral has entered Rx LPI. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXLPITRC[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r RXLPITRC[15:0] r r Bits 31:0 RXLPITRC[31:0]: Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. DocID029587 Rev 3 2873/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 L3 and L4 control 0 register (ETH_MACL3L4C0R) Address offset: 0x0900 Reset value: 0x0000 0000 18 17 16 Res. Res. Res. Res. Res. Res. Res. L4PEN0 15 14 13 12 11 10 9 L3HDBM0[4:0] rw Bits 31:22 rw rw rw 8 7 6 rw rw L3HSBM0[4:0] rw rw rw rw rw rw rw rw 5 4 3 2 1 0 L3PEN0 19 Res. 20 L4SPM0 21 L3SAM0 22 L4SPIM0 23 L3SAIM0 24 L4DPM0 25 L3DAM0 26 L4DPIM0 27 L3DAIM0 28 Res. 29 Res. 30 Res. 31 Res. The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration. rw rw rw rw rw rw Reserved, must be kept at reset value. Bit 21 L4DPIM0: Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4DPM0 bit is set high. Bit 20 L4DPM0: Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. Bit 19 L4SPIM0: Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4SPM0 bit is set high. Bit 18 L4SPM0: Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. Bit 17 Reserved, must be kept at reset value. Bit 16 L4PEN0: Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set. 2874/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 15:11 L3HDBM0[4:0]: Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field: 0: No bits are masked. 1: LSb[0] is masked 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. IPv6 Packets: Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: 0: No bits are masked. 1: LSb[0] is masked. 2: Two LSbs [1:0] are masked .. 127: All bits except MSb are masked. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set. Bits 10:6 L3HSBM0[4:0]: Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: 0: No bits are masked. 1: LSb[0] is masked 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. IPv6 Packets: This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high. Bit 5 L3DAIM0: Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when the L3DAM0 bit is set high. Bit 4 L3DAM0: Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering. Bit 3 L3SAIM0: Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when the L3SAM0 bit is set. DocID029587 Rev 3 2875/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 2 L3SAM0: Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering. Bit 1 Reserved, must be kept at reset value. Bit 0 L3PEN0: Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set. Layer4 address filter 0 register (ETH_MACL4A0R) Address offset: 0x0904 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L4DP0[15:0] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L4SP0[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 L4DP0[15:0]: Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. Bits 15:0 L4SP0[15:0]: Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. 2876/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Layer 3 Address 0 filter 0 register (ETH_MACL3A00R) Address offset: 0x0910 Reset value: 0x0000 0000 For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L3A00[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A00[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 L3A00[31:0]: Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets. Layer3 address 1 filter 0 register (ETH_MACL3A10R) Address offset: 0x0914 Reset value: 0x0000 0000 For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L3A10[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A10[15:0] rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 2877/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 31:0 L3A10[31:0]: Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. Layer3 Address 2 filter 0 register (ETH_MACL3A20) Address offset: 0x0918 Reset value: 0x0000 0000 The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A20[31:16] L3A20[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 L3A20[31:0]: Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. Layer3 Address 3 filter 0 register (ETH_MACL3A30) Address offset: 0x091C Reset value: 0x0000 0000 The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L3A30[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A30[15:0] rw 2878/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:0 L3A30[31:0]: Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. L3 and L4 control 1 register (ETH_MACL3L4C1R) Address offset: 0x0930 Reset value: 0x0000 0000 21 20 19 18 17 16 Res. Res. RESERVED_DMCHEN1 Res. Res. Res. Res. Res. Res. Res. L4PEN1 r 15 14 13 12 11 10 L3HDBM1[4:0] rw Bits 31:22 rw rw rw 9 8 7 6 rw rw L3HSBM1[4:0] rw rw rw rw rw rw rw rw 5 4 3 2 1 0 L3PEN1 22 Res. 23 L4SPM1 24 L3SAM1 25 L4SPIM1 26 L3SAIM1 27 L4DPM1 28 L3DAM1 29 L4DPIM1 30 L3DAIM1 31 Res. The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. rw rw rw rw rw rw Reserved, must be kept at reset value. Bit 21 L4DPIM1: Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4DPM0 bit is set high. Bit 20 L4DPM1: Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching. Bit 19 L4SPIM1: Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when the L4SPM0 bit is set high. Bit 18 L4SPM1: Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching. Bit 17 Reserved, must be kept at reset value. DocID029587 Rev 3 2879/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 16 L4PEN1: Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching. The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set. Bits 15:11 L3HDBM1[4:0]: Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field: 0: No bits are masked. 1: LSb[0] is masked 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. IPv6 Packets: Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: 0: No bits are masked. 1: LSb[0] is masked. 2: Two LSbs [1:0] are masked .. 127: All bits except MSb are masked. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set. Bits 10:6 L3HSBM1[4:0]: Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: 0: No bits are masked. 1: LSb[0] is masked 2: Two LSbs [1:0] are masked .. 31: All bits except MSb are masked. IPv6 Packets: This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high. Bit 5 L3DAIM1: Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when the L3DAM0 bit is set high. Bit 4 L3DAM1: Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering. 2880/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 3 L3SAIM1: Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when the L3SAM0 bit is set. Bit 2 L3SAM1: Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering. Bit 1 Reserved, must be kept at reset value. Bit 0 L3PEN1: Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set. Layer 4 address filter 1 register (ETH_MACL4A1R) Address offset: 0x0934 Reset value: 0x0000 0000 The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L4DP1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L4SP1[15:0] rw rw rw rw rw rw rw rw rw DocID029587 Rev 3 2881/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bits 31:16 L4DP1[15:0]: Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets. Bits 15:0 L4SP1[15:0]: Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the L4PEN0 and L4DPM0 bits are set in ETH_MACL3L4C0R register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets. Layer3 address 0 filter 1 Register (ETH_MACL3A01R) Address offset: 0x0940 Reset value: 0x0000 0000 For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A01[31:0] L3A01[31:0] rw rw rw rw rw rw rw rw rw Bits 31:0 L3A01[31:0]: Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets. 2882/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Layer3 address 1 filter 1 register (ETH_MACL3A11R) Address offset: 0x0944 Reset value: 0x0000 0000 For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L3A11[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A11[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 L3A11[31:0]: Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset and the L3SAM0 bit is set in the ETH_MACL3L4C0R register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets. Layer3 address 2 filter 1 Register (ETH_MACL3A21R) Address offset: 0x0948 Reset value: 0x0000 0000 The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L3A21[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A21[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 L3A21[31:0]: Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. DocID029587 Rev 3 2883/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Layer3 address 3 filter 1 register (ETH_MACL3A31R) Address offset: 0x94C Reset value: 0x0000 0000 The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L3A31[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw L3A31[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 L3A31[31:0]: Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are set in the ETH_MACL3L4C0R register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets. When the L3PEN0 bit is reset in the ETH_MACL3L4C0R register, this field is not used. Timestamp control Register (ETH_MACTSCR) Address offset: 0x0B00 Reset value: 0x0000 2000 Res. Res. Res. Res. CSC TSENMACADDR r rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSENALL Res. Res. TSADDREG Res. TSUPDT TSINIT TSCFUPDT TSENA SNAPTYPSEL[1:0] 16 15 rw rw rw rw rw rw rw rw rw rw rw rw rw 2884/3178 17 Res. 18 TSCTRLSSR 19 Res. 20 TSVER2ENA 21 Res. 22 TSIPENA 23 Res. 24 TSIPV6ENA 25 Res. 26 TSIPV4ENA 27 Res. 28 TSEVNTENA 29 Res. 30 TSMSTRENA 31 TXTSSTSM This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver. DocID029587 Rev 3 rw rw RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:25 Reserved, must be kept at reset value. Bit 24 TXTSSTSM: Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSTSMIS bit of the ETH_MACTxTSSNR register. When this bit is reset, the MAC ignores the timestamp status of current packet if the timestamp status of previous packet is not read by the software. The MAC indicates this by setting the TXTSSTSHI bit of the ETH_MACTxTSSSR register. Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSC: Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set, the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct, for changes made to origin timestamp and/or correction field as part of one step timestamp operation. The application shall form the packet with these two dummy bytes. When reset, no updates are done to keep the UDP checksum correct. The application shall form the packet with UDP checksum set to 0. Bit 18 TSENMACADDR: Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. When this bit is set, received PTP packets with DA containing a special multicast or unicast address that matches the one programmed in MAC address registers are considered for processing as indicated below, when PTP is directly sent over Ethernet. For normal time stamping operation, MAC address registers 0 to 31 is considered for unicast destination address matching. For PTP offload, only MAC address register 0 is considered for unicast destination address matching. Bits 17:16 SNAPTYPSEL[1:0]: Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, decide the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Timestamp Snapshot Dependency on Register Bits Table. Bit 15 TSMSTRENA: Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. Bit 14 TSEVNTENA: Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When this bit is reset, the snapshot is taken for all messages except Announce, Management, and Signaling. For more information about the timestamp snapshots, see Timestamp Snapshot Dependency on Register Bits Table. Bit 13 TSIPV4ENA: Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset, the MAC ignores the PTP transported over IPv4-UDP packets. This bit is set by default. Bit 12 TSIPV6ENA: Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear, the MAC ignores the PTP transported over IPv6-UDP packets. Bit 11 TSIPENA: Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset, the MAC ignores the PTP over Ethernet packets. DocID029587 Rev 3 2885/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 10 TSVER2ENA: Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset, the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588 formats are described in 'PTP Processing and Control'. Bit 9 TSCTRLSSR: Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment must be programmed correctly depending on the PTP reference clock frequency and the value of this bit. Bit 8 TSENALL: Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC. Bits 7:6 Reserved, must be kept at reset value. Bit 5 TSADDREG: Update Addend Register When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set. Bit 4 Reserved, must be kept at reset value. Bit 3 TSUPDT: Update Timestamp When this bit is set, the system time is updated (added or subtracted) with the value specified in ETH_MACSTSUR and ETH_MACSTNUR. This bit should be zero before updating it. This bit is reset when the update is complete in hardware. The Timestamp Higher Word register (if enabled during core configuration) is not updated. Bit 2 TSINIT: Initialize Timestamp When this bit is set, the system time is initialized (overwritten) with the value specified in the MAC Register 80 (System Time Seconds Update Register) and MAC Register 81 (System Time Nanoseconds Update Register). This bit should be zero before it is updated. This bit is reset when the initialization is complete. The Timestamp Higher Word register (if enabled during core configuration) can only be initialized. Bit 1 TSCFUPDT: Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. When this bit is reset, Coarse method is used to update the system timestamp. Bit 0 TSENA: Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. When disabled, timestamp is not added for transmit and receive packets and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the Receive side, the MAC processes the 1588 packets only if this bit is set. Table 545 indicates the PTP messages for which a snapshot is taken depending on the SNAPTYPSEL field in ETH_MACTSCR register. 2886/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Table 545. Timestamp Snapshot Dependency on Register Bits SNAPTYPS EL TSMSTREN TSEVNTEN A A PTP Messages 00 X 0 SYNC, Follow_Up, Delay_Req, Delay_Resp 00 0 1 SYNC 00 1 1 Delay_Req 01 X 0 SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up 01 0 1 SYNC, Pdelay_Req, Pdelay_Resp 01 1 1 Delay_Req, Pdelay_Req, Pdelay_Resp 10 X X SYNC, Delay_Req 11 X X Pdelay_Req, Pdelay_Resp Sub-second increment register (ETH_MACSSIR) Address offset: 0x0B04 Reset value: 0x0000 0000 11 10 9 8 rw rw rw SNSINC[7:0] rw rw rw rw rw 19 18 17 16 SSINC[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. 12 20 Res. Res. 13 21 Res. Res. 14 22 Res. Res. 15 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 Res. The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow. DocID029587 Rev 3 2887/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:24 RM0433 Reserved, must be kept at reset value. Bits 23:16 SSINC[7:0]: Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when the PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in ETH_MACTSCR]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465 ns. In this case, you should program a value of 43 (0x2B) which is derived by 20 ns/0.465. SNSINC SSINC[7:0]:Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value, represented in nanoseconds multiplied by 2^8. This value is accumulated with the sub-nanoseconds field of the sub-second register. For example, when TSCTRLSSR field in the ETH_MACTSCR register is set. and if the required increment is 5.3ns, then SSINC should be 0x05 and SNSINC should be 0x4C. Bits 15:0 2888/3178 Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller System time seconds register (ETH_MACSTSR) Address offset: 0x0B08 Reset value: 0x0000 0000 The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r TSS[31:16] TSS[15:0] r r r r r r r r r Bits 31:0 TSS[31:0]: Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC. System time nanoseconds register (ETH_MACSTNR) Address offset: 0x0B0C Reset value: 0x0000 0000 The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 30 29 28 27 26 25 24 Res. 31 23 22 21 20 19 18 17 16 TSSS[30:16] r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r TSSS[15:0] Bit 31 r r Reserved, must be kept at reset value. Bits 30:0 TSSS[30:0]: Timestamp Sub-seconds The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When Bit 9 is set in ETH_MACTSCR, each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to zero. DocID029587 Rev 3 2889/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 System time seconds update register (ETH_MACSTSUR) Address offset: 0x0B10 Reset value: 0x0000 0000 The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TSS[31:0] TSS[31:0] rw rw rw rw rw rw rw rw rw Bits 31:0 TSS[31:0]: Timestamp Seconds The value in this field is the sub-second part of the update. When ADDSUB is reset, this field must be programmed with the sub-second part of the update value, with an accuracy based on the TSCTRLSSR bit of the ETH_MACTSCR register. When ADDSUB is set, then this field must be programmed with the complement of the sub-second part of the update value as described below. When TSCTRLSSR is set, then the programmed value must be 10^9 - . When TSCTRLSSR is reset, then the programmed value must be 2^31 - For example, when TSCTRLSSR bit is set and if 2.000000001 seconds need to be subtracted from the system time, then the TSS field in the MAC_Timestamp Seconds update register must be 0xFFFF_FFFE (that is, 2^32 - 2), ADDSUB bit in this register should be set, and the TSSS field must be 0x3B9A_C9FF (that is, 10^9 - 1). System time nanoseconds update register (ETH_MACSTNUR) Address offset: 0x0B14 Reset value: 0x0000 0000 This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input. 30 29 28 27 26 25 24 ADDSUB 31 23 22 21 20 19 18 17 16 TSSS[30:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TSSS[15:0] rw 2890/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 31 ADDSUB: Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. Bits 30:0 TSSS[30:0]: Timestamp Sub-seconds The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When the TSCTRLSSR bit is set in the ETH_MACTSCR register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. Timestamp addend register (ETH_MACTSAR) Address offset: 0x0B18 Reset value: 0x0000 0000 The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSAR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw TSAR[15:0] rw rw Bits 31:0 TSAR[31:0]: Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. Timestamp status register (ETH_MACTSSR) Address offset: 0x0B20 Reset value: 0x0000 0000 Res. Res. r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. TSTRGTERR0 AUXTSTRIG TSTARGT0 TSSOVF 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 TXTSSIS 31 ATSSTM The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register. r r r r ATSNS[4:0] r DocID029587 Rev 3 ATSSTN[3:0] 2891/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:30 RM0433 Reserved, must be kept at reset value. Bits 29:25 ATSNS[4:0]: Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected. Bit 24 ATSSTM: Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected. Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 ATSSTN[3:0]: Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: Bit 16: Auxiliary trigger 0 Bit 17: Auxiliary trigger 1 Bit 18: Auxiliary trigger 2 Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. Bit 15 TXTSSIS: Tx Timestamp Status Interrupt Status When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the ETH_MACTxTSSNR and ETH_MACTxTSSSR registers. When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the ETH_MACTxTSSNR and ETH_MACTxTSSSR registers, for PTO generated Delay Request and Pdelay request packets. This bit is cleared when the ETH_MACTxTSSSR register is read. This bit is reserved in all other configurations. Bits 14:4 Reserved, must be kept at reset value. Bit 3 TSTRGTERR0: Timestamp Target Time Error This bit is set when the latest target time programmed in the ETH_MACPPS_Target_Time_seconds and ETH_MACPPS_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Bit 2 AUXTSTRIG: Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected. Bit 1 TSTARGT0: Timestamp Target Time Reached When set, this bit indicates that the value of system time is greater than or equal to the value specified in the ETH_MACPPS_Target_Time_seconds and ETH_MACPPS_Target_Time_Nanoseconds registers. Bit 0 TSSOVF: Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. 2892/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Tx timestamp status nanoseconds register (ETH_MACTxTSSNR) Address offset: 0x0B30 Reset value: 0x0000 0000 This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. 30 29 28 27 26 25 TXTSSMIS 31 24 23 22 21 20 19 18 17 16 TXTSSLO[30:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r TXTSSLO[15:0] r r r r r r r r r Bit 31 TXTSSMIS: Transmit Timestamp Status Missed When this bit is set, it indicates one of the following: – The timestamp of the current packet is ignored if TXTSSTSM bit of the ETH_MACTSCR register is reset – The timestamp of the previous packet is overwritten with timestamp of the current packet if TXTSSTSM bit of the ETH_MACTSCR register is set. Bits 30:0 TXTSSLO[30:0]: Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp. Tx timestamp status seconds register (ETH_MACTxTSSSR) Address offset: 0x0B34 Reset value: 0x0000 0000 The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXTSSHI[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r TXTSSHI[15:0] r r Bits 31:0 TXTSSHI[31:0]: Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp. DocID029587 Rev 3 2893/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Auxiliary control register (ETH_MACACR) Address offset: 0x0B40 Reset value: 0x0000 0000 The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATSEN3 ATSEN2 ATSEN1 ATSEN0 Res. Res. Res. ATSFC 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 rw rw rw rw Bits 31:8 rw Reserved, must be kept at reset value. Bit 7 ATSEN3: Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. When this bit is set, the auxiliary snapshot of the event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when one of the following is true: – The Add IEEE 1588 Auxiliary Snapshot option is not selected while configuring the core. – The selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. Bit 6 ATSEN2: Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. When this bit is set, the auxiliary snapshot of the event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when one of the following is true: – The Add IEEE 1588 Auxiliary Snapshot option is not selected while configuring the core. – The selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than 3. Bit 5 ATSEN1: Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set, the auxiliary snapshot of the event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when one of the following is true: – The Add IEEE 1588 Auxiliary Snapshot option is not selected while configuring the core. – The selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than 2. 2894/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bit 4 ATSEN0: Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set, the auxiliary snapshot of the event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected while configuring the core. Bits 3:1 Reserved, must be kept at reset value. Bit 0 ATSFC: Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, the auxiliary snapshots are stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected while configuring the core. Auxiliary timestamp nanoseconds register (ETH_MACATSNR) Address offset: 0x0B48 Reset value: 0x0000 0000 The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AUXTSLO[30:16] Res. 31 r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r AUXTSLO[15:0] r r Bit 31 Reserved, must be kept at reset value. Bits 30:0 AUXTSLO[30:0]: Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. DocID029587 Rev 3 2895/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Auxiliary timestamp seconds register (ETH_MACATSSR) Address offset: 0x0B4C Reset value: 0x0000 0000 The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AUXTSHI[31:16] r r r r r r r 15 14 13 12 11 10 9 r r r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r AUXTSHI[15:0] r r r r r r r r r Bits 31:0 AUXTSHI[31:0]: Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. Timestamp Ingress asymmetric correction register (ETH_MACTSIACR) Address offset: 0x0B50 Reset value: 0x0000 0000 The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw OSTIAC[31:16] OSTIAC[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 OSTIAC[31:0]: One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 2^16. For example, 2.5 ns is represented as 0x00028000. The value can also be negative, which is represented in 2's complement form with bit 31 representing the sign bit. 2896/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Timestamp Egress asymmetric correction register (ETH_MACTSEACR) Address offset: 0x0B54 Reset value: 0x0000 0000 The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSTEAC[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw OSTEAC[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 OSTEAC[31:0]: One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied by 2^16. For example, if the required correction is +2.5 ns, the programmed value must be 0xFFFD_8000, which is the 2's complement of 0x0002_8000(2.5 * 216). Similarly, if the required correction is -3.3 ns, the programmed value is 0x0003_4CCC (3.3 * 216). Timestamp Ingress correction nanosecond register (ETH_MACTSICNR) Address offset: 0x0B58 Reset value: 0x0000 0000 This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TSIC[31:16] TSIC[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 TSIC[31:0]: Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression. DocID029587 Rev 3 2897/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Timestamp Egress correction nanosecond register (ETH_MACTSECNR) Address offset: 0x0B5C Reset value: 0x0000 0000 This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSEC[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TSEC[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 TSEC[31:0]: Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression. 2898/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller PPS control register (ETH_MACPPSCR) Address offset: 0x0B70 Reset value: 0x0000 0000 The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected. 9 8 7 6 5 Res. rw Bits 31:7 Res. 10 Res. 11 Res. 12 4 3 2 1 0 rw rw rw rw PPSEN0 PPSCTRL_PPSCMD[3:0] Res. 13 Res. Res. 14 Res. Res. 15 TRGTMODSEL0[1:0] Res. 16 Res. 17 Res. 18 Res. 19 Res. 20 Res. 21 Res. 22 Res. 23 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 rw rw Reserved, must be kept at reset value. Bits 6:5 TRGTMODSEL0[1:0]: Target Time Register Mode for PPS Output This field indicates the Target Time registers (MAC registers 96 and 97) mode for PPS output signal: 00: Target Time registers are programmed only for generating the interrupt event. 01: Reserved 10: Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. 11: Target Time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. DocID029587 Rev 3 2899/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Bit 4 PPSEN0: Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode). Bits 3:0 2900/3178 PPSCTRL[3:0]: PPS Output Frequency Control This field controls the frequency of the PPS output (ptp_pps_o) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. .. 1111: The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: – When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms – When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of One clock of 50 percent duty cycle and 537 ms period Second clock of 463 ms period (268 ms low and 195 ms high) – When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of Three clocks of 50 percent duty cycle and 268 ms period Fourth clock of 195 ms period (134 ms low and 61 ms high) This behavior is because of the non-linear toggling of bits in the digital rollover mode in the ETH_MACSTNR register. DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 3:0 or PPSCMD[3:0]: Flexible PPS Output (ptp_pps_o[0]) Control Programming these bits with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The software should ensure that these bits are programmed only when they are 'all-zero'. The following list describes the values of PPSCMD0: 0000: No Command 0001: START Single Pulse This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS Width Register. 0010: START Pulse Train This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by the 'Stop Pulse train at time' or 'Stop Pulse Train immediately' commands. 0011: Cancel START This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time. 0100: STOP Pulse train at time This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses. 0101: STOP Pulse Train immediately This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010). 0110: Cancel STOP Pulse train This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command. 0111-1111: Reserved PPS target time seconds register (ETH_MACPPSTTSR) Address offset: 0x0B80 Reset value: 0x0000 0000 The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSTRH0[31:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TSTRH0[31:0] rw rw rw rw rw rw rw rw rw Bits 31:0 TSTRH0[31:0]: PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on Target Time mode selected for the corresponding PPS output in the ETH_MACPPSCR register. DocID029587 Rev 3 2901/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 PPS target time nanoseconds register (ETH_MACPPSTTNR) Address offset: 0x0B84 Reset value: 0x0000 0000 The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected. 30 29 28 27 26 25 24 TRGTBUSY0 31 23 22 21 20 19 18 17 16 TTSL0[30:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TTSL0[15:0] rw rw rw rw rw rw rw rw rw Bit 31 TRGTBUSY0: PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the ETH_MACPPSCR register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. Bits 30:0 TTSL0[30:0]: Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGTMODSEL0 field (Bits [6:5]) in ETH_MACPPSCR. When the TSCTRLSSR bit is set in the ETH_MACTSCR register, this value should not exceed 0x3B9A_C9FF. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. PPS interval register (ETH_MACPPSIR) Address offset: 0x0B88 Reset value: 0x0000 0000 The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PPSINT0[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PPSINT0[15:0] rw 2902/3178 rw rw rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:0 PPSINT0[31:0]: PPS Output Signal Interval These bits store the interval between the rising edges of PPS signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS signal output is 100 ns (that is, 5 units of sub-second increment value), you should program value 4 (5-1) in this register. PPS width register (ETH_MACPPSWR) Address offset: 0x0B8C Reset value: 0x0000 0000 The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PPSWIDTH0[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PPSWIDTH0[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 PPSWIDTH0[31:0]: PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20 ns), and width between the rising and corresponding falling edges of PPS signal output is 80 ns (that is, four units of sub-second increment value), you should program value 3 (4-1) in this register. Note: The value programmed in this register must be lesser than the value programmed in ETH_MACPP0IR register. PTP Offload control register (ETH_MACPOCR) Address offset: 0x0BC0 Reset value: 0x0000 0000 Res. 12 8 7 6 5 4 3 2 1 0 PTOEN Res. 13 Res. Res. 14 ASYNCEN Res. 15 Res. 16 APDREQEN 17 Res. 18 Res. 19 Res. 20 ASYNCTRIG 21 Res. 22 APDREQTRIG 23 Res. 24 DRRDIS 25 Res. 26 PDRDIS 27 Res. 28 Res. 29 Res. 30 Res. 31 Res. This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected. 11 10 9 rw rw rw rw rw rw rw rw rw rw DN[7:0] rw rw rw rw rw DocID029587 Rev 3 2903/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:16 RM0433 Reserved, must be kept at reset value. Bits 15:8 DN[7:0]: Domain Number This field indicates the domain Number in which the PTP node is operating. Bit 7 Reserved, must be kept at reset value. Bit 6 DRRDIS: Disable PTO Delay Request/Response response generation When this bit is set, the Delay Request and Delay response will not be generated for received SYNC and Delay request packet respectively, as required by the programmed mode. Bit 5 APDREQTRIG: Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this operation. Bit 4 ASYNCTRIG: Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation. Bit 3 Reserved, must be kept at reset value. Bit 2 APDREQEN: Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Peer-to-Peer Transparent mode. Bit 1 ASYNCEN: Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Clock Master mode. Bit 0 PTOEN: PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. PTP Source Port Identity 0 Register (ETH_MACSPI0R) Address offset: 0x0BC4 Reset value: 0x0000 0000 This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw SPI0[31:16] SPI0[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 SPI0[31:0]: Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. 2904/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller PTP Source port identity 1 register (ETH_MACSPI1R) Address offset: 0x0BC8 Reset value: 0x0000 0000 This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPI1[31:16] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw SPI1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 SPI1[31:0]: Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. PTP Source port identity 2 register (ETH_MACSPI2R) Address offset: 0x0BCC Reset value: 0x0000 0000 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. 24 Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 Res. This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw SPI2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 SPI2[15:0]: Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. DocID029587 Rev 3 2905/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Log message interval register (ETH_MACLMIR) Address offset: 0x0BD0 Reset value: 0x0000 0000 24 rw rw rw rw rw rw rw 14 13 12 11 10 9 8 Res. Res. Res. Res. 22 21 20 19 18 17 16 7 6 5 4 DRSYNCR[2:0] rw 15 Res. LMPDRI[7:0] 23 rw rw Res. 25 Res. 26 Res. 27 Res. 28 Res. 29 Res. 30 Res. 31 Res. This register contains the periodic intervals for automatic PTP packet generation. 3 2 1 0 rw rw rw LSI[7:0] rw rw rw rw rw rw Bits 31:24 LMPDRI[7:0]: Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. Bits 23:11 Reserved, must be kept at reset value. Bits 10:8 DRSYNCR[2:0]: Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. 0: DelayReq generated for every received SYNC 1: DelayReq generated every alternate reception of SYNC 2: for every 4 SYNC messages 3: for every 8 SYNC messages 4: for every 16 SYNC messages 5: for every 32 SYNC messages 6-7: Reserved The master sends this information (logMinDelayReqInterval) in the DelayResp PTP messages to the slave. The reception processes this value from the received DelayResp messages and updates this field accordingly. In the Slave mode, the host must not write/update this register unless it has to override the received value. In Master mode, the sum of this field and logSyncInterval (LSI) field is provided in the logMinDelayReqInterval field of the generated multicast Delay_Resp PTP message. Bits 7:0 LSI[7:0]: Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF. 2906/3178 DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC register map and reset values ETH_MACECR Reset value ETH_MACWTR 0 0 0 0 0 0 0 HT31T0[31:0] ETH_MACHT1R HT63T32[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVLS[1:0] ERIVLT EDVLP VTHM EVLRXS Res. EIVLS[1:0] ETH_MACVTR EIVLRXS Res. Reserved 0 0 0 0 0 0 ETH_MACVHTR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VLTI CSVL VLP ETH_MACVIR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VLTI CSVL VLP ETH_MACIVIR VLC [1:0] VLT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value VLC [1:0] VLT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0068 0x006C 0x0074 0x008C VLHT[15:0] Reserved Reset value Reserved ETH_ MACQTxFCR PT[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLT[2:0] 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. DZPQ 0x0070 VL[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x005C 0x0064 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0x0060 WTO[3:0] Reset value 0x0054 0x0058 TE RE 0 0 0 0 0 0 0 0 0 0 0 ETH_MACHT0R 0x0018 0x004C 0x0050 PCF[ 1:0] 0 DOVLTC ERSVLM ESVL VTIM ETV 0x0014 PRELEN[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0x0010 DC GPSL[13:0] Res. Res. TFE FCB_BPA 0x000C 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWE Res. Res. Res. Res. ETH_MACPFR EIPG[4:0] 0 0 0 0 0 0 0 0 0 0 RA Res. Res. Res. Res. Res. Res. Res. Res. Res. DNTU IPFE Res. Res. Res. VTFE Res. Res. Res. Res. Res. HPF SAF SAIF Reset value 0x0008 GPSLCE S2KP CST ACS WD Res. JD JE Res. FES DM LM ECRSFD DO DCRS DR Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 BL [1:0] DBF PM DAIF HMC HUC PR 0x0004 IPG[2:0] EIPGEN Res. Res. Res. Res. Res. USP SPEN DCRCC Res. Res. Reset value SARC [2:0] IPC ETH_MACCR ARPEN 0x0000 Register name Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 546. Ethernet MAC register map and reset values Reserved DocID029587 Rev 3 2907/3178 2915 0x00D0 0x00D8 ETH_ MACRXTXSR 0x00BC ETH_MACPCSR Reset value 0x00C4 ETH_MACLCSR 0x00D4 ETH_MACLTCR Reset value ETH_MACLETR 0x00DC 0x00E0 0x00F8 2908/3178 Reset value ETH_ MAC1USTCR 0 RWKPTR[4:0] 0x00C8 0x00CC Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RWKPFE GLBLUCAST Res. Res. RWKPRCVD MGKPRCVD Res. Res. RWKPKTEN MGKPKTEN PWRDWN 0x00B8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXSTSIE TXSTSIE TSIE Res. Res. Res. Res. Res. Res. LPIIE PMTIE PHYIE Res. Res. Res ETH_MACIER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RWT Res. Res. EXCOL LCOL EXDEF LCARR NCARR TJT 0x00B4 RWKFILTRST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXSTSIS TXSTSIS TSIS Res. MMCTXIS MMCRXIS MMCIS Res. Res. LPIIS PMTIS PHYIS Res. Res. Res.S 0x0094 Reserved 0x00A0 0x00A8 Reserved 0x00AC Reserved Reset value 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 LST[9:0] Reset value Reserved DocID029587 Rev 3 0 0 0 0 0 0 Reset value 0 0 0 0x03E8 0 0 0 0 LPIET[16:0] Res. Res. Res. 0x00C0 ETH_MACISR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPITCSE LPIATE LPITXA PLSEN PLS LPIEN Res. Res. Res. Res. Res. Res. RLPIST TLPIST Res. Res. Res. Res. RLPIEX RLPIEN TLPIEX TLPIEN 0x00B0 Res. Res. Res. Res. Res. Res. Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETH_MACRxFCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UP RFE 0x0090 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Table 546. Ethernet MAC register map and reset values (continued) Reset value 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 ETH_ MACRWKPFR WKUPFRMFTR[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIC_1US_CNTR[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Register name 0x00FC 0x010C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 Reset value RPESTS RXFIFOSIZE[4:0] SPRAM TXFIFOSIZE[4:0] ADVTHWORD PTOEN OSTEN Res. Res. RXCHCNT[3:0] Res. Res. 0 0 0 0 RXQCNT[3 :0] 0 0 0 0 CR[3:0] Res. Res. Res. SKAP GOC_1 GOC_0 C45E MB NTC[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 MD[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved ETH_MACARPAR ARPPA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0214 0x02FC 0x0304 RDA[4:0] RA[15:0] Reset value Reserved ETH_MACA0HR Reset value AE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0300 PA[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 ETH_ MACMDIODR 0x0208 0x020C 0x0AE0 0 0 0 0 Res. ETH_MACMDIOAR Reset value 0x0204 0 0 0 0 TXQCNT[3: 0] Reserved Res. Res. Res. Res. PSE BTB 0x0200 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 TXCHCNT[3:0] Res. Res. PPSOUTNUM[2:0] 0 0 1 0x012C 0x01FC ADDR64[1:0] POUOST Res. RAVSEL AVSEL DBGMEMA TSOEN SPHEN DCBEN HASHTBLSZ[1:0] Res. L3L4FNUM[3:0] 1 0 0 0 1 1 Res. Res. ETH_MACHWF2R 0 0 1 0 AUXSNAPNUM[2:0] ETH_MACHWF1R Reset value 0x0124 0 0 0 Reserved Res. 0x0118 0x0120 SNPSVER[7:0] RFCFCSTS[1:0] ETH_MACDR USERVER[7:0] 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 TPESTS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value TFCSTS[1:0] 0x0114 ETH_MACVR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0110 Reserved Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 546. Ethernet MAC register map and reset values (continued) 1 ADDRHI[15:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ETH_MACA0LR ADDRLO[31:0] Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DocID029587 Rev 3 2909/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 0x0314 0x0318 0x031C Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ETH_MACA2HR Reset value Res. Res. Res. Res. Res. Res. Res. Res. ADDRLO[31:0] MBC[5:0] 0 0 0 0 0 0 0 0 ADDRHI[15:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ETH_MACA2LR ADDRLO[31:0] Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ETH_MACA3HR Reset value MBC[5:0] 0 0 0 0 0 0 0 0 ADDRHI[15:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ETH_MACA3LR ADDRLO[31:0] Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x0320 0x06FC Reserved MMC_CONTROL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UCDBC Res. Res. CNTPRSTLVL CNTPRST CNTFREEZ RSTONRD CNTSTOPRO CNTRST 0x0700 ADDRHI[15:0] Res. Res. Res. Res. Res. Res. Res. Res. 0x0310 Reset value MBC[5:0] ETH_MACA1LR AE SA 0x30C ETH_MACA1HR AE SA 0x0308 Register name AE SA Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 546. Ethernet MAC register map and reset values (continued) 0x0708 MMC_TX_ INTERRUPT Reset value 0x070C MMC_RX_ INTERRUPT_ MASK Reset value 0x0710 MMC_TX_ INTERRUPT_ MASK Reset value 2910/3178 0 0 0 0 0 Res. Res. Res. Res. TXLPITRCIS TXLPIUSCIS Res. Res. Res. Res. TXGPKTIS Res. Res. Res. Res. Res. TXMCOLGPIS TXSCOLGPIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 Res. Res. Res. Res. RXLPITRCIM RXLPIUSCIM Res. Res. Res. Res. Res. Res. Res. Res. RXUCGPIM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXALGNERPIM RXCRCERPIM Res. Res. Res. Res. Res. MMC_RX_ INTERRUPT 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. TXLPITRCIM TXLPIUSCIM Res. Res. Res. Res. TXGPKTIM Res. Res. Res. Res. Res. TXMCOLGPIM TXSCOLGPIM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0704 0 Res. Res. Res. Res. RXLPITRCIS RXLPIUSCIS Res. Res. Res. Res. Res. Res. Res. Res. RXUCGPIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXALGNERPIS RXCRCERPIS Res. Res. Res. Res. Res. Reset value 0 0 0 DocID029587 Rev 3 0 0 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Offset Register name 0x0714 0x0748 Reserved TX_SINGLE_ COLLISION_ 0x074C GOOD_PACKETS 0x0750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_MULTIPLE_ COLLISION_ GOOD_PACKETS TXMULTCOLG[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved TX_PACKET_ COUNT_GOOD TXPKTG[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x076C 0x0790 0x0794 TXSNGLCOLG[31:0] Reset value 0x0754 0x0764 0x0768 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 546. Ethernet MAC register map and reset values (continued) Reserved RX_CRC_ERROR_ PACKETS RXCRCERR[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_ALIGNMENT_ RXALGNERR[31:0] 0x0798 ERROR_PACKETS Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x079C 0x07C0 Reserved RX_UNICAST_ 0x07C4 PACKETS_GOOD Reset value 0x07C8 0x07E8 RXUCASTG[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x07EC TX_LPI_USEC_ CNTR TXLPIUSC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x07F0 TX_LPI_TRAN_ CNTR TXLPITRC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x07F4 RX_LPI_USEC_ CNTR RXLPIUSC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x07F8 RX_LPI_TRAN_ CNTR RXLPITRC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x07FC 0x08FC Reserved DocID029587 Rev 3 2911/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0900 ETH_ MACL3L4C0R Reset value Reset value 0x091C ETH_MACL3A00R L3A00[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACL3A10R L3A10[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACL3A20R L3A20[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACL3A30R L3A30[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0920 0x092C ETH_MACL3L4C1R Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. L4DPIM1 L4DPM1 L4SPIM1 L4SPM1 Res. L4PEN1 0x0930 Reserved Reset value 0x0934 0 0 0 0 ETH_MACL4A1R Reset value 0x0944 0x0948 0x094C 0 L4SP1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved ETH_MACL3A01R L3A01[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACL3A11R L3A11[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACL3A21R L3A21[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACL3A31R L3A31[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0950 0x0AFC Reserved ETH_MACTSCR Reset value 2912/3178 Res. Res. Res. Res. Res. Res. Res. TXTSSTSM Res. Res. Res. Res. CSC TSENMACADDR 0x0B00 L3HSBM 1[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L4DP1[15:0] 0x0938 0x093C 0x0940 L3HDBM1 [4:0] L3DAIM1 L3DAM1 L3SAIM1 L3SAM1 Res. L3PEN1 0x0918 Reserved 0 0 TSMSTRENA TSEVNTENA TSIPV4ENA TSIPV6ENA TSIPENA TSVER2ENA TSCTRLSSR TSENALL Res. Res. TSADDREG Res. TSUPDT TSINIT TSCFUPDT TSENA 0x0914 0 L4SP0[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0908 0x090C 0x0910 L3HSBM0 [4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L4DP0[15:0] SNAPTYPSEL[1:0] 0x0904 0 0 0 0 ETH_MACL4A0R L3HDBM0 [4:0] L3DAIM0 L3DAM0 L3SAIM0 L3SAM0 Res. L3PEN0 Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. L4DPIM0 L4DPM0 L4SPIM0 L4SPM0 Res. L4PEN0 Table 546. Ethernet MAC register map and reset values (continued) 0 0 0 0 0 0 1 0 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller 0x0B0C 0x0B10 0x0B14 TSS[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACSTNR Reset value TSSS[30:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACSTSUR TSS[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACSTNUR TSSS[30:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACTSAR TSAR[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 TXTSSMIS ETH_MACTxTSSNR 0 0 0 0 0 TXTSSLO[30:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXTSSHI[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACACR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ATSEN3 ATSEN2 ATSEN1 ATSEN0 Res. Res. Res. ATSFC Reserved Reset value 0x0B44 0 0 0 0 ETH_MACTxTSSSR 0x0B38 0x0B3C 0x0B40 ATSSTN[3: 0] Reserved Reset value 0x0B34 ATSNS[4:0] ATSSTM Res. Res. Res. Res. ETH_MACTSSR Res. Res. Reserved 0x0B24 0x0B2C 0x0B30 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0B1C 0x0B20 RESERVED_SNSINC[7:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset value ETH_MACSTSR Reset value 0x0B18 SSINC[7:0] TXTSSIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSTRGTERR0 AUXTSTRIG TSTARGT0 TSSOVF 0x0B08 ETH_MACSSIR Res. 0x0B04 Register name ADDSUB Offset Res. Res. Res. Res. Res. Res. Res. Res. Table 546. Ethernet MAC register map and reset values (continued) 0 0 0 0 0 Reserved DocID029587 Rev 3 2913/3178 2915 Ethernet (ETH): media access control (MAC) with DMA controller RM0433 0x0B54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACATSSR AUXTSHI[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACTSIACR OSTIAC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACTSEACR OSTEAC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_ MACTSICNR TSIC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_ MACTSECNR TSEC[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0B58 0x0B5C 0x0B60 0x0B6C ETH_MACPPSCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0B70 Reserved Reset value 0 0 0 0 0 0 0 0x0B74 0x0B7C Reserved TSTRH0[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_ MACPPSTTNR 0x0B84 0x0B8C ETH_ MACPPSTTSR TRGTBUSY0 0x0B80 0x0B88 PPSCTRL_PPSCMD[3:0] 0x0B50 Reset value AUXTSLO[30:0] PPSEN0 0x0B4C ETH_MACATSNR TRGTMODSEL0[1:0] 0x0B48 Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 546. Ethernet MAC register map and reset values (continued) TTSL0[30:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACPPSIR PPSINT0[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACPPSWR PPSWIDTH0[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0B90 0x0BBC 2914/3178 Reserved DocID029587 Rev 3 RM0433 Ethernet (ETH): media access control (MAC) with DMA controller Reset value 0x0BCC 0x0BD0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACSPI0R SPI0[31:0] 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACSPI1R SPI1[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACSPI2R Reset value SPI2[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0BC8 DN[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0BC4 PDRDIS DRRDIS APDREQTRIG ASYNCTRIG Res. APDREQEN ASYNCEN PTOEN ETH_MACPOCR ETH_MACLMIR LMPDRI[7:0] Reset value 0 0 0 0 0 0 0 0 DRSYNCR[2:0] 0x0BC0 Register name Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 546. Ethernet MAC register map and reset values (continued) LSI[7:0] 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. DocID029587 Rev 3 2915/3178 2915 RM0433 HDMI-CEC controller (HDMI-CEC) 59 HDMI-CEC controller (HDMI-CEC) 59.1 Introduction Consumer Electronics Control (CEC) is part of HDMI (High-Definition Multimedia Interface) standard as appendix supplement 1. It contains a protocol that provides high-level control functions between various audiovisual products. CEC operates at low speeds, with minimum processing and memory overhead. The HDMI-CEC controller provides hardware support for this protocol. 59.2 HDMI-CEC controller main features • Complies with HDMI-CEC v1.4 Specification • Independent 32 kHz CEC kernel (refer to Section RCC kernel clock distribution) • Works in Stop mode for ultra low-power applications • Configurable Signal Free Time before start of transmission – Automatic by hardware, according to CEC state and transmission history – Fixed by software (7 timing options) • Configurable Peripheral Address (OAR) • Supports Listen mode – • • • Enables reception of CEC messages sent to destination address different from OAR without interfering with the CEC line Configurable Rx-tolerance margin – Standard tolerance – Extended tolerance Receive-Error detection – Bit rising error (BRE), with optional stop of reception (BRESTP) – Short bit period error (SBPE) – Long bit period error (LBPE) Configurable error-bit generation – on BRE detection (BREGEN) – on LBPE detection (LBPEGEN) – always generated on SBPE detection • Transmission error detection (TXERR) • Arbitration Lost detection (ARBLST) – With automatic transmission retry • Transmission underrun detection (TXUDR) • Reception overrun detection (RXOVR) DocID029587 Rev 3 2915/3178 2934 HDMI-CEC controller (HDMI-CEC) RM0433 59.3 HDMI-CEC functional description 59.3.1 HDMI-CEC pin and internal signals The CEC bus consists of a single bidirectional line that is used to transfer data in and out of the device. It is connected to a +3.3 V supply voltage via a 27 kΩ pull-up resistor. The output stage of the device must have an open-drain or open-collector to allow a wired-and connection. The HDMI-CEC controller manages the CEC bidirectional line as an alternate function of a standard GPIO, assuming that it is configured as Alternate Function Open Drain. The 27 kΩ pull-up must be added externally to the STM32. To not interfere with the CEC bus when the application power is removed, it is mandatory to isolate the CEC pin from the bus in such conditions. This could be done by using a MOS transistor, as shown on Figure 798. Table 548 lists the internal signals that are exchanged between the HDMI-CEC and other functional blocks (such as RCC and EXTI). Table 547. HDMI pin Name CEC Signal type Remarks two states: 1 = high impedance 0 = low impedance A 27 kΩ must be added externally. bidirectional Table 548. HDMI-CEC internal input/output signals 2916/3178 Signal name Signal type cec_wkup Digital output HDMI-CEC wakeup signal cec_it Digital output HDMI-CEC interrupt signal cec_pclk Digital input APB clock cec_ker_ck Digital input HDMI-CEC kernel clock Description DocID029587 Rev 3 RM0433 HDMI-CEC block diagram Figure 798. HDMI-CEC block diagram FHFBLW 670 +'0,B&(& FRQWUROOHU FHFBSFON &(&,7) FHFBNHUBFN FHFBZNXS &/. 5; 5; N+]&(& 7; NHUQHO 7; 9 &(& 3$' Nȍ ELW$3%EXV 59.3.2 HDMI-CEC controller (HDMI-CEC) 9 * &(&OLQH 6 ' 5HPRWH &(& GHYLFH :DNHLQW 06Y 9 DocID029587 Rev 3 2917/3178 2934 HDMI-CEC controller (HDMI-CEC) 59.3.3 RM0433 Message description All transactions on the CEC line consist of an initiator and one or more followers. The initiator is responsible for sending the message structure and the data. The follower is the recipient of any data and is responsible for setting any acknowledgment bits. A message is conveyed in a single frame which consists of a start bit followed by a header block and optionally an opcode and a variable number of operand blocks. All these blocks are made of a 8-bit payload - most significant bit is transmitted first followed by an end of message (EOM) bit and an acknowledge (ACK) bit. The EOM bit is set in the last block of a message and kept reset in all others. In the event that a message contains additional blocks after an EOM is indicated, those additional blocks should be ignored. The EOM bit may be set in the header block to ‘ping’ other devices, to make sure they are active. The acknowledge bit is always set to high impedance by the initiator so that it can be driven low either by the follower which has read its own address in the header or by the follower which needs to reject a broadcast message. The header consists of the source logical address field, and the destination logical address field. Note that the special address 0xF is used for broadcast messages. Figure 799. Message structure WRRSHUDQGV KLJK 67$57 LPSHGDQFH %,7 23&2'( +($'(5 23(5$1' 23(5$1' KLJK LPSHGDQFH 069 Figure 800. Blocks +($'(5%/2&. ,1,7,$725> @ '(67,1$7,21> @ (20 $&. 23&2'(23(5$1'%/2&. '$7$> @ (20 $&. 069 59.3.4 Bit timing The format of the start bit is unique and identifies the start of a message. It should be validated by its low duration and its total duration. All remaining data bits in the message, after the start bit, have consistent timing. The high to low transition at the end of the data bit is the start of the next data bit except for the final bit where the CEC line remains high. 2918/3178 DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) Figure 801. Bit timings PVPV 67$57%,7 PVPV KLJKLPSHGDQFH ORZLPSHGDQFH PVPV '$7$%,7 ,1,7,$725/2*,&$/ PVPV KLJKLPSHGDQFH ORZLPSHGDQFH PVPV '$7$%,7 ,1,7,$725/2*,&$/ PVPV KLJKLPSHGDQFH ORZLPSHGDQFH PVPV '$7$%,7 PVPV )2//2:(5/2*,&$/ PVPD[ KLJKLPSHGDQFH ORZLPSHGDQFH 069 59.4 Arbitration All devices that have to transmit - or retransmit - a message onto the CEC line have to ensure that it has been inactive for a number of bit periods. This signal free time is defined as the time starting from the final bit of the previous frame and depends on the initiating device and the current status as shown in the table below. Figure 802. Signal free time 6LJQDOIUHHWLPH 35(9,2860(66$*( 1(:0(66$*( 069 Since only one initiator is allowed at any one time, an arbitration mechanism is provided to avoid conflict when more than one initiator begins transmitting at the same time. CEC line arbitration commences with the leading edge of the start bit and continues until the end of the initiator address bits within the header block. During this period, the initiator shall monitor the CEC line, if whilst driving the line to high impedance it reads it back to 0, it then assumes it has lost arbitration, stops transmitting and becomes a follower. DocID029587 Rev 3 2919/3178 2934 HDMI-CEC controller (HDMI-CEC) RM0433 Figure 803. Arbitration phase !RBITRATION PHASE HIGH IMPEDANCE 34!24 ")4 ).)4)!4/2;= $%34).!4)/.;= %/- !#+ 069 The Figure 804 shows an example for a SFT of three nominal bit periods Figure 804. SFT of three nominal bit periods ODVWELWRISUHYLRXVIUDPH 3TART BIT 06 9 A configurable time window is counted before starting the transmission. In the SFT=0x0 configuration the HDMI-CEC device performs automatic SFT calculation ensuring compliance with the HDMI-CEC Standard: • 2.5 data bit periods if the CEC is the last bus initiator with unsuccessful transmission • 4 data bit periods if the CEC is the new bus initiator • 6 data bit periods if the CEC is the last bus initiator with successful transmission This is done to guarantee the maximum priority to a failed transmission and the lowest one to the last initiator that completed successfully its transmission. Otherwise there is the possibility to configure the SFT bits to count a fixed timing value. Possible values are 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5 data bit periods. 59.4.1 SFT option bit In case of SFTOPT=0 configuration SFT starts being counted when the start-oftransmission command is set by software (TXSOM=1). In case of SFTOPT=1, SFT starts automatically being counted by the HDMI-CEC device when a bus-idle or line error condition is detected. If the SFT timer is completed at the time TXSOM command is set then transmission starts immediately without latency. If the SFT 2920/3178 DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) timer is still running instead, the system waits until the timer elapses before transmission can start. In case of SFTOPT=1 a bus-event condition starting the SFT timer is detected in the following cases: • In case of a regular end of transmission/reception, when TXEND/RXEND bits are set at the minimum nominal data bit duration of the last bit in the message (ACK bit). • In case of a transmission error detection, SFT timer starts when the TXERR transmission error is detected (TXERR=1). • In case of a missing acknowledge from the CEC follower, the SFT timer starts when the TXACKE bit is set, that is at the nominal sampling time of the ACK bit. • In case of a transmission underrun error, the SFT timer starts when the TXUDR bit is set at the end of the ACK bit. • In case of a receive error detection implying reception abort, the SFT timer starts at the same time the error is detected. If an error bit is generated, then SFT starts being counted at the end of the error bit. • In case of a wrong start bit or of any uncodified low impedance bus state from idle, the SFT timer is restarted as soon as the bus comes back to hi-impedance idleness. 59.5 Error handling 59.5.1 Bit error If a data bit - excluding the start bit - is considered invalid, the follower is expected to notify such error by generating a low bit period on the CEC line of 1.4 to 1.6 times the nominal data bit period, i.e. 3.6 ms nominally. Figure 805. Error bit timing (5525%,7 PVPV KLJKLPSHGDQFH ORZLPSHGDQFH 069 59.5.2 Message error A message is considered lost and therefore may be retransmitted under the following conditions: • a message is not acknowledged in a directly addressed message • a message is negatively acknowledged in a broadcast message • a low impedance is detected on the CEC line while it is not expected (line error) Three kinds of error flag can be detected when the CEC interface is receiving a data bit: DocID029587 Rev 3 2921/3178 2934 HDMI-CEC controller (HDMI-CEC) 59.5.3 RM0433 Bit Rising Error (BRE) BRE (bit rising error): is set when a bit rising edge is detected outside the windows where it is expected (see Figure 806). BRE flag also generates a CEC interrupt if the BREIE=1. In the case of a BRE detection, the message reception can be stopped according to the BRESTP bit value and an error bit can be generated if BREGEN bit is set. When BRE is detected in a broadcast message with BRESTP=1 an error bit is generated even if BREGEN=0 to enforce initiator’s retry of the failed transmission. Error bit generation can be disabled by configuring BREGEN=0, BRDNOGEN=1. 59.5.4 Short Bit Period Error (SBPE) SBPE is set when a bit falling edge is detected earlier than expected (see Figure 806). SBPE flag also generates a CEC interrupt if the SBPEIE=1. An error bit is always generated on the line in case of a SBPE error detection. An Error Bit is not generated upon SBPE detection only when Listen mode is set (LSTN=1) and the following conditions are met: 59.5.5 • A directly addressed message is received containing SBPE • A broadcast message is received containing SBPE AND BRDNOGEN=1 Long Bit Period Error (LBPE) LBPE is set when a bit falling edge is not detected in a valid window (see Figure 806). LBPE flag also generates a CEC interrupt if the LBPEIE=1. LBPE always stops the reception, an error bit is generated on the line when LBPEGEN bit is set. When LBPE is detected in a broadcast message an error bit is generated even if LBPEGEN=0 to enforce initiator’s retry of the failed transmission. Error bit generation can be disabled by configuring LBPEGEN=0, BRDNOGEN=1. Note: 2922/3178 The BREGEN=1, BRESTP=0 configuration must be avoided DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) Figure 806. Error handling /HJHQG %5(&KHFNLQJ:LQGRZ %5( 7ROHUDQFHPDUJLQV #%# INITIATOR BIT TIMING %5( /%3( 6%3( 7V 7 7Q 7 7QV 7 7Q 7 7 7QI 7 069 Table 549. Error handling timing parameters Time RXTOL ms Ts x 0 1 0.3 0 0.4 x 0.6 0 0.8 1 0.9 The latest time for a low - high transition when indicating a logical 1. x 1.05 Nominal sampling time. 1 1.2 0 1.3 The earliest time a device is permitted return to a high impedance state (logical 0). x 1.5 0 1.7 1 1.8 1 1.85 0 2.05 x 2.4 0 2.75 1 2.95 T1 Tn1 T2 Tns T3 Tn0 T4 T5 Tnf T6 Description Bit start event. The earliest time for a low - high transition when indicating a logical 1. The nominal time for a low - high transition when indicating a logical 1. The nominal time a device is permitted return to a high impedance state (logical 0). The latest time a device is permitted return to a high impedance state (logical 0). The earliest time for the start of a following bit. The nominal data bit period. The latest time for the start of a following bit. DocID029587 Rev 3 2923/3178 2934 HDMI-CEC controller (HDMI-CEC) 59.5.6 RM0433 Transmission Error Detection (TXERR) The CEC initiator sets the TXERR flag if detecting low impedance on the CEC line when it is transmitting high impedance and is not expecting a follower asserted bit. TXERR flag also generates a CEC interrupt if the TXERRIE=1. TXERR assertion stops the message transmission. Application is in charge to retry the failed transmission up to 5 times. TXERR checks are performed differently depending on the different states of the CEC line and on the RX tolerance configuration. Figure 807. TXERR detection /HJHQG 7;(55&KHFNLQJ:LQGRZ &(&LQLWLDWRUELWWLPLQJ 7ROHUDQFHPDUJLQV 7[DFNQRZOHGJH 7[DUELWUDWLRQELW 7[GDWDELW 7V 7 7Q 7 7QV 7 7Q 7 7 7QI 7 7[DUELWUDWLRQELW 7[GDWDELW 069 Table 550. TXERR timing parameters Time RXTOL ms Ts x 0 1 0.3 0 0.4 x 0.6 0 0.8 1 0.9 The latest time for a low - high transition when indicating a logical 1. x 1.05 Nominal sampling time. 1 1.2 0 1.3 The earliest time a device is permitted return to a high impedance state (logical 0). T1 Tn1 T2 Tns T3 2924/3178 Description Bit start event. The earliest time for a low - high transition when indicating a logical 1. The nominal time for a low - high transition when indicating a logical 1. DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) Table 550. TXERR timing parameters (continued) Time RXTOL ms Tn0 x 1.5 0 1.7 1 1.8 1 1.85 0 2.05 x 2.4 0 2.75 1 2.95 T4 T5 Tnf T6 59.6 Description The nominal time a device is permitted return to a high impedance state (logical 0). The latest time a device is permitted return to a high impedance state (logical 0). The earliest time for the start of a following bit. The nominal data bit period. The latest time for the start of a following bit. HDMI-CEC interrupts An interrupt can be produced: • during reception if a Receive Block Transfer is finished or if a Receive Error occurs. • during transmission if a Transmit Block Transfer is finished or if a Transmit Error occurs. Table 551. HDMI-CEC interrupts Interrupt event Event flag Enable Control bit RXBR RXBRIE End of reception RXEND RXENDIE Rx-Overrun RXOVR RXOVRIE BRE BREIE Rx-Short Bit Period Error SBPE SBPEIE Rx-Long Bit Period Error LBPE LBPEIE Rx-Missing Acknowledge Error RXACKE RXACKEIE Arbitration lost ARBLST ARBLSTIE TXBR TXBRIE End of transmission TXEND TXENDIE Tx-Buffer Underrun TXUDR TXUDRIE Tx-Error TXERR TXERRIE TXACKE TXACKEIE Rx-Byte Received RxBit Rising Error Tx-Byte Request Tx-Missing Acknowledge Error DocID029587 Rev 3 2925/3178 2934 HDMI-CEC controller (HDMI-CEC) 59.7 RM0433 HDMI-CEC registers Refer to Section 1.1 on page 98 for a list of abbreviations used in register descriptions. 59.7.1 CEC control register (CEC_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. TX EOM TX SOM CEC EN rs rs rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:3 Reserved, must be kept at reset value. Bit 2 TXEOM: Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. 0: TXDR data byte is transmitted with EOM=0 1: TXDR data byte is transmitted with EOM=1 Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message) Bit 1 TXSOM: Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). 2926/3178 DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. 0: No CEC transmission is on-going 1: CEC transmission command Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADER’s first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception Bit 0 CECEN: CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission. 0: CEC peripheral is off 1: CEC peripheral is on 59.7.2 CEC configuration register (CEC_CFGR) This register is used to configure the HDMI-CEC controller. Address offset: 0x04 Reset value: 0x0000 0000 Caution: It is mandatory to write CEC_CFGR only when CECEN=0. 31 30 29 28 27 26 25 24 LSTN Res. 22 21 20 19 18 17 16 2 1 0 OAR[14:0] rw 15 23 rw 14 Res. 13 Res. 12 Res. 11 Res. 10 Res. 9 8 7 6 5 4 3 Res. SFT OPT BRDN OGEN LBPE GEN BRE GEN BRE STP RX TOL SFT[2:0] rw rw rw rw rw rw rw Bit 31 LSTN: Listen mode LSTN bit is set and cleared by software. 0: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received. 1: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent. Bits 30:16 OAR: Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received. Bits 15:9 Reserved, must be kept at reset value. DocID029587 Rev 3 2927/3178 2934 HDMI-CEC controller (HDMI-CEC) RM0433 Bit 8 SFTOP: SFT Option Bit The SFTOPT bit is set and cleared by software. 0: SFT timer starts when TXSOM is set by software 1: SFT timer starts automatically at the end of message transmission/reception. Bit 7 BRDNOGEN: Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software. 0: BRE detection with BRESTP=1 and BREGEN=0 on a broadcast message generates an Error-Bit on the CEC line. LBPE detection with LBPEGEN=0 on a broadcast message generates an Error-Bit on the CEC line 1: Error-Bit is not generated in the same condition as above. An Error-Bit is not generated even in case of an SBPE detection in a broadcast message if listen mode is set. Bit 6 LBPEGEN: Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. 0: LBPE detection does not generate an Error-Bit on the CEC line 1: LBPE detection generates an Error-Bit on the CEC line Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0 Bit 5 BREGEN: Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. 0: BRE detection does not generate an Error-Bit on the CEC line 1: BRE detection generates an Error-Bit on the CEC line (if BRESTP is set) Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0 2928/3178 DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) Bit 4 BRESTP: Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software. 0: BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms. 1: BRE detection stops message reception Bit 3 RXTOL: Rx-Tolerance The RXTOL bit is set and cleared by software. 0: Standard tolerance margin: – Start-Bit, +/- 200 µs rise, +/- 200 µs fall. – Data-Bit: +/- 200 µs rise. +/- 350 µs fall. 1: Extended Tolerance – Start-Bit: +/- 400 µs rise, +/- 400 µs fall – Data-Bit: +/-300 µs rise, +/- 500 µs fall Bits 2:0 SFT: Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. ″ 0x0 – 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) – 4 Data-Bit periods if CEC is the new bus initiator – 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) ″ 0x1: 0.5 nominal data bit periods ″ 0x2: 1.5 nominal data bit periods ″ 0x3: 2.5 nominal data bit periods ″ 0x4: 3.5 nominal data bit periods ″ 0x5: 4.5 nominal data bit periods ″ 0x6: 5.5 nominal data bit periods ″ 0x7: 6.5 nominal data bit periods DocID029587 Rev 3 2929/3178 2934 HDMI-CEC controller (HDMI-CEC) 59.7.3 RM0433 CEC Tx data register (CEC_TXDR) Address offset: 0x8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. w w w w w w w TXD[7:0] w Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 TXD[7:0]: Tx Data register. TXD is a write-only register containing the data byte to be transmitted. 59.7.4 CEC Rx Data Register (CEC_RXDR) Address offset: 0xC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. r r r r r r r RXD[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 RXD[7:0]: Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line. 59.7.5 CEC Interrupt and Status Register (CEC_ISR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. TX ACKE TX ERR TX UDR TX END TXBR ARB LST RX ACKE LBPE SBPE BRE RX OVR RX END RXBR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 2930/3178 DocID029587 Rev 3 RM0433 HDMI-CEC controller (HDMI-CEC) Bits 31:13 Reserved, must be kept at reset value. Bit 12 TXACKE: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1. Bit 11 TXERR: Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1. Bit 10 TXUDR: Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1 Bit 9 TXEND: End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1. Bit 8 TXBR: Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1. Bit 7 ARBLST: Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1. Bit 6 RXACKE: Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1. Bit 5 LBPE: Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1. Bit 4 SBPE: Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1. DocID029587 Rev 3 2931/3178 2934 HDMI-CEC controller (HDMI-CEC) RM0433 Bit 3 BRE: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1. Bit 2 RXOVR: Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1. Bit 1 RXEND: End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1. Bit 0 RXBR: Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1. 59.7.6 CEC interrupt enable register (CEC_IER) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 3 2 1 0 Res. Res. Res. TXACK TXERR TX TXEND IE IE UDRIE IE rw rw rw rw 8 7 6 5 4 TXBR IE ARBLST IE RXACK IE LBPE IE SBPE IE rw rw rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bit 12 TXACKIE: Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software. 0: TXACKE interrupt disabled 1: TXACKE interrupt enabled Bit 11 TXERRIE: Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software. 0: TXERR interrupt disabled 1: TXERR interrupt enabled Bit 10 TXUDRIE: Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software. 0: TXUDR interrupt disabled 1: TXUDR interrupt enabled 2932/3178 DocID029587 Rev 3 RXOVR RXEND RXBR BREIE IE IE IE rw rw rw rw RM0433 HDMI-CEC controller (HDMI-CEC) Bit 9 TXENDIE: Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software. 0: TXEND interrupt disabled 1: TXEND interrupt enabled Bit 8 TXBRIE: Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software. 0: TXBR interrupt disabled 1: TXBR interrupt enabled Bit 7 ARBLSTIE: Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software. 0: ARBLST interrupt disabled 1: ARBLST interrupt enabled Bit 6 RXACKIE: Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software. 0: RXACKE interrupt disabled 1: RXACKE interrupt enabled Bit 5 LBPEIE: Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software. 0: LBPE interrupt disabled 1: LBPE interrupt enabled Bit 4 SBPEIE: Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software. 0: SBPE interrupt disabled 1: SBPE interrupt enabled Bit 3 BREIE: Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software. 0: BRE interrupt disabled 1: BRE interrupt enabled Bit 2 RXOVRIE: Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software. 0: RXOVR interrupt disabled 1: RXOVR interrupt enabled Bit 1 RXENDIE: End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software. 0: RXEND interrupt disabled 1: RXEND interrupt enabled Bit 0 RXBRIE: Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software. 0: RXBR interrupt disabled 1: RXBR interrupt enabled Caution: (*) It is mandatory to write CEC_IER only when CECEN=0 DocID029587 Rev 3 2933/3178 2934 0x14 CEC_IER 2934/3178 DocID029587 Rev 3 TXBR ARBLST RXACKE LBPE SBPE BRE RXOVR RXEND RXBR 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBRIE ARBLSTIE RXACKIE LBPEIE SBPEIE BREIE RXOVRIE RXENDIE RXBRIE Reset value TXEND Reset value TXENDIE Res. Res. CEC_TXDR Res. 0 TXUDR 0 TXUDRIE 0 Res. 0 TXERR 0 TXACKE 0 TXACKIE 0 TXERRIE 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSTN Reset value SFTOPT BRDNOGEN LBPEGEN BREGEN BRESTP RXTOL Res. Res. Res. Res. Res. Res. Res. OAR[14:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEC_CFGR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEC_ISR Res. 0x10 Res. CEC_RXDR Res. 0x0C Res. 0x08 Res. 0x04 Reset value Reset value 0 Refer to Section 2.2.2 on page 105 for the register boundary addresses. 0 0 0 0 0 0 0 0 0 TXSOM CECEN Reset value TXEOM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEC_CR Res. 0x00 Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. 59.7.7 Res. HDMI-CEC controller (HDMI-CEC) RM0433 HDMI-CEC register map The following table summarizes the HDMI-CEC registers. Table 552. HDMI-CEC register map and reset values 0 0 0 SFT[2:0] TXD[7:0] 0 0 0 0 0 0 0 RXD[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0433 Debug infrastructure 60 Debug infrastructure 60.1 Introduction The debug infrastructure allows software designers to debug and trace their embedded software. The debug features can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools. A trace port allows data to be captured for logging and analysis. The trace and debug system has been designed to support a variety of typical use cases: • Low cost trace Limited trace capability is available over the single-wire debug output. This supports code instrumentation using “printf”, tracing of data and address watchpoints, interrupt detection and program counter sampling. Single-wire trace can be maintained even when the processor is switched off or clock-stopped. • Breakpoint debugging The processor can be debugged using equipment connected to the JTAG/SWD debug port. This allows breakpoint and watchpoint setting, code stepping, memory access etc. • Tracing code execution via the trace port Trace information is combined into a single trace stream and output to a trace port analyzer in real time. An ID embedded in the trace allows the analyzer to identify the source of each information packet. • Capturing trace continuously in a circular buffer Instead of streaming it off-chip, the combined trace information can be stored on-chip in a circular buffer. The trace storage can be started and stopped by a debugger command, a software command, an external trigger signal, an internal event, etc. • Draining the buffer to the trace port The stored trace can be dumped off-chip to the trace port analyzer. The buffer draining can be initiated by the debugger, software, external trigger, internal event etc. • Reading the buffer with the debugger The debugger can read the contents of the trace buffer via the debug port. This is slower than the trace port, but allows basic trace functionality on the debugger without the cost of a trace port analyzer. • Analyzing stored trace in software The trace buffer can be read by the processor core, or transferred into system memory by DMA. This powerful feature allows built-in test software to monitor code execution in real time, analyze and identify faults, autonomously handle exceptions, etc. • Uploading stored trace The stored trace can also be uploaded to a host machine using one of the MCU’s many communications interfaces (USB, USART, SPI, I2C, Ethernet, CAN etc). This is especially useful if the trace port is not accessible, for example remote monitoring and failure analysis of a deployed product. DocID029587 Rev 3 2935/3178 3152 Debug infrastructure 60.2 RM0433 Debug infrastructure features A comprehensive set of trace and debug features is provided to support software development and system integration: • Breakpoint debugging • Code execution tracing • Software instrumentation • Cross-triggering • JTAG debug port • Serial-wire debug port • Trigger input and output • Serial-wire trace port • Trace port • ARM® CoreSight™ debug and trace components The CoreSight components are described at high level in this document. Detailed information is available in the ARM® documents referenced in Section 60.7. 60.3 Debug infrastructure functional description 60.3.1 Debug infrastructure block diagram The block diagram shows the logical partitioning of the debug infrastructure. Figure 808. Block diagram of debug infrastructure -7$* 6HULDOZLUHSRUW &RUWH[0GHEXJ 'HEXJDFFHVVSRUW 7UDFH GHEXJ VXEV\VWHP -7066:',2 -7', 6:-'3 -7'2 '$3%86 520 ':7 WDEOH )3% '$3%86 5HSOLFDWRU $+%$3 Q-7567 &RUH6LJKWFRPSRQHQW $3%' V\VWHPGHEXJEXV ,70 -7&.6:&/. /HJHQG $7% WUDFHEXV $+%' 520 WDEOH &RUWH[0 FRUH $+%$3 $3%$3 &70 FURVVWULJJHUPDWUL[ (33% 6\VWHPEXV PDWUL[ &7, 7LPHVWDPS 6LJQDOV (70 $3%PX[ 6\V520 WDEOH '%*0&8 $3%' 76* &70 6\V520 WDEOH &67) 6:7) (7) 7ULJJHU 75*287 75*,2 6\V &7, 75*,1 65$0 6HULDOZLUH WUDFHSRUW 6:2 75$&(6:2 7UDFHSRUW 73,8 75$&(&. 75$&('> @ 06Y 9 2936/3178 DocID029587 Rev 3 RM0433 60.3.2 Debug infrastructure Debug infrastructure pins and internal signals Table 553. JTAG/Serial-wire debug port pins JTAG debug port SW debug port Pin name Type Description JTMS/SWDIO I JTAG test mode select JTCK/SWCLK I JTAG test clock JTDI I JTDO nJTRST Type IO Pin assignment Description Serial wire data in/out PA13 I Serial wire clock PA14 JTAG test data input - - PA15 O JTAG test data output - - PB3 I JTAG test reset - - PB4 Table 554. Trace port pins Pin name Type Description TRACED0 O Trace synchronous data out 0 TRACED1 O Trace synchronous data out 1 TRACED2 O Trace synchronous data out 2 TRACED3 O Trace synchronous data out 3 TRACECK O Trace clock Pin assignment Refer to datasheet Table 555. Serial-wire trace port pins Pin name TRACESWO Type O Description Single wire trace asynchronous data out Pin assignment PB3(1) 1. TRACESWO is multiplexed with JTDO. This means that single wire trace is only available when using the serial wire debug interface, not when using JTAG Table 556. Trigger pins Pin name Type Description TRGIN I External trigger input TRGOUT O External trigger output TRGIO IO External trigger bi-directional(1) Pin assignment Refer to datasheet 1. TRGIO can be configured as an input or an output by the TRGOEN bit in the DBGMCU. If configured as an input, it is connected to TRGIN. If an output, it is connected to TRGOUT. This is because TRGIN and TRGOUT are not available on certain packages. DocID029587 Rev 3 2937/3178 3152 Debug infrastructure 60.3.3 RM0433 Debug infrastructure powering, clocking and reset Power domains Figure 809. Power domains of debug infrastructure 'GRPDLQ -7$* 6HULDOZLUHSRUW &RUH6LJKWFRPSRQHQW 'GRPDLQ -7066:',2 -7', 6:-'3 -7'2 '$3%86 520 ':7 WDEOH )3% $3%' V\VWHPGHEXJEXV ,70 '$3%86 5HSOLFDWRU -7&.6:&/. $+%$3 Q-7567 /HJHQG $7% WUDFHEXV $+%' 520 WDEOH &RUWH[0 FRUH $+%$3 $3%$3 &70 FURVVWULJJHUPDWUL[ (33% 6\VWHPEXV PDWUL[ &7, 7LPHVWDPS 6LJQDOV (70 $3%PX[ 6\V520 WDEOH '%*0&8 $3%' 76* &70 6\V520 WDEOH &67) 6:7) (7) 7ULJJHU 75*287 75*,2 6\V &7, 75*,1 65$0 6HULDOZLUH WUDFHSRUW 6:2 75$&(6:2 7UDFHSRUW 73,8 75$&(&. 75$&('> @ 06Y 9 The debug components are distributed across the power domains D1 and D3. The D3 power domain is considered to be always on when the debugger is connected. It therefore contains the SWJ-DP, so that the debugger does not lose the connection with the SoC when the other power domain is switched off. In addition, it contains the timestamp generator, the DBGMCU and the serial wire trace features. The D1 power domain contains the Cortex-M7 core and the associated debug and trace components. It also contains the system trace components located on the APB-D. This power domain therefore needs to be on whenever a debug access to the Cortex-M7 is required, or whenever a trace functionality is active on the processor. 2938/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Clock domains Figure 810. Clock domains of debug infrastructure '$3&/. 6:7&/. &.B'%*B' -7$* 6HULDOZLUHSRUW /HJHQG &RUH6LJKWFRPSRQHQW -7066:',2 &.B&25(B' -7', 6:-'3 -7'2 '$3%86 520 ':7 WDEOH )3% $3%' V\VWHPGHEXJEXV ,70 '$3%86 5HSOLFDWRU -7&.6:&/. $+%$3 Q-7567 $7% WUDFHEXV $+%' 520 WDEOH &RUWH[0 FRUH $+%$3 $3%$3 &70 FURVVWULJJHUPDWUL[ (33% 6\VWHPEXV PDWUL[ &.B+&/.B' &7, 7LPHVWDPS 6LJQDOV (70 $3%PX[ 6\V520 WDEOH '%*B0&8 $3%' &.B'%*B' 76* &70 6\V520 WDEOH &67) 6:7) (7) 7ULJJHU 75*287 75*,2 65$0 6HULDOZLUH WUDFHSRUW 6\V &7, 75*,1 6:2 75$&(&/. 73,8 75$&(6:2 7UDFHSRUW 75$&(&. 75$&('> @ 06Y 9 The debugger supplies the clock for the debug port, SWTCLK, via the debug interface pin, JTCK/SWCLK. This clock is used to register the serial input data in both serial wire and JTAG mode, as well as to operate the state machines and internal logic of the debug port. It must therefore continue to toggle for several cycles after the end of an access, to ensure that the debug port returns to the idle state. The SWJ-DP contains an asynchronous interface to the DAPCLK domain, which covers the rest of the SWJ-DP and the access ports. The DBGMCU, timestamp generator and System ROM table 1 are also in the DAPCLK domain. CK_DBG_D3 clocks the SWO and serial wire trace funnel. Both DAPCLK and CK_DBG_D3 are gated versions of the D3 domain system clock (CK_HCLK_D3). CK_DBG_D1 clocks the trace components in the D1 power domain: System ROM table 2, CoreSight trace funnel, ETF, system CTI and TPIU. It is a gated version of the D1 domain system clock (CK_HCLK_D1). TRACECLK is the trace port output clock. It is a gated version of the system clock (CK_SYS), except when the PLL1 is the source for the system clock. In this case, TRACECLK is derived directly from the PLL1 VCO output, divided by three. This is required in order to support the high data throughput on the trace port when the processor operates at its maximum frequency. All the debug clocks (except DAPCLK) can be enabled and disabled by register bits in the DBGMCU. The DAPCLK domain is enabled by the debugger using the CDBGPWRUPREQ DocID029587 Rev 3 2939/3178 3152 Debug infrastructure RM0433 bit in the debug port CTRL/STAT register. The clock must be enabled before the debugger can access any of the debug features on the device. It should be disabled at power up and when the debugger is disconnected, to avoid wasting energy. The debug and trace components included in the processor (ETM ITM, DWG, FPB etc) are clocked with the corresponding core clock (CK_CORE_D1). Debug with low-power modes The device includes power-saving features allowing individual power domains to be switched off or stopped when not required. If a power domain is switched off or not clocked, all debug components in that domain are inaccessible to the debugger. To avoid this, power saving mode emulation is implemented. If the emulation is enabled for a domain, the domain still enters power saving mode, but its clock and power are maintained. In other words, the domain behaves as if it is in power saving mode, while the debugger does not lose the connection. The emulation mode is programmed in the MCU Debug (DBGMCU) unit. For more information, refer to Section 60.5.8 Reset of debug infrastructure The debug components, except for the debug port and access ports, are reset by their respective power domain resets. The debug port (SWJ-DP) is reset by a power-on reset of the D3 domain only. 60.4 Debug access port functional description The debug access port (DAP) is a debug subsystem comprising serial-wire and JTAG debug port (SWJ-DP) and three access ports. 60.4.1 Serial-wire and JTAG debug port (SWJ-DP) The SWJ-DP is a CoreSight component that implements an external access port for connecting debugging equipment. The port can be configured as: • a 5-pin standard JTAG debug port (JTAG-DP) • a 2-pin (clock + data) “serial-wire” debug port (SW-DP) The two modes are mutually exclusive, since they share the same IO pins. By default, the JTAG-DP is selected upon a system or power-on reset. The five IOs are configured by hardware in debug alternative function mode. The SWJ-DP incorporates pullup resistors on the JTDI, JTMS/SWDIO, and nJTRST lines, as well as a pull-down resistor on the JTCK/SWCLK line. A debugger can select the SW-DP by transmitting the following serial data sequence on JTMS/SWDIO: ...,(50 or more ones),...,0,1,1,1,1,0,0,1,1,1,1,0,0,1,1,1,...,(50 or more ones),... JTCK/SWCLK must be cycled for each data bit. In SW-DP mode, the unused JTAG lines JTDI, JTDO and nJTRST can be used for other functions. 2940/3178 DocID029587 Rev 3 RM0433 Debug infrastructure All SWJ port IOs can be reconfigured to other functions by software, in which case debugging is no longer possible. Serial wire debug port The Serial wire debug protocol uses two pins: • SWCLK: clock from host to target • SWDIO: bi-directional serial data (100kΩ pull-up required) Serial data is transferred LSB first, synchronously with the clock. A transfer comprises three phases: 1. packet request (8 bits) transmitted by the host 2. acknowledge response (3 bits) transmitted by the target 3. data transfer (33 bits) transmitted by the host (in the case of a write) or target (in the case of a read) The data transfer only occurs if the acknowledge response is OK. Between each phase, if the direction of the data is reversed, a single clock cycle turnaround time is inserted. Table 557. Packet request Field bits Name 0 Start 1 APnDP 2 RnW 0: Write request 1: Read request 4:3 A(3:2) Address field of the DP or AP register (refer to Table 561 and Table 562) 5 Parity Single bit parity of preceding bits 6 Stop 0 7 Park Not driven by host. Must be read as “1” by target. Description Must be “1” 0: DP register access - see Table 561 for a list of DP registers 1: AP register access - see Section 60.4.2 Table 558. ACK response Field bits Name 2:0 ACK Description 000b: FAULT 010b: WAIT 100b: OK Table 559. Data transfer Bit field 31:0 32 Name Description WDATA or Write or Read data RDATA Parity Single bit parity of 32 data bits DocID029587 Rev 3 2941/3178 3152 Debug infrastructure RM0433 Figure 811 shows successful write and read transfers. Figure 811. SWD successful data transfer /HJHQG 6:',2 GULYHQE\KRVW 2YHU :'$7$>@ :'$7$>@ :'$7$> @ :'$7$>@ :'$7$>@ [ [ [ [ [ [ [ 6:',2 GULYHQE\WDUJHW 5'$7$>@ 5'$7$>@ 5'$7$>@ 5'$7$> @ 5'$7$>@ 5'$7$>@ 3DULW\ %LWYDOXHV ±YDOXHLV ±YDOXHLV [±YDOXHLVRU ±WUDQVIHURI6:',2OLQHSRVVHVVLRQ 3DULW\ $&.>@ [ 2YHU $&.>@ $&.>@ [ [ $&.>@ [ [ $&.>@ [ 3DUN 2YHU [ 6WRS [ $&.>@ [ 3DUN [ 2YHU [ 3DULW\ 6WRS 3DULW\ $>@ $>@ $>@ 5Q: $>@ [ 5Q: [ 6WDUW [ $3Q'3 5HDGWUDQVIHU 6WDUW 6:',2OLQH [ $3Q'3 :ULWHWUDQVIHU :'$7$>@ 6:&/.OLQH 06Y 9 In the case of a FAULT or WAIT ACK response from the target, the data transfer phase is cancelled, unless overrun detection is enabled, in which case the data will be ignored by the target (in the case of a write), or not driven (in the case of a read). A line reset must be generated by the host when it is first connected, or following a protocol error. The line reset consists of 50 or more SWCLK cycles with SWDIO high, followed by two SWCLK cycles with SWDIO low. For more details on the Serial Wire debug protocol, refer to the ARM® Debug Interface Architecture Specification [1]. Note: 2942/3178 The SWJ-DP implements SWD protocol version 2 DocID029587 Rev 3 RM0433 Debug infrastructure JTAG debug port Figure 812. JTAG TAP state machine -706 7HVW/RJLF 5HVHW -706 -706 5XQ7HVW ,GOH -706 -706 6HOHFW'5 6FDQ 6HOHFW,5 6FDQ -706 -706 -706 &DSWXUH '5 &DSWXUH,5 -706 -706 6KLIW'5 6KLIW,5 -706 -706 -706 -706 ([LW'5 ([LW,5 -706 -706 -706 3DXVH,5 -706 -706 -706 ([LW'5 -706 -706 ([LW,5 -706 8SGDWH'5 -706 -706 -706 3DXVH'5 -706 -706 -706 -706 8SGDWH,5 -706 -706 06Y 9 The JTAG-DP implements a TAP state machine (TAPSM) based on IEEE 1149.1-1990. The state machine is shown in Figure 812. It controls two scan chains, one associated with an instruction register (IR) and one with a number of data registers (DR). When the TAPSM goes through the Capture-IR state, 0b0001 is transferred onto the instruction register (IR) scan chain. The IR scan chain is connected between JTDI and JTDO. While the TAPSM is in the Shift-IR state, the IR scan chain shifts one bit for each rising edge of JTCK. This means that on the first tick: • The LSB of the IR scan chain is output on JTDO. • Bit [n] of the IR scan chain is transferred to bit [n-1]. • The value on JTDI is transferred to the MSB of the IR scan chain. When the TAPSM goes through the Update-IR state, the value scanned into the IR scan chain is transferred into the instruction register. When the TAPSM goes through the Capture-DR state, a value is transferred from one of the data registers onto one of the DR scan chains, connected between JTDI and JTDO. DocID029587 Rev 3 2943/3178 3152 Debug infrastructure RM0433 The value held in the instruction register determines which data register, and associated DR scan chain, is selected. This data is then shifted while the TAPSM is in the Shift-DR state, in the same manner as the IR shift in the Shift-IR state. When the TAPSM goes through the Update-DR state, the value scanned into the DR scan chain is transferred into the selected data register. When the TAPSM is in the Run-Test/Idle state, no special actions occur. The IDCODE instruction is loaded in IR. When active, the nJTRST signal resets the state machine asynchronously to the Test-LogicReset state. The data registers corresponding to the 4-bit IR instructions are listed in Table 560. Table 560. JTAG-DP data registers Instruction register Data register Scan chain length 0000 to 0111 (BYPASS) 1 Not implemented: BYPASS selected 1000 ABORT 35 Abort register – Bits 31:1 = reserved – Bit 0 = APABORT: write 1 to generate an AP abort 1001 (BYPASS) 1 Reserved: BYPASS selected 35 Debug port access register Initiates the debug port and allows access to a debug port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request Bits 2:1 = A[3:2] = 2-bit address of a debug port register. Bit 0 = RnW = Read request (1) or write request (0). – When transferring data OUT: Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read request Bits 2:0 = ACK[2:0] = 3-bit Acknowledge: 010b = OK/FAULT 001b = WAIT OTHER = reserved 1010 2944/3178 Description DPACC DocID029587 Rev 3 RM0433 Debug infrastructure Table 560. JTAG-DP data registers (continued) Instruction register Data register Scan chain length Description 1011 APACC 35 Access port access register Initiates an access port and allows access to an access port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request Bits 2:1 = A[3:2] = 2-bit sub-address of an access port register. Bit 0 = RnW= Read request (1) or write request (0). – When transferring data OUT: Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read request Bits 2:0 = ACK[2:0] = 3-bit Acknowledge: 010b = OK/FAULT 001b = WAIT OTHER = reserved 1100 (BYPASS) 1 Reserved: BYPASS selected 1101 (BYPASS) 1 Reserved: BYPASS selected 1110 IDCODE 32 ID Code 0x05BA 0477: ARM® JTAG debug port ID code 1111 BYPASS 1 Bypass A single JTCK cycle delay is inserted between JTDI and JTDO The DR registers are described in more detail in the ARM® Debug Interface Architecture Specification [1]. Debug port registers The SW-DP and JTAG-DP both access the debug port (DP) registers. These are listed in Table 561. The debugger can access the DP registers as follows: 1. Program the SELECT register DPBANKSEL field in the DP to select the register bank to be accessed (see Table 561) 2. Program the A(3:2) field in the DPACC register, if using JTAG, with the register address within the bank. Program the R/W bit to select a read or a write. In the case of a write, program the DATA field with the write data. If using SWD, the A(3:2) and R/W fields are part of the Packet Request word sent to the SW-DP with the APnDP bit reset (see Table 557). The write data is sent in the data phase. DocID029587 Rev 3 2945/3178 3152 Debug infrastructure RM0433 Table 561. Debug port registers A(3:2) field R/W value Address 0x0 00 Description R DP_DPIDR register. It contains the IDCODE for the debug port. W DP_ABORT register(1). It aborts the current AP transaction. This register is also used to clear the error flags in the DP_CTRL/STAT register. If DPBANKSEL[3:0] = 0x0 (DP_SELECT register): CTRL/STAT register. It controls the DP and provides status information. 0x4 01 R/W If DPBANKSEL[3:0] = 0x1 (DP_SELECT register): DP_DLCR register(2). It controls the operating mode of the SWD Data Link. If DPBANKSEL[3:0] = 0x2 (DP_SELECT register): DP_TARGETID register. It provides target identification information. If DPBANKSEL[3:0] = 0x3 (DP_SELECT register): DLPIDR register(2). It provides the SWD protocol version. 0x8 R RESEND register(2). It returns the value that was returned by the last AP read or DP_RDBUFF read, used in the event of a corrupted read transfer. W DP_SELECT register. It selects the access port, access port register bank, and DP register at address 0x4. R DP_RDBUFF register Via JTAG-DP, it is used to allow the debugger to get the final result after a sequence of operations (without requesting new JTAG-DP operation). Via SW-DP, it contains the result of the preceding AP read access, allowing a new AP access to be avoided. W DP_TARGETSEL register(2). On a write to DP_TARGETSEL immediately following a line reset sequence, the target is selected if the following conditions are both met: – Bits [31:28] match bits [31:28] in the DP_DLPIDR register. – Bits [27:0] match bits [27:0] in the DP_TARGETID register. Writing any other value deselects the target. Debug tools must write 0xFFFFFFFF to deselect all targets. This is an invalid DP_TARGETID value. All other invalid DP_TARGETID values are reserved. 10 0xC 11 1. Access to the AP ABORT register from the JTAG-DP is done using the ABORT instruction. 2. Only accessible via SW-DP. Register is “reserved” via JTAG-DP. Debug port identification register (DP_DPIDR) Address offset: 0x00 Reset value: 0x6BA0 2477 31 30 29 28 27 26 25 REVISION[3:0] 24 23 22 21 20 PARTNO[7:0] r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 VERSION[3:0] r r 2946/3178 r 19 18 17 16 Res. Res. Res. MIN 3 2 1 0 r DESIGNER[10:0] r r r r r r DocID029587 Rev 3 r Res. r r r r r RM0433 Debug infrastructure Bits 31:28 REVISION[3:0]: Revision code 0x6 Bits 27:20 PARTNO[7:0]: Part number for the debug port 0xBA Bits 19:17 Reserved, must be kept at reset value. Bit 16 MIN: Minimal debug port (MINDP) implementation 0: MINDP not implemented (transaction counter and pushed operations are supported) Bits 15:12 VERSION[3:0]: DP architecture version 0x2: DPv2 Bits 11:1 DESIGNER[10:0]: JEDEC designer identity code 0x23B: ARM® Bit 0 Reserved, must be kept at reset value. Debug port abort register (DP_ABORT) Address offset: 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ORUNERRCLR WDERRCLR STKERRCLR STKCMPCLR DAPABORT Reset value: 0x0000 0000 w w w w w Bits 31:5 Reserved, must be kept at reset value. Bit 4 ORUNERRCLR: Overrun error clear bit 0: No effect 1: Clear CTRL/STAT register’s STICKYORUN bit Bit 3 WDERRCLR: Write data error clear bit 0: No effect 1: Clear CTRL/STAT register’s WDATAERR bit DocID029587 Rev 3 2947/3178 3152 Debug infrastructure RM0433 Bit 2 STKERRCLR: Sticky error clear bit 0: No effect 1: Clear CTRL/STAT register’s STICKYERR bit Bit 1 STKCMPCLR: Sticky compare clear bit 0: No effect 1: Clear CTRL/STAT register’s STICKYCMP bit Bit 0 DAPABORT: Abort current AP transaction The transaction is aborted if an excessive number of WAIT responses are returned, indicating that the transaction has stalled. 0: No effect 1: Abort transaction Debug port control/status register (DP_CTRL/STAT) Address offset: 0x4 Reset value: 0x0000 0000 r rw 15 14 13 12 11 10 TRNCNT[3:0] rw rw rw 9 8 MASKLANE[3:0] rw rw rw rw rw 17 16 TRNCNT[11:4] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DAPABORT rw 18 STKCMPCLR r 19 STKERRCLR rw 20 WDERRCLR r 21 ORUNERRCLR Res. 22 STICKYERR Res. 23 READOK 24 WDATAERR 25 CDBGRSTREQ 26 CDBGRSTACK 27 CDBGPWRUPREQ 28 CDBGPWRUPACK 29 CSYSPWRUPREQ 30 CSYSPWRUPACK 31 r r rw w w w w w Bit 31 CSYSPWRUPACK: System domain power-up status bit - not used in this device Bit 30 CSYSPWRUPREQ: System domain power-up control bit - not used in this device Bit 29 CDBGPWRUPACK: Debug domain power-up status bit This bit is read-only. It returns the status of the debug domain power-up acknowledge signal from the power controller. 0: domain powered down 1: domain powered up Bit 28 CDBGPWRUPREQ. Debug domain power-up/down control bit This bit controls the debug domain power-up/down request signal to the power controller. 0: power-down requested 1: power-up requested Bit 27 CDBGRSTACK: Debug domain reset status bit - not used in this device 2948/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bit 26 CDBGRSTREQ: Debug domain reset control bit - not used in this device Bits 25:24 Reserved, must be kept at reset value. Bits 23:12 TRNCNT[11:0]: Transaction counter To program a sequence of transactions to incremental addresses via an AP, TRNCNT bits are loaded with the number of transactions to perform. It is decremented at the successful completion of each transaction. Bits 11:8 MASKLANE[3:0]: Pushed-compare and pushed-verify masking bits The field indicates the bytes to be masked in pushed-compare and pushed-verify operations (DP_CTRL/STAT register’s field TRNMODE = 1 or 2). In the pushed operations, the word supplied in an AP write transaction is compared with the current value at the target AP address. 0b1XXX: include byte lane 3 in comparisons 0bX1XX: include byte lane 2 in comparisons 0bXX1X: include byte lane 1 in comparisons 0bXXX1: include byte lane 0 in comparisons Bit 7 WDATAERR: Write data error in SW-DP The bit indicates that – there is a parity or a framing error on the data phase of a write operation, or – a write operation that had been accepted by the DP has then be discarded without being submitted to the AP This bit is read-only. It is reset by writing 1 to the WDERRCLR bit of the DP_ABORT register. 0: No error 1: Error has occurred This bit is reserved in JTAG-DP. Bit 6 READOK: AP read response in SW-DP This bit indicates the response to the last AP read access. It is read-only. 0: Read not OK 1: Read OK This bit is Reserved in JTAG-DP. Bit 5 STICKYERR: Transaction error (read-only in SW-DP, R/W in JTAG-DP) This bit indicates that an error occurred during an AP transaction. 0: No error 1: Error has occurred In the SW-DP, this bit is reset by writing 1 to the STKERRCLR bit of the DP_ABORT register. In the JTAG-DP, this bit is reset by programming it to 1. DocID029587 Rev 3 2949/3178 3152 Debug infrastructure RM0433 Bit 4 STICKYCMP. Compare match (read-only in SW-DP, R/W in JTAG-DP) This bit indicates that a match occurred in a pushed operation. 0: Match if TRNMODE = 0x1; no match if TRNMODE = 0x2 1: No match if TRNMODE = 0x1; match if TRNMODE = 0x2 In the SW-DP, this bit is reset by writing 1 to the STKCMPCLR bit in the DP_ABORT register. In the JTAG-DP, this bit is reset by programming it to it. Bits 3:2 TRNMODE: Transfer mode for AP write operations For read operations, this field must be set to 0x0. 0x0: Normal operation - AP transactions are passed directly to the AP. 0x1: Pushed-verify operation. The DP stores the write data and performs a read transaction at the target AP address. The result of the read operation is compared with the stored data. If they do not match, the STICKYCMP bit is set. 0x2: Pushed-compare operation. The DP stores the write data and performs a read transaction at the target AP address. The result of the read is compared with the stored data. If they match, the STICKYCMP bit is set. 0x3: Reserved In pushed operations, only the data bytes indicated by the MASKLANE field are included in the comparison. Bit 1 STICKYORUN. Overrun (read-only in SW-DP, R/W in JTAG-DP) This bit indicates that an overrun occurred (new transaction received before previous transaction completed). This bit is only set if the ORUNDETECT bit is set. 0: No overrun 1: Overrun occurred In the SW-DP, this bit is reset by writing 1 to the ABORT register’s ORUNERRCLR bit. In the JTAG-DP, this bit is reset by writing a 1 to it. Bit 0 ORUNDETECT. Overrun detection mode enable 0: Overrun detection disabled 1: Overrun detection enabled. In the event of an overrun, the STICKYORUN bit will be set and subsequent transactions will be blocked until the STICKYORUN bit is cleared. Debug port data link control register (DP_DLCR) Address offset: 0x4 Reset value: 0x0000 0040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TURNROUND [1:0] rw 2950/3178 rw DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:10 Reserved, must be kept at reset value. Bits 9:8 TURNROUND[1:0]: Tristate period for SWDIO 0x0: 1 data bit period 0x1: 2 data bit periods 0x2: 3 data bit periods 0x3: 4 data bit periods Bits 7:0 Reserved, must be kept at reset value. Debug port target identification register (DP_TARGETID) Address offset: 0x4 Reset value: 0x1045 0401 31 30 29 28 27 26 25 24 23 TREVISION[3:0] 22 21 20 19 18 17 16 TPARTNO[15:4] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPARTNO[3:0] r r r TDESIGNER[10:0] r r r r r r r r Res. r r r r Bits 31:28 TREVISION[3:0]: Target revision 0x1: revision 1 Bits 27:12 TPARTNO[15:0]: Target part number 0x0450: STM32H7 Bits 11:1 TDESIGNER[10:0]: Target designer JEDEC code 0x020: STMicroelectronics Bit 0 Reserved, must be kept at reset value. Debug port data link protocol identification register (DP_DLPIDR) Address offset: 0x4 Reset value: 0x0000 0001 31 30 29 28 TINSTANCE[3:0] 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 0 r r r r 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PROTSVN[3:0] r DocID029587 Rev 3 r r r 2951/3178 3152 Debug infrastructure RM0433 Bits 31:28 TINSTANCE[3:0]: Target instance number These bits define the instance number for this device in a multi-drop system. 0x0 Bits 27:4 Reserved, must be kept at reset value. Bits 3:0 PROTSVN[3:0]: Serial Wire Debug protocol version 0x1: Version 2 Debug port resend register (DP_RESEND) Address offset: 0x8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESEND[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RESEND[15:0] r r r r r r r r r Bits 31:0 RESEND: Last AP read or DP RDBUFF read value These bits contain the value that was returned by the last AP read or DP RDBUFF read. Used in the event of a corrupted read transfer. Debug port access port select register (DP_SELECT) Address offset: 0x8 Reset value: N/A 31 30 29 28 APSEL[3:0] 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 w w w w 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. APBANKSEL[3:0] w 2952/3178 w DocID029587 Rev 3 w DPBANKSEL[3:0] w w w w w RM0433 Debug infrastructure Bits 31:28 APSEL[3:0]: Access port select bits These bits select the access port for the next transaction. 0x0: AP0 - Cortex-M7 debug access port (AHB-AP) 0x1: AP1 - D3 access port (AHB-AP) 0x2: AP2 - System debug access port (APB-AP) 0x3 to 0xF: Reserved Bits 27:8 Reserved, must be kept at reset value. Bits 7:4 APBANKSEL[3:0]: AP register bank select bits These bits select the 4-word register bank on the active AP for the next transaction. Bits 3:0 DPBANKSEL[3:0]: DP register bank select bits These bits select the register at address 0x4 of the debug port. 0x0: CTRL/STAT register 0x1: DLCR register 0x2: TARGETID register 0x3: DLPIDR register 0x4 to 0xF: Reserved Debug port read buffer register (DP_RDBUFF) Address offset: 0xC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDBUFF[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDBUFF[15:0] r r r r r r r r r Bits 31:0 RDBUFF[31:0]: Last AP read value The field contains the value returned by the last AP read access. There are two ways to retrieve the value returned by an AP read access: – perform a second read access to the same address, which will initiate a new transaction on the corresponding bus, or – read the value returned by the last AP read access from the DP_RDBUFF register, in which case no new AP transaction occurs DocID029587 Rev 3 2953/3178 3152 Debug infrastructure RM0433 Debug port target identification register (DP_TARGETSEL) Address offset: 0xC Reset value: N/A 31 30 29 28 27 26 25 24 23 TINSTANCE[3:0] 22 21 20 19 18 17 16 TPARTNO[15:4] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPARTNO[3:0] w w w TDESIGNER[11:0] w w w w w w w w Res. w w w w Bits 31:28 TINSTANCE[3:0]: Target instance number The field defines the instance number for the target device in a multi-drop system. It must be programmed with the same value as TINSTANCE field of DP_DLPIDR register, in order to select this device. Bits 27:12 TPARTNO[15:0]: Target part number The field defines the part number for the target device. It must be programmed with the same value as TPARTNO field of DP_TARGETID register, in order to select this device. Bits 11:1 TDESIGNER[10:0]: Target designer JEDEC code The field defines the JEDEC code for the target device. It must be programmed with the same value as TDESIGNER field of DP_TARGETID register, in order to select this device. Bit 0 Reserved, must be kept at reset value. 60.4.2 Access ports Figure 813. Debug and access port connections -7$*6:' 6:-'3 '$3%86 $3 $+%$3 &RUWH[0 $+%'SRUW $3 $+%$3 '$+%LQWHUFRQQHFW $3 $3%$3 6\VWHP'HEXJ%XV $3%' 06Y 9 2954/3178 DocID029587 Rev 3 RM0433 Debug infrastructure There are the following access ports (AP) attached to the DP: 1. AP0: Cortex-M7 access port (AHB-AP). Allows access to the debug and trace features integrated in the Cortex-M7 processor core via an AHB-Lite bus connected to the AHBD port of the processor. 2. AP1: D3 access port (AHB-AP). Allows access to the bus matrix in the D3 domain. This gives visibility of the D3 domain memory and peripherals when the D1 and D2 domains are switched off. No CoreSight components are accessible via this port. 3. AP2: System access port (APB-AP). Allows access to the debug and trace features on the system APB debug bus, that is, all components not included in the processor core. All access ports are of MEM-AP type, that is, the debug and trace component registers are mapped in the address space of the associated debug bus. The AP is seen by the debugger as a set of 32-bit registers organized in banks of four registers each. Some of these registers are used to configure or monitor the AP itself, while others are used to perform a transfer on the bus. The AP registers are listed in Table 562. The address of the AP registers is composed of: • bits [7:4]: contents of the DP_SELECT register’s APBANKSEL field • bits [3:2]: contents of the A(3:2) field of the APACC data register in the JTAG-DP (see Table 560) or of the SW-DP Packet Request (see Table 557), depending on the debug interface used • bits [1:0]: Always set to 0 The contents of the SELECT register APSEL field in the DP define which MEM-AP is being accessed. The debugger can access the AP registers as follows: 1. Program the DP_SELECT register’s APSEL field to choose one of the APs, and the APBANKSEL field to select the register bank to be accessed. 2. Program the A(3:2) field in the APACC register, if using JTAG, with the register address within the bank. Program the RnW bit to select a read or a write. In the case of a write, program the DATA field with the write data. If using SWD, the A(3:2) and RnW fields are part of the Packet Request word sent to the SW-DP with the APnDP bit set (see Table 557). The write data is sent in the data phase. The debugger can access the memory mapped debug component registers through the MEM-AP registers (using the above AP register access procedure) as follows: 1. Program the transaction target address in the TAR register. 2. Program the CSW register, if necessary, with the transfer parameters (AddrInc for example). 3. Write to or read from the DRW register to initiate a bus transaction at the address held in the TAR register. Alternatively, a read or write to banked data register BDn triggers an access to address TAR[31:4] + n (this allows accessing up to four consecutive addresses without changing the address in the TAR register). For more detailed information on the MEM-AP, refer to the ARM® Debug Interface Architecture Specification [1]. The usage of MEM-AP to connect the debug port to the debug components (in the example, a processor, an ETM and a ROM table), is in the section 7.1.2. DocID029587 Rev 3 2955/3178 3152 Debug infrastructure RM0433 MEM-AP registers Table 562. MEM-AP registers Address APBANKSEL A(3:2) Name 0x00 0x0 0 AP_CSW Control/status word register 0x04 0x0 1 AP_TAR Transfer address register Target address for the bus transaction. 0x08 - - - 0x0C 0x0 3 AP_DRW Data read/write register Access to this register triggers a corresponding transaction on the debug bus to the address in TAR[31:0] 0x10 0x1 0 AP_BD0 Banked data 0 register Access to this register triggers a corresponding transaction on the debug bus to the address in TAR[31:4] << 4 + 0x0 0x14 0x1 1 AP_BD1 Banked Data 1 register Access to this register triggers a corresponding transaction on the debug bus to the address in TAR[31:4] << 4 + 0x4 0x18 0x1 2 AP_BD2 Banked data 2 register Access to this register triggers a corresponding transaction on the debug bus to the address in TAR[31:4] << 4 + 0x8 0x1C 0x1 3 AP_BD3 Banked data 3 register Access to this register triggers a corresponding transaction on the debug bus to the address in TAR[31:4] << 4 + 0xC 0x20-0xEC - - - Reserved 0xF0 - - - Reserved 0xF4 - - - Reserved 0xF8 0xF 2 AP_BASE 0xFC 0xF 3 AP_IDR 2956/3178 Description Reserved Debug base address register (RO) Base address of the ROM table Identification register (RO) DocID029587 Rev 3 RM0433 Debug infrastructure Access port control/status word register (AP_CSW) Address offset: 0x0 Reset value: 0x0000 0002 (APB-AP), 0x4000 0002 (AHB-AP) 31 30 29 Res. SPROT Res. rw rw rw rw rw rw rw r 15 14 13 12 11 10 9 8 Res. Res. Res. 28 27 26 25 24 PROT[4:0] Res. MODE[3:0] rw rw rw 23 22 21 20 19 18 17 16 SPI STATU S Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 TRIN PROG DEVIC EEN r r rw ADDRINC[1:0] rw rw Res. SIZE[2:0] rw rw rw Bit 31 Reserved, must be kept at reset value. Bit 30 SPROT: Secure transfer request bit In the APB-AP, this field is reserved. In the AHB-APs, this field sets the protection attribute HPROT[6] of the bus transfer. 0: If SPIDEN is high, secure transfer. If SPIDEN is low, non-secure transfer. 1: Non-secure transfer. Bit 29 Reserved, must be kept at reset value. Bits 28:24 PROT[4:0] Bus transfer protection bits In the APB-AP, this field is reserved. In the AHB-APs, this field sets the protection attributes HPROT[4:0] of the bus transfer. 0bXXXX0: Instruction fetch 0bXXXX1: Data access 0bXXX0X: User mode 0bXXX1X: Privileged mode 0bXX0XX: Non-bufferable 0bXX1XX: Bufferable 0bX0XXX: Non-cacheable 0bX1XXX: Cacheable 0b0XXXX: Non-exclusive 0b1XXXX: Exclusive Bit 23 SPISTATUS: Status of SPIDEN option bit This bit determines whether the debugger can access secure memory. This field is reserved in the APB-AP. 0: Secure AHB transfers are blocked 1: Secure AHB transfers are allowed Bits 22:12 Reserved, must be kept at reset value. Bits 11:8 MODE[3:0]: Barrier support enabled bit These bits define if memory barrier operation is supported. 0x0: Not supported Bit 7 TRINPROG: Transfer in progress This bit indicates that a bus transfer is in progress on the AP. 0: No transfer in progress. 1: Bus transfer in progress. DocID029587 Rev 3 2957/3178 3152 Debug infrastructure RM0433 Bit 6 DEVICEEN: Device Enable bit This bit defines whether the AP can be accessed or not. 1: AP access enabled. Bits 5:4 ADDRINC[1:0]: Auto-increment mode bits These bits define whether the TAR address is automatically incremented after a transaction. 0x0: no auto-increment 0x1: Address is incremented by the size in bytes of the transaction (SIZE field). 0x2: Packed transfers enabled (Only in AHB-APs - reserved in APB-AP). A 32-bit AP access will give rise to 1 x 32-bit, 2 x 16-bit or 4 x 8-bit bus transactions corresponding to the programmed transaction size. The data will be packed or unpacked accordingly. 0x3: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 SIZE[2:0]: Size of next memory access transaction (only for AHB-APs) 0x0: Byte (8-bit) 0x1: Half-word (16-bit) 0x2: Word (32-bit) 0x3-0x7: Reserved For APB-AP, this field is read-only and fixed at 0x2 (32-bit). Access port base address register (AP_BASE) Address offset: 0xF8 Reset value: 0xE00F E003 (AP0), 0x0000 0002 (AP1), 0xE00E 0003 (AP2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BASEADDR[19:4] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FOR MAT ENTRY PRESE NT r r BASEADDR[3:0] r r r r Bits 31:12 BASEADDR[19:0]: Base address (bits 31 to 12) of ROM table for the AP The 12 LSBs are zero since the ROM table must be aligned on a 4 Kbyte boundary. AP0 (Cortex-M7 AHB-AP): 0xE00FE AP1 (D3 AHB-AP): 0x00000 (No ROM table present) AP2 (System APB-AP): 0xE00E0 2958/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 11:2 Reserved, must be kept at reset value. Bit 1 FORMAT: Base address register format 1: ARM® debug interface v5. Bit 0 ENTRYPRESENT: Debug component present status bit This bit indicates that debug components are present on the access port bus. 0: Debug components are not present (AP1) 1: Debug components are present (AP0, AP2) Access port identification register (AP_IDR) Address offset: 0xFC Reset value: 0x6477 0001 (AP0 and AP1), 0x4477 0002 (AP2) 31 30 29 28 27 REVISION[3:0] 26 25 24 23 22 JEDECBANK[3:0] 21 20 19 18 17 16 MEM AP JEDECBANK[6:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. r r r IDENTITY[7:0] r r r r r Bits 31:28 REVISION[3:0]: ARM core revision 0x2: r0p3 0x4: r0p5 0x6: r0p7 Bits 27:24 JEDECBANK[3:0]: JEDEC bank 0x4: ARM® Bits 23:17 JEDECCODE[6:0]: JEDEC code 0x3B: ARM® Bit 16 MEMAP: Memory access port 1: Standard register map Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 IDENTITY[7:0]: AP type identification 0x01: AHB-AP (AP0 and AP1) 0x02: APB-AP (AP2) 0x11: Reserved DocID029587 Rev 3 2959/3178 3152 Debug infrastructure 60.5 RM0433 Trace and debug subsystem functional description The trace and debug subsystem features the following CoreSight components: • System ROM tables • Global timestamp generator (TSG) • System cross-trigger interface (CTI) • Cross-trigger matrix (CTM) • Trace port interface unit (TPIU) • Trace bus funnel (CSTF) • Embedded trace FIFO (ETF) • Serial wire output (SWO) • Serial wire output trace funnel (SWTF) These components are accessible by the debugger via the system APB-AP and its associated APB-D debug bus. They are also accessible by the Cortex-M7 processor. The MCU debug unit (DBGMCU) is also accessed via the APB-D. This non-CoreSight component contains registers for configuring the behavior of the device in debug mode. Trace bus replicator branches the trace bus from the CPU’s ITM CoreSight component to ETF and SWO, through trace bus funnels. 60.5.1 System ROM tables There are two ROM tables on the APB-D bus. The ROM table is a CoreSight component that contains the base addresses of all the CoreSight components on the APB-D bus. These tables allow a debugger to discover the topology of the CoreSight components automatically. The first table points to the second table, and to the CoreSight components located in D3 power domain: SWO, SWTF, TSG. The DBGMCU is not referenced by the table as it is not a standard CoreSight component. The table occupies a 4-Kbyte, 32-bit wide chunk of APB-D address space, from 0xE00E0000 to 0xE00E0FFC when accessed by the debugger, and from 0x59000000 to 0x59000FFC when accessed from the system bus. Table 563. System ROM table 1 Address offset in ROM table Component name Component base address (debugger) Component base address (system bus) Component address offset Size Entry 0x000 System ROM table 2 0xE00F0000 0x59010000 0x10000 4 Kbyte 0x00010003 0x004 SWO 0xE00E2000 0x59002000 0x02000 4 Kbyte 0x00002003 0x008 Timestamp generator 0xE00E3000 0x59003000 0x03000 4 Kbyte 0x00003003 0x00C SWO funnel 0xE00E4000 0x59004000 0x04000 4 Kbyte 0x00004003 0x010 Top of table - - - - 0x00000000 0x014 to 0xFC8 Reserved - - - - 0x00000000 0xFCC to 0xFFC ROM table registers - - - - See System ROM registers 2960/3178 DocID029587 Rev 3 RM0433 Debug infrastructure The second table occupies a 4-Kbyte, 32-bit wide chunk of APB-D address space, from 0xE00F0000 to 0xE00F0FFC when accessed by the debugger, and from 0x59010000 to 0x59010FFC when accessed from the system bus. Table 564. System ROM table 2 Address offset in ROM table Component name Component base address (debugger) Component base address (system bus) Component address offset Size Entry 0x000 System CTI 0xE00F1000 0x59011000 0x1000 4 Kbyte 0x00001003 0x004 Trace funnel 0xE00F3000 0x59013000 0x3000 4 Kbyte 0x00003003 0x008 ETF 0xE00F4000 0x59014000 0x4000 4 Kbyte 0x00004003 0x00C TPIU 0xE00F5000 0x59015000 0x5000 4 Kbyte 0x00005003 0x010 Top of table - - - - 0x00000000 0x014 to 0xFC8 Reserved - - - - 0x00000000 0xFCC to 0xFFC ROM table registers - - - - See System ROM registers The top of each ROM table contains a number of read-only registers, including the standard CoreSight component and peripheral identity registers, see section System ROM registers. Each debug component occupies one or more 4 Kbyte blocks of address space. This block of address space is referred to as the debug register file for the component. The component address offset field of a ROM Table entry points to the start of the last 4 Kbyte block of the address space of the component. This block always contains the component and peripheral ID registers for the component, starting at offset 0xFD0 from the start of the block. The 4 Kbyte count field PIDR4 [7:4], specifies the number of 4 Kbyte blocks for the component. Therefore, the process for finding the start of the address space for a component is: 1. Read the ROM-table entry for the component and extract its Address_Offset[18:0] from bits [31:12] of the ROM-table entry. 2. Use the address offset, together with the base address of the ROM table, ROM_Base_Address, to calculate the base address of the component: Component_Base_Address = ROM_Base_Address + Address_Offset The Component_Base_Address is the start address of the 4 Kbyte block of the address space for the component. 3. Read the peripheral ID4 register for the component. The address of this register is: Peripheral_ID4_address = Component_Base_Address + 0xFD0 4. Extract the 4 Kbyte count field [7:4] from the value of the Peripheral ID4 Register. 5. Use the 4 Kbyte count field value to calculate the start address of the address space for the component. If the field value is 0b0000, which corresponds to a count value of 1, the address space for the component starts at Component_Base_Address obtained at stage 2. The topology for the CoreSight components on the APB-D is shown in Figure 814. DocID029587 Rev 3 2961/3178 3152 Debug infrastructure RM0433 Figure 814. APB-D CoreSight component topology $3%$3 [(( %$6(UHJLVWHU [) 6\VWHP520WDEOH #[(( [ 2IIVHW [ 6\VWHP520WDEOH #[() [ 2IIVHW [ [ 2IIVHW [ [ 2IIVHW [ [ 2IIVHW [ [ 2IIVHW [ [& 2IIVHW [ [& 2IIVHW [ [ 7RSRIWDEOH [ 7RSRIWDEOH [)' 3,'5 [)' 3,'5 [))& &,'5 [))& &,'5 3,'5 [))& &,'5 3,'5 [))& &,'5 6:2WUDFHIXQQHO 6:7) #[(( [ 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 3,'5 [))& &,'5 [)' 3,'5 [))& &,'5 7UDFHSRUWLQWHUIDFH 73,8 #[() [ 5HJLVWHUILOHEDVH 7LPHVWDPSJHQHUDWRU #[(( [ 5HJLVWHUILOHEDVH [)' [)' 7UDFHIXQQHO &67) #[() [ 5HJLVWHUILOHEDVH 6HULDOZLUHRXWSXW 6:2 #[(( [ 5HJLVWHUILOHEDVH [)' [ 6\VWHP&7, #[() 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 [ 7UDFH),)2 (7) #[() 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 06Y 9 For more information on the use of the ROM table, refer to the ARM® Debug Interface Architecture Specification [1]. System ROM registers SYSROM memory type register (SYSROM_MEMTYPE) Address offset: 0xFCC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SYS MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r 2962/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:1 Reserved, must be kept at reset value. Bit 0 SYSMEM: System memory 0: No system memory is present on this bus SYSROM CoreSight peripheral identity register 4 (SYSROM_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x0: STMicroelectronics JEDEC continuation code SYSROM CoreSight peripheral identity register 0 (SYSROM_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Device part number field, bits [7:0] 0x50: STM32H7 device DocID029587 Rev 3 2963/3178 3152 Debug infrastructure RM0433 SYSROM CoreSight peripheral identity register 1 (SYSROM_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0x0: STMicroelectronics JEDEC code Bits 3:0 PARTNUM[11:8]: Device part number field, bits [11:8] 0x4: STM32H7 device SYSROM CoreSight peripheral identity register 2 (SYSROM_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Device revision number 0x1: Rev 1 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x2: STMicroelectronics JEDEC code 2964/3178 DocID029587 Rev 3 RM0433 Debug infrastructure SYSROM CoreSight peripheral identity register 3 (SYSROM_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications SYSROM CoreSight component identity register 0 (SYSROM_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value SYSROM CoreSight component identity register 1 (SYSROM_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r DocID029587 Rev 3 2965/3178 3152 Debug infrastructure RM0433 Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x1: ROM table component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value SYSROM CoreSight component identity register 2 (SYSROM_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value SYSROM CoreSight component identity register 3 (SYSROM_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE: Component ID field, bits [31:24] 0xB1: Common ID value 2966/3178 DocID029587 Rev 3 0xFFC SYSROM_CIDR3 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSROM_CIDR2 Res. 0xFF8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSROM_CIDR1 Res. 0xFF4 Reset value 0 Reset value 0 Reset value 0 Reset value 0 Reset value 0 Reset value 0 Reset value 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 JEP106ID [6:4] 0 0 0 PARTNUM [11:8] 0 0 0 CMOD [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value JEP106ID [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value REVISION [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value REVAND [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PREAMBLE [11:8] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CLASS [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSROM_CIDR0 Res. 0xFF0 SYSROM_PIDR3 Res. 0xFEC SYSROM_PIDR2 Res. 0xFE8 SYSROM_PIDR1 Res. 0xFE4 SYSROM_PIDR0 Res. 0xFE0 SYSROM_PIDR7 Res. 0xFDC SYSROM_PIDR6 Res. 0xFD8 SYSROM_PIDR5 Res. 0xFD4 JEP106CON[3;0 4KCOUNT[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSROM_PIDR4 Res. 0xFD0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 SYSMEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSROM_ MEMTYPE Res. 0xFCC Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure System ROM register map and reset values Table 565. System ROM table register map and reset values Reset value 0 Reserved Reserved Reserved PARTNUM[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE[7:0] 0 0 0 1 0 PREAMBLE[19:12] PREAMBLE[27:20] 1 1 2967/3178 3152 Debug infrastructure 60.5.2 RM0433 Global timestamp generator (TSG) The global timestamp generator contains a 64-bit counter that provides a common timing reference for all of the trace sources in the system, namely the ETM and ITM in the processor core. These components insert timestamps in the trace streams that allow the trace analyzer to recover the chronological order of trace packets, which can be lost when multiple trace sources are multiplexed into one stream at the funnels. The TSG registers are accessible over the APB-D. This allows the debugger or debug software to: • start and stop the timestamp incrementing • read the current timestamp value • change the current timestamp value – • The timestamp counter must be halted while it is changed. When the timestamp value is changed, the timestamp generator resynchronizes all the trace sources. change the reported timestamp increment For more information on the global timestamp generator CoreSight component, refer to the ARM® CoreSight™ SoC-400 Technical Reference Manual [2]. The timestamp generator is located in the D3 power domain, and the timestamp is distributed to the Cortex-M7. To simplify the distribution over power domain boundaries, the 64-bit timestamp is encoded in seven bits, then decoded in the destination power domain, and interpolated to increase its resolution if the processor clock is significantly faster than the generator clock. The timestamp distribution is shown in Figure 815. Figure 815. Global timestamp distribution 'HEXJ$3% 7LPHVWDPSJHQHUDWRU &RXQWHU> @ &RUWH[0 7LPHVWDPS (QFRGHU 7LPHVWDPS 'HFRGHU 7LPHVWDPS ,QWHUSRODWRU (70 ,70 3RZHUGRPDLQ' ORZIUHTXHQF\FORFN 3RZHUGRPDLQ' &RUWH[0FORFN 06Y 9 2968/3178 DocID029587 Rev 3 RM0433 Debug infrastructure TSG registers TSG counter control register (TSG_CNTCR) Address offset: 0x000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HDBG EN rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 HDBG: Halt on debug 0: Normal operation 1: Halt counter when system-wide debug state is detected - not implemented Bit 0 EN: Enable 0: Counter disabled 1: Counter enabled and incrementing TSG counter status register (TSG_CNTSR) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBGH Res. r Bits 31:2 Reserved, must be kept at reset value. Bit 1 DBGH: Debug halt 0: Normal operation 1: Counter halted due to system-wide debug state Bit 0 Reserved, must be kept at reset value. DocID029587 Rev 3 2969/3178 3152 Debug infrastructure RM0433 TSG current counter value lower register (TSG_CNTCVL) Address offset: 0x008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CNTCVL[31:16] rw 15 14 13 12 11 10 9 8 7 CNTCVL[15:0] rw Bits 31:0 CNTCVL[31:0]: TSG current counter value field, bits[31:0] To change the current timestamp value, write the lower 32 bits of the new value to this register before writing the upper 32 bits to CNTCVU. The timestamp value is not changed until the CNTVCVU register is written to. Note: The TSG_CNTCR register’s EN bit must be cleared before writing to this register. TSG current counter value upper register (TSG_CNTCVU) Address offset: 0x00C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CNTCVU[31:16] rw 15 14 13 12 11 10 9 8 7 CNTCVU[15:0] rw Bits 31:0 CNTCVU[31:0]: TSG current counter value field, bits[63:32] To change the current timestamp value, write the lower 32 bits of the new value to CNTCVL before writing the upper 32 bits to this register. The 64-bit timestamp value is updated with the value from both writes when this register is written to. Note: The TSG_CNTCR register’s EN bit must be cleared before writing to this register. TSG base frequency ID register (TSG_CNTFID0) Address offset: 0x020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 FREQ[31:16] rw 15 14 13 12 11 10 9 8 7 FREQ[15:0] rw 2970/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:0 FREQ: Increment frequency of TSG counter in Hz This field must be programmed with the trace generator clock frequency whenever it changes. TSG CoreSight peripheral identity register 4 (TSG_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code Table 566. TSG CoreSight Peripheral identity register 0 (TSG_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x01: TSG part number DocID029587 Rev 3 2971/3178 3152 Debug infrastructure RM0433 TSG CoreSight peripheral identity register 1 (TSG_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x1: TSG part number TSG CoreSight peripheral identity register 2 (TSG_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 001B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x1: r0p1 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code 2972/3178 DocID029587 Rev 3 RM0433 Debug infrastructure TSG CoreSight peripheral identity register 3 (TSG_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications TSG CoreSight component identity register 0 (TSG_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value TSG CoreSight component identity register 1 (TSG_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r DocID029587 Rev 3 2973/3178 3152 Debug infrastructure RM0433 Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0xF: CoreSight Soc-400 component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value TSG CoreSight component identity register 2 (TSG_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value TSG CoreSight component identity register 3 (TSG_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value 2974/3178 DocID029587 Rev 3 0xFFC TSG_CIDR3 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 Reset value 1 Reset value 0 Reset value 0 Reset value 0 Reset value 1 Reset value 0 1 1 0 0 0 0 0 0 0 Res. Res. 1 Res. PARTNUM[7:0] Res. 0 0 0 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID [3:0] 0 1 1 0 0 1 REVISION [3:0] 1 0 CLASS [3:0] 0 1 0 1 0 0 1 REVAND [3:0] 1 0 1 0 0 0 1 0 1 0 HDBG EN 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 DBGH Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value 1 0 0 0 0 0 0 1 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value 4KCOUNT Res. TSG_PIDR4 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. TSG_CNTFID0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. TSG_CNTCVU Res. Res. Res. Res. Res. Res. 0 Res. TSG_CNTCVL Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 0 Res. TSG_CIDR2 0 0 Res. 0xFF8 TSG_CIDR1 0 Res. 0xFF4 TSG_CIDR0 0 Res. 0xFF0 TSG_PIDR3 Res. 0xFEC TSG_PIDR2 0 0 Res. 0xFE8 TSG_PIDR1 0 Res. 0xFE4 TSG_PIDR0 Res. 0xFE0 TSG_PIDR7 Res. 0xFDC TSG_PIDR6 Res. 0xFD8 Res. 0xFD4 TSG_PIDR5 0 Res. 0xFD0 Res. 0x020 Reset value 0 Res. 0x00C Reset value Res. 0x008 TSG_CNTSR Res. 0x004 TSG_CNTCR Res. 0x000 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure TSG register map and reset values Table 567. TSG register map and reset values CNTCVL_L_32 0 CNTCVU_U_32 FREQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106CON 0 Reset value PARTNUM [11:8] 1 JEP106ID [6:4] CMOD [3:0] 1 PREAMBLE[7:0] 0 0 PREAMBLE [11:8] 0 1 0 PREAMBLE[19:12] PREAMBLE[27:20] 1 1 2975/3178 3152 Debug infrastructure 60.5.3 RM0433 Cross trigger interfaces (CTI) and matrix (CTM) The cross trigger interfaces (CTI) and cross trigger matrix (CTM) together form the CoreSight embedded cross trigger feature. There are two CTI components, one at system level and one dedicated to the Cortex-M7. The two CTIs are connected to each other via the CTM. The system-level CTI is accessible to the debugger via the system access port and associated APB-D. The Cortex-M7 CTI is physically integrated in the Cortex-M7 core, and is accessible via the Cortex-M7 access port and associated AHBD. Figure 816. Embedded cross trigger 6\VWHP&7, $3%' 75*,1 75*287 (7))8// (7)$&4&203 (7) (7)75,* (7))/86+ 73,875,* 73,8 73,8)/86+ 75,*,1 75,*287 75,*,1 75,*,1 75,*287 75,*287 75,*287 75,*287 &70FKDQQHOV> @ $+%' +$/7(' &2030$7&+ &2030$7&+ &RUWH[0 &38 &2030$7&+ ('%*54 '%*5(67$57 Q,54 Q,54 (70(;7287 (70(;7287 (70 (70(9(176 (70(9(176 &RUWH[0&7, 75,*,1 75,*,1 75,*,1 75,*,1 75,*287 75,*287 75,*287 75,*287 75,*,1 75,*,1 75,*287 75,*287 06Y 9 The CTIs allow events from various sources to trigger debug and/or trace activity. For example, a transition detected on an external trigger input can start code trace. Each CTI has up to 8 trigger inputs and 8 trigger outputs. Any input can be connected to any output, on the same CTI, or on another CTI via the CTM. The trigger input and output signals for each CTI are listed in Table 568 to Table 571. 2976/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Table 568. System CTI inputs # Source signal Source component Comments 0 DBTRIGI GPIO 1 ETFACQCOMP ETF ETF capture finished - allows a debug event to be generated when the trace FIFO is empty 2 ETFFULL ETF ETF full flag - allows a debug event to be generated when the trace FIFO is full 3 - - Not used 4 - - Not used 5 - - Not used 6 - - Not used 7 - - Not used External trigger input - allows an external signal to generate a debug event Table 569. System CTI outputs # Output signal Destination component Comments 0 DBTRIGO GPIO External IO trigger output - allows monitoring of events on the external DBTRIGO pin 1 TPIUFLUSH TPIU Trace port flush trigger - causes the TPIU FIFO to be flushed 2 TPIUTRIG TPIU Trace Port enable trigger - starts trace output on the external trace port 3 ETFTRIG ETF ETF enable trigger - starts filling the Trace FIFO 4 ETFFLUSH ETF ETF flush trigger - causes the Trace FIFO to be flushed 5 - - Not used 6 - - Not used 7 - - Not used Table 570. Cortex-M7 CTI inputs # Source signal Source component 0 HALTED Cortex-M7 CPU CPU halted - indicates CPU is in debug mode 1 COMPMATCH0 Cortex-M7 DWT DWT comparator 0 match 2 COMPMATCH1 Cortex-M7 DWT DWT comparator 1 match 3 COMPMATCH2 Cortex-M7 DWT DWT comparator 2 match 4 ETMEXTOUT0 Cortex-M7 ETM ETM external trigger out 5 ETMEXTOUT1 Cortex-M7 ETM ETM external trigger out DocID029587 Rev 3 Comments 2977/3178 3152 Debug infrastructure RM0433 Table 570. Cortex-M7 CTI inputs (continued) # Source signal Source component Comments 6 - - Not used 7 - - Not used Table 571. Cortex-M7 CTI outputs # Output signal Destination component Comments 0 EDBGRQ Cortex-M7 CPU CPU halt request - puts CPU in debug mode 1 nIRQ1 Cortex-M7 NVIC Interrupt request 2 nIRQ2 Cortex-M7 NVIC Interrupt request 3 - - 4 ETMEVENTS0 Cortex-M7 ETM ETM trig request - enables CPU execution trace 5 ETMEVENTS1 Cortex-M7 ETM ETM trig request - enables CPU execution trace 6 - - 7 DBGRESTART Cortex-M7 CPU Not used Not used CPU restart request - CPU exits debug mode There are four event channels in the cross trigger matrix, which allows up to four parallel bidirectional connections between trigger inputs and outputs on different CTIs. To connect input number m on CTI x to output number n on CTI y, the input must be connected to an event channel p using the CTIINENm register of CTI x. The same channel p must be connected to the output using the CTIOUTENn register of CTI y. Note: this applies even if the input and output belong to the same CTI. An input can be connected to more than one channel (up to four), so an input can be routed to several outputs. Similarly, an output can be connected to several inputs. It is also possible to connect several inputs/outputs to the same channel. Figure 817. Mapping of trigger inputs to outputs &7,,1(1P S ,QSXWP &7,287(1Q S &KDQQHOS 2XWSXWQ &KDQQHOT &KDQQHOU &KDQQHOV &7,[ &70 &7,\ 06Y 9 2978/3178 DocID029587 Rev 3 RM0433 Debug infrastructure For more information on the cross-trigger interface CoreSight component, refer to the ARM® CoreSight™ SoC-400 Technical Reference Manual [2]. CTI registers The register file base address for each CTI is defined by the ROM table for the bus to which it is connected. The registers are the same for each CTI. CTI control register (CTI_CONTROL) Address offset: 0x000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GLBEN rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 GLBEN: Global enable. 0: Cross-triggering disabled 1: Cross-triggering enabled CTI trigger acknowledge register (CTI_INTACK) Address offset: 0x010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. INTACK[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bit 7:0 INTACK[7:0]: Trigger acknowledge There is one bit of the register for each CTITRIGOUT output. When a 1 is written to a bit in this register, the corresponding CTITRIGOUT output is acknowledged, causing it to be cleared. DocID029587 Rev 3 2979/3178 3152 Debug infrastructure RM0433 CTI application trigger set register (CTI_APPSET) Address offset: 0x014 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. APPSET[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 APPSET[3:0]: Set channel event Read: 0bXXX0: Channel 0 event inactive 0bXXX0: Channel 0 event active 0bXX0X: Channel 1 event inactive 0bXX1X: Channel 1 event active 0bX0XX: Channel 2 event inactive 0bX1XX: Channel 2 event active 0b0XXX: Channel 3 event inactive 0b1XXX: Channel 3 event active Write: 0bXXX0: No effect 0bXXX0: Set event on Channel 0 0bXX0X: No effect 0bXX1X: Set event on Channel 1 0bX0XX: No effect 0bX1XX: Set event on Channel 2 0b0XXX: No effect 0b1XXX: Set event on Channel 3 CTI application trigger clear register (CTI_APPCLEAR) Address offset: 0x018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. APPCLEAR[3:0] w 2980/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 APPCLEAR[3:0]: Clear channel event 0bXXX0: No effect 0bXXX0: Clear event on Channel 0 0bXX0X: No effect 0bXX1X: Clear event on Channel 1 0bX0XX: No effect 0bX1XX: Clear event on Channel 2 0b0XXX: No effect 0b1XXX: Clear event on Channel 3 CTI application pulse register (CTI_APPPULSE) Address offset: 0x01C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. APPPULSE[3:0] w Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 APPULSE: Pulse channel event This register clears itself immediately. 0bXXX0: No effect 0bXXX0: Generate pulse on Channel 0 0bXX0X: No effect 0bXX1X: Generate pulse on Channel 1 0bX0XX: No effect 0bX1XX: Generate pulse on Channel 2 0b0XXX: No effect 0b1XXX: Generate pulse on Channel 3 CTI trigger IN x enable register (CTI_INENx) Address offset: 0x020 + 4 * x, where x = 0 to 7 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIGINEN[3:0] rw DocID029587 Rev 3 2981/3178 3152 Debug infrastructure RM0433 Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 TRIGINEN[3:0]: Cross-trigger event enable Enables or disables a cross-trigger event on each of the four channels when CTITRIGINx is activated (x = 0 to 7). 0bXXX0: Trigger n does not generate events on Channel 0 0bXXX0: Trigger n generates events on Channel 0 0bXX0X: Trigger n does not generate events on Channel 1 0bXX1X: Trigger n generates events on Channel 1 0bX0XX: Trigger n does not generate events on Channel 2 0bX1XX: Trigger n generates events on Channel 2 0b0XXX: Trigger n does not generate events on Channel 3 0b1XXX: Trigger n generates events on Channel 3 CTI trigger OUT x enable register (CTI_OUTENx) Address offset: 0x0A0 + 4 * x, where x = 0 to 7 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. TRIGOUTEN[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 TRIGOUTEN[3:0]: Enable trigger upon event For each channel, the field defines whether an event on that channel will generate a trigger on CTITRIGOUTx (x = 0 to 7). 0bXXX0: Channel 0 events do not generate triggers on Trigger output n 0bXXX0: Channel 0 events generate triggers on Trigger output n 0bXX0X: Channel 1 events do not generate triggers on Trigger output n 0bXX1X: Channel 1 events generate triggers on Trigger output n 0bX0XX: Channel 2 events do not generate triggers on Trigger output n 0bX1XX: Channel 2 events generate triggers on Trigger output n 0b0XXX: Channel 3 events do not generate triggers on Trigger output n 0b1XXX: Channel 3 events generate triggers on Trigger output n 2982/3178 DocID029587 Rev 3 RM0433 Debug infrastructure CTI trigger IN status register (CTI_TRGISTS) Address offset: 0x130 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. TRIGINSTATUS[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bit 7:0 TRIGINSTATUS[7:0]: Trigger input status There is one bit of the register for each CTITRIGIN input. When a bit is set to 1 it indicates that the corresponding trigger input is active. When it is set to 0, the corresponding trigger input is inactive. CTI trigger OUT status register (CTI_TRGOSTS) Address offset: 0x134 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. TRIGOUTSTATUS[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bit 7:0 TRIGOUTSTATUS[7:0]: Trigger output status There is one bit of the register for each CTITRIGOUT output. When a bit is set to 1 it indicates that the corresponding trigger output is active. When it is set to 0, the corresponding trigger output is inactive. DocID029587 Rev 3 2983/3178 3152 Debug infrastructure RM0433 CTI channel IN status register (CTI_CHINSTS) Address offset: 0x138 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHINSTATUS[3:0] r Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 CHINSTATUS[3:0]: Channel input status There is one bit of the register for each channel input. When a bit is set to 1 it indicates that the corresponding channel input is active. When it is set to 0, the corresponding channel input is inactive. CTI channel OUT status register (CTI_CHOUTSTS) Address offset: 0x13C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHOUTSTATUS[3:0] r Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 CHOUTSTATUS[3:0]: Channel output status There is one bit of the register for each channel output. When a bit is set to 1 it indicates that the corresponding channel output is active. When it is set to 0, the corresponding channel output is inactive. 2984/3178 DocID029587 Rev 3 RM0433 Debug infrastructure CTI channel gate register (CTI_GATE) Address offset: 0x140 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GATEEN[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bit 3:0 GATEEN[3:0]: Channel output enable For each channel, defines whether an event on that channel can propagate over the CTM to other CTIs. 0bXXX0: Channel 0 events do not propagate 0bXXX0: Channel 0 events propagate 0bXX0X: Channel 1 events do not propagate 0bXX1X: Channel 1 events propagate 0bX0XX: Channel 2 events do not propagate 0bX1XX: Channel 2 events propagate 0b0XXX: Channel 3 events do not propagate 0b1XXX: Channel 3 events propagate CTI claim tag set register (CTI_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw DocID029587 Rev 3 2985/3178 3152 Debug infrastructure RM0433 Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag CTI claim tag clear register (CTI_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag CTI lock access register (CTI_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:16] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w 2986/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:0 ACCESS_W[31:0]: CTI register write access enable Enables write access to some CTI registers by processor core (debuggers do not need to unlock the component) 0xC5ACCE55: Enable write access Other values: Disable write access CTI lock status register (CTI_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the CTI_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked. Only read access is permitted. Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented CTI authentication status register (CTI_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r DocID029587 Rev 3 2987/3178 3152 Debug infrastructure RM0433 Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x2: Disabled 0x3: Enabled Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x2: Disabled 0x3: Enabled CTI device configuration register (CTI_DEVID) Address offset: 0xFC8 Reset value: 0x0004 0800 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. 19 18 17 16 NUMCH[3:0] r NUMTRIG[7:0] 3 2 1 0 EXTMUXNUM[4:0] r r Bits 31:20 Reserved, must be kept at reset value. Bits 19:16 NUMCH[3:0]: Number of ECT channels available 0x4: 4 channels Bits 15:8 NUMTRIG[7:0]: Number of ECT triggers available 0x8: 8 trigger inputs and 8 trigger outputs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 EXTMUXNUM[4:0]: Number of trigger input/output multiplexers 0x0: None CTI device type identifier register (CTI_DEVTYPE) Address offset: 0xFCC Reset value: 0x0000 0014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 2988/3178 SUBTYPE[3:0] MAJORTYPE[3:0] r r DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SUBTYPE[3:0]: Sub-classification 0x1: Indicates that this component is a cross-triggering component. Bits 3:0 MAJORTYPE[3:0]: Major classification 0x4: Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. CTI CoreSight peripheral identity register 4 (CTI_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code CTI CoreSight peripheral identity register 0 (CTI_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0006 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x06: CTI part number DocID029587 Rev 3 2989/3178 3152 Debug infrastructure RM0433 CTI CoreSight peripheral identity register 1 (CTI_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: CTI part number CTI CoreSight peripheral identity register 2 (CTI_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 004B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x4: r0p5 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code 2990/3178 DocID029587 Rev 3 RM0433 Debug infrastructure CTI CoreSight peripheral identity register 3 (CTI_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications CTI CoreSight component identity register 0 (CTI_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value CTI CoreSight component identity register 1 (CTI_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r DocID029587 Rev 3 2991/3178 3152 Debug infrastructure RM0433 Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: CoreSight component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value CTI CoreSight component identity register 2 (CTI_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value CTI CoreSight component identity register 3 (CTI_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value 2992/3178 DocID029587 Rev 3 0x0S8 CTI_OUTEN2 Reset value DocID029587 Rev 3 Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TRIGOUTEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN7 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN6 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CTI_INEN5 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN4 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN3 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN2 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN1 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CTI_INEN0 TRIGINEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_OUTEN1 Res. 0x0S4 CTI_OUTEN0 Res. 0x0A0 Res. 0x03C Res. 0x038 Res. 0x034 Reset value Res. 0x030 Res. 0x02C Res. 0x028 Res. 0x024 Res. 0x020 CTI_APPPULSE Res. 0x01C CTI_APPCLEAR Res. 0x018 CTI_APPSET Res. 0x014 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_INTACK Res. 0x010 Reset value Reset value Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIGOUTEN [3:0] 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLBEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_CONTROL Res. 0x000 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure CTI register map and reset values Table 572. CTI register map and reset values 0 INTACK[7:0] 0 APPSET[3:0] 0 APPCLEAR [3:0] APPPULSE [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 TRIGOUTEN [3:0] 0 2993/3178 3152 0xFCC CTI_DEVTYPE 2994/3178 0 1 0 0 0 0 0 0 1 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. CTI_DEVID Res. 0xFC8 Res. Res. Res. Res. Res. Res. Res. Res. Reset value DocID029587 Rev 3 NUMCH[3:0] NUMTRIG[7:0] 0 SID [1:0] 0 0 0 0 0 0 0 0 0 Reset value Reset value Reset value Reset value Reset value Reset value KEY Reset value 0 0 SUB[3:0] 1 0 0 0 0 SLI Res. Reset value SLK Res. Res. Res. Res. Reset value NTT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TRIGOUTEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value NSID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TRIGOUTEN [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value NSNID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value SNID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_LAR Res. CTI_AUTHSTAT Res. CTI_LSR Res. 0xFB4 Res. 0xFB0 Res. CTI_CLAIMCLR Res. 0xFB8 CTI_CLAIMSET Res. 0xFA4 CTI_GATE Res. 0x140 Res. 0xFA0 CTI_CHOUTSTS Res. 0x13C CTI_CHINSTS Res. 0x138 CTI_TRIGOSTS Res. 0x134 CTI_TRIGISTS Res. 0x130 CTI_OUTEN7 Res. 0x0BC CTI_OUTEN6 Res. 0x0B8 CTI_OUTEN5 Res. 0x0B4 CTI_OUTEN4 Res. 0x0B0 CTI_OUTEN3 Res. 0x0SC Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Table 572. CTI register map and reset values (continued) TRIGOUTEN [3:0] 0 0 0 0 0 TRIGOUTEN [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 TRIGOUTEN [3:0] 0 0 TRIGINSTATUS[7:0] 0 0 TRIGOUTSTATUS[7:0] CHISTATUS [3:0] 0 0 0 0 CHOSTATUS [3:0] GATEEN [3:0] 0 0 1 1 CLAIMSET [3:0] CLAIMCLR [3:0] 1 1 0 1 1 EXMUXNUM [4:0] 1 0 MAJOR[3:0] 0 0xFFC 60.5.4 CTI_CIDR3 • S0: Cortex-M7 ETM • S1: Cortex-M7 ITM Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_CIDR2 Res. 0xFF8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_CIDR1 Res. 0xFF4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_CIDR0 Res. 0xFF0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_PIDR2 Res. 0xFE8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value Reset value Reset value Reset value Reset value 0 1 0 0 0 0 1 0 0 1 0 0 CLASS[3:0] PREAMBLE [11:8] 1 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. PARTNUM[7:0] Res. 1 0 0 0 0 0 1 JEP106ID [3:0] 1 0 0 REVISION [3:0] 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT [3:0] JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTI_PIDR1 Res. 0xFE4 CTI_PIDR0 Res. 0xFE0 CTI_PIDR7 Res. 0xFDC CTI_PIDR6 Res. 0xFD8 CTI_PIDR5 Res. 0xFD4 CTI_PIDR4 Res. 0xFD0 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure Table 572. CTI register map and reset values (continued) JEP106CON [3:0] 0 Reset value PARTNUM [11:8] JEP106ID [6:4] 1 1 REVAND[3:0] CMOD[3:0] PREAMBLE[7:0] 0 0 0 1 PREAMBLE[19:12] 0 1 PREAMBLE[27:20] 1 Trace funnel (CSTF) The trace funnel is a CoreSight component that combines the ATB buses from two trace sources into one single ATB. The CSTF has two ATB slave ports, and one ATB master port. An arbiter selects the slave ports according to a programmable priority. The slave ports are connected as follows: 2995/3178 3152 Debug infrastructure RM0433 The CSTF registers allow the slave ports to be individually enabled, and their priority settings to be configured. The priorities can be modified only when trace is disabled. The arbitration works as follows: • The arbiter selects the slave port with the highest assigned priority that has data valid • Up to min_hold_time transfers are passed from the selected slave to the master port, where min_hold_time is programmable in the CONTROL register. • A new arbitration is then performed High priority should be assigned to slave ports connected to sources with a small amount of buffering, or where data loss can not be tolerated. Low priority should be assigned to less critical sources or those with large buffers. For more information on the ATB Funnel CoreSight component, refer to the ARM® CoreSight™ SoC-400 Technical Reference Manual [2]. Trace funnel registers CSTF control register (CSTF_CTRL) Address offset: 0x000 Reset value: 0x0000 0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ENS1 ENS0 rw rw MIN_HOLD_TIME[3:0] rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:8 MIN_HOLD_TIME[3:0]: Number of transactions between arbitrations. 0x0: 1 transaction : 0xE: 15 transactions 0xF: Reserved Bits 7:2 Reserved, must be kept at reset value. Bit 1 ENS1: Slave port S1 enable 0: Disable port 1: Enable port Bit 0 ENS0: Slave port S0 enable 0: Disable port 1: Enable port CSTF priority register (CSTF_PRIORITY) Address offset: 0x004 Reset value: 0x0000 0688 2996/3178 DocID029587 Rev 3 RM0433 Debug infrastructure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIPORT1[2:0] PRIPORT0[2:0] rw rw Bits 31:6 Reserved, must be kept at reset value. Bits 5:3 PRIPORT1[2:0]: Slave port S1 priority 0: Highest priority : 7: Lowest priority Bits 2:0 PRIPORT0[2:0]: Slave port S0 priority 0: Highest priority : 7: Lowest priority CSTF claim tag set register (CSTF_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag CSTF claim tag clear register (CSTF_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 DocID029587 Rev 3 2997/3178 3152 Debug infrastructure RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag CSTF lock access register (CSTF_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:16] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w Bits 31:0 ACCESS_W[31:0]: CSTF register write access enable The field enables write access to some CSTF registers by processor cores (debuggers do not need to unlock the component). 0xC5ACCE55: Enable write access Other values: Disable write access CSTF lock status register (CSTF_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2998/3178 DocID029587 Rev 3 RM0433 15 Res. Debug infrastructure 14 Res. 13 Res. 12 Res. 11 Res. 10 Res. 9 Res. 8 Res. 7 6 Res. Res. 5 4 Res. Res. 3 2 1 0 Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the CSTF_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked. Only read access is permitted. Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented CSTF authentication status register (CSTF_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x2: Disabled 0x3: Enabled Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x2: Disabled 0x3: Enabled CSTF CoreSight device identity register (CSTF_DEVID) Address offset: 0xFC8 DocID029587 Rev 3 2999/3178 3152 Debug infrastructure RM0433 Reset value: 0x0000 0024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SCHEME[3:0] PORTCNT[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SCHEME[3:0]: Priority scheme 0x2: Static priority Bits 3:0 PORTCNT[3:0]: Number of input ports connected 0x4: Four input ports CSTF CoreSight device type identity register (CSTF_TYPEID) Address offset: 0xFCC Reset value: 0x0000 0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. DEVTYPEID[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DEVTYPEID[7:0]: Device type identifier 0x12: Trace funnel CSTF CoreSight peripheral identity register 0 (CSTF_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r 3000/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x08: CSTF part number CSTF CoreSight peripheral identity register 1 (CSTF_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: CSTF part number CSTF CoreSight peripheral identity register 2 (CSTF_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 001B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x1: r0p1 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code CSTF CoreSight peripheral identity register 3 (CSTF_PIDR3) Address offset: 0xFEC DocID029587 Rev 3 3001/3178 3152 Debug infrastructure RM0433 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications CSTF CoreSight peripheral identity register 4 (CSTF_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code CSTF CoreSight component identity register 0 (CSTF_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r 3002/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value CSTF CoreSight component identity register 1 (CSTF_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: CoreSight component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value CSTF CoreSight component identity register 2 (CSTF_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value CSTF CoreSight component identity register 3 (CSTF_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 DocID029587 Rev 3 3003/3178 3152 0xFC8 CSTF_DEVID 3004/3178 Reset value DocID029587 Rev 3 NSID [1:0] 0 0 0 0 0 0 0 1 PORTCNT [3:0] NSNID [1:0] Reset value SID [1:0] Res. Reset value Reset value KEY[31:0] Reset value 0 0 0 0 SLI Reset value Res. Res. Res. Res. PRIPORT0 [2:0] PRIPORT1 [2:0] PRIPORT2 [2:0] Res. Res. Res. Res. ENS0 Res. MIN_HOLD_TIME [3:0] ENS1 Res. PRIPORT3 [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ENS2 0 CLAIMSET [3:0] 0 CLAIMCLR [3:0] 0 SLK 1 ENS3 0 NTT Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. 1 Res. 1 SNID [1:0] Res. Res. Res. Res. Res. Res. Res. 1 SCHEME [3:0] Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_LAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_AUTHSTAT Res. CSTF_LSR Res. 0xFB4 Res. 0xFB0 Res. 0xFB8 CSTF_CLAIMCLR Res. 0xFA4 CSTF_CLAIMSET Res. 0xFA0 CSTF_PRIORITY Res. 0x004 CSTF_CTRL Res. 0x000 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value Trace funnel register map and reset values Table 573. CSTF register map and reset values 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0xFFC 60.5.5 CSTF_CIDR3 1. DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_CIDR2 Res. 0xFF8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_CIDR1 Res. 0xFF4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_CIDR0 Res. 0xFF0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_PIDR2 Res. 0xFE8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 Reset value 1 Reset value 0 Reset value 0 Reset value 0 Reset value Reset value Reset value 0 0 0 0 0 CLASS[3:0] PREAMBLE [11:8] 1 0 0 0 0 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. PARTNUM[7:0] Res. 1 0 0 0 0 0 1 0 0 JEP106ID [3:0] 0 0 0 1 REVISION [3:0] 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 Res. JEP106CON [3:0] 0 Res. 1 Res. 0 Res. 4KCOUNT [3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Reset value JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_PIDR1 Res. 0xFE4 CSTF_PIDR0 Res. 0xFE0 CSTF_PIDR7 Res. 0xFDC CSTF_PIDR6 Res. 0xFD8 CSTF_PIDR5 Res. 0xFD4 CSTF_PIDR4 Res. 0xFD0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSTF_TYPEID Res. 0xFCC Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure Table 573. CSTF register map and reset values (continued) DEVTYPEID[7:0] 0 0 Reset value PARTNUM [11:8] 1 JEP106ID [6:4] 1 REVAND[3:0] CMOD[3:0] PREAMBLE[7:0] 0 0 0 1 0 PREAMBLE[19:12] 1 PREAMBLE[27:20] 1 Embedded trace FIFO (ETF) The ETF is an 8 Kbyte memory that captures trace data from two trace sources, namely the ETM and ITM of the CPU core. The ETF is a design configuration of the CoreSight™ trace memory controller component. The ETF can be used in three modes (selected in the mode register): Hardware FIFO mode The trace memory is used as a FIFO that is drained through the ATB master interface. Trace data is captured into the trace RAM and when full, the incoming trace stream is 3005/3178 3152 Debug infrastructure RM0433 stalled. When the Trace buffer is not empty, trace data is drained out through the ATB master interface to the TPIU. In this mode, the role of the FIFO is to smooth the flow of trace information arriving at the trace port. Since the trace data can be very bursty in nature, the peak data rate can easily exceed the port capability, resulting in an overflow. The ETF allows a steady data rate at the trace port, which can then be sized according to the average rate rather than the peak. The trace is stored off-chip in real time by the trace port analyzer tool, and so the trace log can be very big. 2. Software FIFO mode The trace memory is used as a FIFO that can be read through the RRD Register while trace is being captured. Trace data is captured into the trace RAM and when full, the incoming trace stream is stalled. This mode allows the trace to be transferred by DMA into the system memory, or to a high speed interface (SPI, USB etc), or even monitored by software. Note that unlike the hardware FIFO mode, this mode is invasive, since it uses system resources which are shared by the processor. 3. Circular buffer mode The trace memory is used as a circular buffer. Trace data is captured into the Trace memory starting from the location pointed to by the write pointer register. Even when the trace memory is full, incoming trace data continues to be overwritten into the trace memory until a stop condition occurs. In this mode, the ETF stores the trace data on-chip, so the trace log size is limited to that of the ETF SRAM, 8 Kbytes in this case. Being a circular buffer, if the FIFO becomes full, incoming trace data overwrites the oldest stored data and the oldest stored data is lost. Therefore the contents of the trace buffer represent the most recent activity of the processor, up to the point when the buffer was stopped, rather than all the activity since the trace was started. There are three possible methods to read out the buffer contents once the trace stops: 3006/3178 – via the Trace port - with the TPIU enabled, the contents of the buffer are output over the Trace port. This can be done by setting the DRAINBUF bit in the ETF_FFCR register. – via the Debug port - the debugger can read the buffer via the RRD register that is accessible over the system APB-D. – by software - the processor can read the buffer via the RRD register, since the APB-D is accessible from the system bus. DocID029587 Rev 3 RM0433 Debug infrastructure The ETF can transition between the following states: • Disabled This state is entered after a reset, or when trace capture is disabled. The ETF must only be programmed in this state. • Running Trace capture is performed in this state. It is entered by enabling trace capture while in Disabled state. • Stopped Trace capture is stopped in this state, but the contents of the buffer can be read out or drained. This state is entered after a stop event (trigger or flush). • Disabling This is a transitional state while disabling trace capture. • Stopping This is a transitional state while stopping trace capture. • Draining This state is entered while draining the buffer in Stopped state. The state transition diagram is shown in Figure 818. Figure 818. ETF state transition diagram 'LVDEOHG 5($'< 7&(1 5XQQLQJ 7&(1 5($'< 7&(1 6WRSHYHQW 'LVDEOLQJ 5($'< 7&(1 7&(1 6WRSSLQJ 5($'< &LUFXODUEXIIHUHPSW\ 'UDLQLQJ 5($'< 6WRSSHG 5($'< '5$,1%8) FLUFXODUEXIIHUPRGHRQO\ 06Y 9 For more information on the trace memory controller CoreSight™ component, refer to the ARM® CoreSight™ trace memory controller technical reference manual [3]. ETF registers ETF RAM size register (ETF_RSZ) Address offset: 0x004 Reset value: 0x0000 0800 DocID029587 Rev 3 3007/3178 3152 Debug infrastructure 31 30 29 28 RM0433 27 26 25 24 23 Res. 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RSZ[30:16] r 15 14 13 12 11 10 9 8 7 RSZ[15:0] r Bit 31 Reserved, must be kept at reset value. Bits 30:0 RSZ[30:0]: RAM size The value of the field indicates the number of 32-bit words 0x800: 2048 words = 8 Kbyte ETF status register (ETF_STS) Address offset: 0x00C Reset value: 0x0000 001C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FTEMP EMPTY READY TRIGD TY r r r r FULL r Bits 31:5 Reserved, must be kept at reset value. Bit 4 EMPTY: Trace FIFO empty This bit is valid only when the TCEN bit of the ETF_CTL register is high. This bit reads as zero when TCEN is low. 0: Trace FIFO contains data 1: Trace FIFO is empty. Note: Empty trace FIFO does not mean that the ETF pipeline is empty. The latter is indicated by the FTEMPTY bit. Bit 3 FTEMPTY: Formatter empty This bit is set when trace capture has stopped, and all internal pipelines and buffers have drained. Unlike READY, it is not affected by buffer drains. The ACQCOMP output reflects the value of this bit. 3008/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bit 2 READY: ETF ready This bit is set when trace capture has stopped and all internal pipelines and buffers have drained (Stopped or Disabled state) Bit 1 TRIGD: Triggered The Triggered bit is set when trace capture is in progress and the TMC has detected a Trigger Event. This bit is cleared when leaving Disabled state. This bit is operational only in the Circular buffer mode. In all other modes, this bit is always low. This bit does not indicate that a trigger has been embedded in the formatted output trace data from the TMC. Trigger indication on the output trace stream is determined by the programming of the Formatter and Flush Control Register, ETF_FFCR. Bit 0 FULL: Trace buffer full In circular buffer mode, this flag is set when the RAM write pointer wraps around the top of the buffer, and remains set until the TCEN bit of the ETF_CTL register is cleared and set. In software and hardware FIFO modes, this flag indicates that the current space in the trace memory is less than or equal to the value programmed in the ETF_BUFWM Register, that is, Fill level >= MEM_SIZE - BUFWM. This bit is cleared when leaving Disabled state. The FULL output reflects the value of this register bit. ETF RAM read data register (ETF_RRD) Address offset: 0x010 Reset value: Unknown 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RRD[31:16] r 15 14 13 12 11 10 9 8 7 RRD[15:0] r Bits 31:0 RRD[31:0]: RAM Read Data. Circular buffer mode: When in Stopped state and the buffer is not empty, reading this register returns the next word of data from the trace buffer. When all of the trace buffer has been read, the Empty bit in the ETF_STS Register is set, and subsequent reads return 0xFFFFFFF. Reading this register when not in Stopped state returns 0xFFFFFFFF. Software FIFO mode: Reading this register returns data from the FIFO. If this register is read when the FIFO is empty, the data returned is 0xFFFFFFFF. Hardware FIFO mode: Reading this register returns 0xFFFFFFFF. ETF RAM read pointer register (ETF_RRP) Address offset: 0x014 Reset value: 0x0000 0000 DocID029587 Rev 3 3009/3178 3152 Debug infrastructure RM0433 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. RRP[12:0] rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:0 RRP[12:0]: RAM Read Pointer The RAM Read Pointer Register contains the value of the read pointer that is used to read entries from the trace memory over the APB interface via the ETF_RRD register. The pointer can be programmed with a byte address, 64-bit aligned (that is, bits 0 to 3 should be zero). The pointer is incremented by 8 each time a full 64-bit FIFO entry has been written. When the pointer reaches its maximum value, it wraps around. This register can only be written in Disabled state. It can be read in Disabled state, in Stopped state in circular buffer mode and SW FIFO mode, and also in Running and Stopping states in SW FIFO mode. ETF RAM write pointer register (ETF_RWP) Address offset: 0x018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. RWP[12:0] rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:0 RWP[12:0]: RAM write pointer The RAM write pointer register contains the value of the write pointer that is used to write entries into the trace memory over the APB interface via the ETF_RWD register. The pointer can be programmed with a byte address, 64-bit aligned (that is, bits 0 to 3 should be zero). The pointer is incremented by 8 each time a full 64-bit FIFO entry has been read. When the pointer reaches its maximum value, it wraps around. This register can only be written in Disabled state. It can be read in Disabled state, in Stopped state in circular buffer mode and SW FIFO mode, and also in Running and Stopping states in SW FIFO mode. ETF trigger counter register (ETF_TRG) Address offset: 0x01C Reset value: 0x0000 0000 3010/3178 DocID029587 Rev 3 RM0433 Debug infrastructure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. TRG[10:0] rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:0 TRG[10:0]: Trigger counter In Circular buffer mode, specifies the number of 32-bit words to capture in the trace RAM following the detection of either a rising edge on the TRIGIN input or a trigger packet in the incoming trace stream, ATID =7'h7D. On capturing the specified number of data words, a trigger event occurs. The effect of a trigger event on the ETF behavior is controlled by the FFCR Register. The number of 32-bit words written into the trace RAM following the trigger is the value stored in this register, plus one. This register is ignored when the ETF is in Software FIFO mode or Hardware FIFO mode. When the trigger counter starts counting, any additional triggers, either on TRIGIN or in the incoming trace stream, are ignored until the counter reaches zero. When the trigger counter has reached zero, it remains at zero until it is re-programmed with a write to this register. This register is cleared when READY goes high, so that the state of the counter when trace capture has stopped does not affect a subsequent trace capture session. Writing to this register when not in Disabled state results in unpredictable behavior. A read access to this register is permitted at any time when in Disabled state, or in Circular buffer mode. A read access returns the current value of the trigger counter. ETF control register (ETF_CTL) Address offset: 0x020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TCEN rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 TCEN: Trace capture enable When writing: 0: Disable trace capture (moves from Running, Stopping or Stopped state into Disabling or Disabled state) 1: Enable trace capture (moves from Disabled state into Running state) When reading, this bit is low when in Disabling or Disabled states, and high otherwise. DocID029587 Rev 3 3011/3178 3152 Debug infrastructure RM0433 ETF RAM write data register (ETF_RWD) Address offset: 0x024 Reset value: Unknown 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RWD[31:16] w 15 14 13 12 11 10 9 8 7 RWD[15:0] w Bits 31:0 RWD[31:0]: RAM write data When in Disabled state, a write to this register stores data at the location pointed to by the RWP. Writes to this register when not in Disabled state are ignored. When a full memory width (64-bit) of data has been written, the data is written to memory and the RAM Write Pointer is incremented to the next memory word. This register is used for test purposes. ETF mode register (ETF_MODE) Address offset: 0x028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE[1:0] rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 MODE[1:0]: Operation mode 00b: Circular buffer mode In this mode, the trace memory is used as a circular buffer. Trace data is captured into the Trace memory starting from the location pointed to by the write pointer register. Even when the trace memory is full, incoming trace data continues to be overwritten into the trace memory until a stop condition has occurred. 01b: Software FIFO mode In this mode, the trace memory is used as a FIFO that can be read through the RRD Register while trace is being captured. Trace data is captured into the trace RAM and when full, the incoming trace stream is stalled. 10b: Hardware FIFO mode In this mode, the trace memory is used as a FIFO that is drained through the ATB master interface. Trace data is captured into the trace RAM and when full, the incoming trace stream is stalled. When the Trace buffer is non-empty, trace data is drained out through the ATB master interface to the TPIU. 11b: Reserved 3012/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETF latched buffer fill level register (ETF_LBUFLVL) Address offset: 0x02C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res LBUFLEVEL[11:0] r Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 LBUFLEVEL[11:0]: Latched buffer fill level Reading this register returns the maximum fill level of the trace memory in 32-bit words since this register was last read. Reading this register also results in its contents being updated to the current fill level. When entering Disabled state, this register retains its last value. While in Disabled state, reads from this register do not affect its value. When exiting Disabled state, the LBUFLEVEL Register is cleared. This register is used for performance analysis of the trace system. ETF current buffer fill level register (ETF_CBUFLVL) Address offset: 0x030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res CBUFLEVEL[11:0] r Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 CBUFLEVEL[11:0]: Current buffer fill level Reading this register returns the current fill level of the trace memory in 32-bit words. This register is cleared when TCEN is low. DocID029587 Rev 3 3013/3178 3152 Debug infrastructure RM0433 ETF buffer level watermark register (ETF_BUFWM) Address offset: 0x034 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res Res BUFWM[10:0] rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:0 BUFWM[10:0]: Buffer level watermark The value programmed into this register indicates the required threshold vacancy level in 32bit words in the trace memory. When the space in the FIFO is less than or equal to this value, that is, Fill level >= MEM_SIZE - BUFWM, the FULL output is pulled high and the FULL bit in the STS Register is set. This register is used only in Software FIFO and Hardware FIFO modes. In Circular buffer mode, this functionality can be obtained by programming the RWP to the required vacancy trigger level, so that when the pointer wraps around, the FULL bit is set indicating that the vacancy level has fallen below the required level. The maximum value that can be written into this register is MEM_SIZE - 1. In this case, the FULL bit output is asserted after the first 32-bit word is written to trace memory. Writing to this register other than when in disabled state results in unpredictable behavior. ETF formatter and flush status register (ETF_FFSR) Address offset: 0x300 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FTSTO FLINPR PPED OG r 3014/3178 DocID029587 Rev 3 r RM0433 Debug infrastructure Bits 31:2 Reserved, must be kept at reset value. Bit 1 FTSTOPPED: Formatter stopped This bit behaves in the same way as the FTEMPTY bit in the ETF_STS register. Bit 0 FLINPROG: Flush in progress Indicates whether a flush on the ATB slave port is in progress. This bit reflects the status of the AFVALIDS output. A flush can be initiated by the flush control bits in the ETF_FFCR register, or requested by the ATB master port. 0: No flush in progress 1: Flush in progress ETF formatter and flush control register (ETF_FFCR) Address offset: 0x304 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STOP ONFL Res. Res. Res. ENTI ENFT rw rw Res. STOP DRAIN ONTR BUF. GEV. rw rw rw TRIGO TRGON TRGON NFL. TRGEV TRGIN rw rw Res. rw FLUSH FONTR FONFLI MAN GEV. N rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 DRAINBUF: Drain buffer This bit is used to enable draining of the trace data through the ATB master interface after the formatter has stopped. This is useful in Circular buffer mode to capture trace data into trace memory and then to drain the captured trace through the ATB master interface. Writing a one to this bit when in Stopped state starts the drain of the contents of the trace buffer through the ATB Master interface. This bit always reads as zero. The READY bit in the ETF_STS register goes low while the drain is in progress. This bit is functional only when the ETF is in Circular buffer mode and formatting is enabled, that is, the ENFT bit in the ETF_FFCR register is set. Setting this bit when the ETF is in any other mode, or when not in Stopped state, results in Unpredictable behavior. When trace capture is complete in Circular buffer mode, all of the captured trace must be retrieved from the trace memory through the same mechanism, either read all trace data out through RRD reads, or drain all trace data by setting the DRAINBUF bit. Setting the DRAINBUF bit after some of the captured trace has been read out through RRD results in unpredictable behavior. Bit 13 STPONTRGEV: Stop on trigger event 0: No effect 1: Stop trace capture when a trigger event occurs Enabling the ETF in Software FIFO mode or Hardware FIFO mode with this bit set results in unpredictable behavior. DocID029587 Rev 3 3015/3178 3152 Debug infrastructure RM0433 Bit 12 STOPONFL: Stop on flush 0: No effect 1: Stop trace capture when flush is completed If a flush is initiated by the ATB master interface, its completion does not lead to a formatter stop regardless of the value programmed in this bit. Bit 11 Reserved, must be kept at reset value. Bit 10 TRIGONFL: Trigger on flush 0: No effect 1: Indicate a trigger in the trace stream when flush is completed If ENFT and ENTI are both clear, this bit is ignored and no trigger is inserted into the trace stream. If a flush is initiated by the ATB master interface, its completion does not lead to a trigger indication regardless of the value programmed in this bit. Bit 9 TRGONTRGEV: Trigger on trigger event 0: No effect 1: Indicate a trigger in the trace stream when trigger event occurs If ENFT and ENTI are both clear, this bit is ignored and no trigger is inserted into the trace stream. This bit is not supported in Software FIFO mode or Hardware FIFO mode. Bit 8 TRGONTRGIN: Trigger on trigger in 0: No effect 1: Indicate a trigger in the trace stream when a rising edge is detected on the TRIGIN input. If ENFT and ENTI are both clear, this bit is ignored and no trigger is inserted into the trace stream. Bit 7 Reserved, must be kept at reset value. Bit 6 FLUSHMAN: Manual flush 0: No effect 1: Flush the trace FIFO and pipeline This bit is cleared automatically when the flush completes. If the TCEN bit in the ETF_CTL register is 0, writes to this bit are ignored. Bit 5 FONTRGEV: Flush on trigger event 0: No effect 1: Flush the trace FIFO and pipeline if a trigger event occurs This bit is not supported in Software FIFO mode or Hardware FIFO mode. If STPONTRGEV is set, this bit is ignored. Bit 4 FONFLIN: Flush on flush in 0: No effect 1: Flush the trace FIFO and pipeline if when a rising edge is detected on the FLUSHIN input 3016/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 3:2 Reserved, must be kept at reset value. Bit 1 ENTI: Enable trigger insertion Setting this bit enables the insertion of triggers in the formatted trace stream. A trigger is indicated by inserting one byte of data 8'h00 with ATID 7'h7D in the trace stream. Trigger indication on the trace stream is additionally controlled by the register bits TRIGONFL, TRGONTRGEV, and TRGONTRGIN in the FFCR Register. This bit can only be changed when READY is high, and TCEN is low. This bit takes effect only when the ENFT register bit in this register is set. If ENTI bit is set to high when ENFT is low, it results in formatting being enabled. Bit 0 ENFT: Enable formatting. 0: Formatting is disabled. Incoming trace data is assumed to be from a single trace source. 1: Formatting is enabled. If multiple ATIDs are received by the ETF when trace capture is enabled and the formatter is disabled, it results in interleaving of trace data. Disabling of formatting is supported only in Circular buffer mode. If the ETF is enabled in a mode other than Circular buffer mode with ENFT low, it results in formatting being enabled. If ENTI bit is set to high when ENFT is low, it results in formatting being enabled. This bit is ignored when in Disabled state. ETF periodic synchronization counter register (ETF_PSCR) Address offset: 0x308 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PSCOUNT[4:0] rw Bits 31:5 Reserved, must be kept at reset value. Bits 4:0 PSCOUNT[4:0]: Synchronization counter reload value Determines the reload value of the Synchronization Counter. The reload value takes effect the next time the counter reaches zero. Reads from this register return the reload value programmed into this register. This register is set to 0xA on reset, corresponding to a synchronization period of 1024 bytes. 0x0: Synchronization disabled 0x1-0x6: Reserved 0x7-0x1B: Synchronization period is 2PSCOUNT bytes 0x1C-0x1F: Reserved DocID029587 Rev 3 3017/3178 3152 Debug infrastructure RM0433 ETF claim tag set register (ETF_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag ETF claim tag clear register (ETF_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag 3018/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETF lock access register (ETF_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:16] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w Bits 31:0 ACCESS_W[31:0]: ETF register access enable Enables write access to some ETF registers by processor cores (debuggers do not need to unlock the component) 0xC5ACCE55: Enable write access Other values: Disable write access ETF lock status register (ETF_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the ETF_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked. Only read access is permitted. Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented DocID029587 Rev 3 3019/3178 3152 Debug infrastructure RM0433 ETF authentication status register (ETF_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x0: Not implemented Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x0: Not implemented ETF device configuration register (ETF_DEVID) Address offset: 0xFC8 Reset value: 0x0000 01C0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. MEMWIDTH[2:0] CONFIGTYP[1:0] CLK SCHEM ATBINPORTCNT[4:0] r r r r Bits 31:11 Reserved, must be kept at reset value. Bits 10:8 MEMWIDTH[2:0]: Memory interface data bus width 0x3: 64 bits (corresponds to 32-bit ATB data) Bits 7:6 CONFIGTYP[1:0]: Configuration type of component (ETB, ETR or ETF) 0x2: ETF Bit 5 CLKSCHEM: RAM clocking scheme (synchronous or asynchronous) 0: Synchronous Bits 4:0 ATBINPORTCNT[4:0]: Number/type of ATB input port multiplexing 0x0: None 3020/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETF device type identifier register (ETF_DEVTYPE) Address offset: 0xFCC Reset value: 0x0000 0032 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SUBTYPE[3:0] MAJORTYPE[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SUBTYPE[3:0]: Sub-classification 0x3: Captures trace data from the ATB slave interface into RAM that can be drained through the ATB master interface Bits 3:0 MAJORTYPE[3:0]: Major classification 0x2: Component is a trace link because it has an ATB master interface through which trace data can be drained out in Hardware FIFO mode. ETF CoreSight peripheral identity register 4 (ETF_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code DocID029587 Rev 3 3021/3178 3152 Debug infrastructure RM0433 ETF CoreSight peripheral identity register 0 (ETF_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x61: ETF part number ETF CoreSight peripheral identity register 1 (ETF_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: ETF part number ETF CoreSight peripheral identity register 2 (ETF_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 001F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 3022/3178 REVISION[3:0] JEDEC JEP106ID[6:4] r r r DocID029587 Rev 3 RM0433 Debug infrastructure Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x1: r0p1 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code ETF CoreSight peripheral identity register 3 (ETF_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications ETF CoreSight component identity register 0 (ETF_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value DocID029587 Rev 3 3023/3178 3152 Debug infrastructure RM0433 ETF CoreSight component identity register 1 (ETF_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: CoreSight component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value ETF CoreSight component identity register 2 (ETF_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value ETF CoreSight component identity register 3 (ETF_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r 3024/3178 DocID029587 Rev 3 0x300 ETF_FFSR DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. FTSTOPPED FLINPROG Reset value Res. 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. TCEN 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Reset value RRD[31:0] RRP[12:0] 0 RWP[12:0] 0 0 0 FULL 0 TRIGD 0 READY 0 FTEMPTY 0 EMPTY Reset value Reset value 0 0 0 0 MODE[1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_RWD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_RRD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_BUFWM Res. 0x034 ETF_CBUFLVL Res. 0x030 ETF_LBUFLVL Res. 0x02C ETF_MODE Res. 0x028 Res. 0x024 ETF_CTL Res. 0x020 ETF_TRG Res. 0x01C ETF_RWP Res. 0x018 ETF_RRP Res. 0x014 Res. 0x010 ETF_STS Res. Reset value Res. 0x00C Res. ETF_RSZ Res. 0x004 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value ETF register map and reset values Table 574. ETF register map and reset values RSZ[30:0] 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 TRG[10:0] Reset value RWD[31:0] 0 Reset value LBUFLEVEL[11:0] CBUFLEVEL[11:0] 0 0 0 0 0 0 0 0 BUFWM[10:0] 1 0 3025/3178 3152 0xFD4 0xFD8 3026/3178 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_PIDR6 Res. Reset value Res. ETF_PIDR5 Res. ETF_PIDR4 Res. 0xFD0 Res. Reset value DocID029587 Rev 3 1 Res. Reset value Reset value 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 Reset value ACCESS_W[31:0] Reset value 0 0 0 0 LOCKEXIST Reset value LOCKGRANT Reset value CLAIMCLR [3:0] CLAIMSET [3:0] 0 LOCKTYPE FONTRGEV FONFLIN Res. 1 1 0 1 0 0 0 0 0 0 0 0 1 ENTI ENFT Res. Res. FLUSHMAN Res. Res. TRGONTRGIN Res. Res. TRGONTRGEV Res. 0 NSID [1:0] ATBINPORTCNT [4:0] 0 MAJORTYPE [3:0] Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. TRGONFL Res. Res. STOPONFL Res. Res. STPONTRGEV Res. 0 NSNID [1:0] Res. Res. Res. Res. Res. Res. Res. Reset value JEP106CON [3:0] SID [1:0] 0 CLKSCHEM Reset value SNID [1:0] Res. Res. Res. Res. Res. Res. DRAINBUF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CONFIGTYP [1:0] MEMWDTH [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 SUBTYPE [3:0] 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 4KCOUNT [3:0] Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_LAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_DEVTYPE Res. ETF_DEVID Res. 0xFC8 Res. ETF_AUTHSTAT Res. 0xFD0 ETF_LSR Res. 0xFB4 Res. 0xFB0 Res. 0xFB8 ETF_CLAIMCLR Res. 0xFA4 ETF_CLAIMSET Res. 0x308 ETF_PSCR Res. 0xFA0 ETF_FFCR Res. 0x304 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Table 574. ETF register map and reset values (continued) PSCOUNT[4:0] 0 0 1 1 1 0 0 1 0 1 1 0 0 RM0433 Debug infrastructure Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. ETF_PIDR7 Res. 0xFDC Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 574. ETF register map and reset values (continued) 0 1 Reset value ETF_PIDR0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_PIDR1 Res. 0xFE4 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_PIDR2 Res. 0xFE8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_CIDR1 Res. Reset value 0xFF4 Reset value 60.5.6 0 0 0 0 0 1 0 1 0 PARTNUM [11:8] 1 1 0 0 1 JEP106ID [6:4] 0 1 1 0 0 0 0 0 0 0 1 PREAMBLE[7:0] 0 0 1 1 CLASS[3:0] PREAMBLE [11:8] 1 0 0 0 0 0 1 0 0 0 PREAMBLE[19:12] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_CIDR3 Res. 0xFFC Res. Reset value 1 0 REVAND[3:0] CMOD[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_CIDR2 Res. Reset value 0xFF8 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETF_CIDR0 Res. 0xFF0 Res. Reset value 0 REVISION [3:0] 0 Res. Reset value 1 JEP106ID [3:0] 1 Res. Reset value PARTNUM[7:0] JEDEC 0xFE0 0 0 0 1 0 1 PREAMBLE[27:20] 1 0 1 1 0 0 0 1 Trace port interface unit (TPIU) The TPIU is a CoreSight™ component that formats the trace stream and outputs it on the external trace port signals. The TPIU has a single ATB slave port for incoming trace data. The trace port is a synchronous parallel port, comprising a clock output, TRACECK, and four data outputs, TRACED(7:0). The trace port width is programmable in the range 1 to 8. Using a smaller port width reduces the number of test points/connector pins needed, and frees up IOs for other purposes. However it restricts the bandwidth of the trace port and hence the quantity of trace information that can be output in real time. The TRACECK output must be enabled by setting the TRACECLKEN bit in the DBGMCU control register before trace is sent to the TPIU. Furthermore, the TRACECK frequency can be programmed in the RCC. For more information on the Trace port interface CoreSight™ component, refer to the ARM® CoreSight™ SoC-400 technical reference manual [2]. DocID029587 Rev 3 3027/3178 3152 Debug infrastructure RM0433 TPIU registers TPIU supported port size register (TPIU_SUPPSIZE) Address offset: 0x000 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PORTSIZE[31:16] r 15 14 13 12 11 10 9 8 7 PORTSIZE[15:0] r Bits 31:0 PORTSIZE[31:0]: Indicates supported trace port sizes, from 1 to 32 pins. Bit n-1 when set indicates that port size n is supported. 0x0000 000F: Port sizes 1 to 4 supported TPIU current port size register (TPIU_CURPSIZE) Address offset: 0x004 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PORTSIZE[31:16] rw 15 14 13 12 11 10 9 8 7 PORTSIZE[15:0] rw Bits 31:0 PORTSIZE[31:0]: Indicates current trace port size Bit n-1 when set indicates that the current port size is n pins. The value of n must be within the range of supported port sizes (1-4). Only one bit can be set, or unpredictable behavior may result. This register should only be modified when the formatter is stopped. 3028/3178 DocID029587 Rev 3 RM0433 Debug infrastructure TPIU supported trigger modes register (TPIU_SUPTRGM) Address offset: 0x100 Reset value: 0x0000 011F 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 20 Res. Res. 19 Res. 18 17 16 Res. TRG RUN TRGD r r 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. TCOUN T8 Res. Res. Res. MULT 64K MULT 256 MULT 16 r r r r MULT4 MULT2 r r Bits 31:18 Reserved, must be kept at reset value. Bit 17 TRGRUN: Trigger running 0: Trigger has not occurred or counter is at 0 1: Trigger has occurred and counter is not at 0 Bit 16 TRIGD: Triggered 0: Trigger has not occurred 1: Trigger has occurred and counter has reached 0 Bits 15:9 Reserved, must be kept at reset value. Bit 8 TCOUNT8: 8-bit counter register 1: Implemented Bits 7:5 Reserved, must be kept at reset value. Bit 4 MULT64K: Multiplying the trigger counter by 65536 support 1: Supported Bit 3 MULT256: Multiplying the trigger counter by 256 support 1: Supported Bit 2 MULT16: Multiplying the trigger counter by 16 support 1: Supported Bit 1 MULT4: Multiplying the trigger counter by 4 support 1: Supported Bit 0 MULT2: Multiplying the trigger counter by 2 support 1: Supported DocID029587 Rev 3 3029/3178 3152 Debug infrastructure RM0433 TPIU trigger counter value register (TPIU_TRGCNT) Address offset: 0x104 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. TRIGCOUNT[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 TRIGCOUNT[7:0]: Enable trigger delay indication Enables delaying the indication of triggers to any external connected trace capture or storage devices. This counter is only eight bits wide and is intended to be used only with the counter multipliers in the Trigger multiplier register, 0x108. When a trigger is started, this value, in combination with the multiplier, is the number of words before the trigger is indicated. When the trigger counter reaches 0, the value written here is reloaded. Writing to this register causes the trigger counter value to reset but does not reset any values on the multiplier. Reading this register returns the preset value, not the current count. TPIU trigger multiplier register (TPIU_TRGMULT) Address offset: 0x108 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. MULT 64K MULT 256 MULT 16 rw rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:5 Reserved, must be kept at reset value. Bit 4 MULT64K: Multiply the trigger counter by 65536 0: Disabled 1: Enabled Bit 3 MULT256: Multiply the trigger counter by 256 0: Disabled 1: Enabled 3030/3178 DocID029587 Rev 3 MULT4 MULT2 rw rw RM0433 Debug infrastructure Bit 2 MULT16: Multiply the trigger counter by 16 0: Disabled 1: Enabled Bit 1 MULT4: Multiply the trigger counter by 4 0: Disabled 1: Enabled Bit 0 MULT2: Multiply the trigger counter by 2 0: Disabled 1: Enabled TPIU supported test patterns/modes register (TPIU_SUPTPM) Address offset: 0x200 Reset value: 0x0003 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PATF0 r 17 16 PCONT PTIME EN EN 2 r r 1 0 PATA5 PATW0 PATW1 r r r Bits 31:18 Reserved, must be kept at reset value. Bit 17 PCONTEN: Support of continuous mode 1: Supported Bit 16 PTIMEEN: Support of timed mode 1: Supported Bits 15:4 Reserved, must be kept at reset value. Bit 3 PATF0: Support of FF/00 pattern Indicates whether the FF/00 pattern is supported as output over the trace port. 1: Supported Bit 2 PATA5: Support of AA/55 pattern Indicates whether the AA/55 pattern is supported as output over the trace port. 1: Supported Bit 1 PATW0: Support of walking 0’s pattern Indicates whether the walking 0’s pattern is supported as output over the trace port. 1: Supported Bit 0 PATW1: Support of walking 1’s pattern Indicates whether the walking 1’s pattern is supported as output over the trace port. 1: Supported DocID029587 Rev 3 3031/3178 3152 Debug infrastructure RM0433 TPIU current test pattern/mode register (TPIU_CURTPM) Address offset: 0x204 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PATF0 rw 17 rw rw 1 0 PATA5 PATW0 PATW1 rw rw Bits 31:18 Reserved, must be kept at reset value. Bit 17 PCONTEN: Continuous mode enable 0: Disabled 1: Enabled Bit 16 PTIMEEN: Timed mode enable 0: Disabled 1: Enabled Bits 15:4 Reserved, must be kept at reset value. Bit 3 PATF0: FF/00 pattern enable Indicates whether the FF/00 pattern is enabled as output over the trace port 0: Disabled 1: Enabled Bit 2 PATA5: AA/55 pattern is enable Indicates whether the AA/55 pattern is enabled as output over the trace port 0: Disabled 1: Enabled Bit 1 PATW0: Walking 0’s pattern enable Indicates whether the walking 0’s pattern is enabled as output over the trace port 0: Disabled 1: Enabled Bit 0 PATW1: Walking 1’s pattern enable Indicates whether the walking 1’s pattern is enabled as output over the trace port 0: Disabled 1: Enabled 3032/3178 DocID029587 Rev 3 16 PCONT PTIME EN EN rw RM0433 Debug infrastructure TPIU test pattern repeat counter register (TPIU_TPRCR) Address offset: 0x208 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PATTCOUNT[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PATTCOUNT[7:0]: Number of TRACECLKIN cycles The field provides a 8-bit counter value to indicate the number of TRACECLKIN cycles for which a pattern runs before it switches to the next pattern. TPIU formatter and flush status register (TPIU_FFSR) Address offset: 0x300 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TCPRE FTSTO FLINPR SENT PPED OG r r r Bits 31:3 Reserved, must be kept at reset value. DocID029587 Rev 3 3033/3178 3152 Debug infrastructure RM0433 Bit 2 TCPRESENT: TRACECTL output pin availability Indicates whether the optional TRACECTL output pin is available for use. 0: TRACECTL pin is not present in this device. Bit 1 FTSTOPPED: Formatter stopped The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored. 0: Formatter has not stopped 1: Formatter has stopped Bit 0 FLINPROG: Flush in progress Indicates whether a flush on the ATB slave port is in progress. This bit reflects the status of the AFVALIDS output. A flush can be initiated by the flush control bits in the TPIU_FFCR register. 0: No flush in progress 1: Flush in progress TPIU formatter and flush control register (TPIU_FFCR) Address offset: 0x304 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. TRIG FL TRIG EVT TRIGIN Res. FON MAN FON TRIG FON FLIN Res. ENF CONT EN FTC rw rw rw rw rw rw rw rw Res. Res. STOP STOPF TRIG L rw rw Res. Bits 31:14 Reserved, must be kept at reset value. Bit 13 STOPTRIG: Stop on trigger event 0: No effect 1: Stop formatter when a trigger event occurs Bit 12 STOPFL: Stop on flush 0: No effect 1: Stop formatter when flush is completed Bit 11 Reserved, must be kept at reset value. Bit 10 TRIGFL: Trigger on flush 0: No effect 1: Indicate a trigger in the trace stream when flush is completed Bit 9 TRIGEVT: Trigger on trigger event 0: No effect 1: Indicate a trigger in the trace stream when trigger event occurs 3034/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bit 8 TRIGIN: Trigger on trigger in 0: No effect 1: Indicate a trigger in the trace stream when the TRIGIN input from the system CTI is asserted. Bit 7 Reserved, must be kept at reset value. Bit 6 FONMAN: Generate a manual flush 0: No effect 1: Flush the trace This bit is cleared automatically when the flush completes. Bit 5 FONTRIG: Flush on trigger event A trigger event occurs when the trigger counter reaches 0, or, if the trigger counter is 0, when the TRIGIN input from the system CTI is high. 0: No effect 1: Flush the trace if a trigger event occurs Bit 4 FONFLIN: Flush on flush in 0: No effect 1: Flush the trace if the FLUSHIN input from the system CTI is asserted Bits 3:2 Reserved, must be kept at reset value. Bit 1 ENFCONT: Enable continuous formatting 0: Continuous formatting is disabled 1: Continuous formatting is enabled Bit 0 ENFTC: Enable the embedding of triggers in formatted trace 0: Formatting is disabled 1: Formatting is enabled TPIU formatter synchronization counter register (TPIU_FSCR) Address offset: 0x308 Reset value: 0x0000 0040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CYCCOUNT[4:0] rw DocID029587 Rev 3 3035/3178 3152 Debug infrastructure RM0433 Bits 31:5 Reserved, must be kept at reset value. Bits 4:0 CYCCOUNT[4:0]: Enables effective use of TPAs Enables effective use of different-sized TPAs without wasting large amounts of storage capacity of the capture device. This counter contains the number of formatter frames since the last synchronization packet of 128 bits. It is a 12-bit counter with a maximum count value of 4096. This equates to synchronization every 65536 bytes, that is, 4096 packets x 16 bytes per packet. The default is set up for a synchronization packet every 1024 bytes, that is, every 64 formatter frames. If the formatter is configured for continuous mode, full and half-word sync frames are inserted during normal operation. Under these circumstances, the count value is the maximum number of complete frames between full synchronization packets. TPIU claim tag set register (TPIU_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag TPIU claim tag clear register (TPIU_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw 3036/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag TPIU lock access register (TPIU_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:15] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w Bits 31:0 ACCESS_W[31:0]: TPIU register access enable Enables write access to some TPIU registers by processor cores (debuggers do not need to unlock the component) 0xC5ACCE55: Enable write access Other values: Disable write access TPIU lock status register (TPIU_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID029587 Rev 3 Res. Res. 3037/3178 3152 Debug infrastructure RM0433 Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the TPIU_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked. Only read access is permitted. Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented TPIU authentication status register (TPIU_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x0: Not implemented Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x0: Not implemented 3038/3178 DocID029587 Rev 3 RM0433 Debug infrastructure TPIU device configuration register (TPIU_DEVID) Address offset: 0xFC8 Reset value: 0x0000 00A0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. SWO UART NRZ SWO MAN TCLK DATA FIFO SIZE[2:0] CLK RELAT MAXNUM[3:0] r r r r r r Bits 31:11 Reserved, must be kept at reset value. Bit 11 SWOUARTNRZ: Support of SWO UART or NRZ Indicates whether serial wire output, UART or NRZ, is supported. 0: Not supported Bit 10 SWOMAN: Support of SWO Manchester format Indicates whether serial wire output, Manchester encoded format, is supported. 0: Not supported Bit 9 TCLKDATA: Support of trace clock plus data 0: Not supported Bits 8:6 FIFOSIZE[2:0]: FIFO size in powers of 2 0x2: FIFO size = 4 (16 bytes) Bit 5 CLKRELAT: ATB clock and TRACECLKIN relation Indicates the relationship between the ATB clock and TRACECLKIN (synchronous or asynchronous) 1: Asynchronous Bits 4:0 MAXNUM[4:0]: Number/type of ATB input port multiplexing 0x0: None TPIU device type identifier register (TPIU_DEVTYPE) Address offset: 0xFCC Reset value: 0x0000 0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SUBTYPE[3:0] MAJORTYPE[3:0] r r DocID029587 Rev 3 3039/3178 3152 Debug infrastructure RM0433 Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SUBTYPE[3:0]: Sub-classification 0x1: Trace port component Bits 3:0 MAJORTYPE[3:0]: Major classification 0x1: Trace sink component TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x12: TPIU part number 3040/3178 DocID029587 Rev 3 RM0433 Debug infrastructure TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: TPIU part number TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 004B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x4: r0p5 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code DocID029587 Rev 3 3041/3178 3152 Debug infrastructure RM0433 TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications TPIU CoreSight component identity register 0 (TPIU_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value 3042/3178 DocID029587 Rev 3 RM0433 Debug infrastructure TPIU CoreSight component identity register 1 (TPIU_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: CoreSight component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value TPIU CoreSight component identity register 2 (TPIU_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value DocID029587 Rev 3 3043/3178 3152 Debug infrastructure RM0433 TPIU CoreSight component identity register 3 (TPIU_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value TPIU register map and reset values 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 Reset value 3044/3178 PATW1 1 1 1 1 PATW1 0 PATW0 0 PATW0 0 PATA5 0 PATF0 Res. Res. Res. Res. 0 0 0 0 0 PATTCOUNT[7:0] 0 DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PTIMEEN 0 Res. PTIMEEN 0 Res. PCONTEN 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x104 Res. Reset value TPIU_TPRCR 1 PCONTEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_CURTPM Res. 0x204 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_SUPTPM Res. 0x200 Res. Reset value MULT2 0 MULT4 0 MULT16 0 MULT256 0 PATA5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_TRGMULT Res. 0x108 Res. Reset value TRIGCOUNT[7:0] PATF0 Res. 0 MULT64K Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. TPIU_SUPTRGM 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 TRIGD 0 Res. 0 Res. 0 Reset value 0x104 0 Res. 0 TRGRUN Reset value TPIU_TRGCNT 0 PORTSIZE[31:0] Res. TPIU_CURPSIZE MULT2 0 MULT4 0 MULT16 0 MULT256 0 Res. 0 MULT64K 0 Res. 0 Res. 0 Res. 0 TCOUNT8 PORTSIZE[31:0] 0 Res. 0x100 Reset value Res. 0x004 TPIU_SUPPSIZE Res. 0x000 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 575. TPIU register map and reset values 0 0 0 0 0 0 0 0xFD4 0xFD8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_PIDR6 Res. Reset value Res. TPIU_PIDR5 Res. TPIU_PIDR4 Res. 0xFD0 DocID029587 Rev 3 TCLKDATA 0 0 Reset value Reset value 1 0 0 NSNID [1:0] 0 0 0 0 0 0 0 1 0 0 0 Reset value Reset value Reset value ACCESS_W[31:0] Reset value 0 SUBTYPE [3:0] 0 4KCOUNT [3:0] 1 0 0 0 0 0 LOCKEXIST 0 LOCKGRANT 1 Res. Res. Res. CLAIMSET [3:0] 0 Res. FONTRIG FONFLIN 0 1 0 0 0 FTSTOPPED FLINPROG 0 CYCCOUNT[11:0] 0 1 0 0 0 1 ENFTC 1 ENFCONT TCPRESENT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. FONMAN Res. TRIGIN 0 CLAIMCLR [3:0] 0 Res. TRiGEVt 0 LOCKTYPE Res. Res. Res. 0 Res. TRiGFL 0 Res. Res. Res. Res. 0 Res. Res. STOPFL Res. Reset value NSID [1:0] SID [1:0] Reset value Res. Res. Res. Res. 0 Res. Res. STOPTRIG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 SNID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CLKRELAT FIFOSIZE[2:0] SWOMAN 0 Res. Res. Res. 0 Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value SWOUARTNRZ Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_LAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_DEVTYPE Res. 0xFD0 TPIU_DEVID Res. 0xFC8 TPIU_AUTHSTAT Res. 0xFB8 TPIU_LSR Res. 0xFB4 Res. 0xFB0 TPIU_CLAIMCLR Res. 0xFA4 TPIU_CLAIMSET Res. 0xFA0 TPIU_FSCR Res. 0x308 TPIU_FFCR Res. 0x304 TPIU_FFSR Res. 0x300 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure Table 575. TPIU register map and reset values (continued) 0 0 0 0 1 0 0 0 0 1 0 1 1 0 MUXNUM[4:0] MAJORTYPE [3:0] 0 JEP106CON [3:0] 1 0 Reset value 3045/3178 3152 Debug infrastructure RM0433 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_PIDR7 Res. 0xFDC Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 575. TPIU register map and reset values (continued) 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_PIDR2 Res. 0xFE8 1 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_CIDR1 Reset value 60.5.7 0 0 1 0 0 1 JEP106ID [6:4] 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 PREAMBLE[19:12] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_CIDR3 Res. 0xFFC 1 1 CLASS[3:0] 0 Res. Reset value 1 0 PARTNUM [11:8] PREAMBLE [11:8] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFF8 Res. Reset value TPIU_CIDR2 1 0 PREAMBLE[7:0] 0 Res. Reset value 0xFF4 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_CIDR0 Res. 0xFF0 1 REVAND[3:0] CMOD[3:0] 0 Res. Reset value 0 REVISION [3:0] 0 Res. Reset value 0 JEP106ID [3:0] JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_PIDR1 0 Res. Reset value 0xFE4 PARTNUM [7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TPIU_PIDR0 Res. 0xFE0 Res. Reset value 0 0 0 0 1 0 1 PREAMBLE[27:20] 1 0 1 1 0 0 0 1 Serial wire output (SWO) and SWO trace funnel (SWTF) The SWO is a CoreSight component that formats the trace stream from the processor ITM and outputs it on the single wire TRACESWO output. The SWO trace funnel (SWTF) must be programmed to enable the trace bus from the Cortex-M7 ITM before trace is enabled. The SWTF registers are listed in Table 577. Compared to the TPIU, the SWO contains: • no formatter • no pattern generator • an 8-bit ATB input • no synchronous trace output, that is, no TRACEDATA or TRACECLK pins • no support for flush, because this is not required • no support for triggering The SWO output supports Manchester encoded and UART NRZ formats. For more information about the serial wire output CoreSight™ component, refer to the ARM® CoreSight™ Components Technical Reference Manual [4]. 3046/3178 DocID029587 Rev 3 RM0433 Debug infrastructure SWO registers SWO current output divisor register (SWO_CODR) Address offset: 0x010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. PRESCALER[12:0] rw Bits 31:14 Reserved, must be kept at reset value. Bits 12:0 PRESCALER[12:0]: SWO baud rate scaling The baud rate is the trace clock frequency divided by (PRESCALER - 1). The baud rate changes instantly, so it is recommended to stop the trace source and wait until the port is idle before writing to this register. SWO selected pin protocol register (SWO_SPPR) Address offset: 0x0F0 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PPROT[1:0] rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 PPROT[1:0]: Pin protocol 0x0: Reserved 0x1: Manchester 0x2: NRZ 0x3: Reserved DocID029587 Rev 3 3047/3178 3152 Debug infrastructure RM0433 SWO formatter and flush status register (SWO_FFSR) Address offset: 0x300 Reset value: 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FTNON TCPRE FTSTO STOP SENT PPED r r 0 FLIN PROG r r Bits 31:4 Reserved, must be kept at reset value. Bit 3 FTNONSTOP: Change of settings without stopping formatter 1: Change of settings is allowed with formatter running Bit 2 TCPRESENT: TRACECTL pin present on SWO 0: TRACECTL pin not present Bit 1 FTSTOPPED: Formatter stopped 0: Formatter running The bit always returns 0 as the SWO formatter cannot be stopped in this device. Bit 0 FLINPROG: Flush in progress 0: Flush is not in progress The bit always returns 0 as SWO flushing is not supported in this device. SWO claim tag set register (SWO_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw 3048/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag SWO claim tag clear register (SWO_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag SWO lock access register (SWO_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:15] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w DocID029587 Rev 3 3049/3178 3152 Debug infrastructure RM0433 Bits 31:0 ACCESS_W[31:0]: SWO register write access enable Enables write access to some SWO registers by processor cores (debuggers do not need to unlock the component) 0xC5ACCE55: Enable write access Other values: Disable write access SWO lock status register (SWO_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the SWO_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked - only read access is permitted Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented SWO authentication status register (SWO_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 3050/3178 SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x0: Not implemented Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x0: Not implemented SWO device configuration register (SWO_DEVID) Address offset: 0xFC8 Reset value: 0x0000 0EA0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWO UART NRZ SWO MAN TCLK DATA FIFO SIZE[2:0] CLK RELAT MAXNUM[4:0] r r r r r r Res. Res. Res. Bits 31:11 Reserved, must be kept at reset value. Bit 11 SWOUARTNRZ: SWO UART or NRZ support Indicates whether serial wire output, UART or NRZ, is supported. 1: Supported Bit 10 SWOMAN: SWO Manchester format support Indicates whether serial wire output, Manchester encoded format, is supported. 1: Supported Bit 9 TCLKDATA: Trace clock plus data support Indicates whether trace clock plus data is supported 1: Supported Bits 8:6 FIFOSIZE[2:0]: FIFO size in powers of 2 0x2: FIFO size = 4 (16 bytes) Bit 5 CLKRELAT: ATB clock to TRACECLKIN relation Indicates the relationship between the ATB clock and TRACECLKIN (synchronous or asynchronous) 1: Asynchronous Bits 4:0 MAXNUM[4:0]: Number/type of ATB input port multiplexing 0x0: None DocID029587 Rev 3 3051/3178 3152 Debug infrastructure RM0433 SWO device type identifier register (SWO_DEVTYPE) Address offset: 0xFCC Reset value: 0x0000 0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SUBTYPE[3:0] MAJORTYPE[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SUBTYPE[3:0]: Sub-classification 0x1: Trace port component Bits 3:0 MAJORTYPE[3:0]: Major classification 0x1: Trace sink component SWO CoreSight peripheral identity register 4 (SWO_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code 3052/3178 DocID029587 Rev 3 RM0433 Debug infrastructure SWO CoreSight peripheral identity register 0 (SWO_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x14: SWO part number SWO CoreSight peripheral identity register 1 (SWO_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: SWO part number DocID029587 Rev 3 3053/3178 3152 Debug infrastructure RM0433 SWO CoreSight peripheral identity register 2 (SWO_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 001B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x1: r0p0 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code SWO CoreSight peripheral identity register 3 (SWO_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications 3054/3178 DocID029587 Rev 3 RM0433 Debug infrastructure SWO CoreSight component identity register 0 (SWO_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value SWO CoreSight component identity register 1 (SWO_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: CoreSight component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value DocID029587 Rev 3 3055/3178 3152 Debug infrastructure RM0433 SWO CoreSight component identity register 2 (SWO_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value SWO CoreSight component identity register 3 (SWO_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value SWO register map and reset values Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_SPR Res. 0x000 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 576. SWO register map and reset values 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_CPR Res. 0x004 Res. Reset value Reset value 0x010 SWO_CODR Reset value 3056/3178 DocID029587 Rev 3 PRESCALER[12:0] 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 SWO_PIDR5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFD4 SWO_PIDR4 Res. 0xFD0 Res. SWO_DEVTYPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFD0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWOUARTNRZ SWOMAN TCLKDATA DocID029587 Rev 3 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 NSNID [1:0] 0 0 0 0 0 0 1 0 Reset value Reset value 0 0 SUBTYPE [3:0] 4KCOUNT [3:0] 1 0 0 0 0 LOCKEXIST ACCESS_W[31;0] LOCKGRANT Reset value CLAIMCLR [3;0] Reset value LOCKTYPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET [3;0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FTNONSTOP TCPRESENT FTSTOPPED FLINPROG Reset value Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 0 1 0 0 0 0 1 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value NSID [1;0] SID [1;0] Reset value SNID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_LAR CLKRELAT SWO_AUTHSTAT Res. SWO_LSR Res. SWO_CLAIMCLR Res. Reset value Res. SWO_CLAIMSET Res. SWO_FFCR Res. SWO_FFSR Res. SWO_STPR Res. SWO_STMR FIFOSIZE[2:0] SWO_DEVID Res. 0xFC8 Res. 0xFB8 Res. 0xFB4 PPROT [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_SPPR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 0xFB0 Res. 0xFA4 Res. 0xFA0 Res. 0x304 Res. 0x300 Res. 0x200 Res. 0x100 Res. 0x0F0 Res. RM0433 Debug infrastructure Table 576. SWO register map and reset values (continued) 1 Reset value 1 0 0 0 1 0 1 1 0 MUXNUM[4:0] 0 MAJORTYPE [3:0] JEP106CON [3:0] 1 Reset value 3057/3178 3152 0xFFC SWO_CIDR3 3058/3178 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ENS0 MIN_HOLD_TIME[3:0] rw DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_CIDR2 Res. 0xFF8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_CIDR1 Res. 0xFF4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_CIDR0 Res. 0xFF0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_PIDR2 Res. 0xFE8 Res. Reset value 0 Reset value 1 Reset value 0 Reset value Reset value Reset value Reset value 0 Reset value 1 0 0 0 0 0 0 REVISION [3:0] 0 1 0 0 0 CLASS[3:0] PREAMBLE [11:8] 1 0 0 0 0 0 0 0 1 JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_PIDR1 Res. 0xFE4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWO_PIDR0 Res. 0xFE0 Res. JEP106ID [3:0] 1 0 1 1 1 1 0 0 0 1 1 0 0 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. PARTNUM [7:0] Res. Reset value Res. Res. Res. Reset value Res. SWO_PIDR7 Res. 0xFDC Res. SWO_PIDR6 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 0xFD8 Res. Debug infrastructure RM0433 Table 576. SWO register map and reset values (continued) PARTNUM [11:8] 0 0 JEP106ID [6:4] 0 1 0 1 0 0 0 1 0 0 0 0 rw 1 1 REVAND[3:0] CMOD[3:0] PREAMBLE[7:0] 0 0 0 1 0 PREAMBLE[19:12] PREAMBLE[27:20] 1 1 SWTF registers SWTF control register (SWTF_CTRL) Address offset: 0x000 Reset value: 0x0000 0300 RM0433 Debug infrastructure Bits 31:12 Reserved, must be kept at reset value. Bits 11:8 MIN_HOLD_TIME[3:0]: Number of transactions between arbitrations. 0x0: 1 transaction : 0xE: 15 transactions 0xF: Reserved Bits 7:1 Reserved, must be kept at reset value. Bit 0 ENS0: Slave port S0 enable 0: Disable port 1: Enable port SWTF priority register (SWTF_PRIORITY) Address offset: 0x004 Reset value: 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIPORT0[2:0] rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PRIPORT0[2:0]: Slave port S0 priority 0: Highest priority : 7: Lowest priority SWTF claim tag set register (SWTF_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw DocID029587 Rev 3 3059/3178 3152 Debug infrastructure RM0433 Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag SWTF claim tag clear register (SWTF_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag SWTF lock access register (SWTF_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:16] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w 3060/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:0 ACCESS_W[31:0]: SWTF register write access enable Enables write access to some SWTF registers by processor cores (debuggers do not need to unlock the component) 0xC5ACCE55: Enable write access Other values: Disable write access SWTF lock status register (SWTF_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the SWTF_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked - only read access is permitted Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented SWTF authentication status register (SWTF_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r DocID029587 Rev 3 3061/3178 3152 Debug infrastructure RM0433 Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x2: Disabled 0x3: Enabled Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x2: Disabled 0x3: Enabled SWTF CoreSight device identity register (SWTF_DEVID) Address offset: 0xFC8 Reset value: 0x0000 0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SCHEME[3:0] PORTCNT[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SCHEME[3:0]: Priority scheme 0x2: Static priority Bits 3:0 PORTCNT[3:0]: Number of input ports connected 0x2: Two input ports SWTF CoreSight device type identity register (SWTF_TYPEID) Address offset: 0xFCC Reset value: 0x0000 0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. DEVTYPEID[7:0] r 3062/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DEVTYPEID[7:0]: Device type identifier 0x12: Trace funnel SWTF CoreSight peripheral identity register 0 (SWTF_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x08: SWTF part number SWTF CoreSight peripheral identity register 1 (SWTF_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: SWTF part number DocID029587 Rev 3 3063/3178 3152 Debug infrastructure RM0433 SWTF CoreSight peripheral identity register 2 (SWTF_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 001B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x1: r0p1 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code SWTF CoreSight peripheral identity register 3 (SWTF_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications 3064/3178 DocID029587 Rev 3 RM0433 Debug infrastructure SWTF CoreSight peripheral identity register 4 (SWTF_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code SWTF CoreSight component identity register 0 (SWTF_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value DocID029587 Rev 3 3065/3178 3152 Debug infrastructure RM0433 SWTF CoreSight component identity register 1 (SWTF_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: CoreSight component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value SWTF CoreSight component identity register 2 (SWTF_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value 3066/3178 DocID029587 Rev 3 0xFC8 SWTF_DEVID Reset value DocID029587 Rev 3 0 NSNID [1:0] 0 0 0 0 0 1 Reset value Reset value 0 SCHEME [3:0] 0 0 0 0 0 LOCKEXIST ACCESS_W[31:0] LOCKGRANT Reset value CLAIMCLR [3:0] Reset value LOCKTYPE Res. Res. CLAIMSET [3:0] 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIPORT PRIPORT 1[2:0] 0[2:0] 1 1 0 0 1 0 0 ENS1 ENS0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 NSID [1:0] SID [1:0] Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MIN_HOLD_ TIME[3:0] SNID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_LAR Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_AUTHSTAT Res. 0xFB8 SWTF_LSR Res. 0xFB4 Res. 0xFB0 SWTF_CLAIMCLR Res. 0xFA4 SWTF_CLAIMSET Res. 0xFA0 SWTF_PRIORITY Res. 0x004 SWTF_CTRL Res. 0x000 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure SWTF CoreSight component identity register 3 (SWTF_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value SWTF register map and reset values Table 577. SWTF register map and reset values 0 0 0 1 0 1 0 1 0 1 1 0 PORTCNT [3:0] 0 3067/3178 3152 0xFFC SWTF_CIDR3 60.5.8 3068/3178 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_CIDR2 Res. 0xFF8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_CIDR1 Res. 0xFF4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_CIDR0 Res. 0xFF0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Reset value 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 1 Reset value 0 Reset value 0 Reset value 0 Reset value 1 Reset value 0 1 0 1 1 REVISION] 0 0 0 0 0 0 0 0 0 0 0 1 0 0 JEP106ID [3:0] 0 1 0 0 1 0 0 CLASS 1 0 1 0 0 1 1 REVAND 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 1 Res. 1 Res. 0 0 Res. 4KCOUNT [3:0] Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_PIDR2 Res. 0xFE8 SWTF_PIDR1 Res. 0xFE4 SWTF_PIDR0 Res. 0xFE0 SWTF_PIDR7 Res. 0xFDC SWTF_PIDR6 Res. 0xFD8 SWTF_PIDR5 Res. 0xFD4 SWTF_PIDR4 Res. 0xFD0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTF_TYPEID Res. 0xFCC Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Table 577. SWTF register map and reset values (continued) DEVTYPEID[7:0] JEP106CON [3:0] 0 0 Reset value PARTNUM [7:0] PARTNUM [11:8] JEP106ID [6:4] 1 1 CMOD PREAMBLE 0 0 0 1 PREAMBLE PREAMBLE PREAMBLE 0 0 0 1 0 1 Microcontroller debug unit (DBGMCU) The DBGMCU component contains a number of registers that control the power and clock behavior in debug mode. Specifically it allows the debugger, or debug software, to: • maintain the clock and power to the processor cores when in low-power modes (sleep, stop or standby) • maintain the clock and power to the system debug and trace components when in low power modes • stop the clock to certain peripherals (CAN, SMBUS timeout, Watchdogs, Timers, RTC) when either processor core is stopped in debug mode. For timers having complementary outputs, the outputs are disabled (as if the MOE bit was reset) for RM0433 Debug infrastructure safety purposes when the counter is stopped (TIM1/8/15/16/17 = 1 in DBGMCU_APB2FZ1). The DBGMCU registers are not reset by a system reset, only by a power on reset. They are accessible to the debugger via the APB-D bus at base address 0xE00E1000. They are also accessible by both processor cores at base address 0x5C001000 Note: the DBGMCU is not a standard CoreSight component. Therefore, it does not appear in the system ROM table. DBGMCU registers DBGMCU identity code register (DBGMCU_IDC) Address offset: 0x000 Reset value: 0x100X 6450 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 20 19 18 17 16 Res. Res. Res. Res. 3 2 1 0 REV_ID[15:0] r 15 14 13 12 Res. Res. Res. Res. 11 10 9 8 7 DEV_ID[11:0] r Bits 31:16 REV_ID[15:0]: Revision 0x1001 = Revision Z 0x1003 = Revision Y Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DEV_ID[11:0]: Device ID 0x450: STM32H7 DBGMCU configuration register (DBGMCU_CR) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 Res. Res. Res. TRGO EN Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 rw Res. Res. Res. Res. Res. Res. Res. DBGST DBGST BY_D3 OP_D3 rw 22 21 D3DBG D1DBG TRACE CKEN CKEN CLKEN rw rw rw 6 5 4 Res. rw DocID029587 Rev 3 Res. Res. Res. DBG DBGST DBGST SLEEP BY_D1 OP_D1 _D1 rw rw rw 3069/3178 3152 Debug infrastructure RM0433 Bits 31:29 Reserved, must be kept at reset value. Bit 28 TRGOEN: External trigger output enable This bit controls the direction of the bi-directional trigger pin, TRGIO. 0: Input - TRGIO is connected to TRGIN 1: Output - TRGIO is connected to TRGOUT Bits 27:23 Reserved, must be kept at reset value. Bit 22 D3DBGCKEN: D3 debug clock enable This bit allows the debug components in the D3 domain (excluding the DAPCLK domain) to be switched off if they are not needed. 0: Disabled - D3 domain debug components are disabled and their clocks gated 1: Enabled - D3 domain debug components are clocked whenever the corresponding domain clock (CK_HCLK_D3) is active Bit 21 D1DBGCKEN: D1 debug clock enable This bit allows the debug components in the D1 domain (excluding those in the processor core) to be switched off if they are not needed. 0: Disabled - D1 domain debug components are disabled and their clocks gated 1: Enabled - D1 domain debug components are clocked whenever the corresponding domain clock (CK_HCLK_D1) is active Bit 20 TRACECLKEN: Trace port clock enable This bit enables the trace port clock, TRACECLK. 0: Disabled - TRACECLK is disabled 1: Enabled - TRACECLK is active Bits 19:9 Reserved, must be kept at reset value. Bit 8 DBGSTBY_D3: Allow debug in D3 Standby mode 0: Normal operation - all clocks are disabled and the domain powered down automatically in Standby mode(1). 1: Automatic clock stop/power-down disabled - all active clocks and oscillators continue to run during Standby mode, and the domain supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. Bit 7 DBGSTOP_D3: Allow debug in D3 Stop mode 0: Normal operation - domain clocks are disabled automatically in Stop mode(2) 1: Automatic clock stop/power-down disabled - all active clocks and oscillators continue to run during Stop mode. On exit from Stop mode, the clock settings is set to the Stop mode exit state. Bits 6:3 Reserved, must be kept at reset value. 3070/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bit 2 DBGSTBY_D1: Allow D1 domain debug in Standby mode 0: Normal operation - all clocks is disabled and the domain powered down automatically in Standby mode. 1: Automatic clock stop/power-down disabled - all active clocks and oscillators continue to run during Standby mode, and the domain supply is maintained, allowing full debug capability. On exit from Standby mode, a domain reset is performed. Bit 1 DBGSTOP_D1: Allow D1 domain debug in Stop mode 0: Normal operation - all clocks are disabled automatically in Stop mode 1: Automatic clock stop disabled - all active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings is set to the Stop mode exit state. Bit 0 DBGSLEEP_D1: Allow D1 domain debug in Sleep mode 0: Normal operation - processor clock is stopped automatically in Sleep mode 1: Automatic clock stop disabled - processor clock continues to run, allowing full debug capability 1. If CDBGPWRUPREQ in the debug port Control/Stat register is asserted, D3 will remain powered up and the DAPCLK active in Standby mode, even if DBGSTBY_D3 is reset. However the remaining D3 domain clocks will be switched off. 2. If CDBGPWRUPREQ in the debug port Control/Stat register is asserted, D3 will remain powered up and the DAPCLK active in Stop mode, even if DBGSTOP_D3 is reset. However the remaining D3 domain clocks will be switched off. DBGMCU APB3 peripheral freeze register CPU (DBGMCU_APB3FZ1) Address offset: 0x034 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. WWDG 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 WWDG1: WWDG1 stop in debug 0: Normal operation - WWDG1 continues to operate while the core is in debug mode 1: Stop in debug - WWDG1 is frozen while the core is in debug mode Bits 5:0 Reserved, must be kept at reset value. DocID029587 Rev 3 3071/3178 3152 Debug infrastructure RM0433 DBGMCU APB1L peripheral freeze register CPU (DBGMCU_APB1LFZ1) Address offset: 0x03C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. I2C3 I2C2 I2C1 Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. LPTIM1 TIM14 TIM13 TIM12 TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 I2C3: I2C3 SMBUS timeout stop in debug 0: Normal operation - I2C3 SMBUS timeout continues to operate while the core is in debug mode 1: Stop in debug - I2C3 SMBUS timeout is frozen while Cortex-M7 is in debug mode Bit 22 I2C2: I2C2 SMBUS timeout stop in debug 0: Normal operation - I2C2 SMBUS timeout continues to operate while the core is in debug mode 1: Stop in debug - I2C2 SMBUS timeout is frozen while Cortex-M7 is in debug mode Bit 21 I2C1: I2C1 SMBUS timeout stop in debug 0: Normal operation - I2C1 SMBUS timeout continues to operate while the core is in debug mode 1: Stop in debug - I2C1 SMBUS timeout is frozen while the core is in debug mode Bits 20:11 Reserved, must be kept at reset value. Bit 10 Reserved, must be kept at reset value. Bit 9 LPTIM1: LPTIM1 stop in debug 0: Normal operation - LPTIM1 continues to operate while the core is in debug mode 1: Stop in debug - LPTIM1 is frozen while Cortex-M7 is in debug mode Bit 8 TIM14: TIM14 stop in debug 0: Normal operation - TIM14 continues to operate while the core is in debug mode 1: Stop in debug - TIM14 is frozen while Cortex-M7 is in debug mode Bit 7 TIM13: TIM13 stop in debug 0: Normal operation - TIM13 continues to operate while the core is in debug mode 1: Stop in debug - TIM13 is frozen while Cortex-M7 is in debug mode Bit 6 TIM12: TIM12 stop in debug 0: Normal operation - TIM12 continues to operate while the core is in debug mode 1: Stop in debug - TIM12 is frozen while Cortex-M7 is in debug mode Bit 5 TIM7: TIM7 stop in debug 0: Normal operation - TIM7 continues to operate while the core is in debug mode 1: Stop in debug - TIM7 is frozen while Cortex-M7 is in debug mode Bit 4 TIM6: TIM6 stop in debug 0: Normal operation - TIM6 continues to operate while the core is in debug mode 1: Stop in debug - TIM6 is frozen while Cortex-M7 is in debug mode 3072/3178 DocID029587 Rev 3 RM0433 Bit 3 Debug infrastructure TIM5: TIM5 stop in debug 0: Normal operation - TIM5 continues to operate while the core is in debug mode 1: Stop in debug - TIM5 is frozen while Cortex-M7 is in debug mode Bit 2 TIM4: TIM4 stop in debug 0: Normal operation - TIM4 continues to operate while the core is in debug mode 1: Stop in debug - TIM4 is frozen while Cortex-M7 is in debug mode Bit 1 TIM3: TIM3 stop in debug 0: Normal operation - TIM3 continues to operate while the core is in debug mode 1: Stop in debug - TIM3 is frozen while Cortex-M7 is in debug mode Bit 0 TIM2: TIM2 stop in debug 0: Normal operation - TIM2 continues to operate while the core is in debug mode 1: Stop in debug - TIM2 is frozen while Cortex-M7 is in debug mode DBGMCU APB1H peripheral freeze register CPU (DBGMCU_APB1HFZ1) Address offset: 0x044 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. FDCAN Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 FDCAN: FDCAN stop in debug 0: Normal operation - FDCAN continues to operate while the core is in debug mode 1: Stop in debug - FDCAN is frozen while the core is in debug mode Bits 7:0 Reserved, must be kept at reset value. DBGMCU APB2 peripheral freeze register CPU (DBGMCU_APB2FZ1) Address offset: 0x04C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. HRTIM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM17 TIM16 TIM15 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM8 TIM1 rw rw rw DocID029587 Rev 3 3073/3178 3152 Debug infrastructure RM0433 Bits 31:30 Reserved, must be kept at reset value. Bit 29 HRTIM: HRTIM stop in debug 0: Normal operation - HRTIM continues to operate while the core is in debug mode 1: Stop in debug - HRTIM is frozen while Cortex-M7 is in debug mode Bits 27:18 Reserved, must be kept at reset value. Bit 18 TIM17: TIM17 stop in debug 0: Normal operation - TIM17 continues to operate while the core is in debug mode 1: Stop in debug - TIM17 is frozen and TIM17 outputs are disabled while Cortex-M7 is in debug mode Bit 17 TIM16: TIM16 stop in debug 0: Normal operation - TIM16 continues to operate while the core is in debug mode 1: Stop in debug - TIM16 is frozen and TIM16 outputs are disabled while Cortex-M7 is in debug mode Bit 16 TIM15: TIM15 stop in debug 0: Normal operation - TIM15 continues to operate while the core is in debug mode 1: Stop in debug - TIM15 is frozen and TIM15 outputs are disabled while Cortex-M7 is in debug mode Bits 15:2 Reserved, must be kept at reset value. Bit 1 TIM8: TIM8 stop in debug 0: Normal operation - TIM8 continues to operate while the core is in debug mode 1: Stop in debug - TIM8 is frozen and TIM8 outputs are disabled while Cortex-M7 is in debug mode Bit 0 TIM1: TIM1 stop in debug 0: Normal operation - TIM1 continues to operate while the core is in debug mode 1: Stop in debug - TIM1 is frozen and TIM1 outputs are disabled while Cortex-M7 is in debug mode. DBGMCU APB4 peripheral freeze register CPU (DBGMCU_APB4FZ1) Address offset: 0x04C Reset value: 0x0000 0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 Res. Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 18 17 16 Res. WDGL SD1 Res. RTC rw 15 Res. 14 Res. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LPTIM 5 LPTIM 4 LPTIM 3 LPTIM 2 Res. I2C4 Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 WDGLSD1: LS watchdog for D1 stop in debug 0: Normal operation - watchdog continues to count while the core is in debug mode 1: Stop in debug - watchdog is frozen while Cortex-M7 is in debug mode Bit 17 3074/3178 rw Reserved, must be kept at reset value. DocID029587 Rev 3 RM0433 Bit 16 Debug infrastructure RTC: RTC stop in debug 0: Normal operation - RTC continues to operate while the core is in debug mode 1: Stop in debug - RTC is frozen while Cortex-M7 is in debug mode Bits 15:13 Reserved, must be kept at reset value. Bit 12 LPTIM5: LPTIM5 stop in debug 0: Normal operation - LPTIM5 continues to operate while the core is in debug mode 1: Stop in debug - LPTIM5 is frozen while Cortex-M7 is in debug mode Bit 11 LPTIM4: LPTIM4 stop in debug 0: Normal operation - LPTIM4 continues to operate while the core is in debug mode 1: Stop in debug - LPTIM4 is frozen while Cortex-M7 is in debug mode Bit 10 LPTIM3: LPTIM2 stop in debug 0: Normal operation - LPTIM2 continues to operate while the core is in debug mode 1: Stop in debug - LPTIM2 is frozen while Cortex-M7 is in debug mode Bit 9 LPTIM2: LPTIM2 stop in debug 0: Normal operation - LPTIM2 continues to operate while the core is in debug mode 1: Stop in debug - LPTIM2 is frozen while Cortex-M7 is in debug mode Bit 8 Reserved, must be kept at reset value. Bit 7 I2C4: I2C4 SMBUS timeout stop in debug 0: Normal operation - I2C4 SMBUS timeout continues to operate while the core is in debug mode 1: Stop in debug - I2C4 SMBUS timeout is frozen while the core is in debug mode Bits 6:0 Reserved, must be kept at reset value. DocID029587 Rev 3 3075/3178 3152 0x054 DBGMCU_APB4FZ 1 60.6 3076/3178 Reset value 0x058 • ROM tables • System control space (SCS) • Breakpoint unit (FPB) • Data watchpoint and trace unit (DWT) • Instrumentation trace macrocell (ITM) • Embedded trace macrocell (ETM) • Cross trigger interface (CTI) DocID029587 Rev 3 LPTIM3 LPTIM2 0 0 0 0 0 Res. Res. TIM3 TIM2 Res. Reserved Res. Res. TIM4 0 TIM1 Res. TIM5 0 TIM8 Res. Res. Res. Res. Res. D3DBGCKEN D1DBGCKEN TRACECLKEN Res. Res. DBGSTPD2 DBGSLPD2 DBGSTBD1 DBGSTPD1 DBGSLPD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 Reserved Cortex-M7 debug functional description The Cortex-M7 subsystem features the following CoreSight™ components: Res. Res. TRGOEN 0 0 Res. Res. TIM6 0 Res. Res. 0 Res. 0 Res. Res. Reset value 0 Res. DBGMCU_CR DBGSTBD2 Res. TIM7 0 Res. 0 DBGSTPD3 0 Res. 0 Res. 0 Res. 0 WWDG1 TIM12 0 Res. 0 0 Res. 1 Res. 0 Res. 0 DBGSTBD3 TIM13 Reserved TIM14 0 FDCAN Reserved 0 Res. 1 0 Res. Reset value Res. 0 0 Res. 0 0 Res. 0 0 Res. 1 0 Res. 0 0 Res. 0 Res. 1 Res. 1 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 1 Res. 0 0 LPTIM1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. LPTIM4 0 LPTIM5 0 Res. 0 Res. 0 Res. TIM15 Res. Res. Res. Reset value REV_ID[15:0] Res. TIM16 0 Res. 0x050 Res. 0x048 Res. 0x040 TIM17 0x038 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x01C to 0x030 WDGLSD1 I2C1 Res. I2C2 0 Res. Res. Res. I2C3 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. HRTIM Res. Res. DBGMCU_IDC Res. Res. Reset value Res. DBGMCU_APB2FZ 1 Res. 0x04C DBGMCU_APB1HF Z1 Res. 0x044 DBGMCU_APB1LF Z1 Res. 0x03C DBGMCU_APB3FZ 1 Res. 0x034 Res. 0x004 Res. 0x000 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 DBGMCU register map and reset values Table 578. DBGMCU register map and reset values DEV_ID[11:0] Reserved 0 0 RM0433 Debug infrastructure These components are accessible by the debugger via the Cortex-M7 AHB-AP and its associated AHBD bus. 60.6.1 Cortex-M7 ROM tables The ROM table is a CoreSight™ component that contains the base addresses of all the CoreSight debug components accessible via the AHBD. These tables allow a debugger to discover the topology of the CoreSight system automatically. There are two ROM tables in the Cortex-M7 sub-system: • Cortex-M7 CPU ROM table This table is pointed to by the BASE register in the Cortex-M7 AHB-AP. It contains the base address pointers for the ETM and CTI, as well as for the Cortex-M7 CPU ROM table. • Cortex-M7 PPB (private peripheral bus) ROM table This table contains pointers to the Cortex-M7 System Control Space registers allowing the debugger to identify the CPU core, as well as to the remaining CoreSight components in the Cortex-M7 subsystem: FPB, DWT and ITM. The CPU ROM table occupies a 4-Kbyte, 32-bit wide chunk of AHBD address space, from 0xE00FE000 to 0xE00FEFFC. Table 579. Cortex-M7 CPU ROM table Address in ROM table Component name Component base address Component address offset Size Entry 0xE00FE000 Cortex-M7 PPB ROM table 0xE00FF000 0x00001000 4 Kbyte 0x00001003 0xE00FE004 Cortex-M7 ETM 0xE0041000 0xFFF43000 4 Kbyte 0xFFF43003 0xE00FE008 Cortex-M7 CTI 0xE0043000 0xFFF44000 4 Kbyte 0xFFF44003 0xE00FE00C Reserved - - - 0x1FF02002 0xE00FE010 Top of table - - - 0x00000000 0xE00FE010 to 0xE00FEFC8 Reserved - - - 0x00000000 0xE00FEFCC to 0xE00FEFFC ROM table registers - - - See Table 581 The Cortex-M7 PPB ROM table occupies a 4-Kbyte, 32-bit wide chunk of APB-D address space, from 0xE00FF000 to 0xE00FFFFC. Table 580. Cortex-M7 PPB ROM table Address in ROM table Component name Component base address Component address offset Size Entry 0xE00FF000 SCS 0xE000E000 0xFFF0F000 4 Kbyte 0xFFF0F003 0xE00FF004 DWT 0xE0001000 0xFFF02000 4 Kbyte 0xFFF02003 0xE00FF008 FPB 0xE0002000 0xFFF03000 4 Kbyte 0xFFF03003 0xE00FF00C ITM 0xE0000000 0xFFF01000 4 Kbyte 0xFFF01003 DocID029587 Rev 3 3077/3178 3152 Debug infrastructure RM0433 Table 580. Cortex-M7 PPB ROM table Address in ROM table Component name Component base address Component address offset Size Entry 0xE00FF010 TPIU(1) 0xE0040000 0xFFF41000 4 Kbyte 0xFFF41002 0xE00FF014 (1) 0xE0041000 0xFFF42000 4 Kbyte 0xFFF42002 ETM 0xE00FF018 Top of table - - - 0x00000000 0xE00FF01C to 0xE00FFFC8 Reserved - - - 0x00000000 0xE00FFFCC to 0xE00FFFFC ROM table registers - - - See Table 582 1. The TPIU and ETM are included in this table by default, but bit 0 is reset to indicate that they are not present. The Topology for the CoreSight™ components in the Cortex-M7 subsystem is shown in Figure 819. Figure 819. Cortex-M7 CoreSight Topology $+%$3 &RUWH[0&38520WDEOH #[()( &RUWH[033%520WDEOH #[()) [ 2IIVHW [)))) [()( [ 2IIVHW [ %$6(UHJLVWHU [) [ 2IIVHW [))) [ 2IIVHW [))) [ 2IIVHW [))) [ 2IIVHW [))) [& 7RSRIWDEOH [& 2IIVHW [))) [ 2IIVHW [))) [)' 3,'5 [ 2IIVHW [))) [ 7RSRIWDEOH [)' 3,'5 [))& &,'5 [))& &,'5 (PEHGGHGWUDFH (70 #[( [ 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 [ &URVVWULJJHU &7, #[( 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 6\VWHPFRQWUROVSDFH 6&6 #[(( [ 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 'DWDZDWFKSRLQWWUDFH ':7 #[( [ 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 %UHDNSRLQWXQLW )3% #[( [ 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 ,QVWUXPHQWDWLRQWUDFH ,70 #[( [ 5HJLVWHUILOHEDVH [)' 3,'5 [))& &,'5 06Y 9 3078/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Cortex-M7 CPU ROM registers CPU ROM memory type register (M7_CPUROM_MEMTYPE) Address offset: 0xFCC Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSME M r Bits 31:1 Reserved, must be kept at reset value. Bit 0 SYSMEM: System memory presence 1: System memory is present on this bus CPU ROM CoreSight peripheral identity register 4 (M7_CPUROM_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC continuation code DocID029587 Rev 3 3079/3178 3152 Debug infrastructure RM0433 CPU ROM CoreSight peripheral identity register 0 (M7_CPUROM_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0c8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0xC8: Cortex-M7 Processor ROM table CPU ROM CoreSight peripheral identity register 1 (M7_CPUROM_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x4: Cortex-M7 Processor ROM table CPU ROM CoreSight peripheral identity register 2 (M7_CPUROM_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 000B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3080/3178 DocID029587 Rev 3 RM0433 Debug infrastructure 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x0: rev r0p0 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code CPU ROM CoreSight peripheral identity register 3 (M7_CPUROM_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications CPU ROM CoreSight component identity register 0 (M7_CPUROM_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r DocID029587 Rev 3 3081/3178 3152 Debug infrastructure RM0433 Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value CPU ROM CoreSight component identity register 1 (M7_CPUROM_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x1: ROM table component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value CPU ROM CoreSight component identity register 2 (M7_CPUROM_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value 3082/3178 DocID029587 Rev 3 0xFEC M7_CPUROM _PIDR3 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_CPUROM _PIDR2 Res. 0xFE8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value 1 1 0 0 1 0 0 0 0 1 0 0 JEP106ID [3:0] 0 1 REVISION [3:0] 0 0 1 0 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 1 0 0 0 0 1 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT [3:0] JEDEC M7_CPUROM _PIDR1 Res. 0xFE4 M7_CPUROM _PIDR0 Res. Reset value Res. Reset value Res. 0xFDC M7_CPUROM _PIDR7 Res. M7_CPUROM _PIDR6 Res. 0xFD8 Res. 0xFD4 M7_CPUROM _PIDR5 Res. M7_CPUROM _PIDR4 Res. Reset value 0xFD0 Res. 0xFE0 SYSMEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_CPUROM _MEMTYPE Res. 0xFCC Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure CPU ROM CoreSight component identity register 3 (M7_CPUROM_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value Cortex-M7 CPU ROM table register map and reset values Table 581. Cortex-M7 CPU ROM table register map and reset values JEP106CON [3:0] 1 0 Reset value PARTNUM [7:0] PARTNUM [11:8] 0 JEP106ID [6:4] 1 REVAND[3:0] CMOD[3:0] 0 3083/3178 3152 Debug infrastructure RM0433 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFFC M7_CPUROM _CIDR3 Res. 0xFF8 M7_CPUROM _CIDR2 Res. 0xFF4 M7_CPUROM _CIDR1 Res. M7_CPUROM _CIDR0 Res. 0xFF0 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 581. Cortex-M7 CPU ROM table register map and reset values (continued) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value PREAMBLE[7:0] 1 1 0 1 0 0 0 0 1 0 0 0 PREAMBLE[19:12] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 CLASS[3:0] 0 Res. Reset value 0 PREAMBLE [11:8] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 1 0 1 PREAMBLE[27:20] 1 0 1 1 0 0 0 1 Cortex-M7 PPB ROM registers PPB ROM memory type register (M7_PPBROM_MEMTYPE) Address offset: 0xFCC Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SYSME M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r Bits 31:1 Reserved, must be kept at reset value. Bit 0 SYSMEM: System memory presence 1: System memory is present on this bus PPB ROM CoreSight peripheral identity register 4 (M7_PPBROM_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 3084/3178 4KCOUNT[3:0] JEP106CON[3:0] r r DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC continuation code PPB ROM CoreSight peripheral identity register 0 (M7_PPBROM_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0c8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0xC7: Cortex-M7 PPB ROM table PPB ROM CoreSight peripheral identity register 1 (M7_PPBROM_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x4: Cortex-M7 PPB ROM table DocID029587 Rev 3 3085/3178 3152 Debug infrastructure RM0433 PPB ROM CoreSight peripheral identity register 2 (M7_PPBROM_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 000B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x0: rev r0p0 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code PPB ROM CoreSight peripheral identity register 3 (M7_PPBROM_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications 3086/3178 DocID029587 Rev 3 RM0433 Debug infrastructure PPB ROM CoreSight component identity register 0 (M7_PPBROM_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value PPB ROM CoreSight component identity register 1 (M7_PPBROM_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x1: ROM table component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value DocID029587 Rev 3 3087/3178 3152 Debug infrastructure RM0433 PPB ROM CoreSight component identity register 2 (M7_PPBROM_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value PPB ROM CoreSight component identity register 3 (M7_PPBROM_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value Cortex-M7 PPB ROM table register map and reset values Reset value 3088/3178 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_PPBROM _PIDR4 Res. 0xFD0 Res. 1 Res. Reset value SYSMEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_PPBROM _MEMTYPE Res. 0xFCC Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 582. Cortex-M7 PPB ROM table register map and reset values 4KCOUNT [3:0] 0 DocID029587 Rev 3 0 0 0 JEP106CON [3:0] 0 1 0 0 Reset value Reset value Reset value 0xFF0 M7_PPBROM _CIDR0 0xFF4 M7_PPBROM _CIDR1 0xFF8 M7_PPBROM _CIDR2 0xFFC M7_PPBROM _CIDR3 60.6.2 DocID029587 Rev 3 • watchpoint • ETM trigger • PC sampling trigger • data address sampling trigger • data comparator (comparator 1 only) • clock cycle counter comparator (comparator 0 only) Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFEC M7_PPBROM _PIDR3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_PPBROM _PIDR2 Res. Reset value 0xFE8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 1 Reset value Reset value JEP106ID [3:0] 1 0 0 0 0 1 1 0 0 0 0 CLASS[3:0] PREAMBLE [11:8] 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 REVISION [3:0] 0 0 0 1 0 1 JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFE4 M7_PPBROM _PIDR1 Res. 0xFE0 M7_PPBROM _PIDR0 Res. Reset value M7_PPBROM _PIDR7 Res. Reset value 0xFDC Res. 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFD8 M7_PPBROM _PIDR6 Res. M7_PPBROM _PIDR5 Res. Reset value 0xFD4 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure Table 582. Cortex-M7 PPB ROM table register map and reset values (continued) PARTNUM [7:0] PARTNUM [11:8] 0 JEP106ID [6:4] 1 REVAND[3:0] CMOD[3:0] PREAMBLE[7:0] 0 0 0 1 0 PREAMBLE[19:12] 1 PREAMBLE[27:20] 1 Cortex-M7 data watchpoint and trace unit (DWT) The DWT provides four comparators that can be used as: 3089/3178 3152 Debug infrastructure RM0433 It also contains counters for: • clock cycles • folded instructions • load store unit (LSU) operations • sleep cycles • number of cycles per instruction • interrupt overhead A DWT comparator compares one of the following with the value held in its DWT_COMP register: • a data address • an instruction address • a data value • the cycle count value, for comparator 0 only. For address matching, the comparator can use a mask, so it matches a range of addresses. On a successful match, the comparator generates one of the following: • one or more DWT data trace packets, containing one or more of: – the address of the instruction that caused a data access – an address offset, bits[15:0] of the data access address – the matched data value • a watchpoint debug event, on either the PC value or the accessed data address • a CMPMATCH[N] event that signals the match outside the DWT unit A watchpoint debug event either generates a DebugMonitor exception, or causes the processor to halt execution and enter Debug state. For more details on how to use the DWT, refer to the ARM®v7-M Architecture Reference Manual [5]. Cortex-M7 DWT registers DWT control register (M7_DWT_CTRL) Address offset: 0x000 Reset value: 0x4000 0000 31 30 29 28 NOTR CPKT NUMCOMP[3:0]. r 15 Res. 14 Res. 3090/3178 27 26 25 24 NOEX NOCYC NOPRF TTRIG CNT CNT r r r r 11 10 9 8 23 Res. 22 21 20 19 18 17 16 SLEEP CYCEV FOLDE LSUEV EXCEV CPIEVT EXCTR EVTEN TENA VTENA TENA TENA ENA CENA A 7 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 13 12 Res. PCSA MPLE NA SYNCTAP[1:0] CYCTA P POSTINIT[3:0] POSTRESET[3:0] CYCCN TENA rw rw rw rw rw rw DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:28 NUMCOMP[3:0]: Number of comparators implemented (read-only) 0x4: Four comparators Bit 27 NOTRCPKT: Trace sampling and exception tracing support (read-only) 0: Supported Bit 26 NOEXTTRIG: External match signal, CMPMATCH support (read-only) 0: Supported Bit 25 NOCYCCNT: Cycle counter support (read-only) 0: Supported Bit 24 NOPRFCNT: Profiling counter support (read-only) 0: Supported Bit 23 Reserved, must be kept at reset value. Bit 22 CYCEVTENA: Enable for POSTCNT underflow event counter packet generation 0: Disabled 1: Enabled Bit 21 FOLDEVTENA: Enable for folded instruction counter overflow event generation 0: Disabled 1: Enabled Bit 20 LSUEVTENA: Enable for LSU counter overflow event generation 0: Disabled 1: Enabled Bit 19 SLEEPEVTENA: Enable for sleep counter overflow event generation 0: Disabled 1: Enabled Bit 18 EXCEVTENA: Enable for exception overhead counter overflow event generation 0: Disabled 1: Enabled Bit 17 CPIEVTENA: Enable for CPI counter overflow event generation 0: Disabled 1: Enabled Bit 16 EXCTRCENA: Enable for exception trace generation 0: Disabled 1: Enabled Bits 15:13 Reserved, must be kept at reset value. Bit 12 PCSAMPLENA: POSTCNT counter use enable Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation. 0: Disabled 1: Enabled DocID029587 Rev 3 3091/3178 3152 Debug infrastructure RM0433 Bits 11:10 SYNCTAP[1:0]: Position of synchronization packet counter tap on CYCCNT counter This selection determines the synchronization packet rate. 0x0: Disabled - no synchronization packets 0x1: Tap at CYCCNT[24] 0x2: Tap at CYCCNT[26] 0x3: Tap at CYCCNT[28] Bit 9 CYCTAP: Position of the POSTCNT tap on the CYCCNT counter 0: Tap at CYCCNT[6] 1: Tap at CYCCNT[10] Bits 8:5 POSTINIT[3:0]: Initial value of the POSTCNT counter Writes to this field are ignored if POSTCNT counter is enabled (that is, CYCEVTENA or PCSAMPLENA must be reset prior to writing POSTINIT). Bits 4:1 POSTPRESET[3:0]: Reload value of the POSTCNT counter. Bit 0 CYCCNTENA: CYCCNT counter enable 0: Disabled 1: Enabled DWT cycle count register (M7_DWT_CYCCNT) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CYCCNT[31:15] rw 15 14 13 12 11 10 9 8 7 CYCCNT[15:0] rw Bits 31:0 CYCCNT[31:0]: Processor clock cycle counter DWT CPI count register (M7_DWT_CPICNT) Address offset: 0x008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CPICNT[7:0] rw 3092/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 CPICNT[7:0]: CPI counter Counts additional cycles required to execute multi-cycle instructions, except those recorded by DWT_LSUCNT, and counts any instruction fetch stalls. DWT exception count register (M7_DWT_EXCCNT) Address offset: 0x00C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. EXCCNT[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 EXCCNT[7:0]: Exception overhead cycle counter Counts the number of cycles spent in exception processing. DWT sleep count register (M7_DWT_SLPCNT) Address offset: 0x010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SLEEPCNT[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 SLEEPCNT[7:0]: Sleep cycle counter Counts the number of cycles spent in sleep mode (WFI, WFE, sleep-on-exit). DocID029587 Rev 3 3093/3178 3152 Debug infrastructure RM0433 DWT LSU count register (M7_DWT_LSUCNT) Address offset: 0x014 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. LSUCNT[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 LSUCNT[7:0]: Load store counter Counts additional cycles required to execute load and store instructions. DWT fold count register (M7_DWT_FOLDCNT) Address offset: 0x018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. FOLDCNT[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 FOLDCNT[7:0]: Folded instruction counter Increments on each instruction that takes 0 cycles. DWT program counter sample register (M7_DWT_PCSR) Address offset: 0x01C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EIASAMPLE[31:15] rw 15 14 13 12 11 10 9 8 7 EIASAMPLE[15:0] rw 3094/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:0 EIASAMPLE[31:0]: Executed instruction address sample value Samples the current value of the program counter. DWT comparator register x (M7_DWT_COMPx) Address offset: 0x020 + x * 0x10 (for x = 0 to 3) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 COMP[31:15] rw 15 14 13 12 11 10 9 8 7 COMP[15:0] rw Bits 31:0 COMP[31:0]: Reference value for comparison. DWT mask register x (M7_DWT_MASKx) Address offset: 0x024 + x * 0x10 (for x = 0 to 3) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MASK[4:0] rw Bits 31:5 Reserved, must be kept at reset value. Bits 4:0 MASK[4:0]: Comparator mask size Provides the size of the ignore mask applied to the access address for address range matching by comparator n. A debugger can write 0b11111 to this field and then read the register back to determine the maximum mask size supported. DWT function register x (M7_DWT_FUNCTx) Address offset: 0x028 + x * 0x10 (for x = 0 to 3) Reset value: 0x0000 0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 23 22 21 20 Res. MATCH ED Res. Res. Res. Res. r DocID029587 Rev 3 19 18 17 16 DATAVADDR1[3:0] rw 3095/3178 3152 Debug infrastructure 15 14 13 12 RM0433 11 10 9 8 DATAVADDR0[3:0] DATAVSIZE[1:0] LINK1 ENA rw rw rw 7 DATAV CYC MATCH MATCH rw 6 5 4 Res. EMIT RANGE Res. rw 3 2 1 0 FUNCTION[3:0] rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 MATCHED: Comparator match (read-only) Indicates if a comparator match has occurred since the register was last read. 0: No match 1: Match occurred Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 DATAVADDR1[3:0]: Comparator number of a second comparator When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a second comparator to use for linked address comparison. Bits 15:12 DATAVADDR0[3:0]: Comparator number of a comparator When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold the comparator number of a comparator to use for linked address comparison. Bits 11:10 DATAVSIZE[1:0]: Size of required data comparison For data value matching, specifies the size of the required data comparison. 0x0: Byte 0x1: Half word 0x2: Word 0x3: Reserved Bit 9 LNK1ENA: Support of a second linked comparator (read-only) Indicates whether use of a second linked comparator is supported (read-only). 1: Supported Bit 8 DATAVMATCH: Cycle comparison enable 0: Perform address comparison 1: Perform data value comparison Bit 7 CYCMATCH: Cycle count comparison enable on comparator 0 This field is reserved for other comparators. 0: No cycle count comparison 1: Compare DWT_COMP0 with the cycle counter, DWT_CYCCNT Bit 6 Reserved, must be kept at reset value. 3096/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bit 5 EMITRANGE: Data trace address offset packet enable Enables generation of data trace address offset packets (containing data address bits 0 to 15) 0: Disabled 1: Enabled Bit 4 Reserved, must be kept at reset value. Bits 3:0 FUNCTION[3:0]: Action on comparator match The meaning of this bit field depends on the setting of the DATAVMATCH and CYCMATCH fields. See [5]. DWT CoreSight peripheral identity register 4 (M7_DWT_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code DWT CoreSight peripheral identity register 0 (M7_DWT_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x02: DWT part number DocID029587 Rev 3 3097/3178 3152 Debug infrastructure RM0433 DWT CoreSight peripheral identity register 1 (M7_DWT_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x0: DWT part number DWT CoreSight peripheral identity register 2 (M7_DWT_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 003B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x3: r0p4 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code DWT CoreSight peripheral identity register 3 (M7_DWT_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 3098/3178 DocID029587 Rev 3 RM0433 Debug infrastructure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications DWT CoreSight component identity register 0 (M7_DWT_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value DWT CoreSight component identity register 1 (M7_DWT_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 00E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r DocID029587 Rev 3 3099/3178 3152 Debug infrastructure RM0433 Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0xE: Trace generator component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value DWT CoreSight component identity register 2 (M7_DWT_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value DWT CoreSight component identity register 3 (M7_DWT_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value Cortex-M7 DWT register map and reset values The Cortex-M7 DWT registers are located at address range 0xE0001000 to 0xE0001FFC, on the AHBD. 3100/3178 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M7_DWT_MASK2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x044 Reset value Res. 0x040 Res. 0x038 M7_DWT_FUNCT1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 M7_DWT_MASK1 Res. Res. Res. Res. Res. Res. Res. 0 0 M7_DWT_COMP1 M7_DWT_COMP2 0 0 0 0 0 Reset value DocID029587 Rev 3 0 0 0 0 0 0 0 0 M7_DWT_MASK0 Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Reset value SLEEPCNT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 FUNCTION [3:0] 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. 0 0 0 Res. 0 Res. Res. Res. Reset value 0 Res. Reset value 0 0 EMITRANGE 0 Res. Res. Res. Res. Reset value 0 Res. Reset value Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYCCNTENA POSTPRESET [3:0] POSINIT [3:0] CYCTAP SYNCTAP [1:0] PCSAMPLENA Res. Res. Res. 0 Res. Res. Res. CPIEVTENA EXCTRCENA 0 Res. Res. Res. Res. 0 CYCMATCH 0 Res. 0 Res. Res. Res. EXCEVTENA 0 LNK1ENA 0 Res. 0 Res. Res. Res. Res. LSUEVTENA SLEEPEVTENA 0 DATAVMATCH 0 Res. 0 Res. Res. Res. Res. FOLDEVTENA 0 Res. Res. CYCEVTENA 0 DATAVSIZE [1:0] 0 Res. M7_DWT_COMP0 Res. Res. Res. 0 FUNCTION [3:0] 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 DATAVADDR0 [3:0] 0 Res. M7_DWT_PCSR Res. Res. Res. Res. Res. 0 EMITRANGE 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. 0 CYCMATCH 0 Res. 0 Res. 0 DATAVADDR1 [3:0] 0 Res. Res. 0 LNK1ENA 0 Res. 0 Res. 0 Res. Res. 0 DATAVMATCH 0 Res. 0 Res. Res. CYCCNT[31:0] 0 DATAVSIZE [1:0] 0 Res. 0 Res. 0 Res. M7_DWT_CPICNT Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 DATAVADDR0 [3:0] 0 Res. 0 Res. NOPRFCNT 0 Res. 0 Res. NOCYCCNT 0 Res. Res. Res. Reset value Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 DATAVADDR1 [3:0] 0 Res. Reset value Res. Res. NOTRCPKT NOEXTTRIG 0 NUMCOMP [3:0] 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 MATCHED Res. Res. Res. Res. Res. Res. 1 Res. 0 Res. Res. Res. Res. Res. Res. M7_DWT_CYCCNT 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 MATCHED 0 Res. 0 Res. 0 Res. Reset value Res. 0 Res. 0 Res. 0 Res. M7_DWT_FUNCT0 0 Res. Reset value Res. M7_DWT_FOLDCN T Res. 0 Res. 0x034 Reset value Res. 0x030 M7_DWT_LSUCNT Res. 0x028 M7_DWT_SLPCNT Res. 0x024 Res. 0x020 Res. 0x01C Res. 0x018 Res. 0x014 M7_DWT_EXCCNT Res. Reset value Res. 0x010 Res. 0x00C Res. 0x008 M7_DWT_CTRL Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. 0x004 Res. 0x000 Res. RM0433 Debug infrastructure Table 583. Cortex-M7 DWT register map and reset values CPICNT[7:0] EXCCNT[7:0] LSUCNT[7:0] FOLDCNT[7:0] 0 0 0 0 0 0 0 0 EIASAMPLE[31:0] COMP[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK[4:0] 0 0 0 0 COMP[31:0] 0 0 0 0 0 0 0 0 MASK[4:0] 0 COMP[31:0] 0 0 0 0 0 0 0 0 MASK[4:0] 0 3101/3178 3152 0xFFC M7_DWT_CIDR3 3102/3178 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 Reset value 1 0 Reset value 0 Reset value 0 Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 M7_DWT_MASK3 Reset value 0 0 0 0 0 0 CLASS[3:0] PREAMBLE [11:8] 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 4KCOUNT [3:0] 0 0 JEP106ID [3:0] 1 REVISION [3:0] 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 Res. 0 FUNCTION [3:0] 0 Res. 0 Res. 0 Res. 0 Res. CYCMATCH FUNCTION [3:0] Res. EMITRANGE Res. DATAVSIZE [1:0] LNK1ENA DATAVADDR0 [3:0] DATAVADDR1 [3:0] Res. Res. Res. DATAVMATCH 0 Res. 0 EMITRANGE 0 Res. CYCMATCH 0 Res. LNK1ENA DATAVMATCH 0 Res. Res. Res. 0 Res. Reset value Res. Res. Res. Res. DATAVSIZE [1:0] 0 Res. Res. 0 Reset value PARTNUM [7:0] Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. MATCHED 0 Res. Res. Res. Res. DATAVADDR0 [3:0] 0 Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. DATAVADDR1 [3:0] Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MATCHED 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. M7_DWT_COMP3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. M7_DWT_CIDR2 Res. 0xFF8 M7_DWT_CIDR1 Res. 0xFF4 M7_DWT_CIDR0 Res. 0xFF0 M7_DWT_PIDR3 Res. 0xFEC M7_DWT_PIDR2 Res. 0xFE8 M7_DWT_PIDR1 Res. 0xFE4 M7_DWT_PIDR0 Res. 0xFE0 M7_DWT_PIDR7 Res. 0xFDC M7_DWT_PIDR6 Res. 0xFD8 M7_DWT_PIDR5 Res. 0xFD4 M7_DWT_PIDR4 Res. 0xFD0 M7_DWT_FUNCT3 Res. 0x058 Res. 0x054 Res. 0x050 M7_DWT_FUNCT2 Res. 0x048 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Table 583. Cortex-M7 DWT register map and reset values (continued) COMP[31:0] 0 0 0 0 0 0 0 0 MASK[4:0] 0 0 JEP106CON [3:0] 0 Reset value 1 0 PARTNUM [11:8] 0 JEP106ID [6:4] REVAND[3:0] CMOD[3:0] 1 PREAMBLE[7:0] 0 0 0 1 0 PREAMBLE[19:12] 1 PREAMBLE[27:20] 1 RM0433 Debug infrastructure 60.6.3 Cortex-M7 instrumentation trace macrocell (ITM) The ITM generates trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1. Software trace Software can write directly to any of 32 x 32-bit ITM stimulus registers to generate packets. The permission level for each port can be programmed. When software writes to an enabled stimulus port, the ITM combines the identity of the port, the size of the write access, and the data written, into a packet that it writes to a FIFO. The ITM outputs packets from the FIFO onto the trace bus. Reading a stimulus port register returns the status of the stimulus register (empty or pending) in bit 0. 2. Hardware trace The DWT generates trace packets in response to a data trace event, a PC sample or a performance profiling counter wraparound. The ITM outputs these packets on the trace bus. 3. Local timestamping The ITM contains a 21-bit counter clocked by the (pre-divided) processor clock. The counter value is output in a timestamp packet on the trace bus. The counter is reset to zero every time a timestamp packet is generated. The timestamps thus indicate the time elapsed since the previous timestamp packet. 4. Global system timestamping Timestamps can also be generated using the system-wide 64-bit count value coming from the Timestamp Generator component. Cortex-M7 ITM registers ITM stimulus register x (M7_ITM_STIMx) Address offset: 0x000 + x * 0x4 (x = 0 to 31) Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 STIMULUS[31:15] rw 15 14 13 12 11 10 9 8 7 STIMULUS[15:0] rw Bits 31:0 STIMULUS[31:0]: Software event packet / FIFOREADY Write data is output on the trace bus as a software event packet. When reading, bit 0 is a FIFOREADY indicator: 0: Stimulus port buffer is full (or port is disabled) 1: Stimulus port can accept new write data DocID029587 Rev 3 3103/3178 3152 Debug infrastructure RM0433 ITM trace enable register (M7_ITM_TER) Address offset: 0x080 Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 STIMENA[31:15] rw 15 14 13 12 11 10 9 8 7 STIMENA[15:0] rw Bits 31:0 STIMENA[31:0]: Stimulus port enable Each bit n (0:31) enables the stimulus port associated with the M7_ITM_STIMn register. 0: Port disabled 1: Port enabled ITM trace privilege registers (M7_ITM_TPR) Address offset: 0xE00 Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PRIVMASK[31:15] rw 15 14 13 12 11 10 9 8 7 PRIVMASK[15:0] rw Bits 31:0 PRIVMASK[31:0]: Enable unprivileged access to ITM stimulus ports Each bit controls eight stimulus ports: 0bXXX0: Unprivileged access permitted on ports 0 to 7 0bXXX1: Only privileged access permitted on ports 0 to 7 0bXX0X: Unprivileged access permitted on ports 8 to 15 0bXX1X: Only privileged access permitted on ports 8 to 15 0bX0XX: Unprivileged access permitted on ports 16 to 23 0bX1XX: Only privileged access permitted on ports 16 to 23 0b0XXX: Unprivileged access permitted on ports 24 to 31 0b1XXX: Only privileged access permitted on ports 24 to 31 ITM trace control register (M7_ITM_TCR) Address offset: 0xE80 Reset value: 0x0000 0000 3104/3178 DocID029587 Rev 3 RM0433 Debug infrastructure 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. BUSY TRACEBUSID[6:0] rw rw 15 14 13 12 Res. Res. Res. Res. 11 10 9 8 GTSFREQ[1:0] TSPRESCALE [1:0] rw rw 22 21 7 6 5 Res. Res. Res. 20 4 19 3 SWOE TXENA NA r rw 18 17 16 2 1 0 SYNC ENA TSENA ITM ENA rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 BUSY: ITM busy Indicates whether the ITM is currently processing events (read-only): 0: Not busy 1: Busy Bits 22:16 TRACEBUSID[6:0]: Identifier for multi-source trace stream formatting If multi-source trace is in use, the debugger must write a non-zero value to this field. Note: different IDs must be used for each trace source in the system. Bits 15:12 Reserved, must be kept at reset value. Bits 11:10 GTSFREQ[1:0]: Global timestamp frequency Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps. The possible values are: 0x0: Disable generation of global timestamps 0x1: Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [63:7]; this is approximately every 128 cycles 0x2: Generate timestamp request whenever the ITM detects a change in global timestamp counter bits [63:13]; this is approximately every 8192 cycles 0x3: Generate a timestamp after every packet, if the output FIFO is empty Bits 9:8 TSPRESCALE[1:0]: Local timestamp prescale Prescale used with the trace packet reference clock The possible values are: 0x0: No prescaling 0x1: Divide by 4 0x2: Divide by 16 0x3: Divide by 64 Bit 7:5 Reserved, must be kept at reset value. Bit 4 SWOENA: Asynchronous clocking enable for the timestamp counter (read-only) 0: Timestamp counter uses processor clock Bit 3 TXENA: Hardware event packet forwarding enable Enables forwarding of hardware event packets from the DWT unit to the trace port. 0: Disabled 1: Enabled DocID029587 Rev 3 3105/3178 3152 Debug infrastructure RM0433 Bit 2 SYNCENA: Synchronization packet transmission enable If a debugger sets this bit it must also configure the DWT_CTRL register SYNCTAP field in the DWT for the correct synchronization speed. 0: Disabled 1: Enabled Bit 1 TSENA: Local timestamp generation enable 0: Disabled 1: Enabled Bit 0 ITMENA: ITM enable 0: Disabled 1: Enabled ITM CoreSight peripheral identity register 4 (M7_ITM_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code ITM CoreSight peripheral identity register 0 (M7_ITM_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r 3106/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x01: ITM part number ITM CoreSight peripheral identity register 1 (M7_ITM_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x1: ITM part number ITM CoreSight peripheral identity register 2 (M7_ITM_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 003B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x3: r0p4 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code DocID029587 Rev 3 3107/3178 3152 Debug infrastructure RM0433 ITM CoreSight peripheral identity register 3 (M7_ITM_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications ITM CoreSight component identity register 0 (M7_ITM_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value 3108/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ITM CoreSight component identity register 1 (M7_ITM_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 00E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0xE: Trace generator component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value ITM CoreSight component identity register 2 (M7_ITM_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value DocID029587 Rev 3 3109/3178 3152 Debug infrastructure RM0433 ITM CoreSight component identity register 3 (M7_ITM_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value Cortex-M7 ITM register map and reset values The ITM registers are located at address range 0xE0000000 to 0xE0000FFC, on the AHBD. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 584. Cortex-M7 ITM register map and reset values 0x000 to M7_ITM_STIM0-31 0x07C Reset value STIMULUS[31:0] M7_ITM_TER 0x0E00 STIMENA[31:0] PRIVMASK [3:0] 0 0 0 SYNCENA TSENA ITMENA Res. 0 0 0 0 JEP106CON [3:0] 0 0 Res. 1 Res. 0 Res. 0 Res. 0 0 TXENA SWOENA Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0xFD4 0 4KCOUNT [3:0] Res. Res. 0 Reset value M7_ITM_PIDR5 Res. TSPRESCALE [1:0] Res. GTSFREQ [1:0] 0 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. TRACEBUSID[6:0] Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_PIDR4 Res. 0xFD0 0 Res. Reset value BUSY Res. Res. Res. Res. Res. Res. M7_ITM_TCR Res. 0xE80 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_TPR 0x0E40 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_PIDR6 Res. 0xFD8 Res. Reset value Reset value 0xFDC M7_ITM_PIDR7 Reset value 3110/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_PIDR2 Res. 0xFE8 1 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_CIDR1 Res. Reset value 0xFF4 Reset value 60.6.4 0 0 0 0 1 0 0 1 PARTNUM [11:8] 1 0 1 1 0 0 0 JEP106ID [6:4] 0 1 1 0 0 0 0 0 0 0 1 PREAMBLE[7:0] 0 0 1 1 CLASS[3:0] PREAMBLE [11:8] 0 0 1 1 1 0 0 0 PREAMBLE[19:12] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xFFC 1 0 0 0 Res. Reset value M7_ITM_CIDR3 0 REVAND[3:0] CMOD[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_CIDR2 Res. Reset value 0xFF8 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_CIDR0 Res. 0xFF0 Res. Reset value 0 REVISION [3:0] 0 Res. Reset value 0 JEP106ID [3:0] JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_PIDR1 0 Res. Reset value 0xFE4 PARTNUM [7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ITM_PIDR0 Res. 0xFE0 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 584. Cortex-M7 ITM register map and reset values (continued) 0 0 0 0 1 0 1 PREAMBLE[27:20] 1 0 1 1 0 0 0 1 Cortex-M7 breakpoint unit (FPB) The FPB allows hardware breakpoints to be set. It contains eight comparators which monitor the instruction fetch address and return a breakpoint instruction when a match is detected.The Cortex-M7 FPB does not support flash patch functionality. Cortex-M7 FPB registers FPB control register (M7_FPB_CTRL) Address offset: 0x000 Reset value: 0x0000 0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. KEY ENABL E rw rw Res. NUM_CODE[6:4] NUM_LIT[3:0] NUM_CODE[3:0] r r r DocID029587 Rev 3 3111/3178 3152 Debug infrastructure RM0433 Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 NUM_CODE[6:4]: Instruction address comparator number field, three MSBs This read-only field holds the three MSBs of the number of instruction address comparators supported. 0x0: the MSBs of the number are all 0 Bits 11:8 NUM_LIT[3:0]: Number of literal address comparators supported (read-only). 0x0: No literal comparators supported. Bits 7:4 NUM_CODE[3:0]: Instruction address comparator number field, four LSBs This read-only field holds the four LSBs of the number of instruction address comparators supported. 0x8: 8 instruction comparators supported Bit 1 KEY: Write protect key A write to M7_FPB_CTRL register will be ignored if this bit is not set to 1. Bits 0 ENABLE: FPB enable 0: Disable 1: Enable FPB remap register (M7_FPB_REMAP) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 Res. Res. RMPS PT REMAP[23:11] r rw 15 14 13 28 12 27 11 26 10 25 9 24 8 23 22 7 6 REMAP[10:0] rw Bits 31:8 Reserved, must be kept at reset value. Bit 29 RMPSPT: Flash patch remap support (read-only) 0: Remapping not supported Bits 28:5 REMAP[23:0]: Reserved - not supported Bits 4:0 Reserved, must be kept at reset value. 3112/3178 DocID029587 Rev 3 21 20 19 18 17 16 5 4 3 2 1 0 Res. Res. Res. Res. Res. RM0433 Debug infrastructure FPB comparator registers (M7_FPB_COMPx) Address offset: 0x008 + x * 0x4 (for x = 0 to 7) Reset value: 0x0000 0000 31 30 REPLACE[1:0] 29 28 27 26 25 24 23 Res. 21 20 19 18 17 16 5 4 3 2 1 0 Res. ENABL E COMP[26:14] rw 15 22 rw 14 13 12 11 10 9 8 7 6 COMP[13:0] rw rw Bits 31:30 REPLACE[1:0]: Behavior upon COMP versus instruction fetch address match Defines the behavior when a match occurs between the COMP field and the instruction fetch address: 0x0: Reserved 0x1: Breakpoint on lower half-word, upper half-word is unaffected. 0x2: Breakpoint on upper half-word, lower half-word is unaffected. 0x3: Breakpoint on both upper and lower half-words. Bit 29 Reserved, must be kept at reset value. Bits 28:2 COMP[26:0]: Value to compare with code memory access address Value to compare with address bits 28:2 of accesses to instruction code memory (0x00000000 to 0x1FFFFFFF). If a match occurs, the action to take is defined by the REPLACE field. Bit 1 Reserved, must be kept at reset value. Bit 0 ENABLE: Comparator enable The comparator is only enabled if both this bit and the FPB ENABLE bit in the M7_FPB_CTRL register are set. 0: Disabled 1: Enabled FPB CoreSight peripheral identity register 4 (M7_FPB_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r DocID029587 Rev 3 3113/3178 3152 Debug infrastructure RM0433 Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code FPB CoreSight peripheral identity register 0 (M7_FPB_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 000C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, bits [7:0] 0x0C: FPB part number FPB CoreSight peripheral identity register 1 (M7_FPB_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x0: FPB part number 3114/3178 DocID029587 Rev 3 RM0433 Debug infrastructure FPB CoreSight peripheral identity register 2 (M7_FPB_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 002B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x2: r0p3 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code FPB CoreSight peripheral identity register 3 (M7_FPB_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications DocID029587 Rev 3 3115/3178 3152 Debug infrastructure RM0433 FPB CoreSight component identity register 0 (M7_FPB_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value FPB CoreSight component identity register 1 (M7_FPB_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 00E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0xE: Trace generator component Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value 3116/3178 DocID029587 Rev 3 RM0433 Debug infrastructure FPB CoreSight component identity register 2 (M7_FPB_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value FPB CoreSight component identity register 3 (M7_FPB_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value Cortex-M7 FPB register map and reset values The Cortex-M7 FPB registers are located at address range 0xE0002000 to 0xE0002FFC. DocID029587 Rev 3 0 0 0 0 1 0 0 0 Res. Res. NUM_CODE [3:0] 0 KEY 0 NUM_LIT [3:0] NUM_CODE [6:4] 0 ENABLE Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_FPB_CTRL Res. 0x000 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 585. Cortex-M7 FPB register map and reset values 0 0 3117/3178 3152 0xFFC M7_FPB_CIDR3 3118/3178 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 1 Reset value 0 Reset value 0 Reset value 0 Reset value Reset value 0 1 0 0 0 0 0 CLASS[3:0] PREAMBLE [11:8] 1 0 1 0 0 Reset value 0 1 1 0 0 1 0 1 0 JEP106ID [3:0] 0 1 REVISION [3:0] 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 Res. Res. Res. Res. Res. Res. ENABLE 0 Res. COMP[26:0] Res. 0 Res. 4KCOUNT [3:0] Res. 0 Res. 0 0 Res. Reset value 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RMPSPT Res. Res. REMAP[23:0] JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REPLACE [1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Reset value 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. M7_FPB_CIDR2 0 Res. 0xFF8 M7_FPB_CIDR1 Res. 0xFF4 M7_FPB_CIDR0 Res. 0xFF0 M7_FPB_PIDR3 0 Res. 0xFEC M7_FPB_PIDR2 Res. Reset value Res. 0xFE8 M7_FPB_PIDR1 Res. 0xFE4 M7_FPB_PIDR0 Res. 0xFE0 M7_FPB_PIDR7 Res. 0xFDC M7_FPB_PIDR6 Res. 0xFD8 M7_FPB_PIDR5 Res. 0xFD4 M7_FPB_PIDR4 Res. 0x008 to M7_FPB_COMP0-7 0x024 Res. 0xFD0 M7_FPB_REMAP Res. 0x004 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Table 585. Cortex-M7 FPB register map and reset values (continued) JEP106CON [3:0] 0 0 Reset value PARTNUM [7:0] PARTNUM [11:8] 0 JEP106ID [6:4] 1 REVAND[3:0] CMOD[3:0] PREAMBLE[7:0] 0 0 0 1 PREAMBLE[19:12] 0 1 PREAMBLE[27:20] 1 RM0433 Debug infrastructure 60.6.5 Cortex-M7 embedded trace macrocell (ETM) The Cortex-M7 ETM is a CoreSight™ component closely coupled to the CPU. The ETM generates trace packets that allow the execution of the Cortex-M7 core to be traced. In the STM32H7, the ETM is configured for instruction trace only, so data accesses are not included in the trace information. The ETM receives information from the CPU over the processor trace interface, including: • The number of instructions executed in the same cycle • Changes in program flow • The current processor instruction state • The addresses of memory locations accessed by load and store instructions • The type, direction and size of a transfer • Condition code information • Exception information • Wait for interrupt state information For more information, refer to the ARM® CoreSight™ ETM™-M7 technical reference manual [6]. Cortex-M7 ETM registers ETM programming control register (M7_ETM_PRGCTL) Address offset: 0x004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EN rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 EN: Trace program enable 0: Trace unit is disabled 1: Trace unit is enabled DocID029587 Rev 3 3119/3178 3152 Debug infrastructure RM0433 ETM processor select control register (M7_ETM_PROCSEL) Address offset: 0x008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PROC SEL rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 PROCSEL: Processor select This field has no effect since only the Cortex-M7 uses this ETM. ETM status register (M7_ETM_STAT) Address offset: 0x00C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PMSTA BLE IDLE r r Bits 31:2 Reserved, must be kept at reset value. Bit 1 PMSTABLE: Programmers model stable Indicates whether the ETM registers are stable and can be read. 0: Registers are not stable 1: Registers are stable Bit 0 IDLE: Trace unit inactive 0: ETM is not idle 1: ETM is idle 3120/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM trace configuration register (M7_ETM_CONFIG) Address offset: 0x010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DV DA rw rw 1 0 15 14 13 12 11 10 9 8 Res. Res. Res. RS TS COND[2:0] rw rw rw 7 6 5 4 3 2 Res. Res. Res. CCI BB INSTP0[1:0] rw rw r Res. Bits 31:18 Reserved, must be kept at reset value. Bit 17 DV: Data value tracing (read-only) 0: Disabled Bit 16 DA: Data address tracing (read-only) 0: Disabled Bits 15:13 Reserved, must be kept at reset value. Bit 12 RS: Return stack enable 0: Disabled 1: Enabled Bit 11 TS: Global timestamp tracing 0: Disabled 1: Enabled Bits 10:8 COND[2:0]: Conditional instruction tracing 0x0: Conditional instruction tracing disabled 0x1: Conditional load instructions are traced 0x2: Conditional store instructions are traced 0x3: Conditional load and store instructions are traced 0x7: All conditional instructions are traced Other: Reserved Bits 7:5 Reserved, must be kept at reset value. Bit 4 CCI: Cycle counting in instruction trace 0: Disabled 1: Enabled Bit 3 BB: Branch broadcast mode 0: Disabled 1: Enabled Bits 2:1 INSTP0[1:0]: Determines which instructions are P0 instructions (read-only) 0x0: Only branches are P0 instructions Bit 0 Reserved, must be kept at reset value. DocID029587 Rev 3 3121/3178 3152 Debug infrastructure RM0433 ETM event control 0 register (M7_ETM_EVENTCTL0) Only accepts writes when trace unit is disabled Address offset: 0x020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 SEL1[3:0] TYPE0 Res. Res. Res. rw rw 15 14 13 12 TYPE1 Res. Res. Res. rw SEL0[3:0] rw Bits 31:16 Reserved, must be kept at reset value. Bit 15 TYPE1: Resource type for event 1 0: Single selected resource 1: Boolean combined resource pair Bits 14:12 Reserved, must be kept at reset value. Bits 11:8 SEL1[3:0]: Resource / Boolean combined resource pair, for event 1 When TYPE1 is 0, selects a single selected resource from 0-15 defined by bits[3:0] When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0] Bit 7 TYPE0: Resource type for event 0 0: Single selected resource 1: Boolean combined resource pair Bits 6:4 Reserved, must be kept at reset value. Bits 3:0 SEL0[3:0]: Resource / Boolean combined resource pair for event 0 When TYPE0 is 0, selects a single selected resource from 0-15 defined by bits[3:0] When TYPE0 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0] ETM event control 1 register (M7_ETM_EVENTCTL1) Only accepts writes when trace unit is disabled Address offset: 0x024 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. LPOVE RRIDE ATB Res. Res. Res. Res. Res. Res. Res. rw rw 3122/3178 INSTEN[3:0] rw DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:13 Reserved, must be kept at reset value. Bit 12 LPOVERRIDE: Low power state behavior override 0: Low power state normal behavior 1: Entry to low power state does not affect resources and event trace generation Bit 11 ATB: ATB trigger enable 0: Disabled 1: Enabled Bits 10:4 Reserved, must be kept at reset value. Bits 3:0 INSTEN[3:0]: Instruction trace event element enable Each bit corresponds to an event: 0bXXX0: Event 0 does not cause an event element 0bXXX1: Event 0 causes an event element 0bXX0X: Event 1 does not cause an event element 0bXX1X: Event 1 causes an event element 0bX0XX: Event 2 does not cause an event element 0bX1XX: Event 2 causes an event element 0b0XXX: Event 3 does not cause an event element 0b1XXX: Event 3 causes an event element ETM stall control register (M7_ETM_STALLCTL) Only accepts writes when trace unit is disabled Address offset: 0x02C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DSTAL ISTALL L rw rw LEVEL[1:0] rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 DSTALL: Stall processor based on data trace buffer space 0: Do not stall processor 1: Stall processor Bit 8 ISTALL: Stall processor based on instruction trace buffer space 0: Do not stall processor 1: Stall processor DocID029587 Rev 3 3123/3178 3152 Debug infrastructure RM0433 Bits 7:4 Reserved, must be kept at reset value. Bits 3:2 LEVEL[1:0]: Stalling threshold level A low level minimizes the amount of processor stalling, with a higher risk of FIFO overflow. A high level minimizes the risk of FIFO overflow but increases the amount of processor stalling. Bits 1:0 Reserved, must be kept at reset value. ETM global timestamp control register (M7_ETM_TSCTL) Only accepts writes when trace unit is disabled Address offset: 0x030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. TYPE Res. Res. Res. SEL[1:0] rw rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 TYPE: Resource type for time stamp insertion 0: Single selected resource 1: Boolean combined resource pair Bits 6:4 Reserved, must be kept at reset value. Bits 3:0 SEL[3:0]: Resource / Boolean combined resource pair When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0] When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0] ETM synchronization period register (M7_ETM_SYNCP) Address offset: 0x034 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PERIOD[4:0] r Bits 31:5 Reserved, must be kept at reset value. Bits 4:0 PERIOD[4:0]: Trace bytes between synchronization requests Defines the number of bytes of trace information between trace synchronization requests. 0xA: 1024 bytes 3124/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM cycle count control register (M7_ETM_CCCTL) Address offset: 0x038 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. PERIOD[11:0] rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 THRESHOLD[11:0]: Threshold value for instruction trace cycle counting The threshold represents the minimum interval between cycle count trace packets. 0x0: Reserved Other: Threshold ETM trace ID register (M7_ETM_TRACEID) Address offset: 0x040 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. TRACEID[6:0] rw Bits 31:7 Reserved, must be kept at reset value. Bits 6:0 TRACEID[6:0]: Trace ID 0x00: Reserved 0x01 to 0x6F: Valid ID 0x70 to 0x7F: Reserved DocID029587 Rev 3 3125/3178 3152 Debug infrastructure RM0433 ETM ViewInst main control register (M7_ETM_VICTL) Address offset: 0x080 Reset value: 0x0000 0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 Res. Res. 23 Res. 22 Res. 21 Res. 20 19 Res. EXLEV EL_S3 18 Res. 17 16 Res. EXLEV EL_S0 rw 15 Res. 14 Res. 13 Res. 6 5 4 3 rw 12 11 10 9 8 7 Res. TRCE RR TRCR ESET SSSTA TUS 2 1 Res. TYPE SEL[3:0] rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bit 19 EXLEVEL_S3: Trace disable, exception level 3 Disables tracing in the specified exception level in Secure state for exception level 3. 0: Enable ViewInst in this exception level 1: Disable ViewInst in this exception level Bits 18:17 Reserved, must be kept at reset value. Bit 16 EXLEVEL_S0: Trace disable, exception level 0 Disables tracing in the specified exception level in Secure state for exception level 0. 0: Enable ViewInst in this exception level 1: Disable ViewInst in this exception level Bits 15:12 Reserved, must be kept at reset value. Bit 11 TRCERR: Tracing of system error exception Selects whether a system error exception must always be traced. 0: System error exception is traced only if the instruction or exception immediately before the system error exception is traced 1: System error exception is always traced regardless of the value of ViewInst Bit 10 TRCRESET: Tracing of reset exception Selects whether a reset exception must always be traced. 0: Reset exception is traced only if the instruction or exception immediately before the reset exception is traced 1: Reset exception is always traced regardless of the value of ViewInst Bit 9 SSSTATUS: Current status of the start/stop logic 0: Stop state 1: Started state Bit 8 Reserved, must be kept at reset value. 3126/3178 DocID029587 Rev 3 0 RM0433 Debug infrastructure Bit 7 TYPE: Resource type 0: Single selected resource 1: Boolean combined resource pair Bits 6:14 Reserved, must be kept at reset value. Bits 3:0 SEL[3:0]: Resource / Boolean combined resource pair When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0] When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0] ETM ViewInst start/stop control register (M7_ETM_VISSCTL) Address offset: 0x088 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 2 1 0 STOP[7:0] rw 7 6 5 4 3 START[7:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 STOP[7:0]: Selector of single address comparators to stop trace Defines the single address comparators to stop trace with the ViewInst Start/Stop control. One bit is provided for each implemented single address comparator. Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 START[7:0]: Selector of single address comparators to start trace Defines the single address comparators to start trace with the ViewInst Start/Stop control. One bit is provided for each implemented single address comparator. ETM ViewInst start/stop processor comparator control register (M7_ETM_VIPCSSCTL) Address offset: 0x08C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19 18 17 16 STOP[3:0] rw 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 0 START[3:0] rw DocID029587 Rev 3 3127/3178 3152 Debug infrastructure RM0433 Bits 31:20 Reserved, must be kept at reset value. Bits 19:16 STOP[3:0]: Selector of processor comparator input to stop trace Selects which processor comparator inputs are in use with ViewInst start-stop control, for the purpose of stopping trace. One bit is provided for each processor comparator input. Bits 15:4 Reserved, must be kept at reset value. Bits 3:0 START[3:0]: Selector of processor comparator input to start trace Selects which processor comparator inputs are in use with ViewInst start-stop control, for the purpose of starting trace. One bit is provided for each processor comparator input. ETM counter reload value register (M7_ETM_CNTRLDV) Address offset: 0x140 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 VALUE[15:0]: Counter reload value This value is loaded into the counter each time the reload event occurs. ETM ID register 8 (M7_ETM_IDR8) Address offset: 0x180 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 MAXSPEC[31:16] r 15 14 13 12 11 10 9 8 7 MAXSPEC[15:0] r Bits 31:0 MAXSPEC[31:0]: Maximum speculation depth Indicates the maximum speculation depth of the instruction trace stream. This is the maximum number of P0 elements that have not been committed in the trace stream at any one time. 0x2: Maximum trace speculation depth is 2 3128/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM ID register 9 (M7_ETM_IDR9) Address offset: 0x184 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 NUMP0KEY[31:16] r 15 14 13 12 11 10 9 8 7 NUMP0KEY[15:0] r Bits 31:0 NUMP0KEY[31:0]: Number of P0 right-hand keys used 0x0: No P0 keys used in instruction trace only configuration ETM ID register 10 (M7_ETM_IDR10) Address offset: 0x188 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 NUMP1KEY[31:16] r 15 14 13 12 11 10 9 8 7 NUMP1KEY[15:0] r Bits 31:0 NUMP1KEY[31:0]: Total number of P1 right-hand keys Indicates the total number of P1 right-hand keys, including normal and special keys. 0x0: No P1 keys used in instruction trace only configuration ETM ID register 11 (M7_ETM_IDR11) Address offset: 0x18C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 NUMP1SPC[31:16] r 15 14 13 12 11 10 9 8 7 NUMP1SPC[15:0] r Bits 31:0 NUMP1SPC[31:0]: Total number of special P1 right-hand keys used 0x0: No special P1 keys used DocID029587 Rev 3 3129/3178 3152 Debug infrastructure RM0433 ETM ID register 12 (M7_ETM_IDR12) Address offset: 0x190 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 NUMCONDKEY[31:16] r 15 14 13 12 11 10 9 8 7 6 NUMCONDKEY[15:0] r Bits 31:0 NUMCONDKEY[31:0]: Indicates the total number of conditional instruction right-hand keys, including normal and special keys. 0x1: One conditional instruction right hand-key implemented ETM ID register 13 (M7_ETM_IDR13) Address offset: 0x194 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 NUMCONDSPC[31:16] r 15 14 13 12 11 10 9 8 7 6 NUMCONDSPC[15:0] r Bits 31:0 NUMCONDSPC[31:0]: Number of special conditional instruction right-hand keys 0x0: No special conditional instruction right hand-keys implemented ETM implementation specific register 0 (M7_ETM_IMSPEC0) Address offset: 0x1C0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUPPORT[3:0] r 3130/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 SUPPORT[3:0]: Support for implementation specific extensions 0x0: No implementation specific extensions are supported ETM ID register 0 (M7_ETM_IDR0) Address offset: 0x1E0 Reset value: 0x0C00 1EE1 31 Res. 15 QSUP P[0] r 30 29 Res. COMM OPT TSSIZE[4:0] r r 14 Res. 28 13 12 27 26 11 10 25 24 Res. r 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. QSUPP [1] r 9 8 CONDTYPE[1:0 NUMEVENT[1:0 RETST ] ] ACK r 23 Res. 7 6 5 TRCCC TRCCO TRCBB I ND r r r 4 3 2 1 0 Res. Res. Res. Res. Res. r Bits 31:30 Reserved, must be kept at reset value. Bit 29 COMMOPT: Meaning of the commit field in some packets 0: Commit mode 0 Bits 28:24 TSSIZE[4:0]: Global timestamp size 0x08: Maximum of 64-bit global timestamp implemented Bits 23:17 Reserved, must be kept at reset value. Bits 16:15 QSUPP[1:0]: Q element support 0x0: Q elements not supported Bit 14 Reserved, must be kept at reset value. Bits 13:12 CONDTYPE[1:0]: Way of conditional result tracing 0x1: APSR condition flag values traced Bits 11:10 NUMEVENT[1:0]: Number of events supported in the trace 0x1: Two events supported for instruction only configuration Bit 9 RETSTACK: Return stack support 1: Two entry return stack supported Bit 8 Reserved, must be kept at reset value. Bit 7 TRCCCI: Support for cycle counting in the instruction trace 1: Cycle counting in the instruction trace is implemented Bit 6 TRCCOND: Support for conditional instruction tracing 1: Conditional instruction trace is implemented Bit 5 TRCBB: Support for branch broadcast tracing 1: Branch broadcast trace is implemented Bits 4:0 Reserved, must be kept at reset value. DocID029587 Rev 3 3131/3178 3152 Debug infrastructure RM0433 ETM ID register 1 (M7_ETM_IDR1) Address offset: 0x1E4 Reset value: 0x4100 F401 31 30 29 28 27 26 25 24 DESIGNER[7:0] 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 r 15 14 13 12 Res. Res. Res. Res. 11 10 9 8 TRCARCHMAJ[3:0] TRCARCHMIN[3:0] REVISION[3:0] r r r Bits 31:24 DESIGNER[7:0]: Trace unit designer entity 0x41: ARM® Bits 23:12 Reserved, must be kept at reset value. Bits 11:8 TRCARCHMAJ[3:0]: Major trace unit architecture version number 0x4: ETM v4 Bits 7:4 TRCARCHMIN[3:0]: Minor trace unit architecture version number 0x0: Minor version 0 Bits 3:0 REVISION[3:0]: Implementation revision number 0x1: Rev 1 ETM ID register 2 (M7_ETM_IDR2) Address offset: 0x1E8 Reset value: 0x0000 0004 31 30 29 Res. Res. Res. 15 14 13 28 27 26 25 24 23 22 21 20 19 18 17 CCSIZE[3:0] DVSIZE[4:0] DASIZE[4:1] r r r 12 11 10 9 8 7 6 5 4 3 2 DASIZ E[0] VMIDSIZE[4:0] CIDSIZE[4:0] IASIZE[4:0] r r r r Bits 31:29 Reserved, must be kept at reset value. Bits 28:25 CCSIZE[3:0]: Cycle counter size Indicates the size of the cycle counter in bits minus 12. 0x0: Cycle counter is 12 bits Bits 24:20 DVSIZE[4:0]: Data value size in bytes 0x0: Data value size is not supported in instruction only configuration Bits 19:15 DASIZE[4:0]: Data address size in bytes 0x0: Data address size is not supported in instruction only configuration 3132/3178 DocID029587 Rev 3 1 16 0 RM0433 Debug infrastructure Bits 14:10 VMIDSIZE[4:0]: Virtual machine ID size 0x0: Virtual machine ID tracing not implemented Bits 9:5 CIDSIZE[4:0]: Context ID size 0x0: Context ID tracing not implemented Bits 4:0 IASIZE[4:0]: Instruction address size 0x4: 32-bit maximum address size ETM ID register 3 (M7_ETM_IDR3) Address offset: 0x1EC Reset value: 0x0509 0004 31 30 29 28 NOOV ERFLO W NUMPROC[2:0] r r 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 SYSST STALL SYNCP TRCER ALL CTL R R r r r r 11 10 9 8 23 22 21 20 Res. Res. Res. Res. 19 18 17 16 EXLEVEL_S[3:0] r 7 6 5 4 3 2 1 0 CCITMIN[11:0] r Bit 31 NOOVERFLOW: Support of NOOVERFLOW Indicates whether the NOOVERFLOW of trace stall control is implemented. 0: Not implemented Bits 30:28 NUMPROC[2:0]: Number of processors available for tracing 0x0: Only one processor can be traced Bit 27 SYSSTALL: System support for stall control of the processor 0: Not supported Bit 26 STALLCTL: Stall control support 1: Trace stall control (TRCSTALLCTLR) is implemented Bit 25 SYNCPR: Trace synchronization period support 0: TRCSYNCPR is read-only for instruction trace only configuration; the trace synchronization period is fixed Bit 24 TRCERR: Support of TRCVICTLR.TRCERR Indicates whether TRCVICTLR.TRCERR is implemented. 0x4: 32-bit maximum address size Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 EXLEVEL_S[3:0]: Support of privilege levels Privilege levels are implemented; one bit for each level. 0x9: Privilege levels Thread and Handler are implemented Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 CCITMIN[11:0]: Instruction trace cycle counting minimum threshold 0x4: Minimum threshold is 4 instruction trace cycle DocID029587 Rev 3 3133/3178 3152 Debug infrastructure RM0433 ETM ID register 4 (M7_ETM_IDR4) Address offset: 0x1F0 Reset value: 0x0001 4000 31 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NUMVMIDC[3:0] NUMCIDC[3:0] NUMSSCC[3:0] NUMRSPAIR[3:0] r r r r 14 13 12 NUMPC[3:0] 11 Res. 10 Res. 9 8 Res. SUPPA DC NUMDVC[3:0] NUMACPAIRS[3:0] r r r r 7 6 5 4 3 2 1 16 0 Bits 31:28 NUMVMIDC[3:0]: Number of Virtual Machine ID comparators implemented 0x0: None Bits 27:24 NUMCIDC[3:0]: Number of Context ID comparators implemented 0x0: None Bits 23:20 NUMSSCC[3:0]: Number of single-shot comparator controls implemented 0x0: None Bits 19:16 NUMRSPAIR[3:0]: Number of resource selection pairs implemented 0x1: None Bits 15:12 NUMPC[3:0]: Number of processor comparator inputs implemented 0x4: Four Bits 11:9 Reserved, must be kept at reset value. Bit 8 SUPPADC: Support of data address comparisons 0: Not implemented Bits 7:4 NUMDVC[3:0]: Number of data value comparators implemented 0x0: None Bits 3:0 NUMACPAIRS[3:0]: Number of address comparator pairs implemented. 0x0: None ETM ID register 5 (M7_ETM_IDR5) Address offset: 0x1F4 Reset value: 0x90C7 0402 31 30 29 28 27 26 25 REDF UNCN TR NUMCNTR[2:0] NUMSEQSTATE[2:0] r r r 15 14 13 12 Res. Res. Res. Res. 3134/3178 11 10 9 24 Res. 8 23 22 21 20 LPOVE ATBTRI RRIDE G r r 7 6 19 17 16 1 0 TRACEIDSIZE[5:0] r 5 4 NUMEXTINSEL[2:0] NUMEXTIN[8:0] r r DocID029587 Rev 3 18 3 2 RM0433 Debug infrastructure Bit 31 REDFUNCNTR: Support of reduced function counter 1: Implemented Bits 30:28 NUMCNTR[2:0]: Number of counters implemented 0x1: One counter implemented Bits 27:25 NUMSEQSTATE[2:0]: Number of sequencer states implemented 0x0: None Bit 24 Reserved, must be kept at reset value. Bit 23 LPOVERRIDE: Support of low-power state override 1: Implemented Bit 22 ATBTRIG: Support of ATB trigger 1: Implemented Bits 21:16 TRACEIDSIZE[5:0]: Number of bits of trace ID 0x07: Seven-bit trace ID implemented. Bits 15:12 Reserved, must be kept at reset value. Bits 11:9 NUMEXTINSEL[2:0]: Number of external input selectors implemented 0x2: Two external input selectors implemented Bits 8:0 NUMEXTIN[8:0]: Number of external inputs implemented 0x2: Two external inputs implemented ETM resource selection register 2 (M7_ETM_RSCTL2) Address offset: 0x208 Reset value: 0x0000 0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 Res. 7 22 21 20 19 Res. PAIRIN V INV Res. rw rw 5 4 6 18 17 16 GROUP[2:0] rw 3 2 1 0 SELECT[7:0] rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 PAIRINV: Inversion of result of a combined pair of resources 0: Not inverted 1: Inverted Bit 20 INV: Inversion of the selected resources 0: Not inverted 1: Inverted Bit 19 Reserved, must be kept at reset value. DocID029587 Rev 3 3135/3178 3152 Debug infrastructure RM0433 Bits 18:16 GROUP[2:0]: Selects a group of resources Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 SELECT[7:0]: Selector of resources from desired group Selects one or more resources from the desired group. One bit is provided per resource from the group. ETM resource selection register 3 (M7_ETM_RSCTL3) Address offset: 0x20C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INV Res. 18 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 16 GROUP[2:0] rw 15 17 rw 4 3 2 1 0 SELECT[7:0] rw Bits 31:21 Reserved, must be kept at reset value. Bit 20 INV: Inversion of the selected resources 0: Not inverted 1: Inverted Bit 19 Reserved, must be kept at reset value. Bits 18:16 GROUP[2:0]: Selects a group of resources Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 SELECT[7:0]: Selector of resources from desired group Selects one or more resources from the desired group. One bit is provided per resource from the group. ETM single-shot comparator control register 0 (M7_ETM_SSCC0) Address offset: 0x280 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. RST Res. Res. Res. Res. Res. Res. Res. Res. rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3136/3178 DocID029587 Rev 3 RM0433 Debug infrastructure Bits 31:25 Reserved, must be kept at reset value. Bit 24 RST: Single-shot comparator resource reset enable Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected. 0: Disabled 1: Reset enabled; multiple matches can occur Bits 23:0 Reserved, must be kept at reset value. ETM single-shot comparator status register 0 (M7_ETM_SSCS0) Address offset: 0x2A0 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STATU S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DV DA INST r r r rw Bit 31 STATUS: Single-shot status This indicates whether any of the selected comparators have matched. If SSCC0.RST is set to 0, the STATUS bit must be written with 0 in order to enable single-shot comparator control. 0: No match occurred 1: Match has occurred at least once. Bits 30:3 Reserved, must be kept at reset value. Bit 2 DV: Data value comparator support 0: Single-shot data value comparisons not supported Bit 1 DA: Data address comparator support 0: Single-shot data address comparisons not supported Bit 0 INST: Instruction address comparator support 1: Single-shot instruction address comparisons supported DocID029587 Rev 3 3137/3178 3152 Debug infrastructure RM0433 ETM single-shot processor comparator input control register (M7_ETM_SSPCIC0) Address offset: 0x2C0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PC[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PC[7:0]: Comparator input selector for single-shot control Selects one or more processor comparator inputs for single-shot control. One bit is provided for each processor comparator input. ETM power-down control register (M7_ETM_PDC) Address offset: 0x2C0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU Res. Res. Res. r Bits 31:4 Reserved, must be kept at reset value. Bit 3 PU: Power up request Request to maintain power to the ETM and access to the trace registers. 0: Power not requested 1: Power requested Bits 2:0 Reserved, must be kept at reset value. 3138/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM power-down status register (M7_ETM_PDS) Address offset: 0x2C0 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. STICKY POWE PD R r r Bits 31:2 Reserved, must be kept at reset value. Bit 1 STICKYPD: Sticky power-down state This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR. 0: Trace register power uninterrupted since the last read of PDS register 1: Trace register power interrupted since the last read of PDS register Bit 0 POWER: ETM powered up 1: ETM is powered up; all registers are accessible ETM claim tag set register (M7_ETM_CLAIMSET) Address offset: 0xFA0 Reset value: 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMSET[3:0]: Set claim tag bits Write: 0000: No effect xxx1: Set bit 0 xx1x: Set bit 1 x1xx: Set bit 2 1xxx: Set bit 3 Read: 0xF: Indicates there are four bits in claim tag DocID029587 Rev 3 3139/3178 3152 Debug infrastructure RM0433 ETM claim tag clear register (M7_ETM_CLAIMCLR) Address offset: 0xFA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0] rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 CLAIMCLR[3:0]: Reset claim tag bits Write: 0000: No effect xxx1: Clear bit 0 xx1x: Clear bit 1 x1xx: Clear bit 2 1xxx: Clear bit 3 Read: Returns current value of claim tag ETM lock access register (M7_ETM_LAR) Address offset: 0xFB0 Reset value: N/A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ACCESS_W[31:16] w 15 14 13 12 11 10 9 8 7 ACCESS_W[15:0] w Bits 31:0 ACCESS_W[31:0]: ETM register write access Enables write access to some ETM registers by processor cores (debuggers do not need to unlock the component) 0xC5ACCE55: Enable write access Other values: Disable write access 3140/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM lock status register (M7_ETM_LSR) Address offset: 0xFB4 Reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LOCK TYPE LOCK GRANT LOCK EXIST r r r Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:3 Reserved, must be kept at reset value. Bit 2 LOCKTYPE: Size of the M7_ETM_LAR register 0: 32-bit Bit 1 LOCKGRANT: Current status of lock This bit always returns zero when read by an external debugger. 0: Write access is permitted 1: Write access is blocked. Only read access is permitted. Bit 0 LOCKEXIST: Existence of lock control mechanism The bit indicates whether a lock control mechanism exists. It always returns zero when read by an external debugger. 0: No lock control mechanism exists 1: Lock control mechanism is implemented ETM authentication status register (M7_ETM_AUTHSTAT) Address offset: 0xFB8 Reset value: 0x0000 000A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SNID[1:0] SID[1:0] NSNID[1:0] NSID[1:0] r r r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:6 SNID[1:0]: Security level for secure non-invasive debug 0x0: Not implemented DocID029587 Rev 3 3141/3178 3152 Debug infrastructure RM0433 Bits 5:4 SID[1:0]: Security level for secure invasive debug 0x0: Not implemented Bits 3:2 NSNID[1:0]: Security level for non-secure non-invasive debug 0x2: Disabled 0x3: Enabled Bits 1:0 NSID[1:0]: Security level for non-secure invasive debug 0x2: Disabled 0x3: Enabled ETM CoreSight device architecture register (M7_ETM_DEVARCH) Address offset: 0xFBC Reset value: 0x4770 4A13 31 15 30 14 29 13 28 12 27 26 25 24 23 22 21 20 19 18 17 ARCHITECT[10:0] PRESE NT REVISION[3:0] r r r 11 10 9 8 7 6 5 4 16 3 2 1 0 ARCHID[15:0] r Bits 31:21 ARCHITECT[10:0]: Component architect 0x23B: ARM® Bit 20 PRESENT: Indicates the presence of this register 1: Present Bits 19:16 REVISION[3:0]: Architecture revision 0x0: Rev 0 Bits 15:0 ARCHID[15:0]: Architecture ID 0x4A13: ETMv4 component ETM CoreSight device identity register (M7_ETM_DEVID) Address offset: 0xFC8 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:0 Reserved, must be kept at reset value. 3142/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM CoreSight device type identity register (M7_ETM_DEVTYPE) Address offset: 0xFCC Reset value: 0x0000 0013 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SUBTYPE[3:0] MAJORTYPE[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 SUBTYPE: Device sub-type identifier 0x1: Processor trace Bits 3:0 MAJORTYPE: Device main type identifier 0x3: Trace source ETM CoreSight peripheral identity register 4 (M7_ETM_PIDR4) Address offset: 0xFD0 Reset value: 0x0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. 4KCOUNT[3:0] JEP106CON[3:0] r r Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 4KCOUNT[3:0]: Register file size 0x0: Register file occupies a single 4 Kbyte region Bits 3:0 JEP106CON[3:0]: JEP106 continuation code 0x4: ARM® JEDEC code DocID029587 Rev 3 3143/3178 3152 Debug infrastructure RM0433 ETM CoreSight peripheral identity register 0 (M7_ETM_PIDR0) Address offset: 0xFE0 Reset value: 0x0000 0075 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PARTNUM[7:0]: Part number field, field, bits [7:0] 0x75: ETM part number ETM CoreSight peripheral identity register 1 (M7_ETM_PIDR1) Address offset: 0xFE4 Reset value: 0x0000 00B9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. JEP106ID[3:0] PARTNUM[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 JEP106ID[3:0]: JEP106 identity code field, bits [3:0] 0xB: ARM® JEDEC code Bits 3:0 PARTNUM[11:8]: Part number field, bits [11:8] 0x9: ETM part number 3144/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM CoreSight peripheral identity register 2 (M7_ETM_PIDR2) Address offset: 0xFE8 Reset value: 0x0000 002B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4] r r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVISION[3:0]: Component revision number 0x1: r0p2 Bit 3 JEDEC: JEDEC assigned value 1: Designer ID specified by JEDEC Bits 2:0 JEP106ID[6:4]: JEP106 identity code field, bits [6:4] 0x3: ARM® JEDEC code ETM CoreSight peripheral identity register 3 (M7_ETM_PIDR3) Address offset: 0xFEC Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 REVAND[3:0]: Metal fix version 0x0: No metal fix Bits 3:0 CMOD[3:0]: Customer modified 0x0: No customer modifications DocID029587 Rev 3 3145/3178 3152 Debug infrastructure RM0433 ETM CoreSight component identity register 0 (M7_ETM_CIDR0) Address offset: 0xFF0 Reset value: 0x0000 000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[7:0]: Component ID field, bits [7:0] 0x0D: Common ID value ETM CoreSight component identity register 1 (M7_ETM_CIDR1) Address offset: 0xFF4 Reset value: 0x0000 0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8] r r Bit 31:8 Reserved, must be kept at reset value. Bits 7:4 CLASS[3:0]: Component ID field, bits [15:12] - component class 0x9: Debug component with CoreSight-compatible registers Bits 3:0 PREAMBLE[11:8]: Component ID field, bits [11:8] 0x0: Common ID value 3146/3178 DocID029587 Rev 3 RM0433 Debug infrastructure ETM CoreSight component identity register 2 (M7_ETM_CIDR2) Address offset: 0xFF8 Reset value: 0x0000 0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[19:12]: Component ID field, bits [23:16] 0x05: Common ID value ETM CoreSight component identity register 3 (M7_ETM_CIDR3) Address offset: 0xFFC Reset value: 0x0000 00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20] r Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PREAMBLE[27:20]: Component ID field, bits [31:24] 0xB1: Common ID value DocID029587 Rev 3 3147/3178 3152 0x080 M7_ETM_VICTL Reset value 3148/3178 0 DocID029587 Rev 3 SSSTATUS 0 0 0 Reset value 0 Reset value 0 0 Reset value 0 0 0 0 0 0 0 0 0 Res. Res. 0 LEVEL [1:0] Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 Res. Res. 0 Reset value IDLE 0 0 0 0 Res. 0 0 PMSTABLE BB Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value INSTP0 [1:0] CCI Res. CID TYPE0 Res. VMID 0 Res. Res. Res. COND [2:0] 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. TYPE 0 Res. SEL1[3:0] Res. ISATLL 0 Res. 0 Res. 0 Res. Res. 0 Res. TS Res. Res. RS 0 Res. 0 Res. DSTALL 0 Res. Reset value Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. ATB Res. Res. LPOVERRIDE Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. DA Res. TYPE1 DV Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TYPE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. TRCRESET Reset value Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TRCERR 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. EXLEVEL_S0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. EXLEVEL_S3 Res. Res. Res. Res. Res. Res. Res. M7_ETM_TRACEID Res. M7_ETM_CCCTL Res. M7_ETM_SYNCP Res. 0x040 M7_ETM_TSCTL Res. 0x038 M7_ETM _STALLCTL Res. 0x02C Res. 0x034 M7_ETM _EVENTCTL1 Res. 0x030 M7_ETM _EVENTCTL0 Res. 0x024 M7_ETM_CONFIG Res. 0x020 M7_ETM_STAT Res. 0x010 PROCSEL [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM _PROCSEL Res. 0x008 Res. 0x00C 0 0 0 0 0 0 EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_PRGCTL Res. 0x004 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Cortex-M7 ETM register map and reset values The ETM registers are accessed by the debugger via the Cortex-M7 PPB, at address range 0xE0041000 to 0xE0041FFC. Table 586. Cortex-M7 ETM register map and reset values Reset value 0 0 1 SEL0[3:0] 0 0 INSTEN[3:0] 0 SEL[3:0] PERIOD[4:0] 0 0 0 THRESHOLD[11:0] 0 0 0 TRACEID[6:0] 0 0 0 0 SEL[3:0] 0 RM0433 Debug infrastructure 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M7_ETM_IDR10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M7_ETM_IDR11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 DocID029587 Rev 3 1 0 1 0 0 0 0 Res. Res. TRCBB 0 Res. TRCCOND Res. TRCCCI 1 1 0 0 0 0 REVISION [3:0] TRCARCHMIN [3:0] TRCARCHMAJ [3:0] 1 0 0 CIDSIZE[4:0] 0 0 0 0 0 0 0 1 IASIZE[4:0] 0 0 0 1 0 0 0 0 1 0 0 0 0 CCITMIN[11:0] 0 0 0 0 0 0 0 0 NUMACPAIRS [3:0] EXLEVEL_S [3:0] 1 0 NUMDVC [3:0] 0 Res. NUMEVENT [1:0] Res. 0 0 RETSTACK CONDTYPE [1:0] Res. Res. Res. QSUPP[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 SUPPDAC 0 0 0 1 Res. 0 NUMCIDC [3:0] M7_ETM_IDR4 0 0 0 0 VMIDSIZE[4:0] 0 1 0 1 1 Res. 1 0 1 1 Res. 0 DASIZE[4:0] 0 1 Res. 1 0 1 Res. 0 0 1 Res. 0 0 1 NUMPC [3:0] 0 0 Res. 0 TRCERR 0 SYNCPR 0 STALLCTL 0 DVSIZE[4:0] SYSSTALL 0 Res. 1 0 Res. Res. 0 NUMPROC[2:0] NOOVERFLOW Reset value 0 CCSIZE[3:0] 0 M7_ETM_IDR3 0 0 NUMRSPAIR [3:0] M7_ETM_IDR2 0 Res. 1 Res. Res. 0 Res. 0 0 Res. SUPPORT [3:0] Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 Reset value 0 Res. 0 NUMVMIDC [3:0] 0x1F0 1 NUMSSCC [3:0] Reset value Reset value 0x1EC 0 DESIGNER[7:0] Res. 0x1E8 M7_ETM_IDR1 Res. 0x1E4 0 TSSIZE[4:0] Res. Reset value COMMOPT Res. Res. M7_ETM_IDR0 0 START[3:0] Reset value 0x1E0 0 NUMCONDSPC[31:0] Res. M7_ETM_IMSPEC0 0 NUMCONDKEY[31:0] M7_ETM_IDR13 Reset value 0 NUMP1SPC[31:0] M7_ETM_IDR12 Reset value 0 Res. Reset value 0 NUMP1KEY[31:0] Res. Reset value 0 NUMP0KEY[31:0] Res. 0x1C0 0 Res. 0x194 0 Res. 0x190 0 Res. 0x18C 0 Res. 0x188 0 M7_ETM_IDR9 Reset value 0 MAXSPEC[31:0] Res. 0x184 Reset value START[7:0] VALUE[15:0] Reset value 0x180 Res. STOP[3:0] M7_ETM_IDR8 Res. Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM _CNTRLDV Res. 0x140 Res. Reset value 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x08C M7_ETM _VIPCSSCTL Res. Reset value STOP[7:0] Res. Res. Res. Res. Res. Res. M7_ETM_VISSCTL Res. 0x088 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 586. Cortex-M7 ETM register map and reset values (continued) 0 0 0 0 0 0 3149/3178 3152 0xFC8 0xFBC Reset value 3150/3178 Reset value 0 0 M7_ETM _DEVARCH 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 ARCHITECT[10:0] 1 0 1 0 0 0 M7_ETM_DEVID 0 0 0 0 DocID029587 Rev 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value KEY[31:0] Reset value 0 0 0 0 SLI Reset value SLK Reset value Reset value 0 Res. 0 POWER 0 Res. Res. Res. Res. Res. Res. DV DA INST 0 STICKYPD Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 NTT 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 0 Res. Res. 0 0 0 0 0 1 NSID [1:0] NSNID [1:0] Reset value 0 Res. Reset value SID [1:0] Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GROUP [2:0] 0 SNID [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. GROUP [2:0] 1 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 1 Res. Res. Res. Res. INV Res. NUMEXTINSEL [2:0] Res. Res. Res. Res. TRACEIDSIZE[5:0] Res. Res. M7_ETM_LAR Res. Res. Res. INV 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. ATBTRIG Res. PAIRINV 0 1 Res. Res. Res. Res. PAIRINV Res. NUMSEQSTATE [2:0] LPOVERRIDE Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. Res. Reset value RST Res. Res. Res. Res. NUMCNTR[2:0] M7_ETM_RSCTL2 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. REDFUNCNTR 1 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. STATUS Res. Res. 1 Res. Res. Res. Res. Res. Reset value REVISION [3:0] M7_ETM _AUTHSTAT Res. M7_ETM_IDR5 PRESENT 0xFB8 Res. M7_ETM_LSR Res. 0xFA4 M7_ETM _CLAIMCLR Res. M7_ETM _CLAIMSET Res. 0xFA0 Res. M7_ETM_PDS Res. M7_ETM_SSPCIC0 Res. 0xFB4 0 Res. 0xFB0 Reset value Res. 0x314 M7_ETM_PDC Res. 0x310 M7_ETM_SSCS0 Res. 0x2C0 Res. 0x2A0 M7_ETM_SSCC0 Res. 0x280 M7_ETM_RSCTL3 Res. 0x20C Res. 0x208 Res. 0x1F4 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. Debug infrastructure RM0433 Table 586. Cortex-M7 ETM register map and reset values (continued) NUMEXTIN[8:0] SELECT[7:0] SELECT[7:0] 1 0 0 0 0 0 PC[7:0] 0 0 1 0 0 0 1 1 SET[3:0] 0 0 CLR[3:0] 0 1 1 ARCHID[15:0] DEVICEID[31:0] 1 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xFFC 60.6.6 M7_ETM_CIDR3 Reset value DocID029587 Rev 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_CIDR2 Res. 0xFF8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_CIDR1 Res. 0xFF4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_CIDR0 Res. 0xFF0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_PIDR3 Res. 0xFEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_PIDR2 Res. 0xFE8 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Reset value 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value Reset value Reset value Reset value Reset value Reset value 0 4KCOUNT [3:0] 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 CLASS[3:0] PREAMBLE [11:8] 1 0 0 0 0 0 0 1 1 0 JEP106ID [3:0] 1 REVISION [3:0] 1 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 MAJORTYPE [3:0] SUBTYPE [3:0] Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM _DEVTYPE JEDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. M7_ETM_PIDR1 Res. 0xFE4 M7_ETM_PIDR0 Res. 0xFE0 M7_ETM_PIDR7 Res. 0xFDC M7_ETM_PIDR6 Res. 0xFD8 M7_ETM_PIDR5 Res. 0xFD4 M7_ETM_PIDR4 Res. 0xFD0 Res. 0xFD0 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name Res. RM0433 Debug infrastructure Table 586. Cortex-M7 ETM register map and reset values (continued) JEP106CON [3:0] 1 0 Reset value PARTNUM [7:0] PARTNUM [11:8] JEP106ID [6:4] 1 1 REVAND[3:0] CMOD[3:0] PREAMBLE[7:0] 0 0 0 1 0 PREAMBLE[19:12] 1 PREAMBLE[27:20] 1 Cortex-M7 cross trigger interface (CTI) See Section 60.5.3. 3151/3178 3152 Debug infrastructure 60.7 3152/3178 RM0433 References for debug infrastructure 1. IHI 0031C (ID080813) - ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2, Issue C 2. DDI 0480F (ID100313) - ARM® CoreSight™ SoC-400 r3p2 Technical Reference Manual, Issue G 3. DDI 0461B (ID010111) - ARM® CoreSight™ Trace Memory Controller r0p1 Technical Reference Manual, Issue B 4. DDI 0314H - ARM® CoreSight™ Components Technical Reference Manual, Issue H 5. DDI 0403D (ID100710) - ARM®v7-M Architecture Reference Manual, Issue E.b 6. DDI 0494-2a (ID062813) - ARM® CoreSight™ ETM™-M7 r0p1 Technical Reference Manual, Issue D DocID029587 Rev 3 RM0433 Device electronic signature 61 Device electronic signature The electronic signature is stored in the Flash memory area. It can be read using the JTAG/SWD or the CPU. It contains factory-programmed identification data that allow the user firmware or other external devices to automatically match its interface to the characteristics of the STM32H7x3 microcontrollers. 61.1 Unique device ID register (96 bits) The unique device identifier is ideally suited: • for use as serial numbers (for example USB string serial numbers or other end applications) • for use as security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal Flash memory • to activate secure boot processes, etc. The 96-bit unique device identifier provides a reference number which is unique for any device and in any context. These bits can never be altered by the user. The 96-bit unique device identifier can also be read in single bytes/half-words/words in different ways and then be concatenated using a custom algorithm. Base address: 0x1FF1 E800 Address offset: 0x00 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r U_ID(31:0) r r r r r r r r r r r r r r r r r r r r r r Bits 31:0 U_ID(31:0): 31:0 unique ID bits Address offset: 0x04 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r U_ID(63:48) U_ID(47:32) r r r r r r r r r Bits 31:0 U_ID(63:32): 63:32 unique ID bits DocID029587 Rev 3 3153/3178 3154 Device electronic signature RM0433 Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r U_ID(95:80) U_ID(79:64) r r r r r r r r r Bits 31:0 U_ID(95:64): 95:64 Unique ID bits. 61.2 Flash size Base address: 0x1FF1 E880 Address offset: 0x00 Read only = 0xXXXX where X is factory-programmed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r F_SIZE r r r r r r r r Bits 15:0 F_ID(15:0): Flash memory size This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x0400 corresponds to 1024 Kbytes. 61.3 Package data register Refer to SYSCFG package register (SYSCFG_PKGR) for package identification. The SYSCFG clock should be enabled first in the RCC_APB4ENR register. 3154/3178 DocID029587 Rev 3 RM0433 Revision history Revision history Table 587. Document revision history Date Revision 12-Dec-2016 1 Changes Initial release. Section 2 renamed Memory and bus architecture. Updated Section : Embedded bootloader. Section 3: Embedded Flash memory (FLASH) Updated Section : Flash sector erase, Section : Standard Flash bank erase, Section : Flash bank erase with automatic protection removal and Section : Flash mass erase. Added Section : Flash mass erase with automatic protection removal. Updated Table 16: FLASH register map and reset value: – FLASH_BOOT7_CURR/PRG (add offset = 0x140/0x144) available only on RM0399. – Added FLASH_CRCEADD2R at add. offset = 0x158 – Added FLASH_CRCEADD2R at add offset = 0x15C 26-May-2017 2 Section 6: Power control (PWR) Updated Section 6.3.1: PWR pins and internal signals. Updated VBAT in Section 6.4: Power supplies. Updated Figure 13: Power supply overview and Figure 15: Device startup with VCORE supplied from voltage regulator. Removed VCORE in Section 6.5: Power supply supervision. Updated Figure 24: VCORE voltage scaling versus system power modes and Figure 25: Power control modes detailed state diagram. Section 8: Reset and Clock Control (RCC) Names of all clock source selection bits changed from XXSCR to XXSEL. RC48 renamed HSI48. VSWRST bit renamed BDRST in RCC_BDCR and bit description modified. CAMITFEN renamed DCMIEN in RCC_AHB2ENR; and CAMITFLPEN renamed DCMILPEN in RCC_AHB2LPENR. FLITFLPEN bit renamed FLASHLPEN in RCC_AHB3LPENR. HDMICECLPEN renamed CECLPEN in RCC_APB1LLPENR, Updated peripheral kernel clock names in the whole document. Updated Figure 34: System reset circuit to remove VDDA. Updated maximum frequency for ADC1, 2, 3 in Table 51: Kernel clock distribution overview. Removed lsi_ck as USBxOTG clock in Section : Peripherals dedicated to control and data transfer. DocID029587 Rev 3 3155/3178 3165 Revision history RM0433 Table 587. Document revision history (continued) Date Revision Changes Section 8: Reset and Clock Control (RCC) (continued) Renamed USART7RST/EN/LPEN bits into UART7RST/EN/LPEN, and USART8RST/EN/LPEN bits into UART8RST/EN/LPEN in Section 8.7.31: RCC APB1 Peripheral Reset Register (RCC_APB1LRSTR), Section 8.7.43: RCC APB1 Clock Register (RCC_APB1LENR) and Section 8.7.52: RCC APB1 Low Sleep Clock Register (RCC_APB1LLPENR). Section 10: Hardware semaphore (HSEM) Renamed pclk into hsem_hclk in the whole document. Updated COREID bit description in Section 10.4.1: HSEM register (HSEM_R0 - HSEM_R31). Section 11: General-purpose I/Os (GPIO) Table 84: GPIO register map and reset values: – updated GPIOx_MODER reset values – changed index to A to K for GPIOx_AFRH. – added GPIOC..K_PUPDR 26-May-2017 2 (continued) Section 12: System configuration controller (SYSCFG) Updated SYSCFG_UR3 register. Section 13: Block interconnect In Table 92: DMAMUX1, DMA1 and DMA2 connections, renamed dac1_dma and dac2_dma into dac_ch1_dma and dac_ch2_dma, respectively. Updated several source and destination signals in Table 88: Peripherals interconnect matrix details and Table 89: EXTI wakeup inputs. Section 17: DMA request multiplexer (DMAMUX) Updated resources in Table 110: DMAMUX1: assignment of multiplexer inputs to resources to Table 112: DMAMUX1: assignment of synchronization inputs to resources. Section 19: Nested Vectored Interrupt Controllers Added LCD-TFT interrupts (ltdc_it and ltdc_err_it) in Table 130: NVIC. Extended interrupt and event controller (EXTI) Replaced DMA1 by BDMA for events 66 to 73 in Table 133: EXTI Event input mapping. 3156/3178 DocID029587 Rev 3 RM0433 Revision history Table 587. Document revision history (continued) Date Revision Changes Section 22: Flexible memory controller (FMC) – Updated internal signals in Figure 86: FMC block diagram – HCLK renamed fmc_hclk – KCK_FMC renamed fmc_ker_ck Updated Section 22.5: AXI interface to add 32-bit accesses. Read FIFO depth changed to 6x64 bits. AXI bus width correct (64 bits instead of 32 bits). All waveforms made generic for what regards data bus and NBL bits. In Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4), modified DATAST example and updated BURSTURN description. In Section : SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4): updated BURSTURN description. Updated Section : SDRAM Control registers 1,2 (FMC_SDCR1,2) to add bitfield width. Added missing FMC_SDCR2 bits in Table 181: FMC register map. 26-May-2017 Section 23: Quad-SPI interface (QUADSPI) Updated internal signals in Figure 115: QUADSPI block diagram when dual-flash mode is disabled and Figure 116: QUADSPI block diagram when dual-flash mode is enabled. Added Section 23.3.2: QUADSPI pins and internal signals. Modified error type for access by Cortex CPU in Section 23.3.7: QUADSPI memory-mapped 2 mode. (continued) Added Section 23.3.8: QUADSPI Free running clock mode as well as FRCM bit in Section 23.5.6: QUADSPI communication configuration register (QUADSPI_CCR). Updated Section 23.5.1: QUADSPI control register (QUADSPI_CR). In Table 185: QUADSPI register map and reset values, changed DMAEN bit to reserved for QUADSPI_CR register. Section 24: Delay block (DLYB) Added internal signals in Figure 123: DLYB block diagram and added Section 24.3.2: DLYB pins and internal signals. Section 25: Analog-to-digital converters (ADC) Number of ADCs changed to 3 in Section 25.1: Introduction. Added internal signals in Section 25.3.1: ADC block diagram. Changed ADCx_IN[19:0] into ADCx_INP[19:0] and ADCx_INN[19:0] in Figure 124: ADC block diagram and Table 190: ADC input/output pins. Changed ADC_CLK into adc_ker_ck. Updated Figure 126: ADC1 connectivity, Figure 127: ADC2 connectivity and Figure 128: ADC3 connectivity and added note below figure. Updated Figure 175: Dual ADC block diagram(1). Updated notes in Section : Dual clock domain architecture. Updated Section 25.3.11: Channel selection (SQRx, JSQRx) and Section 25.3.12: Channel preselection register (ADCx_PCSEL). DocID029587 Rev 3 3157/3178 3165 Revision history RM0433 Table 587. Document revision history (continued) Date Revision Changes Section 25: Analog-to-digital converters (ADC) (continued) Examples given for 24 MHz instead of 72 MHz in Section 25.3.13: Channel-wise programmable sampling time (SMPR1, SMPR2) and Section 25.3.17: Timing. 6-bit resolution removed and updated Table 195: TSAR timings depending on resolution in Section 25.3.23: Programmable resolution (RES) - fast conversion mode. Updated notes in Section : Combined regular/injected simultaneous mode and Section : Combined regular simultaneous + alternate trigger mode. Added Section : DFSDM mode in dual ADC simultaneous mode. Changed ADC3_IN18 into ADC3 VINP[18] in Section 25.3.33: Temperature sensor. Changed ADC3_IN17 into ADC3 VINP[17] in Section 25.3.34: VBAT supply monitoring. Changed ADC3_IN19 into ADC3 VINP[19] in Section 25.3.35: Monitoring the internal voltage reference. Changed all bit access type to ‘r’ in Section 25.5.15: ADC x regular Data Register (ADCx_DR) (x=1 to 3). Updated Table 206: ADC register map and reset values (master and slave ADC common registers) offset =0x300). 26-May-2017 Section 26: Digital-to-analog converter (DAC) 2 (continued) Updated/added internal signals in Figure 194: DAC channel block diagram. Added Section 26.3.2: DAC pins and internal signals.. APB1 clock and LSI clock replaced by dac_pclk and by lsi_ck in the whole document. Section 28: Comparator (COMP) Replaced COMP_IFCR by COMP_ICFR in Section 28.7.1: Comparator status register (COMP_SR). Section 29: Operational amplifiers (OPAMP) Replaced all occurrences of DACx_int by dac_outx (x = 1, 2). Updated VP_SEL bit description in Section 29.6.1: OPAMP1 control/status register (OPAMP1_CSR) register. Section 31: Digital camera interface (DCMI) Section DCMI pins merged with Section 31.4.4: DCMI physical interface. External signals HSYNC, VSYNC and PIXCLK standardized to DCMI_HSYNC, DCMI_VSYNC and DCIM_PIXCLK in the whole document. Updated Figure 224: DCMI block diagram and Figure 225: Toplevel block diagram. 3158/3178 DocID029587 Rev 3 RM0433 Revision history Table 587. Document revision history (continued) Date Revision Changes Section 32: LCD-TFT Display Controller (LTDC) LCD-TFT pins and signal interface renamed LCD-TFT pins and external signal interface. Internal signal names updated in Figure 233: LTDC block diagram. ck_axi_d1 renamed ltdc_aclk in the whole document. Updated Section 32.3.4: LTDC reset and clocks. Updated CFBP bitfield size in Section 32.7.23: LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2). Section 33: JPEG codec (JPEG) Added Internal signal names in Figure 238: JPEG codec block diagram and added Section 33.3.2: JPEG internal signals. Suppressed DMA feature. Updated JPEG_CR, JPEG_SR and JPRG_CFR registers in Table 259: JPEG codec register map and reset values. 26-May-2017 Section 37: High-Resolution Timer (HRTIM) Renamed SCOUT into HRTIM_SCOUT in the whole section. Renamed Tx into HRTIM_CHxy in all figures where it is referred to. Updated internal signals in Figure 274: High-resolution timer block diagram. Added hrtim_in_sync1 and hrtim_out_sync1 in Table 283: HRTIM Input/output summary. Updated Section : Definition of terms. 2 (continued) Updated internal signal names in all the figures where they are mentioned and in HRTIM functional description Added note related to hrtim_ker_ck in Table 283: HRTIM Input/output summary. Modified ADC3TAPER bit description in Section 37.5.56: HRTIM ADC Trigger 3 Register (HRTIM_ADC3R). Modified ADC4TCRST, ADC4TAPER, ADC4TAC2, ADC4EEV6, ADC4MPER and DC4MC1 bit descriptions in and Section 37.5.57: HRTIM ADC Trigger 4 Register (HRTIM_ADC4R). Section 43: Low-power timer (LPTIM) Added internal signals in Figure 515: Low-power timer block diagram (LPTIM1 and LPTIM2), Figure 516: Low-power timer block diagram (LPTIM3) and Figure 517: Low-power timer block diagram (LPTIM4 and LPTIM5). Added Section 43.4.2: LPTIM pins and internal signals. Table 335: LPTIM1 external trigger connection to Table 339: LPTIM5 external trigger connection updated and moved under Section 43.4.3: LPTIM input and trigger mapping. Table 340: LPTIM1 Input 1 connection to Table 344: LPTIM3 Input 1 connection updated and moved under Section 43.4.3: LPTIM input and trigger mapping. Updated TRIGSEL bitfield description in Section 43.6.4: LPTIM configuration register (LPTIM_CFGR). DocID029587 Rev 3 3159/3178 3165 Revision history RM0433 Table 587. Document revision history (continued) Date Revision Changes Section 43: Low-power timer (LPTIM) (continued) Added caution note for COUNTRST bit in Section 43.6.5: LPTIM control register (LPTIM_CR). Updated IN1SEL and IN2SEL bitfield description and added caution note in Section 43.6.9: LPTIM configuration register 2 (LPTIM_CFGR2). Added caution note in Section 43.6.10: LPTIM3 configuration register 2 (LPTIM3_CFGR2). Section 46: Real-time clock (RTC) Added Figure 527: RTC block overview. Updated title of Figure 528: Detailed RTC block diagram. Added Section 46.3.2: RTC pins and internal signals. Updated Table 353: RTC pins and internal signals. Updated Section 46.3.3: GPIOs controlled by the RTC. Updated Section 46.6.16: RTC tamper configuration register (RTC_TAMPCR). 26-May-2017 Section 47: Inter-integrated circuit (I2C) interface Updated OA1[7:1] and OA2[7:1] bit description in Section 47.7.3: 2 Own address 1 register (I2C_OAR1) and Section 47.7.4: Own (continued) address 2 register (I2C_OAR2). Replaced HSI16 by HSI or CSI or internal oscillator in Section 47.4.14: Wakeup from Stop mode on address match. Section 48: Universal synchronous asynchronous receiver transmitter (USART) Section 48.5.14: USART synchronous mode: removed Figure RX data setup/hold time, added reference to synchronous mater mode in Figure 574: USART data clock timing diagram in synchronous master mode (M bits =’00’) and Figure 575: USART data clock timing diagram in synchronous master mode (M bits = ‘01’) and figure contents updated to mention two M bits instead of one. Updated Figure 586: Wakeup event verified (wakeup event = address match, FIFO disabled) in Section 48.5.21: USART lowpower management. Section 51: Serial audio interface (SAI) Updated SYNCIN bitfield description in Section 51.5.1: Global configuration register (SAI_GCR). 3160/3178 DocID029587 Rev 3 RM0433 Revision history Table 587. Document revision history (continued) Date Revision Changes Section 50: Serial peripheral interface (SPI) Updated note in Section : Simplex communications. Added note about the PCM long and short frame definition in Section : PCM standard. Added Section 50.9.3: Bits and fields usable in I2S/PCM mode description and Table 391: Bit fields usable in PCM/I2S mode. Updated WSINV in Section 50.11.14: SPI/I2S configuration register (SPI_I2SCGFR) and Section 50.12: SPI register map and reset values. Section 52: SPDIF receiver interface (SPDIFRX) Added internal signals in Section Figure 658.: SPDIFRX block diagram and added Section 52.3.1: SPDIFRX pins and internal signals. 26-May-2017 Section 55: Secure digital input/output MultiMediaCard interface (SDMMC) – Renamed internal signals in the whole section; updated Figure 694: SDMMC block diagram; added Section 55.4.2: SDMMC pins and internal signals – Added Section 55.4.7: MDMA request generation – Removed SDMMC_VER, SDMMC_ID, SDMMC_SID – Updated SDMMC_STAR bit 12 and 13 in Table 449: SDMMC 2 register map. (continued) Section 56: FD Controller Area Network (FDCAN) ASC (asynchronous serial communication) removed from the whole section. Added F0OM bit (bit 31) and F1OM bit (bit 31) in FDCAN Rx FIFO 0 Configuration Register (FDCAN_RXF0C) and FDCAN Rx FIFO 1 Configuration Register (FDCAN_RXF1C), respectively. Section 57: USB on-the-go high-speed (OTG_HS) Added Section 57.4.2: USB OTG pin and internal signals. Section 60: Debug infrastructure Updated Section 60.5.8: Microcontroller debug unit (DBGMCU). Replaced in all DBGMCU register names: – D1APB1 by APB3 – D2APB1 by APB1 – D2APB2 by APB2 – D3APB4byAPB4 WDGLSD2 bit changed to reserved in Section : DBGMCU APB4 peripheral freeze register CPU (DBGMCU_APB4FZ1)DBGMCU_APB4FZ1. Removed reserved registers in Table 578: DBGMCU register map and reset values. DocID029587 Rev 3 3161/3178 3165 Revision history RM0433 Table 587. Document revision history (continued) Date Revision Changes Section 2.3: Embedded SRAM Added Section : Error code correction (ECC). Section 12: System configuration controller (SYSCFG) Changed 2.5 to 2.7 V in HSLV bit description of SYSCFG compensation cell control/status register (SYSCFG_CCCSR) and IO_HSLV of SYSCFG user register 17 (SYSCFG_UR17). Section 3: Embedded Flash memory (FLASH) In Table 16: FLASH register map and reset value: – Updated FLASH_OPTSR_CUR at address offset 0x11C. – Updated FLASH_OPTSR_PRG at address offset 0x120. Changed 2.5 to 2.7 V in IO_HSLV bit description of FLASH option status register (current value) (FLASH_OPTSR_CUR) and FLASH option status register (value to program) (FLASH_OPTSR_PRG). 11-Aug-2017 3 Section 6: Power control (PWR) Replace AIEC by EXTI and wait VDD11 by Wait VCORE in Figure 27: Dynamic voltage scaling behavior with D1, D2 and system in Stop mode, Figure 28: Dynamic Voltage Scaling D1, D2, system Standby mode and Figure 29: Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and D3 in autonomous mode. Updated Section 6.4.7: USB regulator Updated Section : Entering Stop mode. Section 7: Low-power D3 domain Replaced VDD11 by VCORE. Section 8: Reset and Clock Control (RCC) Updated maximum frequency for ADC1, 2, 3 in Table 51: Kernel clock distribution overview. Section 10: Hardware semaphore (HSEM) Whole section updated to align with the product features. Section 14: MDMA controller (MDMA) Removed iterator in MDMA_CxISR and MDMA_CxIFCR bit names. Section 19: Nested Vectored Interrupt Controllers Changed usart4_gbl_it into uart4_gbl_it in Table 130: NVIC. Section 21: Cyclic redundancy check calculation unit (CRC) Updated first two features of Section 21.2: CRC main features. 3162/3178 DocID029587 Rev 3 RM0433 Revision history Table 587. Document revision history (continued) Date 11-Aug-2017 Revision Changes Section 25: Analog-to-digital converters (ADC) Section 25.2: ADC main features: suppressed ADC supply requirements. Renamed VTS into VSENSE in the whole section. Updated Figure 124: ADC block diagram, Figure 126: ADC1 connectivity, Figure 127: ADC2 connectivity and Figure 128: ADC3 connectivity. VINN connected to ADC_INN instead of ADC_INN-1 in Table 190: ADC input/output pins. Section : I/O analog switches voltage booster: voltage booster enable bit renamed BOOTSE (instead of BOOTSEN) and corresponding register renamed SYSCFG_PMCR (instead of SYSCFG_CFGR1). Added note related to software trigger selection in Section 25.3.16: Starting conversions (ADSTART, JADSTART). Updated Figure 136: Triggers are shared between ADC master and ADC slave, Figure 191: Temperature sensor channel block diagram, Figure 192: VBAT channel block diagram and Figure 193: VREFINT channel block diagram. Updated Section : Analog watchdog. Updated software notification by interrupt at end of conversion in Section : Interleaved mode with independent injected; updated Figure 178: Interleaved mode on 1 channel in continuous 3 (continued) conversion mode: dual ADC mode and Figure 179: Interleaved mode on 1 channel in single conversion mode: dual ADC mode. Removed temperature sensor precision and replaced ambient by junction temperature in Section 25.3.33: Temperature sensor. Section 25.6.2: ADC x common control register (ADCx_CCR) (x=12 or 3): – VBATEN bit description made generic – TSEN renamed VSENSEEN and description made generic – Updated Table 203: DELAY bits versus ADC resolution. ADCx_OR register suppressed since all bits are reserved. Renamed ADCx_LHTR1 into ADCx_HTR1. Changed ADCx_ISR bit access type to rc_w1. Updated iterators for all ADC common registers Section 26: Digital-to-analog converter (DAC) Updated VREF+ range in Table 207: DAC input/output pins Updated Section 26.3.5: DAC conversion. Added note related to ENx limitation when CENx is set in Section 26.3.12: DAC channel buffer calibration. Added case of accesses to DHRxxxD for wave generation in Section 26.3.13: Dual DAC channel conversion (if available). Renamed DAC_M_ID into DAC_SIDR and M_ID bits into SID. DocID029587 Rev 3 3163/3178 3165 Revision history RM0433 Table 587. Document revision history (continued) Date Revision Changes Section 26: Digital-to-analog converter (DAC) (continued) Added Section 26.5: DAC interrupts Section 26.6.1: DAC x control register (DACx_CR) (x=1 to 2): – TEN2 bit: replaced DACx_DHRy by DACx_DHR2 – TEN1 bit: replaced DACx_DHRy by DACx_DHR1 in. – TSELx bits: updated information on trigger selection/mapping Section 26.6.16: DAC x mode control register (DACx_MCR) (x=1 to 2): added note related to ENx bit for MODEx bit description. Section 26.6.19: DAC x Sample and Hold hold time register (DACx_SHHR)(x=1 to 2): added notes related to THOLDx modification when ENx=0. Section 26.6.20: DAC x Sample and Hold refresh time register (DACx_SHRR)(x=1 to 2): added note related to TREFRESHx modification when ENx=0. Suppressed DAC_OR register. Section 29: Operational amplifiers (OPAMP) Updated OPAMP1_VINM internal connection in Table 225: Operational amplifier possible connections. 11-Aug-2017 3 (continued) Section 37: High-Resolution Timer (HRTIM) Updated Note 1. in Table 289: External events mapping and associated features. Section 44: System window watchdog (WWDG) Corrected math equations used to calculate the WWDG period. Section 47: Inter-integrated circuit (I2C) interface Updated NACKCF bit definition in Section 47.7.8: Interrupt clear register (I2C_ICR) register. Section 51: Serial audio interface (SAI) SAIXEN bit renamed SAIEN in SAI_xCR register. Updated Figure 643: PDM typical connection and timing to make the block diagram independent from the number of data and clock lines. Updated Figure 644: Detailed PDM interface block diagram to add “n” and “p” indexes (n being the number of data lines and p the number of microphone pairs). Section 52: SPDIF receiver interface (SPDIFRX) Updated Figure 658: SPDIFRX block diagram. Section 59: HDMI-CEC controller (HDMI-CEC) Updated – Section 59.2: HDMI-CEC controller main features – Updated Figure 798: HDMI-CEC block diagram 3164/3178 DocID029587 Rev 3 RM0433 Revision history Table 587. Document revision history (continued) Date 11-Aug-2017 Revision Changes Section 61: Device electronic signature Updated Unique device ID register base address in Section 61.1: Unique device ID register (96 bits). 3 (continued) Updated Flash size base address in Section 61.2: Flash size. Replaced package data register description by reference to SYSCFG_PKGR in Section 61.3: Package data register. DocID029587 Rev 3 3165/3178 3165 Index RM0433 Index A ADC_JSQR . . . . . . . . . . . . . . . . . . . . . . . . . .961 ADCx_AWD2CR . . . . . . . . . . . . . . . . . . . . . .964 ADCx_AWD3CR . . . . . . . . . . . . . . . . . . . . . .965 ADCx_CALFACT . . . . . . . . . . . . . . . . . . . . . .968 ADCx_CALFACT2 . . . . . . . . . . . . . . . . . . . . .968 ADCx_CCR . . . . . . . . . . . . . . . . . . . . . . . . . .972 ADCx_CDR . . . . . . . . . . . . . . . . . . . . . . . . . .975 ADCx_CDR2 . . . . . . . . . . . . . . . . . . . . . . . . .975 ADCx_CFGR . . . . . . . . . . . . . . . . . . . . . . . . .946 ADCx_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . .950 ADCx_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .941 ADCx_CSR . . . . . . . . . . . . . . . . . . . . . . . . . .970 ADCx_DIFSEL . . . . . . . . . . . . . . . . . . . . . . . .967 ADCx_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .960 ADCx_HTR1 . . . . . . . . . . . . . . . . . . . . . . . . .955 ADCx_HTR2 . . . . . . . . . . . . . . . . . . . . . . . . .966 ADCx_HTR3 . . . . . . . . . . . . . . . . . . . . . . . . .967 ADCx_IER . . . . . . . . . . . . . . . . . . . . . . . . . . .939 ADCx_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . .937 ADCx_JDRy . . . . . . . . . . . . . . . . . . . . . . . . . .964 ADCx_LTR1 . . . . . . . . . . . . . . . . . . . . . . . . . .954 ADCx_LTR2 . . . . . . . . . . . . . . . . . . . . . . . . . .965 ADCx_LTR3 . . . . . . . . . . . . . . . . . . . . . . . . . .966 ADCx_OFRy . . . . . . . . . . . . . . . . . . . . . . . . .963 ADCx_PCSEL . . . . . . . . . . . . . . . . . . . . . . . .954 ADCx_SMPR1 . . . . . . . . . . . . . . . . . . . . . . . .952 ADCx_SMPR2 . . . . . . . . . . . . . . . . . . . . . . . .953 ADCx_SQR1 . . . . . . . . . . . . . . . . . . . . . . . . .956 ADCx_SQR2 . . . . . . . . . . . . . . . . . . . . . . . . .957 ADCx_SQR3 . . . . . . . . . . . . . . . . . . . . . . . . .958 ADCx_SQR4 . . . . . . . . . . . . . . . . . . . . . . . . .959 AXI_COMP_ID_0 . . . . . . . . . . . . . . . . . . . . . .201 AXI_COMP_ID_1 . . . . . . . . . . . . . . . . . . . . . .202 AXI_COMP_ID_2 . . . . . . . . . . . . . . . . . . . . . .202 AXI_COMP_ID_3 . . . . . . . . . . . . . . . . . . . . . .203 AXI_INIx_FN_MOD . . . . . . . . . . . . . . . . . . . .207 AXI_INIx_FN_MOD_AHB . . . . . . . . . . . . . . .206 AXI_INIx_FN_MOD2 . . . . . . . . . . . . . . . . . . .205 AXI_INIx_READ_QOS . . . . . . . . . . . . . . . . . .206 AXI_INIx_WRITE_QOS . . . . . . . . . . . . . . . . .207 AXI_PERIPH_ID_0 . . . . . . . . . . . . . . . . . . . .199 AXI_PERIPH_ID_1 . . . . . . . . . . . . . . . . . . . .200 AXI_PERIPH_ID_2 . . . . . . . . . . . . . . . . . . . .200 AXI_PERIPH_ID_3 . . . . . . . . . . . . . . . . . . . .201 AXI_PERIPH_ID_4 . . . . . . . . . . . . . . . . . . . .199 AXI_TARGx_FN_MOD . . . . . . . . . . . . . . . . .205 AXI_TARGx_FN_MOD_ISS_BM . . . . . . . . . .203 3166/3178 AXI_TARGx_FN_MOD_LB . . . . . . . . . . . . . . 204 AXI_TARGx_FN_MOD2 . . . . . . . . . . . . . . . . 204 C CAN_TTGTP . . . . . . . . . . . . . . . . . . . . . . . . 2477 CCU_CCFG . . . . . . . . . . . . . . . . . . . . . . . . 2496 CCU_CREL . . . . . . . . . . . . . . . . . . . . . . . . . 2496 CCU_CSTAT . . . . . . . . . . . . . . . . . . . . . . . . 2498 CCU_CWD . . . . . . . . . . . . . . . . . . . . . . . . . 2499 CCU_IE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500 CCU_IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500 CEC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . 2927 CEC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926 CEC_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . 2932 CEC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930 CEC_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . 2930 CEC_TXDR . . . . . . . . . . . . . . . . . . . . . . . . . 2930 COMP_CFGR1 . . . . . . . . . . . . . . . . . . . . . . 1028 COMP_CFGR2 . . . . . . . . . . . . . . . . . . . . . . 1030 COMP_ICFR . . . . . . . . . . . . . . . . . . . . . . . . 1026 COMP_OR . . . . . . . . . . . . . . . . . . . . . . . . . 1027 COMP_SR . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 CRC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 CRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 CRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 CRC_INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 CRC_POL . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 CRS_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . . 465 CRS_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 CRS_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 CRS_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 CRYP_CR . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 CRYP_DIN . . . . . . . . . . . . . . . . . . . . . . . . . 1255 CRYP_DMACR . . . . . . . . . . . . . . . . . . . . . . 1257 CRYP_DOUT . . . . . . . . . . . . . . . . . . . . . . . 1256 CRYP_IMSCR . . . . . . . . . . . . . . . . . . . . . . . 1257 CRYP_IV0RR . . . . . . . . . . . . . . . . . . . . . . . 1263 CRYP_IV1LR . . . . . . . . . . . . . . . . . . . . . . . 1263 CRYP_IV1RR . . . . . . . . . . . . . . . . . . . . . . . 1263 CRYP_K0LR . . . . . . . . . . . . . . . . . . . . . . . . 1259 CRYP_K1LR . . . . . . . . . . . . . . . . . . . . . . . . 1260 CRYP_K1RR . . . . . . . . . . . . . . . . . . . . . . . . 1260 CRYP_K2LR . . . . . . . . . . . . . . . . . . . . . . . . 1261 CRYP_K2RR . . . . . . . . . . . . . . . . . . . . . . . . 1261 CRYP_K3LR . . . . . . . . . . . . . . . . . . . . . . . . 1262 CRYP_K3RR . . . . . . . . . . . . . . . . . . . . . . . . 1262 CRYP_MISR . . . . . . . . . . . . . . . . . . . . . . . . 1258 CRYP_RISR . . . . . . . . . . . . . . . . . . . . . . . . 1258 DocID029587 Rev 3 RM0433 Index CRYP_SR . . . . . . . . . . . . . . . . . . . . . . . . . .1255 CSTF_AUTHSTAT . . . . . . . . . . . . . . . . . . . .2999 CSTF_CIDR0 . . . . . . . . . . . . . . . . . . . . . . . .3002 CSTF_CIDR1 . . . . . . . . . . . . . . . . . . . . . . . .3003 CSTF_CIDR2 . . . . . . . . . . . . . . . . . . . . . . . .3003 CSTF_CIDR3 . . . . . . . . . . . . . . . . . . . . . . . .3003 CSTF_CLAIMCLR . . . . . . . . . . . . . . . . . . . .2997 CSTF_CLAIMSET . . . . . . . . . . . . . . . . . . . .2997 CSTF_CTRL . . . . . . . . . . . . . . . . . . . . . . . .2996 CSTF_DEVID . . . . . . . . . . . . . . . . . . . . . . . .2999 CSTF_LAR . . . . . . . . . . . . . . . . . . . . . . . . . .2998 CSTF_LSR . . . . . . . . . . . . . . . . . . . . . . . . . .2998 CSTF_PIDR0 . . . . . . . . . . . . . . . . . . . . . . . .3000 CSTF_PIDR1 . . . . . . . . . . . . . . . . . . . . . . . .3001 CSTF_PIDR2 . . . . . . . . . . . . . . . . . . . . . . . .3001 CSTF_PIDR3 . . . . . . . . . . . . . . . . . . . . . . . .3001 CSTF_PIDR4 . . . . . . . . . . . . . . . . . . . . . . . .3002 CSTF_PRIORITY . . . . . . . . . . . . . . . . . . . . .2996 CSTF_TYPEID . . . . . . . . . . . . . . . . . . . . . . .3000 CTI_APPCLEAR . . . . . . . . . . . . . . . . . . . . .2980 CTI_APPPULSE . . . . . . . . . . . . . . . . . . . . .2981 CTI_APPSET . . . . . . . . . . . . . . . . . . . . . . . .2980 CTI_AUTHSTAT . . . . . . . . . . . . . . . . . . . . .2987 CTI_CHINSTS . . . . . . . . . . . . . . . . . . . . . . .2984 CTI_CHOUTSTS . . . . . . . . . . . . . . . . . . . . .2984 CTI_CIDR0 . . . . . . . . . . . . . . . . . . . . . . . . . .2991 CTI_CIDR1 . . . . . . . . . . . . . . . . . . . . . . . . . .2991 CTI_CIDR2 . . . . . . . . . . . . . . . . . . . . . . . . . .2992 CTI_CIDR3 . . . . . . . . . . . . . . . . . . . . . . . . . .2992 CTI_CLAIMCLR . . . . . . . . . . . . . . . . . . . . . .2986 CTI_CLAIMSET . . . . . . . . . . . . . . . . . . . . . .2985 CTI_CONTROL . . . . . . . . . . . . . . . . . . . . . .2979 CTI_DEVID . . . . . . . . . . . . . . . . . . . . . . . . .2988 CTI_DEVTYPE . . . . . . . . . . . . . . . . . . . . . . .2988 CTI_GATE . . . . . . . . . . . . . . . . . . . . . . . . . .2985 CTI_INENx . . . . . . . . . . . . . . . . . . . . . . . . . .2981 CTI_INTACK . . . . . . . . . . . . . . . . . . . . . . . .2979 CTI_LAR . . . . . . . . . . . . . . . . . . . . . . . . . . .2986 CTI_LSR . . . . . . . . . . . . . . . . . . . . . . . . . . .2987 CTI_OUTENx . . . . . . . . . . . . . . . . . . . . . . . .2982 CTI_PIDR0 . . . . . . . . . . . . . . . . . . . . . . . . . .2989 CTI_PIDR1 . . . . . . . . . . . . . . . . . . . . . . . . . .2990 CTI_PIDR2 . . . . . . . . . . . . . . . . . . . . . . . . . .2990 CTI_PIDR3 . . . . . . . . . . . . . . . . . . . . . . . . . .2991 CTI_PIDR4 . . . . . . . . . . . . . . . . . . . . . . . . . .2989 CTI_TRGISTS . . . . . . . . . . . . . . . . . . . . . . .2983 CTI_TRGOSTS . . . . . . . . . . . . . . . . . . . . . .2983 D DACx_CCR . . . . . . . . . . . . . . . . . . . . . . . . .1007 DACx_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .998 DACx_DHR12L1 . . . . . . . . . . . . . . . . . . . . . 1002 DACx_DHR12L2 . . . . . . . . . . . . . . . . . . . . . 1003 DACx_DHR12LD . . . . . . . . . . . . . . . . . . . . . 1004 DACx_DHR12R1 . . . . . . . . . . . . . . . . . . . . . 1002 DACx_DHR12R2 . . . . . . . . . . . . . . . . . . . . . 1003 DACx_DHR12RD . . . . . . . . . . . . . . . . . . . . 1004 DACx_DHR8R1 . . . . . . . . . . . . . . . . . . . . . . 1002 DACx_DHR8R2 . . . . . . . . . . . . . . . . . . . . . . 1004 DACx_DHR8RD . . . . . . . . . . . . . . . . . . . . . 1005 DACx_DOR1 . . . . . . . . . . . . . . . . . . . . . . . . 1005 DACx_DOR2 . . . . . . . . . . . . . . . . . . . . . . . . 1006 DACx_MCR . . . . . . . . . . . . . . . . . . . . . . . . . 1008 DACx_SHHR . . . . . . . . . . . . . . . . . . . . . . . . 1010 DACx_SHRR . . . . . . . . . . . . . . . . . . . . . . . . 1011 DACx_SHSR1 . . . . . . . . . . . . . . . . . . . . . . . 1009 DACx_SHSR2 . . . . . . . . . . . . . . . . . . . . . . . 1010 DACx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 DACx_SWTRGR . . . . . . . . . . . . . . . . . . . . . 1001 DBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . 3069 DBGMCU_D1APB1FZ1 . . . . . . . . . . . . . . . 3071 DBGMCU_D2APB1HFZ1 . . . . . . . . . . . . . . 3073 DBGMCU_D2APB1LFZ1 . . . . . . . . . . . . . . 3072 DBGMCU_D2APB2FZ1 . . . . . . . . . . . . . . . 3073 DBGMCU_D3APB4FZ1 . . . . . . . . . . . . . . . 3074 DBGMCU_IDC . . . . . . . . . . . . . . . . . . . . . . 3069 DCMI_CR . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 DCMI_CWSIZE . . . . . . . . . . . . . . . . . . . . . . 1132 DCMI_CWSTRT . . . . . . . . . . . . . . . . . . . . . 1132 DCMI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 DCMI_ESCR . . . . . . . . . . . . . . . . . . . . . . . . 1130 DCMI_ESUR . . . . . . . . . . . . . . . . . . . . . . . . 1131 DCMI_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 DCMI_IER . . . . . . . . . . . . . . . . . . . . . . . . . . 1127 DCMI_MIS . . . . . . . . . . . . . . . . . . . . . . . . . . 1128 DCMI_RIS . . . . . . . . . . . . . . . . . . . . . . . . . . 1126 DCMI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 DFSDM_CHyAWSCDR . . . . . . . . . . . . . . . . 1084 DFSDM_CHyCFGR1 . . . . . . . . . . . . . . . . . 1081 DFSDM_CHyCFGR2 . . . . . . . . . . . . . . . . . 1083 DFSDM_CHyDATINR . . . . . . . . . . . . . . . . . 1085 DFSDM_CHyWDATR . . . . . . . . . . . . . . . . . 1085 DFSDM_FLTxAWCFR . . . . . . . . . . . . . . . . 1097 DFSDM_FLTxAWHTR . . . . . . . . . . . . . . . . 1096 DFSDM_FLTxAWLTR . . . . . . . . . . . . . . . . . 1096 DFSDM_FLTxAWSR . . . . . . . . . . . . . . . . . . 1097 DFSDM_FLTxCNVTIMR . . . . . . . . . . . . . . . 1099 DFSDM_FLTxCR1 . . . . . . . . . . . . . . . . . . . 1086 DFSDM_FLTxCR2 . . . . . . . . . . . . . . . . . . . 1089 DFSDM_FLTxEXMAX . . . . . . . . . . . . . . . . . 1098 DFSDM_FLTxEXMIN . . . . . . . . . . . . . . . . . 1098 DFSDM_FLTxFCR . . . . . . . . . . . . . . . . . . . 1093 DFSDM_FLTxICR . . . . . . . . . . . . . . . . . . . . 1092 DocID029587 Rev 3 3167/3178 Index RM0433 DFSDM_FLTxISR . . . . . . . . . . . . . . . . . . . .1090 DFSDM_FLTxJCHGR . . . . . . . . . . . . . . . . .1093 DFSDM_FLTxJDATAR . . . . . . . . . . . . . . . .1094 DFSDM_FLTxRDATAR . . . . . . . . . . . . . . . .1095 DLYB_CFGR . . . . . . . . . . . . . . . . . . . . . . . . .852 DLYB_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .852 DMA_CCRx . . . . . . . . . . . . . . . . . . . . . . . . . .629 DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .632 DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .631 DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .631 DMA_HIFCR . . . . . . . . . . . . . . . . . . . . . . . . .610 DMA_HISR . . . . . . . . . . . . . . . . . . . . . . . . . . .609 DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .628 DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .627 DMA_LIFCR . . . . . . . . . . . . . . . . . . . . . .570, 610 DMA_LISR . . . . . . . . . . . . . . . 568-569, 571, 608 DMA_SxCR . . . . . . . . . . . . . . . . . 573, 575, 611 DMA_SxFCR . . . . . . . . . . . . . . . . . . . . . . . . .616 DMA_SxM0AR . . . . . . . . . . . . . . . . . . . . . . . .615 DMA_SxM1AR . . . . . . . . . . . . . . . . . . . . . . . .615 DMA_SxNDTR . . . . . . . . . . . . . . . . . . . .578, 614 DMA_SxPAR . . . . . . . . . . . . . 580, 582-585, 615 DMA2D_AMTCR . . . . . . . . . . . . . . . . . . . . . .688 DMA2D_BGCMAR . . . . . . . . . . . . . . . . . . . . .684 DMA2D_BGCOLR . . . . . . . . . . . . . . . . . . . . .683 DMA2D_BGMAR . . . . . . . . . . . . . . . . . . . . . .677 DMA2D_BGOR . . . . . . . . . . . . . . . . . . . . . . .677 DMA2D_BGPFCCR . . . . . . . . . . . . . . . . . . . .681 DMA2D_CR . . . . . . . . . . . . . . . . . . . . . . . . . .672 DMA2D_FGCMAR . . . . . . . . . . . . . . . . . . . . .683 DMA2D_FGCOLR . . . . . . . . . . . . . . . . . . . . .680 DMA2D_FGMAR . . . . . . . . . . . . . . . . . . . . . .676 DMA2D_FGOR . . . . . . . . . . . . . . . . . . . . . . .676 DMA2D_FGPFCCR . . . . . . . . . . . . . . . . . . . .678 DMA2D_IFCR . . . . . . . . . . . . . . . . . . . . . . . .675 DMA2D_ISR . . . . . . . . . . . . . . . . . . . . . . . . . .674 DMA2D_LWR . . . . . . . . . . . . . . . . . . . . . . . . .688 DMA2D_NLR . . . . . . . . . . . . . . . . . . . . . . . . .687 DMA2D_OCOLR . . . . . . . . . . . . . . . . . . . . . .685 DMA2D_OMAR . . . . . . . . . . . . . . . . . . . . . . .686 DMA2D_OOR . . . . . . . . . . . . . . . . . . . . . . . .687 DMA2D_OPFCCR . . . . . . . . . . . . . . . . . . . . .684 DMAMUX1_CSR . . . . . . . . . . . . . . . . . . . . . .649 DP_DPIDR . . . . . . . . . . . . . . . . . . . . . . . . . .2946 E ETF_AUTHSTAT . . . . . . . . . . . . . . . . . . . . .3020 ETF_BUFWM . . . . . . . . . . . . . . . . . . . . . . . .3014 ETF_CBUFLVL . . . . . . . . . . . . . . . . . . . . . .3013 ETF_CIDR0 . . . . . . . . . . . . . . . . . . . . . . . . .3023 ETF_CIDR1 . . . . . . . . . . . . . . . . . . . . . . . . .3024 3168/3178 ETF_CIDR2 . . . . . . . . . . . . . . . . . . . . . . . . . 3024 ETF_CIDR3 . . . . . . . . . . . . . . . . . . . . . . . . . 3024 ETF_CLAIMCLR . . . . . . . . . . . . . . . . . . . . . 3018 ETF_CLAIMSET . . . . . . . . . . . . . . . . . . . . . 3018 ETF_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 3011 ETF_DEVID . . . . . . . . . . . . . . . . . . . . . . . . . 3020 ETF_DEVTYPE . . . . . . . . . . . . . . . . . . . . . . 3021 ETF_FFCR . . . . . . . . . . . . . . . . . . . . . . . . . 3015 ETF_FFSR . . . . . . . . . . . . . . . . . . . . . . . . . 3014 ETF_LAR . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019 ETF_LBUFLVL . . . . . . . . . . . . . . . . . . . . . . 3013 ETF_LSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019 ETF_MODE . . . . . . . . . . . . . . . . . . . . . . . . . 3012 ETF_PIDR0 . . . . . . . . . . . . . . . . . . . . . . . . . 3022 ETF_PIDR1 . . . . . . . . . . . . . . . . . . . . . . . . . 3022 ETF_PIDR2 . . . . . . . . . . . . . . . . . . . . . . . . . 3022 ETF_PIDR3 . . . . . . . . . . . . . . . . . . . . . . . . . 3023 ETF_PIDR4 . . . . . . . . . . . . . . . . . . . . . . . . . 3021 ETF_PSCR . . . . . . . . . . . . . . . . . . . . . . . . . 3017 ETF_RRD . . . . . . . . . . . . . . . . . . . . . . . . . . 3009 ETF_RRP . . . . . . . . . . . . . . . . . . . . . . . . . . 3009 ETF_RSZ . . . . . . . . . . . . . . . . . . . . . . . . . . 3007 ETF_RWD . . . . . . . . . . . . . . . . . . . . . . . . . . 3012 ETF_RWP . . . . . . . . . . . . . . . . . . . . . . . . . . 3010 ETF_STS . . . . . . . . . . . . . . . . . . . . . . . . . . . 3008 ETF_TRG . . . . . . . . . . . . . . . . . . . . . . . . . . 3010 ETH_DMAC0CARxBR . . . . . . . . . . . . . . . . 2794 ETH_DMAC0CARxDR . . . . . . . . . . . . . . . . 2793 ETH_DMAC0RxCR . . . . . . . . . . . . . . . . . . . 2782 ETH_DMAC0RxDLAR . . . . . . . . . . . . . . . . . 2785 ETH_DMAC0RxDTPR . . . . . . . . . . . . . . . . 2787 ETH_DMAC0RxIWTR . . . . . . . . . . . . . . . . . 2792 ETH_DMAC0RxRLR . . . . . . . . . . . . . . . . . . 2788 ETH_DMACiCATxBR . . . . . . . . . . . . . . . . . 2793 ETH_DMACiCATxDR . . . . . . . . . . . . . . . . . 2792 ETH_DMACiCR . . . . . . . . . . . . . . . . . . . . . . 2779 ETH_DMACiIER . . . . . . . . . . . . . . . . . . . . . 2788 ETH_DMACiMFCR . . . . . . . . . . . . . . . . . . . 2797 ETH_DMACiSR . . . . . . . . . . . . . . . . . . . . . . 2794 ETH_DMACiTxCR . . . . . . . . . . . . . . . . . . . . 2780 ETH_DMACiTxDLAR . . . . . . . . . . . . . . . . . 2784 ETH_DMACiTxDTPR . . . . . . . . . . . . . . . . . 2786 ETH_DMACiTxRLR . . . . . . . . . . . . . . . . . . . 2787 ETH_DMADSR . . . . . . . . . . . . . . . . . . . . . . 2778 ETH_DMAISR . . . . . . . . . . . . . . . . . . . . . . . 2777 ETH_DMAMR . . . . . . . . . . . . . . . . . . . . . . . 2774 ETH_DMASBMR . . . . . . . . . . . . . . . . . . . . . 2776 ETH_MAC1USTCR . . . . . . . . . . . . . . . . . . . 2850 ETH_MACA0HR . . . . . . . . . . . . . . . . . . . . . 2860 ETH_MACACR . . . . . . . . . . . . . . . . . . . . . . 2893 ETH_MACARPAR . . . . . . . . . . . . . . . . . . . . 2860 ETH_MACATSNR . . . . . . . . . . . . . . . . . . . . 2894 DocID029587 Rev 3 RM0433 Index ETH_MACATSSR . . . . . . . . . . . . . . . . . . . .2895 ETH_MACAxHR . . . . . . . . . . . . . . . . . . . . . .2861 ETH_MACAxLR . . . . . . . . . . . . . . . . . . . . . .2861 ETH_MACCR . . . . . . . . . . . . . . . . . . . . . . . .2814 ETH_MACDR . . . . . . . . . . . . . . . . . . . . . . . .2851 ETH_MACECR . . . . . . . . . . . . . . . . . . . . . .2820 ETH_MACHT0R . . . . . . . . . . . . . . . . . . . . . .2826 ETH_MACHT1R . . . . . . . . . . . . . . . . . . . . . .2827 ETH_MACHWF1R . . . . . . . . . . . . . . . . . . . .2852 ETH_MACHWF2R . . . . . . . . . . . . . . . . . . . .2855 ETH_MACIER . . . . . . . . . . . . . . . . . . . . . . .2838 ETH_MACISR . . . . . . . . . . . . . . . . . . . . . . .2836 ETH_MACIVIR . . . . . . . . . . . . . . . . . . . . . . .2832 ETH_MACL3A00R . . . . . . . . . . . . . . . . . . . .2876 ETH_MACL3A01R . . . . . . . . . . . . . . . . . . . .2881 ETH_MACL3A10R . . . . . . . . . . . . . . . . . . . .2876 ETH_MACL3A11R . . . . . . . . . . . . . . . . . . . .2882 ETH_MACL3A20 . . . . . . . . . . . . . . . . . . . . .2877 ETH_MACL3A21R . . . . . . . . . . . . . . . . . . . .2882 ETH_MACL3A30 . . . . . . . . . . . . . . . . . . . . .2877 ETH_MACL3A31R . . . . . . . . . . . . . . . . . . . .2883 ETH_MACL3L4C0R . . . . . . . . . . . . . . . . . . .2873 ETH_MACL3L4C1R . . . . . . . . . . . . . . . . . . .2878 ETH_MACL4A0R . . . . . . . . . . . . . . . . . . . . .2875 ETH_MACL4A1R . . . . . . . . . . . . . . . . . . . . .2880 ETH_MACLCSR . . . . . . . . . . . . . . . . . . . . .2847 ETH_MACLETR . . . . . . . . . . . . . . . . . . . . . .2850 ETH_MACLMIR . . . . . . . . . . . . . . . . . . . . . .2905 ETH_MACLTCR . . . . . . . . . . . . . . . . . . . . . .2849 ETH_MACMDIOAR . . . . . . . . . . . . . . . . . . .2856 ETH_MACMDIODR . . . . . . . . . . . . . . . . . . .2859 ETH_MACPCSR . . . . . . . . . . . . . . . . . . . . .2841 ETH_MACPFR . . . . . . . . . . . . . . . . . . . . . . .2822 ETH_MACPOCR . . . . . . . . . . . . . . . . . . . . .2902 ETH_MACPPSCR . . . . . . . . . . . . . . . . . . . .2898 ETH_MACPPSIR . . . . . . . . . . . . . . . . . . . . .2901 ETH_MACPPSTTNR . . . . . . . . . . . . . . . . . .2901 ETH_MACPPSTTSR . . . . . . . . . . . . . . . . . .2900 ETH_MACPPSWR . . . . . . . . . . . . . . . . . . . .2902 ETH_MACQ0TxFCR . . . . . . . . . . . . . . . . . .2833 ETH_MACRWKPFR . . . . . . . . . . . . . . . . . .2843 ETH_MACRxFCR . . . . . . . . . . . . . . . . . . . .2835 ETH_MACRxTxSR . . . . . . . . . . . . . . . . . . . .2839 ETH_MACSPI0R . . . . . . . . . . . . . . . . . . . . .2903 ETH_MACSPI1R . . . . . . . . . . . . . . . . . . . . .2904 ETH_MACSPI2R . . . . . . . . . . . . . . . . . . . . .2904 ETH_MACSSIR . . . . . . . . . . . . . . . . . . . . . .2886 ETH_MACSTNR . . . . . . . . . . . . . . . . . . . . .2888 ETH_MACSTNUR . . . . . . . . . . . . . . . . . . . .2889 ETH_MACSTSR . . . . . . . . . . . . . . . . . . . . .2888 ETH_MACSTSUR . . . . . . . . . . . . . . . . . . . .2889 ETH_MACTSAR . . . . . . . . . . . . . . . . . . . . .2890 ETH_MACTSCR . . . . . . . . . . . . . . . . . . . . . 2883 ETH_MACTSEACR . . . . . . . . . . . . . . . . . . . 2896 ETH_MACTSECNR . . . . . . . . . . . . . . . . . . 2897 ETH_MACTSIACR . . . . . . . . . . . . . . . . . . . 2895 ETH_MACTSICNR . . . . . . . . . . . . . . . . . . . 2896 ETH_MACTSSR . . . . . . . . . . . . . . . . . . . . . 2890 ETH_MACTxTSSNR . . . . . . . . . . . . . . . . . . 2892 ETH_MACTxTSSSR . . . . . . . . . . . . . . . . . . 2892 ETH_MACVHTR . . . . . . . . . . . . . . . . . . . . . 2830 ETH_MACVIR . . . . . . . . . . . . . . . . . . . . . . . 2831 ETH_MACVR . . . . . . . . . . . . . . . . . . . . . . . 2851 ETH_MACVTR . . . . . . . . . . . . . . . . . . . . . . 2828 ETH_MACWTR . . . . . . . . . . . . . . . . . . . . . . 2825 ETH_MTLISR . . . . . . . . . . . . . . . . . . . . . . . 2802 ETH_MTLOMR . . . . . . . . . . . . . . . . . . . . . . 2801 ETH_MTLQiICSR . . . . . . . . . . . . . . . . . . . . 2807 ETH_MTLRxQ0OMR . . . . . . . . . . . . . . . . . 2808 ETH_MTLRxQiDR . . . . . . . . . . . . . . . . . . . . 2811 ETH_MTLRxQiMPOCR . . . . . . . . . . . . . . . . 2810 ETH_MTLTxQiDR . . . . . . . . . . . . . . . . . . . . 2805 ETH_MTLTxQiOMR . . . . . . . . . . . . . . . . . . 2802 ETH_MTLTxQiUR . . . . . . . . . . . . . . . . . . . . 2804 EXTI_EMR . . . . . . . . . . . . . . . . . . . . . . 723, 725 EXTI_FTSR . . . . . . . . . . . . . . . . . . 713, 717, 720 EXTI_IMR . . . . 714-715, 718-719, 721-724, 726 EXTI_PR . . . . . . . . . . . . . . . . . . . . 724-725, 727 EXTI_RTSR . . . . . . . . . . . . . . . . . . 713, 716, 720 EXTI_SWIER . . . . . . . . . . . . . . . . . 714, 717, 721 F FDCAN_ TXBCIE . . . . . . . . . . . . . . . . . . . . 2467 FDCAN_CCCR . . . . . . . . . . . . . . . . . . . . . . 2435 FDCAN_CREL . . . . . . . . . . . . . . . . . . . . . . 2431 FDCAN_DBTP . . . . . . . . . . . . . . . . . . . . . . 2432 FDCAN_ECR . . . . . . . . . . . . . . . . . . . . . . . 2440 FDCAN_ENDN . . . . . . . . . . . . . . . . . . . . . . 2432 FDCAN_GFC . . . . . . . . . . . . . . . . . . . . . . . 2451 FDCAN_HPMS . . . . . . . . . . . . . . . . . . . . . . 2454 FDCAN_IE . . . . . . . . . . . . . . . . . . . . . . . . . . 2446 FDCAN_ILE . . . . . . . . . . . . . . . . . . . . . . . . . 2450 FDCAN_ILS . . . . . . . . . . . . . . . . . . . . . . . . . 2449 FDCAN_IR . . . . . . . . . . . . . . . . . . . . . . . . . 2443 FDCAN_NBTP . . . . . . . . . . . . . . . . . . . . . . 2436 FDCAN_NDAT1 . . . . . . . . . . . . . . . . . . . . . 2454 FDCAN_NDAT2 . . . . . . . . . . . . . . . . . . . . . 2455 FDCAN_PSR . . . . . . . . . . . . . . . . . . . . . . . . 2441 FDCAN_RWD . . . . . . . . . . . . . . . . . . . . . . . 2434 FDCAN_RXBC . . . . . . . . . . . . . . . . . . . . . . 2457 FDCAN_RXESC . . . . . . . . . . . . . . . . . . . . . 2460 FDCAN_RXF0A . . . . . . . . . . . . . . . . . . . . . 2457 FDCAN_RXF0C . . . . . . . . . . . . . . . . . . . . . 2455 DocID029587 Rev 3 3169/3178 Index RM0433 FDCAN_RXF0S . . . . . . . . . . . . . . . . . . . . . .2456 FDCAN_RXF1A . . . . . . . . . . . . . . . . . . . . . .2460 FDCAN_RXF1C . . . . . . . . . . . . . . . . . . . . . .2458 FDCAN_RXF1S . . . . . . . . . . . . . . . . . . . . . .2459 FDCAN_SIDFC . . . . . . . . . . . . . . . . . . . . . .2452 FDCAN_TDCR . . . . . . . . . . . . . . . . . . . . . . .2443 FDCAN_TEST . . . . . . . . . . . . . . . . . . . . . . .2433 FDCAN_TOCC . . . . . . . . . . . . . . . . . . . . . . .2439 FDCAN_TOCV . . . . . . . . . . . . . . . . . . . . . . .2439 FDCAN_TSCC . . . . . . . . . . . . . . . . . . . . . . .2437 FDCAN_TSCV . . . . . . . . . . . . . . . . . . . . . . .2438 FDCAN_TTCPT . . . . . . . . . . . . . . . . . . . . . .2488 FDCAN_TTCSM . . . . . . . . . . . . . . . . . . . . .2488 FDCAN_TTCTC . . . . . . . . . . . . . . . . . . . . . .2487 FDCAN_TTIE . . . . . . . . . . . . . . . . . . . . . . . .2481 FDCAN_TTILS . . . . . . . . . . . . . . . . . . . . . . .2483 FDCAN_TTIR . . . . . . . . . . . . . . . . . . . . . . . .2479 FDCAN_TTLGT . . . . . . . . . . . . . . . . . . . . . .2487 FDCAN_TTMLM . . . . . . . . . . . . . . . . . . . . .2473 FDCAN_TTOCF . . . . . . . . . . . . . . . . . . . . . .2472 FDCAN_TTOCN . . . . . . . . . . . . . . . . . . . . .2476 FDCAN_TTOST . . . . . . . . . . . . . . . . . . . . . .2484 FDCAN_TTRMC . . . . . . . . . . . . . . . . . . . . .2471 FDCAN_TTTMC . . . . . . . . . . . . . . . . . . . . . .2470 FDCAN_TTTMK . . . . . . . . . . . . . . . . . . . . . .2478 FDCAN_TTTS . . . . . . . . . . . . . . . . . . . . . . .2489 FDCAN_TURCF . . . . . . . . . . . . . . . . . . . . . .2474 FDCAN_TURNA . . . . . . . . . . . . . . . . . . . . .2486 FDCAN_TXBAR . . . . . . . . . . . . . . . . . . . . . .2465 FDCAN_TXBC . . . . . . . . . . . . . . . . . . . . . . .2461 FDCAN_TXBCF . . . . . . . . . . . . . . . . . . . . . .2466 FDCAN_TXBCR . . . . . . . . . . . . . . . . . . . . . .2465 FDCAN_TXBRP . . . . . . . . . . . . . . . . . . . . . .2464 FDCAN_TXBTIE . . . . . . . . . . . . . . . . . . . . .2467 FDCAN_TXBTO . . . . . . . . . . . . . . . . . . . . . .2466 FDCAN_TXEFA . . . . . . . . . . . . . . . . . . . . . .2469 FDCAN_TXEFC . . . . . . . . . . . . . . . . . . . . . .2468 FDCAN_TXEFS . . . . . . . . . . . . . . . . . . . . . .2469 FDCAN_TXESC . . . . . . . . . . . . . . . . . . . . . .2463 FDCAN_TXFQS . . . . . . . . . . . . . . . . . . . . . .2462 FDCAN_XIDAM . . . . . . . . . . . . . . . . . . . . . .2453 FDCAN_XIDFC . . . . . . . . . . . . . . . . . . . . . .2452 FLASH_ACR . . . . . . . . . . . . . . . . . . . . . . . . .140 FLASH_BOOT7_CUR . . . . . . . . . . . . . . . . . .161 FLASH_BOOT7_PRG . . . . . . . . . . . . . . . . . .161 FLASH_CCR_A . . . . . . . . . . . . . . . . . . . . . . .149 FLASH_CCR_B . . . . . . . . . . . . . . . . . . . . . . .173 FLASH_CR_A . . . . . . . . . . . . . . . . . . . . . . . .142 FLASH_CRCCR_A . . . . . . . . . . . . . . . . . . . .162 FLASH_CRCCR_B . . . . . . . . . . . . . . . . . . . .178 FLASH_CRCDATA_A . . . . . . . . . . . . . . . . . .164 FLASH_CRCEADD_A . . . . . . . . . . . . . . . . . .164 3170/3178 FLASH_CRCEADD_B . . . . . . . . . . . . . . . . . . 180 FLASH_CRCSADD_A . . . . . . . . . . . . . . . . . . 163 FLASH_CRCSADD_B . . . . . . . . . . . . . . . . . . 179 FLASH_ECC_FA_A . . . . . . . . . . . . . . . 165, 173 FLASH_ECC_FA_B . . . . . . . . . . . . . . . . . . . 180 FLASH_FKEYR_B . . . . . . . . . . . . . . . . . . . . 166 FLASH_FLASH_CR_B . . . . . . . . . . . . . . . . . 166 FLASH_KEYR_A . . . . . . . . . . . . . . . . . . . . . . 141 FLASH_OPTCCR . . . . . . . . . . . . . . . . . . . . . 156 FLASH_OPTCR . . . . . . . . . . . . . . . . . . . . . . 150 FLASH_OPTKEYR . . . . . . . . . . . . . . . . . . . . 142 FLASH_OPTSR_CUR . . . . . . . . . . . . . . . . . . 151 FLASH_OPTSR_PRG . . . . . . . . . . . . . . . . . . 154 FLASH_PRAR_CUR_A . . . . . . . . . . . . . . . . . 157 FLASH_PRAR_CUR_B . . . . . . . . . . . . . . . . . 174 FLASH_PRAR_PRG_A . . . . . . . . . . . . . . . . . 158 FLASH_PRAR_PRG_B . . . . . . . . . . . . . . . . . 175 FLASH_SCAR_CUR_A . . . . . . . . . . . . . . . . . 158 FLASH_SCAR_CUR_B . . . . . . . . . . . . . . . . . 175 FLASH_SCAR_PRG_A . . . . . . . . . . . . . . . . . 159 FLASH_SCAR_PRG_B . . . . . . . . . . . . . . . . . 176 FLASH_SR_A . . . . . . . . . . . . . . . . . . . . . . . . 146 FLASH_SR_B . . . . . . . . . . . . . . . . . . . . . . . . 170 FLASH_WPSn_CUR_A . . . . . . . . . . . . . . . . 160 FLASH_WPSn_CUR_B . . . . . . . . . . . . . . . . 177 FLASH_WPSn_PRG_A . . . . . . . . . . . . . . . . 160 FLASH_WPSn_PRG_B . . . . . . . . . . . . . . . . 177 FMC_BCR1..4 . . . . . . . . . . . . . . . . . . . . . . . . 778 FMC_BTR1..4 . . . . . . . . . . . . . . . . . . . . . . . . 782 FMC_BWTR1..4 . . . . . . . . . . . . . . . . . . . . . . 785 FMC_ECCR . . . . . . . . . . . . . . . . . . . . . . . . . 798 FMC_PATT . . . . . . . . . . . . . . . . . . . . . . . . . . 797 FMC_PCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 FMC_PMEM . . . . . . . . . . . . . . . . . . . . . . . . . 795 FMC_SDCMR . . . . . . . . . . . . . . . . . . . . . . . . 813 FMC_SDCR1,2 . . . . . . . . . . . . . . . . . . . . . . . 810 FMC_SDRTR . . . . . . . . . . . . . . . . . . . . . . . . 814 FMC_SDSR . . . . . . . . . . . . . . . . . . . . . . . . . . 816 FMC_SDTR1,2 . . . . . . . . . . . . . . . . . . . . . . . 811 FMC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 FMPI2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . 1944 G GPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 499 GPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 498 GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 496 GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 496 GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 497 GPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 494 GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 496 GPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 495 DocID029587 Rev 3 RM0433 Index GPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . .494 GPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . .495 H HASH_CR . . . . . . . . . . . . . . . . . . . . . . . . . .1281 HASH_CSRx . . . . . . . . . . . . . . . . . . . . . . . .1290 HASH_DIN . . . . . . . . . . . . . . . . . . . . . . . . . .1284 HASH_HR0 . . . . . . . . . . . . . . . . . . . . . . . . .1286 HASH_HR1 . . . . . . . . . . . . . . . . . . . .1286, 1288 HASH_HR2 . . . . . . . . . . . . . . . . . . . . 1287-1288 HASH_HR3 . . . . . . . . . . . . . . . . . . . . . . . . .1287 HASH_HR4 . . . . . . . . . . . . . . . . . . . . . . . . .1287 HASH_IMR . . . . . . . . . . . . . . . . . . . . . . . . . .1288 HASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . .1289 HASH_STR . . . . . . . . . . . . . . . . . . . . . . . . .1285 HRTIM_ADC1R . . . . . . . . . . . . . . . . . . . . . .1445 HRTIM_ADC2R . . . . . . . . . . . . . . . . . . . . . .1446 HRTIM_ADC3R . . . . . . . . . . . . . . . . . . . . . .1447 HRTIM_ADC4R . . . . . . . . . . . . . . . . . . . . . .1449 HRTIM_BDMADR . . . . . . . . . . . . . . . . . . . .1457 HRTIM_BDMUPR . . . . . . . . . . . . . . . . . . . .1455 HRTIM_BDTxUPR . . . . . . . . . . . . . . . . . . . .1456 HRTIM_BMCMPR . . . . . . . . . . . . . . . . . . . .1440 HRTIM_BMCR . . . . . . . . . . . . . . . . . . . . . . .1436 HRTIM_BMPER . . . . . . . . . . . . . . . . . . . . . .1440 HRTIM_BMTRGR . . . . . . . . . . . . . . . . . . . .1438 HRTIM_CHPxR . . . . . . . . . . . . . . . . . . . . . .1417 HRTIM_CMP1CxR . . . . . . . . . . . . . . . . . . . .1402 HRTIM_CMP1xR . . . . . . . . . . . . . . . . . . . . .1401 HRTIM_CMP2xR . . . . . . . . . . . . . . . . . . . . .1402 HRTIM_CMP3xR . . . . . . . . . . . . . . . . . . . . .1403 HRTIM_CMP4xR . . . . . . . . . . . . . . . . . . . . .1403 HRTIM_CNTxR . . . . . . . . . . . . . . . . . . . . . .1400 HRTIM_CPT1xCR . . . . . . . . . . . . . . . . . . . .1419 HRTIM_CPT1xR . . . . . . . . . . . . . . . . . . . . .1404 HRTIM_CPT2xCR . . . . . . . . . . . . . . . . . . . .1420 HRTIM_CPT2xR . . . . . . . . . . . . . . . . . . . . .1404 HRTIM_CR1 . . . . . . . . . . . . . . . . . . . . . . . . .1427 HRTIM_CR2 . . . . . . . . . . . . . . . . . . . . . . . . .1429 HRTIM_DTxR . . . . . . . . . . . . . . . . . . . . . . . .1405 HRTIM_EECR1 . . . . . . . . . . . . . . . . . . . . . .1441 HRTIM_EECR2 . . . . . . . . . . . . . . . . . . . . . .1443 HRTIM_EECR3 . . . . . . . . . . . . . . . . . . . . . .1444 HRTIM_EEFxR1 . . . . . . . . . . . . . . . . . . . . .1411 HRTIM_EEFxR2 . . . . . . . . . . . . . . . . . . . . .1413 HRTIM_FLTINR1 . . . . . . . . . . . . . . . . . . . . .1451 HRTIM_FLTINR2 . . . . . . . . . . . . . . . . . . . . .1453 HRTIM_FLTxR . . . . . . . . . . . . . . . . . . . . . . .1426 HRTIM_ICR . . . . . . . . . . . . . . . . . . . . . . . . .1431 HRTIM_IER . . . . . . . . . . . . . . . . . . . . . . . . .1432 HRTIM_ISR . . . . . . . . . . . . . . . . . . . . . . . . .1430 HRTIM_MCMP1R . . . . . . . . . . . . . . . . . . . . 1387 HRTIM_MCMP2R . . . . . . . . . . . . . . . . . . . . 1388 HRTIM_MCMP3R . . . . . . . . . . . . . . . . . . . . 1388 HRTIM_MCMP4R . . . . . . . . . . . . . . . . . . . . 1389 HRTIM_MCNTR . . . . . . . . . . . . . . . . . . . . . 1386 HRTIM_MCR . . . . . . . . . . . . . . . . . . . . . . . . 1379 HRTIM_MDIER . . . . . . . . . . . . . . . . . . . . . . 1384 HRTIM_MICR . . . . . . . . . . . . . . . . . . . . . . . 1383 HRTIM_MISR . . . . . . . . . . . . . . . . . . . . . . . 1382 HRTIM_MPER . . . . . . . . . . . . . . . . . . . . . . . 1386 HRTIM_MREP . . . . . . . . . . . . . . . . . . . . . . . 1387 HRTIM_ODISR . . . . . . . . . . . . . . . . . . . . . . 1434 HRTIM_ODSR . . . . . . . . . . . . . . . . . . . . . . . 1435 HRTIM_OENR . . . . . . . . . . . . . . . . . . . . . . . 1433 HRTIM_OUTxR . . . . . . . . . . . . . . . . . . . . . . 1423 HRTIM_PERxR . . . . . . . . . . . . . . . . . . . . . . 1400 HRTIM_REPxR . . . . . . . . . . . . . . . . . . . . . . 1401 HRTIM_RSTAR . . . . . . . . . . . . . . . . . . . . . . 1414 HRTIM_RSTBR . . . . . . . . . . . . . . . . . . . . . . 1416 HRTIM_RSTCR . . . . . . . . . . . . . . . . . . . . . . 1416 HRTIM_RSTDR . . . . . . . . . . . . . . . . . . . . . . 1416 HRTIM_RSTER . . . . . . . . . . . . . . . . . . . . . . 1417 HRTIM_RSTx1R . . . . . . . . . . . . . . . . . . . . . 1409 HRTIM_RSTx2R . . . . . . . . . . . . . . . . . . . . . 1410 HRTIM_SETx1R . . . . . . . . . . . . . . . . . . . . . 1407 HRTIM_SETx2R . . . . . . . . . . . . . . . . . . . . . 1409 HRTIM_TIMxCR . . . . . . . . . . . . . . . . . . . . . 1390 HRTIM_TIMxDIER . . . . . . . . . . . . . . . . . . . 1397 HRTIM_TIMxICR . . . . . . . . . . . . . . . . . . . . . 1396 HRTIM_TIMxISR . . . . . . . . . . . . . . . . . . . . . 1394 HSEM_CnICR . . . . . . . . . . . . . . . . . . . . . . . . 480 HSEM_CnIER . . . . . . . . . . . . . . . . . . . . . . . . 480 HSEM_CnISR . . . . . . . . . . . . . . . . . . . . . . . . 480 HSEM_CnMISR . . . . . . . . . . . . . . . . . . . . . . 481 HSEM_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 HSEM_KEYR . . . . . . . . . . . . . . . . . . . . . . . . 482 HSEM_R0 - HSEM_R31 . . . . . . . . . . . . . . . . 478 HSEM_RLR0 - HSEM_RLR31 . . . . . . . . . . . 479 I I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934 I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937 I2C_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946 I2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1940 I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 1941 I2C_PECR . . . . . . . . . . . . . . . . . . . . . . . . . . 1947 I2C_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . . 1948 I2C_TIMEOUTR . . . . . . . . . . . . . . . . . . . . . 1943 I2C_TIMINGR . . . . . . . . . . . . . . . . . . . . . . . 1942 I2C_TXDR . . . . . . . . . . . . . . . . . . . . . . . . . . 1948 DocID029587 Rev 3 3171/3178 Index RM0433 I2Cx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .1937 IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . .1829 IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . .1830 IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . .1831 IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .1832 IWDG_WINR . . . . . . . . . . . . . . . . . . . . . . . .1833 J JPEG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .1181 JPEG_CONFR0 . . . . . . . . . . . . . . . . . . . . . .1176 JPEG_CONFR1 . . . . . . . . . . . . . . . . . . . . . .1176 JPEG_CONFR2 . . . . . . . . . . . . . . . . . . . . . .1177 JPEG_CONFR3 . . . . . . . . . . . . . . . . . . . . . .1178 JPEG_CONFR4-7 . . . . . . . . . . . . . . . . . . . .1178 JPEG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . .1179 JPEG_DIR . . . . . . . . . . . . . . . . . . . . . . . . . .1182 JPEG_DOR . . . . . . . . . . . . . . . . . . . . . . . . .1182 JPEG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .1180 L LPTIM_ARR . . . . . . . . . . . . . . . . . . . . . . . . .1814 LPTIM_CFGR . . . . . . . . . . . . . . . . . . . . . . .1809 LPTIM_CMP . . . . . . . . . . . . . . . . . . . . . . . . .1814 LPTIM_CNT . . . . . . . . . . . . . . . . . . . . . . . . .1814 LPTIM_CR . . . . . . . . . . . . . . . . . . . . . . . . . .1812 LPTIM_ICR . . . . . . . . . . . . . . . . . . . . . . . . .1808 LPTIM_IER . . . . . . . . . . . . . . . . . . . . . . . . . .1808 LPTIM_ISR . . . . . . . . . . . . . . . . . . . . . . . . . .1807 LPUART_PRESC . . . . . . . . . . . . . . . . . . . . .2072 LTDC_AWCR . . . . . . . . . . . . . . . . . . . . . . . .1149 LTDC_BCCR . . . . . . . . . . . . . . . . . . . . . . . .1152 LTDC_BPCR . . . . . . . . . . . . . . . . . . . . . . . .1148 LTDC_CDSR . . . . . . . . . . . . . . . . . . . . . . . .1156 LTDC_CPSR . . . . . . . . . . . . . . . . . . . . . . . .1155 LTDC_GCR . . . . . . . . . . . . . . . . . . . . . . . . .1150 LTDC_ICR . . . . . . . . . . . . . . . . . . . . . . . . . .1154 LTDC_IER . . . . . . . . . . . . . . . . . . . . . . . . . .1153 LTDC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . .1154 LTDC_LIPCR . . . . . . . . . . . . . . . . . . . . . . . .1155 LTDC_LxBFCR . . . . . . . . . . . . . . . . . . . . . .1163 LTDC_LxCACR . . . . . . . . . . . . . . . . . . . . . .1161 LTDC_LxCFBAR . . . . . . . . . . . . . . . . . . . . .1164 LTDC_LxCFBLNR . . . . . . . . . . . . . . . . . . . .1165 LTDC_LxCFBLR . . . . . . . . . . . . . . . . . . . . .1164 LTDC_LxCKCR . . . . . . . . . . . . . . . . . . . . . .1159 LTDC_LxCLUTWR . . . . . . . . . . . . . . . . . . . .1166 LTDC_LxCR . . . . . . . . . . . . . . . . . . . . . . . . .1157 LTDC_LxDCCR . . . . . . . . . . . . . . . . . . . . . .1161 LTDC_LxPFCR . . . . . . . . . . . . . . . . . . . . . .1160 LTDC_LxWHPCR . . . . . . . . . . . . . . . . . . . .1157 LTDC_LxWVPCR . . . . . . . . . . . . . . . . . . . . .1159 3172/3178 LTDC_SRCR . . . . . . . . . . . . . . . . . . . . . . . . 1152 LTDC_SSCR . . . . . . . . . . . . . . . . . . . . . . . . 1148 LTDC_TWCR . . . . . . . . . . . . . . . . . . . . . . . 1150 M M7_DWT_CIDR0 . . . . . . . . . . . . . . . . . . . . 3099 M7_DWT_CIDR1 . . . . . . . . . . . . . . . . . . . . 3099 M7_DWT_CIDR2 . . . . . . . . . . . . . . . . . . . . 3100 M7_DWT_CIDR3 . . . . . . . . . . . . . . . . . . . . 3100 M7_DWT_COMPx . . . . . . . . . . . . . . . . . . . . 3095 M7_DWT_CPICNT . . . . . . . . . . . . . . . . . . . 3092 M7_DWT_CTRL . . . . . . . . . . . . . . . . . . . . . 3090 M7_DWT_CYCCNT . . . . . . . . . . . . . . . . . . 3092 M7_DWT_EXCCNT . . . . . . . . . . . . . . . . . . 3093 M7_DWT_FOLDCNT . . . . . . . . . . . . . . . . . 3094 M7_DWT_FUNCTx . . . . . . . . . . . . . . . . . . . 3095 M7_DWT_LSUCNT . . . . . . . . . . . . . . . . . . . 3094 M7_DWT_MASKx . . . . . . . . . . . . . . . . . . . . 3095 M7_DWT_PCSR . . . . . . . . . . . . . . . . . . . . . 3094 M7_DWT_PIDR0 . . . . . . . . . . . . . . . . . . . . . 3097 M7_DWT_PIDR1 . . . . . . . . . . . . . . . . . . . . . 3098 M7_DWT_PIDR2 . . . . . . . . . . . . . . . . . . . . . 3098 M7_DWT_PIDR3 . . . . . . . . . . . . . . . . . . . . . 3098 M7_DWT_PIDR4 . . . . . . . . . . . . . . . . . . . . . 3097 M7_DWT_SLPCNT . . . . . . . . . . . . . . . . . . . 3093 M7_ETM_AUTHSTAT . . . . . . . . . . . . . . . . . 3141 M7_ETM_CCCTL . . . . . . . . . . . . . . . . . . . . 3125 M7_ETM_CIDR0 . . . . . . . . . . . . . . . . . . . . . 3146 M7_ETM_CIDR1 . . . . . . . . . . . . . . . . . . . . . 3146 M7_ETM_CIDR2 . . . . . . . . . . . . . . . . . . . . . 3147 M7_ETM_CIDR3 . . . . . . . . . . . . . . . . . . . . . 3147 M7_ETM_CLAIMCLR . . . . . . . . . . . . . . . . . 3140 M7_ETM_CLAIMSET . . . . . . . . . . . . . . . . . 3139 M7_ETM_CNTRLDV . . . . . . . . . . . . . . . . . . 3128 M7_ETM_CONFIG . . . . . . . . . . . . . . . . . . . 3121 M7_ETM_DEVARCH . . . . . . . . . . . . . . . . . 3142 M7_ETM_DEVID . . . . . . . . . . . . . . . . . . . . . 3142 M7_ETM_DEVTYPE . . . . . . . . . . . . . . . . . . 3143 M7_ETM_EVENTCTL0 . . . . . . . . . . . . . . . . 3122 M7_ETM_EVENTCTL1 . . . . . . . . . . . . . . . . 3122 M7_ETM_IDR0 . . . . . . . . . . . . . . . . . . . . . . 3131 M7_ETM_IDR1 . . . . . . . . . . . . . . . . . . . . . . 3132 M7_ETM_IDR10 . . . . . . . . . . . . . . . . . . . . . 3129 M7_ETM_IDR11 . . . . . . . . . . . . . . . . . . . . . 3129 M7_ETM_IDR12 . . . . . . . . . . . . . . . . . . . . . 3130 M7_ETM_IDR13 . . . . . . . . . . . . . . . . . . . . . 3130 M7_ETM_IDR2 . . . . . . . . . . . . . . . . . . . . . . 3132 M7_ETM_IDR3 . . . . . . . . . . . . . . . . . . . . . . 3133 M7_ETM_IDR4 . . . . . . . . . . . . . . . . . . . . . . 3134 M7_ETM_IDR5 . . . . . . . . . . . . . . . . . . . . . . 3134 M7_ETM_IDR8 . . . . . . . . . . . . . . . . . . . . . . 3128 DocID029587 Rev 3 RM0433 Index M7_ETM_IDR9 . . . . . . . . . . . . . . . . . . . . . .3129 M7_ETM_IMSPEC0 . . . . . . . . . . . . . . . . . . .3130 M7_ETM_LAR . . . . . . . . . . . . . . . . . . . . . . .3140 M7_ETM_LSR . . . . . . . . . . . . . . . . . . . . . . .3141 M7_ETM_PDC . . . . . . . . . . . . . . . . . . . . . . .3138 M7_ETM_PDS . . . . . . . . . . . . . . . . . . . . . . .3139 M7_ETM_PIDR0 . . . . . . . . . . . . . . . . . . . . .3144 M7_ETM_PIDR1 . . . . . . . . . . . . . . . . . . . . .3144 M7_ETM_PIDR2 . . . . . . . . . . . . . . . . . . . . .3145 M7_ETM_PIDR3 . . . . . . . . . . . . . . . . . . . . .3145 M7_ETM_PIDR4 . . . . . . . . . . . . . . . . . . . . .3143 M7_ETM_PRGCTL . . . . . . . . . . . . . . . . . . .3119 M7_ETM_PROCSEL . . . . . . . . . . . . . . . . . .3120 M7_ETM_RSCTL2 . . . . . . . . . . . . . . . . . . . .3135 M7_ETM_RSCTL3 . . . . . . . . . . . . . . . . . . . .3136 M7_ETM_SSCC0 . . . . . . . . . . . . . . . . . . . . .3136 M7_ETM_SSCS0 . . . . . . . . . . . . . . . . . . . . .3137 M7_ETM_SSPCIC0 . . . . . . . . . . . . . . . . . . .3138 M7_ETM_STALLCTL . . . . . . . . . . . . . . . . . .3123 M7_ETM_STAT . . . . . . . . . . . . . . . . . . . . . .3120 M7_ETM_SYNCP . . . . . . . . . . . . . . . . . . . .3124 M7_ETM_TRACEID . . . . . . . . . . . . . . . . . . .3125 M7_ETM_TSCTL . . . . . . . . . . . . . . . . . . . . .3124 M7_ETM_VICTL . . . . . . . . . . . . . . . . . . . . .3126 M7_ETM_VIPCSSCTL . . . . . . . . . . . . . . . . .3127 M7_ETM_VISSCTL . . . . . . . . . . . . . . . . . . .3127 M7_FPB_CIDR0 . . . . . . . . . . . . . . . . . . . . .3116 M7_FPB_CIDR1 . . . . . . . . . . . . . . . . . . . . .3116 M7_FPB_CIDR2 . . . . . . . . . . . . . . . . . . . . .3117 M7_FPB_CIDR3 . . . . . . . . . . . . . . . . . . . . .3117 M7_FPB_COMPx . . . . . . . . . . . . . . . . . . . . .3113 M7_FPB_CTRL . . . . . . . . . . . . . . . . . . . . . .3111 M7_FPB_PIDR0 . . . . . . . . . . . . . . . . . . . . . .3114 M7_FPB_PIDR1 . . . . . . . . . . . . . . . . . . . . . .3114 M7_FPB_PIDR2 . . . . . . . . . . . . . . . . . . . . . .3115 M7_FPB_PIDR3 . . . . . . . . . . . . . . . . . . . . . .3115 M7_FPB_PIDR4 . . . . . . . . . . . . . . . . . . . . . .3113 M7_FPB_REMAP . . . . . . . . . . . . . . . . . . . .3112 M7_ITM_CIDR0 . . . . . . . . . . . . . . . . . . . . . .3108 M7_ITM_CIDR1 . . . . . . . . . . . . . . . . . . . . . .3109 M7_ITM_CIDR2 . . . . . . . . . . . . . . . . . . . . . .3109 M7_ITM_CIDR3 . . . . . . . . . . . . . . . . . . . . . .3110 M7_ITM_PIDR0 . . . . . . . . . . . . . . . . . . . . . .3106 M7_ITM_PIDR1 . . . . . . . . . . . . . . . . . . . . . .3107 M7_ITM_PIDR2 . . . . . . . . . . . . . . . . . . . . . .3107 M7_ITM_PIDR3 . . . . . . . . . . . . . . . . . . . . . .3108 M7_ITM_PIDR4 . . . . . . . . . . . . . . . . . . . . . .3106 M7_ITM_STIMx . . . . . . . . . . . . . . . . . . . . . .3103 M7_ITM_TCR . . . . . . . . . . . . . . . . . . . . . . . .3104 M7_ITM_TER . . . . . . . . . . . . . . . . . . . . . . . .3104 M7_ITM_TPR . . . . . . . . . . . . . . . . . . . . . . . .3104 M7_PILROM_CIDR0 . . . . . . . . . . . . . . . . . .3081 M7_PILROM_CIDR1 . . . . . . . . . . . . . . . . . . 3082 M7_PILROM_CIDR2 . . . . . . . . . . . . . . . . . . 3082 M7_PILROM_CIDR3 . . . . . . . . . . . . . . . . . . 3083 M7_PILROM_MEMTYPE . . . . . . . . . . . . . . 3079 M7_PILROM_PIDR0 . . . . . . . . . . . . . . . . . . 3080 M7_PILROM_PIDR1 . . . . . . . . . . . . . . . . . . 3080 M7_PILROM_PIDR2 . . . . . . . . . . . . . . . . . . 3080 M7_PILROM_PIDR3 . . . . . . . . . . . . . . . . . . 3081 M7_PILROM_PIDR4 . . . . . . . . . . . . . . . . . . 3079 M7_PPBROM_CIDR0 . . . . . . . . . . . . . . . . . 3087 M7_PPBROM_CIDR1 . . . . . . . . . . . . . . . . . 3087 M7_PPBROM_CIDR2 . . . . . . . . . . . . . . . . . 3088 M7_PPBROM_CIDR3 . . . . . . . . . . . . . . . . . 3088 M7_PPBROM_MEMTYPE . . . . . . . . . . . . . 3084 M7_PPBROM_PIDR0 . . . . . . . . . . . . . . . . . 3085 M7_PPBROM_PIDR1 . . . . . . . . . . . . . . . . . 3085 M7_PPBROM_PIDR2 . . . . . . . . . . . . . . . . . 3086 M7_PPBROM_PIDR3 . . . . . . . . . . . . . . . . . 3086 M7_PPBROM_PIDR4 . . . . . . . . . . . . . . . . . 3084 MDIOS_CLRFR . . . . . . . . . . . . . . . . . . . . . . 2283 MDIOS_CRDFR . . . . . . . . . . . . . . . . . . . . . 2281 MDIOS_CWRFR . . . . . . . . . . . . . . . . . . . . . 2280 MDIOS_DINR0-MDIOS_DINR31 . . . . . . . . 2284 MDIOS_DOUTR0-MDIOS_DOUTR31 . . . . 2284 MDIOS_RDFR . . . . . . . . . . . . . . . . . . . . . . . 2281 MDIOS_SR . . . . . . . . . . . . . . . . . . . . . . . . . 2282 MMC_CONTROL . . . . . . . . . . . . . . . . . . . . 2863 MMC_RX_INTERRUPT . . . . . . . . . . . . . . . 2864 MMC_RX_INTERRUPT_MASK . . . . . . . . . 2867 MMC_TX_INTERRUPT . . . . . . . . . . . . . . . . 2865 MMC_TX_INTERRUPT_MASK . . . . . . . . . 2868 N NBTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2436 O OPAMP_OR . . . . . . . . . . . . . . . . . . . . . . . . 1047 OPAMP1_CSR . . . . . . . . . . . . . . . . . . . . . . 1044 OPAMP1_HSOTR . . . . . . . . . . . . . . . . . . . . 1047 OPAMP1_OTR . . . . . . . . . . . . . . . . . . . . . . 1046 OPAMP2_CSR . . . . . . . . . . . . . . . . . . . . . . 1047 OPAMP2_HSOTR . . . . . . . . . . . . . . . . . . . . 1050 OPAMP2_OTR . . . . . . . . . . . . . . . . . . . . . . 1049 OTG_CID . . . . . . . . . . . . . . . . . . . . . . . . . . 2556 OTG_DAINT . . . . . . . . . . . . . . . . . . . . . . . . 2581 OTG_DAINTMSK . . . . . . . . . . . . . . . . . . . . 2582 OTG_DCFG . . . . . . . . . . . . . . . . . . . . . . . . 2574 OTG_DCTL . . . . . . . . . . . . . . . . . . . . . . . . . 2576 OTG_DEACHINT . . . . . . . . . . . . . . . . . . . . 2585 OTG_DEACHINTMSK . . . . . . . . . . . . . . . . 2585 OTG_DIEPCTLx . . . . . . . . . . . . . . . . . . . . . 2586 DocID029587 Rev 3 3173/3178 Index RM0433 OTG_DIEPEMPMSK . . . . . . . . . . . . . . . . . .2584 OTG_DIEPINTx . . . . . . . . . . . . . . . . . . . . . .2592 OTG_DIEPMSK . . . . . . . . . . . . . . . . . . . . . .2579 OTG_DIEPTSIZ0 . . . . . . . . . . . . . . . . . . . . .2595 OTG_DIEPTSIZx . . . . . . . . . . . . . . . .2595, 2597 OTG_DIEPTXF0 . . . . . . . . . . . . . . . . . . . . .2552 OTG_DIEPTXFx . . . . . . . . . . . . . . . . . . . . .2561 OTG_DOEPCTL0 . . . . . . . . . . . . . . . . . . . .2588 OTG_DOEPCTLx . . . . . . . . . . . . . . . . . . . . .2590 OTG_DOEPINTx . . . . . . . . . . . . . . . . . . . . .2593 OTG_DOEPMSK . . . . . . . . . . . . . . . . . . . . .2580 OTG_DOEPTSIZ0 . . . . . . . . . . . . . . . . . . . .2596 OTG_DOEPTSIZx . . . . . . . . . . . . . . . . . . . .2599 OTG_DSTS . . . . . . . . . . . . . . . . . . . . . . . . .2578 OTG_DTHRCTL . . . . . . . . . . . . . . . . . . . . . .2583 OTG_DTXFSTSx . . . . . . . . . . . . . . . . . . . . .2598 OTG_DVBUSDIS . . . . . . . . . . . . . . . . . . . . .2582 OTG_DVBUSPULSE . . . . . . . . . . . . . . . . . .2583 OTG_GAHBCFG . . . . . . . . . . . . . . . . . . . . .2535 OTG_GCCFG . . . . . . . . . . . . . . . . . . . . . . .2555 OTG_GI2CCTL . . . . . . . . . . . . . . . . . . . . . .2553 OTG_GINTMSK . . . . . . . . . . . . . . . . . . . . . .2547 OTG_GINTSTS . . . . . . . . . . . . . . . . . . . . . .2542 OTG_GLPMCFG . . . . . . . . . . . . . . . . . . . . .2556 OTG_GOTGCTL . . . . . . . . . . . . . . . . . . . . .2532 OTG_GOTGINT . . . . . . . . . . . . . . . . . . . . . .2534 OTG_GRSTCTL . . . . . . . . . . . . . . . . . . . . . .2540 OTG_GRXFSIZ . . . . . . . . . . . . . . . . . . . . . .2551 OTG_GRXSTSP . . . . . . . . . . . . . . . . . . . . .2550 OTG_GRXSTSR . . . . . . . . . . . . . . . . . . . . .2550 OTG_GUSBCFG . . . . . . . . . . . . . . . . . . . . .2537 OTG_HAINT . . . . . . . . . . . . . . . . . . . . . . . . .2564 OTG_HAINTMSK . . . . . . . . . . . . . . . . . . . . .2565 OTG_HCCHARx . . . . . . . . . . . . . . . . . . . . .2568 OTG_HCDMAx . . . . . . . . . . . . . . . . . . . . . .2574 OTG_HCFG . . . . . . . . . . . . . . . . . . . . . . . . .2562 OTG_HCINTMSKx . . . . . . . . . . . . . . . . . . . .2571 OTG_HCINTx . . . . . . . . . . . . . . . . . . . . . . . .2570 OTG_HCSPLTx . . . . . . . . . . . . . . . . . . . . . .2569 OTG_HCTSIZx . . . . . . . . . . . . . . . . . . . . . . .2572 OTG_HFIR . . . . . . . . . . . . . . . . . . . . . . . . . .2562 OTG_HFNUM . . . . . . . . . . . . . . . . . . . . . . .2563 OTG_HNPTXFSIZ . . . . . . . . . . . . . . . . . . . .2552 OTG_HNPTXSTS . . . . . . . . . . . . . . . . . . . .2553 OTG_HPRT . . . . . . . . . . . . . . . . . . . . . . . . .2565 OTG_HPTXFSIZ . . . . . . . . . . . . . . . . . . . . .2561 OTG_HPTXSTS . . . . . . . . . . . . . . . . . . . . . .2564 OTG_PCGCCTL . . . . . . . . . . . . . . . . . . . . .2600 P purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . .1695 3174/3178 PWR_CSR . . . . . . . . . . . . . . . . . . 264, 268-269 Q QUADSPI _PIR . . . . . . . . . . . . . . . . . . . . . . . 847 QUADSPI _PSMAR . . . . . . . . . . . . . . . . . . . 846 QUADSPI _PSMKR . . . . . . . . . . . . . . . . . . . 846 QUADSPI_ABR . . . . . . . . . . . . . . . . . . . . . . . 845 QUADSPI_AR . . . . . . . . . . . . . . . . . . . . . . . . 844 QUADSPI_CCR . . . . . . . . . . . . . . . . . . . . . . 842 QUADSPI_CR . . . . . . . . . . . . . . . . . . . . . . . . 836 QUADSPI_DCR . . . . . . . . . . . . . . . . . . . . . . 839 QUADSPI_DLR . . . . . . . . . . . . . . . . . . . . . . . 841 QUADSPI_DR . . . . . . . . . . . . . . . . . . . . . . . . 845 QUADSPI_FCR . . . . . . . . . . . . . . . . . . . . . . . 841 QUADSPI_LPTR . . . . . . . . . . . . . . . . . . . . . . 847 QUADSPI_SR . . . . . . . . . . . . . . . . . . . . . . . . 840 R RCC_BDCR . . . . . . . . . . . . . . . . . . . . . . . . . 380 RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . . . . 344 RCC_CICR . . . . . . . . . . . . . . . . . . . . . . . . . . 378 RCC_CIER . . . . . . . . . . . . . . . . . . . . . . . . . . 374 RCC_CIFR . . . . . . . . . . . . . . . . . . . . . . . . . . 376 RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 RCC_CRRCR . . . . . . . . . . . . . . . . . . . . . . . . 343 RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 RCC_D1AHB1ENR . . . . . . . . . . . . . . . . . . . . 405 RCC_D1AHB1LPENR . . . . . . . . . . . . . . . . . . 427 RCC_D1AHB1RSTR . . . . . . . . . . . . . . . . . . . 383 RCC_D1APB1ENR . . . . . . . . . . . . . . . . . . . . 414 RCC_D1APB1LPENR . . . . . . . . . . . . . . 436-437 RCC_D1APB1RSTR . . . . . . . . . . . . . . . . . . . 390 RCC_D1CCIPR . . . . . . . . . . . . . . . . . . . . . . . 365 RCC_D1CFGR . . . . . . . . . . . . . . . . . . . . . . . 347 RCC_D2AHB1ENR . . . . . . . . . . . . . . . . . . . . 407 RCC_D2AHB1LPENR . . . . . . . . . . . . . . . . . . 429 RCC_D2AHB1RSTR . . . . . . . . . . . . . . . . . . . 385 RCC_D2AHB2ENR . . . . . . . . . . . . . . . . . . . . 409 RCC_D2AHB2LPENR . . . . . . . . . . . . . . . . . . 431 RCC_D2AHB2RSTR . . . . . . . . . . . . . . . . . . . 387 RCC_D2APB1HENR . . . . . . . . . . . . . . . . . . . 419 RCC_D2APB1HLPENR . . . . . . . . . . . . . . . . 441 RCC_D2APB1HRSTR . . . . . . . . . . . . . . . . . 394 RCC_D2APB1LENR . . . . . . . . . . . . . . . . . . . 415 RCC_D2APB1LRSTR . . . . . . . . . . . . . . . . . . 391 RCC_D2APB2ENR . . . . . . . . . . . . . . . . . . . . 421 RCC_D2APB2LPENR . . . . . . . . . . . . . . . . . . 443 RCC_D2APB2RSTR . . . . . . . . . . . . . . . . . . . 395 RCC_D2CCIP1R . . . . . . . . . . . . . . . . . . . . . . 366 RCC_D2CCIP2R . . . . . . . . . . . . . . . . . . . . . . 369 RCC_D2CFGR . . . . . . . . . . . . . . . . . . . . . . . 349 DocID029587 Rev 3 RM0433 Index RCC_D3AHB1ENR . . . . . . . . . . . . . . . . . . . .411 RCC_D3AHB1LPENR . . . . . . . . . . . . . . . . . .433 RCC_D3AHB1RSTR . . . . . . . . . . . . . . . . . . .388 RCC_D3AMR . . . . . . . . . . . . . . . . . . . . . . . . .400 RCC_D3APB1ENR . . . . . . . . . . . . . . . . . . . .424 RCC_D3APB1LPENR . . . . . . . . . . . . . . . . . .446 RCC_D3APB1RSTR . . . . . . . . . . . . . . . . . . .397 RCC_D3CCIPR . . . . . . . . . . . . . . . . . . . . . . .371 RCC_D3CFGR . . . . . . . . . . . . . . . . . . . . . . . .350 RCC_GCR . . . . . . . . . . . . . . . . . . . . . . . . . . .399 RCC_ICSCR . . . . . . . . . . . . . . . . . . . . . . . . .342 RCC_PLL1DIVR . . . . . . . . . . . . . . . . . . . . . .356 RCC_PLL1FRACR . . . . . . . . . . . . . . . . . . . . .358 RCC_PLL2DIVR . . . . . . . . . . . . . . . . . . . . . .359 RCC_PLL2FRACR . . . . . . . . . . . . . . . . . . . . .361 RCC_PLL3DIVR . . . . . . . . . . . . . . . . . . . . . .362 RCC_PLL3FRACR . . . . . . . . . . . . . . . . . . . . .364 RCC_PLLCFGR . . . . . . . . . . . . . . . . . . . . . . .353 RCC_PLLCKSELR . . . . . . . . . . . . . . . . . . . . .351 RCC_RSR . . . . . . . . . . . . . . . . . . . . . . . . . . .403 RNG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . .1196 RNG_DR . . . . . . . . . . . . . . . . . . . . . . . . . . .1198 RNG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .1197 RTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . .1865 RTC_ALRMBR . . . . . . . . . . . . . . . . . . . . . . .1866 RTC_ALRMBSSR . . . . . . . . . . . . . . . . . . . .1877 RTC_BKPxR . . . . . . . . . . . . . . . . . . . . . . . .1878 RTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . .1872 RTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .1857 RTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .1855 RTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . .1860 RTC_OR . . . . . . . . . . . . . . . . . . . . . . . . . . .1878 RTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . .1863 RTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . .1868 RTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . .1867 RTC_TR . . 261-263, 266-267, 1854, 2279-2280 RTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . .1870 RTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . .1871 RTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . .1869 RTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . .1867 RTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . .1864 RX_ALIGNMENT_ERROR_PACKETS . . . .2870 RX_CRC_ERROR_PACKETS . . . . . . . . . . .2870 RX_LPI_TRAN_CNTR . . . . . . . . . . . . . . . . .2872 RX_LPI_USEC_CNTR . . . . . . . . . . . . . . . . .2872 RX_UNICAST_PACKETS_GOOD . . . . . . . .2871 S SAI_ACLRFR . . . . . . . . . . . . . . . . . . . . . . . .2197 SAI_ACR1 . . . . . . . . . . . . . . . . . . . . . . . . . .2186 SAI_ACR2 . . . . . . . . . . . . . . . . . . . . . . . . . .2189 SAI_ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198 SAI_AFRCR . . . . . . . . . . . . . . . . . . . . . . . . 2191 SAI_AIM . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194 SAI_ASLOTR . . . . . . . . . . . . . . . . . . . . . . . 2193 SAI_ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2195 SAI_BCLRFR . . . . . . . . . . . . . . . . . . . . . . . 2197 SAI_BCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2186 SAI_BCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 2189 SAI_BDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198 SAI_BFRCR . . . . . . . . . . . . . . . . . . . . . . . . 2191 SAI_BIM . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194 SAI_BSLOTR . . . . . . . . . . . . . . . . . . . . . . . 2193 SAI_BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2195 SAI_GCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 2186 SAI_PDMCR . . . . . . . . . . . . . . . . . . . . . . . . 2199 SAI_PDMDLY . . . . . . . . . . . . . . . . . . . . . . . 2200 SDMMC_ACKTIMER . . . . . . . . . . . . . . . . . 2360 SDMMC_ARGR . . . . . . . . . . . . . . . . . . . . . 2344 SDMMC_CLKCR . . . . . . . . . . . . . . . . . . . . . 2342 SDMMC_CMDR . . . . . . . . . . . . . . . . . . . . . 2346 SDMMC_DCNTR . . . . . . . . . . . . . . . . . . . . 2351 SDMMC_DCTRL . . . . . . . . . . . . . . . . . . . . . 2350 SDMMC_DLENR . . . . . . . . . . . . . . . . . . . . . 2349 SDMMC_DTIMER . . . . . . . . . . . . . . . . . . . . 2348 SDMMC_FIFOR . . . . . . . . . . . . . . . . . . . . . 2362 SDMMC_ICR . . . . . . . . . . . . . . . . . . . . . . . . 2355 SDMMC_IDMABASE0R . . . . . . . . . . . . . . . 2363 SDMMC_IDMABASE1R . . . . . . . . . . . . . . . 2364 SDMMC_IDMABSIZER . . . . . . . . . . . . . . . . 2363 SDMMC_IDMACTRLR . . . . . . . . . . . . . . . . 2362 SDMMC_MASKR . . . . . . . . . . . . . . . . . . . . 2358 SDMMC_POWER . . . . . . . . . . . . . . . . . . . . 2341 SDMMC_RESPCMDR . . . . . . . . . . . . . . . . 2347 SDMMC_RESPxR . . . . . . . . . . . . . . . . . . . . 2348 SDMMC_STAR . . . . . . . . . . . . . . . . . . . . . . 2353 SMPMI_IER . . . . . . . . . . . . . . . . . . . . . . . . . 2266 SPI_DR . . . . . . . . . . . . . . . . . . . . . . . 2143-2145 SPI_I2SCFGR . . . . . . . . . . . . . . . . . . . . . . . 2146 SPIx_SR . . . . . . . . . . . . . . . . . 2138-2139, 2142 SWO_AUTHSTAT . . . . . . . . . . . . . . . . . . . . 3050 SWO_CIDR0 . . . . . . . . . . . . . . . . . . . . . . . . 3055 SWO_CIDR1 . . . . . . . . . . . . . . . . . . . . . . . . 3055 SWO_CIDR2 . . . . . . . . . . . . . . . . . . . . . . . . 3056 SWO_CIDR3 . . . . . . . . . . . . . . . . . . . . . . . . 3056 SWO_CLAIMCLR . . . . . . . . . . . . . . . . . . . . 3049 SWO_CLAIMSET . . . . . . . . . . . . . . . . . . . . 3048 SWO_CODR . . . . . . . . . . . . . . . . . . . . . . . . 3047 SWO_DEVID . . . . . . . . . . . . . . . . . . . . . . . . 3051 SWO_DEVTYPE . . . . . . . . . . . . . . . . . . . . . 3052 SWO_FFSR . . . . . . . . . . . . . . . . . . . . . . . . 3048 SWO_LAR . . . . . . . . . . . . . . . . . . . . . . . . . . 3049 SWO_LSR . . . . . . . . . . . . . . . . . . . . . . . . . . 3050 DocID029587 Rev 3 3175/3178 Index RM0433 SWO_PIDR0 . . . . . . . . . . . . . . . . . . . . . . . .3053 SWO_PIDR1 . . . . . . . . . . . . . . . . . . . . . . . .3053 SWO_PIDR2 . . . . . . . . . . . . . . . . . . . . . . . .3054 SWO_PIDR3 . . . . . . . . . . . . . . . . . . . . . . . .3054 SWO_PIDR4 . . . . . . . . . . . . . . . . . . . . . . . .3052 SWO_SPPR . . . . . . . . . . . . . . . . . . . . . . . . .3047 SWPMI_BRR . . . . . . . . . . . . . . . . . . . . . . . .2263 SWPMI_CR . . . . . . . . . . . . . . . . . . . . . . . . .2262 SWPMI_ICR . . . . . . . . . . . . . . . . . . . . . . . . .2265 SWPMI_ISR . . . . . . . . . . . . . . . . . . . . . . . . .2264 SWPMI_OR . . . . . . . . . . . . . . . . . . . . . . . . .2269 SWPMI_RDR . . . . . . . . . . . . . . . . . . . . . . . .2268 SWPMI_RFL . . . . . . . . . . . . . . . . . . . . . . . .2268 SWPMI_TDR . . . . . . . . . . . . . . . . . . . . . . . .2268 SWTF_AUTHSTAT . . . . . . . . . . . . . . . . . . .3061 SWTF_CIDR0 . . . . . . . . . . . . . . . . . . . . . . .3065 SWTF_CIDR1 . . . . . . . . . . . . . . . . . . . . . . .3066 SWTF_CIDR2 . . . . . . . . . . . . . . . . . . . . . . .3066 SWTF_CIDR3 . . . . . . . . . . . . . . . . . . . . . . .3067 SWTF_CLAIMCLR . . . . . . . . . . . . . . . . . . . .3060 SWTF_CLAIMSET . . . . . . . . . . . . . . . . . . . .3059 SWTF_CTRL . . . . . . . . . . . . . . . . . . . . . . . .3058 SWTF_DEVID . . . . . . . . . . . . . . . . . . . . . . .3062 SWTF_LAR . . . . . . . . . . . . . . . . . . . . . . . . .3060 SWTF_LSR . . . . . . . . . . . . . . . . . . . . . . . . .3061 SWTF_PIDR0 . . . . . . . . . . . . . . . . . . . . . . .3063 SWTF_PIDR1 . . . . . . . . . . . . . . . . . . . . . . .3063 SWTF_PIDR2 . . . . . . . . . . . . . . . . . . . . . . .3064 SWTF_PIDR3 . . . . . . . . . . . . . . . . . . . . . . .3064 SWTF_PIDR4 . . . . . . . . . . . . . . . . . . . . . . .3065 SWTF_PRIORITY . . . . . . . . . . . . . . . . . . . .3059 SWTF_TYPEID . . . . . . . . . . . . . . . . . . . . . .3062 SYSCFG_CCCR . . . . . . . . . . . . . . . . . . . . . .509 SYSCFG_CCCSR . . . . . . . . . . . . . . . . . . . . .508 SYSCFG_CCVR . . . . . . . . . . . . . . . . . . . . . .509 SYSCFG_EXTICR1 . . . . . . . . . . . . . . . . . . . .504 SYSCFG_EXTICR2 . . . . . . . . . . . . . . . . . . . .505 SYSCFG_EXTICR3 . . . . . . . . . . . . . . . . . . . .506 SYSCFG_EXTICR4 . . . . . . . . . . . . . . . . . . . .507 SYSCFG_PKGR . . . . . . . . . . . . . . . . . . . . . .510 SYSCFG_PMCR . . . . . . . . . . . . . . . . . . . . . .502 SYSCFG_UR0 . . . . . . . . . . . . . . . . . . . . . . . .511 SYSCFG_UR10 . . . . . . . . . . . . . . . . . . . . . . .515 SYSCFG_UR11 . . . . . . . . . . . . . . . . . . . . . . .516 SYSCFG_UR12 . . . . . . . . . . . . . . . . . . . . . . .516 SYSCFG_UR13 . . . . . . . . . . . . . . . . . . . . . . .517 SYSCFG_UR14 . . . . . . . . . . . . . . . . . . . . . . .518 SYSCFG_UR15 . . . . . . . . . . . . . . . . . . . . . . .519 SYSCFG_UR16 . . . . . . . . . . . . . . . . . . . . . . .520 SYSCFG_UR17 . . . . . . . . . . . . . . . . . . . . . . .520 SYSCFG_UR2 . . . . . . . . . . . . . . . . . . . . . . . .511 SYSCFG_UR3 . . . . . . . . . . . . . . . . . . . . . . . .512 3176/3178 SYSCFG_UR4 . . . . . . . . . . . . . . . . . . . . . . . 512 SYSCFG_UR5 . . . . . . . . . . . . . . . . . . . . . . . 513 SYSCFG_UR6 . . . . . . . . . . . . . . . . . . . . . . . 513 SYSCFG_UR7 . . . . . . . . . . . . . . . . . . . . . . . 514 SYSCFG_UR8 . . . . . . . . . . . . . . . . . . . . . . . 514 SYSCFG_UR9 . . . . . . . . . . . . . . . . . . . . . . . 515 SYSROM_CIDR0 . . . . . . . . . . . . . . . . . . . . 2965 SYSROM_CIDR1 . . . . . . . . . . . . . . . . . . . . 2965 SYSROM_CIDR2 . . . . . . . . . . . . . . . . . . . . 2966 SYSROM_CIDR3 . . . . . . . . . . . . . . . . . . . . 2966 SYSROM_MEMTYPE . . . . . . . . . . . . . . . . . 2962 SYSROM_PIDR0 . . . . . . . . . . . . . . . . . . . . 2963 SYSROM_PIDR1 . . . . . . . . . . . . . . . . . . . . 2964 SYSROM_PIDR2 . . . . . . . . . . . . . . . . . . . . 2964 SYSROM_PIDR3 . . . . . . . . . . . . . . . . . . . . 2965 SYSROM_PIDR4 . . . . . . . . . . . . . . . . . . . . 2963 T TIM1_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1557 TIM1_AF2 . . . . . . . . . . . . . . . . . . . . . . . . . . 1559 TIM1_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 1564 TIM12_TISEL . . . . . . . . . . . . . . . . . . . . . . . 1681 TIM13_TISEL . . . . . . . . . . . . . . . . . . . . . . . 1692 TIM14_TISEL . . . . . . . . . . . . . . . . . . . . . . . 1692 TIM15_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . 1752 TIM15_ARR . . . . . . . . . . . . . . . . . . . . . . . . . 1746 TIM15_BDTR . . . . . . . . . . . . . . . . . . . . . . . 1748 TIM15_CCER . . . . . . . . . . . . . . . . . . . . . . . 1743 TIM15_CCMR1 . . . . . . . . . . . . . . . . . . . . . . 1740 TIM15_CCR1 . . . . . . . . . . . . . . . . . . . . . . . 1747 TIM15_CCR2 . . . . . . . . . . . . . . . . . . . . . . . 1748 TIM15_CNT . . . . . . . . . . . . . . . . . . . . . . . . . 1746 TIM15_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . 1732 TIM15_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . 1733 TIM15_DCR . . . . . . . . . . . . . . . . . . . . . . . . 1751 TIM15_DIER . . . . . . . . . . . . . . . . . . . . . . . . 1736 TIM15_DMAR . . . . . . . . . . . . . . . . . . . . . . . 1751 TIM15_EGR . . . . . . . . . . . . . . . . . . . . . . . . 1739 TIM15_PSC . . . . . . . . . . . . . . . . . . . . . . . . . 1746 TIM15_RCR . . . . . . . . . . . . . . . . . . . . . . . . 1747 TIM15_SMCR . . . . . . . . . . . . . . . . . . . . . . . 1735 TIM15_SR . . . . . . . . . . . . . . . . . . . . . . . . . . 1737 TIM15_TISEL . . . . . . . . . . . . . . . . . . . . . . . 1753 TIM16_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . 1772 TIM16_TISEL . . . . . . . . . . . . . . . . . . . . . . . 1773 TIM17_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . 1774 TIM17_TISEL . . . . . . . . . . . . . . . . . . . . . . . 1775 TIM2_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1637 TIM2_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 1638 TIM3_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1637 TIM3_TISEL . . . . . . . . . . . . . . . . . . . . . . . . 1639 DocID029587 Rev 3 RM0433 Index TIM5_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . .1638 TIM5_TISEL . . . . . . . . . . . . . . . . . . . . . . . . .1640 TIM8_AF1 . . . . . . . . . . . . . . . . . . . . . . . . . .1560 TIM8_AF2 . . . . . . . . . . . . . . . . . . . . . . . . . .1562 TIM8_TISEL . . . . . . . . . . . . . . . . . . . . . . . . .1564 TIMx_ARR 1547, 1633, 1680, 1691, 1766, 1789 TIMx_BDTR . . . . . . . . . . . . . . . . . . . .1550, 1768 TIMx_CCER . . . . 1543, 1631, 1678, 1689, 1763 TIMx_CCMR1 . . 1537, 1625, 1674, 1687, 1761 TIMx_CCMR2 . . . . . . . . . . . . . . . . . .1541, 1629 TIMx_CCMR3 . . . . . . . . . . . . . . . . . . . . . . .1555 TIMx_CCR1 . . . . 1548, 1634, 1680, 1691, 1767 TIMx_CCR2 . . . . . . . . . . . . . . 1549, 1634, 1680 TIMx_CCR3 . . . . . . . . . . . . . . . . . . . .1549, 1635 TIMx_CCR4 . . . . . . . . . . . . . . . . . . . .1550, 1635 TIMx_CCR5 . . . . . . . . . . . . . . . . . . . . . . . . .1556 TIMx_CCR6 . . . . . . . . . . . . . . . . . . . . . . . . .1557 TIMx_CNT 1547, 1632, 1679, 1690, 1765, 1788 TIMx_CR1 1526, 1616, 1669, 1684, 1756, 1785 TIMx_CR2 . . . . . . . . . . 1527, 1617, 1757, 1787 TIMx_DCR . . . . . . . . . . . . . . . 1553, 1636, 1770 TIMx_DIER 1532, 1622, 1672, 1685, 1758, 1787 TIMx_DMAR . . . . . . . . . . . . . . 1554, 1636, 1771 TIMx_EGR 1536, 1624, 1673, 1686, 1760, 1788 TIMx_PSC 1547, 1633, 1679, 1691, 1766, 1789 TIMx_RCR . . . . . . . . . . . . . . . . . . . . .1548, 1767 TIMx_SMCR . . . . . . . . . . . . . . 1530, 1619, 1670 TIMx_SR . 1534, 1623, 1672, 1685, 1759, 1788 TPIU_AUTHSTAT . . . . . . . . . . . . . . . . . . . .3038 TPIU_CIDR0 . . . . . . . . . . . . . . . . . . . . . . . .3042 TPIU_CIDR1 . . . . . . . . . . . . . . . . . . . . . . . .3043 TPIU_CIDR2 . . . . . . . . . . . . . . . . . . . . . . . .3043 TPIU_CIDR3 . . . . . . . . . . . . . . . . . . . . . . . .3044 TPIU_CLAIMCLR . . . . . . . . . . . . . . . . . . . . .3036 TPIU_CLAIMSET . . . . . . . . . . . . . . . . . . . . .3036 TPIU_CURPSIZE . . . . . . . . . . . . . . . . . . . . .3028 TPIU_CURTPM . . . . . . . . . . . . . . . . . . . . . .3032 TPIU_DEVID . . . . . . . . . . . . . . . . . . . . . . . .3039 TPIU_DEVTYPE . . . . . . . . . . . . . . . . . . . . .3039 TPIU_FFCR . . . . . . . . . . . . . . . . . . . . . . . . .3034 TPIU_FFSR . . . . . . . . . . . . . . . . . . . . . . . . .3033 TPIU_FSCR . . . . . . . . . . . . . . . . . . . . . . . . .3035 TPIU_LAR . . . . . . . . . . . . . . . . . . . . . . . . . .3037 TPIU_LSR . . . . . . . . . . . . . . . . . . . . . . . . . .3037 TPIU_PIDR0 . . . . . . . . . . . . . . . . . . . . . . . .3040 TPIU_PIDR1 . . . . . . . . . . . . . . . . . . . . . . . .3041 TPIU_PIDR2 . . . . . . . . . . . . . . . . . . . . . . . .3041 TPIU_PIDR3 . . . . . . . . . . . . . . . . . . . . . . . .3042 TPIU_PIDR4 . . . . . . . . . . . . . . . . . . . . . . . .3040 TPIU_SUPPSIZE . . . . . . . . . . . . . . . . . . . . .3028 TPIU_SUPTPM . . . . . . . . . . . . . . . . . . . . . .3031 TPIU_SUPTRGM . . . . . . . . . . . . . . . . . . . . .3029 TPIU_TPRCR . . . . . . . . . . . . . . . . . . . . . . . 3033 TPIU_TRGCNT . . . . . . . . . . . . . . . . . . . . . . 3030 TPIU_TRGMULT . . . . . . . . . . . . . . . . . . . . . 3030 TSG_CIDR0 . . . . . . . . . . . . . . . . . . . . . . . . 2973 TSG_CIDR1 . . . . . . . . . . . . . . . . . . . . . . . . 2973 TSG_CIDR2 . . . . . . . . . . . . . . . . . . . . . . . . 2974 TSG_CIDR3 . . . . . . . . . . . . . . . . . . . . . . . . 2974 TSG_CNTCR . . . . . . . . . . . . . . . . . . . . . . . 2969 TSG_CNTCVL . . . . . . . . . . . . . . . . . . . . . . . 2970 TSG_CNTCVU . . . . . . . . . . . . . . . . . . . . . . 2970 TSG_CNTFID0 . . . . . . . . . . . . . . . . . . . . . . 2970 TSG_CNTSR . . . . . . . . . . . . . . . . . . . . . . . . 2969 TSG_PIDR1 . . . . . . . . . . . . . . . . . . . . . . . . 2972 TSG_PIDR2 . . . . . . . . . . . . . . . . . . . . . . . . 2972 TSG_PIDR3 . . . . . . . . . . . . . . . . . . . . . . . . 2973 TSG_PIDR4 . . . . . . . . . . . . . . . . . . . . . . . . 2971 TX_LPI_TRAN_CNTR . . . . . . . . . . . . . . . . . 2871 TX_LPI_USEC_CNTR . . . . . . . . . . . . . . . . 2871 TX_MULTIPLE_COLLISION_GOOD_PACKETS 2869 TX_PACKET_COUNT_GOOD . . . . . . . . . . 2869 TX_SINGLE_COLLISION_GOOD_PACKETS . . 2869 U USART_BRR . . . . . . . . . . . . . . . . . . . 2014, 2065 USART_CR1 . . . . .383, 2001, 2057, 2228, 2231 USART_CR2 . . . . . . . . . . . . . . . . . . . 2006, 2060 USART_CR3 . . . . . . . . . . . . . . . . . . . 2009, 2062 USART_DR . 2025-2026, 2071-2072, 2235-2239 USART_GTPR . . . . . . . . . . . . . . . . . 2014-2015 USART_ISR . . . . . . . . . . . . . . . . . . . 2017, 2066 USART_PRESC . . . . . . . . . . . . . . . . . . . . . 2026 USART_SR 2016, 2024, 2066, 2070, 2232-2233 V VREFBUF_CCR . . . . . . . . . . . . . . . . . . . . . 1016 VREFBUF_CSR . . . . . . . . . . . . . . . . . . . . . 1015 W WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . 1824 WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . 1823 WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . 1824 DocID029587 Rev 3 3177/3178 RM0433 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 3178/3178 DocID029587 Rev 3
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No Page Layout : SinglePage Page Mode : UseNone Page Count : 3179 Creator : C2 v4.2.0220 build 670 - c2_rendition_config : Techlit_Active Producer : Acrobat Elements 10.0.0 (Windows); modified using iText 2.1.7 by 1T3XT Title : STM32H7x3 advanced ARM®-based 32-bit MCUs Keywords : Technical Literature, 029587, Product Development, Specification, Reference manual, STM32H7x3 Modify Date : 2017:08:29 11:25:33+02:00 Subject : - Author : STMICROELECTRONICS Create Date : 2017:08:14 08:31:47ZEXIF Metadata provided by EXIF.tools