SA22 7200 0_370 ESA_Principles_of_Operation_Aug88 0 370 ESA Principles Of Operation Aug88
SA22-7200-0_370-ESA_Principles_of_Operation_Aug88 SA22-7200-0_370-ESA_Principles_of_Operation_Aug88
User Manual: SA22-7200-0_370-ESA_Principles_of_Operation_Aug88
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---___ -- ---- --- -----t_ IBM Enterprise Systems Architecture/370 Principles of Operation Publication Number 5A22-7200-0 File Number 5370-01 First Edition (August 1988) Changes are made occasionally to the information herein; before using this publication in connection with the operation of IBM equipment, refer to the latest IBM System/370, 30xx, 4300, and 9370 Processors Bibliography, GC20-000 I, for the editions that are applicable and current. may have patents or pending patent applications covering subject matter described herein. Furnishing this publication does not constitute or imply a grant of any license under any patents, patent applications, trademarks, copyrights, or other rights of IBM or of any third party, or any right to refer to IBM in any advertising or other promotional or marketing activities. IBM assumes no responsibility for any infringement of patents or other rights that may result from the use of this publication or from the manufacture, use, lease, or sale of apparatus described herein. IBM Licenses under IBM'S utility patents are available on reasonable and nondiscriminatory terms and conditions. Inquiries relative to licensing should be directed, in writing, to: IBM Corporation, Director of Contracts and Licensing, Armonk, NY, USA 10504. References in this publication to IBM products, programs, or services do not imply that these available in all countries in which IBM operates. IBM intends to make Publications are not stocked at the address given below. Requests for IBM publications should be made to your IBM representative or to the IBM branch office serving your locality. A form for reader's comments is provided at the back of this publication. If the form has been removed, comments nlay be addressed to: IBM Corporation, Central Systems Architecture, Department E57, PO Box 950, Poughkeepsie, NY, USA 12602. IBM may use or distribute whatever information you supply in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 1988. All rights reserved. Preface This publication provides, for reference purposes, a detailed Enterprise Systems Architecture/370™ (ESA/370™) description. The publication applies only to systems operating as defmed by ESA/370. For systems operating in accordance with the System/370 or System/370 extended-architecture (370-XA) defmitions, the IBM System/370 Principles of Operation, GA22-7000, or the IBM 370-XA Principles of Operation, SA22-7085, should be consulted. The publication describes each function at the level of detail needed to prepare an assembler-language program that relies on that function. It does not, however, describe the notation and conventions that must be employed in preparing such a program, for which the user must instead refer to the appropriate assembler-language publication. The information in this publication is provided principally for use by assembler-language programmers, although anyone concerned with the functional details of ESA/370 will fmd it useful. This publication is written as a reference and should not be considered an introduction or a textbook. It assumes the user has a basic knowledge of data-processing systems. IBM publications relating to ESA/370 are listed and described in the IBM System/370, 30xx, 4300, and 9370 Processors Bibliography, GC20-000 1. All facilities discussed in this publication are not necessarily available on every model. Furthermore, in some instances the defmitions have been structured to allow for some degree of extendibility, and therefore certain capabilities may be described or implied that are not offered on any model. Examples of such capabilities are the use of a 16-bit field in the subsystem-identification word to identify the channel s:ub system , the size of the CPU address, and the number of CPUs sharing main storage. The allowance for this type of extendibility should not be construed as implying any intention by IBM to provide such capabilities. For information about the characteristics and availability of facilities on a specific model, see the functional characteristics publication for that model. Largely because this publication is arranged for reference, certain words and phrases appear, of necessity, earlier in the publication than the principal discussions explaining them. The reader who encounters a problem because of this arrangement should refer to the index, which indicates the location of the key description. The information presented in this publication is grouped in 17 chapters and several appendixes: Chapter 1, Introduction, highlights some of the major facilities of ESA/370. Chapter 2, Organization, describes the major groupings within the system -- the central processing unit (cPu), storage, and input/output -- with some attention given to the composition and characteristics of those groupings. Chapter 3, Storage, explains the information formats, the addressing of storage, and the facilities for storage protection. It also deals with dynamic address translation (DAT), which, coupled with special programming support, makes the use of a virtual storage possible. Chapter 4, Control, describes the facilities for the switching of system status, for special externally initiated operations, for debugging, and for timing. It deals specifically with CPU states, control modes, the program-status word (psw), control registers, tracing, program-event recording, timing facilities, resets, store status, and initial program loading. Chapter 5, Program Execution, explains the role of instructions in program execution, looks in detail at instruction formats, and describes briefly the use of the program-status word (psw), of branching, and of interruptions. It contains the principal description of the advanced address-space facilities that are introduced in ESA/370. It also details the aspects of program execution on one CPU as observed by other CPus and by channel programs. Enterprise Systems Architecture/370 and ESA/370 are trademarks of the International Business Machines Corporation. Preface iii Chapter 6, Interruptions, details the mechanism that permits the CPU to change its state as a result of conditions external to the system, within the system, or within the CPU itself. Six classes of interruptions are identified and described: machinecheck interruptions, program interruptions, supervisor-call interruptions, external interruptions, input/output interruptions, and restart interruptions. Chapter 7, General Instructions, contains detailed descriptions of logical and binary-integer data formats and of all unprivileged instructions except the decimal and floating-point instructions. Chapter 8, Decimal Instructions, describes in detail decimal data formats and the decimal instructions. Chapter 9, Floating-Point Instructions, contains detailed descriptions of floating-point data formats and the floating-point instructions. Chapter /7, I/O Support Functions, describes such functions as channel-subsystem usage monitoring, resets, initial-program loading, reconfiguration, and channel-subsystem recovery. The Appendixes include: • Information about number representation • Instruction-use examples • Lists of the instructions arranged in several sequences • A summary of the condition-code settings • A summary of the differences between 370-XA and ESA/370 • A summary of the differences between System/370 and 370-XA • A table of the powers of 2 • Tabular information helpful in dealing with hexadecimal numbers • An EBCDIC chart Size Notation Chapter /0, Control Instructions, contains detailed descriptions of all of the semiprivilegedand privileged instructions except for the I/O instructions. Chapter /1, Machine-Check Handling, describes the mechanism for detecting, correcting, and reporting machine malfunctions. Chapter /2, Operator Facilities, describes the basic manual functions and controls available for operating and controlling the system. Chapters 13-17 of this publication provide a detailed defInition of the functions performed by the channel subsystem and the logical interface between the CPU and the channel subsystem. Chapter /3, I/O Overview, provides a brief description of the basic components and operation of the channel subsystem. Chapter /4, I/O Instructions, description of the I/O instructions. contains the Chapter /5, Basic I/O Functions, describes the basic functions performed by the channel subsystem, including the initiation, control, and conclusion of I/O operations. I/O Chapter /6, I/O Interruptions, covers ruptions and interruption conditions. iv ESA/370 Principles of Operation I/O inter- In this publication, the letters K, M, G, and T denote the multipliers 210, 220, 230, and 240, respectively. Although the letters are borrowed from the decimal system and stand for kilo (10 3 ), mega (106 ), giga (10 9 ), and tera (10 12 ), they do not have the decimal meaning but instead represent the power of 2 closest to the corresponding power of 10. Their meaning in this publication is as follows: Symbol Value K (kil 0) 1t 024 = 210 M (mega) 1t 048 t 576 = 220 G (giga) 1,073,741,824 = 230 T (tera) 1,099,511,627,776 = 240 The following are some examples of the use of K, M, G, and T: 2,048 is expressed as 2K. 4,096 is expressed as 4K. 65,536 is expressed as 64K (not 65K). 224 is expressed as 16M. 231 is expressed as 2G. 242 is expressed as 4T. When the words "thousand" and "million" are used, no special power-of-2 meaning is assigned to them. Bytes, Characters, and Codes Other Publications Although the System/360 architecture was originally designed to support the Extended BinaryCoded-Decimal Interchange Code (EBCDIC), the instructions and data formats of the architecture are for the most part independent of the external code which is to be processed by the machine. For most instructions, all 256 possible combinations of bit patterns for a particular byte can be processed, independent of the character which the bit pattern is intended to represent. For instructions which use the zoned format, and for those few instructions which are dependent on a particular external code, the instruction TRANSLATE may be used to convert data from one code to another code. Thus, a machine operating in accordance with FSA/370 can process EBCDIC, ASCII, or any other code which can be represented in eight or fewer bits per character. The channel-to-channel adapter is described in the IBM Channel-to-Channel-Adapter, publication SA22-7091. In this publication, unless otherwise specified, the value given for a byte is the value obtained by considering the bits of the byte to represent a binary code. Thus, when a byte is said to contain a zero, the value 00000000 binary, or 00 hex, is meant, and not the value for an EBCDIC character "0," which would be FO hex. The I/O interface is described in the publication IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers' I njormation, GA22-6974. The mathematical assists are described in the publication IBM System/ 370 Mathematical Assists, SA22-7094, which describes the instructions ARCTANGENT, COMMON LOGARITHM, COSINE, EXPONENTIAL, MULTIPLY AND ADD, NATURAL LOGARITHM, RAISE TO POWER, SINE, and SQUARE ROOT. Vector operations are described in the publication Enterprise System~ Architecture/370 and System/370 Vector Operations, SA22-7125. The interpretive-execution facility is described in the publication IBM 370-XA Interpretive Execution, SA22-7095. Preface V This page is intentionally left blank. vi ESAj370 Principles of Operation Contents Chapter 1. Introduction . . . . . . . . Highlights of ESA/370 . . . . . . . . . Advanced Address-Space Facilities The 370-XA Base .. . System Program . . . . . . . . . . . Compatibility . . . . . . . . . . . . . Compatibility among ESA/370 Systems Compatibility among ESA/370, 370-XA, a1ld System/370 . . . . . . . . . Control-Program Compatibility Problem-State Compatibility Availability . . . . . . . . .... . 1-1 1-1 1-1 1-2 1-3 1-3 1-3 1-4 1-4 1-4 1-4 Chapter 2. Organization Main Storage CPU . . . . . . . . PSW .......... . General Registers Floating-Point Registers Control Registers Access Registers ... . Vector Facility . . . . . I/O . . . . . . . . . . . . . . . . . Channel Subsystem . . . . . . I/O Devices and Control Units Operator Facilities 2-1 2-2 2-2 2-2 2-3 2-3 2-3 2-3 2-4 2-4 2-6 2-6 2-6 Chapter 3. Storage Storage Addressing ..... Information Formats Integral Boundaries Address Types and Formats . . . . . . . . . Address Types . . . . . . . . . . . . . . . Absolute Address Real Address . . . . . . Virtual Address . . . . . Primary Virtual Address Secondary Virtual Address AR -Specified Virtual Address . . . . Home Virtual Address .. Logical Address . . . Instruction Address Effective Address ., Address Size and Wraparound ., Address Wraparound . . . . . Storage Key . . . . . . . . . . . . . . . . . . . Protection . . . . . . . . . . . . . . . . . . . Key-Controlled Protection . . . . . . . . Fetch-Protection-Override Control .. Page Protection . . . . . . . . . . . . . Low-Address Protection Reference Recording . . . . . . . . . . . . 3-1 3-2 3-2 3-3 3-3 3-3 . . . . 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-5 3-5 3-5 3-5 3-7 3-8 3-8 3-9 3-9 3-10 3-10 Change Recording ......... . . ........ . Prefixing . . . . . Address Spaces . . . . . . . . . . Changing to Different Address Spaces Address-Space Number ASN Translation . . . . . . . . . . . . . AS N -Translation Controls Control Register 14 Control Register 0 ASN-Translation Tables ASN -First-Table Entries ASN -Second-Table Entries AS N -Translation Process ... ASN-First-Table Lookup . ASN -Second-Table Lookup Recognition of Exceptions during AS N Translation . . . . . . . . . . . . ASN Authorization . . . . . . . . . . . . . . ASN-Authorization Controls Control Register 4 ASN-Second-Table Entry Authority-Table Entries . ASN-Authorization Process . . . . . Authority-Table Lookup . . . . . Recognition of Exceptions during AS N Authorization . . . . . . . . . . . . Dynamic Address Translation . . . . . . . . Translation Control ... Translation Modes Control Register 0 Control Register 1 Control Register 7 Control Register 13 Translation Tables . . . . Segment-Table Entries . . . . . . Page-Table Entries . . . . . . . . Summary of Segment-Table and Page-Table Sizes . . . . . . . . Translation Process . . . . . . . . . Effective Segment-Table Designation Inspection of Control Register 0 Segment-Table Lookup Page-Table Lookup . . . . . . . Formation of the Real Address . Recognition of Exceptions during Translation . . . . . . . Translation-Lookaside Buffer TLB Structure . . . . . . Formation of TLB Entries Use of TLB Entries Modification of Translation Tables Address Summary . . . . . . . . . . . . . . 3-11 3-11 3-13 3-13 3-13 3-14 3-15 3-15 3-15 3-15 3-1'5 3-16 3-17 3-18 3-19 3-19 . 3-19 3-19 3-20 3-20 3-20 3-20 3-22 . 3-22 . 3-22 3-24 3-24 3-24 3-24 3-25 3-25 3-26 3-26 3-27 3-27 3-27 3-28 3-30 3-30 3-30 3-31 3-31 3-31 3-31 3-32 3-32 3-33 . 3-35 Contents vii Addresses Translated Handling of Addresses Assigned Storage Locations Chapter 4. Control . . . . . . Stopped, Operating, Load, and Check-Stop States . . . . . . Stopped State Operating State Load State Check-Stop State Program-Status Word Program-Status-Word Format Control Registers . . . . . . . Tracing . . . . . . . . . . . . . Control-Register Allocation Trace Entries . . . . . . Operation . . . . . . . . . . Pro gram-Event Recording .. Control-Register Allocation Operation . . . . . . . . . . Identification of Cause Priority of Indication Storage-Area Designation PER Events . . . . . . Successful Branching Instruction Fetching Storage Alteration General-Register Alteration Store Using Real Address Indication of PER Events Concurrently with Other Interruption Conditions Timing . . . . . . . . . Time-of-Day Clock Format .... . States ..... . Changes in Clock State Setting and Inspecting the Clock TOD-Clock Synchronization Clock Comparator CPU Timer . . . . . . . . Externally Initiated Functions Resets . . . . . . . . CPU Reset Initial CPU Reset Subsystem Reset Clear Reset Power~On Reset Initial Program Loading Store Status Multiprocessing . . . . . . Shared Main Storage CPU -Address Identification CPU Signaling and Response Signal-Processor Orders .. Conditions Determining Response viii ESAj370 Principles of Operation 3-35 3-36 3-39 4-1 4-1 4-2 4-2 4-2 4-2 4-3 4-5 4-6 4-9 4-9 4-10 4-12 4-12 4-13 4-14 4-14 4-15 4-16 4-16 4-16 4-17 4-17 4-17 4-18 4-18 4-21 4-21 4-21 4-22 4-23 4-23 4-24 4-25 4-26 4-27 4-27 4-30 4-31 4-31 4-31 4-32 4-32 4-33 4-33 4-34 4-34 4-34 4-34 4-36 Conditions Precluding Interpretation of the Order Code 4-36 Status Bits . . . . . . . . . 4-37 Chapter 5. Program Execution Instructions . . . . . . Operands . . . . . . Instruction Formats Register Operands Immediate Operands Storage Operands Address Generation . . . . Bimodal Addressing .. Sequential Instruction-Address Generation Operand-Address Generation . . . . . Formation of the Intermediate Value Formation of the Address . . . . Branch-Address Generation Formation of the Branch Address Instruction Execution and Sequencing Decision Making . . . . . . . . . . Loop Control . . . . . . . . . . . . Subroutine Linkage without the Linkage Stack . . . . . . . . . . . . . Interruptions . . . . . . . . . Types of Instruction Ending Completion Suppression Nullification Termination Interruptible Instructions Point of Interruption Execution of Interruptible Instructions Exceptions to Nullification and Suppression . . . . . . . . . . . . . . . Storage Change and Restoration for DAT -Associated Access Exceptions Modification of DAT -Table Entries Trial Execution for Editing Instructions and Translate Instruction Authorization Mechanisms Mode Requirements . . . . . Extraction-Authority Control PSW-Key Mask . . . . . . Secondary-Space Control Subsystem-Linkage Control ASN-Translation Control Authorization Index Access-Register and Linkage-Stack Mechanisms . . . . . . . . . . PC-Number Translation . . . . . . . PC-Number Translation Control Control Register 0 . . . . . . Control Register 5 . . . . . . PC-Number Translation Tables 5-1 5-2 5-2 5-3 5-4 5-5 5-5 5-5 5-5 5-5 5-6 5-6 5-6 5-7 5-7 5-7 5-7 5-8 5-8 5-12 5-12 5-12 5-12 5-12 5-12 5-12 5-12 5-13 5-14 5-15 5-15 5-15 5-16 5-16 5-16 5-16 5-17 5-17 5-17 5-17 5·18 5·21 5·21 5·21 5·21 5·22 Linkage-Table Entries 5-22 5-22 Entry-Table Entries PC-Number-Translation Process 5-23 Obtaining the Linkage-Table 5-24 Designation . . . . . 5-25 Linkage-Table Lookup 5-25 Entry-Table Lookup . Recognition of Exceptions during 5-25 PC-Number Translation 5-26 Home Address Space . . . . . 5-26 Access-Registers Introduction 5-26 Summary . . . . . . . . . . Access-Register Functions 5-27 Access-Register-Specified Address Spaces . . . . . . . . . . . 5-27 5-34 Access-Register Instructions 5-35 Access-Register Translation ... 5-35 Access- Register-Translation Control 5-35 Address-Space-Function Control Control Register 2 5-36 Control Register 5 5-36 5-36 Control Register 8 Access Registers 5-36 Access-Register-Translation Tables 5-37 5-37 Access-List Designations 5-39 Access-List Entries . . . . . . . . Extended ASN-Second-Table Entries 5-40 Access-Register:. Translation Process 5-41 Selecting the Access-List-Entry Token 5-44 Obtaining the Primary or Secondary Segment-Table Designation . . . . . 5-44 5-44 Checking the First Byte of the ALET Obtaining the Effective Access-List Designation . . . . . . . . . . . . . . 5-44 Access-List Lookup . . . . . . . . . . 5-44 Locating the ASN-Second-Table Entry 5-45 Authorizing the Use of the Access-List Entry . . . . . . . . . . . . . . . . . . . 5-45 Obtaining the Segment-Table Designation from the 5-46 ASN-Second-Table Entry Recognition of Exceptions During Access-Register Translation 5-46 5-46 ART -Lookaside Buffer ... ALB Structure 5-46 5-47 Formation of ALB Entries Use of ALB Entries 5-48 Modification of ART Tables 5-48 Linkage-Stack Introduction 5-48 Summary . . . . . . . . . . . . . 5-48 5-49 Linkage-Stack Functions ... . Transferring Program Control 5-49 Branching Using the Linkage Stack 5-51 5-51 Adding and Retrieving Information Testing Authorization 5-52 5-52 Pro gram-Problem Analysis Extended Entry-Table Entries ... . Linkage-Stack Operations . . . . . . Linkage-Stack-Operations Control Control Register 0 Control Register 15 Linkage Stack Entry Descriptors Header Entries Trailer Entries State Entries Stacking Process Locating Space for a New Entry Fonning the New Entry .. . Updating the Current Entry .. . Updating Control Register 15 Recognition of Exceptions During the Stacking Process . . . . . . . Unstacking Process . . . . . . . . Locating the Current Entry and Processing a Header Entry Checking for a State Entry Restoring Information '" Updating the Preceding Entry Updating Control Register 15 Recognition of Exceptions during the Un stacking Process '" Sequence of Storage References . . . . . . Conceptual Sequence . . . . . . . . Overlapped Operation of Instruction Execution . . . . . . . . . . . . . . Divisible Instruction Execution .. . Interlocks for Virtual-Storage References Interlocks Between Instructions Interlocks Within a Single Instruction Instruction Fetching . . . . . . . . . . ART-Table and OAT-Table Fetches Storage-Key Accesses . . . . . . . . . Storage-Operand References . . . . . Storage-Operand Fetch References Storage-Operand Store References Storage-Operand Update References Storage-Operand Consistency Single-Access References Multiple-Access References . Block-Concurrent References Consistency Specification Relation between Operand Accesses Other Storage References Serialization . . . . . . . . . . . . CPU Serialization . . . . . . . Channel-Program Serialization 5-52 5-54 5-56 5-56 5-56 5-56 5-56 5-58 5-58 5-59 5-60 5-61 5-62 5-62 5-62 5-62 5-63 5-63 5-64 5-64 5-64 5-65 5-65 5-65 5-65 5-66 5-66 5-66 5-67 5-67 5-69 5-71 5-71 5-72 5-72 5-72 5-72 5-74 5-74 5-74 5-74 5-74 5-75 5-76 5-76 5-76 5-77 6-1 6-2 6-5 Chapter 6. Interruptions Interruption Action . Interruption Code ., Contents ix Enabling and Disabling . . . . . . Handling of Floating Interruption Conditions . . . . . . . Instruction-Length Code . . . . . Zero ILC . . . . . . . . . . . . ILC on Instruction-Fetching Exceptions Exceptions Associated with the PSW Early Exception Recognition Late Exception Recognition External Interruption Clock Comparator CPU Timer Emergency Signal External Call ... Interrupt Key Malfunction Alert Service Signal TOD-Clock Sync Check I/O Interruption ..... . Machine-Check Interruption Program Interruption Exception-Extension Code Program-Interruption Conditions Addressing Exception AFX -Translation Exception ALEN-Translation Exception ALE-Sequence Exception .. ALET -Specification Exception ASN-Translation-Specification Exception . . . . . . . . . ASTE-Sequence Exception ASTE-Validity Exception ASX -Translation Exception Data Exception . . . . . . . Decimal-Divide Exception Decimal-Overflow Exception Execute Exception . . . . . . Exponent-Overflow Exception Exponent-Underflow Exception EX-Translation Exception Extended-Authority Exception Fixed-Point- Divide Exception Fixed-Point-Overflow Exception Floating-Point-Divide Exception LX -Translation Exception Monitor Event Operand Exception . . . . Operation Exception ... Page-Translation Exception PC-Translation-Specification Exception PER Event . . . . . . . . . . . Primary-Authority Exception Privileged-Operation Exception Protection Exception ..... Secondary-Authority Exception Segment-Translation Exception X ESAj370 Principles o{Operation 6-6 6-6 6-7 6-7 6-7 6-8 6-8 6-9 6-9 6-10 6-10 6-11 6-11 6-11 6-11 6-12 6-12 6-12 6-13 6-13 6-14 6-14 6-14 6-16 6-16 6-16 6-16 6-16 6-17 6-17 6-17 6-17 6-18 6-18 6-18 6-18 6-19 6-19 6-19 6-19 6-19 6-20 6-20 6-20 6-21 6-21 6-21 6-22 6-22 6-22 6-22 6-23 6-24 6-24 Significance Exception ... Space-Switch Event Special-Operation Exception Specification Exception Stack-Empty Exception Stack-Full Exception .. Stack-Operation Exception Stack-Specification Exception Stack-Type Exception . . . . Trace-Table Exception Translation-Specification Exception , Unnormalized-Operand Exception Vector-Operation Exception Collective Program-Interruption Names Recognition of Access Exceptions ... Multiple Program-Interruption Conditions Access Exceptions . . . . . . ASN -Translation Exceptions Trace Exceptions ... Restart Interruption Supervisor-Call Interruption Priority of Interruptions 6-24 6-24 6-25 6-26 6-27 6-27 6-27 6-27 6-27 6-28 6-28 6-28 6-28 6-29 6-29 6-32 6-34 6-38 6-38 6-38 6-38 6-39 Chapter 7. General Instructions Data Format . . . . . . . . . Binary-Integer Representation Binary Arithmetic . . . . . . . Signed Binary Arithmetic Addition and Subtraction Fixed-Point Overflow Unsigned Binary Arithmetic Signed and Logical Comparison Instructions Add . . . . . . Add Halfword Add Logical AND . . . . . Branch and Link Branch and Save Branch and Save and Set Mode Branch and Set Mode Branch on Condition Branch on Count Branch on Index High Branch on Index Low or Equal Compare . . . . . . . . . . . . Compare and Form Codeword Compare and Swap Compare Double and Swap Compare Halfword Compare Logical . . . . . Compare Logical Characters under Mask Compare Logical Long Convert to Binary Convert to Decimal .. 7-1 7-2 7-2 7-3 7-3 7-3 7-3 7-3 7-4 7-4 7-8 7-8 7-9 7-9 7-10 7-11 7-11 7-12 7-12 7-13 7-14 7-14 7-15 7-15 7-19 7-19 7-20 7-21 7-21 7-22 7-24 7-24 Copy Access " " " " " " " ' " Divide " " " " " " " " " ' " Exclusive OR " " " " " " " " Execute " " " " " " " " " " Extract Access " " " " " " " " Insert Character " " " " " " ' " Insert Characters under Mask " " ' " Insert Program Mask " " " " " " wad " " " " " " " " " ' " wad Access Multiple " " " " " " wad Address " " " " " " " " wad Address Extended , , , , , , , , , , , wad and Test " " " " " " " " wad Complement " " " " " ' " wad Halfword , , ' , . , , , , . . . . . . . wad Multiple " " " " " " " " wad Negative " " " " " " " " wad Positive " " " " " " " " Monitor Call " " , " " " " " " Move Move Inverse " " " " " " " " Move Long, , , , , , , , , , , , , , , , , , Move Numerics " " " " " " ' " Move with Offset " " " " " " " Move Zones " " " " " " " ' " Multiply " " " " " " " " ' " Multiply Halfword , " " " " " " OR " " " " " " " " " " " Pack " " " " " " " " " " " Set Access " " " " " " " " " Set Program Mask , , , , , , , , , , , , , , Shlft Left Double " " " " " " " Shlft Left Double wgical " , . , " " Shift Left Single " " " " " " ' " Shlft Left Single Logical " " ' " . , ' Shlft Right Double " " " " " ' " Shlft Right Double wgical " , , , , , , , Shift Right Single , . , . , . . . . . . , . , Shlft Right Single Logical " " , . , " Store " " " " " " " " " ' " Store Access Multiple " ' , ... , . , . , "'" Store Character . . . . , . , . , . . . " . 'Store Characters under Mask " ' , . , ' Store Clock , , , , , , , , , , , , , , , . . , Store Halfword . . , " " , , , , , , , , , Store Multiple " " " " " " " " Subtract " " " ' , " " " " " " Subtract Halfword " " " " " " " Subtract Logical " " " " " " ' " Supervisor Call , , , , , , , , , , , , , , , , Test and Set " " " " " " " ' , . Test under Mask "" , , , , , , , , , , , Translate " ' , . , " " " " " ' " Translate and Test " , . , " " " ' " Unpack " " " , . " . , " , ... ,' 7-24 7-25 7-25 7-26 7-27 7-27 7-27 7-28 7-28 7-28 7-29 7-29 7-30 7-30 7-30 7-31 7-31 7-31 7-32 7-32 7-33 7-33 7-37 7-37 7-38 7-39 7-39 7-40 7-40 7-41 7-41 7-42 7-42 7-43 7-43 7-43 7-44 7-44 7-45 7-45 7-45 7-46 7-46 7-46 7-47 7-47 7-48 7-48 7-48 7-49 7-49 7-50 7-50 7-51 7-52 Update Tree 7-52 Chapter 8. Decimal Instructions , . , " , ' Decimal-Number Formats . , , .. , . , .. , Zoned Format . " . . , . . . . " . , . , Packed Format ..,.......,',.. Decimal Codes . , . . . . , . " . " . , . Decimal Operations " " " " " ' , . , Decimal-Arithmetic Instructions , . " . , Editing Instructions " " " " " ' " Execution of Decimal Instructions Other Instructions for Decimal Operands Instructions " " " " , . " . , ' , . , . Add Decimal " " " " " " " ' , . Compare Decimal . . . . , . . . . . . . . . Divide Decimal . " . , . . . . . . . . , . Edit . . . . . . . . . . . , . . . . . . . . . . Edit and Mark . . . . . . . , . . . , . , . . Multiply Decimal . . . . . . . . , . . , . . Shift and Round Decimal . . , . . . . . . Subtract Decimal . . . . . " . . . . . . . Zero and Add . . . . . . . ' . , . . , . . . 8-1 8-1 8-1 8-1 8-2 8-2 8-2 8-3 8-3 8-3 8-3 8-5 8-5 8-6 8-6 8-10 8-10 8-11 8-12 8-12 Chapter 9. Floating-Point Instructions Floating-Point Number Representation Normalization . . . . . . . . , .. , . , . . . . Floating-Point-Data Format ,., . . . . . , Instructions , , " " " ' , " " " , . . Add Normalized " " " " " " ' , . Add Unnormalized , . , " " ' . , ' . . Compare " ' , . . . , ' , . . . " . . . , Divide , . " . , " ' , . , " ... , . . . Halve ... " . , . " . , .. , . , " " wad , . , " " , .. " . , ' , . , ' " wad and Test " , . . , " " , . , . , . wad Complement ... , ' . , . " . , . ,.",,""',.,' Load Negative Load Positive . . , . . , ' , . . , ' , . , ' wad Rounded " . . , . , . . . " . . . , Multiply " , . , . . . . . . . . . . . . . , Store , . . . . . . . . , " , . , " ' , . , Subtract Normalized . , " " ' , " , . Subtract Unnormalized , . . , " " ' " 9-1 9-1 9-2 9-2 9-4 9-7 9-8 9-9 9-9 9-11 9-12 9-12 9-12 9-13 9-13 9-14 9-14 9-16 9-16 9-17 Chapter 10. Control Instructions " " ' " 10-1 Branch and Stack " " , . , ' , . , ' , . 10- 5 Diagnose . , . , ' , . , . , . , " " ' , . 10-7 Extract Primary ASN . , " " " , . , ' 10-7 Extract Secondary ASN " ' , . , " , . 10-8 Extract Stacked Registers " ' , . , . , " 10-8 10-1 0 Extract Stacked State " , " " " " Insert Address Space Control " " " 10-12 Insert PSW Key " " , . . . . , . , " 10-12 Insert Storage Key Extended " " , . , 10-13 Insert Virtual Storage Key . " . , ' " 10-13 Invalidate Page Table Entry " , . , . , 10-14 Contents xi Load Address Space Parameters . . . . Load Control . . . . . . . . . . . . . . Load PSW . . . . . . . . . . . . . . . . Load Real Address . . . . . . . . . . . Load Using Real Address . . . . . . . Modify Stacked State . . . . . . . . . . Move to Primary . . . . . . . . . . . Move to Secondary . . . . . . . . . . . Move with Destination Key . . . . . . Move with Key . . . . . . . . . . . . . Move with Source Key . . . . . . . . . .............. Program Call Program Return . . . . . . . . . . . . . Program Transfer . . . . . . . . . . . . Purge ALB . . . . . . . . . . . . . . . . Purge TLB . . . . . . . . . . . . . . . . Reset Reference Bit Extended . . . . . Set Address Space Control . . . . . . . Set Clock . . . . . . . . . . . . . . . . . Set Clock Comparator . . . . . . . . . Set CPU Timer . . . . . . . . . . . . . Set Prefix . . . . . . . . . . . . . . . . . Set PSW Key from Address . . . . . . Set Secondary ASN . . . . . . . . . . . Set Storage Key Extended . . . . . . . Set System Mask . . . . . . . . . . . . Signal Processor . . . . . . . . . . . . . Store Clock Comparator . . . . . . . . Store Control . . . . . . . . . . . . . . .......... Store CPU Address Store CPU ID ............. Store CPU Timer . . . . . . . . . . . . Store Prefix . . . . . . . . . . . . . . . . Store Then AND System Mask . . . . Store Then OR System Mask . . . . . Store Using Real Address . . . . . . . ............. Test Access " Test Block . . . . . . . . . . . . . . . . Test Protection Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 11. Machine-Check Handling Machine-Check Detection . . . . . . . . . . . Correction of Machine Malfunctions . . . . . Error Checking and Correction . . . . . . CPU Retry . . . . . . . . . . . . . . . . . . Effects of CPU Retry . . . . . . . . . . Checkpoint Synchronization . . . . . . Handling of Machine Checks during Checkpoint Synchronization . . . . Checkpoint-Synchronization Operations Checkpoint-Synchronization Action .. Channel-Subsystem Recovery . . . . . . . Unit Deletion . . . . . . . . . . . . . . . . Handling of Machine Checks . . . . . . . . . xii ESAj370 Principles of Operation 10-16 10-24 10-24 10-25 10-27 10-27 10-29 10-29 10-30 10-31 10-32 10-34 10-44 10-47 10-53 10-53 10-53 10-54 10-55 10-56 10-56 10-56 10-57 10-58 10-61 10-61 10-61 10-63 10-63 10-63 10-64 10-64 10-65 10-65 10-65 10-66 10-66 10-69 10-71 10-73 11-1 11-2 11-2 11-2 11-2 11-3 11-3 11-3 11-3 11-4 11-4 11-4 11-4 Validation . . . . . . . . . . . . . . . . . . 11-5 Invalid CBC in Storage . . . . . . . . . . . 11-6 Programmed Validation of Storage . . . 11-6 Invalid CBC in Storage Keys . . . . . . . 11-7 Invalid CBC in Registers . . . . . . . . . 11-10 Check-Stop State . . . . . . . . . . . . . . . 11-11 System Check Stop . . . . . . . . . . 11-11 Machine-Check Interruption . . . . . . . . 11-11 Exigent Conditions . . . . . . . . . . . . 11-11 Repressible Conditions . . . . . . . . . . 11-12 Interruption Action . . . . . . . . . . . . 11-12 Point of Interruption . . . . . . . . . . . 11-14 Machine-Check-Interruption Code . . . . . 11-14 Subclass . . . . . . . . . . . . . . . . . . . 11-15 . . . . . . . . . . . . 11-15 System Damage Instruction-Processing Damage . . . . 11-16 System Recovery . . . . . . . . . . . . 11-16 Timing-Facility Damage . . . . . . . . 11-16 External Damage . . . . . . . . . . . . 11-16 Vector-Facility Failure . . . . . . . . . 11-17 Degradation . . . . . . . . . . . . . . . 11-17 Warning . . . . . . . . . . . . . . . . . 11-17 Channel Report Pending . . . . . . . 11-17 Service-Processor Damage . . . . . . 11-17 Channel-Subsystem Damage . . . . . 11-17 Subclass Modifiers . . . . . . . . . . . . . 11-18 Vector-Facility Source . . . . . . . . . 11-18 Backed Up . . . . . . . . . . . . . . . 11-18 Delayed Access Exception .. . . . .. 11-18 Synchronous Machine-Check-Interruption Conditions 11-18 Processing Backup . . . . . . . . . . . 11-18 Processing Damage . . . . . . . . . . . 11-19 Storage Errors . . . . . . . . . . . . . . . 11-19 Storage Error Uncorrected . . . . . . 11-19 Storage Error Corrected . . . . . . . . 11-19 Storage-Key Error Uncorrected ... . 11-19 Storage Degradation . . . . . . . . . . 11-19 Indirect Storage Error . . . . . . . . . 11-20 Machine-Check Interruption-Code Validity Bits . . . . . . . . . . . . . . . 11-20 PSW-MWP Validity . . . . . . . . . . 11-20 PSW Mask and Key Validity . . . . . 11-20 PSW Program-Mask and Condition-Code Validity . . . . . . . 11-21 PSW-Instruction-Address Validity .. 11-21 Failing-Storage-Address Validity 11-21 External-Damage-Code Validity 11-21 Floating-Point-Register Validity 11-21 General-Register Validity . . . . . . . 11-21 Contro1-Register Validity . . . . . . . 11-21 Storage Logical Validity . . . . . . . . 11-21 Access-Register Validity . . . . . . . . 11-21 CPU-Timer Validity . . . . . . . . . . 11-21 Clock-Comparator Validity . . . . . . 11-21 Machine-Check Extended Interruption Infonnation . . . . . . . . . . . . . Register-Save Areas . . . . . . . . External-Damage Code . . . . . . Failing-Storage Address . . . . . . Handling of Machine-Check Conditions Floating Interruption Conditions Floating Machine-Check-Interruption Conditions . . . . . . . . . . . Floating I/O Interruptions Machine-Check Masking . . . . . . . . Channel-Report-Pending Subclass Mask . . . . . . . . . . . . Recovery Subclass Mask . . . . . Degradation Subclass Mask ... . External-Damage Subclass Mask . Waming Subclass Mask . . . . . . Machine-Check Logout . . . . . . . . . . . Summary of Machine-Check Masking . Chapter 12. Operator Facilities Manual Operation . . . . . . Basic Operator Facilities .,. Address-Compare Controls Alter-and-Display Controls Architectural-Mode Indicator Architectural-Mode-Selection Controls . Check-Stop Indicator . IML Controls Interrupt Key . . . . . . . Load Indicator . . . . . . . Load-Clear Key . . . . . . Load-Nonnal Key . . . . . . . . . . . . . . Load-Unit-Address Controls . Manual Indicator Power Controls Rate Control . . . . . . . . Restart Key Start Key . . . . . . .... Stop Key . . . . . Store-Status Key . . . . . . . . . . . . System-Reset-Clear Key . . . . . System-Reset-Nonnal Key ..... Test Indicator TO D-Clock Control Wait Indicator . . . . Multiprocessing Configurations 11-22 11-22 11-22 11-22 11-23 11-23 11-23 11-23 11-23 11-24 11-24 11-24 11-24 11-24 11-24 11-24 12-1 12-1 12-1 12-1 12-2 12-2 12-2 12-2 12-2 12-3 12-3 12-3 12-3 12-3 12-3 12-3 12-3 12-4 12-4 12-4 12-4 12-4 12-5 12-5 12-5 12-5 12-5 Chapter 13. 1/0 Overview 13-1 Comparison among ESA/370, 370-XA, and System/370 . . . . . . . . . . . . . . . . . . . 13-1 13-2 The Channel Subsystem . . . . . . . . . Subchannels . . . . . . . . . . . . . . 13-2 13-3 Attachment of Input/Output Devices Channel Paths . . . . . . . . 13-3 Control Units 13-4 13-4 13-5 13-5 13-5 13-5 13-5 13-6 13-6 13-7 13-7 13-8 13-9 I/O Devices ..... . I/O Addressing . . . . . . Channel-Path Identifier Subchannel Number Device Number Device Identifier . . . . . Execution of I/O Operations Start-Function Initiation Path Management . . . . Channel-Program Execution Conclusion of I/O Operations I/O Interruptions . . . . . Chapter 14. 1/0 Instructions I/O-Instruction Fonnats ... 1/0-Instruction Execution Serialization Operand Access Condition Code Program Exceptions Instructions Clear Subchannel Halt Subchannel Modify Subchannel Reset Channel Path Resume Subchannel Set Address Limit Set Channel Monitor Start Subchannel . . . Store Channel Path Status Store Channel Report Word Store Subchannel Test Pending Interruption Test Subchannel . . . . . 14-1 14-1 14-1 14-1 14-1 14-2 14-2 14-2 14-4 14-4 14-6 14-7 14-8 14-10 14-10 14-12 14-14 14-14 14-15 14-16 14-17 Chapter 15. Basic 1/0 Functions Control of Basic I/O Functions Subchannel-Information Block Path-Management-Control Word Subchannel-Status Word . . . . . . . Model-Dependent Area . . . . . Summary of Modifiable Fields Channel-Path Allegiance Working Allegiance Active Allegiance Dedicated Allegiance Channel-Path Availability Control-Unit Type Clear Function . . . . . . . Clear-Function Path Management Clear-Function Subchannel Modification Clear-Function Signaling and Completion Halt Function . . . . . . . . . . . . . . . . . Halt-Function Path Management ... . Halt-Function Signaling and Completion 15-1 15-1 15-1 15-2 . 15-7 15-7 15-7 15-10 15-11 15-11 15-11 15-12 15-12 15-13 15-13 15-13 15-14 15-14 15-15 15-15 Contents xiii Start Function and Resume Function ... Start-Function and Resume-Function Path Management . . . . . . . . . . . . Execution of I/O Operations . . . . . . . . Blocking of Data . . . . . . . . . . . . . Operation-Request Block .. . . . . . . . Channel-Command Wprd . . . . . . . . Command Code . . . . . . . . . : . . . . Designation of Storage Area . . . . . . . Chaining . . . . . . . . . . . . . . . . . . Data Chaining . . . . . . . . . . . . . Command Chaining . . . . . . . . . . Skipping' . . . . . . . . . . . . . . . . . . Program-Controlled Interruption CCW Indirect Data Addressing . . . . . Suspension of Channel-Program Execution . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . Write . . . . . . . . . . . . . . . . . . . Read . . . . . . . . . . . . . . . . . . . Read Backward . . . . . . . . . . . . . Control Sense . . . . . . . . . . . . . . . . . . . Sense ID . . . . . . . . . . . . . . . . . Transfer in Channel . . . . . . . . . . Command Retry . . . . . . . . . . . . . . Concluding I/O Operations During Initiation . . . . . . . . . . . . . . . . . . . Immediate Conclusion of I/O Operations . Concluding I/O Operations During Data Transfer . . . . . . . . . . . . . . . . . . . Channel-Path-Reset Function . . . . . . . Channel-Path-Reset-Function Signaling Channel-Path-Reset Function-Completion Signaling 15-17 15-18 15-19 15-21 15-21 15-23 15-24 15-25 15-26 15-28 15-29 15-30 15-30 15-31 15-32 15-34 15-35 15-35 15-36 15-36 15-37 15-39 15-40 15-41 15-41 15-42 15-42 15-43 15-43 15-44 Chapter 16. 1/0 Interruptions . . . .. 16-1 Interruption Conditions . . . . . . . . . . . 16-2 Intermediate Interruption Condition 16-4 Primary Interruption Condition . . . . . . 16-4 Secondary Interruption Condition . . . . . 16-4 Alert Interruption Condition . . . . . . . . 16-4 Priority of Interruptions . . . . . . . . . . . . 16-5 Interruption Action . . . . . . . . . . . . . . . 16-5 Interruption-Response Block . . . . . . . . . 16-6 Subchannel-Status Word . . . . . . . . . . . . 16-6 Subchannel Key . . . . . . . . . . . . . 16-8 Suspend Control (S) . . . . . . . . . . . 16-8 Extended-Status-Word Format (L) 16-8 Deferred Condition Code (CC) . . . . . 16-8 Format (F) . . . . . . . . . . . . . . . 16-10 Prefetch (P) . . . . . . . . . . . . . . . 16-11 Initial-Status-Interruption Control (I) 16-11 Address- Limit-Checking Control (A) 16-11 Suppress-Suspended Interruption (U) 16-11 Subchannel-Control Field . . . . . . 16-11 xiv ESA/370 Principles of Operation Zero Condition Code (Z) . . . . . . Extended Control (E) . . . . . . . . Path Not Operational (N) . . . . . . Function Control (FC) . . . . . . . Activity Control (AC) . . . . . . . . Status Control (SC) . . . . . . . . . CCW-Address Field . . . . . . . . . . . Device-Status Field Attention . . . . . . . . . . . . . . . Status Modifier . . . . . . . . . . . . Control-Unit End . . . . . . . . . . Busy ... ". . . . . . . . . . . . . . . Channel End . . . . . . . . . . . . . Device End Unit Check Unit Exception . . . . . . . . . . . . Subchannel-Status Field . . . . . . . . Program-Controlled Interruption .. Incorrect Length . . . . . . . . . . . Program Check . . . . . . . . . . . . Protection Check . . . . . . . . . . . Channel-Data Check . . . . . . . . . Channel-Control Check . . . . . . . Interface-Control Check . . . . . . . Chaining Check. . . . . . . . . . . . Count Field . . . . . . . . . . . . . . . Extended-Status Word . . . . . . . . . . . Extended-Status Format 0 . . . . . . . Subchannel Logout . . . . . . . . . Extended-Report Word . . . . . . . Failing-Storage Address . . . . . . . Extended-Status Format I . . . . . . . Extended-Status Format 2 . . . . . . . Extended-Status Format 3 . . . . . . . Extended-Control Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16-11 16-12 16-12 16-13 16-16 16-18 16-23 16-23 16-23 16-24 16-25 16-25 16-26 16-26 16-27 16-28 16-28 16-28 16-29 16-30 16-30 16-31 16-32 16-33 16-33 16-36 16-36 16-36 16-40 16-40 16-40 16-41 16-42 16-43 Chapter 17. 1/0 Support Functions . . . . . 17-1 Channel-Subsystem Monitoring . . . . . . . 17-1 Channel-Subsystem Timing . . . . . . . . 17-1 Channel-Subsystem Timer . . . . . . . 17-2 Measurement-Block Update . . . . . . . . 17-2 Measurement Block . . . . . . . . . . . 17-2 Time-Interval-Measurement Accuracy 17-4 17-5 Device-Connect-Time Measurement Signals and Resets . . . . . . . . . . . . . . . 17-5 Signals . . . . . . . . . . . . . . . . . . . . 17-5 Halt Signal . . . . . . . . . . . . . . . . 17-5 Clear Signal . . . . . . . . . . . . . . . . 17-5 Reset Signal . . . . . . . . . . . . . . . . 17-6 Resets . . . . . . . . . . . . . . . . . . . . . 17-6 Channel-Path Reset . . . . . . . . . . . 17-6 I/O-System Reset . . . . . . . . . . . . 17-6 Externally Initiated Functions . . . . . . . . 17-10 Initial Program Loading . . . . . . . . . 17-10 Reconfiguration of the I/O System 17-12 Status Verification . . . . . . . . . . . . . . Address-Limit Checking . . . . . . . . . . . Configuration Alert . . . . . . . . . . . . . . Incorrect-Length-Indication Suppression Channel-Subsystem Recovery . . . . . . . . Channel Report . . . . . . . . . . . . . . Channel-Report Word . . . . . . . . . . 17-12 17-12 17-13 17-13 17-13 17-14 17-15 Appendix A. Number Representation and Instruction-Use Examples . . . . . . . . . . A-I Number Representation . . . . . . . . . . . . A -2 Binary Integers . . . . . . . . . . . . . . . . A-2 Signed Binary Integers ... ,. . . . . . . A -2 Unsigned Binary Integers . . . . . . . . A-4 Decimal Integers . . . . . . . . . . . . . . . A-5 Floating-Point Numbers . . . . . . . . . . A-5 Conversion Example . . . . . . . . . . . . A-7 Instruction-Use Examples . . . . . . . . . . . A-7 Machine Format . . . . . . . . . . . . . .. A-7 Assembler-Language Format . . . . . . . . A-7 Addressing Mode in Examples . . . . . A-8 General Instructions . . . . . . . . . . . . . . A -8 Add Halfword (AH) . . . . . . . . . . . . . A-8 AND (N, NC, NI, NR) . . . . . . . . . . A-8 NI Example . . . . . . . . . . . . . . . . A-8 Linkage Instructions (BAL, BALR, BAS, BASR, BASSM, BSM) . . . . . . . . . . A-8 Other BALR and BASR Examples A-10 Branch and Stack (BAKR) ... ~ . . .. A-10 BAKR Example 1 . . . . . . . . . . . A-ll BAKR Example 2 . . . . . . . . . . . A-ll BAKR Example 3 . . . . . . . . . . . A-12 Branch on Condition (BC, BCR) . . . . A-12 Branch on Count (BCT, BCTR) A-12 Branch on Index High (BXH) . . . . . . A -13 BXH Example 1 . . . . . . . . . . . . A-13 BXH Example 2 . . . . . . . . . . . . A-13 A-14 Branch on Index Low or Equal (BXLE) BXLE Example 1 . . . . . . . . . . . A -14 BXLE Example 2 . . . . . . . . . . . A-14 Compare Halfword (CH) . . . . . . . . . A-15 Compare Logical (CL, CLC, CLI, CLR) A-15 CLC Example . . . . . . . . . . . . . A -15 CLI Example . . . . . . . . . . . . . . A -16 CLR Example . . . . . . . . . . . . . A-16 Compare Logical Characters under Mask (CLM) . . . . . . . . . . . . . . . . . . A-16 Compare Logical Long (CLCL) . . . . . A-17 Convert to Binary (CVB) . . . . . . . . A-18 Convert to Decimal (CVD) . . . . . . . A-18 Divide (D, DR) . . . . . . . . . . . . . . A-19 Exclusive OR (X, XC, XI, XR) . . . . . A-19 XC Example . . . . . . . . . . . . . . A-19 XI Example . . . . . . . . . . . . . . . A-20 . . . . . . . . . . . . . . . A-21 Execute (EX) Insert Characters under Mask (lCM) Load (L, LR) . . . . . . . . . . . . . . . Load Address (LA) . . . . . . . . . . . . Load Halfword (LH) . . . . . . . . . . . Move (MVC, MVI) . . . . . . . . . . . . MVC Example . . . . . . . . . . . . . MVI Example ............ . Move Inverse (MVCIN) . . . . . . . . . Move Long (MVCL) . . . . . . . . . . . Move Numerics (MVN) . . . . . . . . . Move with Offset (MVO) ....... . .......... . Move Zones (MVZ) Multiply (M, MR) ........... . Multiply Halfword (MH) . . . . . . . . . OR (0, OC, 01, OR) . . . . . . . . . . . 01 Example . . . . . . . . . . . . . . . Pack (PACK) . . . . . . . . . . . . . . . Shift Left Double (SLDA) . . . . . . . . Shift Left Single (SLA) . . . . . . . . . . Store Characters under Mask (STCM) . Store Multiple (STM) . . . . . . . . . . . Test under Mask (TM) . . . . . . . . . . Translate (TR) . . . . . . . . . . . . . . . Translate and Test (TRT) . . . . . . . . Unpack (UNPK) . . . . . . . . . . . . . Decimal Instructions . . . . . . . . . . . . . ........... . Add Decimal (AP) Compare Decimal (CP) . . . . . . . . . . Divide Decimal (DP) . . . . . . . . . . . Edit (ED) . . . . . . . . . . . . . . . . . . Edit and Mark (EDMK) . . . . . . . . . ........ . Multiply Decimal (MP) Shift and Round Decimal (SRP) Decimal Left Shift . . . . . . . . . . . Decimal Right Shift . . . . . . . . . . Decimal Right Shift and Round Multiplying by a Variable Power of 10 Zero and Add (ZAP) . . . . . . . . . . . Floating-Point Instructions . . . . . . . . . Add Normalized (AD, ADR, AE, AER, AXR) . . . . . . . . . . . . . . . . . . . Add Unnormalized (AU, AUR, AW, AWR) . . . . . . . . . . . . . . . . . . . Compare (CD, CDR, CE, CER) Divide (DO, DDR, DE, DER) . . . . . Halve (HDR, HER) .......... . Multiply (MD, MDR, ME, MER, MXD, MXDR, MXR) . . . . . . . . . . . . . Floating-Point-Number Conversion Fixed Point to Floating Point Floating Point to Fixed Point Multiprogramming and Multiprocessing Examples . . . . . . . . . . . . . . . . . . . Example of a Program Failure Using OR ItrUllediate ............... . Contents A-21 A-22 A-22 A-23 A-23 A-23 A-24 A-24 A-25 A-25 A-26 A-26 A-27 A-27 A-28 A-28 A-28 A-28 A-29 A-29 A-30 A-30 A-30 A-31 A-33 A-33 A-33 A-33 A-34 A-34 A-35 A-36 A-36 A-36 A-37 A-37 A-37 A-38 A-38 A-38 A-39 A-39 A-40 A-40 A-40 A-41 A-41 A-41 A-42 A-42 XV Conditional Swapping Instructions (CS, CDS) . . . . . . . . . ... . A-43 . . . . . A-43 Setting a Single Bit . . . . . . . . . A-44 Updating Counters . . . . . . . . . A-44 Bypassing Post and Wait .. Bypass Post Routine . . . . . . . . . . A-44 Bypass Wait Routine . . . . . A-4S Lock/Unlock . . . . . . . . . . . . . . . . A-4S Lock/Unlock with LIFO Queuing for Contentions . . . . . . . . . . . . . . A-4S Lock/Unlock with FIFO Queuing for A-46 Contentions . . . . A-47 Free-Pool Manipulation Appendix B. I.,ists of Instructions B-1 Appendix C. Condition-Code Settings ... C-I Appendix D. Comparison Between 370-XA and ESA/370 . . . . . . . . . New Facilities in ESA/370 . . . Access Registers ... Home Address Space Linkage Stack Load and Store Using Real Address Move with Source or Destination Key .. Private Space . . . . . . . . . . . . . . . Comparison of Facilities . . . . ..... .. . . . . Summary of Changes ...... . New Instructions Provided Comparison of PSW Formats .. . New Control-Register Assignments ... New Assigned Storage Locations New Exceptions . . . . . . . . . . . . . . Change to Secondary-Space Mode Changes to ASN-Second-Table Entry and ASN Translation . . . . . . . . . . Changes to Entry-Table Entry and PC-Number Translation . . . . . Changes to PROGRAM CALL .. . Changes to SET ADDRESS SPACE CONTROL . . . . . . . . . . . . . . xvi ESAj370 Principles of nl~:~ration D-I D-I D-I D-I D-I D-2 D-2 D-2 D-2 D-2 D-2 D-3 D-3 D-3 D-3 D-4 Effects in New Translation Modes . . . . . Effects on Interlocks for Virtual-Storage References . . . . . . . . . . . . . . . . Effect on INSERT ADDRESS SPACE CONTROL . . . . . . . . . . . . . . . Effect on LOAD REAL ADDRESS .. Effect on TEST PENDING INTERRUPTION . . . . . . . . . . . Effect on TEST PROTECTION . . . . D-4 D-5 . D-5 . D-5 . D-5 . D-5 Appendix E. Comparison Between System/370 and 370-XA . . . . . . . . . . . ......... . New Facilities'in 370-XA Bimodal Addressing . . . . . . . . . . . . . 31-Bit Logical Addressing . . . . . . . . . 31-Bit Real and Absolute Addressing .. . Page Protection . . . . . . . . . . . . . . . 'rracing . . . . . . . . . . . . . . . . . . . . Incorrect-Length -Indication' Suppression Status Verification . . . . . . . . . . . . Comparison of Facilities . . . . . . . . . . . . ............ . Summary of Changes Changes in Instructions Provided Input/Output Comparison . . . . . . . . . Comparison of PSW Formats . . . . . . . Changes in Control-Register Assignments Changes in Assigned Storage Locations SIGNAL PROCESSOR Changes . . . . . Machine-Check Changes . . . . . . . . . . Changes to Addressing Wraparound Changes to LOAD REAL ADDRESS .. Changes to 31-Bit Real Operand Addresses E-I E-I E-I E-I E-I E-I E-2 E-2 E-2 E-2 E-3 E-3 E-4 E-5 E-6 E-6 E-7 E-7 E-8 E-8 E-8 Appendix F. Table of Powers of 2 F-I Appendix G. Hexadecimal Tables G-I Appendix H. EBCDIC Chart . . . H-I ................ . X-I D-4 D-4 D-4 D-4 Index Chapter 1. Introduction Highlights of ESA/370 . . . . . . . . Advanced Address-Space Facilities The 370-XA Base System Program . . . . . . . . . . . Compatibility . . . . . . . . . . . . . Compatibility among ESA/370 Systems 1-1 1-1 1-2 1-3 1-3 1-3 This publication provides, for reference purposes, a detailed Enterprise Systems Architecture/370 (ESA/370) description. The architecture of a system defmes its attributes as seen by the programmer, that is, the conceptual structure and functional behavior of the machine, as distinct from the organization of the data flow, the logical design, the physical design, and the performance of any particular implementation. Several dissimilar machine implementations may conform to a single architecture. When the execution of a set of programs on different machine implementations produces the results that are dermed by a single architecture, the implementations are considered to be compatible for those programs. Highlights of ESA/370 ESA/370 is the next step in the evolution from the System/360 to the System/370 to the System/370 extended architecture (370-XA). ESA/370 includes all of the facilities of 370-XA and offers major new facilities. These new facilities add to the virtual storage and 31-bit addressing of 370-XA by further increasing the amount of apparent main storage that is readily available for use. ESA/370 allows the program to operate on data concurrently and efficiently in the instruction address space and other address spaces. ESA/370 also provides increased functions for transferring control between programs, and it includes means for improving the efficiency of the control program. The new facilities of ESA/370 are referred to collectively as the advanced address-space facilities. A detailed comparison of the differences among ESA/370, 370-XA, and System/370 appears in Appendixes D and E. Compatibility among ESA/370, 370-XA, and System/ 370 . . . . . . . . . Control-Program Compatibility Problem-State Compatibility Availability . . . . . . . . . . . . . . 1-4 1-4 1-4 1-4 Advanced Address-Space Facilities The most significant characteristic of the ESA/370 advanced address-space facilities is the improved capability, compared to that of 370-XA, to have programs and data reside in different address spaces. In addition, data can be accessed in multiple address spaces concurrently, which increases the amount of data that can be processed concurrently; and unprivileged instructions can be used to select the address spaces to be accessed, which increases the amount of data that can be processed without control-program intervention. The following is a summary of the new facilities of ESA/370. • Sixteen access registers permit the program to have immediate access to storage operands in up to 16 2G-byte address spaces, including the address space in which the program resides. In a dynamic-address-translation mode called access-register mode, the instruction B field, or for certain instructions the R field, designates both a general register and an access register, and the contents of the access register, along with the contents of protected tables, specify the operand address space to be accessed. By changing the contents of the access registers, the program, under the control of an authorization mechanism, can have fast access to hundreds of different operand address spaces. Instructions are provided for changing between the access-register mode and other translation modes and for loading and storing the contents of the access registers. For address spaces not containing programs, the number of possible address spaces is not limited to 65,536, as it is in 370-XA. • A linkage stack is used in a functionally expanded mechanism for passing control Chapter 1. Introduction 1-1 between programs in either the same or different address spaces. This mechanism makes use also of the previously existing PROGRAM CALL instruction, an extended entry-table entry, and a new PROGRAM RETURN instruction. The mechanism saves various elements of status, including access-register and generalregister contents, during a calling linkage, provides for changing the current status during the calling linkage, and restores the original status during the returning linkage. A significant benefit is that each program in a sequence of calling and called programs can have degrees of privilege and authority that are arbitrarily different from those of programs before or after it in the sequence, including the authority to access address spaces by means of access registers. ·The linkage stack can also be used to save and restore access-register and general-register contents during a branch-type linkage performed by the new instruction BRANCH AND STACK. Instructions are provided for examining the contents of the linkage stack, for changing those contents in a limited way, and for testing the authorization of a calling program. • A translation mode called home-space mode provides an efficient means for the control program to obtain control in the address space, called the home address space, in which the principal control blocks for a dispatchable unit (a task or process) are kept. The space-switch event is extended to allow indication of a transfer of control to or from the home address space. • The semiprivileged MOVE WITH SOURCE KEY and MOVE WITH DESTINATION KEY instructions allow bidirectional movement of data between storage areas having different storage keys, without the need to change the psw key. • The privileged LOAD USING REAL ADDRESS and STORE USING REAL ADDRESS instructions allow the control program to access data in real storage more efficiently. A program-eventrecording store-using-real-address event provides serviceability. • The private-space facility provides a bit, the private-space-controlbit, in the segment-table designation. This bit, when one, causes the address space dermed by the segment-table designation not to contain any common segments and causes low-address protection and fetch- 1-2 ESA/370 Principles of Operation protection override not to apply to the address space. In order to use access registers to access different address spaces, the program must be coded to manage the contents of the access registers. Programs containing the existing PROGRAM CALL instruction can make use of the linkage stack without any change to the programs, although efficiency will be improved if existing saving and restoring functions of the programs are eliminated. The 370-XA Base ESA/370 includes the complete set of facilities of 370-XA as its base. This section briefly outlines most of the facilities that were added to System/370 to form 370-XA. The cPu-related facilities are as follows. • Bimodal addressing provides two modes of operation: .a 24-bit addressing mode for the execution of old programs and a 3 I-bit addressing mode. • 31-bit logical addressing extends the virtual address space from the 16M bytes addressable 24-bit addresses to 2G bytes with (2,147,483,648 bytes). • 31-bit real and absolute addressing provides addressability for up to 2G bytes of main storage. • The 370-XA protection facilities include keycontrolled protection on only 4K-byte blocks, page protection, and, as in System/370, lowaddress protection for addresses below 512. Fetch-protection override eliminates fetch protection for locations 0-2047. • The tracing facility assists in the determination of system problems by providing an ongoing record in storage of significant events. • The COMPARE AND FORM CODEWORD and UPDATE TREE instructions facilitate sorting applications. The I/o-related differences between 370-XA and System/370 result from the 370-XA channel subsystem, which includes: • Path-independent addressing of I/O devices, which permits the initiation of I/O operations without regard to which CPU is executing the I/O instruction or how the I/O device is attached to the channel subsystem. Any I/O interruption can be handled by any CPU enabled for it. • Path management, whereby the channel subsystem determines which paths are available for selection, chooses a path, and manages any busy conditions encountered while attempting to initiate I/0 processing with the associated devices. • Dynamic reconnection, which pennits any I/0 device using this capability to reconnect to any available channel path to which it has access in order to continue execution of a chain of commands. • Programmable interruption subclasses, which pennit the programmed assignment of I/o-interruption requests from individual I/O devices to anyone of eight maskable interruption queues. • An additional CCW format for the direct use of 31-bit addresses in channel programs. The new ccw format, called format 1, is provided in addition to the System/370 ccw format, now called format O. • Address-limit checking, which provides an additional storage-protection facility to prevent data access to storage locations above or below a specified absolute address. • Monitoring facilities, which can be invoked by the program to cause the channel subsystem to measure and accumulate key I/o-resource usage parameters. • Status-verification facility, which reports inappropriate combinations of device-status bits presented by a device. • A set of 13 I/O instructions, with associated control blocks, which are provided for the control of the channel subsystem. The facilities appearing in System/370 but not provided in 370-XA are described in Appendix E. System Program ESA/370 is designed to be used with a control program that coordinates the use of system resources and executes all I/O instructions, handles exceptional conditions, and supervises scheduling and execution of multiple programs. Compatibility Compatibility among ESA/370 Systems Although systems operating as dermed by ESA/370 may differ in implementation and physical capabilities, logically they are upward and downward compatible. Compatibility provides for simplicity in education, availability of system backup, and ease in system growth. Specifically, any program written for ESA/370 gives identical results on any ESA/370 implementation, provided that the program: 1. Is not time-dependent. 2. Does not depend on system facilities (such as storage capacity, I/O equipment, or optional . facilities) being present when the facilities are not included in the configuration. 3. Does not depend on system facilities being absent when the facilities are included in the configuration. For example, the program must not depend on interruptions caused by the use of operation codes or command. codes that are not installed in some models. Also, it must not use or depend on fields associated with uninstalled facilities. For example, data should not be placed in an area used by another model for fixed-logout information. Similarly, the program must not use or depend on unassigned fields in machine formats (control registers, instruction formats, etc.) that are not explicitly made available for program use. 4. Does not depend on results or functions that are defined to be unpredictable or modeldependent or are identified as undefined. This includes the requirement that the program should not depend on the assignment of device numbers and CPU addresses. 5. Does not depend on results or functions that are dermed in the functional-characteristics publication for a particular model to be deviations from the architecture. 6. Takes into account any changes made to the architecture that are identified as affecting compatibility. Chapter 1. Introduction 1-3 Programming Notes: Compatibility among ESA/370, 370-XA, and System/370 1. This publication assigns meanings to various operation codes, to bit positions in instructions, channel-command words, registers, and table entries, and· to fixed locations in the low 512 bytes of storage. Unless specifically noted, the remaining operation codes, bit positions, and low-storage locations are reserved for future assignment to new facilities and other extensions of the architecture. Control-Program Compatibility Control programs written for 370-XA can be directly transferred to systems operating as defmed by FSA/370. Almost all of the new functions of FSA/370 are enabled only when a control-register bit assigned only in FSA/370 is set to one. When this bit is zero, the machine operates essentially as specified for 370-XA; the most significant exceptions are ( I) instructions that load and store the contents of the access registers can be executed successfully, and (2) certain previously unassigned real and absolute storage locations below address 512 are stored in during the store-status operation, certain program interruptions, and the machine-check interruption. When the new control-register bit is zero, no unprivileged or semiprivileged instruction can place the CPU in the access-register mode, and so the access registers cannot be used to specify address spaces. To ensure that existing programs operate if and when such new facilities are installed, programs should not depend on an indication of an exception as a result of invalid values that are .currently defmed as being checked. If a value must be placed in unassigned positions that are not checked, the program should enter zeros. When the machine provides a code or field, the program should take into account that new codes and bits may be assigned in the future. The program should not use unassigned lowstorage locations for keeping information since these locations may be assigned in the future in such a way that the machine causes the contents of the locations to be changed. Control programs written for System/ 370 cannot be directly transferred to systems operating as defmed by FSA/370. This is because in the 370-XA base of FSA/370 the basic-control mode is not present and the facilities for I/O and dynamic address translation are changed. (See Appendixes D and E for a detailed comparison among FSA/370, 370-XA, and System/370.) 2. If a control program is used that does not support the use of access registers, a problemstate program under this control program still is able to load and store the contents of the access registers, and it might do so simply to use the access registers for data storage instead of for addressing. However, the use of access registers in such circumstances may be unsuccessful because the unsupporting control program does not save and restore the contents of the access registers when switching between dispatchable units. Furthermore, the use of access registers in such circumstances may constitute a loss of security because the contents of access registers loaded by one dispatchable unit will be visible to other dispatchable units. To avoid the problems referred to here, a program using access registers must be executed only in a system with a control program that properly supports the use of access registers. Problem-State Compatibility A high degree of cOlnpatibility exists at the problem-state level in going forward from 370-XA or System/370 to FSA/370. Because the majority of a user's applications are written for the problem state, this problem-state compatibility is useful in many installations. A problem-state program written for 370-XA or System/370 operates with FSA/370, provided that the program: 1. Complies with the limitations described in the "Compatibility among ESA/370 section Systems" in this chapter. 2. Is not dependent on control-program facilities which are unavailable on the system. 3. Takes into account other changes made to the System/370 architectural defmition that affect compatibility between System/370 and the 370-XA base of FSA/370. These changes are described in Appendix E. 1-4 ESA/370 Principles of Operation c Availability A vailability is the capability of a system to accept and successfully process an individual job. Systems operating in accordance with FSA/370 permit substantial availability by (1) allowing a large number and broad range of jobs to be processed concur- rently, thus making the system readily accessible to any particular job, and (2) limiting the effect of an error and identifying more precisely its cause, with the result that the number of jobs affected by errors is minimized and the correction of the errors facilitated. Several design aspects make this possible. • A program is checked for the correctness of instructions and data as the program is executed, and program errors are indicated separate from equipment errors. Such checking and reporting assists in locating failures and isolating effects. • The protection facilities, in conjunction with dynamic address translation and the separation of programs and data in different address spaces, permit the protection of the contents of storage from destruction or misuse caused by erroneous or unauthorized storing or fetching by a program. This provides increased security for the user, thus permitting applications with different security requirements to be processed concurrently with other applications. • Dynamic address translation allows isolation of one application from another, still permitting them to share common resources. Also, it permits the implementation of virtual machines, which may be used in the design and testing of new versions of operating systems along with the concurrent processing of application programs. Additionally, it provides for the concurrent operation of incompatible operating systems. • The use of access registers to have programs and data and also different collections of data reside in different address spaces further reduces the likelihood that a store using an incorrect address will produce either erroneous results or a system-wide failure. • Multiprocessing and the channel subsystem permit better use of storage and processing capabilities, more direct communication between cpus, and duplication of resources, thus aiding in the continuation of system operation in the event of machine failures. • MONITOR CALL, program-event recording, and the timing facilities permit the testing and debugging of programs without manual intervention and with little effect on the concurrent processing of other programs. • On most models, error checking and correction (ECC) in main storage, CPU retry, and command retry provide for circumventing intermittent equipment malfunctions, thus reducing the number of equipment failures. • An enhanced machine-cheek-handling mechanism provides model-independent fault isolation, which reduces the number of programs impacted by uncorrected errors. Additionally, it provides model-independent recording of machine-status information. This leads to greater machine-check-handling compatibility between models and improves the capability for loading and operating a program on a different model when a system failure occurs. • A small number of manual controls are required for basic system operation, permitting most operator-system interaction to take place via a unit operating as an 1/0 device and thus reducing the possibility of operator errors. Chapter 1. Introduction 1-5 Chapter 2. Organization Main Storage CPU PSW (Jeneral Ftegjsters Floating-Point Ftegjsters Control Regjsters 2-2 2-2 2-2 2-3 2-3 2-3 Logjcally, a system consists of main storage, one or more central processing urnts (cPus), operator facilities, a chartl1el subsystem, artd I/O devices. I/O devices are attached to the channel subsystem through control urnts. The connection between the chal1l1el subsystem artd a control urnt is called a chal1l1el path. The physical identity of these functions may vary among implementations, called "models." Figure 2-1 depicts the logjcal structure of a two-cPU multiprocessing system. Specific processors may differ in their internal characteristics, the installed facilities, the number of subchartl1els, chartl1el paths, artd control urnts which cart be attached to the chartl1el subsystem, the size of main storage, artd the representation of the operator facilities. The differences in internal characteristics are apparent to the observer only as differences in machine performance. A system viewed without regard to its I/O devices is referred to as a configuration. All of the physical equipment, whether in the configuration or not, is referred to as the installation. Model-dependent reconfiguration controls may be provided to chartge the amount of main storage and the number of CPUs artd chartl1el paths in the configuration. In some instartces, the reconfiguration controls may be used to partition a single configuration into multiple configurations. Each of the configurations so reconfigured has the same structure, that is, main storage, one or more cpus, and one or more subchal1l1els artd chal1l1el paths in the chartl1el subsystem. Each configuration is isolated in that the main storage in one configuration is not directly addressable by the CPUs and the chartl1el subsystem of artother configuration. It is, however, possible for one configuration to communicate with another by means of shared I/O devices or a channel-tochannel adapter. At arty one time, the storage, CPus, subchannels, and channel paths connected 2-3 Access Ftegjsters Vector Facility . I/O . . . . . . . . . Chal1l1el Subsystem I/O Devices artd Control Urnts Operator Facilities . . . . . . . . 2-4 2-4 2-6 2-6 2-6 together in a system are referred to as being in the configuration. Each CPU, subchannel , chal1l1el path, artd main-storage location Cart be in only one configuration at a time. CPU ,- I CPU ~ '-- Main Storage Channel Subsystem 1111' "1 Channel Paths II / / ~------~------/ "-----,-----/ t--r--,--r-/ 000 ~-~-~------~---/ Figure 2-1. Logical Structure of an ESA/370 System with Two CPUs Chapter 2. Organization 2-1 ~, 1"'---_ _ _ Main Storage Main storage, which is directly addressable, provides for high-speed processing of data by the CPUs and the channel subsystem. Both data and programs must be loaded into main storage from input devices before they can be processed. The amount of main storage available on the system depends on the model, and, depending on the model, the amount in the configuration may be under control of model-dependent configuration controls. The storage is available in multiples of 4K-byte blocks. At any instant in time, the channel subsystem and all CPUs in the configuration have access to the same blocks of storage and refer to a particular block of main-storage locations by using the same absolute address. Main storage may include a faster-access buffer storage, sometimes called a cache. Each CPU may have an associated cache. The effects, except on performance, of the physical construction and the use of distinct storage media are not observable by the program. CPU The central processing unit (cpu) is the controlling center of the system. It contains the sequencing and processing facilities for instruction execution interruption action, timing functions, initiai program loading, and other machine-related functions. The physical implementation of the CPU may differ arnong models, but the logical function remains the same. The result of executing an instruction is the same for each model, providing that the program complies with the compatibility rules. The CPU, in executing instructions, can process binary integers and floating-point numbers of fixed length, decimal integers of variable length, and logical information of either fixed or variable length. Processing may be in parallel or in series; the width of the processing elements, the multiplicity of the shifting paths, and the degree of simultaneity in performing the different types of arithmetic differ from one CPU to another without affecting the logical results. Instructions which the CPU executes fall into five classes: general, decimal, floating-point, control, and I/O instructions. The general instructions are used in performing binary-integer-arithmetic opera- 2-2 ESA/370 Principles of Operation tions and logical, branching, and other nonarithmetic operations. The decimal instructions operate on data in the decimal format, and the floatingpoint instructions on data in the floating-point format. The privileged control instructions and the I/O instructions can be executed only when the CPU is in the supervisor state; the semiprivileged control instructions can be executed in the problem state subject to the appropriate authorization mech~ anisms. To perform its functions, the CPU may use a certain amount of internal storage. Although this internal storage may use the same physical storage medium as main storage, it is not considered part of main storage and is not addressable by programs. The CPU provides registers which are available to programs but do not have addressable representations in main storage. They include the current program-status word (psw), the general registers, the floating-point registers, the control registers, the access registers, the prefix register, and the registers for the clock comparator and the CPU timer. Each CPU in an installation provides access to a time-of-day (TaD) clock, which may be local to that CPU or shared with other CPus in the installation. The instruction operation code determines which type of register is to be used in an operation. See Figure 2-2 on page 2- 5 for the format of those registers. PSW The program-status word (psw) includes the instruction address, condition code, and other information used to control instruction sequencing and to determine the state of the CPU. The active or controlling psw is called the current psw. It governs the program currently being executed. The CPU has an interruption capability, which permits the CPU to switch rapidly to another program in response to exceptional conditions and external stimuli. When an interruption occurs, the cpu places the current psw in an assigned storage location, called the old- psw location, for the particular class of interruption. The CPU fetches a new psw from a second assigned storage location. This new psw determines the next program to be executed. When it has finished processing the interruption, the interrupting program may reload the old psw, making it again the current psw, so that the interrupted program can continue. There are six classes of interruption: external, I/O, machine check, program, restart, and supervisor call. Each class has a distinct pair of old-psw and new- psw locations permanently assigned in real storage. General Registers Instructions may designate infonnation in one or more of 16 general registers. The general registers may be used as base-address registers and index registers in address arithmetic and as accumulators in general arithmetic and logical operations. Each register contains 32 bits. The general registers are identified by the numbers 0-15 and are designated by a four-bit R field in an instruction. Some instructions provide for addressing multiple general registers by having several R fields. For some instructions, the use of a specific general register is implied rather than explicitly designated by an R field of the instruction. For some operations, two adjacent general registers are coupled, providing a 64-bit format. In these operations, the program nlUst designate an evennumbered register, which contains the leftmost (high-order) 32 bits. The next higher-numbered register contains the rightmost (low-order) 32 bits. In addition to their use as accumulators in general arithmetic and logical operations, 15 of the 16 general registers are also used as base-address and index registers in address generation. In these cases, the registers are designated by a four-bit B field or X field in an instruction. A value of zero in the B or X field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index. Floating-Point Registers Four floating-point registers are available for floating-point operations. They are identified by the numbers 0, 2, 4, and 6 and are designated by a four-bit R field in floating-point instructions. Each floating-point register is 64 bits long and can contain either a short (32-bit) or a long (64-bit) floating-point operand. A short operand occupies the leftmost bit positions of a floating-point register. The rightmost portion of the register is ignored in operations that use short operands and remains unchanged in operations that produce short results. Two pairs of adjacent floating-point registers can be. used for extended operands: registers 0 and 2, and registers 4 and 6. Each of these pairs, identified by the numbers 0 and 4, provides for a 128-bit format. Control Registers The CPU has 16 control registers, each having 32 bit positions. The bit positions in the registers are assigned to particular facilities in the system, such as program-event recording, and are used either to specify that an operation can take place or to furnish special information required by the facility. The control registers are identified by the numbers 0-15 and are designated by four-bit R fields in the instructions LOAD CONTROL and STORE CONTROL. Multiple control registers can be addressed by these instructions. Access Registers ESA/370 introduces 16 access registers numbered 0-15. An access register consists of 32 bit positions containing an indirect specification (not described here in detail) of a segtnent-table designation. A segment-table designation is a parameter used by the dynamic-address-translation (DAT) mechanism to translate references to a corresponding address space. When the CPU is in a mode called the access-register mode (controlled by bits in the psw), an instruction B field, used to specify a logical address for a storage-operand reference, designates an access register, and the segment-table designation specified by the access register is used by OAT for the reference being made. For some instructions, an R field is used instead of a B field. Instructions are provided for loading and storing the contents of the access registers and for moving the contents of one access register to another. Each of access registers 1-15 can designate any address space, including the current instruction space (the primary address space). Access register 0 always designates the current instruction space. When one of access registers 1-15 is used to designate an address space, the CPU determines which address space is designated by translating the contents of the access register. When access register 0 is used to designate an address space, the CPU treats the access register as designating the current instruction space, and it does not examine the actual contents of the access register. Therefore, the 16 access registers can designate, at anyone time, the current instruction space and a maximum of 15 other spaces. Chapter 2. Qrganization 2-3 Vector Facility 1/0 Depending on the model, a vector facility may be provided as an extension of the Cpu. When the vector facility is provided on a CPU, it functions as an integral part of that cpu. The functions of the vector facility· and its registers are described in the publication Enterprise Systems Architecture/370 and System/370 Vector Operations, SA22-7125. Input/output (I/O) operations involve the transfer of information between main storage and an I/O device. I/O devices and their control units attach to the channel subsystem, which controls this data transfer. 2-4 ESAj370 Principles of Operation R Field and Register Number Control Registers 1+-32 Access Registers bi ts.... 1 1+-32 I I eae1 1 I I 2 I I eaee a ea1e bits"" 1 1+-32 Floating-Point Registers bits"" 1 1~64 bf ts------' 1 ] [I ] I [I eOll 3 I I 4 I I ele1 5 I I eue 6 I I elee General Registers I [II I I I I [I eUl 7 I I 10ea 8 I I I [I 1ee1 9 I I I I 1911 11 I I uee 12 I I lela Ie [I 1191 13 I I 1U9 14 I I lUI 15 I I I I [I J Note: The brackets indicate that the two registers may be coupled as a double-register pair, designated by specifying the lowernumbered register in the R field. For example, the generalregister pair 14 and 15 is designated by 111e binary in the R field. I [I I Figure 2-2. Control, Access, General, and Floating-Point Registers Chapter 2. Organization 2-5 Channel Subsystem The channel subsystem directs the flow of information between I/O devices and main storage. It relieves CPus of the task of communicating directly with I/O devices and permits data processing to proceed concurrently with I/O processing. The channel subsystem uses one or more channel paths as the communication link in managing the flow of infonnation to or from I/O devices. As part of I/O processing, the channel subsystem also performs the path-management function of testing for channel-path availability, selecting an available channel path, and initiating execution of the operation with the I/O device. Within the channel subsystem are subchannels. One subchannel is provided for and dedicated to each I/O device accessible to the channel subsystem. Each subchannel contains storage for information concerning the associated I/O device and its attachment to the channel subsystem. The subchannel also provides storage for information concerning I/O operations and other functions involving the associated I/O device. Information contained in the subchannel can be accessed by CPus using I/O instructions as well as by the channel subsystem and serves as the means of communication between any CPU and the channel subsystem concerning the associated I/O device. The actual number of subchannels provided depends on the model and the configuration; the maximum number of subchannels is 65,536. I/O devices are attached through control units to the channel subsystem via channel paths. Control units may be attached to the channel subsystem via more than one channel path, and an I/O device may be attached to more than one control unit. In all, 2-6 ESAj370 Principles of Operation an individual I/O device may be accessible to the channel subsystem by as many as eight different channel paths, depending on the model and the configuration. The total number of channel paths provided by a channel subsystem depends on the model and the configuration; the maximum number of channel paths is 256. 1/0 Devices and Control Units I/O devices include such equipment as card readers and punches, magnetic-tape units, direct-access storage, displays, keyboards, printers, teleprocessing devices, communications controllers, and sensorbased equipment. Many I/O devices function with an external medium, such as punched cards or magnetic tape. Some I/O devices handle only electrical signals, such as those found in sensor-based networks. In either case, I/o-device operation is regulated by a control unit. In all cases, the control-unit function provides the logical and buffering capabilities necessary to operate the associated I/0 device. From the programming point of view, most control-unit functions merge with I/o-device functions. The control-unit function may be housed with the I/O device or in the CPU, or a separate control unit may be used. Operator Facilities The operator facilities provide the functions necessary for operator control of the machine. Associated with the operator facilities may be an operator-console device, which may also be used as an I/O device for communicating with the program. The main functions provided by the operator facilities include resetting, clearing, initial program loading, start, stop, alter, and display. Chapter 3. Storage Storage Addressing Information Formats Integral Boundaries Address Types and Formats Address Types Absolute Address Real Address Virtual Address Primary Virtual Address Secondary Virtual Address AR -Specified Virtual Address Home Virtual Address Logical Address .. Instruction Address Effective Address Address Size and Wraparound Address Wraparound Storage Key . . . . . . . . . . Protection . . . . . . . . . . . Key-Controlled Protection Fetch-Protection-Override Control Page Protection Low-Address Protection Reference Recording Change Recording Prefixing . . . . . . . Address Spaces Changing to Different Address Spaces Address-Space Number ASN Translation . . . . . . . ASN-Translation Controls Control Register 14 Control Register 0 ASN-Translation Tables ASN-First-Table Entries ASN-Second-Table Entries ASN-Translation Process ... ASN -First-Table Lookup ASN-Second-Table Lookup 3-2 3-2 3-3 3-3 3-3 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-5 3-5 3-5 3-5 3-7 3-8 3-8 3-9 3-9 3-10 3-10 3-11 3-11 3-13 3-13 3-13 3-14 3-15 3-15 3-15 3-15 3-15 3-16 3-17 3-18 3-19 This chapter discusses the representation of information in main storage, as well as addressing, protection, and reference and change recording. The aspects of addressing which are covered include the format of addresses, the concept of address spaces, the various types of addresses, and the manner in which one type of address is translated to another type of address. A list of permanently assigned storage locations appears at the end of the chapter. Recognition of Exceptions during AS N Translation . . . . . . . ASN Authorization . . . . . . . ASN -Authorization Controls Control Register 4 ASN-Second-Table Entry Authority-Table Entries ASN -Authorization Process Authority-Table Lookup Recognition of Exceptions during ASN Authorization . . . . . Dynamic Address Translation Translation Control Translation Modes Control Register 0 Control Register 1 Control Register 7 Control Register 13 Translation Tables . . Segment-Table Entries Page-Table Entries .. Summary of Segment-Table and Page-Table Sizes . . . . . . . . Translation Process . . . . . . . . . Effective Segment-Table Designation Inspection of Control Register 0 Segment-Table Lookup Page-Table Lookup . . . . . . . Formation of the Real Address Recognition of Exceptions during Translation . . . . . . . Translation-Lookaside Buffer TLB Structure . . . . . . Formation of TLB Entries Use of TLB Entries Modification of Translation Tables Address Summary Addresses Translated Handling of Addresses Assigned Storage Locations 3-19 3-19 3-19 3-20 3-20 3-20 3-20 3-22 3-22 3-22 3-24 3-24 3-24 3-24 3-25 3-25 3-26 3-26 3-27 3-27 3-27 3-28 3-30 3-30 3-30 3-31 3-31 3-31 3-31 3-32 3-32 3-33 3-35 3-35 3-36 3-39 Main storage provides the system with directly addressable fast-access storage of data. Both data and programs must be loaded into main storage (from input devices) before they can be processed. Main storage may include one or more smaller faster-access buffer storages, sometimes called caches. A cache is usually physically associated Chapter 3. Storage 3-1 with a CPU or an I/O processor. The effects, except on performance, of the physical construction and use of distinct storage media are not observable by the program. to-right sequence. Addresses are either 24-bit or 31-bit unsigned binary integers and are described in the section "Address Size and Wraparound" in this chapter. Fetching and storing of data by a CPU are not affected by any concurrent channel-subsystem activity or by a concurrent reference to the same storage location by another CPU. When concurrent requests to a main-storage location occur, access normally is granted in a sequence that assigns highest priority to references by the channel subsystem, the priority being rotated among CPUs. If a reference changes the contents of the location, any subsequent.storage fetches obtain the new contents. Information Formats Main storage may be volatile or nonvolatile. If it is volatile, the contents of main storage are not preserved when power is turned off. If it is nonvolatile, turning power off and then back on does not affect the contents of main storage, provided all CPUs are in the stopped state and no references are made to main storage when power is being turned off. In both types of main storage, the contents of the storage key are not necessarily preserved when the power for main storage is turned off. Note: Because most references in this publication apply to virtual storage, the abbreviated term "storage" is often used in place of "virtual storage." The term "storage" may also be used in place of "main storage," "absolute storage," or "real storage" when the meaning is clear. The terms "main storage" and "absolute storage" are used to describe storage which is addressable by means of an absolute address. The tenus describe fast-access storage, as opposed to auxiliary storage, such as provided by direct-access storage devices. "Real storage" is synonymous with "absolute storage" except for the effects of prefixing. Storage Addressing Storage is viewed as a long horizontal string of bits. For most operations, accesses to storage proceed in a left-to-right sequence. The string of bits is subdivided into units of eight bits. An eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte location in storage is identified by a unique nonnegative integer, which is the address of that byte location or, simply, the byte address. Adjacent byte locations have consecutive addresses, starting with 0 on the left and proceeding in a left- 3-2 ESAj370 Principles of Operation Information is transmitted between storage and a CPU or the channel subsystem one byte, or a group of bytes, at a time. Unless otherwise specified, a group of bytes in storage is addressed by the leftmost byte of the group. The number of bytes in the group is either implied or explicitly specified by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, bits are numbered in a left-to-right sequence. The leftmost bits are sometimes referred to as the "high-order" bits and the rightmost bits as the "low-order" bits. Bit numbers are not storage addresses, however. Only bytes can be addressed. To operate on individual bits of a byte in storage, it is necessary to access the entire byte. The bits in a byte are numbered 0 through 7, from left to right. The bits in an address are numbered 8 through 31 for 24-bit addresses and I through 31 for 31-bit addresses. Within any other fixed-length format of multiple bytes, the bits making up the format are consecutively numbered starting from O. For purposes of error detection, and in some models for correction, one or more check bits may be transmitted with each byte or with a group of bytes. Such check bits are generated automatically by the machine and cannot be directly controlled by the program. References in this publication to the length of data fields and registers exclude mention of the associated check bits. All storage capacities are expressed in number of bytes. When the length of a storage-operand field is implied by the operation code of an instruction, the field is said to have a fixed length, which can be one, two, four, or eight bytes. Larger fields may be implied for some instructions. When the length of a storage-operand field is not implied but is stated explicitly, the field is said to have a variable length. Variable-length operands can vary in length by increments of one byte. When infonnation is placed in storage, the contents of only those byte locations are replaced that are included in the designated field, even though the width of the physical path to storage may be greater than the length of the field being stored. - -.... Storage Addresses Bytes I ell I 2 I 3 I 4 I 5 I 6 I 7 I B I Integral Boundaries Certain units of infonnation must be on an integral boundary in storage. A boundary is called integral for a unit of infonnation when its storage address is a multiple of the length of the unit in bytes. Special names are given to fields of two, four, and eight bytes on an integral boundary. A halfword is a group of two consecutive bytes on a two-byte boundary and is the basic building block of instructions. A word is a group of four consecutive bytes on a four-byte boundary. A doubleword is a group of eight consecutive bytes on an eight-byte boundary. (See Figure 3-1.) When storage addresses designate halfwords, words, and doublewords, the binary representation of the address contains one, two, or three rightmost zero bits, respectively. Instructions must be on two-byte integral boundaries, and ccws, IDAWS, and the storage operands of certain instructions must be on other integral boundaries. The storage operands of most instructions do not have boundary-alignment requirements. Doublewords Figure Ie: : : : : : : I B : 3-1. Integral Boundaries Addresses with Storage Programming Note: For fixed-field-length operations with field lengths that are a power of 2, significant perfonnance degradation is possible when storage operands are not positioned at addresses that are integral multiples of the operand length. To improve perfonnance, frequently used storage operands should be aligned on integral boundaries. .Address Types and Formats Address Types For purposes of addressing main storage, three basic types of addresses are recognized: absolute, real, and virtual. The addresses are distinguished on the basis of the transfonnations that are applied to the address during a storage access. Address translation converts virtual to real, and prefixing converts real to absolute. In addition to the three basic address types, additional types are defined which are treated as one or another of the three basic types, depending on the instruction and the current mode. Chapter 3. Storage 3-3 Absolute Address An absolute address is the address assigned to a main-storage location. An absolute address is used for a storage access without any transformations performed on it. The channel subsystem and all CPus in the configuration refer to a shared main -storage location by using the same absolute address. Available main storage is usually assigned contiguous absolute addresses starting at 0, and the addresses are always assigned in complete 4K-byte blocks on integral boundaries. An exception is recognized when an attempt is made to use an absolute address in a block which has not been assigned to physical On some models, storagelocations. reconfiguration controls may be provided which permit the operator to change the correspondence between absolute addresses and physical locations. However, at anyone time, a physical location is not associated with more than one absolute address. Storage consisting of byte locations sequenced according to their absolute addresses is referred to as absolute storage. Real Address A real address identifies a location in real storage. When a real address is used for an access to main storage, it is converted, by means of prefixing, to an absolute address. At any instant there is one real-address to. absoluteaddress mapping for each CPU in the configuration. When a real address is used by a CPU to access main storage, it is converted to an absolute address by prefixing. The particular transformation is defined by the value in the prefix register for the CPU. Storage consisting of byte locations sequenced according to their real addresses is referred to as real storage. Virtual Address A virtual address identifies a location in virtual storage. When a virtual address is used for an access to main storage, it is translated by means of dynamic address translation to a r~al address, which is then further converted by prefixing to an absolute address. 3-4 ESA/370 Principles of Operation Primary Virtual Address A primary virtual address is a virtual address which is to be translated by means of the primary segment-table designation. Logical addresses are treated as primary virtual addresses when in the primary-space mode. Instruction addresses are treated as primary virtual addresses when in the primary-space mode, secondary-space mode, or access-register mode. The first-operand address of MOVE TO PRIMARY and the second-operand address of MOVE TO SECONDARY are always treated as primary virtual addresses. Secondary Virtual Address A secondary virtual address is a virtual address which is to be translated by means of the secondary segment-table designation. Logical addresses are treated as secondary virtual addresses when in the The second-operand secondary-space mode. address of MOVE TO PRIMARY and the frrst-operand address of MOVE TO SECONDARY are always treated as secondary virtual addresses. AR-Specified Virtual Address An AR-specified virtual address is a virtual address which is to be translated by means of an accessregister-specified segment-table designation. Logical addresses are treated as AR-specified addresses when in the access-register mode. Home Virtual Address A home virtual address is a virtual address which is to be translated by means of the home segmenttable designation. Logical addresses and instruction addresses are treated as home virtual addresses when in the home-space mode. Logical Address Except where otherwise specified, the storageoperand addresses for most instructions are logical addresses. Logical addresses are treated as real addresses in the real mode, as primary virtual addresses in the primary-space mode, as secondary virtual addresses in the secondary-space mode, as AR-specified virtual addresses in the access~register mode, and as home virtual addresses in the homespace mode. Some instructions have storageoperand addresses or storage accesses associated with the instruction which do not follow the rules for logical addresses. In all such cases, the instruction defmition contains a defmition of the type of address. Instruction Address Addresses used to fetch instructions from storage are called instruction addresses. Instruction addresses are treated as real addresses in the real mode, as primary virtual addresses in the primaryspace mode, secondary-space mode, or accessregister mode, and as home virtual addresses in the home-space mode. The instruction address in the current psw and the target address of EXECUTE are instruction addresses. Effective Address In some situations, it is convenient to use the term "effective address." An effective address is the address which results from address arithmetic, before address translation, if any, is performed. Address arithmetic is the addition of the base and displacement or of the base, index, and displacement. Address Size and Wraparound Two sizes of addresses are provided: 24-bit and 31-bit. A 24-bit address can accommodate a maximum of 16,777,216 (16M) bytes; with a 3l-bit address, 2,147,483,648 (2G) bytes of storage can be addressed. The bits of the address are numbered 8-31 and 1-31, respectively, corresponding to the numbering of base-address and index bits in a general register: 24-bit Address o 8 II 31-Bit Address o 1 31 31 A 24-bit virtual address is expanded to 31 bits by appending seven zeros on the left before it is translated by means of the "DAT process, and a 24-bit real address is similarly expanded to 31 bits before it is transformed by prefixing. A 24-bit absolute address is expanded to 31 bits before main storage is accessed. Thus, the 24-bit address always designates the frrst 16M-byte block of the 2G-byte storage addressable by a 3l-bit address. Unless specifically stated to the contrary, the following defmition applies in this publication: whenever the machine generates and provides to the program an address, a 31-bit value imbedded in a 32-bit field is made available (placed in storage or loaded into a register). For "24-bit addresses, bits 0-7 are set to zeros, and the address appears in bit positions 8-31; for 31-bit addresses, bit 0 is set to zero, and the address appears in bit positions 1-31. The size of effective addresses is controlled by bit 32 of the PSW, the addressing-mode bit. When the bit is zero, the CPU is in the 24-bit addressing mode, and 24-bit operand and instruction effective addresses are specified. When the bit is one, the CPU is in the 31-bit addressing mode, and 31-bit operand and instruction effective addresses are specified (see the section "Address Generation" in Chapter 5, "Program Execution"). The size of the real addresses yielded by the AS N-translation, pc-number-translation, ASN-authorization, and tracing processes, and the real (or absolute) addresses yielded by the DAT process, is always 31 bits. The size of the data address in a ccw is under control of the format-control bit in the operationrequest block designated by a START SUBCHANNEL instruction. The CCws with 24-bit and 31-bit addresses are called format-O and format-l ccws, respectively. Format-O and format-l CCWs are described in Chapter 15, "Basic I/O Functions." Address Wraparound The CPU performs address generation when it forms an operand or instruction address or when it generates the address of a table entry from the appropriate table origin and index. It also performs address generation when it increments an address to access successive bytes of a field. Similarly, the channel subsystem performs address generation when it increments an address (1) to fetch a CCW, (2) to fetch an IDAW, (3) to transfer data, or (4) to compute the address of an 110 measurement block. When, during the generation of the address, an address is obtained that exceeds the value allowed for the address size (224 - 1 or 231 - 1), one of the following two actions is taken: 1. The carry out of the high-order bit position of the address is ignored. This handling of an address of excessive size is called wraparound. 2. An interruption condition is recognized. The effect of wraparound is to make an address space appear circular; that is, address 0 appears to follow the maximum allowable address. Address arithmetic and wraparound occur before transformation, if any, of the address by DAT or prefixing. Chapter 3. Storage 3-5 Addresses generated by the CPU always wrap, except for addresses generated for OAT-table entries. For DAT-table entries, it is unpredictable whether the address wraps or whether an addressing exception is recognized. Wraparound also occurs when the linkage-stack-entry address in control register 15 is decremented below 0 by PROGRAM RETURN. Address Generation for For channel-program execution, when the generated address exceeds the value for the address size (or, for the read-backward command is decremented below 0), an 1/0 program-check condition is recognized. Figure 3-2 identifies what limit values apply to the generation of different addresses and how addresses are handled when they exceed the allowed value. Handling When Address Address Would Type Wrap Instructions and operands when AM is zero L,I,R,V W24 Successive bytes of instructions and operands when AM is zero I,L,Vl W24 Instructions and operands when AM is one L,I,R,V W31 Successive bytes of instructions and operands when AM is one I,L,Vl W31 OAT-table entries when used for implicit translation A or R2 X31 OAT-table entries when used for LRA A or R2 X31 ASN-first-table, ASN-second-table, authorization-table, linkage-table, entry-table, and access-list entries, and dispatchable-unit and primary-space access-list designations R W31 Linkage-stack entry v W31 I/O measurement block A P31 Successive CCWs A P24 Success i ve IDAWs A P24 Successive bytes of I/O data (without IDAWs) A P24 Successive bytes of I/O data (with IDAWs) A P31 For a channel program with format-0 CCWs: Figure 3-6 3-2 (Part 1 of 2). Address Wraparound ESA/370 Principles of Operation Address Generation for Handling When Address Address Would Type Wrap For a channel program with format-l CCWs: Successive CCWs A P31 Successive IDAWs A P31 Successive bytes of I/O data (without IDAWs) A P31 Successive bytes of I/O data (with IDAWs) A P31 Explanation: 1 2 A AM I L P24 P31 R V W24 W31 X31 Real addresses do not apply in this case since the instructions which designate operands by means of real addresses cannot designate operands that cross boundaries 224 and 231. It is unpredictable whether the address is absolute or real. Absolute address. Addressing-mode bit in the PSW. Instruction address. Logical address. An I/O program-check condition is recognized when the address exceeds 224 - 1 or is decremented below zero. An I/O program-check condition is recognized when the address exceeds 231 - 1 or is decremented below zero. Real address. Virtual address. Wrap to location 0 after location 224 - 1 and vice versa. Wrap to location 0 after location 231 - 1 and vice versa. When the address exceeds 231 - 1, it is unpredictable whether the address wraps to location 0 after location 231 - 1 or whether an addressing exception is recognized. Figure 3-2 (Part 2 of 2). Address Wraparound Storage Key A storage key is associated with each 4K-byte block of storage that is available in the configuration. The storage key has the following format: o 4 6 The bit positions in the storage key are allocated as follows: If a reference is subject to key-controlled protection, the four access-control bits, bits 0-3, are matched with the four-bit access key when information is stored, or when information is fetched from a location that is protected against fetching. Fetch-Protection Bit (F): If a reference is subject to key-controlled protection, the fetch-protection bit, bit 4, controls whether key-controlled protection applies to fetch-type references: a zero indicates that only store-type references are monitored and that fetching with any access key is permitted; a one indicates that key -controlled protection applies to both fetching and storing. No distinction is made between the fetching of instructions and of operands. Access-Control Bits (ACC): Reference Bit (R): The reference bit, bit 5, normally is set to one each time a location in the corresponding storage block is referred to either for storing or for fetching of information. Chapter 3. Storage 3-7 The change bit, bit 6, is set to one each time information is stored at a location in the corresponding storage block. Change Bit (C): Storage keys are not part of addressable storage. The entire storage key is set by SET STORAGE KEY EXTENDED and inspected by INSERT STORAGE KEY EXTENDED. Additionally, the instruction RESET REFERENCE BIT EXTENDED provides a means of inspecting the reference and change bits and of setting the reference bit to zero. Bits 0-4 of the storage key are inspected by the INSERT VIRTUAL STORAGE KEY instruction. The contents of the storage key are unpredictable during and after the execution of the usability test of the TEST BLOCK instruction. Protection Three protection facilities are provided to protect the contents of main storage from destruction or misuse by programs that contain errors or are unauthorized: key-controlled protection, page protection, and low-address protection. The protection facilities are applied independently; access to main storage is only permitted when none of the facilities prohibit the access. Key-controlled protection affords protection against improper storing or against both improper storing and fetching, but not against improper fetching alone. Key-Controlled Protection When key-controlled protection applies to a storage access, a store is permitted only when the storage key matches the access key associated with the request for storage access; a fetch is permitted when the keys match or when the fetch-protection bit of the storage key is zero. The keys are said to match when the four accesscontrol bits of the storage key are equal to the access key, or when the access key is zero. The protection action is summarized in Figure 3-3. 3-8 ESA/370 Principles of Operation Conditions Is Access to 1---------.------1 Storage Permitted? Fetch-Protection Bit of Storage Key Key Relation Fetch Store e e 1 1 Match Mismatch Match Mismatch Yes Yes Yes No Yes No Yes No Explanation: Match The four access-control bits of the storage key are equal to the access key, or the access key is zero. Yes Access is permitted. No Access is not permitted. On fetching, the information is not made available to the program; on storing, the contents of the storage location are not changed. Figure 3-3. Summary of Protection Action When the access to storage is initiated by the CPU and key-controlled protection applies, the psw key is the access key, except that, for the second operand of MOVE WITH KEY and MOVE TO PRIMARY and the frrst operand of MOVE TO SECONDARY, the access key is specified in a general register. The psw key occupies bit positions 8-11 of the current psw. When the access to storage is for the purpose of channel-program execution, the subchannel key associated with that channel program is the access key. The subchannel key for a channel program is specified in the operation-request block (ORB). When, for purposes of channel-subsystem monitoring, an access to the measurement block is made, the measurement-block key is the access key. The measurement-block key is specified by the SET CHANNEL MONITOR instruction. When a CPU access is prohibited because of keycontrolled protection, the unit of operation is suppressed or the instruction is terminated, and a program interruption for a protection exception takes place. When a channel-program access is prohibited, the start function is ended, and the protection-check condition is indicated in the associated interruption-response block (IRB). When a measurement-block access is prohibited, the I/O measurement-block protection-check condition is indicated. When a store access is prohibited because of keycontrolled protection, the contents of the protected location remain unchanged. When a fetch access is prohibited, the protected information is not loaded into a register, moved to another storage location, or provided to an I/O device. For a prohibited instruction fetch, the instruction is suppressed, and an arbitrary instruction-length code is indicated. Key-controlled protection is independent of whether the CPU is in the problem or the supervisor state and, except as described below, does not depend on the type of CPU instruction or channelcommand word being executed. Except where otherwise specified, all accesses to storage locations that are explicitly designated by the program and that are used by the CPU to store or fetch information are subject to key-controlled protection. Accesses to the second operand of TEST not subject to key -controlled protection. BLOCK are All storage accesses by the channel subsystem to access the I/O measurement block, or by a channel program to fetch a ccw or IDAW or to access a data area designated during the execution of a ccw, are subject to key-controlled protection. However, if a CCW, an IDAW, or output data is prefetched, a protection check is not indicated until the ccw or IDAW is due to take control or until the data is due to be written. Key-controlled protection is not applied to accesses that are implicitly made for any of such sequences as: • An interruption • CPU logout • Fetching of table entries for dynamic-address translation, pc-number translation, ASN translation, or ASN authorization • Tracing • A store-status function • Storing in real locations 184-191 when TEST PENDING INTERRUPTION has an operand address of zero • Initial program loading Similarly, protection does not apply to accesses initiated via the operator facilities for altering or displaying information. However, when the program explicitly designates these locations, they are subject to protection. Fetch-Protection-Override Control Bit 6 of control register 0 is the fetch-protectionoverride control. When the bit is one, fetch protection is ignored for locations at effective addresses 0-2047. However, fetch protection is not ignored if the effective address is subject to dynamic address translation and the private-space control, bit 23, is one in the segment-table designation used in the translation. The function of the private-space control is available if the private-space facility is installed. Fetch-protection override applies to instruction fetch and to the fetch accesses of instructions whose operand addresses are logical, virtual, or real. It does not apply to fetch accesses made for the purpose of channel-program execution or for the purpose of channel-subsystem monitoring. When this bit is set to zero, fetch protection of locations at effective addresses 0-2047 is determined by the state of the fetch-protection bit of the storage key associated with those locations. Fetch-protection override has no effect on accesses which are not subject to key-controlled protection. Page Protection The page-protection facility controls access to virtual storage by using the page-protection bit in each page-table entry. It provides protection against improper storing. The page-protection bit, bit 22 of the page-table entry, controls whether storing is allowed into the corresponding 4K-byte page. When the bit is zero, both fetching and storing are permitted; when the bit is one, only fetching is permitted. When an attempt is made to store into a protected page, a program interruption for protection takes place. The contents of the protected location remain unchanged. Page protection applies to all store-type references that use a virtual address. Chapter 3. Storage 3-9 Low-Address Protection The low-address-protection facility provides protection against the destruction of main-storage information used by the CPU during interruption processing. This is accomplished by prohibiting instructions from storing with effective addresses in the range 0 through 511. The range criterion is applied before address transformation, if any, of the address by dynamic address translation or prefixing. However, the range criterion is not applied, with the result that low-address protection does not apply, if the effective address is subject to dynamic address translation and the private-space control, bit 23, is one in the segment-table designation used in the translation. The function of the privatespace control is available if the private-space facility is installed. Low-address protection is under control of bit 3 of control register 0, the low-address-protectioncontrol bit. When the bit is zero, low-address protection is off; when the bit is one, low-address protection is on. Programming Notes: 1. Low-address protection and key-controlled protection apply to the same store accesses, except that: • Low-address protection does not apply to storing perfonned by the channel subsystem, whereas key-controlled protection does. • Key-controlled protection does not apply to tracing, the second operand of TEST BLOCK, or instructions that operate specifically on the linkage stack, whereas lowaddress protection does. 2. Because fetch-protection override and lowaddress protection do not apply to an address space for which the private-space control is one in the segment-table designation, locations 0-2047 in the· address space are usable the same as the other locations in the space. Reference Recording If an access is prohibited because of low-address protection, the contents of the protected location remain unchanged, a program interruption for a protection exception takes place, and the unit of operation is suppressed or the instruction terminated. Reference recording provides information for use in selecting pages for replacement. Reference recording uses the reference bit, bit 5 of the storage key. The reference· bit is set to one each time a location in the corresponding storage block is referred to either for fetching or storing information, regardless of whether DAT is on or off. Any attempt by the program to store by using effective addresses in the range 0 through 511 is subject to low-address protection. Low-address protection is applied to the store accesses of instructions whose operand addresses are logical, virtual, or real. Low-address protection is also applied to the trace table. Reference recording is always active and takes p~ace for all storage accesses, including those made by any CPU, any operator facility, or the channel subsystem. It takes place for implicit accesses made by the machine, such as those which are part of interruptions and I/o-instruction execution. Low-address protection is not applied to accesses made by the CPU or the channel subsystem for such sequences as interruptions, CPU logout, the storing of the I/o-interruption code in reallocations 184-191 by TEST PENDING INTERRUPTION, and the initial-pro gram-loading and store-status functions, nor is it applied to data stores during I/O data transfer. However, explicit stores by a program at any of these locations are subject to low-address protection. 3-10 ESAj370 Principles of Operation Reference recording does not occur for operand accesses of the following instructions since they directly refer to a storage key without accessing a storage location: • INSERT STORAGE KEY EXTENDED • RESET REFERENCE BIT EXTENDED (reference bit is set to zero) • SET STORAGE KEY EXTENDED (reference bit is set to a specified value) The record provided by the reference bit is substantiallyaccurate. The reference bit may be set to one by fetching data or instructions that are neither designated nor used by the program, and, under certain conditions, a reference may be made without the reference bit being set to one. Under certain unusual circumstances, a reference bit may be set to zero by other than explicit program action. Change Recording Change recording provides information as to which pages have to be saved in auxiliary storage when they are replaced in main storage. Change recording uses the change bit, bit 6 of the storage key. The change bit is set to one each time a store access causes the contents in the corresponding storage block to be changed. A store access that does not change the contents of storage mayor may not set the change bit to one. The change bit is not set to one for an attempt to store if the access is prohibited. In particular: 1. For the cPU, a store access is prohibited when- ever an access exception exists for that access, or whenever an exception exists which is of higher priority than the priority of an access exception for that access. 2. For the channel subsystem, a store access is prohibited whenever a key-controlledprotection violation exists for that access. Change recording is always active and takes place for all store accesses to storage, including those made by any CPU, any operator facility, or the channel subsystem. It takes place for implicit references made by the machine, such as those which are part of interruptions. Change recording does not take place for the operands of the following instructions since they directly modify a storage key without modifying a storage location: • RESET REFERENCE BIT EXTENDED • SET STORAGE KEY EXTENDED (change bit is set to a specified value) Change bits which have been changed from zeros to ones are not necessarily restored to zeros on CPU retry (see the section "CPU Retry" in Chapter 11, "Machine-Check Handling"). See the section "Exceptions to Nu1li:fication and Suppression" in Chapter 5, "Program Execution," for a description of the handling of the change bit in certain unusual situations. Prefixing Prefixing provides the ability to assign the range of real addresses 0-4095 (the prefix area) to a different block in absolute storage for each CPU, thus permitting more than one CPU sharing main storage to operate concurrently with a minimum of interference, especially in the processing of interruptions. Prefixing causes real addresses in the range 0-4095 to correspond to the block of 4K-byte absolute addresses identified by the value in the prefix r~g ister for the CPU, and the block of real addresses identified by the value in the prefix register to corThe respond to absolute addresses 0-4095. remaining real addresses are the same as the corresponding absolute addresses. This transformation allows each CPU to access all of main storage, including the frrst 4K bytes and the locations designated by the prefix registers of other CPUs. The relationship between real and absolute addresses is graphically depicted in Figure 3-4 on page 3-12. The prefix is a 19-bit quantity contained in bit positions 1-19 of the prefix register. The register has the following format: Prefix o 1 1/11/11/II/II I 20 31 The contents of the register can be set and inspected by the privileged instructions SET PREFIX and STORE PREFIX, respectively. On setting, bits corresponding to bit positions 0 and 20-31 of the prefix register are ignored. On storing, zeros are provided for these bit positions. When the contents of the prefix register are changed, the change is effective for the next sequential instruction. When prefixing is applied, the real address is transformed into an absolute address by using one of the following rules, depending on bits 1-19 of the real address: 1. Bits 1-19 of the address, if all zeros, are replaced with bits 1-19 of the prefix. 2. Bits 1-19 of the address, if equal to bits 1-19 of the prefix, are replaced with zeros. 3. Bits 1-19 of the address, if not all zeros and not equal to bits 1-19 of the prefix, remain unchanged. Chapter 3. Storage 3-11 The distinction between real and absolute addresses is made even when the prefix register contains all zeros, in which case a real address and its corresponding absolute address are identical. In all cases, bits 20-31 of the address remain unchanged. Only the address presented to storage is translated by prefixing. The contents of the source of the address remain unchanged. Prefixing I --l I I I r- - - I - - - - 1 NOChange---L-- - I I I I I I I I ~---+-No Change ___~---_+_--- I I ~ I ~="' IL __________ ~I I :.--Add~ess Address 4096 I ...-Address 4096 Iop3 opl = op3 opl < op3 opl > op3 9 1 2 9 2 1 OGR3bl X, nop3 X, nopl OGR3bl X, topl X, top3 - - - - OGR3 OGR3 OGRI OGRI - - Explanation: - The contents of the register remain unchanged. OGRI The original contents of GRI OGR3 The original contents of GR3 OGR3bl The original contents of GR3 with bit e set to one X Bits 9-15 of GR2 contain 2 more than the index of the first unequal halfword. nopl Bits 16-31 of GR2 contain the one's complement of the first unequal halfword in operand 1. nop3 Bits 16-31 of GR2 contain the one's complement of the first unequal halfword in operand 3. topl Bits 16-31 of GR2 contain the first unequal halfword in operand 1. top3 Bits 16-31 of GR2 contain the first unequal halfword in operand 3. Figure 7-2. Operation of COMPARE AND FORM CODEWORD Chapter 7. General Instructions 7-17 2 x bits 17-3e of 2nd-operand address Bit 31 of 2nd-operand address ~ index limit ~ operand-control bit No Bit 31 of GRl, GR2, and GR3 all zerosf------... Specification exception Yes Bits 16-31 of GR2 > Yes index limit 1 - - - - - - - - - - , No Unit-ofoperation boundary GRI + bits 16-31 of GR2 1st-operand address GR3 ~ GR2 ~ 1 ~ bit e of GR2 GR3 ~ bits 16-31 of GR2 3rd-operand address + e ~ Cond code Fetch halfwords from current Ist- and 3rd-operand locations 'End operation GR2 + 2 ~ GR2 1st op high One's complement of 3rd-op HW ~ TEMPHW lst-op HW ~ TEMPHW One's complement of Ist-op HW ~ TEMPHW Exchange GRI and GR3 Exchange GRI and GR3 2 2 --. Cond code ~ Cond code l.. ~--------. l ~--------------.,.------------~ ~ Shift GR2 left 16 positions TEMPHW ~ bits 16-31 of GR2 l End operation Figure 7-3. Execution of COMPARE AND FORM CODEWORD 7-18 ESA/370 Principles of Operation A serialization function is performed before the operand is fetched and again after the operation is completed. Compare and Swap cs Rl,R3,D2(B2) 'BA' 13 [RS] I R. I R3 I B2 8 12 16 D2 213 31 Compare Double and Swap CDS Rl,R3,D2(B2) 'BB' 13 8 12 Resulting Condition Code: [RS] I R. I R3 I B2 16 The second operand of COMPARE AND SWAP must be designated on a word boundary. The R1 and R3 fields for COMPARE DOUBLE AND SWAP must each designate an even register, and the second operand for the CDS instruction must be designated on a doubleword boundary. Otherwise, a specification exception is recognized. o D2 213 31 First and second operands equal, second operand replaced by third operand First and second operands unequal, frrst operand replaced by second operand 2 3 The frrst and second operands are compared. If they are equal, the third operand is stored at the second-operand location. If they are unequal, the second operand is loaded into the frrst-operand location. The result of the comparison is indicated in the condition code. For COMPARE AND SWAP, the frrst and third operands are 32 bits in length, with each operand occupying a general register. The second operand is a word in storage. For COMPARE DOUBLE AND SWAP, the frrst and third operands are 64 bits in length, with each operand occupying an even-odd pair of general registers. The second operand is a doubleword in storage. When an equal comparison occurs, the third operand is stored at the second-operand location. The fetch of the second operand for purposes of comparison and the store into the second-operand location appear to be a block-concurrent interlocked-update reference as observed by other CPUs. When the result of the comparison is unequal, the second-operand location remains unchanged. However, on some models, the value may be fetched and subsequently stored back unchanged at the second-operand location. This update appears to be a block-concurrent interlocked-update reference as observed by other CPus. Program Exceptions: • Access (fetch and store, operand 2) • Specification . Programming Notes: 1. Several examples of the use of the COMPARE AND SWAP and COMPARE DOUBLE AND SWAP instructions are given in Appendix A. 2. COMPARE AND SWAP can be used by CPU programs sharing common storage areas in either a multiprogramming or multiprocessing environment. Two examples are: a. By performing the following procedure, a CPU program can modify the contents of a storage location even though the possibility exists that the CPU program may be interrupted by another CPU program that will update the location or that another CPU program may simultaneously update the location. First, the entire word containing the byte or. bytes to be updated is loaded into a general register. Next, the updated value is computed and placed in another general register. Then COMPARE AND SWAP is executed with the R1 field designating the register that contains the original value and the R3 field designating the register that contains the updated value. If the update has been successful, condition code o is set. If the storage location no longer contains the original value, the update has not been successful, the general registe( designated by the Rl field of the COMPARE Chapter 7. General Instructions 7-19 together, the possibility of ,the list being incorrectly updated is reduced to a negligible level. That is, an incorrect update can occur only if the fIrst CPU program is delayed while changes. exactly equal in number to a multiple of 232 take place and only if the last change places the original message address in the control word. AND SWAP instruction contains the new current value of the storage location, and condition code I is set. When condition code 1 is set, the CPU program can repeat the procedure using the new current value. b. 3. COMPARE AND SWAP can be used for controlled sharing of a common storage area, including the capability of leaving a message (in a chained list of messages) when the common area is in use. To accomplish this, a word in .storage can be used as a control word, with a zero value in the word indicating that the common area is not in use and that no messages exist, a negative value indicating that the area is in use and that no messages exist, and a nonzero positive value indicating that the common area is in use and that the value is the address of the most recent message added to the list. Thus, any number of CPU programs desiring to seize the area can use COMPARE AND SWAP to update the control word to indicate that the area is in use or to add messages to the list. The single CPU program which has seized the area can also safely use COMPARE AND SWAP to remove messages from the list. COMPARE DOUBLE AND SWAP can be used in a manner similar to that described for COMPARE AND SWAP. In addition, it has another use. Consider a chained list, with a control word used to address the fIrst message in the list, as described in programming note 2b above. If multiple CPU programs are to be permitted to delete messages by using COMPARE AND SWAP (and not just the single CPU program which has seized the common area), there is a possibility the list will be incorrectly updated. This would occur if, for example, after one CPU program has fetched the address of the most recent message in order to remove the message, another CPU program removes the fIrst t:wo messages and then adds the fIrst message back. into the chain. Th~ fIrst CPU program, on continuing, cannot easily detect that the list is changed. By increasing the size of the control word to a double\yord containing both the fIrst message address and a word with a change number that is incremented for each modification of the list, and by using COMPARE DOUBLE AND SWAP' to update .both fields 7-20 ESA/370 Principles of Operation 4. COMPARE AND SWAP and COMPARE DOUBLE AND SWAP do not interlock against storage accesses by channel programs. Therefore, the instructions should not be used to update a location at which a channel program may store, since the channel-program data may be lost. s. For the case of a condition-code setting of 1, COMPARE AND SWAP and COMPARE DOUBLE AND SWAP mayor may not, depending on the model, cause any of the following to occur for the second-operand location: a PER storagealteration event may be recognized; a protection exception for storing may be recognized; and, provided no access exception exists, the change bit may be set to one. Compare Halfword '49' I R. I I X2 8 12 B2 16 02 2e 31 The fIrst operand is compared with the second operand, and the result is indicated in the condition code. The second operand is two bytes in length and is treated as a 16-bit signed binary integer. The fIrst operand is treated as a 32-bit signed binary integer. Resulting Condition Code: o 1 2 3 Operands equal First operand low First operand high Program Exceptions: • Access (fetch, operand 2) Programming Note: An example of the use of the instruction is given in . AppendixA. COMPARE HALFWORD Programming Notes: Compare Logical ClR R1,R2 115 1 0 [RR] 2. I I I R. R2 12 15 8 Cl I. Examples of the use of the COMPARE instruction are given in Appendix A. R1,02(X2,B2) 155 1 0 R. 8 X2 12 02 B2 16 COMPARE LOGICAL treats all bits of each operand alike as part of a field of unstructured logical data. For COMPARE LOGICAL (CLC) , the comparison may extend to field lengths. of 256 bytes. Compare Logical Characters under Mask [RX] I I I LOGICAL ClM 20 [RS] 31 IBOI CLI 01 (B 1) ,12 195 1 0 12 20 l 8 I B. 16 [SS] I&H&~ / / 20 32 36 47 The first operand is compared with the second operand, and the result is indicated in the condition code. The comparison proceeds left to right, byte by byte, and ends as soon as an inequality is found or the end of the fields is reached. For COMPARE LOGICAL (CL) and COMPARE LOGICAL (CLC) , access exceptions mayor may not be recognized for the portion of a storage operand to the right of the first unequal byte. Resulting Condition Code: o I 2 3 8 12 16 20 31 The frrst operand is compared with the second operand under control of a mask, and the result is indicated in the condition code. 31 01 (l,B1) ,02(B2) 105 1 0 o 01 B1 16 8 ClC [SI] Operands equal First operand low First operand high The contents of the M 3 field are used as a mask. These four bits, left to right, correspond one for one with the four bytes, left to right, of general register Rl. The byte positions corresponding to ones in the mask are considered as a contiguous field and are compared with the second operand. The second operand is a contiguous field in storage, starting at the second-operand address and equal in length to the number of ones in the mask. The bytes in t e general register corresponding to zeros in the mask do not participate in the operation. The .comparison proceeds left to right, byte by byte, and ends .,as soon as an inequality is found or the end of the fields is reached. When the mask, is not zero, exceptions associated with storage-operand access are recognized for no more than the number of bytes specified by the mask. Access exceptions mayor may not be recognized for the portion of a storage operand to the right of the ftrst unequal byte. When the mask is zero, access exceptions are recognized for one byte at the second-operand address. Resulting Condition Code: Program Exceptions: • Access (fetch, operand 2, operand I, CLI and CLC) CL and CLC; fetch, o I 2 3 Operands equal, or mask bits all zeros First operand low First operand high Chapter 7. General Instructions 7-21 even-numbered register; otherwise, a specification exception is recognized. Program Exceptions: • Access (fetch, operand 2) The location of the leftmost byte of the frrst operand and second operand is designated by the contents of general registers Rl and R2, respectively. The number of bytes in the frrst-operand and second-operand locations is specified by bits 8-31 of general registers Rl + 1 and R2 + 1, respectively. Bit positions 0-7 of general register R2 -I- 1 contain the padding byte. The contents of bit positions 0-7 of general register Rl + 1 are ignored. An example of the use of the Programming Note: COMPARE LOGICAL CHARACTERS UNDER MASK instruction is given in Appendix A. Compare Logical Long Rl,R2 CLCL [RR] I R. I R, I 'aF' o 8 The handling of the addresses in general registers Rl and R2 is dependent on the addressing mode. 12 15 In the 24-bit addressing mode, the contents of bit positions 8-31 of general registers Rl and R2 constitute the address, and the contents of bit positions 0-7 are ignored. In the 31-bit addressing mode, the contents of bit positions 1-31 of general registers R 1 and R2 constitute the address, and the contents of bit position 0 are ignored. The frrst operand is compared with the second operand, and the result is indicated in the condition code. The shorter operand is considered to be extended on the right with padding bytes. The Rl and R2 fields each designate an even-odd pair of general registers and must designate an The contents of. the registers just described are shown in Figure 7-4. 31-Bit Addressing Mode 24-Bit Addressing Mode I11111111I Rl 0 Rl + 1 31 8 I11111111I 31 8 0 + Pad 1 0 31 31 Second-Operand Address 0 1 Pad 31 First-Operand Length 8 0 Second-Operand Length 8 31 0 1 III R2 R2 First-Operand Address 1//////III First-Operand Length 8 0 III First-Operand Address 0 Figure 7-4. Register Contents for COMPARE LOGICAL LONG 7-22 ESA/370 PrlDclples of Operation 31 Second-Operand Length 8 31 The comparison proceeds left to right, byte by byte, and ends as soon as an inequality is found or the end of the longer operand is reached. If the operands are not of the same length, the shorter operand is considered to be extended on the right with the appropriate number of padding bytes. If both operands are of zero length, the operands are considered to be equal. The execution of the instruction is interruptible. When an interruption occurs, other than one that causes termination, the contents of general registers Rl + 1 and R2 + 1 are decremented by the number of bytes compared, and the contents of general registers Rl and R2 are incremented by the same number, so that the instruction, when reexecuted, resumes at the point of interruption. The leftmost bits which are not part of the address in general registers Rl and R2 are set to zeros; the contents of bit positions 0-7 of general registers Rl + 1 and R2 + 1 remain unchanged; and the condition code is unpredictable. If the operation is interrupted after the shorter operand has been exhausted, the length field pertaining to the shorter operand is zero, and its address is updated accordingly. If the operation ends because of an inequality, the address fields in general registers Rl and R2 at completion identify the frrst unequal byte in each operand. The lengths in bit positions 8-31 of general registers Rl + 1 and R2 + 1 are decremented by the number of bytes that were equal, unless the inequality occurred with the padding byte, in which case the length field for the shorter operand is set to zero. The addresses in general registers Rl and R2 are incremented by the amounts by which the corresponding length fields were reduced. If the two operands, including the padding byte, if necessary, are equal, both length fields are made zero at completion, and the addresses are incremented by the corresponding operand-length values. At the completion of the operation, the leftmost bits which are not part of the address in general registers Rl and R2 are set to zeros, including the case when one or both of the initial length values are zero. The contents of bit positions 0-7 of general registers Rl + 1 and R2 + 1 remain unchanged. Access exceptions for the portion of a storage operand to the right of the frrst unequal byte may or may not be recognized. For operands longer than 2K bytes, access exceptions are not recognized more than 2K bytes beyond the byte being processed. Access exceptions are not indicated for locations more than 2K bytes beyond the frrst unequal byte. When the length of an operand. is zero, no access exceptions are recognized for that operand. Access exceptions are not recognized for an operand if the R field associated with that operand is odd. Resulting Condition Code: o 1 2 3 Operands equal, or both zero length First operand low First operand high Program Exceptions: • Access (fetch, operands 1 and 2) • Specification Programming Notes: 1. An example of the use of the COMPARE LOGICAL LONG instruction is given in Appendix A. 2. When the Rl and R2 fields are the same, the operation proceeds in the same way as when two distinct pairs of registers having the same contents are specified, and, in the absence of dynamic modification of the operand area by another CPU or by a channel program, condition code 0 is set. However, it is unpredictable whether access exceptions are recognized for the operand since the operation can be completed without storage being accessed. 3. Special precautions should be taken when COMPARE LOGICAL LONG is made the target of EXECUTE. See the programming note concerning interruptible instructions under EXECUTE. 4. Other programming notes concerning interruptible instructions are included in the section "Interruptible Instructions" in Chapter 5, "Program Execution." 5. In the access-register mode, access register 0 designates the primary address space regardless of the contents of access register O. Chapter 7. General Instructions 7-23 Convert to Decimal Convert to Binary CVB Rl,02(X2,B2) '4F' 0 [RX] I R. I x. I B2 8 12 16 '4E' 02 20 o I R. I ~. I B. 8 12 16 D. 20 31 31 The second operand is changed from decimal to binary, and the result is placed at the fust-operand location. The fust operand is changed from binary to decimal, and the result is stored at the secondoperand location. The first operand is treated as a 32-bit signed binary integer. The second operand occupies eight bytes in storage and has the fonnat of packed decimal data, as described in Chapter 8, "Decimal Instructions." It is checked for valid sign and digit codes, and a data exception is recognized when an invalid code is detected. The result occupies eight bytes in storage and is in the fonnat for packed decimal data, as described in Chapter 8, "Decimal Instructions." The rightmost four bits of the result represent the sign. A positive sign is encoded as 1100; a negative sign is encoded as 1101. The result of the conversion is a 32-bit signed binary integer, which is placed in general register Rio The maximum positive number that can be converted and still be contained in a 32-bit register is 2,147,483,647; the maximum negative number (the negative number with the greatest absolute value) that can be converted is -2,147,483,648. For any decimal number outside this range, the operation is completed by placing the 32 rightmost bits of the binary result in the register, and a fixedpoint-divide exception is recognized. Condition Code: The code remains unchanged. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2) • Data • Fixed-point divide 3. The storage-operand references for CONVERT TO BINARY may be multiple-access references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution. ") ESA/370 Principles of Operation Programming Notes: 1. An example of the use of the CONVERT TO DECIMAL instruction is given in Appendix A. 2. The number to be converted is a 32-bit signed binary integer obtained from a general register. Since 15 decimal digits are available for the result, and. the decimal equivalent of 31 bits requires at most 10 decimal digits, an overflow cannot occur. TO 2. When the second operand is negative, the result is in two's-complement notation. 7-24 • Access (store, operand 2) 3. The storage-operand references for CONVERT TO DECIMAL may be multiple-access references. (See the section "Storage-Operand Consistency" m Chapter 5, "Program Execution. ") Programming Notes: 1. An example of the use of the CONVERT BINARY instruction is given in Appendix A. Program Exceptions: Copy Access [RRE] CPYA '8240' o 1//////1/1 R. 16 24 28 31 The contents of access register access register R 1 • R2 are placed in Condition Code: The code remains unchanged. Program Exceptions: Bits 16-23 of the instruction are ignored. • Access (fetch, operand 2 of 0 only) • Fixed-point divide • Specification Condition Code: The code remains unchanged. Program Exceptions: None. Exclusive OR Divide XR R1,R2 [RR] DR I R, I R2 I 1171 '10' o I R, I R2 I 8 0 8 o 15 R1,02(X2,B2) [RX] '57 1 '50' o 8 12 12 15 X o [RR] 12 16 20 [RX] I R, I X2 I B2 8 12 16 02 20 31 31 XI The doubleword frrst operand (the dividend) is divided by the second operand (the divisor), and the remainder and the quotient are placed at the first-operand location. The R 1 field designates an even-odd pair of general registers and must designate an even-numbered register; otherwise, a specification exception is recognized. [51] 12 '97 1 o The sign of the quotient is determined by the rules of algebra. The remainder has the same sign as the dividend, except that a zero quotient or a zero remainder is always positive. When the divisor is zero, or when the magnitudes of the dividend and divisor are such that the quotient cannot be expressed by a 32-bit signed binary integer, a fixed-point-divide exception is recognized. This includes the case of division of zero by zero. 16 8 01 20 31 XC [55] '07' The dividend is treated as a 64-bit signed binary integer. The divisor, the remainder, and the quotient are treated as 32-bit signed binary integers. The remainder is placed in general register R 1, and the quotient is placed in general register Rl + 1. B1 L I B, I &Hb~ / ~--~----~--~/ o 8 16 20 32 36 47 The EXCLUSIVE OR of the first and second operands is placed at the frrst-operand location. The connective EXCLUSIVE OR is applied to the operands bit by bit. A bit position in the result is set to one if the corresponding bit positions in the two operands are unlike; otherwise, the result bit is set to zero. For EXCLUSIVE OR (XC), each operand is processed left to right. When the operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after fetching the necessary operand bytes. Chapter 7. General Instructions 7-25 For EXCLUSIVE OR (XI), the first operand byte in length, and only one byte is stored. IS one Resulting Condition Code: o 1 2 Result zero Result not zero 3 Program Exceptions: • Access (fetch, operand 2, X and XC; fetch and store, operand 1, XI and xc) Programming Notes: 1. An example of the use of the EXCLUSIVE OR instruction is given in Appendix A. 2. EXCLUSIVE OR may be used to invert a bit, an operation particularly useful in testing and setting programmed binary bit switches. 3. A field EXCLUSlvE-oRed with itself becomes all zeros. 4. For EXCLUSIVE OR (XR), the sequence A EXCLUSIVE-OR B, B EXCLUSIVE-OR A, A EXCLUSIVE-OR B results in the exchange of the contents of A and B without the use of an additional general register. 5. Accesses to the frrst operand of EXCLUSIVE OR (XI) and EXCLUSIVE OR (XC) consist in fetching a frrst-operand byte from storage and subsequently storing the updated value. These fetch and store accesses to a particular byte do not necessarily occur one immediately after the other. Thus, EXCLUSIVE OR cannot be safely used to update a location in storage if the possibility exists that another CPU or a channel program may also be updating the location. An example of this effect is shown for OR (01) in the section "Multiprogramming and Multiprocessing Examples" in Appendix A. Execute , 44 ' o 7- 26 8 2 12 2 16 When the Rl field is not zero, bits 8-15 of the instruction designated by the second-operand address are 0 Red with bits 24-31 of general register R1. The 0 Ring does not change either the· contents of general register R 1 or the instruction in storage, and it is effective only for the interpretation of the instruction to be executed. When the R1 field is zero, no oRing takes place. The target instruction may be two, four, or six bytes in length. The execution and exception handling of the target instruction are exactly as if the target instruction were obtained in normal sequential operation, except for the instruction address and the instruction-length code. The instruction address of the current psw is increased by the length of EXECUTE. This updated address and the instruction-length code of EXECUTE are used, for example, as part of the link information when the target instruction is BRANCH AND LINK. When the target instruction is a successful branching instruction, the instruction address of the current psw is replaced by the branch address specified by the target instruction. When the target instruction is in tum EXECUTE, an execute exception is recognized. The effective address of EXECUTE must be even; otherwise, a specification exception is recognized. When the target instruction is two or three halfwords in length but can be executed without fetching its second or third halfword, it is unpredictable whether access exceptions are recognized for the unused halfwords. Access exceptions are not recognized for the second-operand address when the address is odd. The second-operand address of EXECUTE is an instruction address rather than a logical address; thus, the target instruction is fetched from the primary address space when in the primary-space, secondary-space, or access-register mode. IR Ix IB 1 The single instruction at the second-operand address is modified by the contents of general register R1, and the resulting instruction, called the target instruction, is executed. 02 Condition Code: 20 ESA/370 Principles of Operation 31 target instruction. The code may be set by the Bits 16-23 of the instruction are ignored. Program Exceptions: • Access (fetch, target instruction) • Execute • Specification Condition Code: The code remains unchanged. Program Exceptions: None. Programming Notes: 1. An example of the use of the tion is given in Appendix A. EXECUTE instruc- Insert Character 2. The oRing of eight bits from the general register with the designated instruction permits the indirect specification of the length, index, mask, immediate-data, register, or extended-op-code field. o 3. The fetching of the target instruction is considered to be an instruction fetch for purposes of program-event recording and for purposes of reporting access exceptions. The byte at the second-operand location is inserted into bit positions 24-31 of general register Rl. The remaining bits in the register remain unchanged. 4. An access or specification exception may be caused by EXECUTE or by the target instruction. 5. When an interruptible instruction is made the target of EXECUTE, the program normally should not designate any register updated by the interruptible instruction as the R 1, X 2, or B 2 register for EXECUTE. Otherwise, on resumption of execution after an interruption, or if the instruction is refetched without an interruption, the updated values of these registers will be used in the execution of EXECUTE. Similarly, the program should normally not let the destination field in storage of an interruptible instruction include the location of EXECUTE, since the new contents of the location may be interpreted when resuming execution. Extract Access EAR [RRE] 'B24F' o 16 24 28 31 The contents of access register R 2 are placed in general register R 1. '43' I I I X2 R. 8 12 B2 16 02 20 31 Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2) Insert Characters under Mask 'BF' o I R. I M, I 8 12 16 B2 02 20 31 Bytes from contiguous locations beginning at the second-operand address are inserted into general register Rl under control of a mask. The contents of the M 3 field are used as a mask. These four bits, left to right, correspond one for one with the four bytes, left to right, of general register R 1. The byte positions corresponding to ones in the mask are filled, left to right, with bytes from successive storage locations beginning at the second-operand address. When the mask is not zero, the length of the second operand is equal to the number of ones in the mask. The bytes in the general register corresponding to zeros in the mask remain unchanged. Chapter 7. General Instructions 7-27 The'resulting .condition code is based on the mask and on the value of the bits inserted. When the mask is zero or when all inserted bits are zeros, the condition code is set to O. When the inserted bits are not all zeros, the code is set according to the leftmost bit of the storage operand: if this bit is one, the code is set to 1; if this bit is zero, the code is set to 2. The condition code and program mask from the current psw are inserted into bit positions 2-3 and 4-7, respectively, of general register R 1. Bits 0 and 1 of the register are set to zeros; bits 8-31 are left unchanged. Bits 16-23 and 28-31 of the instruction are ignored. Condition Code: The code remains unchanged. When the mask is not zero, exceptions associated with storage-operand access are recognized only for the number of bytes specified by the mask. When the mask is zero, access exceptions are recognized for one byte at the second-operand address. 1 2 Load LR Resulting Condition Code: o Program Exceptions: None. All inserted bits zeros, or mask bits all zeros Leftmost inserted bit one Leftmost inserted bit zero, and not all inserted bits zeros [RR] '18' o I R. I R2 I 8 12 15 3 Program Exceptions: • Access (fetch, operand 2) '58' Programming Notes: 1. Examples of the use of the INSERT CHARACTERS UNDER MASK instruction are given in AppendixA. 2. The condition code for INSERT CHARACTERS UNDER MASK is defmed such that, when the mask is 1111, the instruction causes the same condition code to be set as for LOAD AND TEST. Thus, the instruction may be used as a storage-to-register load-and-test operation. 3. INSERT CHARACTERS UNDER MASK with a mask of 1111 or 0001 performs a function similar to that of a LOAD (L) or INSERT CHARACTER (IC) instruction, respectively, with the exception of the condition-code setting. However, the performance of INSERT CHARACTERS UNDER MASK may be slower. o 182221 o 7-28 24 28 31 ESA/370 Principles of Operation 12 B2 16 02 20 31 Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2 of L only) Programming Note: An example of the use of the LOAD instruction is given in Appendix A. Load Access Multiple LAM o I11111111I R. I1111I 16 8 [RS] , 9A ' [RRE] X2 The second operand is placed unchanged at the frrst-operand location. Insert Program Mask IPM I R. I I I R. I R3 I 8 12 B2 16 20 31 The set of access registers starting with access register R 1 and ending with access register R3 is loaded from the locations designated by the secondoperand address. The storage area from which the contents of the access registers are obtained starts at the location designated by the second-operand address and continues through as many storage words as the number of access registers specified. The access registers are loaded in ascending order of their register numbers, starting with access register Rl and continuing up to and including access register R3, with access register 0 following access register 15. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. (with B2 set to zero) or B2 (with X2 set to zero). The instruction updates 24 bits in the 24-bit addressing mode and updates 31 bits in the 31-bit addressing mode. Load Address Extended [RX] LAE '51' o Rl 8 I I X2 12 16 B2 31 20 Condition Code: The code remains unchanged. The address specified by the X 2, B 2, and D 2 fields is placed in general register R 1. Access register R 1 is loaded with a value that depends on the current value of the address-space-contro1 bits, bits 16 and 17 of the psw. If the address-space-control bits are 01 binary, the value placed in the access register also depends on whether the B 2 field is zero or nonzero. Program Exceptions: • Access (fetch, operand 2) • Specification Load Address o 8 12 16 20 31 The address specified by the X 2, B 2, and D 2 fields is placed in general register Rl. The address computation follows the rules for address arithmetic. The address computation follows the rules for address arithmetic. In the 24-bit addressing mode, the address is placed in bit positions 8-31 of general register Rl, and bits 0-7 are set to zeros. In the 31-bit addressing mode, the address is placed in bit positions 1-31 of general register Rl, and bit 0 is set to zero. The value placed in access register in the following table: R1 is as shown In the 24-bit addressing mode, the address is placed in bit positions 8-31, and bits 0-7 are set to zeros. In the 31-bit addressing mode, the address is placed in bit positions 1-31, and bit 0 is set to zero. PSW Bits 16 and 17 00 00000000 hex (zeros in bit positions 0-31) No storage references for operands take place, and the address is not inspected for access exceptions. 10 00000001 hex (zeros in bit positions 0-30 and one in bit position 31) Condition Code: The code remains unchanged. 01 If B 2 field is zero: 00000000 hex (zeros in bit positions 0-31) Program Exceptions: None. If B 2 field is nonzero: Contents of access register B 2 Programming Notes: 1. An example of the use of the LOAD instruction is given in Appendix A. Value Placed in Access Register R 1 ADDRESS 2. LOAD ADDRESS may be used to increment the rightmost bits of a general register, other than register 0, by the contents of the D2 field of the instruction. The register to be incremented should be designated by R 1 and by either x 2 11 00000002 hex (zeros in bit positions 0-29 and 31, and one in bit position 30) However, when psw bits 16 and 17 are 01 binary and the B2 field is nonzero, bit positions 0-6 of access register B 2 must contain all zeros; otherwise, Chapter 7. General Instructions 7-29 the results in general register Rl are unpredictable. R1 and access register No storage references for operands take place, and the address is not inspected for access exceptions. Program Exceptions: None. Programming Note: When the Rl and R2 fields designate the same register, the operation is equivalent to a test without data movement. Condition Code: The code remains unchanged. Load Complement Program Exceptions: None. LCR [RR] Programming Notes: I. When DAT is on, the different values of the address-space-control bits correspond to translation modes as follows: PSW Bits 16 and 17 Translation Mode Primary-space mode Secondary-space mode Access-register mode Home-space mode 00 10 01 11 2. In the access-register mode, the value 00000000 hex in an access register designates the primary address space, and the value 0000000 I hex designates the secondary address space. The value 00000002 hex designates the home address space if the control program assigns access-list entry 2 as designating the home address space and places a zero access-list-entry sequence number (ALESN) in access-list entry 2. Load and Test LTR [RR] '12' o I R. I R2 I 8 12 15 The second operand is placed unchanged at the frrst-operand location, and the sign and magnitude of the second operand, treated as a 32-bit signed binary integer, are indicated in the condition code. '13' o I R. I R2 I 8 12 15 The two IS complement of the second operand is placed at the frrst-operand location. The second operand and result are treated as 32-bit signed binary integers. When there is an overflow, the result is obtained by allowing any carry into the sign-bit position and ignoring any carry out of the sign-bit position, and condition code 3 is set. If the fixed-point-overflow mask is one, a program interruption for fixed-point overflow occurs. Resulting Condition Code: o I 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Fixed-point overflow Programming Note: The operation complements all numbers. Zero and the maximum negative number remain unchanged. An overflow condition occurs when the maximum negative number is complemented. Load Halfword [RX] Resulting Condition Code: o I 2 3 Result zero Result less than zero Result greater than zero 7-30 '48' o IRI I X21 B2 8 12 16 02 20 31 The second operand is considered to be extended to a 32-bit signed binary integer and is placed at the ESAj370 Principles of Operation first-operand location. The second operand is two bytes in length and is considered to be a 16-bit signed binary integer. The second operand is extended to 32 bits by setting each of the 16 leftmost bit positions equal to the sign bit of the storage operand. Load Negative Condition Code: The code remains unchanged. o LNR [RR] 8 12 15 Program Exceptions: • Access (fetch, operand 2) Programming Note: An example of the use of the LOAD HALFWORD instruction is given in Appendix The two's complement of the absolute value of the second operand is placed at the frrst-operand The second operand and result are location. treated as 32-bit signed binary integers. A. Resulting Condition Code: o Load Multiple 1 2 [RS] 3 I '98 ' I R I R3 I B, Program Exceptions: 1 o 8 12 16 Result zero Result less than zero 20 31 The set of general registers starting with general register R 1 and ending with general register R3 is loaded from storage beginning at the location designated by the second-operand address and continuing through as many locations as needed. The general registers are loaded in the ascending order of their register numbers, starting with general register R 1 and continuing up to and including general register R3, with general register 0 following general register 15. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2) Programming Note: All combinations of register numbers specified by R 1 and R3 are valid. When the register numbers are equal, only four bytes are transmitted. When the number specified by R3 is less than the number specified by Rl, the register numbers wrap around from 15 to o. None. Programming Note: The operation complements positive numbers; negative numbers remain unchanged. The number zero remains unchanged. Load Positive LPR Rl,R2 'le' o [RR] I Rli R, I 8 12 15 The absolute value of the second operand is placed at the fust-operand location. The second operand and the result are treated as 32-bit signed binary integers. When there is an overflow, the result is obtained by allowing any carry into the sign-bit position and ignoring any carry out of the sign-bit position, and condition code 3 is set. If the fixed-point-overflow mask is one, a program interruption for fixed-point overflow occurs. Resulting Condition Code: o Result zero; no overflow I 2 3 Result greater than zero; no overflow Overflow Chapter 7. General Instructions 7-31 Program Exceptions: Program Exceptions: • Fixed-point overflow Programming Note: The operation complements negative numbers; positive numbers and zero remain unchanged. An overflow condition occurs when the maximum negative number is complemented; the number remains unchanged. • Monitor event • Specification Programming Notes: 1. Monitor Call [51] MC IAFI o 8 16 20 31 A program interruption is caused if the appropriate monitor-mask bit in control register 8 is one. The monitor-mask bits are in bit positions 16-31 of control register 8, which correspond to monitor classes 0-15, respectively. Bit positions 12-15 in the 12 field contain a binary number specifying one of 16 monitoring classes. When the monitor-mask bit corresponding to the class specified by the 12 field is one, a monitorevent program interruption occurs. The contents of the 12 field are stored at location 149, with zeros stored at location 148. Bit 9 of the programinterruption code is set to one. The frrst-operand address is not used to address data; instead, the address specified by the Bland D 1 fields forms the monitor code, which is placed in the word at location 156. Address computation follows the rules of address arithmetic; in the 24-bit addressing mode, bits 0-7 are set to zeros; in the 31-bit addressing mode, bit 0 is set to zero. MONITOR CALL provides the capability for passing control to a monitoring program when selected points are reached in the monitored program. This is accomplished by implanting MONITOR CALL instructions at the desired points in the monitored program. This function may be useful in performing various measurement functions; specifically, tracing information can be generated indicating which programs were executed, counting information can be generated indicating how often particular programs were used, and timing information can be generated indicating how long a particular program required for execution. 2. The monitor masks provide a means of disallowing all monitor-event program interruptions or allowing monitor-event program interruptions for all or selected classes. 3. The monitor code provides a means of associating descriptive information, in addition to the class number, with each MONITOR CALL. Without the use of a base register, up to 4,096 distinct monitor codes can be associated with a monitoring interruption. With the base register designated by a nonzero value in the B1 field, each monitoring interruption can be identified by a 24-bit code in the 24-bit addressing mode or a 3l-bit code in the 31-bit addressing mode. Move [51] 1921 12 When the monitor-mask bit corresponding to the class specified by bits 12-15 of the instruction is zero, no interruption occurs, and the instruction is executed as a no-operation. MVC Bit positions 8-11 of the instruction must contain zeros; otherwise, a specification exception is recognized. ~ID_21~__L_I~B_l~I~~~J o o 8 16 20 31 [55] 8 16 20 32 36 47 Condition Code: The code remains unchanged. The second operand is placed at the frrst-operand location. 7-32 ESAj370 Principles of Operation For MOVE (MVC), each operand is processed left to right. When the operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after fetching the necessary operand byte. When the operands overlap by more than one byte, the contents of the overlapped portion of the result field are unpredictable. For MOVE (MVI), the frrst operand is one byte in length, and only one byte is stored. Program Exceptions: Condition Code: The code remains unchanged. Program Exceptions: Condition Code: The code remains unchanged. • Access (fetch, operand 2; store, operand 1) • Operation (if the move-inverse facility is not installed) Programming Notes: • Access (fetch, operand 2 of operand I, MVI and MVC) MVC; store, Programming Notes: 1. Examples of the use of the MOVE instruction are given in Appendix A. 1. An example of the use of the MOVE INVERSE instruction is given in Appendix A. 2. The contents of each byte moved remain unchanged. 3. 2. It is possible to propagate one byte through an entire field by having the frrst operand start one byte to the right of the second operand. Move Inverse [SS] ~H~~ 1E81 _ -----L-_L---LI_B_1 L....-- o MOVE INVERSE is the only ss-format instruction for which the second-operand address designates the rightmost, instead of the leftmost, byte of the second operand. 4. The storage-operand references for MOVE INVERSE may be multiple-access references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution. ") Move Long ..1.-1 8 16 20 32 36 47 The second operand is placed at the frrst-operand location with the left-to-right sequence of the bytes inverted. The frrst-operand address designates the leftmost byte of the frrst operand. The second-operand address designates the rightmost byte of the second operand. Both operands have the same length. The result is obtained as if the second operand were processed from right to left and the frrst operand from left to right. The second operand may wrap around from -location 0 to location 224 - 1 in the 24-bit addressing mode, or, in the 31-bit addressing mode, to location 231 - 1. The frrst -operand may, in the 24-bit addressing mode, wrap around from location 224 - 1 to location 0, or, in the 31-bit addressing mode, from location 231 - 1 to location O. MVCL , 0E ' o Rl,R2 1 R1 8 [RR] 1 R2 1 12 15 The second operand is placed at the frrst-operand location, provided overlapping of operand locations would not affect the fmal contents of the frrstoperand location. The remaining rightmost byte positions, if any, of the frrst-operand location are filled with padding bytes. The R1 and R2 fields each designate an even-odd pair of general registers and must designate an even-numbered register; otherwise, a specification exception is recognized. The location of the leftmost byte of the frrst operand and second operand is designated by the contents of general registers R1 and R2, respectively. The number of bytes in the frrst-operand and second-operand locations is specified by bits 8-31 Chapter 7. General Instructions 7-33 of general registers Rl + 1 and R2 + 1, respectively. Bit positions 0-7 of register R2 + 1 contain the padding byte. The contents of bit positions 0-7 of register Rl + 1 are ignored. address, and the contents of bit positions 0-7 are ignored. In the 31-bit addressing mode, the contents of bit positions 1-31 of registers Rl and R2 constitute the address, and the contents of bit position 0 are ignored. The handling of the addresses in general registers Rl and R2 is dependent on the addressing mode. In the 24-bit addressing mode, the contents of bit positions 8-31 of registers Rl and R2 constitute the The contents of the registers just described are shown in Figure 7-5. 24-Bit Addressing Mode Rl 31-Bit Addressing Mode First-Operand Address e R. + 1 31 8 I11111111I First-Operand e 8 Length R, + 1 I e 8 Pad I Second-Operand 8 Length First-Operand Address 31 1 31 1""""1 e 31 Itle I R2 e Itl e I 31 Figure 7-5. Register Contents for MOVE LONG 7-34 ESAj370 Principles of Operation 8 31 Second-Operand Address 31 1 Pad e First-Operand Length Second-Operand Length 8 31 The movement starts at the left end of both fields and proceeds to the right. The operation is ended when the number of bytes specified by bit positions 8-31 of general register Rl + 1 have been moved into the frrst-operand location. If the second operand is shorter than the frrst operand, the remaining rightmost bytes of the frrst-operand location are filled with the padding byte. As part of the execution of the instruction, the values of the two length fields are compared for the setting of the condition code, and a check is made for destructive overlap of the operands. Operands are said to overlap destructively when the frrstoperand location is used as a source after data has been moved into it, assuming the inspection for overlap is performed by the use of logical operand addresses. When the operands overlap destructively, no movement takes place, and condition code 3 is set. Operands do not overlap destructively, and movement is performed, if the leftmost byte of the frrst operand does not coincide with any of the secondoperand bytes participating in the operation other than the leftmost byte of the second operand. When an operand wraps around from location 224 - 1 (or 231 - 1) to location 0, operand bytes in locations up to and including 224 - 1 (or 231 - 1) are considered to be to the left of bytes in locations from 0 up. In the 24-bit addressing mode, wraparound is from location 224 - I to location 0; in the 31-bit addressing mode, wraparound is from location 231 - 1 to location o. In the access-register mode, the contents of access register Rl and access register R2 are compared. If the Rl or R2 field is zero, 32 zeros are used rather than the contents of access register o. If all 32 bits of the compared values are equal, then the destructive overlap test is made. If all 32 bits of the compared values are not equal, destructive overlap is declared not to exist. If, for this case, the operands actually overlap in real storage, it is unpredictable whether the result reflects the overlap condition. When the length specified by bit positions 8-31 of general register Rl + 1 is zero, no movement takes place, and condition code 0 or I is set to indicate the relative values of the lengths. The execution of the instruction is interruptible. When an interruption occurs other than one that causes termination, the contents of general registers Rl + 1 and R2 + 1 are decremented by the number of bytes moved, and the contents of general registers Rl and R2 are incremented by the same number, so that the instruction, when reexecuted, resumes at the point of interruption. The leftmost bits which are not part of the address in general registers Rl and R2 are set to zeros; the contents of bit positions 0-7 of general registers Rl + 1 and R2 + 1 remain unchanged; and the condition code is unpredictable. If the operation is interrupted during padding, the length field in general register R2 + 1 is 0, the address in general register R2 is incremented by the original contents of general register R2 + 1, and general registers R 1 and Rl + 1 reflect the extent of the padding operation. When the frrst-operand location includes the location of the instruction or of EXECUTE, the instruction may be refetched from storage and reinterpreted even in the absence of an interruption during execution. The exact point in the execution at which such a refetch occurs is unpredictable. As observed by other CPus and by channel programs, that portion of the frrst operand which is filled with the padding byte is not necessarily stored into in a left-to-right direction and may appear to be stored into more than once. At the completion of the operation, the length in general· register Rl + 1 is decremented by the number of bytes stored at the frrst-operand location, and the address in general register R 1 is incremented by the same amount. The length in general register R2 + 1 is decremented by the number of bytes moved out of the second-operand location, and the address in general register R2 is incremented by the same amount. The leftmost bits which are not part of the address in general registers Rl and R2 are set to zeros, including the case when one or both of the original length values are zeros or when condition code 3 is set. The contents of bit positions 0-7 of general registers Rl + 1 and R2 -+ 1 remain unchanged. When condition code 3 is set, no exceptions associated with operand access are recognized. When the length of an operand is zero, no access exceptions for that operand are recognized. Similarly, when the second operand is longer than the frrst operand, access exceptions are not recognized for the part of the second-operand field that is in excess of the frrstoperand field. For operands longer than 2K bytes, access exceptions are not recognized for locations more than 2K bytes beyond the current location Chapter 7. General Instructions 7-35 being processed. Access exceptions are not recognized for an operand if the R field associated with that operand is odd. Also, when the Rl field is odd, PER storage-alteration events are not recognized, and no change bits are set. Resulting Condition Code: o I 2 3 Operand lengths equal; no destructive overlap First-operand length low; no destructive overlap First-operand length high; no destructive overlap No movement performed because of destructive overlap Program Exceptions: • Access (fetch, operand 2; store, operand I) • Specification Programming Notes: 1. An example of the use of the MOVE instruction is given in Appendix A. 2. LONG may be used for clearing storage by setting the padding byte to zero and the second-operand length to zero. On most models, this is the fastest instruction for clearing storage areas in excess of 256 bytes. However, the stores associated with this clearing may be multiple-access stores and should not be used to clear an area if the possibility exists that another CPU or a channel program will attempt to access and use the area as soon as it appears to be zero. For more details, see the section "Storage-Operand Consistency" in Chapter 5, "Program Execution. " MOVE LONG 3. The program should avoid specification of a length for either operand which would result in an addressing exception. Addressing (and also protection) exceptions may result in termination of the entire operation, not just the current .unit of operation. The termination may be such that the contents of all result fields are unpredictable; in the case of MOVE LONG, this includes the condition code and the two even-odd general-register pairs, as well as the frrst-operand location in main storage. The following are situations that have actually occurred on one or more models: a. When a protection exception occurs on a 4K-byte block of a fIrst operand which is 7-36 ESA/370 Principles of Operation several blocks in length, stores to the protected block are suppressed. However, the move continues into the subsequent blocks of the frrst operand, which are not protected. Similarly, an addressing exception on a block does not necessarily suppress processing of subsequent blocks which are available. b. Some models may update the general registers only when an external, 1/0, repressible machine-check, or restart interruption occurs, or when a program interruption occurs for which it is required to nullify or suppress a unit of operation. Thus, if, after a move into several blocks of the fIrst operand, an addressing or protection exception occurs, the general registers may remain unchanged. 4. When the frrst-operand length is zero, the operation consists in setting the condition code and setting the leftmost bits of general registers R 1 and R2 to zero. 5. When the contents of the Rl and R2 fields are the same, the operation proceeds the same way as when two distinct pairs of registers having the same contents are designated. Condition code 0 is set. 6. The following is a detailed description of those cases in which movement takes place, that is, where destructive overlap does not exist. In the access-register mode, the contents of the access registers used are called the effective space designations. When the effective space designations are not equal, destructive overlap is declared not to exist and movement occurs. When the effective space designations are the same or when not in the access-register mode, then the following cases apply. Depending on whether the second operand wraps around from location 224 - I to location 0, or, in the 31-bit addressing mode, from location 231 - I to location 0, movement takes place in the following cases: a. When the second operand does not wrap around, movement is performed if the leftmost byte of the frrst operand coincides with or is to the left of the leftmost. byte of the second operand, or if the leftmost byte of the frrst operand is to the right of the rightmost second-operand byte participating in the operation. b. When the second operand wraps· around, movement is performed if the leftmost byte of the fust operand coincides with or is to the left of the leftmost byte of the second operand, and if the leftmost byte of the fust operand is to the right of the rightmost second-operand byte participating in the operation. The rightmost second-operand byte is determined by using the smaller of the fust-operand and second-operand lengths. When the second-operand length is one or zero, destructive overlap cannot exist. Each operand is processed left to right. When the operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after fetching the necessary operand bytes. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) Programming Notes: 1. An example of the use of the MOVE NUMERICS instruction is given in Appendix A. 7. Special precautions should be taken if MOVE LONG is made the target of EXECUTE. See the programming note concerning interruptible instructions under EXECUTE. 2. 8. Since the execution of MOVE LONG is interruptible, the instruction cannot be used for situations where the program must rely on uninterrupted execution of the instruction. Similarly, the program should normally not let the first. operand of MOVE LONG include the location of the instruction or of EXECUTE because the new contents of the location may be interpreted for a resumption after .an interruption, or the instruction may be refetched without an interruption. MOVE NUMERICS moves the numeric portion of a decimal-data field that is in the zoned format. The zoned-decimal format is described in Chapter 8, "Decimal Instructions." The operands are not checked for valid sign and digit codes. 3. Accesses to the fust operand of' MOVE consist in fetching the rightmost four bits of each byte in the frrst operand and subsequently storing the updated value of the byte. These fetch and store accesses to a particular byte do not necessarily occur one immediately after the other. Thus, this instruction cannot be safely used to update a location in storage if the possibility exists that another CPU or a channel program may also be updating the location. An example of this effect is shown for OR (01) in the section "Multiprogramming and Multiprocessing Examples" in Appendix A. NUMERICS 9. Further programming notes concerning interruptible instructions are included in the section "Interruptible Instructions" in Chapter 5, "Program Execution." 10. In the access-register mode, access register 0 designates the primary address space regardless of the contents of access register O. Move with Offset Move Numerics MVO MVN ~'D_11-",--_L-",--IB_1-,--I~H~~ 9 [SS] [SS] 8 16 29 32 36 ~'Fl_'. L.-.-IL- -&I_L2--,-I_B1--,--I~H~~ ' 9 8 12 16 29 32 36 47 47 The rightmost four bits of each byte in the second· operand are placed in the rightmost bit positions of the corresponding bytes in the fITst operand. The leftmost four bits of each byte in the fust operand remain unchanged. . The second operand is placed to the left of and adjacent to the rightmost four bits of the frrst operand. The rightmost four bits of the fust operand are attached as the rightmost bits to the second operand, the second operand bits are offset by four Chapter 7. General Instructions 7-37 the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") bit positions, and the result is placed at the frrstoperand location. The result is obtained as if the operands were processed right to left. When necessary, the second operand is considered to be extended on the left with zeros. If the frrst operand is too short to contain all of the second operand, the remaining leftmost portion of the second operand is ignored. Access exceptions for the unused portion of the second operand mayor may not be indicated. When the operands overlap, the result is obtained as if the operands were processed one byte at a time, as if each result byte were stored immediately after fetching the necessary operand bytes, and as if the left digit of each second-operand byte were to remain available for the next result byte and need not be refetched. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) Programming Notes: 1. An example of the use of the MOVE WITH OFFSET instruction is given in Appendix A. 2. MOVE WITH OFFSET may be used to shift packed decimal data by an odd number of digit positions. The packed-decimal format is described in Chapter 8, "Decimal Instructions." The operands are not checked for valid sign and digit codes. In many cases, however, SHIFT AND ROUND DECIMAL may be more convenient to use. 3. Access to the rightmost byte of the first operand of MOVE WITH OFFSET consists in fetching the rightmost four bits and subsequently storing the updated value of this byte. These fetch and store accesses to the rightmost byte of the first operand do not necessarily occur one immediately after the other. Thus, this instruction cannot be safely used to update a location in storage if the possibility exists that another CPU or a channel program may also be updating the location. An example of this effect is shown for OR (01) in the section "Multiprogramming and Multiprocessing Examples" in Appendix A. 4. The storage-operand references for MOVE WITH OFFSET may be multiple-access references. (See 7-38 ESAj370 Principles of Operation Move Zones [55] MVZ L..--'0_3,--'-_L-----LI_B_l 1 o 8 16 20 ~H~~ .L- 32 36 47 The leftmost four bits of each byte in the second operand are placed in the leftmost four bit positions of the corresponding bytes in the frrst operand. The rightmost four bits of each byte in . the frrst operand remain unchanged. Each operand is processed left to right. When the operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after the necessary operand byte'is fetched. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) Programming Notes: 1. An example of the use of the MOVE ZONES instruction is given in Appendix A. 2. MOVE ZONES moves the zoned portion of a decimal field in the zoned format. The zoned format is described in Chapter 8, "Decimal Instructions. " The operands are not checked for valid sign and digit codes. 3. Accesses to the frrst operand of MOVE ZONES consist in fetching the leftmost four bits of each byte in the frrst operand and subsequently storing the updated value of the byte. These fetch and store accesses to a particular byte do not necessarily occur one immediately after the other. Thus, this instruction cannot be safely used to update a location in storage if the possibility exists that another CPU or a channel program may also be updating the location. An example of this effect is shown for the OR (01) instruction in the section "Multiprogramming and Multiprocessing Examples" in AppendixA. Multiply Multiply Halfword [RX] MH MR [RR] , IC ' o R, 8 '5C' o I I R2 '4C' I o 1 8 2 12 16 20 31 12 15 I R, I X2 I B2 8 I R I X I B2 12 16 The frrst operand (multiplicand) is multiplied ty the second operand (multiplier), and the product is placed at the frrst-operand location. The second operand is two bytes in length and is considered to be a 16-bit signed binary integer. D2 20 31 The second word of the frrst operand (multiplicand) is multiplied by the second operand (multiplier), and the doubleword product is placed at the frrst-operand location. The R1 field designates an even-odd pair of general registers and must designate an even-numbered register; otherwise, a specification exception is recognized. Both the multiplicand and multiplier are treated as 32-bit signed binary integers. The multiplicand is taken from general register Rl + 1. The contents of general register R 1 are ignored. The product is a 64-bit signed binary integer, which replaces the contents of the even-odd pair of general registers designated by R 1. An overflow cannot occur. The sign of the product is determined by the rules of algebra from the multiplier and multiplicand sign, except that a zero result is always positive. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2 of M only) • Specification ' Programming Notes: The multiplicand is treated as a 32-bit signed binary integer and is replaced by the rightmost 32 bits of the signed-binary-integer product. The bits to the left of the 32 rightmost bits of the product are not tested for significance; no overflow indication is given. The sign of the product is determined by the rules of algebra from the multiplier and multiplicand sign, except that a zero result is always positive. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2) Programming Notes: 1. An example of the use of the MULTIPLY HALFWORD instruction is given in Appendix A. 2. The significant part of the product usually occupies 46 bits or fewer. Only when two maximum negative numbers are multiplied are 47 significant product bits formed. Since the rightmost 32 bits of the product are stored unchanged, ignoring all bits to the left, the sign bit of the result may differ from the true sign of the product in the case of overflow. For a negative product, the 32 bits placed in register Rl are the rightmost part of the product in two scomplement notation. I 1. An example of the use of the MULTIPLY instruction is given in Appendix A. 2. The significant part of the product usually occupies 62 bits or fewer. Only when two maximum negative numbers are multiplied are 63 significant product bits formed. Chapter 7. General Instructions 7-39 2 OR 3 OR R1,R2 '16' 0 [RR] Program Exceptions: • Access (fetch, operand 2, 0 and oe; fetch and store, operand 1,01 and oe) I I I R, R2 12 15 8 Programming Notes: R1,02(X2,B2) 0 1. Examples of the use of the given in Appendix A. [RX] OR instruction are 2. OR may be used to set a bit to one. '56' 0 I I I R, 8 X2 B2 16 12 '96' 0 D1 B1 "12 16 8 31 20 [SI] 01 (B1) ,12 01 02 31 20 OC 3. Accesses to the fust operand of OR (01) and OR (oe) consist in fetching a fust-operand byte from storage and subsequently storing the updated value. These fetch and store accesses to a particular byte do not necessarily occur one immediately after the other. Thus, OR cannot be safely used to update a location in storage if the possibility exists that another CPU or a channel program may also be updating the location. An example of this effect is shown in the section "Multiprogramming and Multiprocessing Examples" in Appendix A. [SS] Pack 'D6' L I IbHb~ / B, ~--~----~---~/ o 8 16 20 32 PACK 36 47 'F2' I I IB' I ~H~~ L, L2 The OR of the first and second operands is placed at the first-operand location. o The connective OR is applied to the operands bit by bit. A bit position in the result is set to one if the corresponding bit position in one or both operands contains a one; otherwise, the result bit is set to zero. The format of the second operand is changed from zoned to packed, and the result is placed at the fust-operand location. The zoned and packed formats are described in Chapter 8, "Decimal Instructions. " For OR (oe), each operand is processed left to right. When the operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after fetching the necessary operand bytes. The second operand is treated as though it had the zoned format. The numeric bits of each byte are treated as a digit. The zone bits are ignored, except the zone bits in the rightmost byte, which are treated as a sign. For OR (01), the fust operand is only one byte in length, and only one byte is stored. The sign and digits are moved unchanged to the fust operand and are not checked for valid codes. The sign is placed in the rightmost four bit positions of the rightmost byte of the result field, and the digits are placed adjacent to the sign and to each other in the remainder of the result· field. Resulting Condition Code: o I Result zero Result not zero 7-40 ESAj370 Principles of Operation 8 12 16 20 32 36 47 The result is obtained as if the operands were processed right to left. When necessary, the second operand is considered to be extended on the left with zeros. If the frrst operand is too short to contain all digits of the second operand, the remaining leftmost portion of the second operand is ignored. Access exceptions for the unused portion of the second operand mayor may not be indicated. When the operands overlap, the result is obtained as if each result byte were stored immediately after fetching the necessary operand bytes. Two secondoperand bytes are needed for each result byte, except for the rightmost byte of the result field, which requires only the rightmost second-operand byte. The contents of general register access register R 1. R2 are placed in Bits 16-23 of the instruction are ignored. Condition Code: The code remains unchanged. Program Exceptions: None. Set Program Mask [RR] SPM Rl '84' e 8 I1111I 12 15 Condition Code: The code remains unchanged. The frrst operand is used to set the condition code and the program mask of the current psw. Program Exceptions: • Access (fetch, operand 2; store, operand 1) Programming Notes: 1. An example of the use of the is given in Appendix A. 2. PACK instruction PACK may be used to interchange the two hexadecimal digits in one byte by specifying a zero in the L 1 and L2 fields and the same address for both operands. 3. To remove the zone bits of all bytes of a field, including the rightmost byte, both operands must be extended on the right with a dummy byte, which subsequently is ignored in the result field. 4. The storage-operand references for PACK may be multiple-access references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") Set Access [RRE] SAR 'B24E' e 16 24 28 31 Bits 12-15 of the instruction are ignored. Bits 2 and 3 of general register R 1 replace the condition code, and bits 4-7 replace the program mask. Bits 0, 1, and 8-31 of general register Rl are ignored. The code is set as specified by bits 2 and 3 of general register R 1. Condition Code: Program Exceptions: None. Programming Notes: 1. Bits 2-7 of the general register may have been loaded from the psw by execution of BRANCH AN 0 LI N K in the 24-bit addressing mode or by execution of INSERT PROGRAM MASK in either the 24-bit or 31-bit addressing mode. 2. pennits setting of the condition code and the mask bits in either the problem state or the supervisor state. SET PROGRAM MASK 3. The program should take into consideration that the setting of the program mask can have a significant effect on subsequent execution of the program. Not only do the four mask bits control whether the corresponding interruptions occur, but the exponent-underflow and significance masks also determine the result which is obtained. Chapt.er 7. General Instructions 7-4 t Programming Notes: Shift Left Double 1. An example of the use of the SHIFf LEFf DOUBLE instruction is given in Appendix A. [RS] 'SF' o I Rl 8 I1111I B2 12 16 02 20 31 The 63-bit numeric part of the signed frrst operand is shifted left the number of bits specified by the second-operand address, and the result is placed at the frrst-operand location. Bits 12-15 of the instruction are ignored. The R 1 field designates an even -odd pair of general registers and must designate an even-numbered register; otherwise, a specification exception is recognized. The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. The frrst operand is treated as a 64-bit signed binary integer. The sign position of the evennumbered register remains unchanged. The leftmost bit position of the odd-numbered register contains a numeric bit, which participates in the shift in the same manner as the other numeric bits. Zeros are supplied to the vacated bit positions on the right. 2. The eight shift instructions provide the following three pairs of alternatives: left or right, single or double, and signed or logical. The signed shifts differ from the logical shifts in that, in the signed shifts, overflow is recognized, the condition code is set, and the leftmost bit participates as a sign. 3. A zero shift amount in the two signed doubleshift operations provides a double-length sign and magnitude test. 4. The base register participating in the generation of the second-operand address permits indirect specification of the shift amount. A zero in the B 2 field indicates the absence of indirect shift specification. Shift Left Double Logical 'SO' o I Rl I1111I B2 8 12 16 D2 20 31 The 64-bit frrst operand is shifted left the number of bits specified by the second-operand address, and the result is placed at the first-operand location. Bits 12-15 of the instruction are ignored. If one or more bits unlike the sign bit are shifted out of bit position 1 of the even-numbered register, an overflow occurs, and condition code 3 is set. If the fixed-point-overflow mask bit is one, a program interruption for fixed-point overflow occurs. Resulting Condition Code: o 1 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Fixed-point overflow • Specification The R 1 field designates an even-odd pair of general registers and must designate an even-numbered register; otherwise, a specification exception is recognized. The second-operand address is not used to address data; its rightm~st six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. All 64 bits of the frrst operand participate· in the shift. Bits shifted out orbit position 0 of the evennumbered register are not inspected and are lost. Zeros are supplied to the vacated bit positions on the right. Condition Code: The code remains unchanged. 7-42 ESAj370 Principles of Operation 3. Shift amounts from 31 to 63 cause the entire numeric part to be shifted out of the register, leaving a result of the maximum negative number or zero, depending on whether or not the initial contents were negative. Program Exceptions: • Specification Shift Left Single SLA Rl ,02 (B2) '8B' I Rl 8 0 111111 12 Shift Left Single Logical [RS] 02 82 16 20 31 The 31-bit numeric part of the signed frrst operand is shifted left the number of bits specified by the second-operand address, and the result is placed at the first-operand location. Bits 12-15 of the instruction are ignored. The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. The frrst operand is treated as a 32-bit signed binary integer. The sign of the frrst operand remains unchanged. All 31 numeric bits of the operand participate in the left shift. Zeros are supplied to the vacated bit positions on the right. If one or more bits unlike the sign bit are shifted out of bit position 1, an overflow occurs, and condition code 3 is set. If the fixed-point-overflow mask bit is one, a program interruption for fixedpoint overflow occurs. 8 12 16 20 31 The 32-bit first operand is shifted left the number of bits specified by the second-operand address, and the result is placed at the frrst-operand location. Bits 12-15 of the instruction are ignored. The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. All 32 bits of the first operand participate in the shift. Bits shifted out of bit position 0 are not inspected and are lost. Zeros are supplied to the vacated bit positions on the right. Condition Code: The code remains unchanged. Program Exceptions: None. Shift Right Double Resulting Condition Code: o 1 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Fixed-point overflow Programming Notes: 1. An example of the use of the SHIFf LEFf SINGLE instruction is given in Appendix A. 2. For numbers with a value greater than or equal to _230 and less than 2 30 , a left shift of one bit position is equivalent to multiplying the number by 2. 'BE' I Rl I1111I 8 12 16 B2 02 20 31 The 63-bit numeric part of the signed fust operand is shifted right the number of bits specified by the second-operand address, and the result is placed at the frrst-operand location. Bits 12-15 of the instruction are ignored. The R 1 field designates an even-odd pair of general registers and must designate an even-numbered reg- Chapter 7. General Instructions 7-43 ister; otherwise, a specification exception is recognized. bit positions to be shifted; The remainder of the address is ignored. The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. All 64 bits of the frrst operand participate in the shift. Bits shifted out of bit position 31 of the oddnumbered register are not inspected and are lost. Zeros are supplied to the vacated bit positions on the left. The frrst· operand is treated as a 64-bit signed binary integer. The sign position of the evennumbered register remains unchanged. The leftmost bit position of the odd-numbered register contains a numeric bit; which participates in the shift in the same manner as the other numeric bits. Bits shifted out of bit position 31 of the oddnumbered register are not inspected and are lost. Bits equal to the sign are supplied to the vacated bit positions on the left. Condition Code: The code remains unchanged. Program Exceptions: • Specification Shift Right Single SRA [RS] Resulting Condition Code: o 1 2 3 '8A' Result zero Result less than zero Result greater than zero 13 I RII //111 8 12 16 B, 213 31 The 31-bit numeric part of the signed first operand is shifted right the number of bits specified by the second-operand address, and the result is placed at the frrst-operand location. Program Exceptions: • Specification Shift Right Double Logical Bits 12-15 of the instruction are ignored. SRDL The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. Rl,02(B2) 8 12 [RS] 16 213 31 The 64-bit frrst operand is shifted right the number of bits specified by the second-operand address, and the result is placed at the frrst-operand location. Bits 12-15 of the instruction are ignored. The Rl field designates an even-odd pair of general registers and must designate an even-numbered register; otherwise, a specification exception is recognized. The frrst operand is treated as a 32-bit signed binary integer. . The sign of the frrst operand remains unchanged. All 31 numeric bits of the operand participate in the right shift. Bits shifted out of bit position 31 are not inspected and are lost. Bits equal to the sign are supplied to the vacated bit positions on the left. Resulting Condition Code: o 1 2 3 The second-operand address is not used to address data; its rightmost six bits indicate the number of 7-44 ESAj370 Principles of Operation Result zero Result less than zero Result greater than zero Program Exceptions: None. Store Programming Notes: 1. A right shift of one bit position is equivalent to division by 2 with rounding downward. When an even number is shifted right one position, the result is equivalent to dividing the number by 2. When an odd number is shifted right one position, the result is equivalent to dividing the ne~t lower number by 2. For example, + 5 shifted right by one bit position yields + 2, whereas -5 yields -3. 2. Shift amounts from 31 to 63 cause the entire numeric part to be shifted out of the register, leaving a result of -lor zero, depending on whether or not the initial contents were negative. o I Rl 8 IIIIII 12 16 B2 o I I I X2 R1 8 12 16 B2 D2 20 31 The frrst operand is placed unchanged at the second-operand location. Condition Code: The code remains unchanged. Program Exceptions: • Access (store, operand 2) Store Access Multiple Shift Right Single Logical 'BB' '59 ' D2 20 31 The 32-bit frrst operand is shifted right the number of bits specified by the second-operand address, and the result is placed at the frrst-operand location. Bits 12-15 of the instruction are ignored. The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored. All 32 bits of the first operand participate in the shift. Bits shifted out of bit position 31 are not inspected and are lost. Zeros are supplied to the vacated bit positions on the left. Condition Code: The code remains unchanged. Program Exceptions: None. o 8 12 16 20 31 The contents of the set of access registers starting with access register R 1 and ending with access register RJ are stored at the locations designated by the second-operand address. The storage area where the contents of the access registers are placed starts at the location designated by the second-operand address and continues through as many storage. words as the number of access registers specified. The contents of the access registers are stored in ascending order of their register numbers, starting with access register R 1 and continuing up to and including access reg~ster RJ, with access register 0 following access reg1ster 15. The contents of the access registers remain unchanged. The second operand must be designated on a word /boundary; otherwise, a specification exception is recognized. Condition Code: The. code remains unchanged. Program Exceptions: • Access (store, operand 2) -Specification Chapter 7. General Instructions 7-45 be an interlocked-update reference as observed by other CPUs. Store Character Condition Code: The code remains unchanged. [RX] STC Program Exceptions: , 42 ' 13 1 R. 1 x21 B2 8 12 16 • Access (store, operand 2) 213 31 Programming Notes: 1. An example of the use of the STORE CHARAC- Bits 24-31 of general register Rl are placed unchanged at the second-operand location. The second operand is one byte in length. TERS UNDER MASK instruction is given in AppendixA. 2. STORE CHARACTERS UNDER MASK with a mask of 0111 may be used to store a three-byte address, for example, in modifying the address in a ccw. Condition Code: The code remains unchanged. Program Exceptions: 3. STORE CHARACTERS UNDER MASK with a mask of 1111, 0011, or 0001 performs the same function as STORE, STORE HALFWORD, or STORE CHARACTER,' respectively. However, on most models, the. performance of STORE CHARACTERS UNDER MASK is slower. • Access (store, operand 2) Store Characters under Mask 'BE' 13 1 8 R. 1 M, I 12 16 B2 4. Using STORE CHARACTERS UNDER MASK with a zero mask should be avoided since this instruction,. depending on the model, may perform a fetch and store of the single byte designated by the second-operand address. This reference is not interlocked against accesses by channel programs. In addition, it may cause any of the following to occur for the byte designated by the second-operand address: a PER storage-alteration event may be recognized; access exceptions may be recognized; and, provided no access exceptions exist, the change bit may be set to one. 02 213 31 Bytes selected from general register Rl under control of a mask are placed at contiguous byte locations beginning at the second-operand address. The contents of the M3 field are used as a mask. These four bits, left to right, correspond one for one with the four bytes, left to right, of general register R1.' The bytes corresponding to ones in the mask are placed in the same order at successive and ~ontiguous storage locations beginning at the second-operand address. When the mask is not zero, the length of the second operand is equal to the number of ones in the mask. The contents of the general register remain unchanged. "When the mask is not zero, exceptions associated with storage-operand accesses are recognized only for the number of bytes specified by the mask. When the mask is zero, the. single byte designated by the second~operand address remains unchanged; however, on some models, the value may be fetched and subsequently stored back unchanged at the same storage location. This update appears to 7-46 ESAj370 Principles of Operation Store Clock [S] IB2e5 1 13 16 213 31 The current value of the TO D clock is stored at the eight-byte field designated by the second-operand address, provided the clock is in the set, stopped, or not-set state. Zeros are stored for the rightmost bit positions that are not provided by the clock. Zeros are stored at the operand location when the . clock is in the error state or in the not-operational state. The quality of the clock value stored by the instruction is indicated by the resultant conditioncode setting. A serialization function is performed before the value of the clock is fetched and again after the value is placed in storage. value stored when the condition code is 2 is not necessarily zero. Store Halfword [RX] , 49 ' o IR Ix IB 1 8 2 12 2 15 20 31 Resulting Condition Code: o Clock in set state I 2 3 Clock in not-set state Clock in error state Clock in stopped state or not-operational state Program Exceptions: • Access (store, operand 2) Bits 16-31 of general register Rl are placed unchanged at the second-operand location. The second operand is two bytes in length. Condition Code: The code remains unchanged. Program Exceptions: • Access (store, operand 2) Programming Notes: 1. Bit position 31 of the clock is incremented every 1.048576 seconds; hence, for timing applications involving human responses, the leftmost clock word may provide sufficient resolution. 2. Condition code 0 normally indicates that the clock has been set by the control program. Accordingly, the value may be used in elapsedtime measurements and as a valid time-of-day and calendar indication. Condition code I indicates that the clock value is the elapsed time since the power for the clock was turned on. In this case, the value may be used in elapsed-time measurements but is not a valid time-of-day indication. Condition codes 2 and 3 mean that the value provided by STORE CLOCK cannot be used for time measurement or indication. 3. Condition code 3 indicates that the clock is in either the stopped state or the not-operational state. These two states can normally be distinguished because an all-zero value is stored when the clock is in the not-operational state. 4. If a problem program written for ESA/370 is to be executed also on a system in the System/370 mode, then the program should take into account that, in the System/370 mode, the Store Multiple '90' o I I I Rl 8 R, 12 15 B2 02 20 31 The contents of the set of general registers starting with general register R1 and ending with general register R3 are placed in the storage area beginning at the location designated by the second-operand address and continuing through as many locations as needed. The general registers are stored in the ascending order of register numbers, starting with general register R1 and continuing up to and including general registerR3, with general register 0 following general register 15. Condition Code: The code remains unchanged. Program Exceptions: • Access (store, operand 2) Programming Note: An example of the use of the STORE MULTIPLE instruction is given in Appendix A. Chapter 7. General Instructions 7-47 Subtract Subtract Halfword [RR] SR 'lB' o I I I Rl 8 '5B' o R. Rl 8 '4B' o 12 15 I I I X2 12 16 [RX] SH B2 02 20 31 The second operand is subtracted from the frrst operand, and the difference is placed at the frrstoperand location. The operands and the difference are treated as 32-bit signed binary integers. When there is an overflow, the result is obtained by allowing any carry into the sign-bit position and ignoring any carry out of the sign-bit position, and condition code 3 is set. If the fixed-point-overflow mask is one, a program interruption for fixed-point overflow occurs. I I I RI 8 X2 12 B2 16 20 31 The second operand is subtracted from the frrst operand, and the difference is placed at the frrstoperand location. The second operand is two bytes in length and is treated as a 16-bit signed binary integer. The frrst operand and the difference are treated as 32-bit signed binary integers. When there is an overflow, the result is obtained by allowing any carry into the sign-bit position and ignoring any carry out of the sign-bit position, and condition code 3 is set. If the fixed-point-overflow mask is one, a program interruption for fixed-point overflow occurs. Resulting Condition Code: o I 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow Resulting Condition Code: o I 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Access (fetch, operand 2 of s only) • Fixed-point overflow Program Exceptions: • Access (fetch, operand 2) • Fixed-point overflow Subtract Logical Programming Notes: 1. When, in the RR fonnat, Rl and R2 designate the same register, subtracting is equivalent to clearing the register. [RR] SLR 'IF' o 2. Subtracting a maximum negative number from another maximum negative number gives a zero result and no overflow. 8 '5F' o I Rl I R2 I 12 15 I Rl I X2 I B2 8 12 16 02 20 31 The second operand is subtracted from the first operand, and the difference is placed at the frrst- 7-48 ESA/370 Principles of Operation operand location. The operands and the difference are treated as 32-bit unsigned binary integers. A serialization and checkpoint-synchronization function is perfonned. Resulting Condition Code: The code remains unchanged and is saved as part of the old psw. A new condition code is loaded as part of the supervisor-call interruption. o 1 2 3 Result not zero; no carry Result zero; carry Result not zero; carry Condition Code: Program Exceptions: None. Program Exceptions: • Access (fetch, operand 2 of SL only) Programming Notes: 1. Logical subtraction is perfonned by adding the one's complement of the second operand and a value of one to the frrst operand. The use of the one's complement and the value of one instead of the two's complement of the second operand results in a carry when the second operand is zero. 2. SUBTRACT LOGICAL differs from SUBTRACT only in the meaning of the condition code and in the absence of the interruption for overflow. 3. A zero difference is always accompanied by a carry out of bit position O. 4. The condition-code setting for SUBTRACT LOGICAL can also be interpreted as indicating the presence and absence of a borrow, as follows: I 2 3 Result not zero; borrow Result zero; no borrow Result not zero; no borrow Supervisor Call 5VC [RR] Test and Set T5 '93' 0 [5] D2 (B2) 1////////1 8 16 B2 D2 20 31 The leftmost bit (bit position 0) of the byte located at the second-operand address is used to set the condition code, and then the byte is set to all ones. Bits 8-15 of the instruction are ignored. The byte in storage is set to all ones as it is fetched for the testing of bit position O. This update appears to be an interlocked-update reference as observed by other CPUs. A serialization function is perfonned before the byte is fetched and again after the storing of all ones. Resulting Condition Code: o I 2 3 Leftmost bit zero Leftmost bit one Program Exceptions: '0A' • Access (fetch and store, operand 2) 8 15 Programming Notes: The instruction causes a supervisor-call interruption, with the I field of the instruction providing the rightmost byte of the interruption code. Bits 8-15 of the instruction, '- with eight zeros appended on the left, are placed in the supervisor., call interruption code that is stored in the course of the interruption. See "Supervisor-Call Interruption" in Chapter 6, "Interruptions." 1. TEST AND SET may be used for controlled sharing of a common storage area by programs operating on different cpus. This instruction is provided primarily for compatibility with programs written for System/360. The instructions COMPARE AND SWAP and COMPARE DOUBLE AND SWAP provide functions which are more suitable for sharing among programs on a Chapter 7. General Instructions 7-49 single cPU or for programs that may be interSee the description of these rupted. instructions and the associated programming notes for details. 2. TEST AND SET does not interlock against storage accesses by channel programs. Therefore, the instruction should not be used to update a location. into which a channel program may store, since the channel-program data may be lost. Test under Mask [SI] TM [SS] 'DC' L I B. I bHb~ / ~--~----~~I o 8 16 20 32 36 47 The bytes of the frrst operand are used as eight-bit arguments to reference a list designated by the second-operand address. Each function byte selected from the list replaces the corresponding argument in the frrst operand. The L field specifies the length of only the frrst operand. 1911 o Translate 8 16 20 31 A mask is used to select bits of the frrst operand, and the result is indicated in the condition code. The byte of immediate data, 12, is used as an eight-bit mask. The bits of the mask are made to correspond one for one with the bits of the byte in storage designated by the frrst-operand address. The bytes of the frrst operand are selected one by one for translation, proceeding left to right. Each argument byte is added to the initial secc.aJoperand address. The addition is performed following the rules fo~ address arithmetic, with the argument byte treated as an eight-bit unsigned binary integer and extended with zeros on the left. The sum is used as the address of the function byte, which then replaces the original argument byte. A mask bit of one indicates that the storage bit is to be tested. When the mask bit is zero, the storage bit is ignored. When all storage bits thus selected are zero, condition code 0 is set. Condition code 0 is also set when the mask is all zeros. When the selected bits are all ones, condition code 3 is set; otherwise, condition code lis set. The operation proceeds until the frrst-operand field is exhausted. The list is not altered unless an overlap occurs. Access exceptions associated with the storage operand are recognized for one byte even when the mask is all zeros. Access exceptions are recognized only for those bytes in the second operand which are actually required. Resulting Condition Code: Condition Code: The code remains unchanged. o 1 Selected bits all zeros; or mask bits all zeros Selected bits mixed zeros and ones 2 3 Selected bits all ones Program Exceptions: • Access (fetch, operand 1) Programming Note: An example of the use of the instruction is given in Appendix TEST UNDER MASK A. When the operands overlap, the result is obtained as if each result byte were stored immediately after fetching the corresponding function byte. Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) Programming Notes: 1. An example of the use of the instruction is given in Appendix A. TRANSLATE 2. TRANSLATE may be used to convert data from" one code to another code. 3. The instruction may also be used to rearrange 7-50 ESAj370 Principles of Operation data. This may be accomplished by placing a pattern in the destination area, by designating the pattern as the first operand of TRANSLATE, and by designating the data that is to be rearranged as the second operand. Each byte of the pattern contains an eight-bit number specifying the byte destined for this position. Thus, when the instruction is executed, the pattern selects the bytes of the second operand in the desired order. 4. Because each eight-bit argument byte is added to the initial second-operand address to obtain the address of a functiqh byte, the list may contain 256 bytes. In cases where it is known that not all eight-bit argument values will occur, it is possible to reduce the size of the . list. 5. Significant performance degradation is possible when, with OAT on, the second-operand address of TRANSLATE designates a location that is less than 256 bytes to the left of a 4K-byte boundary. This is because the machine may perform a trial execution of the instruction to determine if the second operand actually crosses the boundary. 6. The fetch and subsequent store accesses to a particular byte in the frrst-operand field do not necessarily occur one immediately after the other. Thus, this instruction cannot be safely used to update a location in storage if the possibility exists that another CPU or a channel program may also be updating the location. An example of this effect is shown for OR (01) in the section "Multiprogramming and Multiprocessing Examples" in Appendix A. 7. The storage-operand references of TRANSLATE may be multiple-access references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") TRT . 0.-1~H~~ '----'D_D,---'-_L-LI_B_l 8 16 20 The L field specifies the length of only the frrst operand. The bytes of the frrst operand are selected one by one for translation, proceeding from left to right. The frrst operand remains unchanged in storage. Calculation of the. address of the function byte is performed as in the TRANSLATE instruction. The function byte retrieved from the list is inspected for a value of zero. When the function byte is zero, the operation proceeds with the next byte of the frrst operand. When the frrst-operand field is exhausted before a nonzero function byte is encountered, the operation is completed by setting condition code O. The contents of general registers 1 and 2 remain unchanged. When the function byte is nonzero, the operation is completed by inserting the function byte in general register 2 and the related argument address in general register 1. This address points to the argument byte last translated. The function byte replaces bits 24-31 of general register 2. In the 24-bit addressing mode, the address replaces bits 8-31, and bits 0-7 of general register 1 remain unchanged. In the 31-bit addressing mode, the address replaces bits 1-31, and bit 0 of general register 1 is set to zero. In both modes, bits 0-23 of general register 2 remain unchanged. When the function byte is nonzero, either condition code I or 2 is set, depending on whether the argument byte is the rightmost byte of the frrst operand. Condition code 1 is set if one or more argument bytes remain to be translated. Condition code 2 is set if no more argument bytes remain. The contents of access register 1 always remain unchanged. Translate and Test o 2, and the related argument address in general register 1. 32 36 47 Access ex.ceptions are recognized only for those bytes in the second operand which are actually required. Acce~s exceptions are not recognized for those bytes in the frrst operand which are to the right of the frrst byte for which a nonzero function byte is obtained. Resulting Condition Code: The bytes of the frrst operand are used as eight-bit arguments to select function bytes from a list designated by the second-operand address. The frrst nonzero function byte is inserted in general register o 1 All function bytes zero Nonzero function byte; frrst-operand field not exhausted . Chapter 7. General Instructions 7-51 2 Nonzero function byte; frrst-operand field exhausted 3 Program Exceptions: • Access (fetch, operands 1 and 2) Programming Notes: 1. An example of the use of the TRANSLATE AND TEST instruction is given in Appendix A. 2. TRANSLATE AND TEST may be used to scan the frrst operand for characters with special meaning. The second operand, or list, is set up with all-zero function bytes for those characters to be skipped over and with nonzero function bytes for the characters to be detected. time and as if the frrst result byte were stored immediately after fetching the frrst operand byte. The entire rightmost second-operand byte is used in forming the frrst result byte. For the remainder of the field, information for two result bytes is obtained from a single second-operand byte, and execution proceeds as if the leftmost four bits of the byte were to remain available for the next result byte and need not be refetched. Thus, the result is as if two result bytes were to be stored immediately after fetching a single operand byte. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2; store, operand 1) Programming Notes: Unpack " The format of the second operand is changed from packed to zoned, and the result is placed at the frrst-operand location. The packed and zoned formats are described in Chapter 8, "Decimal Instructions. " The second operand is treated as though it had the packed format. Its digits and sign are placed unchanged in the frrst-operand location, using the zoned format. Zone bits with coding of 1111 are supplied for all bytes except the rightmost byte, the zone of which receives the sign of. the second operand. The sign and digits are not checked for valid codes. The result is obtained as if the operands were processed right to left. When necessary, the second operand is considered to be extended on the left with zeros. If the frrst-operand field is too short to contain all digits of the second operand, the remaining leftmost portion of the second operand is ignored. Access exceptions for the unused portion of the second operand mayor may not be indicated. When the operands overlap, the result is obtained as if the operands were processed one byte at a 7-52 ESAj370 Principles of Operation 1. An example of the use of the UNPACK instruction is given in Appendix A. 2. A field that is to be unpacked can be destroyed by improper overlapping. To save storage space for unpacking by overlapping the operands, the rightmost byte of the fust operand must be to the right of the rightmost byte of the second operand by the number of bytes in the second operand minus 2. If only one or two bytes are to be unpacked, the rightmost bytes of the two operands may coincide. 3. The storage-operand references of UNPACK may be multiple-access references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") Update Tree UPT [E] '0102' o 15 The doubleword nodes of a tree in storage are examined successively on a path toward the base of the tree, and the contents of general-register pair 0-1 are conditionally interchanged with the contents of the nodes so as to give a unique maximum logical value in general register O. General register 4 contains the base address of the tree, and general register 5 contains the index of a node whose parent node will be examined fIrst. The initial contents of general registers 4 and 5 must be a multiple of 8; otherwise, a specifIcation exception is recognized. Access exceptions, change-bit action, and PER storage alteration do not occur if a specification exception exists. Resulting Condition Code: In the access-register mode, access register 4 specifies the address space containing the tree. This instruction may be interrupted between units of operation. The condition code is unpredictable if the instruction is interrupted. A unit of operation begins by shifting the contents of general register 5 right logically one position and then setting bit 29 to zero. However, general register 5 remains unchanged if the execution of a unit of "operation is nullifIed or suppressed. If after shifting and setting bit 29 to zero, the contents of general register 5 are zero, the instruction is completed' and condition code 1 is set; otherwise, the unit of operation continues. Bit 0 of general register 0 is tested. If bit 0 of register 0 is one, the instruction is completed, and condition code 3 is set. If bit 0 of general register 0 is zero, the sum of the contents of general registers 4 and 5 is used as the intennediate value for nonnal operand address generation. The generated address is the address of a node in storage. The contents of general register 0 are logically compared with the contents of the fust word of the currently addressed node. If the register operand is low, the contents of general-register pair 0-1 are interchanged with those of the node, and a unit of operation is completed. If the register operand is high, no additional action is taken, and the unit of operation is completed. If the compare values are equal, general-register pair 2-3 is loaded from the currently addressed node, the instruction is completed, and condition code 0 is set. In those cases when the value in the fust word of the node is less than or equal to the value in the register, the contents of the node remain unchanged. However, in some models, these contents may be fetched and subsequently stored back. Access exceptions are recognized only for one doubleword node at a time. Access exceptions, change-bit action, and PER storage alteration do not occur for· subsequent nodes until the previous node has been successfully compared and updated. o Equal compare values at currently addressed node No equal compare values found on path, or no comparison made 2 3 General register 5 nonzero and general register o negative Program Exceptions: • Access (fetch and store, nodes of tree) • Specification Programming Notes: 1. For use in sorting, when equal compare values have been found, the contents of general registers 1 and 3 can be appropriate (depending on the contents of the tree) for the subsequent execution of COMPARE AND FORM CODEWORD. The contents of general register 2, shifted right 16 bit positions, can be similarly appropriate, and they can provide for minimal recomparison of partially equal keys. 2. The program should avoid placing a nonzero value in bit positions 0-6 of general register 5 when in the 24-bit addressing mode. If any bit in bit positions 0-6 is a one, the nodes of the tree will not be examined successively. 3. The storage-operand references for UPDATE TREE may be multiple-access references. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") 4. In those cases when the value in the fust word of the node is less than or equal to the value in the register, depending on the model, the contents of the node may be fetched and subsequently stored back. As a result, any of the following may occur for the storage location containing the node: a PER storage-alteration event may be recognized; a protection exception for storing may be recognized; and, provided no access exceptions exist, the change bit may be set to one. 5. Special precautions should be taken when UPDATE TREE is made the target of EXECUTE. See the programming note concerning interruptible instructions under EXECUTE. Chapter 7. General Instructions 7-53 7. Figure 7-6 is a summary of the operation of 6. Further programming notes concerning interruptible instructions are included in the section "Interruptible Instructions" in Chapter 5, "Program Execution." Bits 29-31 of GR4 and GRS all zeros UPDATE TREE. Specification Exception Yes Unit-ofoperati on 1--------_1 boundary GRS shifted ri ght one positi on B- TEMPWORD1 8i t 29 of TEMPWORD1 .---------, Yes 1 - - - - - - -.... 9 - No 1- GRS Cond Code Yes 8i t B of GRB one 1 - - - - - - - - - - - , No TEMPWORD1 3 GR4 + TEMPWORD1 - GRS Cond Code TEMPADDRESS End operation Fetch doub1eword from location in storage designated by TEMPADDRESS; 8i ts 9-31 - TEMPWORD2 8i ts 32-64 - TEMPWORD3 l GRB hi gh , . . . - - - - - - - - - - - - - , GR9 equal GR9 low Store contents of GRe and GR1 in doub1eword designated by TEMPADDRESS TEMPWORD2 - GR2 TEMPWORD3 - GR3 9- TEMPWORD2 - GRB TEMPWORD3 - GR1 Cond Code End operati on Figure 7-6. Execution of UPDATE TREE 7-54 ESA/370 Principles of Operation Chapter 8. Decimal Instructions Decimal-Number Formats Zoned Format Packed Format Decimal Codes Decimal Operations Decimal-Arithmetic Instructions Editing Instructions ........ Execution of Decimal Instructions Other Instructions for Decimal Operands Instructions .................. 8-1 8-1 8-1 8-2 8-2 8-2 8-3 8-3 8-3 8-3 Add Decimal ... Compare Decimal Divide Decimal Edit ....... Edit and Mark Multiply Decimal Shift and Round Decimal Subtract Decimal Zero and Add ......... 8-5 8-5 8-6 8-6 8-10 8-10 8-11 8-12 8-12 The decimal instructions of this chapter perform arithmetic and editing operations on decimal data. Additional operations on decimal data are provided by several of the instructions in Chapter 7, "General Instructions." Decimal operands always reside in storage, and all decimal instructions use Decimal operands the ss instruction format. occupy storage fields that can start on any byte boundary. Decimal digits in the zoned format may be part of a larger character set, which includes also alphabetic and special characters. The zoned format is, therefore, suitable for input, editing, and output of numeric data in human-readable form. There are no decimal-arithmetic instructions which operate directly on decimal numbers in the zoned format; such numbers must frrst be converted to the packed format. Decimal-Number Formats The editing instructions produce a result of up to 256 bytes; each byte may be a decimal digit in the zoned format, a message byte, or a fill byte. Decimal numbers may be represented in either the zoned or packed format. Both decimal-number formats are of variable length; the instructions used to operate on decimal data each specify the length of their operands and results. Each byte of either format consists of a pair of four-bit codes; the four-bit codes include decimal-digit codes, sign codes, and a zone code. Zoned Format I liN I liN I; I liN Il/sl N I In the zoned format, the rightmost four bits of a byte are called the numeric bits (N) and normally consist of a code representing a decimal digit. The leftmost four bits of a byte are called the zone bits (z), except for the rightmost byte of a decimal operand, where these bits may be treated either as a zone or as a sign (s). Packed Format I 0 I 0 I 0 I 0 I ; I 0 I 0 I 0 I s I In the packed format, each byte contains two decimal digits (0), except for the rightmost byte, which contains a sign to the right of a decimal digit. Decimal arithmetic is performed with operands in the packed format and generates results in the packed format. The packed-format operands and results of decimal-arithmetic instructions may be up to 16 bytes (31 digits and sign), except that the maximum length of a multiplier or divisor is eight bytes (15 digits and sign). In division, the sum of the lengths of the quotient and remainder may be from two to 16 bytes. The editing instructions can fetch as many as 256 decimal digits from one or more decimal numbers of variable length, each in the packed format. Chapter 8. Decimal Instructions 8-1 Decimal Codes The meaning of the decimal codes is summarized in Figure 8-1 The decimal digits 0-9 have the binary encoding Programming Note: Since 1111 is both the zone code and an alternate code for plus, unsigned (positive) decimal numbers may be represented in the zoned format with 1111 zone codes in all byte positions. The result of the PACK instruction converting such a number to the packed format may be used directly as an operand for decimal instructions. 0000-1001. The preferred sign codes are 1100 for plus and 1101 for minus. These are the sign codes generated for the results of the decimal-arithmetic instructions and the CONVERT TO DECIMAL instruction. Alternate sign codes are also recognized as valid in the sign position: 1010, 1110, and 1111 are alternate codes for plus, and 1011 is an alternate code for minus. Alternate sign codes are accepted for any decimal source operand, but are not generated in the completed result of a decimal-arithmetic instruction or CONVERT TO DECIMAL. This is true even when an operand remains otherwise unchanged, such as when adding zero to a number. An alternate sign code is, however, left unchanged by MOVE NUMERICS, MOVE WITH OFFSET, MOVE ZONES, PACK, and UNPACK. When an invalid sign or digit code is detected, a data exception is recognized. For the decimalarithmetic instructions and CONVERT TO BINARY, the action taken for a data exception depends on whether a sign code is invalid. When a sign code is invalid, the operation is suppressed regardless of whether any other condition causing a data exception exists. When an invalid digit code is detected but no sign code is invalid, the operation is terminated. For the editing instructions EDIT and EDIT AND an invalid sign code is not recognized. The operation is terminated for a data exception due to an invalid digit code. No validity checking is performed by MOVE NUMERICS, MOVE WITH OFFSET, MOVE ZONES, PACK, and UNPACK. MARK, The zone code 1111 is generated in the left four bit positions of each byte representing a zone and a decimal digit in zoned-fonnat results. Zonedformat results are produced by EDIT, EDIT AND MARK, and UNPACK. For EDIT and EDIT AND MARK, each result byte representing a zoned-fonnat decimal digit contains the zone code 1111 in the left four bit positions and the decimal-digit code in the right four bit positions. For UNPACK, zone bits with a coding of 1111 are supplied for all bytes except the rightmost byte, the zone of which receives the sign. 8·2 ESAj370 Principles of Operation Recognized As Code Digit Sign 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Pl us Minus Plus (preferred) Minus (preferred) Plus Plus (zone) Figure 2 3 4 5 6 7 8 9 Invalid Invalid Invalid Invalid Invalid Invalid 8-1. Summary of Digit and Sign Codes Decimal Operations The decimal instructions in this chapter consist of two classes, the decimal-arithmetic instructions and the editing instructions. Decimal-Arithmetic Instructions The decimal-arithmetic instructions perform addition, subtraction, multiplication, division, comparison, and shifting. Operands of the decimal-arithmetic instructions are in the packed format and are treated as signed decimal integers. A decimal integer is represented in true form as an absolute value with a separate plus or minus sign. It contains an odd number of decimal digits, from one to 31, and the sign; this corresponds to an operand length of one to 16 bytes. A decimal zero nonnally has a plus sign, but multiplication, division, and overflow may produce a zero value with a minus sign. Such a negative zero is.a valid operand and is treated as equal to a positive zero by COMPARE DECIMAL. The lengths of the two operands specified in the instruction need not be the same. If necessary, the shorter operand is considered to be extended with zeros on the left. Results, however, cannot exceed the frrst-operand length as specified in the instruction. When a carry or leftmost nonzero digits of the result are lost because the frrst-operand field is too short, the result is obtained by ignoring the overflow digits, condition code 3 is set, and, if the decimal-overflow mask bit is one, a program interruption for decimal overflow occurs. The operand lengths alone are not an indication of overflow; nonzero digits must have been lost during the operation. The operands of decimal-arithmetic instructions should not overlap at all or should have coincident rightmost bytes. In ZERO AND ADD, the operands may also overlap in such a manner that the rightmost byte of the frrst operand (which becomes the result) is to the right of the rightmost byte of the second operand. For these cases of proper overlap, the result is obtained as if operands were processed right to left. Because the codes for digits and signs are verified during the perfonnance of the arithmetic, improperly overlapping operands are recognized as data exceptions. Programming Note: A packed decimal number in storage may be designated as both the frrst and second operand of ADD DECIMAL, COMPARE DECIMAL, DIVIDE DECIMAL, MULTIPLY DECIMAL, SUBTRACT DECIMAL, or ZERO AND ADD. Thus, a decimal number may be added to itself, compared with itself, and so forth; SUBTRACT DECIMAL may be used to set a decimal field in storage to zero, and, for MULTIPLY DECIMAL, a decimal number may be squared in place. Overlapping operands for the editing instructions yield unpredictable results. Execution of Decimal Instructions During the execution of a decimal instruction, all bytes of the operands are not necessarily accessed concurrently, and the fetch and store accesses to a single location do not necessarily occur one immediately after the other. Furthermore, for decimal instructions, data in source fields may be accessed more than once, and intermediate values may be placed in the result field that may differ from the original operand and fmal result values. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") Thus, in a multiprocessing configuration, an instruction such as ADD DECIMAL cannot be safely used to update a shared storage location when the possibility exists that another CPU may also be updating that location. Other Instructions for Decimal Operands In addition to the decimal instructions in this chapter, MOVE NUMERICS and MOVE ZONES are provided for operating on data of lengths up to 256 bytes in the zoned format. Two instructions are provided for converting data between the zoned and packed formats: PACK transforms zoned data of lengths up to 16 bytes into packed data, and UNPACK performs the reverse transformation. MOVE WITH OFFSET can operate on packed data of lengths up to 16 bytes. Two instructions are provided for conversion between the packed-decimal and signed-binary-integer formats. CONVERT TO BINARY converts packed decimal to binary, and CONVERT TO DECIMAL converts binary to packed decimal; the length of the packed decimal operand of these instructions is eight bytes (15 digits and sign). These seven instructions are not considered to be decimal instructions and are described in Chapter 7, "General Instructions." The editing instructions in this chapter may also be used to change data from the packed to the zoned format. Editing Instructions The editing instructions are ED IT and EDIT AND MARK. For these instructions, only the frrst operand (the pattern) has an explicitly specified length. The second operand (the source) is considered to have as many digits as necessary for the completion of the operation. Instructions The decimal instructions and their mnemonics, formats, and operation codes are listed in Figure 8-2 on page 8-4. The figure also indicates when the condition code is set, the instruction fields that designate access registers, and the excep- Chapter 8. Decimal Instructions 8-3 tional conditions in operand designations, data, or results that cause a program interruption. operand designation for the assembler language are shown with each instruction. For ADD DECIMAL, for . example, AP is the mnemonic and Dl{Ll,Bl),D2{L2.B2) the operand designation. Note: In the detailed descriptions of the individual instructions, the mnemonic and the symbolic Name Mnemonic . ADD DECIMAL COMPARE DECIMAL DIVIDE DECIMAL EDIT EDIT AND MARK AP CP DP ED EDMK SS SS SS SS SS MULTIPLY DECIMAL SHIFT AND ROUND DECIMAL SUBTRACT DECIMAL ZERO AND ADD MP SRP SP ZAP SS SS C SS C SS C C C C C Op Code Characteristics A D DF A D DK A SP D D A A D G1 A SP D D DF A A D DF A D DF ST Bl Bl ST Bl ST Bl R ST Bl ST ST ST ST 0 OF OK G1 R SP SS ST Figure 8-4 Access exceptions for logical addresses. B1 field designates an access register in the access-register mode. B2 field designates an access register in the access-register mode. Condition code is set. Data exception. Decimal-overflow exception. Decimal-divide exception. Instruction execution includes the implied use of general register 1. PER general-register-alteration event. Specification exception. SS instruction format. PER storage-alteration event. . 8-2. Summary of Decimal Instructions ESAj370 Principles of Operation FA F9 FD DE OF Bl B2 FC Fe Bl Bl B2 FB Bl B2 Fa Explanation: A Bl B2 C B2 B2 B2 B2 B2 Compare Decimal Add Decimal [SS] AP ~H~;] L---'FA_'..1..-1L----I'I_L2--LI_Bl--1-1 o 8 12 16 20 32 36 47 The second operand is added to the frrst operand, and the resulting sum is placed at the frrst-operand location. The operands and result are in the packed format. Addition is algebraic, taking into account the signs and all digits of both operands. All sign and digit codes are checked for validity. If the frrst operand is too short to contain all leftmost nonzero digits of the sum, decimal overflow occurs. The operation is completed. The result is obtained by ignoring the overflow digits, and condition code 3 is set. If the decimal-overflow mask is one, a program interruption for decimal overflow occurs. CP [SS] ~'F9_'..1..-1 ~H~;] L--I,'I_L2---,-I_Bl--,--1 o 8 12 16 20 32 36 47 The first operand is compared with the second operand, and the result is indicated in the condition code. The operands are in the packed format. Comparison is algebraic and follows the procedure for decimal subtraction, except that both operands remain unchanged. When the difference is zero, the operands are equal. When a nonzero difference is positive or negative, the frrst operand is high or low, respectively. Overflow cannot occur because the difference is discarded. All sign and digit codes are checked for validity. Resulting Condition Code: The sign of the sum is determined by the rules of algebra. In the absence of overflow, the sign of a zero result is made positive. If overflow occurs, a zero result is given either a positive or negative sign, as determined by what the sign of the correct sum would have been. Resulting Condition Code: o 1 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) • Data • Decimal overflow o 1 2 3 Operands equal First operand low First operand high Program Exceptions: • Access (fetch, operands 1 and 2) • Data Programming Notes: 1. An example of the use of the COMPARE DECIMAL instruction is given in Appendix A. 2. The preferred and alternate sign codes for a particular sign are treated as equivalent for comparison purposes. 3. A negative zero and a positive zero compare equal. Programming Note: An example of the use of the instruction is given in Appendix A. ADD DECIMAL Chapter 8. Decimal Instructions 8-5 Program Exceptions: Divide Decimal • Access (fetch, operand 2; fetch and store, operand 1) • Data • Decimal divide • Specification DP ~H~~ ,----I FD_'--I-I_L1---,--I_L2--,--I_B1-,--I 8 8 12 16 28 32 36 47 Programming Notes: 1. An example of the use of the DIVIDE DECIMAL The fIrst operand (the dividend) is divided by the second operand (the divisor). The resulting quotient and remainder are placed at the fIrst-operand location. The operands and results are in the packed format. instruction is given in Appendix A. 2. The dividend cannot exceed 31 digits and sign. Since the remainder cannot be shorter than one digit and sign, the quotient cannot exceed 29 digits and sign. The quotient is placed leftmost in the fIrst-operand location. The number of bytes in the quotient field is equal to the difference between the dividend and divisor lengths (Ll - L2). The remainder is placed rightmost in the fIrst-operand location and has a length equal to the divisor length. Together, the quotient and remainder fields occupy the entire fIrst operand; therefore, the address of the quotient is the address of the fIrst operand. The divisor length cannot exceed 15 digits and sign (L2 not greater than seven) and must be less than the dividend length (L2 less than Ll); otherwise, a specification exception is recognized. The dividend, divisor, quotient, and remainder are each signed decimal integers in the packed format and are right-aligned in their fields. All sign and digit codes of the dividend and divisor are checked for validity. The sign of the quotient is determined by the rules of algebra from the dividend and divisor signs. The sign of the remainder has the same value as the dividend sign. These rules hold even when the quotient or remainder is zero. Overflow cannot occur. If the divisor is zero or the quotient is too large to be represented by the number of digits specified, a decimal-divide exception is recognized. This includes the case of division of zero by zero. The decimal-divide exception is indicated only if the sign codes of both the dividend and divisor are valid, and only if the digit or digits used in establishing the exception are valid. Condition Code: The code remains unchanged. 8-6 ESA/370 Principles of Operation 3. The condition for a decimal-divide exception can be determined by a trial comparison. The leftmost digit of the divisor is aligned one digit to the right of the leftmost dividend digit. When the divisor, so aligned, is less than or equal to the dividend, ignoring signs, a divide exception is indicated. 4. If a data exception does not exist, a decimaldivide exception occurs when the leftmost dividend digit is not zero. ~ Edit ED ~H~~ '---ID_EI--'-_L----'-I_B_l. L.-I 8 8 16 28 32 36 47 The second operand (the source), which normally contains one or more decimal numbers in the packed format, is changed to the zoned format and modified under the control of the fIrst operand (the pattern). The edited result replaces the first operand~ The length field specifies the length of· the fIrst operand, which may contain bytes of any value. The length of the source is determined by the operation according to the contents of the pattern. The source normally consists of one or more decimal numbers, each in the packed format. The leftmost four bits of each source byte must specify a decimal-digit code (0000-1001); a sign code ( 1010-1111) is recognized as a data exception. The rightmost four bits may specify either a sign code or a decimal-digit code. Access and data exceptions are recognized only for those bytes in the second operand which are actually required. The result is obtained as if both operands were processed left to right one byte at a time. Overlapping pattern and source fields give unpredictable results. During the editing process, each byte of the pattern is affected in one of three ways: 1. It is left unchanged. 2. It is replaced by a source digit expanded to the zoned fonnat. 3. It is replaced by the frrst byte in the pattern, called the fill byte. Which of the three actions takes place is determined by one or more of the following: the type of the pattern byte, the state of the significance indicator, and whether the source digit examined is zero. Pattern Bytes: There are four types of pattern bytes: digit selector, significance starter, field separator, and message byte. Their coding is as follows: Name Digit selector Significance starter Field separator Message byte Code eele eeee eele eeel eele eele Any other The detection of either a digit selector or a significance starter in the pattern causes an examination to be made of the significance indicator and of a source digit. As a result, either the expanded source digit or the fill byte, as appropriate, is selected to replace the pattern byte. Additionally, encountering a digit selector or a significance starter may cause the significance indicator to be changed. The· field separator identifies individual fields in a It is always multiple-field editing operation. replaced in the result by the fill byte, and the significance indicator is always off after the field separator is encountered. Message bytes in the pattern are either replaced by the fill byte or remain unchanged in the result, depending on the state of the significance indicator. They may thus be used for padding, punctuation, or text in the significant portion of a field or for the insertion of sign-dependent symbols. Fill Byte: The first byte of the pattern is used as the fill byte. The fill byte can have any code and may concurrently specify a control function. If this byte is a digit selector or significance starter, the indicated editing action is taken after the code has been assigned to the fill byte. Source Digits: Each time a digit selector or significance starter is encountered in the pattern, a new source digit is examined for placement in the pattern field. Either the source digit is disregarded, or it is expanded to the zoned fonnat, by appending the zone code 1111 on the left, and stored in place of the pattern byte. Execution is as if the source digits were selected one byte at a time and as if a source byte were fetched for inspection only once during an editing operation. Each source digit is examined only once for a zero value. The leftmost four bits of each byte are examined frrst, and the rightmost four bits, when they represent a decimal-digit code, remain available for the next pattern byte that calls for a digit examination. When the leftmost four bits contain an invalid digit code, a data exception is recognized, and the operation is terminated. At the time the left digit of a source byte is examined' the rightmost four bits are checked for the existence of a sign code. When a sign code is encountered in the rightmost four bit positions, these bits are not treated as a decimal-digit code, and a new source byte is fetched from storage when the next pattern byte calls for a source-digit examination. When the pattern contains no digit selector or significance starter, no source bytes are fetched and examined. Significance Indicator: The significance indicator is turned on or off to indicate the significance or nonsignificance, respectively, of subsequent source digits or message bytes. Significant source digits replace their corresponding digit selectors or significance starters in the result. Significant message bytes remain unchanged in the result. The significance indicator, by its on or off state, indicates also the negative or positive value, respectively, of a completed source field and is used as one factor in the setting of the condition code~ Chapter 8. Decimal Instructions 8-7 The significance indicator is set to off at the start of the editing operation, after a field separator is encountered, or after a source byte is examined that has a plus code in the rightmost four bit positions. The significance indicator is set to on when a significance starter is encountered whose sOJlrce digit is a valid decimal digit, or when a digit selector is encountered whose source digit is a nonzero decimal digit, provided that in both instances the source byte does not have a plus code in the rightmost four bit positions. In all other situations, the significance indicator is not changed. A minus sign code has no effect on the significance indicator. The result of an editing operation replaces and is equal in length to the pattern. It is composed of pattern bytes, fill bytes, and zoned source digits. Result Bytes: If the pattern byte is a message byte and the significance indicator is on, the message byte remains unchanged in the result. If the pattern byte is a field separator or if the significance indicator is off when a message byte is encountered in the pattern, the fill byte replaces the pattern byte in the result. If the digit selector or significance starter is encountered in the pattern with the significance indicator off and the source digit zero, the source digit is considered nonsignificant, and the fill byte replaces the pattern byte. If the digit selector or significance starter is encountered with either the significance indicator on or with a nonzero decimal source digit, the source digit is considered significant, is changed to the zoned format, and replaces the pattern byte in the result. The sign and magnitude of the last field edited are used to set the condition code. The term "last field" refers to those source digits, if any, in the second operand selected by digit selectors or significance starters after the last field separator; if the pattern contains no field separator, there is only one field, which is considered to be the last field. If no such source digits are selected, the last field is considered to be of zero length. Condition Code: Condition code 0 is set when the last field edited is zero or of zero length. Condition· code I is set when the last field edited is nonzero and the significance indicator is on. (This 8-8 ESA/370 Principles of Operation indicates a result less than zero if the last source byte examined contained a sign code in the rightmost four bits.) Condition code 2 is set when the last field edited is nonzero and the significance indicator is off. (This indicates a result greater than zero if the last source byte examined contained a sign code in the rightmost four bits.) Figure 8-3 on page 8-9 summarizes the functions of the EDIT and EDIT AND MARK operations. The leftmost four columns list all the significant combinations of the four conditions that can be encountered in the execution of an editing operation. The rightmost two columns list the action taken for each case -- the type of byte placed in the result field and the new setting of the significance indicator. Resulting Condition Code: o 1 2 3 Last field zero or zero length Last field less than zero Last field greater than zero Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) • Data Programming Notes: 1. Examples of the use of the EDIT instruction are given in Appendix A. 2. Editing includes sign and punctuation control, and the suppression and protection of leading zeros by replacing them with blanks or asterisks. It also facilitates programmed blanking of all-zero fields. Several fields may be edited in one operation, and numeric information may be combined with text. 3. In most cases, the source is shorter than the pattern because each four-bit source digit produces an eight-bit byte in the result. 4. The total number of digit selectors and significance starters in the pattern always equals the number of source digits edited. S. If the fill byte is a blank, if no significance starter exists in the pattern, and if the source digit examined for each digit selector is zero, the editing operation blanks the result field. 6. The resulting condition code indicates whether or not the last field is all zeros and, if nonzero, reflects the state of the significance indicator. The significance indicator reflects the sign of the source field only if the last source byte examined contains a sign code in the rightmost four bits. For multiple-field editing operations, the condition code reflects the sign and value only of the field following the last field separator. 7. Significant perfonnance degradation is possible when, with DAT on, the second-operand address of an ED IT instruction designates a location that is closer to the left of a 4K-byte boundary than the length of the fll'st operand of that instruction. This is because the machine may perfonn a trial execution of the instruction to detennine if the second operand actually crosses the boundary. The second operand of ED IT, while nonnally shorter than the frrst operand, can in the extreme case have the same length as the fll'st. Results Conditions Pattern Byte Digit selector Previous Right Four State of Significance Source Source Bits Indicator Digit Are Plus Code Result Byte Off On Significance starter Off On State of Significance Indicator at End of Digit Examination 0 1-9 1-9 0-9 0-9 * No Yes No Yes Fill byte Source digit# Source digit# Source digit Source digit Off On Off On Off 0 0 1-9 1-9 0-9 0-9 No Yes No Yes No Yes Fill byte Fill byte Source digit# Source digiti Source digit Source digit On Off On Off On Off Field separator * ** ** Fill byte Off Message byte Off On ** ** ** ** Fill byte Message byte Off On Explanation: * No effect on result byte or on new state of significance indicator. ** Not applicable because source is not examined. # For EDIT AND MARK only, the address of the rightmost such result byte is placed in general register 1. Figure 8-3. Summary of Editing Functions Chapter 8. Decimal Instructions 8-9 Programming Notes: Edit and Mark 1. Examples of the use of the EDIT AND instruction are given in Appendix A. [SS] ~'D_F'~__L~I_B_l~I~~~~ o 8 16 20 32 36 2. 47 The second operand (the source), which normally contains one or more decimal numbers in the packed format, is changed to the zoned format and modified under the control of the first operand (the pattern). The address of the frrst significant result byte is inserted in general register 1. The edited result replaces the pattern. EDIT AND MARK is identical to EDIT, except for the additional function of inserting the address of the result byte in general register 1 if the result byte is a zoned source digit and the significance indicator was off before the examination. If no result byte meets the criteria, general register 1 remains unchanged; if more than one result byte meets the criteria, the address of the rightmost such result byte is inserted. In the 24-bit addressing mode, the address replaces bits 8-31 of general register 1, and bits 0-7 of the register are not changed. In the 31-bit addressing mode, the address replaces bits 1-31 of general register 1, and bit 0 of the register is set to zero. The contents of access register 1 remain unchanged. o 1 2 3 Last field zero or zero length Last field less than zero Last field greater than zero EDIT AND MARK facilitates the programming of floating currency-symbol insertion. Using appropriate source and pattern data, the address inserted .in general register 1 is one greater than the address where a floating currency-sign would be inserted. BRANCH ON COUNT (BCTR), with zero in the R2 field, may be used to reduce the inserted address by one. 3. No address is inserted in general register 1 when the significance indicator is turned on as a result of encountering a significance starter with the corresponding source digit zero. To ensure that general register 1 contains a proper address when this occurs, the address of the pattern byte that immediately follows the appropriate significance starter could be placed in the register beforehand. 4. When multiple fields are edited with one execution of the EDIT AND MARK instruction, the address, if any, inserted in general register 1 applies to the rightmost field edited for which the criteria were met. s. See also the programming, note under EDIT regarding performance degradation due to a possible trial execution. Multiply Decimal MP See Figure 8-3 on page 8-9 for a summary of the EDIT and EDIT AND MARK operations. Resulting Condition Code: MARK [SS] 'Fe' o . IL. .IL2 IB. IIb~b~ I 8 12 16 20 32 36 47 The product of the frrst operand (the multiplicand) and the second operand (the multiplier) is placed at the frrst-operand location. The operands and result are in the packed format. Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) • Data The multiplier length cannot exceed 15 digits and sign (L2 not greater than seven) and must be less than the multiplicand length (L2 less than Ll); otherwise, a specification exception is recognized. The multiplicand must have at least as many bytes of leftmost zeros as the number of bytes in the multiplier; otherwise, a data exception is recog- 8-10 ESAj370 Principles of Operation nized. This restriction ensures that no product overflow occurs. The multiplicand, multiplier, and product are each signed decimal integers in the packed format and are right-aligned in their fields. All sign and digit codes of the multiplicand and multiplier are checked for validity. The sign of the product is determined by the rules of algebra from the multiplier and multiplicand signs, even if one or both operands are zeros. The second-operand address, specified by the B2 and D2 fields, is not used to address data; bits 26-31 of that address are the shift value, and the leftmost bits of the address are ignored. The shift value is a six-bit signed binary integer, indicating the direction and the number of decimaldigit positions to be shifted. Positive shift values specify shifting to the left. Negative shift values, which are represented in two's complement notation, specify shifting to the right. The following are examples of the interpretation of shift values: Condition Code: The code remains unchanged. 5hift Value Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) • Data • Specification 011111 000001 000000 111111 100000 Amount and Direction 31 digits One digit No shift One digit 32 digits to the left to the left to the right to the right Programming Notes: 1. An example of the use of the MULTIPLY DECIMAL instruction is given in Appendix A. 2. The product cannot exceed 31 digits and sign. The leftmost digit of the product is always zero. Shift and Round Decimal 5RP [55] ~I ' ,---'F0_ o ~H~~ 1_13--,-I_B1--,--1 L----,' 8 12 16 20 32 36 47 The first operand is shifted in the direction and for the number of decimal-digit positions specified by the second-operand address, and, when shifting to the right is specified, the absolute value of the fITst operand is rounded by the rounding digit, 13. The fITst operand and the result are in the packed format. The first operand is considered to be in the packeddecimal format. Only its digit portion is shifted; the sign position does not participate in the shifting. Zeros are supplied for the vacated digit positions. The result replaces the fITst operand. Nothing is stored outside of the specified fITstoperand location. For a right shift, the 13 field, bits 12-15 of the instruction, are used as a decimal rounding digit. The fITst operand, which is treated as positive by ignoring the sign, is rounded by decimally adding the rounding digit to the leftmost of the digits to be shifted out and by propagating the carry, if any, to the left. The result of this addition is then shifted right. Except for validity checking and the participation in rounding, the digits shifted out of the rightmost decimal-digit position are ignored and are lost. If one or more nonzero digits are shifted out during a left shift, decimal overflow occurs. The operation is completed. The result is obtained by ignoring the overflow digits, and condition code 3 is set. If the decimal-overflow mask is one, a program interruption for decimal overflow occurs. Overflow cannot occur for a right shift, with or without rounding, or when no shifting is specified. In the absence of overflow, the sign of a zero result is made positive. If overflow occurs, the sign of the result is the same as the original sign but with the preferred sign code. A data exception is recognized when the fITst operand does not have valid sign and digit codes or when the rounding digit is not a valid digit code. The validity of the fITst-operand codes is checked even when no shift is specified, and the validity of the rounding digit is checked even when no addition for rounding takes place. Chapter 8. Decimal Instructions 8-11 Resulting Condition Code: o 1 2 3 Result zero; no overflow Result less than zero; no overflow Result greater than zero; no overflow Overflow 1 2 3 Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Access (fetch, operand 2; fetch and store, operand 1) • Data • Decimal overflow Program Exceptions: • Access (fetch and store, operand 1) • Data • Decimal overflow Zero and Add Programming Notes: [SS] 1. Examples of the use of the SHIFT AND ROUND DECIMAL instruction are given in Appendix A. ZAP 2. SHIFT AND ROUND DECIMAL can be used for shifting up to 31 digit positions left and up to 32 digit positions right. This is sufficient to clear all digits of any decimal number even with rounding. ,---I FB_I-,--IL---I'I___L2---L.I_B1--,--1 3. For right shifts, the rounding digit 5 provides conventional rounding of the result. The rounding digit 0 specifies truncation without rounding. 4. When the B2 field is zero, the six-bit shift value is obtained directly from bits 42-47 of the instruction. Subtract Decimal [SS] ,----I FB_I 9 ~H~~ I,---L2---L.I_Bl--L-I L--...I' ..L.-...I B 12 16 29 32 36 47 The second operand is subtracted from the ftrst operand, and the reSUlting difference is placed at the ftrst-operand location. The operands and result are in the packed format. SUBTRACT DECIMAL is executed the same as ADD DECIMAL, except that the second operand is con- sidered to have a sign opposite to the sign in storage. The second operand in storage remains unchanged. Resulting Condition Code: o Result zero; no overflow 8-12 ESA/370 Principles of Operation ~H~~ 9 B 12 16 29 32 36 47 The second operand is placed at the first-operand location. The operation is equivalent to an addition to zero. The operand and result are in the packed format. Only the second operand is checked for valid sign and digit codes. Extra zeros are supplied on the left for the shorter operand if needed. If the ftrst operand is too short to contain all leftmost nonzero digits of the second operand, decimal overflow occurs. The operation is completed. The result is obtained by ignoring the overflow digits, and condition code 3 is set. If the decimaloverflow mask is one, a program interruption for decimal overflow occurs. In the absence of overflow, the sign of a zero result is made positive. If overflow occurs, a zero result is given the sign of the second operand but with the preferred sign code. The two operands may overlap, provided the rightmost byte of the ftrst operand is coincident with or to the right of the rightmost byte of the second operand. In this case the result is obtained as if the operands were processed right to left. Resulting Condition Code: o Result zero; no overflow 1 2 3 Result less than zero; no overflow Result greater than zero; no overflow Overflow Program Exceptions: • Access (fetch, operand 2; store, operand 1) • Data • Decimal overflow Programming Note: An example of the use of the ZERO AND ADD instruction is given in Appendix A. " Chapter 8. Decimal Instructions 8-13 Chapter 9. Floating-Point Instructions Floating-Point Number Representation Normalization . . . . . . . . Floating-Point-Data Format Instructions . . . . . Add Normalized . Add Unnormalized Compare Divide Halve Load 9-1 9-2 9-2 9-4 9-7 9-8 9-9 9-9 9-11 9-12 Floating-point instructions are used to perform calculations -on operands with a wide range of magnitude and to yield results scaled to preserve precision. The floating-point instructions provide for loading, rounding, adding, ~ubtracting, comparing, multiplying, dividing, and storing, as well as controlling the sign of short, long, and extended operands. Short operands generally permit faster processing and require less storage than long or extended operands. On the other hand, long and extended operands permit greater precision in computation. _Four floating-point registers are provided. Instructions may perform either register-to-register or storage-and-register operations. _ Most of the instructions generate normalized results, which preserve the highest precision in the For addition and 'subtraction, operation. instructions are also provided that generate unnormalized results. Either normalized or unnormalized numbers may be used as operands for any floatingpoint operation. Floating-Point Number Representation A floating-point number consists of a signed hexadecimal fraction and an unsigned seven-bit binary integer called the characteristic. The characteristic represents a signed exponent and is obtained by adding 64 to the exponent value (excess-64 notation). The range of the characteristic is 0 to 127, which corresponds to an exponent range of -64 to + 63. The value of a floating-point number is the product of its fraction and the number 16 Load and Test Load Complement Load Negative Load Positive Load Rounded Multiply Store . . . . . Subtract Normalized Subtract Unnormalized 9-12 9-12 9-13 9-13 9-14 9-14 9-16 9-16 9-17 raised to the power of the exponent which is represented by its characteristic. The fraction of a floating-point number is treated as a hexadecimal number because it is considered to be multiplied by a number which is a power of 16. The name, fraction, indicates that the radix point is assumed to be immediately to the left of the leftmost fraction digit. The fraction is represented by its absolute value and a separate sign bit. The entire number is positive or negative, depending on whether the sign bit of the fraction is zero or one, respectively. When a floating-point operation would cause the result exponent to exceed 63, the characteristic wraps around- from 127 to 0, and an exponentoverflow condition exists. The result characteristic is then too small by 128. When an operation would cause the exponent to be less than -64, the characteristic wraps around from 0 to 127, and an exponent-underflow condition exists. The result characteristic is then too large by 128, except that a zero characteristic is produced when a true zero is forced. A true zero is a floating-point number with a zero characteristic, zero fraction, and plus sign. A true zero may arise as the normal result of an arithmetic operation because of the particular magnitude of the operands. The result is forced to be a true zero when: 1. An exponent underflow occurs and the exponent-underflow mask bit in the psw is zero, 2. The result fraction of an addition or subtraction operation is zero and the significance mask bit in the psw is zero, or Chapter 9. Floating-Point Instructions 9-1 3. The operand of the HALVE instruction, one or both operands of the MULTIPLY instruction, or the dividend in the DIVIDE instruction has a zero fraction. When a program interruption for exponent underflow occurs, a true zero is not forced; instead, the fraction and sign remain correct, and the characteristic is too large by 128. When a program interruption for significance occurs, the fraction remains zero, the sign is positive, and the characteristic remains correct. The sign of a sum, difference, product, or quotient with a zero fraction is positive. The sign of a zero fraction resulting from other operations is established from the operand sign, the same as for nonzero fractions. other normalized operations, normalization takes place when the intermediate arithmetic result is changed to the fmal result. When the intermediate result of addition, subtraction, or rounding causes the fraction to overflow, the fraction is shifted right by one hexadecimal-digit position and the value one is supplied to the vacated leftmost digit position. The fraction is then truncated to the fmal result length, while the characteristic is increased by one. This adjustment is made for both normalized and unnormalized operations. Programming Note: Up to three leftmost bits of the fraction of a normalized number may be zeros, since the nonzero test applies to the entire leftmost hexadecimal digit. Normalization Floating-Point-Data Format A quantity can be represented with the greatest precision by a floating-point number of a given fraction length when that number is normalized. A normalized floating-point number has a nonzero lefttllost hexadecimal fraction digit. If one or more leftmost fraction digits are zeros, the number is said to be unnormalized. Floating-point numbers have a 32-bit (short) format, a 64-bit (long) format, or a 128-bit (extended) format. Numbers in the short and long formats may be designated as operands both in storage and in the floating-point registers, whereas operands having the extended format can be designated only in the floating-point registers. Unnormalized numbers are normalized by shifting the fraction left, one digit at a time, until the leftmost hexadecimal digit is nonzero and reducing the characteristic by the number of hexadecimal digits shifted. A number with a zero fraction cannot be normalized; its characteristic either remains unchanged, or it is made zero when the result is forced to be a true zero. The floating-point registers contain 64 bits each and are numbered 0, 2, 4, and 6. A short or long floating-point number requires a single floatingpoint register. An extended floating-point number requires a pair of these registers: either registers 0 and 2 or registers 4 and 6; the two register pairs are designated as 0 or 4, respectively. When the Rl or R2 field of a floating-point instruction designates any register number other than 0, 2, 4, or 6 for the short or long format, or any register number other than 0 or 4 for the extended format, a program interruption for specification exception occurs. Addition and subtraction with extended operands, as well as the MULTIPLY, DIVIDE, and HALVE operations, are performed only with normalization. Addition and subtraction with short or long oper-_ ands may be specified as either normalized or unnormalized. For all other operations, the result is produced without normalization. Short Floating-Point Number t_~ract i on i l'-s.....l_ch_a_r_a_c_te_r_i_s_t C--,I_5_-_D_i_9_ 1_· With unnormalized operations, leftmost zeros in the result fraction are not eliminated. The result mayor may not be in normalized fonn, depending upon the original operands. In both normalized and unnormalized operations, the initial operands need not be in normalized form. The operands for multiplication and division are normalized before the arithmetic process. For 9-2 ESAj370 Principles of Operation e 1 8 I 31 Long Floating-Point Number l~s~1~ch~a~r~a~ct~e~r~is~t~i~c~1~~1~4~-D~i~9~i~~F~r~a~ct~i~o~n~= e 1 8 53 Extended Floating-Point Number High-Order Part ------------~----/'--------~ High-Order Leftmost 14 Digits S Characteristic of 28-Digit Fraction L L_________ _____ / ~ o 1 8 63 Low-Order Part When an extended result is made a true zero, both the high-order and low-order parts are made a true zero. The range covered by the magnitude (M) of a normalized floating-point number depends on the format. In the short format: --------------~--------/'----------~ 16-65 s M s (1 - 16-6) X 1663 Low-Order Rightmost 14 Digits S Characteristic of 28-Digit Fraction L L___________ ______ / In the long format: 64 16-65 :s M s (1 - 16- 14) x 1663 ~ 72 127 In the extended format: In all formats, the frrst bit (bit 0) is the sign bit (S). The next seven bits are the characteristic. In the short and long formats, the remaining bits constitute the fraction, which consists of six or 14 hexadecimal digits, respectively. A short floating-point number occupies only the leftmost 32 bit positions of a floating-point register. The rightmost 32 bit positions of the register are ignored when used as an operand in the short format and remain unchanged when a short result is placed in the register. An extended floating-point number has a 28-digit fraction and consists of two long floating-point numbers which are called the high-order and loworder parts. The high-order part may be any long floating-point number. The fraction of the highorder part contains the leftmost 14 hexadecimal digits of the 28-digit fraction. The characteristic and sign of the high-order part are the characteristic and sign of the extended floating-point number. If the high-order part is normalized, the extended number is considered normalized. The fraction of the low-order part contains the rightmost 14 digits of the 28-digit fraction. The sign and characteristic of the low-order part of an extended operand are ignored. When a result in the extended format is placed in a register pair, the sign of the low-order part is made the same as that of the high-order part, and, unless the result is a true zero, the low-order characteristic is made 14 less than the high-order characteristic. When the subtraction of 14 would cause the loworder characteristic to become less than zero, the characteristic is made 128 greater than its correct value. Exponent underflow is indicated only when the high-order characteristic underflows. 16-65 s M s (1 - 16-28 ) X 1663 In all fonnats, approximately: 5.4 x 10-79 s M s 7.2 x 1075 Although the fmal result of a floating-point operation has six hexadecimal fraction digits in the short format, 14 fraction digits in the long format, and 28 fraction digits in the extended format, intermediate results have one additional hexadecimal digit on the right. This digit is called the guard digit. The guard digit may increase the precision of the fmal result because it participates in addition, subtraction, and comparison operations and in the left shift that occurs during normalization. The entire set of floating-point operations is available for both short and long operands. The instructions generate a result that has the same format as the operands, except that for MULTIPLY, a long product is produced from a short multiplier and multiplicand. Floating-point operations in the extended format are available only for normalized addition, subtraction, multiplication, and division. MULTIPLY can also generate an extended product from a long multiplier and multiplicand. LOAD ROUNDED provides for rounding from extended to long format or from long to short format. Programming Notes: 1. A long floating-point number can be converted to the extended format by appending any long floating-point number having a zero fraction, including a true zero. Conversion from the extended to the long format can be accomplished by truncation or by means of the LOAD ROUNDED instruction. 2. In the absence of an exponent overflow or exponent underflow, the long floating-point number constituting the low-order part of an Chapter 9. Floating-Point Instructions 9-3 extended result correctly expresses the value of the low-order part the extended result when the characteristic of the high-order part is 14 or higher. This applies also when the result is a true zero. When the high-order characteristic is less than 14 but the number is not a true zero, the low-order part, when considered as a long floating-point numbert does not express the correct characteristic value. or 3. The entire fraction of an extended result participates in normalization. The low-order part alone mayor may not appear to be a normalized long floating-point number, depending on whether the 15th digit of the normalized 28-digit fraction is nonzero or zero. Instructions The floating-point instructions and their mnemonics, fonnats, and operation codes are listed in Figure 9-1 on page 9. . 5. The figure also indicates when the condition code is set, the instruction fields that designate access registers, and the excep- 9-4 ESA/370 Principles of Operation tional conditions in: operand designations, data, or ' results that cause a,program interruption. Mnemonics for the floating-point instructions have an R as the last letter when the instruction is in the RR format. For instructions where all operands are the same length, certain letters are used to represent operand-format length and normalization, as follows: E U D W X Short normalized Short unnormalized Long normalized Long unnormalized Extended normalized Note: In the detailed descriptions of the individual instructions, the mnemonic and the symbolic operand designation for the assembler language are shown with each instruction. For a register-toregister operation using LOAD (short), for example, LER is the mnemonic and Rl,R2 the operand desig' nation. Mnemonic Name ADD ADD ADD ADD ADD NORMALIZED NORMALIZED NORMALIZED NORMALIZED NORMALIZED (extended) (long) .(long) (short) (short) Characteristics Op Code AXR ADR AD AER AE RR RR RX RR RX C XP C C C C SP SP A SP SP A SP AWR AW AUR AU CDR RR RX RR RX RR C C C C C SP A SP SP A SP SP COMPARE (long) COMPARE (short) COMPARE (short) DIVIDE (extended) DIVIDE (1ong) CD CER CE DXR DDR RX C RR C RX C RRE RR A SP SP A SP SP EU EO FK SP EU EO FK 82 69 39 82 79 8220 20 DIVIDE (long) DIVIDE (short) DIVIDE (short) HALVE (long) HALVE (short) DO DER DE HDR HER RX RR RX RR RR A SP SP A SP SP SP 82 60 3D 82 70 24 34 LOAD LOAD LOAD LOAD LOAD (long) (long) (short) (short) AND TEST (long) LOR LD LER LE LTDR RR RX RR RX RR C SP A SP SP A SP SP 28 82 68 38 82 78 22 LOAD LOAD LOAD LOAD LOAD AND TEST (short) COMPLEMENT (long) COMPLEMENT (short) NEGATIVE (long) NEGATIVE (short) LTER LCDR LCER LNDR LNER RR RR RR RR RR SP SP SP SP SP 32 23 33 21 31 LOAD POSITIVE (long) LOAD POSITIVE (short) LOAD ROUNDED (ext. to long) LOAD ROUNDED (long to short) MULTIPLY (extended) LPDR LPER LRDR LRER MXR RR C RR C RR RR RR SP SP SP EO SP EO SP EU EO 20 30 25 35 26 MULTIPLY MUL TIPLY MULTIPLY MULTIPLY MULTIPLY MDR MD MXDR MXD MER RR RX RR RX RR ADD UNNORMALIZED ADD UNNORMALIZED ADD UNNORMALIZED ADD UNNORMALIZED COMPARE (long) (long) (long) (short) (short) (long) (long) (long to extended) (long to extended) (short to long) C C C C C SP A SP SP A SP SP EU EU EU EU EU EO EO EO EO EO LS LS LS LS LS 36 2A 82 6A 3A 82 7A EO EO EO EO LS LS LS LS 2E 82 6E 3E 82 7E 29 EU EO FK EU EO FK EU EO FK EU EU EU EU EU EU EU EO EO EO EO EO 2C 82 6C 27 82 67 3C Figure 9-1 (Part 1 of 2). Summary of Floating-Point Instructions Chapter 9. Floating-Point Instructions 9-5 Name Mnemonic Op Code Characteristics MULTIPLY (short to long) STORE (long) STORE (short) SUBTRACT NORMALIZED (ext. ) SUBTRACT NORMALIZED (long) ME STD STE SXR SDR RX RX RX RR C RR C A A A SP EU EO SP SP SP EU EO SP EU EO LS LS B2 7C B2 60 B2 70 37 2B SUBTRACT SUBTRACT SUBTRACT SUBTRACT SUBTRACT SO SER SE SWR SW RX RR RX RR RX A SP EU EO SP EU EO A SP EU EO SP EO EO A SP LS LS LS LS LS B2 6B 3B B2 7B 2F B2 6F SP A SP LS LS 3F B2 7F NORMALIZED (long) NORMALIZED (short) NORMALIZED (short) UNNORMALIZED (long) UNNORMALIZED (long) SUBTRACT UNNORMALIZED (short) SUR SUBTRACT UNNORMALIZED (short) SU C C C C C RR C RX C EO EO ST ST Ex~lanation: A B2 C EO EU FK LS RR RRE RX SP ST Figure 9-6 Access exceptions for logical addresses. B2 field designates an access register in the access-register mode. Condition code is set. Exponent-overflow exception. Exponent-underflow exception. Floating-point-divide exception. Significance exception. RR instruction format. RRE instruction format. RX instruction format. Specification exception. PER storage-alteration event. 9-1 (Part 2 of 2). Summary of Floating-Point Instructions ESA/370 Principles of Operation Add Normalized AER Rl,R2 'JA' o AE [RR, Short Operands] I I Rl 8 R. 12 15 Rl,D2(X2,B2) o 12 8 [RX, Short Operands] 16 '2A' o I Rl I ,8 12 15 R. [RX, Long Operands] AD , 6A ' o I R I x. lB. 12 8 16 20 31 [RR, Extended Operands] AXR '36' o D. 1 l I I Rl 8 The intermediate-sum fraction consists of seven (short format), 15 (long format), or 29 (extended format) hexadecimal digits, including the guard digit, and a possible carry. If a carry is present, the sum is shifted right one digit position so that the carry becomes the leftmost digit of the fraction, and the characteristic is increased by one. 31 20 [RR, Long Operands] ADR retained as a guard digit. The fraction that is not shifted is considered to be extended with a zero in the guard-digit position. When no alignment shift occurs, both operands are considered to be extended with zeros in the guard-digit position. The fractions with signs are then added algebraically to fonn a signed intermediate sum. R. 12 15 The second operand is added to the fIrst operand, and the normalized sum is placed at the frrstoperand location. Addition of two floating-point numbers consists in characteristic comparison, fraction alignment, and signed fraction addition. The characteristics of the two operands. are compared, and the fraction accompanying the smaller characteristic is aligned with the other fraction by a right shift, with its characteristic increased by one for each hexadecimal digit of shift until the two characteristics agree. When a fraction is shifted right during alignment, the leftmost hexadecimal digit shifted out is If the addition produces no carry, the intermediate-sum fraction is shifted left as necessary to eliminate any leading hexadecimal zero digits resulting from the addition, provided the fraction is not zero. Zeros are supplied to the vacated rightmost digits, and the characteristic is reduced by the number of hexadecimal digits of shift. The fraction thus normalized is then truncated on the right to six (short fonnat), 14 (long format), or 28 (extended format) hexadecimal digits. In the extended format, a characteristic is generated for the low-order part, which is 14 less than the high-order characteristic. The sign of the sum is determined by the rules of algebra, unless all digits of the intermediate-sum fraction are zero, in which case the sign is made plus. An exponent-overflow exception is recognized when a carry from the leftmost position of the intermediate-sum fraction would cause the characteristic of the normalized sum to exceed 127. The operation is completed by making the result characteristic 128 less than the correct value, and a program interruption for exponent overflow takes place. The result sign and fraction remain correct, and, for AXR, the characteristic of the low-order part remains correct. An exponent-underflow exception is recognized when the characteristic of the normalized sum would be less than zero and the fraction is not zero. If the exponent-underflow mask bit is one, the operation is completed by making the result characteristic 128 greater than the correct value. The result sign and fraction remain correct, and a program interruption for exponent underflow takes place. When exponent underflow occurs and the Chapter 9. Floating-Point Instructions 9-7 exponent-underflow mask bit is zero, a program interruption does not take place; instead, the operation is completed by making the result a true zero. For AXR, no exponent underflow is recognized when the characteristic of the low-order part would be less than zero but the characteristic of the highorder part is zero or greater. The result fraction is zero when the intermediate-sum fraction, including the guard digit, is zero. With a zero result fraction, the action depends on the setting of the significance mask bit. If the significance mask bit is one, no normalization occurs, the intermediate and fmal result characteristics are the same, and a program interruption for significance takes place. If the significance mask bit is zero, the program interruption does not occur; instead, the result is made a true zero. Add Unnormalized • 3E' o AU Resulting Condition Code: o 1 2 Short Operands] I Rl I X, I B, I 12 16 Rl,R2 '2E' 0 20 31 [RR, Long Operands] [RX, Long Operands] 12 15 Rl,02(X2,B2) •fiE • 02 I Rl I R2 8 o [RX, 12 15 8 AW Short Operands] R, Rl,02(X2,B2) 0 Result fraction zero Result less than zero Result greater than zero 3 Rl 8 '7E' AWR The Rl field for AER, AE, ADR, and AD, and the R2 field for AER and ADR must designate register 0, 2, 4, or 6. The R 1 and R2 fields for AXR must designate register 0 or 4. Otherwise, a specification exception is recognized. I I [RR, I R I X, I B, 1 8 12 16 20 31 Program Exceptions: • • • • • Access (fetch, operand 2 of AE and AD only) Exponent overflow Exponent underflow Significance Specification Programming Notes: 1. An example of the use of the ADD NORMALI ZED instruction is given in Appendix A. 2. Interchanging the two operands in a floatingpoint addition does not affect the value of the sum. 3. The ADD NORMALIZED instruction normalizes the sum but not the operands. Thus, if one or both operands are unnonnalized, precision may be lost during fraction alignment. The second operand is added to the fIrst operand, and the unnormalized sum is placed at the fIrstoperand location .. The execution of ADD UN NORMALIZED is identical to that of ADD NORMALIZED, except that: 1. When no carry is present after the addition, the intennediate-sum fraction is truncated to the proper result-fraction length without a left shift to eliminate leading hexadecimal zeros and without the corresponding reduction of the characteristic. 2. Exponent underflow cannot occur. 3. The guard digit does not participate in the recognition of a zero result fraction. A zero result fraction is recognized when the fraction (that is, the intennediate-sum fraction, excluding the guard digit) is zero. The Rl and R2 fields must designate register 0, 2,4, or 6; otherwise, a specification exception is recognized. 9-8 ESA/370 Principles of Operation Resulting Condition Code: o I 2 3 The fIrst operand is compared with the second operand, and the condition code is set to indicate the result. Result fraction zero Result less than zero Result greater than zero Program Exceptions: • • • • Access (fetch, operand 2 of AU and A W only) Exponent overflow Significance Specification Programming Notes: 1. An example of the use of the ADD UNNORMALIZED instruction is given in Appendix A. 2. Except when the result is made a true zero, the characteristic of the result of ADD UNNORMALIZED is equal to the greater of the two operand -characteristics, increased by one if the fraction addition produced a carry, or set to zero if exponent overflow occurred. Compare [RR, Short Operands] '39' o I I R. 8 The comparison is algebraic and follows the procedure for normalized floating-point subtraction, except that the difference is discarded after setting the condition code and both operands remain unchanged. When the difference, including the guard digit, is zero, the operands are equal. When a nonzero difference is positive or negative, the fIrst operand is high or low, respectively. An exponent-overflow, exponent-underflow, or significance exception cannot occur. The R 1 and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. Resulting Condition Code: o 1 2 3 Operands equal First operand low First operand high Program Exceptions: • Access (fetch, operand 2 of CE and CD only) • Specification R, Progr~mming 12 15 Notes: 1. Examples of the use of the COMPARE instruction are given in Appendix A. CE Rl,02(X2,B2) o 8 12 [RX, Short Operands] 16 20 31 [RR, Long Operands] '29' o co R. 8 Divide [RR, Short Operands] 12 15 R. X, 12 '3D' [RX, Long Operands] I I I 8 3. Numbers with zero fractions compare equal even when they differ in sign or characteristic. R, Rl,02(X2,B2) '69' o I I 2. An exponent inequality alone is not sufficient to determine the inequality of two operands with the same sign, because the fractions. may have different numbers of leading hexadecimal zeros. 16 o B, I R. I R. 8 12 15 D. 20 31 Chapter 9. Floating-Point Instructions 9-9 Rl,D2(X2,B2) DE '70' e I Rl I X2 I B2 I 8 OOR [RX, Short Operands] 12 16 e 12 15 [RX, Long Operands] Rl,02(X2,B2) 160 1 9 OXR I Rl I X2 I B2 8 Rl,R2 18220 1 o 31 I Rll R2 8 DO 20 [RR, Long Operands] Rl,R2 120 1 02 16 12 D2 20 31 less than the correct value. If, for the DIVIDE (DXR) instruction, the low-order characteristic would also exceed 127, it, too, is decreased by 128. The result is normalized, and the sign and fraction remain correct. A program interruption for exponent overflow occurs. An exponent-underflow exception exists when the characteristic of the final quotient would be less than zero and the fraction is not zero. If the exponent-underflow mask bit is one, the operation is completed by making the characteristic 128 greater than the correct value, and a program interruption for exponent underflow occurs. The result is normalized, and the sign and fraction remain correct. If the exponent-underflow mask bit is zero, a program interruption does not take place; instead, the operation is completed by making the quotient a true zero. For the DXR instruction, exponent underflow is not recognized when the low-order characteristic is less than zero but the high-order characteristic is equal to or greater than zero. [RRE, Extended Operands] I11111111I 16 24 Rl I R2 I 28 31 The frrst operand (the dividend) is divided by the second operand (the divisor), and the normalized quotient is placed at the fJtst-operand location. No remainder is preserved. Floating-point division consists in characteristic subtraction and fraction division. The operands are frrst normalized to eliminate leading hexadecimal zeros. The difference between the dividend and divisor characteristics of the normalized operands, plus 64, is used as the characteristic of an intermediate quotient. All dividend and divisor fraction digits participate in fonning the fraction of the intermediate quotient. The intermediate-quotient fraction can have no leading hexadecimal zeros, but a right shift of one digit position may be necessary with an increase of the characteristic by one. The fraction is then truncated to the proper result-fraction length. Exponent underflow does not occur when an operand characteristic becomes less than zero during normalization of the operands or when the intermediate-quotient characteristic is less than zero, as long as the fmal quotient can be represented with the correct characteristic. When the divisor fraction is zero, a floating-pointdivide exception is recognized. This includes the case of division of zero by zero. When the dividend fraction is zero, but the divisor fraction is nonzero, the quotient is made a true zero. No exponent overflow or exponent underflow occurs. The sign of the quotient is determined by the rules of algebra, except that the sign is always plus when the quotient is made a true zero. The Rl field for DER, DE, DDR, and DD, and the R2 field for DER and DDR, must designate register 0, 2, 4, or 6. The Rl and R2 fields for DXR must designate register 0 or 4. Otherwise, a specification exception is recognized. Condition Code: The code remains unchanged. An exponent-overflow exception is recognized when the characteristic of the fmal quotient would exceed 127 and the fraction is not zero. The operation is completed by making the characteristic 128 9-10 ESA/370 Principles of Operation Program Exceptions: • Access (fetch, operand 2 of DD and • Exponent overflow DE only) • Exponent underflow • Floating-point divide • Specification Programming Note: DIVIDE Examples of the use of the instruction are given in Appendix A. the exponent-underflow mask bit is zero, a program interruption does not take place; instead, the operation is completed by making the result a true zero. When the fraction of the second operand is zero, the result is made a true zero, and no exponent underflow occurs. Halve [RR, Short Operands] '34' o I Rl I R, 8 The sign of the result is the same as that of the second operand, except that the sign is always plus when the quotient is made a true zero. The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. 12 15 Condition Code: The code remains unchanged. [RR, Long Operands] Program Exceptions: '24' o I Rl I R, 8 • Exponent underflow • Specification 12 15 Programming Notes: The second operand is divided by 2, and the normalized quotient is placed at the fust-operand location. The fraction of the second operand is shifted right one bit position, placing the contents of the rightmost bit position in the leftmost bit position of the guard digit, and a zero is supplied to the leftmost bit position of the fraction. The intermediate result, including the guard digit, is then normalized, and the fmal result is truncated to the proper length. An exponent-underflow exception exists when the characteristic of the fmal result would be less than zero and the fraction is not zero. If the exponentunderflow mask bit is one, the operation is completed by making the characteristic 128 greater than the correct value, and a program interruption for exponent underflow occurs. The result is normalized, and the sign and fraction remain correct. If 1. An example of the use of the HALVE instruction is given in Appendix A. 2. With short and long operands, the halve operation is identical to a divide operation with the number 2 as divisor. Similarly, the result of HDR is identical to that of MD or MDR with one-half as a multiplier. No multiply operation corresponds to HER, since no multiply operation produces short results. 3. The result of HALVE is zero only when the second-operand fraction is zero, or when exponent underflow occurs with the exponentunderflow mask set to zero. A fraction with zeros in every bit position, except for a one in the rightmost bit position, does not become zero after the right shift. This is because the one bit is preserved in the guard-digit position and,· when the result is not made a true zero because of exponent underflow, becomes the leftmost bit after normalization of the result. Chapter 9. Floating-Point Instructions 9-11 Load and Test Load [RR, Short Operands] [RR, Short Operands] '38' I R. o IR2 '32' Rl,02(X2,S2) LE o 12 15 8 [RX, Short Operands] 8 8 LOR 12 16 20 Rl,R2 '28' o [RR, Long Operands] I R. I R2 8 LO 31 12 15 [RR, Long Operands] LTOR Rl,R2 '22' o I R. I·R2 o I I R2 R. 8 12 15 The second operand is placed unchanged at the frrst-operand location, and its sign and magnitude are tested to determine the setting of the condition code. ' The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. 12 15 Rl,02(X2,B2) [RX, Long Operands] Resulting Condition Code: '68' o I I I X2 R. 8 12 °I B2 16 20 31 2 Result fraction zero Result less than zero Result greater than zero 3 The second operand is placed unchanged at the frrst-operand location. Program Exceptions: • Specification The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2 of LE and LD only) • Specification Programming Note: When the same register is designated as the frrst-operand and second-operand location, the operation is equivalent to a test without data movement. Load Complement '33' o 9-12 ESAj370 Principles of Operation [RR, Short Operands] LeER Rl,R2 I R. I R2 8 12 15 [RR, Long Operands] '23' e I R, I R, 8 12 The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. Resulting Condition Code: 15 o 1 Result fraction zero Result less than zero The second operand is placed at the first-operand location with the sign bit inverted. . 2 The sign bit is inverted, even if the fraction is zero. The characteristic and fraction are not changed. Program Exceptions: 3 • Specification The Rl and R2 fields must designate regi&ter 0, 2, 4, or 6; otherwise, a specification exception is recognized. Load Positive [RR, Short Operands] Resulting Condition Code: o 1 2 3 Result fraction zero Result less than zero Result greater than zero Program Exceptions: '38' e 8 '28' Load Negative o '31' e I I R, 8 R, 12 15 The second operand is placed at the frrst-operand location with the sign made plus. I R, I R, The sign bit is made zero. The characteristic and fraction are not changed. 12 15 LNDR Rl,R2 e [RR, Long Operands] [RR, Short Operands] 8 '21' 12 15 LPDR Rl,R2 • Specification LNER Rl,R2 I R, I R, [RR, Long Operands] I I R, 8 The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. R, 12 15 The second operand is placed at the frrst-operand location with the sign made minus. The sign bit is made one, even if the fraction is zero. The characteristic and fraction are not changed. Resulting Condition Code: o Result fraction zero 1 2 3 Result greater than zero Program Exceptions: • Specification Chapter 9. Floating-Point Instructions 9-13 Load Rounded Exponent-underflow and significance exceptions cannot occur. LRER Rl,R2 The R 1 field must designate register 0, 2, 4, or 6; the R2 field of LRER must designate register 0, 2, 4, or 6; and the R2 field of LRDR must designate register or 4. Otherwise, a specification exception is recognized. [RR, Long Operand 2, Short Operand 1] Rl '35' o 8 I R2 I 12 15 ° Condition Code: The code remains unchanged. Program Exceptions: LROR Rl,R2 • Exponent overflow • Specification [RR, Extended Operand 2, Long Operand 1] '25' o I I Rl 8 R2 I 12 15 The second operand is rounded to the next shorter format, and the result is placed at the first-operand location. Multiply MER Rl,R2 [RR, Short Multiplier and Multiplicand, Long Product] '3C' Rounding consists in adding a one in bit position 32 or 72 of the long or extended second operand, respectively, and propagating any carry to the left. The sign of the fraction is ignored, and addition is performed as if the fractions were positive. If rounding causes a carry out of the leftmost hexadecimal digit position of the fraction, the fraction is shifted right one digit position so that the carry becomes the leftmost digit of the fraction, and the characteristic is increased by one. o I I Rl R2 12 15 8 [RX, Short Multiplier and Multiplicand, Long Product] , 7C ' o I R I X2 B2 1 8 12 16 D2 20 31 The intermediate fraction is then truncated to the proper result-fraction length. MOR The sign of the result is the same as the sign of the second operand. There is no normalization to eliminate leading zeros. An exponent-overflow exception exists when shifting the fraction right would cause the characteristic to exceed 127. The operation is completed by loading a number whose characteristic is 128 less than the correct value, and a program interruption for exponent overflow occurs. The result is normalized, and the sign and fraction remain correct. 9-14 ESA/370 Principles of Operation Rl,R2 '2C' 0 MO I Rl I R2 8 12 15 [RX, Long Operands] Rl,02(X2,B2) '6C' 0 [RR, Long Operands] I Rl I X2 I B2 8 12 16 02 20 31 [RR, long Multiplier and Multiplicand, Extended Product] '27' e I Rl I R2 I 8 12 15 [RX, long Multiplier and Multiplicand, Extended Product] '67' e MXR Rl 8 Rl,R2 '26' o I I I X2 12 16 B2 02 20 31 [RR, Extended Operands] I Rl I R2 I 8 12 15 The nonnalized product of the second operand (the multiplier) and the frrst operand (the multiplicand) is placed at the frrst-operand location. Multiplication of two floating-point numbers consists in exponent addition and fraction multiplication. The operands are frrst nonnalized to eliminate leading hexadecimal zeros. The sum of the characteristics of the nonnalized operands, less 64, is used as the characteristic of the intennediate product. The fraction of the intennediate product is the exact product of the nonnalized operand fractions. When the intennediate-product fraction has one leading hexadecimal zero digit, the fraction is shifted left one digit position, bringing the contents of the guard-digit position into the rightmost position of the result fraction, and the intennediateproduct characteristic is reduced by one. The fraction is then truncated to the proper result-fraction length. For MER and ME, the mUltiplier and multiplicand fractions have six hexadecimal digits; the product fraction has the full 14 digits of the long fonnat, with the two rightmost fraction digits always zeros. For MDR and MD, the multiplier and multiplicand fractions have 14 digits, and the fmal product fraction is truncated to 14 digits. For MXDR and MXD, the multiplier and multiplicand fractions have 14 digits, with the multiplicand occupying the highorder part of the frrst operand; the fmal product fraction contains 28 digits and is an exact product of the operand fractions. For MXR, the multiplier and multiplicand fractions have 28 digits, and the fmal product fraction is truncated to 28 digits. An exponent-overflow exception is recognized when the characteristic of the fmal product would exceed 127 and the fraction is not zero. The operation is completed by making the characteristic 128 less than the correct value. If, for extended results, the low-order characteristic would also exceed 127, it, too, is decreased by 128. The result is nonnalized, and the sign and fraction remain correct. A program interruption for exponent overflow occurs. Exponent overflow is not recognized when the intermediate-product characteristic is initially 128 but is brought back within range by nonnalization. An exponent-underflow exception exists when the characteristic of the fmal product would be less than zero and the fraction is not zero. If the exponent-underflow mask bit is one, the operation is completed by making the characteristic 128 greater than the correct value, and a program interruption for exponent underflow occurs. The result is nonnalized, and the sign and fraction remain correct. If the exponent-underflow mask bit is zero, program interruption does not take place; instead, the operation is completed by making the product a true zero. For extended results, exponent underflow is not recognized when the loworder characteristic would be less than zero but the high-order characteristic is equal to or greater than zero. Exponent underflow does not occur when the characteristic of an operand becomes less than zero during normalization of the operands, as long as the final product can be represented with the correct characteristic. When either or both operand fractions are zero, the result is made a true zero, and no exponent overflow or exponent underflow occurs. The sign of the product is detennined by the rules of algebra, except that the sign is always zero when the result is made a true zero. Chapter 9. Floating-Point Instructions 9-15 The Rl field for MER, ME, MDR, and MD, and the R2 field for MER, MDR, and MXDR must designate register 0,2,4, or 6. The Rl field for MXDR, MXD, and MXR, and the R2 field for MXR must designate register 0 or 4. Otherwise, a specification exception' is recognized. Subtract Normalized Condition Code: The code remains unchanged. o [RR t Short Operands] '3B' I I R. 8 R, 12 15 Program Exceptions: • Access (fetch, operand 2 of ME, MD, and MXD only) • Exponent overflow • Exponent underflow • Specification SE Rl t D2(X2 t B2) '7B' o [RX t Short Operands] I I I I R. X, 12 8 B, 16 20 0, 31 Programming Notes: 1. An example of the use of the instruction is given in Appendix A. MULTIPLY 2. Interchanging the two operands in a floatingpoint multiplication does not affect the value of the product. Store STE SDR '2B' o SD Rl t D2(X2 t B2) 12 I R. IR' 12 15 8 Rl t D2(X2 t B2) o 8 [RR t Long Operands] [RX t Long Operands] [RX t Short Operands] 170 1 o Rl t R2 16 20 12 8 16 20 31 31 [RR t Extended Operands] STD Rl t D2(X2 t B2) [RX t Long Operands] '37' o 160 1 o 8 12 16 20 31 The frrst operand is placed unchanged at the second-operand location. The Rl field must designate register 0, 2, 4, or 6; otherwise, a specification exception is recognized. I I I R. 8 R, 12 15 The second operand is subtracted from the frrst operand, and the normalized difference is placed at the frrst-operand location. The execution of SUBTRACf NORMALIZED is identical to that of ADD NORMALIZED, except that the second operand participates in the operation with its sign bit inverted. Condition Code: The code remains unchanged. Program Exceptions: • Access (store, operand 2) • Specification 9-16 ESA/370 Principles of Operation The Rl field of SER, SE, SDR, and SD, and the R2 field OfSER and SDR must designate register 0, 2, 4, or 6. The Rl and R2 fields of SXR must designate register 0 or 4. Otherwise, a specification exception is recognized. Resulting Condition Code: o 1 2 3 SW Result fraction zero Result less than zero Result greater than zero '6F' o Program Exceptions: • • • • • Access (fetch, operand 2 of SE and Exponent overflow Exponent underflow Significance Specification so only) Rl,R2 '3F' o SU [RR, Short Operands] I I R. R2 I IX21 82 1 R. 8 12 16 20 ::02 31 The second operand is subtracted from the fust operand, and the unnormalized difference is placed at the first-operand location. The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a specification exception is recogniud. Resulting Condition Code: 12 15 8 [RX, Long Operands] The execution of SUBTRAcr UNNORMALIZEO is identical to that of ADD UNNORMALIZEO, except that the second operand participates in the operation with its sign bit inverted. Subtract Unnormalized SUR Rl,D2(X2,B2) Rl,D2(X2,B2) [RX, Short Operands] o Result fraction zero 1 2 Remit less than zero Retult greater than zero 3 Program Exceptions: o 8 12 16 20 • Acce.ss (fetch, operand 2 of su and sw only) 31 [RR, Long Operands] '2F' e I I R. 8 • Exponent overflow • Significance • Specification R2 12 15 Chapter 9. Pleating-Point Instructions 9-17 Chapter 10. Control Instructions Branch and Stack Diagnose Extract Primary ASN Extract Secondary ASN Extract Stacked Registers Extract Stacked State Insert Address Space Control Insert PSW Key . . . . . . . Insert Storage Key Extended Insert Virtual Storage Key Invalidate Page Table Entry Load Address Space Parameters Load Control Load PSW . . . . . . . . Load Real Address Load Using Real Address Modify Stacked State Move to Primary Move to Secondary Move with Destination Key Move with Key Move with Source Key Program Call .. Program Return Program Transfer Purge ALB '" 10-5 10-7 10-7 10-8 10-8 10-10 10-12 10-12 10-13 10-13 10-14 10-16 10-24 10-24 10-25 10-27 10-27 10-29 10-29 10-30 10-31 10-32 10-34 10-44 10-47 10-53 This chapter includes all privileged and semiprivileged instructions described in this publication, except the input/output instructions, which are described in Chapter 14, "I/O Instructions." Privileged instructions may be executed only when the CPU is in the supervisor state. An attempt to execute a privileged instruction in the problem state generates a privileged-operation exception. The semiprivileged instructions are those instructions that can be executed in the problem state when certain authority requirements are met. An attempt to execute a semiprivileged instruction in the problem state when the authority requirements are not met generates a privileged-operation exception or some other program-interruption condition depending on the particular requirement which is violated. Those requirements which cause a privileged-operation exception to be· generated in the problem state are not enforced when execution is attempted in the supervisor state. Purge TLB . . . . . . . . . . . Reset Reference Bit Extended Set Address Space Control Set Clock . . . . . . . Set Clock Comparator Set CPU Timer Set Prefix . . . . . . . Set PSW Key from Address Set Secondary ASN ... Set Storage Key Extended Set System Mask Signal Processor . . . . . Store Clock Comparator Store Control Store CPU Address Store CPU ID Store CPU Timer Store Prefix . . . . Store Then AND System Mask Store Then OR System Mask Store Using Real Address Test Access .. Test Block Test Protection Trace 10-53 10-53 10-54 10-55 10-56 10-56 10-56 10-57 10-58 10-61 10-61 10-61 10-63 10-63 10-63 10-64 10-64 10-65 10-65 10-65 10-66 10-66 10-69 10-71 10-73 The control instructions and their mnemonics, formats, and operation codes are listed in Figure 10-1 on page 10-2. The figure also indicates when the condition code is set, the instruction fields that designate access registers, and the exceptional conditions in operand designations, data, or results that cause a program interruption. For those control instructions which have special rules regarding the handling of exceptional situations, a section called "Special Conditions" is included. This section indicates the type of ending (suppression, nullification, or completion) only for those exceptions for which the ending may vary. Note: In the detailed descriptions of the individual instructions, the mnemonic and the symbolic operand designation for the assembler language are shown with each instruction. For LOAD psw, for example, LPSW is the mnemonic and D2(B2) the operand designation. Chapter 10. Control Instructions 10-1 Programming Note: The following additional instructions are available in ESA/370 as compared to • • • • 370-XA: • • • BRANCH AND STACK EXTRACT STACKED REGISTERS EXTRACTSTACKEDSTATE • LOAD USING REAL ADDRESS Name MODIFY STACKED STATE MOVE WITH DESTINATION KEY MOVE WITH SOURCE KEY PROGRAM RETURN • PURGE ALB • STORE USING REAL ADDRESS • TEST ACCESS Mnemonic Op Code Characteristics SF T EPAR RRE EREG RRE ESTA RRE C Al P DM Q Al Al SP SO SE SE R R R EXTRACT SECONDARY ASN INSERT ADDRESS SPACE CONTROL INSERT PSW KEY INSERT STORAGE KEY EXTENDED INSERT VIRTUAL STORAGE KEY ESAR lAC IPK ISKE IVSK RRE RRE C S RRE RRE Q Q Q P Al Q Al SO SO R R R INVALIDATE PAGE TABLE ENTRY LOAD ADDRESS SPACE PARAMETERS LOAD CONTROL LOAD PSW LOAD REAL ADDRESS IPTE LASP LCTL LPSW LRA RRE SSE C RS S L RX C P Al P Al SP AS P ASP P A SP P Al AT LOAD USING REAL ADDRESS MODIFY STACKED STATE MOVE TO PRIMARY MOVE TO SECONDARY MOVE WITH DESTINATION KEY LURA MSTA MVCP MVCS MVCDK RRE RRE SS C SS C SSE MK P Al SP Al SP SE SO QA SO QA QA MOVE WITH KEY MOVE WITH SOURCE KEY PROGRAM CALL PROGRAM RETURN PROGRAM TRANSFER MVCK MVCSK PC PR PT SS C Q A ST Bl B2 D9 SSE MK Q A GM ST Bl B2 E50E Q Al ZI T ¢ GM B R ST S B218 Al Z4 T ¢2 E U B R ST 0101 Q Al SP Z2 T ¢ RRE B228 B PURGE ALB PURGE TLB RESET REFERENCE BIT EXTENDED SET ADDRESS SPACE CONTROL SET CLOCK PALB PTLB RRBE SAC SCK RRE S RRE C S S C BRANCH AND STACK DIAGNOSE EXTRACT PRIMARY ASN EXTRACT STACKED REGISTERS EXTRACT STACKED STATE BAKR RRE DM 10-2 ESA/370 Principles of Operation G2 SO P P P Al Q SP SW P A SP Figure 10-1 (Part 1 of 3). Summary of Control Instructions B ST B240 MD 83 B226 Ul U2 B249 B24A B227 B224 B20B B229 R2 B223 R $ Bl ¢ R B221 E500 B2 B7 B2 82 BP B1 R ¢ ¢ GM $ $ ¢ ST ST ST ST B1 B2 B24B B247 DA DB E50F B248 B20D B22A B219 B2 B204 ) Name Mnemonic CLOCK COMPARATOR CPU TIMER PREFIX PSW KEY FROM ADDRESS SECONDARY ASN SCKC SPT SPX SPKA SSAR S S S S RRE SET STORAGE KEY EXTENDED SET SYSTEM MASK SIGNAL PROCESSOR STORE CLOCK COMPARATOR STORE CONTROL SSKE SSM SIGP STCKC STCTL RRE S RS C S RS P Al P A SP SO P P A SP P A SP STORE STORE STORE STORE STORE STAP STIDP STPT STPX STNSM S S S S SI PA PA PA PA PA STOSM STURA TAR TB TPROT TRACE SI RRE RRE C RRE C SSE C RS P A SP P Al SP Al AS P Al II $ G0 P Al P A SP T It SET SET SET SET SET CPU ADDRESS CPU ID CPU TIMER PREFIX THEN AND SYSTEM MASK STORE THEN OR SYSTEM MASK STORE USING REAL ADDRESS TEST ACCESS TEST BLOCK TEST PROTECTION TRACE Op Code Characteristics P A SP P A SP P A SP B2 B206 B2 B208 B2 B210 B20A B225 $ Q Al Z3 T ¢ B22B B2 80 AE B2 B207 B2 B6 ¢ $ R ST ST ST ST ST ST ST Bl SP SP SP SP ST Bl SU Ul R Bl B2 B2 B2 B2 B212 B202 B209 B211 AC AD B246 B24C B22C E501 99 Explanation: ¢ ¢2 $ A Al AS AT B Bl B2 BP C DM G0 G2 GM Causes serialization and checkpoint synchronization. Causes serialization and checkpoint synchronization when the state entry to be unstacked is a program-call state entry. Causes serialization. Access exceptions for logical addresses. Access exceptions; not all access exceptions may occur; see instruction description for details. ASN-translation-specification and special-operation exceptions. ASN-translation-specification exception. PER branch event. Bl field designates an access register in the access-register mode. B2 field designates an access register in the access-register mode. B2 field designates an access register when PSW bits 16 and 17 have the val ue 01. Condition code is set. Depending on the model, DIAGNOSE may generate various program exceptions and may change the condition code. Instruction execution includes the implied use of general register 0. Instruction execution includes the implied use of general register 2. Instruction execution includes the implied use of multiple general registers: General registers 0 and 1 for MOVE WITH DESTINATION KEY and MOVE WITH SOURCE KEY. General registers 3, 4, and 14 for PROGRAM CALL. Figure 10-1 (Part 2 of 3). Summary of Control Instructions Chapter 10. Control Instructions 10-3 Explanation (Continued): II L MD Interruptible instruction. New condition code is loaded. Designation of access registers in the access-register mode is modeldependent. MK Move-with-source-or-destination-key facility. P Privileged-operation exception. Q Privileged-operation exception for semiprivileged instructions. PER general-register alteration event. R Rl Rl field designates an access register in the access-register mode. R2 R2 field designates an access register in the access-register mode. RRE RRE instruction format. RS RS instruction format. RX RX instruction format. S S instruction format. SE Special operation, stack-empty, stack-specification, and stack-type exceptions. SF Special-operation, stack-full, and stack-specification exceptions. SI SI instruction format. SO Special-operation exception. SP Specification exception. SS SS instruction format. SSE SSE instruction format. ST PER storage-alteration event. SU PER store-using-real-address event. SW Special-operation exception and space-switch event. Trace exceptions (which include trace table, addressing, and low-address T protection). U Condition code is unpredictable. Ul Rl field designates an access register unconditionally. U2 R2 field designates an access register unconditionally. Zl Additional exceptions and events for PROGRAM CALL (which include AFX-translation, ASN-translation-specification, ASX-translation, EX-translation, LX-translation, PC-translation-specification, special-operation, stack-full, and stack-specification exceptions and space-switch event). Z2 Additional exceptions and events for PROGRAM TRANSFER (which include AFXtranslation, ASN-translation-specification, ASX-translation, primaryauthority, and special-operation exceptions and space-switch event). Z3 Additional exceptions for SET SECONDARY ASN (which include AFX translation, ASN-translation specification, ASX translation, secondary authority, and special operation). . Z4 Additional exceptions and events for PROGRAM RETURN (which i.nclude AFXtranslation, ASN-translatiQn-specification, ASX-translation, secondaryauthority, special-operation, stack-empty, stack-operation, stack-specification, and stack-type exceptions and space-switch event). Figure 10-1 (Part 3 of 3). Summary of Control Instructions t 0-4 ESA/370 Principles of Operation Subsequently, when the R 2 field is nonzero, the instruction address in the current psw is replaced by the branch address. The branch address is generated from the contents of general register R2 under the control of the current addressing mode. When the R2 field is zero, the operation is perfonned without branching. Branch and Stack BAKR [RRE] IB240 1 o 16 24 28 31 A linkage-stack branch state entry is fonned, and the current PSW, except with an unpredictable PER mask and an addressing-mode bit and instruction address from the frrst operand substituted for bits 32-63, is placed in the state entry. Subsequently, the updated instruction address in the current psw is replaced from the second operand. The new value of psw bits 32-63 and the psw-key mask, PASN, SAsN, EAX, and contents of general registers 0-15 and access registers 0-15 also are placed in the state entry. The action associated with an operand is not performed if the R field designating the operand is zero. The branch state entry is formed and information is placed in it as described in the section "Stacking Process" in Chapter 5, "Program Execution." The entry-type code in the state entry is 0000100 binary. Key-controlled protection does not apply to accesses to the linkage stack, but low-address and page protection do apply. Special Conditions The CPU must be in the primary-space mode or access-register mode, and the address-spacefunction control, bit 15 of control register 0 must be one; otherwise, a special-operation exception is recognized. Bits 16-23 of the instruction are ignored. When the R 1 field is nonzero, the contents of general register R 1 specify an address referred to as the return address. The return address is generated from the contents of the register under the control of the addressing mode specified by bit 0 of the register: 24-bit mode if bit 0 is zero, or 31-bit mode if bit 0 is one. Bit 0 of the register and the return address are substituted for the addressing-mode bit and the updated instruction address, respectively, in the current psw when the contents of that psw are placed in the state entry. The contents of the current psw are not changed. When the R 1 field is zero, there is no substitution for the addressing-mode bit and instruction address in the current psw when that psw is placed in the state entry. A stack-full or stack-specification exception may be recognized during the stacking process. The operation is suppressed on all addressing and protection exceptions. The priority of recognition of program exceptions for the instruction is shown in Figure 10-2 on page 10-6. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch or store, except for key-controlled protection, linkage-stack entry) • Special operation • Stack full • Stack specification • Trace Chapter 10. Control Instructions 10-5 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off, the CPU being in secondary-space mode or home-space mode, or the address-space-function control, bit 15 of control register 0, being zero. 8.A Trace exceptions (only if R2 is nonzero). 8.B.1 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry. Note: Exceptions 8.B.2-8.B.7 can occur only if there is not enough remalnlng free space in the current linkage-stack section. 8.B.2 Stack-specification exception due to remaining-free-space value in current linkage-stack entry not being a multiple of 8. 8.B.3 Access exceptions (fetch) for second word of the trailer entry of the current section. The entry is presumed to bea trailer entry; its entry-type field is not examined. 8.B.4 Stack-full exception due to forward-section validity bit in the trailer entry being zero. 8.B.5 Access exceptions (fetch) for entry descriptor of the header entry of the next section. This entry is presumed to be a header entry; its entry-type field is not examined. 8.B.6 Stack-specification exception due to not enough remaining free space in the next section. 8.B.7 Access exceptions (store) for second word of the header entry of the next section. If there is no exception, the header is now called the current entry. 8.B.8 Access exceptions (store) for entry descriptor of the current entry and for the new state entry. Figure 10-2. Priority of Execution: BRANCH AND STACK Programming Notes:' BRANCH AND STACK provides a programlinkage function that is comparable to the function of BRANCH AND SAVE. 1. Examples of the use of the BRANCH AND STACK instruction are given in Appendix A. 2. In no case does BRANCH AND the current addressing mode. STACK change 3. The effect when the Rl field is zero is that the return address, which would otherwise be specified by the R 1 general register, is the address of the next sequential instruction. In this case, 10-6 ESA/370 Principles of Operation 4. BRANCH AND STACK with a nonzero Rl field is intended for use at or near the entry point of a called program. The program may be called by means of BRANCH AND LINK (BALR),. BRANCH AND SAVE (BAS or BASR) , or BRANCH AND SAVE AND SET MODE, or by means of a BRANCH AND SET MODE instruction located in a "glue module." In all of these cases, even when the addressing mode was changed during the calling linkage, BRANCH AND STACK correctly saves the addressing mode and 24-bit or 31-bit return address of the calling program so that the subsequent execution of PROGRAM RETURN will return correctly to the calling program. other aspects of system operation, including instruction execution and channel-program operation, to an extent that the operation does not comply with that specified in this publication. As a result of the improper use of DIAGNOSE, the system may be left in such a condior tion that the power-on reset initial-micro program-loading (IML) function must be performed. Since the function performed by DIAGNOSE may differ from model to model and between versions of a model, the program should avoid issuing DIAGNOSE unless the program recognizes both the model number and version code stored by STORE CPU ID. Diagnose '83' o 8 31 The CPU performs built-in diagnostic functions, or other model-dependent functions. The purpose of the diagnostic functions is to verify proper functioning of equipment and to locate faulty components. Other model-dependent functions may include disabling of failing buffers, reconfiguration of cpus, storage, and channel paths, and modification of control storage. Bits 8-31 may be used as in the SI or RS formats, or in some other way, to specify the particular diagnostic function. The use depends on the model. Extract Primary ASN EPAR Rl [RRE] '8226' o 16 24 28 31 The 16-bit PASN, bits 16-31 of control register 4, is placed in bit positions 16-31 of general register Rl. Bits 0-15 of the general register are set to zeros. Bits 16-23 and 28-31 of the instruction are ignored. The execution of the instruction may affect the state of the CPU and the contents of a register or storage location, as well as the progress of an I/O operation. Some diagnostic functions may cause the test indicator to be turned on. Condition Code: The code is unpredictable. Program Exceptions: • Privileged operation • Depending on the model, other exceptions may be recognized. Programming Notes: 1. Since the instruction is not intended for problem-state-program or control-program use, DIAGNOSE has no mnemonic. 2. unlike other instructions, does not follow the rule that programming errors are distinguished from equipment errors. Improper use of DIAGNOSE may result in false machinecheck indications or may cause actual machine malfunctions to be ignored. It may also alter DIAGNOSE, Special Conditions The instruction must be executed with DAT on; otherwise, a special-operation exception is recognized. The special-operation exception is recognized in both the problem and supervisor states. In the problem state, the extraction-authority control, bit 4 of control register 0, must be one; otherwise, a privileged-operation exception is recognized. In the supervisor state, the extractionauthority-control bit is not examined. The priority of recognition of program exceptions for the instruction is shown in Figure 10-3 on page 10-8. Condition Code: The code remains unchanged. Program Exceptions: • Privileged operation (extraction-authority control is zero in the problem state) • Special operation Chapter 10. Control Instructions 10-7 Program Exceptions: 1.-6. Exceptions with the same priority es the priority of program-interruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off. 8. Privileged-operation exception due to extraction-authority control, bit 4 of control register 0, being zero in problem state. Figure 10-3. Priority of Execution: PRIMARY ASN • Privileged operation (extraction-authority control is zero in the problem state) • Special operation EXTRAcr 1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off. 8. Privileged-operation exception due to extraction-authority control bit 4 of control register 0, being zero in problem state. Extract Secondary ASN ESAR Rl Figure 10-4. Priority of Execution: ONDARY ASN [RRE] IB2271 o EXTRACT SEC- Extract Stacked Registers 16 24 28 31 The 16-bit SASN, bits 16-31 of control register 3, is placed in bit positions 16-31 of general register Rl. Bits 0-15 of the general register are set to zeros. EREG [RRE] IB249 1 o I11111111I Rl 16 24 R2 28 31 Bits 16-23 and 28-31 of the instruction are ignored. Special Conditions The instruction must be executed with DAT on; otherwise, a special-operation exception is recognized. The special-operation exception is recognized in both the problem and supervisor states. In the problem state, the extraction-authority control, bit 4 of control register 0, must be one; otherwise, a privileged-operation exception is recognized. In the supervisor state, the extractionauthority-control bit is not examined. The priority of recognition of program exceptions for the instruction is shown in Figure 10-4. Condition Code: The code remains unchanged. 10-8 ESA/370 Principles of Operation The contents of a set of general registers and a set of access registers that were saved in the last state entry in the linkage stack are restored to the registers. Each set of registers begins with register R 1 and ends with register R2. For each of the general registers and the access registers, the registers are loaded in ascending order of their register numbers, starting with register Rl and continuing up to and including register R2, with register 0 following register 15. Each register is loaded from the position in the state entry where the contents of the register were saved when the state entry was created. The contents of the state entry remain unchanged. The last state entry is located as described in the section "Unstacking Process" in Chapter 5, "Program Execution." The state entry remains in the linkage stack, and the linkage-stack-entry address in control register 15 remains unchanged. suppressed on all addressing Key-controlled protection does not apply to references to the linkage stack. The operation exceptions. Bits 16-23 of the instruction are ignored. The priority of recognition of program exceptions for the instruction is shown in Figure 10-5. IS Special Conditions Condition Code: The code remains unchanged. The CPU must be in the primary-space mode, access-register mode, or home-space mode, and the address-space-function control, bit 15 of control register 0, must be one; otherwise, a specialoperation exception is recognized. A stack-empty, stack-specification, or stack-type exception may be recognized during the unstacking process. Program Exceptions: • Access (fetch, except for protection, linkagestack entry) • Special operation • Stack empty • Stack specification • Stack type 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to the CPU being in the real mode or secondary-space mode or the address-space-function control, bit 15 of control register 0, being zero. 8. Access exceptions for entry descriptor of the current linkagestack entry. 9. Stack-type exception due to current entry not being a state entry or header entry. Note: Exceptions 10-14 can occur only if the current entry is a header entry. 10. Access exceptions for second word of the header entry. 11. Stack-empty exception due to backward stack-entry validity bit in the header entry being zero. 12. Access exceptions for entry descriptor of preceding entry, which is the entry designated by the backward stack-entry address in the current (header) entry. 13. Stack-specification exception due to preceding entry being a header entry. 14. Stack-type exception due to preceding entry not being a state entry. 15. Access exceptions for the selected contents of the state entry. Figure 10-5. Priority of Execution: EXTRACf STACKED REGISTERS Chapter 10. Control Instructions 10-9 In a Program-Call State Entry Extract Stacked State PC Number ESTA 144 [RRE] 'B24A' I11111111I R. o 24 16 148 R2 Modifiable Area 28 31 152 The contents of one of the four eight-byte fields immediately preceding the entry descriptor of the last state entry in the linkage stack are placed in the pair of general registers designated by the Rl field. The condition code is set to indicate whether the state entry is a branch state entry or a program-call state entry. The Rl field designates the even-numbered register of an even-odd pair of general registers. Bits 24-31 of general register R2 are an unsigned binary integer that is used to select the state-entry byte positions from which information is to be extracted, as follows: Value of Bits 24-31 of Gen. Reg. R2 State-Entry Byte Positions Selected o 128-135 136-143 144-151 152-159 1 2 3 The format of byte positions 128-159 of the state entry is as follows: PKM 128 SASN 130 EAX 132 PASN 134 10-10 148 The contents of the state entry remain unchanged. The last state entry is located as described in the section "Unstacking Process" in Chapter 5, "Program Execution." The state entry remains in the linkage stack, and the linkage-stack-entry address in control register 15 remains unchanged. When the entry-type code in the entry descriptor of the state entry is 0000100 binary ,indicating a branch state entry, the condition code is set to O. When the entry-type code is 0000101 binary, indicating a program-call state entry, the condition code is set to 1. Key-controlled protection does not apply to references to the linkage stack. Bits 16-23 of the instruction and bits 0-23 of general register R2 are ignored. Special Conditions A specification exception is recognized when R 1 is odd or the value of bits 24-31 of general register R2 is greater than three. 135 143 A stack-empty, stack-specification, or stack-type exception may be recognized during the un stacking process. The operation is suppressed on all addressing exceptions. In a Branch State Entry 144 159 The CPU must be in the primary-space mode, access-register mode, or home-space mode, and the address-space-function control, bit 15 of control register 0, must be one; otherwise, a specialoperation exception is recognized. PSW 136 151 151 ESA/370 Principles of Operation The priority of recognition of program exceptions for the instruction is shown in Figure 10-6 on page 10-11. Resulting· Condition Code: o 1 2 3 Branch state entry Program-call state entry Program Exceptions: • Access (fetch, except for protection, linkagestack entry) • Special operation • Specification • Stack empty • Stack specification • Stack type 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to the CPU being in the real mode or secondary-space mode or the address-space-function control, bit 15 of control register 0, being zero. 8.A Specification exception due to Rl being odd or bits 24-31 of general register R2 having a value greater than three. 8.B.1 Access exceptions for entry descriptor of the current linkagestack entry. 8.B.2 Stack-type exception due to current entry not being a state entry or header entry. Note: Exceptions 8.B.3-8.B.7 can occur only if the current entry is a header entry. 8.B.3 Access exceptions for second word of the header entry. 8.B.4 Stack-empty exception due to backward stack-entry validity bit in the header entry being zero. 8.B.5 Access exceptions for entry descriptor of preceding entry, which is the entry designated by the backward stack-entry address in the current (header) entry. 8.B.6 Stack-specification exception due to preceding entry being a header entry. 8.B.7 Stack-type exception due to preceding entry not being a state entry. 8.B.8 Access exceptions for the selected contents of the state entry. Figure 10-6. Priority of Execution: EXTRACT STACKED STATE Chapter 10. Control Instructions 10-11 Insert Address Space Control lAC 1~-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to DAT being off. 8. Privileged-operation exception due to extraction-authority control, bit 4 control register 0, being zero in problem state. [RRE] IB2241 e 16 24 28 31 The address-space-control bits, bits 16 and 17 of the current PSW, are placed in reversed order in bit positions 22 and 23 of general register Rl; that is, bit 16 is placed in bit position 23, and ·bit 17 is placed in bit position 22. Bits 16-21 of the register are set to zeros, and bits 0-15 and 24-31 of the register remain unchanged. The address-space-control bits are also used to set the condition code. Figure 10-7. Priority of Execution: INSERT ADDRESS SPACE CONTROL Bits 16-23 and 28-31 of the instruction are ignored. Programming Notes: Special Conditions The instruction must be executed with OAT on; otherwise, a special-operation exception is recognized. The special-operation exception is recognized in both the problem and supervisor states. In the problem state, the extraction-authority control, hit 4 of control register 0, must be one; otherwise, a privileged-operation exception is recognized. In the supervisor state, the extractionauthority-control bit is not examined. The priority of recognition of program exceptions for the instruction is shown in Figure 10-7. 1. Bits 16-21 of general register R 1 are reserved for expansion for use with possible future facilities. The program should not depend on these bits being set to zeros. 2. INSERT ADDRESS SPACE CONTROL and SET ADDRESS SPACE CONTROL are dermed to operate on the third byte of a general register so that the address-space-control bits can be saved in the same general register as the psw key, which is placed in the fourth byte of general register 2 by INSERT PSW KEY. Insert PSW Key [S] JPK Resulting Condition Code: o 2 3 psw bits 16 and 17 zeros (indicating primaryspace mode) psw bit 16 one and bit 17 zero (indicating secondary-space mode) psw bit 16 zero and bit 17 one (indicating access-register mode) psw bits 16 and 17 ones (indicating homespace mode) Program Exceptions: • Privileged operation (extraction-authority control is zero in the problem state) • Special operation 10-12 ESA/370 Principles of Operation IB20B' o 1////////////////1 16 31 The four-bit psw-key, bits 8-11 of the current PSW, is inserted in bit positions 24-27 of general register 2, and bits 28-31 of that register are set to zeros. Bits 0-23 of general register 2 remain unchanged. Bits 16-31 of the instruction are ignored. Special Conditions In the problem state, the extraction-authority control, bit 4 of control register 0, must be one; otherwise, a privileged-operation exception is recog- nized. In the supervisor state, the extractionauthority-control bit is not examined. Insert Virtual Storage Key [RRE] Condition Code: The code remains unchanged. Program Exceptions: IB223 1 • Privileged operation (extraction-authority control is zero in the problem state) Insert Storage Key Extended [RRE] e I11111111I Rl I R. 16 28 31 24 I The storage key for the location designated by the virtual address in general register R2 is inserted in general register R1. Bits 16-23 of the instruction are ignored. IB229 1 e 16 24 28 31 The storage key for the block that is addressed by the contents of general register R2 is inserted in general register R1. Bits 16-23 of the instruction are ignored. In the 24-bit addressing mode, bits 8-19 of general register R2 designate a 4K -byte block in real storage, and bits 0-7 and 20-31 of the register are ignored. In the 31-bit addressing mode, bits 1-19 of general register R2 designate a 4K-byte block in real storage, and bits 0 and 20-31 of the register are ignored. The address designating the storage block, being a real address, is not subject to dynamic address translation. The reference to the storage key is not subject to a protection exception. The seven-bit storage key is inserted in bit positions 24-30 of· general register R1, and bit 31 is set to zero. The contents of bit positions 0-23 of the register remain unchanged. Condition Code: The code remains unchanged. Program Exceptions: Selected bits of general register R2 are used as a virtual address. In the 24-bit addressing mode, the address is designated by bits 8-31 of the register, and bits 0-7 are ignored. In the 31-bit addressing mode, the address is designated by bits 1-31, and bit 0 is ignored. The address is a virtual address and is subject to the address-space-control bits, bits 16 and 17 of the current psw. The address is treated as a primary virtual address in the primary-space mode, as a secondary virtual address in the secondary-space mode, as an AR-specified virtual address in the access-register mode, or as a home virtual address in the home-space mode. The reference to the storage key is not subject to a protection exception. Bits 0-4 of the storage key, which are the accesscontrol bits and the fetch-protection bit, are placed in bit positions 24-28 of general register R1, with bits 29-31 set to zeros. The contents of bit positions 0-23 of the register remain unchanged. The change and reference bits in the storage key are not inspected. The change bit is not affected by the operation. The reference bit, depending on the model, mayor may not be set to one as a result of the operation. The following diagram shows the storage key and the register positions just described. • Addressing (address specified by general register R2) • Privileged operation Chapter 10. Control Instructions 10-13 Storage Key for the Location IACC IFI+I Teros~ I a 24 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off. 8. Privileged-operation exception due to extraction-authority control, bit 4 of control register a, being zero. 9. Access exceptions (except for protection) for address specified by general register R2. I IACC IFl e0e l Rl 1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. 28 31 Special Conditions The instruction must be executed with DAT on; otherwise, a special-operation exception is recognized. The special-operation exception is recognized in both the problem and supervisor states. In the problem state, the extraction-authority control, bit 4 of control register 0, must be one; otherwise, a privileged-operation exception is recognized. In the supervisor state, the extractionauthority-control bit is not examined. The priority of recognition of program exceptions for the instruction is shown in Figure 10-8. Figure 10-8. Priority of Execution: VIRTUAL STORAGE KEY INSERT Programming Notes: 1. Since all bytes in a 4K-byte block are associated with the same page and the same storage key, bits 20-31 of general register R2 essentially are ignored. 2. In the access-register mode, access register 0 . designates the primary address space regardless of the contents of access register O. Condition Code: The code remains unchanged. Invalidate Page Table Entry Program Exceptions: • Access (except for protection, address specified by general register R2) • Privileged operation (extraction-authority control is zero in the problem state) • Special operation [RRE] 'B221' 1111111111 16 24 R. I R, 28 31 The designated page-table entry is invalidated, and the translation-Iookaside buffers (TLBS) in all CPUs in the configuration are cleared of the associated entries. Bits 16-23 of the instruction are ignored. The contents of general register Rl have the format of a segment-table entry with only the page-table origin used. The contents of general register R2 have the format of a virtual address with only the page index used. The contents of fields that are not part of the page-table origin or page index are ignored. 10-14 ESA/370 Principles of Operation The contents of the general registers just described are as follows: • The page index designated by the second operand • The page-frame real address contained in the designated page-table entry "I Page-Table Origin 9 1 26 1/1//1//1//1/1 12 PX 31 1/1///I//I//II 29 31 The page-table origin and the page index designate a page-table entry, following the dynamic-addresstranslation rules for page-table lookup. The pagetable origin is treated as a 31-bit address, and the addition is performed by using the rules for 31-bit address' arithmetic, regardless of the setting of the addressing mode, which is specified by bit 32 of the current psw. Carries into bit position 0 as a result of the addition of the page index and page-table origin are ignored. The address formed from these two components is a real address. The page-invalid bit of this page-table entry is set to one. During this procedure, no page-table-length check is made, and the page-table entry is not inspected for availability or format errors. Additionally, the pageframe/ real address contained in the entry is not checked for an addressing exception. The entire page-table entry is fetched concurrently from storage. Subsequently the byte containing the page-invalid bit is stored. The fetch access to the page-table entry is subject to key-controlled protection, and the store access is subject to keycontrolled protection and low-address protection. A serialization function is performed before the operation begins and again after the operation is completed. As is the case for all· serialization operations, this serialization applies only to this cpu; . other cpus are not necessarily serialized. If it is successful in setting the page-invalid bit to one, this cpu clears selected entries from its TLB and signals all CPUs in the configuration to clear selected entries from their TLBs. Each TLB is cleared of at least those entries that have been formed using all of the following: • The page-table origin designated by the fIrst operand The execution of INVALIDATE PAGE TABLE ENTRY is not completed on the cpu which executes it until ( 1) all entries corresponding to the specified parameters have been cleared from the TLB on this cpu and (2) all other CPus in the configuration have completed any storage accesses, including the updating of the change and reference bits, by using TLB entries corresponding to the specified parameters. Special Conditions When bit positions 8-12 of control register 0 contain an invalid code, a translation-specification exception is recognized. The exception is recognized regardless of whether DAT is on or off. The operation is suppressed on all addressing and protection exceptions. Condition Code: The code remains unchanged. Program Exceptions: • Addressing (page-table entry) • Privileged operation • .Protection (fetch and store, page-table entry, key-controlled protection, and low-address protection) • Translation specification (bits 8-12 in control register 0 only) Programming Notes: 1. The selective clearing of entries may be implemented in different ways, depending on the model, and, in general,. more entries may be cleared than the minimum number required. Some models nlay clear all entries which contain the designated page-frame real address. Others may clear all entries which contain the designated page index, and some implementations may clear precisely the minimum number of entries required. Therefore, in order for a program to operate on all models, the program should not take advantage of any properties obtained by a less selective· clearing on a particular model. 2. The clearing of TLB entries may make use of the page-frame real address in the page-table entry. Therefore, if the page-table entry, when Chapter 10. Control Instructions 10-15 in the attached state, ever contained a pageframe real address that is different from the current value, copies of the previous values may remain in the TLB. 3. INVALIDATE PAGE TABLE ENTRY cannot be safely used to update a shared location in main storage if the possibility exists that another CPU or a channel program may also be updating the location. 4. The address of the page-table entry for INV ALIDATE PAGE TABLE ENTRY is a 3 I-bit real address, and the address arithmetic is performed by following the normal rules for 31-bit address arithmetic with wraparound at 231 - I. Contrast this with implicit translation and the translation for LOAD REAL ADDRESS, both of which, depending on the model, may treat addresses of OAT-table entries as either real or absolute and may result either in wraparound or in an addressing exception when a carry occurs into bit position O. Accordingly, the OAT tables should not be specified to wrap from maximum storage locations to location 0 and should not be placed at storage locations whose real and absolute addresses are different. Load Address Space Parameters LASP 'E500 0 I Bl I&H&~ / / 16 20 32 The doubleword frrst operand contains a psw-key mask (PKM), a secondary ASN (SASN), an authorization index (AX), and a primary ASN (PASN). The primary ASN is translated by means of the ASN-translation tables to obtain a PSTD, LTD or PASTEO, and, optionally, an AX. The secondary ASN is translated by means of the ASN-translation tables to obtain an SSTD, and, optionally, an authority check is made to ensure that the new AX is authorized to establish the new SASN. The doubleword at the frrst-operand location has the following format: PKM-d 0 I 16 SASN-d PASN-d AX-d 32 48 63 36 47 The contents of the doubleword at the frrstoperand location contain values to be loaded into control registers 3 and 4, including a secondary ASN and a primary ASN. Execution of the instruction consists in performing four major steps: PASN translation, SASN translation, SASN authorization, and control-register loading. Each of these steps mayor may not be performed, depending on the outcome of certain tests and on the setting of bits 29-31 of the second-operand address. These steps, when successful, obtain additional values, which are loaded into control registers 1, 5, and 7. When the steps are not successful, no control registers are 10-16 When the address-space-function (ASP) control, bit 15 of control register 0, is zero, control register 5 contains the linkage-table designation (LTD), and this instruction may place a new LTD in control register 5. When the ASP control is one, control register 5 contains the primary-AsN-second-tableentry origin (PASTEO ), and this instruction may place a new PASTEO in control register 5. For simplicity, this defmition sometimes frrst describes an operation as if the AS F control were zero and then describes the different operation that occurs when the ASP control is one. [SSE] 01 (81) ,02 (82) 1 changed, and the reason is indicated in the condition code. ESAj370 Principles of Operation The "d" stands for designated doubleword and is used to distinguish these fields from other fields with similar names which are referred to in the definition. The current contents of the corresponding fields in the control registers are referred to as PKM -old, SASN -old, etc. The updated. contents of the control registers are referred to as PKM -new, SASN-new, etc. The second-operand address is not used to address data; instead, the rightmost three bits are used to control portions of the operation. The remainder of the second-operand address is ignored. Bits 29-31 of the second-operand address are used as follows: Function Specified in Second Operand Bit When Bit Is Zero When Bit Is One 29 ASN translation per- ASN translation performed only when new formed. * ASN and old ASN are different. 3e AX associated with PASN used. AX from first operand used. 31 SASN authorization performed. * SASN authorization not performed. * SASN translation and SASN authorization are performed only when SASN-d is not not equal to PASN-d. When SASN-d is equal to PASN-d, the SSTD is loaded from the PSTD, and no authorization is performed. The operation of LOAD ADDRESS SPACE PARAMETERS is depicted in Figure 10-12 on page 10-23. P ASN Translation In the PAsN-translation process, the PAsN-d is translated by means of the ASN frrst table and the ASN second table. The STD and LTD fields, and optionally the AX field, obtained from the ASN-second-table entry are subsequently used to update the corresponding control registers. However, when the ASP control is one, the LTD is not obtained, and the PASTEO resulting from PASN translation is used to update control register 5. When bit 29 of the second-operand address is one, PASN translation is always performed. When bit 29 is zero, PASN translation is performed only when PASN-d is not equal to PASN-old. When bit 29 is zero and PAsN-d is equal to PAsN-old, the PSTD-old and the LTD-old or PASTEO-old are left unchanged in the control registers and become the pSTD-new and the LTD-new or PASTEo-new, respectively. In this case, if bit 30 is zero, then the AX -old is left unchanged in the control register and becomes the Ax-new. The PASN translation follows the normal rules for ASN translation, except that the invalid bits, bit 0 in the ASN-frrst-table entry and bit 0 in the ASN-second-table entry, when ones, do not result in an ASN-translation exception, and the space-switchevent-control bit in the ASN-second-table entry, when one, does not result in a space-switch event. When either of the invalid bits is one, condition code 1 is set. When the ASN-second-table entry is valid and either the current primary space-switchevent-control bit in control register 1 is one or the space-switch-event-control bit in the ASN-secondtable entry is one, condition code 3 is set. When condition code 1 or 3 is set, the control registers remain unchanged. The contents of the AX, STD, and LTD fields in the ASN-second-table entry which is accessed as a result of the PASN translation are referred to as AX-p, STD-p, and LTD-p, respectively.· The origin of the ASN-second-table entry is referred to as PASTEO-p. SASN Translation In the sAsN-translation process, the SASN-d is translated by means of the ASN frrst table and the ASN second table. The STD field obtained from the ASN-second-table entry is subsequently used to update the secondary-segment-table designation (SSTD) in control register 7. The ATO and ATL fields obtained are used in the SASN authorization, if it occurs. SASN translation is performed only when SASN-d is not equal to PASN -d. When SASN -d is equal to PASN -d, the SSTD-new is set to the same value as PSTD-new. When sAsN-d is equal to sAsN-old, bit 29 (force ASN translation) is zero, and bit 31 (skip SASN authorization) is one, SASN translation is not performed, and sSTD-old becomes SSTD-new. The SASN translation follows the normal rules for ASN translation, except that the invalid bits, bit 0 in the ASN-frrst-table entry and bit 0 in the ASN-second-table entry, when ones, do not result in an ASN-translation exception. When either of the invalid bits is one, condition code 2 is set, and the control registers remain unchanged. The contents of the STD, ATO, and ATL fields in the ASN-second-table entry which is accessed as a result of the SASN translation are referred to as STD-S, ATO-S, and ATL-S, respectively. SASN Authorization SASN authorization is performed when bit 31 of the second-operand address is zero and sAsN-d is not equal to PASN-d. When sAsN-d is equal to PAsN-d or when bit 31 of the second-operand address is one, SASN authorization is not performed. Chapter 10. Control Instructions 10-17 is SASN authorizatjon performed by using ATO-S, ATL-S, and the intended value for AX-new. When bit 30 of the second-operand address is zero and PASN translation was performed, the intended value for Ax-new is AX-p. When bit 30 of that address is zero and PASN translation was not performed, the AX is not changed, and AX -new is the same as AX -old. When bit 30 of that address is one, the intended value for AX-new is Ax-d. SASN authorization follows the rules for secondary authorization as described in the section "AsN-Authorization Process" in Chapter 3, "Storage." If the SASN is not authorized (that is, the authority-table length is exceeded, or the selected bit is zero), condition code 2 is set, and none of the control registers is updated. Control-Register Loading When the PAsN-translation, sAsN-translation, and SASN -authorization functions, if called for in the operation, are performed without encountering any exceptions, the operation is completed by replacing the contents of control registers 1, 3, 4, 5, and 7 with the new values, and condition code 0 is set. The control registers are loaded as follows: The psw-key-mask and SASN fields in control register 3 are replaced by the PKM-d and sAsN-d fields from the first-operand location. The PASN, bits 16-31' of control register 4, is replaced by the PASN-d field from the frrst-operand location. The authorization index, bits 0-15 of control register 4, is replaced as follows: • When bit 30 of the second-operand address is one, from AX -d. • When bit 30 of the second-operand address is zero and PASN translation is performed, from AX-p. • When bit 30 of the second-operand address is zero and PASN translation is not performed, the authorization index is not changed. The primary segment-table designation in control register 1 and the linkage-table designation or primary-AsN-second-table-entry origin (PASTEO) in control register 5 are replaced as follows: • When PASN translation is performed, the primary segment-table designation in control register 1 is replaced from the STD-P field, which is obtained during PASN translation. 10-18 ESA/370 Principles of Operation Also, the linkage-table designation in control register 5 is replaced from the LTD-p field if the ASF control is zero, or the primary-AsN-secondtable origin (p ASTEO ) in control register 5 is replaced by the PASTEO-p if the ASF control is When the ASF control is one, the one. PASTEO-p is placed in bit positions 1-25 of control register 5, and zeros are placed in bit positions 0 and 26-31. • When PASN translation is not performed, the contents of control registers 1 and 5 remain unchanged. The contents of the secondary segment-table designation in control register 7 are replaced as follows: • When sAsN-d equals PAsN-d, by the new contents of control register 1, the primary segmenttable designation. ' • When SASN translation is performed, by the contents of the STD-S. When SASN-d does not equal PAsN-d and SASN translation is not performed, the secondary segment-table designation remains unchanged. Other Condition-Code Settings When PASN translation is called for and cannot b~ completed because bit 0 is one in either the ASN-frrst-table entry or the ASN-second-tableentry, condition code 1 is set, and the control registers are not changed. When PASN translation is called for and completed and either (1) the current primary space-switchevent-control bit, bit 0 of control register I is one or (2) the space-switch-event-control bit in the ASN-second-table entry is one, condition code 3 is set, and the control registers are not changed. When SASN translation is called for and the translation cannot be completed because either (1) bit 0 is one in either the ASN -frrst-tableentry or the ASN-second-table entry, or (2) SASN authorization is called for and the SASN is not authorized, condition code 2 is set, and the control registers are not changed. Special Conditions The instruction can be executed only when the ASN-translation control, bit 12 of control register 14, is one. If the ASN-translation-control bit is zero, a special-operation exception is recognized. The frrst operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. 2 Primary ASN not available; parameters not loaded Secondary ASN not available or not authorized; parameters not loaded Space-switch event specified; parameters not loaded The operation is suppressed on all addressing and protection exceptions. 3 Figure 10-10 on page 10-21 and Figure 10-9 on page 10-20 summarize the functions of the instruction and the priority of recognition of exceptions and condition codes. Program Exceptions: Resulting Condition Code: o Translation and parameters loaded authorization complete; • Access (fetch, operand I) • Addressing (AsN-frrst-table entry, ASN-secondtable entry, authority-table entry) • ASN-translation specification • Privileged operation • Special operation • Specification Chapter 10. Control Instructions 10-19 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second and third instruction halfwords. 7.B.1 Privileged-operation exception. 7.B.2 Special-operation exception due to the ASN-translation control, bit 12 of control register 14, being zero. 8. Specification exception. 9. Access exceptions for the first operand. 19. Execution of PASN translation (when performed). 19.1 Addressing exception for access to ASN-first-table entry. 19.2 Condition code 1 due to I bit (bit 9) in ASN-first-table entry being one. 19.3 ASN-translation-specification exception due to invalid ones (bits 28-31) in ASN-first-table entry. 19.4 Addressing exception for access to ASN-second-table entry. 19.5 Condition code 1 due to I bit (bit 9) in ASN-second-table entry being one. 19.6 ASN-translation-specification exception due to invalid ones (bits 39, 31, 69-63) in ASN-second-table entry. 19.7 Condition code 3 due to either the old or new space-switch-eventcontrol bit being one. 11. Execution of SASN translation (when performed). 11.1 Addressing exception for access to ASN-first-table entry. 11.2 Condition code 2 due to I bit (bit 9) in ASN-first-table entry being one. 11.3 ASN-translation-specification exception due to invalid ones (bits 28-31) in ASN-first-table entry. 11.4 Addressing exception for access to ASN-second-table entry. 11.5 Condition code 2 due to I bit (bit 9) in ASN-second-table entry being one. 11.6 ASN-translation-specification exception due to invalid ones (bits 39, 31, 69-63) in ASN-second-table entry. 12. Execution of secondary authorization (when performed). 12.1 Condition code 2 due to authority-table entry being outside table. 12.2 Addressing exception for access to authority-table entry. 12.3 Condition code 2 due to S bit in authority-table entry being zero. Figure 10-9. Priority of Execution: LOAD ADDRESS SPACE PARAMETERS 10-20 ESA/370 Principles of Operation SecondOperandAddress Bitsl PASN-d Equals PASN-old 29 Yes Yes Yes Yes No No 0 0 1 1 - - Result Field PASN Translation Performed PSTD-new AX-new CR5-new 2 PKM-new SASN-new PASN-new 30 0 1 0 1 0 1 No No Yes Yes Yes Yes PSTD-old PSTD-old STD-p STD-p STD-p STD-p AX-old AX-d AX-p AX-d AX-p AX-d CR5-old CR5-old CR5-p CR5-p CR5-p CR5-p PKM-d PKM-d PKM-d PKM-d PKM-d PKM-d SASN-d SASN-d SASN-d SASN-d SASN-d SASN-d PASN-d PASN-d PASN-d PASN-d PASN-d PASN-d Figure 10-10 (Part 1 of 2). Summary of Actions: LOAD ADDRESS SPACE PARAMETERS Second-OperandAddress Bitsl SASN SASN SASN-d SASN-d Equals Equals Translation Authorization Result Field Performed Performed 3 PASN-d SASN-old 29 31 SSTD-new Yes No No No No No - Yes Yes Yes No No - 0 1 - - 1 1 0 1 0 No No Yes Yes Yes Yes No No No Yes 'No Yes PSTD-new SSTD-old STD-s STD-s STD-s STD-s Ex~lanation: - Action in this case is the same regardless of the outcome of this comparison or of the setting of this bit. 1 Second-operand-address bits: 29 Force ASN translation. 30 Use AX from first operand. 31 Skip secondary authority test. 2 "CR5" stands for "LTD" if the ASF control, bit 15 of control register 0, is zero or for "PASTEO" if the ASF control is one. 3 SASN authorization is performed using ATO-s, ATL-s, and AX-new. Figure 10-10 (Part 2 of 2). Summary of Actions: LOAD ADDRESS SPACE PARAMETERS Chapter 10. Control Instructions 10-21 Programming Notes: Abbreviation for 1. Bits 29 and 31 in the second-operand address are intended primarily to provide improved perfonnance for those cases where the associated action is unnecessary. ControlRegister Number. Bit When bit 29 is set to zero, the action of the instruction is based on the assumption that the current values for PSTD-old, LTD-old or PASTEO-old, and AX -old are consisient with PASN-old and that SSTD-old is consistent with SASN -old. When this is not the case, bit 29 should be set to one. 1. 0-31 3.0-15 3.16-31 4.0-15 4.16-31 5.0-31 5.1-25 7.0-31 Bit 31, when one, eliminates the sASN-authorization test. The program may be able to determine in certain cases that the SASN is authorized, either because of prior use or because the AX being loaded is authorized to access all address spaces. Previous Contents Subsequent Contents PSTD-old PKM-old SASN-old AX;..old PASN-old LTD-old PASTEO-old SSTD-old PSTD-new PKM-new SASN-new AX-new PASN-new LTD-new PASTEO-new SSTD-new First-Operand Bit Positions Abbreviation 0-15 16-31 32-47 48-63 2. The sASN-translation and sAsN-authorization steps are not perfonned when sAsN-d is equal to PAsN~d. This is consistent with the action in SET SECONDARY ASN to current primary (SSAR-Cp), which does not perfonn the translation or ASN authorization. PKM-d SASN-d AX-d PASN-d Abbreviation Used for the Field When Accessed as Part of 3. See Figure 10-11 for a listing of abbreviations used in this instruction description. Field in ASNSecond-Table Entry 1-29 32-47 48-59 64-95 96-127 PASN Translation SASN Translation - ATO-s - ATL-s STD-s - AX-p STD-p LTD-pI - Explanation: - The field is not used in this case. 1 LTD-p is accessed only when the ASF control is zero. When the ASF control is one, PASTEO-p is used in the operation, and it is bits 1-25 of the address of the ASN-second-table entry. Figure 10-11. Summary of Abbreviations for LOAD ADDRESS SPACE PARAMETERS 10-22 ESA/370 Principles of Operation IFetch op-l dou~~ord PASN-d = PASN-old AND Op-2-addr bit 29 = 8 N °---.ll No '--_---,,.--_---Jf-- ~ Cond Code I ? Yes Either old or new Yes space-switch-eventcontrol bit = 1 ? PSTD-old ~ PSTD-tmp LTD-old ~ LTD-tmp Note AX-old -. AX-tmp \3 ~ Cond COde\ . No STD-p LTD-p AX-p ~ ~ ~ PSTD-tmp LTD-tmp Note AX-tmp SASN-d = SASN-old AND Op-2-addr bit 29 = 8 No AND Op-2-addr bit 31 = 1 ? IASN ava il~t--_NO_-'·12 ~ Cond. Code I \ Yes PSTD-tmp~ TVe, STD-s SSTD-tmp No .-~p-2-addr o Op-2-addr bit 38 Yes SSTD-tmp ~ ---,-----' ~ =~ --bit 31 = 8 ? ? AX-tmp ~ AX-new -~Authorize~.-NO--•• 12 -~ con~ Note Note: PSTD-tmp LTD-tmp SSTD-tmp ~ PSTD-n~~ ~ PKM-new ~ ~ PASN-new ~ I PKM-d LTD-new 1-----I~iISASN-d SSTD-new PASN-d F~ ~ SASN-new~ ~~J Replace "LTD" with "PASTED" when the ASF control is one. Figure 10-12. Execution of LOAD ADDRESS SPACE PARAMETERS Chapter 10. Control Instructions 10-23 registers 9-11. Where possible, the program should avoid unnecessary loading of control registers. In loading control registers 9-11, most models attempt to optimize for the case when the bits of control register 9 are zeros. Load Control [RS] 'B7' o I R. I R, I B2 8 12 16 02 20 31 The set of control registers starting with control register Rl and ending with control register RJ is loaded from the locations designated by the secondoperand address. The storage area from which the contents of the control registers are obtained starts at the location designated by the second-operand address and continues through as many storage words as the number of control registers specified. The control registers are loaded in ascending order of their register numbers, starting with control register Rl and continuing up to and including control register R3, with control register 0 following control register 15. The second operand remains unchanged. Special Conditions The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2) • Privileged operation • Specification Programming Notes: 1. To ensure that existing programs operate cor- rectly if and when new facilities using additional control-register positions are defmed, only zeros should be loaded in unassigned control-register positions. 2. Loading of control registers on some models may require a significant amount of time. This is particularly true for changes in significant parameters. For example, the TLB may be cleared of entries as a result of changing or .enabling the program-event-recording parameters in control 10-24 As another example, the translation format, bits 8-12 of control register 0, is initialized to all zeros by initial CPU reset. An all-zero value is an invalid translation format, and, on some models, results in purging the TLB even though DAT may be off. Thus, the program should avoid loading invalid values for this field. ESA/370 Principles of Operation Load PSW '82' o I11111111I 8 16 B2 02 20 31 The current psw is replaced by the contents of the doubleword at the location designated by the second-operand address. Bits 8-15 of the instruction are ignored. A serialization and checkpoint-synchronization function is performed before or after the operand is fetched and again after the operation is completed. Special Conditions The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. The value which is to be loaded by the instruction is not checked for validity before it is loaded. However, immediately after loading, a specification exception is recognized and a program interruption occurs when any of the following is true for the newly loaded pSW: • A one is introduced into an unassigned bit position of the psw (that is, any of bit positions 0, 2-4, or 24-31). • A zero is introduced into bit position 32 of the PSW, but bits 33-39 are not all zeros. • A zero is introduced into bit position 12 of the psw. In these cases, the operation is completed, and the resulting instruction-length code is zero. PSW Bits 16 and 17 The test for a specification exception after the psw is loaded is described in the section "Early Exception Recognition" in Chapter 6, "Interruptions." It may be considered as occurring early in the process of preparing to execute the subsequent instruction. 00 Contents of control register 1 10 Contents of control register 7 01 The segment-table designation obtained by applying the accessregister-translation (ART) process to the access register designated by the B2 field II Contents of control register 13 The operation is suppressed on all addressing and protection exceptions. The code is set as specified in the new psw loaded. Segment-Table Designation Used by DAT Condition Code: Program Exceptions: • Access (fetch, operand 2) • Privileged operation • Specification OAT is performed without the use of the A zero is translation-lookaside buffer (TLB). appended on the left of the resultant 31-bit real address to produce a 32-bit result, which is then The translated placed in general register R1. address is not inspected for boundary alignment or for addressing or protection exceptions. Load Real Address [RX] LRA 'B1' o I I I RI 8 X2 12 16 ART may be performed with the use of the ART-lookaside buffer (ALB). The virtual-address computation is performed according to the current addressing mode, specified by bit 32 of the current PSW. B2 20 31 The real address corresponding to the secondoperand virtual address is placed in general register Rl. The virtual address specified by the X 2, B2, and 02 fields is translated by means of the dynamicaddress-translation facility, regardless of whether OAT is on or off. DAT is performed by using a segment-table designation that depends on the current value of the address-space-control bits, bits 16 and 17 of the PSW, as shown in the following table: The addresses of the segment-table entry and pagetable entry are treated as 31-bit addresses, regardless of the current addressing mode specified by bit 32 of the current psw. It is unpredictable whether the addresses of these entries are treated as real or absolute addresses. Condition code 0 is set when both ART, if applicable, and DAT can be completed, that is, when a segment-table designation can be obtained and the entry in each OAT table lies within the specified table length and has a zero I bit. When psw bits 16 and 17 are 0 I binary and a segment-table designation cannot be obtained because of a situation that would normally cause one of the exceptions shown in the following table, ( 1) the interruption code assigned to the exception is placed in bit positions 16-31 of general register R1, and bit 0 of this register is set to one and bits 1-15 are set to zeros, and (2) the instruction is completed by setting condition code 3. Chapter 10. Control Instructions 10-25 Exception Name Cause Code (in hex) ALET specification Access-list-entrytoken (ALET) bits 0-6 not zeros 0028 ALEN translation- Access-list entry (ALE) outside list or invalid (bit 0 is one) 0029 ALE sequence ALE sequence number (ALESN) in ALET not equal to ALESN in ALE 002A ASTE validity ASN-second-table entry (ASTE) invalid (bit 0 is one) 002B ASTE sequence ASTE sequence number (ASTESN) in ALE not equal to ASTESN in ASTE 002C Extended authority ALE private bit not zero, ALB authorization index (ALEAX) not equal to extended authorization index (EAX), and secondary bit selected by EAX either outside authority table or zero 002D When ART is completed normally, the operation is continued through the performance of DAT. When the I bit in the segment-table entry is one, condition code I is set, and the real address of the segment-table entry is placed in general register Rl. When the I bit in the page-table entry is one, condition code 2 is set, and the real address of the page-table entry is placed in general register Rl. When either the segment-table entry or the pagetable entry is outside the table, condition code 3 is set, and general register R1 is loaded with the real address of the entry that would have been fetched if the length violation had not occurred. In all these cases, a' zero is appended on the left of the resultant 31-bit real address to produce a 32-bit result, and the 32-bit result is placed in the register. 10-26 ESAj370 Principles of Operation Special Conditions An addressing exception is recognized when the address used by ART to fetch the effective access-list designation or the ALE, ASTE, or authority-table entry designates a location which is not available in the configuration. When it is necessary to access the authority table ,.- when the private bit is not zero and the ALEAX is not equal to the EAX -- an ASN-translation-specification exception is recognized when bits 30, 31, and 60-63 of the ASTE are not all zeros. An addressing exception is recognized when the address used to fetch the segment-table entry or page-table entry designates a location which is not available in the configuration. A translationspecification exception is recognized when bits 8-12 of control register 0 contain an invalid code, or the segment-table entry or page-table entry has a zero I bit and a format error. A carry into bit position 0 as a result of the addition done to compute the address of either the segment-table entry or the page-table entry may be ignored or may result in an addressing exception. The operation is suppressed on all addressing exceptions. Resulting Condition Code: o I 2 3 Translation available Segment-table entry invalid (I bit is one) Page-table entry invalid (I bit is one) Segment-table designation not available or segment- or page-table length exceeded Program Exceptions: • Addressing (effective access-list designation, access-list entry, ASN-second-table entry, authority-table entry, segment-table entry, or page-table entry) • ASN-translation specification • Privileged operation • Translation specification Programming Note: Caution must be exercised in the use of LOAD REAL ADDRESS in a multiprocSince INVALIDATE PAGE essing configuration. TABLE ENTRY may set the I bit in storage to one before causing the corresponding entries in TLBS of other CPUs to be cleared, the simultaneous execution of LOAD REAL ADDRESS on this CPU and INVALIDATE PAGE TABLE ENTRY on another CPU may produce inconsistent results. Because LOAD REAL ADDRESS accesses the tables in storage, the page-table entry may appear to be invalid (condition code 2) even though the corresponding TLB entry has not yet been cleared, and the TLB entry may remain in the TLB until the completion of INVALIDATE PAGE TABLE ENTRY on the other CPU. There is no guaranteed limit to the number of instructions which may occur between the completion of LOAD REAL ADDRESS and the TLB being cleared of the entry. [RRE] MSTA 182471 16 (:) 24 28 31 The contents of the pair of general registers designated by the Rl field are placed in the modifiable area, byte positions 152-159, of the last state entry in the linkage stack. Load Using Real Address LURA Modify Stacked State [RRE] The Rl field designates the even-numbered register of an even-odd pair of general registers. 18248 1 16 (:) 24 28 31 The word at the real-storage location addressed by the contents of general register R2 is placed in general register R 1. Bits 16-23 of the instruction are ignored. In the 24-bit addressing mode, bits 8-31 of general register R2 designate a real-storage location on a word boundary, and bits 0-7 of the register are ignored. In the 31-bit addressing mode, bits 1-31 of general register R2 designate a real-storage location on a word boundary, and bit 0 of the register is ignored. The last state entry is located as described in the section "Unstacking Process" in Chapter 5, "Program Execution." The state entry remains in the linkage stack, and the linkage-stack-entry address in control register 15 remains unchanged. Key-controlled protection does not apply to the references to the linkage stack, but low-address and page protection do apply. Bits 16-23 and 28-31 of the instruction are ignored. Special Conditions A specification exception is recognized when Rl ·is odd. Special Conditions The CPU must be in the primary-space mode, access-register mode, or home-space mode, and the address-space-function control, bit 15 of control register 0, must be one; otherwise, a specialoperation exception is recognized. The contents of general register R2 must designate a location on a word boundary; otherwise, a specification exception is recognized. A stack-empty, stack-specification, or stack-type exception may be recognized during the un stacking process. Condition Code: The code remains unchanged. The operation is suppressed on all addressing and protection exceptions. Because it is a real address, the address designating the storage word is not subject to dynamic address translation. Program Exceptions: • Addressing (address specified by general register R2) • Privileged operation • Protection (fetch, operand 2, key-controlled protection) • Specification The priority of recognition of program exceptions for the instruction is shown in Figure 10-13 on page 10-28. Condition Code: The code remains unchanged. Chapter 10. Control Instructions 10-27 Program Exceptions: • Access (fetch and' store, except for keycontrolled protection, linkage-stack entry) • Special operation • • • • Specification Stack empty Stack specification Stack type 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to the CPU being in the real mode or secondary-space mode or the address-space-function control, bit 15 of control register 0, being zero. 8.A Specification exception due to Rl being odd. 8.B.1 Access exceptions for entry descriptor of the current linkagestack entry. 8.B.2 Stack-type exception due to current entry not being a state entry or header entry. Note: Exceptions 8.B.3-8.B.7 can occur only if the current entry ;s a header entry. 8.B.3 Access exceptions for second word of the header entry. 8.B.4 Stack-empty exception due to backward stack-entry validity bit in the header entry being zero. 8.B.5 Access exceptions for entry descriptor of preceding entry, which is the entry designated by the backward stack-entry address in the current (header) entry. 8.B.6 Stack-specification exception due to preceding entry being a header entry. 8.B.7 Stack-type exception due to preceding entry not being a state entry. 8.B.8 Access exceptions for the modifiable area of the state entry. Figure 10-13. Priority of Execution: MODIFY STACKED STATE 10-28 ESA/370 Principles of Operation Move to Primary [SS] IDAI o I R. I R. I B. I &~&~ / /~ 8 12 16 20 32 36 47 Bit positions 24-27 of general register R3 are used as the secondary-space access key. Bit positions 0-23 and 28-31 of the register are ignored. The contents of general register Rl are a 32-bit unsigned value called the true length. The contents of the general registers just described are as follows: Move to Secondary True Length [SS] lOBI o I R·I R. I B. I &~&~ / / 8 12 16 20 32 36 47 o 31 R3 o The frrst operand is replaced by the second operand. One operand is in the primary address space, and the other is in the secondary address space. The accesses to the operand in the primary space are perfonned by using the psw key; the accesses to the operand in the secondary space are performed by using the key specified by the third operand. The addresses of the frrst and second operands are virtual, one operand address being translated by means of the primary segment-table designation and the other by means of the secondary segmenttable designation. Operand-address translation is performed in the same way when the address-spacecontrol bits in the current psw specify either the primary-space mode or the secondary-space mode. For MOVE TO PRIMARY, movement is to the primary space from the secondary space. The frrstoperand address is translated by using the primary segment table, and the second-operand address is translated by using the secondary segment table. For MOVE TO SECONDARY, movement is to the secondary space from the primary space. The frrstoperand address is translated by using the secondary segment table, and the .second-operand address is translated by using the primary segment table. 24 28 31 The frrst and second operands are the same length, called the effective length. The effective length is equal to the true length, or 256, whichever is less. Access exceptions for the frrst and second operands are recognized only for that portion of the operand within the effective length. When the effective length is zero, no access exceptions are recognized for the frrst and second operands, and no movement takes place. Each storage operand is processed left to right. The storage-operand-consistency rules are the same as for MOVE (MVC), except that when the operands overlap in real storage, the use of the common realstorage locations is not necessarily recognized. As part of the execution of the instruction, the value of the true length is used to set the condition code. If the true length is 256 or less, including zero, the true length and effective length are equal, and condition code 0 is set. If the true length is greater than 256, the effective length is 256, and condition code 3 is set. For both and MOVE TO SECa serialization and checkpointsynchronization function is performed before the operation begins and again after the operation is completed. MOVE TO PRIMARY ONDARY, Chapter 10. Control Instructions 10-29 Special Conditions 1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. Since the secondary space is accessed, the operation is performed only when the secondary-space control, bit 5 of control register 0, is one and OAT is on. When either the secondary-space control is zero or OAT is off, a special-operation exception is recognized. A special-operation exception is also recognized when the address-space-control bits in the current psw specify the access-register or homespace mode. The special-operation exceptions are recognized in both the problem and supervisor states. In the problem state, the operation is performed only if the secondary-space access key is valid, that is, if the corresponding psw-key-mask bit in control register 3 is one. Otherwise, a privileged-operation exception is recognized. In the supervisor state, any value for the secondary-space access key is valid. 7.A Access exceptions for second and third instruction halfwords. 7.B Special-operation exception due to the secondary-space control, bit 5 of control register 0, being zero, to OAT being off, or to the CPU being in the access-register or home-space mode. 8. Privileged-operation exception due to selected PSW-key-mask bit being zero in the problem state. 9. Completion due to length zero. 10. Access exceptions for operands. The priority of the recognition of exceptions and condition codes is shown in Figure 10-14. Figure 10-14. Priority of Execution: MOVE TO PRIMARY and MOVE TO SECONDARY Resulting Condition Code: Programming Notes: o True length less than or equal to 256 1 2 3 True length greater than 256 Program Exceptions: • Access (fetch, primary virtual address, operand 2, MVCS; fetch, secondary virtual address, operand 2, MVCP; store, secondary virtual address, operand I, MVCS; store, primary virtual address, operand 1, MVCP) • Privileged operation (selected psw-key-mask bit is zero in the problem state) • Special operation 1. MOVE TO PRIMARY and MOVE TO SECONDARY can be used in a loop to move a variable number of bytes of any length. See the programming note under MOVE WITH KEY. 2. MOVE TO PRIMARY and MOVE TO SECONDARY should be used only when movement is between different address spaces. The performance of these instructions on most models may be significantly slower than that of MOVE WITH KEY, MOVE (MVC), or MOVE LONG. In addition, the defInition of overlapping operands for MOVE TO PRIMARY and MOVE TO SECONDARY is not compatible with the more precise definitions for MOVE (MVC), MOVE WITH KEY, and MOVE LONG. Move with Destination Key MVCOK 01 (B1) ,02 (B2) [SSE] ~__I_E5_0F_I__~I_Bl~I~~~~ o 16 20 32 36 47 The frrst operand is replaced by the second operand. The accesses to the destination-operand 10-30 ESA/370 Principles of Operation location are performed by using the key specified in general register 1, and the accesses to the sourceoperand location are performed by using the psw key. The frrst and second operands are of the same length, which is specified by bits 24-31 of general register O. Bits 0-23 of general register 0 are ignored. Bits 24-27 of general register 1 are used as the specified access key. Bits 0-23 and 28-31 of general register 1 are ignored. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2; store, operand 1) • Operation (if the move-with-source-ordestination-key facility is not installed) • Privileged operation (selected psw-key-mask bit is zero in the problem state) Programming Note: See the programming notes for the MOVE WITH SOURCE KEY instruction. Move with Key The contents of general registers 0 and 1 are as follows: GR0 1////////////////////////11 o o 24 31 28 ~H~~ I_ ,---' D9_'..1--1R---..I' L 24 [55] 31 L specifies the number of bytes to the right of the frrst byte of each operand. Therefore, the length in bytes of each operand is 1-256, corresponding to a length code in L of 0-255. The fetch accesses to the second-operand location are performed by using the psw key, and the store accesses to the first-operand location are performed by using the key specified in general register 1. Each of the operands is processed left to right. When the operands overlap in real storage, the results in the frrst-operand location are unpredictable. Except for this unpredictability in the case of overlap, the storage-operand-consistency rules are the same as for the MOVE (MVC) instruction. o 8 12 R3 ----l-I_B1--1..-1 16 20 32 36 47 The frrst operand is replaced by the second operand. The fetch accesses to the second-operand location are performed by using the key specified in the third operand, and the store accesses to the frrst-operand location are performed by using the pswkey. Bit positions 24-27 of general register R3 are used as the source access key. Bit positions 0-23 and 28-31 of the register are ignored. The contents of general register Rl are a 32-bit unsigned value called the true length. The contents of the general registers just described are as follows: Rl True Length o 31 Special Conditions R3 In the problem state, the operation is performed only if the access key specified in general register I is valid, that is, if the corresponding psw-key~mask bit in control register 3 is one. Otherwise, a privileged-operation exception is recognized. In the supervisor state, any value for the specified access key is valid. o 24 28 31 The frrst and second operands are the same length, called the effective length. The effective length is equal to the true length, or 256, whichever is less. Access exceptions for the first and second operands are recognized only for that portion of the operand Chapter 10. Control Instructions 10-31 within the effective length. When the effective length is zero, no access exceptions are recognized for the frrst and second operands, and no movement takes place. 1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. Each storage operand is processed left to right. When the storage operands overlap, the result is obtained as if the operands were processed one byte at a time and each result byte were stored immediately after the necessary operand byte was fetched. The storage-operand-consistency rules are the same as for the MOVE (MVC) instruction. As part of the execution of the instruction, the value of the true length is used to set the condition code. If the true length is 256 or less, including zero, the true length and effective length are equal, and condition code 0 is set. If the true length is greater than 256, the effective length is 256, and condition code 3 is set. 7.A Access exceptions for second and third instruction halfwords. 8. Privileged-operation exception due to selected PSW-key-mask bit being zero in the problem state. 9. Completion due to length zero. 10. Access exceptions for operands. Figure 10-15. Priority of Execution: KEY MOVE WITH Programming Notes: 1. MOVE WITH KEY can be used in a loop to Special Conditions move a variable number of bytes of any length, as follows: In the problem state, the operation is performed only if the source access key is valid, that is, if the corresponding psw-key-mask bit in control register 3 is one. Otherwise, a privileged-operation exception is recognized. In the supervisor state, any value for the source access key is valid. The priority of the recognition of exceptions and condition codes is shown in Figure 10-15. Resulting Condition Code: o True length less than or equal to 256 1 2 3 LOOP LA MVCK BC AR AR SR B RW,256 Dl(Rl,Bl},D2(B2},R3 8,END Bl,RW B2,RW Rl,RW ) LOOP END 2. The performance of MOVE WITH KEY on most models may be significantly slower than that of the MOVE (MVC) and MOVE LONG instructions. Therefore, MOVE WITH KEY should not ~.e used if the keys of the source and the target are the same. True length greater than 256 Program Exceptions: • Access (fetch, operand 2; store, operand 1) • Privileged operation (selected psw-key-mask bit is zero in the problem state) Move with Source Key MVCSK ~__I_E5_0_EI__~_B_l~I~~~~~ o 16 20 32 36 47 The frrst operand is replaced by the second operand. The accesses to the source-operand location are performed by using the key specified in general register 1, and the accesses to the destination-operand location are performed by using the psw key. 10-32 ESA/370 Principles of Operation The fIrst and second operands are of the same length, which is specified by bits 24-31 of general register o. Bits 0-23 of general register 0 are ignored. Bits 24-27 of general register 1 are used as the specified access key. Bits 0-23 and 28-31 of general register 1 are ignored. The contents of general registers 0 and 1 are as follows: GRB 1/////////////////////////1 24 24 L 31 Program Exceptions: • Access (fetch, operand 2; store, operand 1) • Operation (if the move-with-source-ordestination-key facility is not installed) • Privileged operation (selected psw-key-mask bit is zero in the problem state) Programming Notes: 1. When data is to be moved alternately in both directions between two storage areas that are fetch protected by means of different keys, then MOVE WITH SOURCE KEY and MOVE WITH DESTINATION KEY can be used while leaving the psw key unchanged; and this may be, on most models, significantly faster than using MOVE WITH KEY along with SET PSW KEY FROM ADDRESS to change the psw key. 2. MOVE WITH SOURCE KEY TINATION KEY should 3. MOVE WITH SOURCE KEY or MOVE WITH DESTINATION KEY can be used in a loop to move a 28 31 L specifies the number of bytes to the right of the fIrst byte of each operand. Therefore, the length in bytes of each operand is 1-256, corresponding to a length code in L of 0-255. The fetch accesses to the second-operand location are performed by using the key specified in general register I, and the store accesses to the fIrst-operand location are performed by using the psw key. Each of the operands is processed left to right. When the operands overlap in real storage, the results in the fIrst-operand location are unpredictable. Except for this unpredictability in the case of overlap, the storage-operand-consistency rules are the same as for the MOVE (MVC) instruction. and MOVE WITH DESbe used only when movement is between storage areas having different keys. The performance of these instructions on most models may be significantly slower than that of the MOVE (MVC) instruction. variable number of bytes as shown in the following example. In the example, the specified access key, the fIrst-operand address, the second-operand address, and the length of each operand are assumed to be in general registers 1-4, respectively, at the beginning of the example. The length of each operand is treated as a 32-bit signed value, and a negative value is treated as zero. Special Conditions In the problem state, the operation is performed only if the access key specified in general register 1 is valid, that is, if the corresponding psw-key-mask bit in control register 3 is one. Otherwise, a privileged-operation exception is recognized. In the supervisor state, any value for the specified access LOOP key is valid. END LAST LTR BC 4,4 S 4,=F'256 1 BC LA MVCSK LA LA 12,LAST 12,END O,255 O(2),O(3) 2,256(2) 3,256(3) 4,=F'256 1 S BC 2,LOOP LA 0,255( 4) MVCSK O(2) ,O(3) Condition Code: The code remains unchanged. Chapter 10. Control Instructions 10-33 Stacking PROGRAM CALL optionally replaces the psw key in the psw and the· EAX in control register 8 from the ETE, and it sets the address-spacecontrol bits in the psw, as determined by control bits in the ETE. Program Call [S] 'B218 1 o 16 20 ,31 A program-call number specified .by the secondoperand address is used in a two-level lookup to When the locate an entry-table entry (ETE). address-space-function (AS F) control, bit 15 of control register 0, is zero, a 16-byte ETE is located; otherwise, when the ASF control is one, a 32-byte ETE is located. The program is authorized to use the ETE when the AND of the psw-key mask in control register 3 and the authorization key mask in the ETE is. nonzero or when the CPU is in the supervisor state. When a l6-byte ETE is located, or when a 32-byte ETE is located but the pc-type bit, bit 128 of the ETE, is zero, an operation called basic PROGRAM CALL is performed. When a 32-byte ETE is located and the pc-type bit is one, an operation called stacking PROGRAM CALL is performed. Basic PROGRAM CALL loads the addressing-mode bit, updated instruction address, and problem-state bit from the psw into general register 14, and it places the psw-key mask and PASN in general register 3. Stacking PROGRAM CALL places the entire psw contents, except with an unpredictable PER mask, and also the psw-key mask, PASN, SASN, and EAX in a linkage-stack program-call state entry that it forms. The program-call number and the contents of general registers 0-15 and access registers 0-15 also are placed in the state entry. Basic and stacking PROGRAM CALL both replace the addressing-mode bit, instruction address, and problem-state bit in the psw from the ETE, and. both load the entry parameter from' the ETE into general register 4. Basic PROGRAM CALL ORs the entry key mask from the ETE into the psw-key mask in control register 3. Stacking PROGRAM CALL does the same, or it replaces the psw-key mask with the entry key mask, as determined by the psw-key-mask control in the ETE. 10-34 ESAj370 Principles of Operation The ETE causes a space-switching operation to occur if it contains a nonzero ASN. When the ETE contains a zero ASN, the operation is. called PROGRAM CALL to current primary (pc-cp);when the ETE contains a nonzero ASN, the operation is called PROGRAM CALL with space switching (pc-ss). When space switching is specified, the new PASN is loaded into control register 4 from the ErE and is used in a two-level lookup to locate an. ASN-second-table entry (ASTE). However, when the ASF control is one, the address of the ASTE may be obtained directly from the ETE. From this ASTE, a new PSTD and AX are loaded into control registers 1 and 4, respectively. When the ASF control is zero, a new LTD is loaded into control register 5 from the ASTE. When the ASF control is one, bits 1-25 of the address of the ASTE are loaded into control register 5 as the new primary-AsTE origin. In both Pc-cp and Pc-ss, the SASN and SSTD are set equal to the original PASN and PSTD, respectively. However, the space-switching stacking PROGRAM CALL operation may set the SASN and SSTD equal to the new PAS N and PSTD, respectively, as determined by a control bit in the ETE. PROGRAM CALL PC-Number Translation The second-operand address is not used to· address data; instead, the rightmost 20 bits of the address are used as a PC number and have the following format: Second-Operand Address ,...----pc Number----. 111//////////1 o EX LX 12 24 31 Bits 12-23 of the secondoperand address are the linkage index and are used to select an entry from the linkage table designated by the linkage-table designation. When the ASF control, bit 15 of control register 0, is zero, the linkage-table designation is in .control register 5. When the ASF control is one, the linkage-table desLinkage Index (LX): ignation is in the primary ASN-second-table entry (primary ASTB), and the primary-ASTB origin is in control register 5. Bits 24-31 of the secondoperand address are the entry index and are used to select an entry from the entry table designated by the linkage-table entry. Entry Index (EX): Bits 0-11 of the second-operand address are ignored. The linkage-table and entry-table lookup process is depicted in part 1 of Figure 10-17 on page 10-40. The detailed defmition of this table-lookup process is in the section "pc-Number Translation" in Chapter 5, "Program Execution." The 16-byte entry-table entry (ETB) is identical to the fust 16 bytes of the 32-byte BTB. The 32-byte BTH has the following format: AKM o H ASN 16 EIA 32 Entry Parameter 64 63 144 160 192 If the result of the AND of the AKM and the psw-key mask is not zero, or if the CPU is in the supervisor state, the execution of the instruction continues. If a 16-byte ETE has been fetched, or if a 32-byte BTE has been fetched but bit 128 of the ETE (T) is zero, the basic PROGRAM CALL operation is specified. If a 32-byte ETE has been fetched and bit 128 of the ETE is one, the stacking PROGRAM CALL operation is specified. 127 Bits 32-62 of the current psw (the addressing-mode bit and the updated instruction address) are placed in bit positions 0-30 of general register 14. Bit 15 of the psw (the problem-state bit) is placed in bit position 31 of general register 14. 186 191 Bits 32-62 of the ETE (A and the EIA), with a zero appended on the right, are placed in psw bit positions 32-63 (the addressing-mode bit and the instruction address). Bit 63 of the ETE (p) is placed in psw bit position 15 (the problem-state bit). 112 ICntrl/EKI EEAX 128 Mter the ETE has been fetched, if the current psw specifies the problem state, the current psw-key mask in control register 3 is tested against the AKM field in the ETE to determine whether the program is authorized to access this entry. The AKM and psw-key mask are AN oed, and if the result is zero, a privileged-operation exception is recognized. The psw-key mask in control register 3 remains unchanged. When PROGRAM CALL is executed in the supervisor state, the AKM field is ignored. Basic PROGRAM CALL: The following operations are performed when basic PROGRAM CALL is specified. EKM 96 otherwise, a pc-translation-specification exception is recognized. 255 Bits 128-143 of the HTH have the following detailed format: The psw-key mask, bits 0-15 of control register 3, is placed in bit positions 0-15 of general register 3, and the current PASN, bits 16-31 of control register 4, is placed in bit positions 16-31 of general register 3. 128 131 136 143 When bit 32 of the HTH is zero (24-bit addressing mode), then bits 33-39 of the HTH must be zeros; Bits 96-111 of the ETE (the EKM) are oRed with the psw-key mask, bits 0-15 of control register 3, and the result replaces the psw-key mask in control register 3. Bits 64-95 of the ETE (the entry parameter) are loaded into general register 4. Chapter 10. Control Instructions 10-35 Stacking PROGRAM CALL: The following opera- tions are perfonned when stacking PROGRAM CALL is specified. The stacking process is perfonned to fonn a linkage-stack program-call state entry and place the following infonnation in the state entry: current psw (with an unpredictable PER mask), psw-key mask, PASN, SASN, EAX, program-call number, contents of general registers 0-15, and contents of access registers 0-15. This is described in the section "Stacking Process" in Chapter 5, "Program Execution." The entry-type code in the state· entry is 0000101 binary. Bits 32-62 of the ETE (A and the EIA), with a zero appended on the right, are placed in psw bit positions 32-63 (the addressing-mode bit and the instruction address). Bit 63 of the ETE (p) is placed in psw bit position 15 (the problem-state bit). When bit 131 of the ETE (K) is zero, bits 8-11 of the psw (the psw key) remain unchanged. When bit 131 of the ETE is one, bits 136-139 of the ETE (the EK) replace the psw key in the psw. When bit 132 of the ETE (M) is zero, bits 96-111 of the ETE (the EKM) are oRed with the psw-key mask, bits 0-15 of control register 3, and the result replaces the psw-key mask in control register 3. When bit 132 of the ETE is one, bits 96-111 of the ETE replace the psw-key mask in control register 3. When bit 133 of the ETE (E) is zero, the EAX, bits 0-15 of control register 8, remains unchanged. When bit 133 of the ETE is one, bits 144-159 of the ETE (the EEAX) replace the EAX in control register PROGRAM CALL to Current Primary (PC-cp) If bits 16-31 of the ETE (the ASN) are zeros, PROGRAM CALL to current primary (pc-cp) is specified, and the execution of the instruction is completed after the operations described above and the following operations have been perfonned. The current PASN, bits 16-31 of control register 4, is placed in bit positions 16-31 of control register 3 to become the current SASN. The current PSTD, bits 0-31 of control register 1, is placed in control register 7 to become the current SSTD. The basic pc-cp operation is depicted in parts 1 The and 2 of Figure 10-17 on page 10-40. stacking pc-cp operation is depicted in parts 1 and 3 of the figure. PROGRAM CALL with Space Switching (PC-ss) If the ASN in the ETE is nonzero, PROGRAM CALL with space switching (pc-ss) is specified, and the execution of the instruction is completed after the "PROG RAM CALL operations described in pc-Number Translation" and the following operations have been perfonned. When the ASP control is zero, the ASN in the ETE is translated by means of a two-level table lookup to locate an ASN-second-table entry (ASTE). Otherwise, when the ASP control is one, the ASTE may be located either by means of ASN translation or by means of obtaining its address directly from the ETE, and which of these occurs is unpredictable. 8. When bit 134 of the ETE (c) is zero, bits 16 and 17 of the psw (the address-space-control bits) are set to 00 binary (primary-space mode). When bit 134 of the ETE is one, the address-space-control bits in the psw are set to 01 binary (access-register mode). Bits 64-95 of the ETE (the entry parameter) are loaded into general register 4. Key-controlled protection does not apply to references to the linkage stack, but low-address and page protection do apply. 10-36 ESA/370 Principles of Operation When ASN translation occurs, bits 16-25 of the ETE are used as a 10-bit APX to index into the ASN fust table, and bits 26-31 are used as a 6-bit ASX to index into the ASN second table specified by the APX. The ASN table-lookup process is described in the section "ASN Translation" in Chapter 3, "Storage." The exceptions associated with ASN translation are collectively called ASN-translation exceptions. These exceptions and their priority are described in Chapter 6, "Interruptions." When ASN translation does not occur, bits 161-185 of the ETE, with six zeros appended on the right, are used as the real address of the ASTE. An Asx-trans1ation exception is recognized if bit 0 of the ASTE is one, or an ASN-translation-specification exception is recognized if any of bits 30, 31, and 60-63 of the ASTE is one. (These exceptions are a subset of the ASN-translation exceptions.) Bits 16-31 of the ETE (the ASN) are placed in bit positions 16-31 of control register 4 as the new PASN. Bits 64-95 of the ASTE (the STD) are placed in control register 1 as the new PSTD. Bits 32-47 of the ASTE (the AX) are placed in bit positions 0-15 of control register 4 as the new authorization index. When the ASF control is zero, bits 96-127 of the ASTE (the LTD) are placed in control register 5 as the new linkage-table designation. When the ASF control is one, bits 1-25 of the ASTE address are placed in bit positions 1-25 of control register 5 as the new primary-ASTE origin, and zeros are placed in bit positions 0 and 26-31. In basic PROGRAM CALL, or in stacking PROGRAM CALL when bit 135 of the ETE (s) is zero, the PASN existing before the PASN is replaced from the ETE is placed in bit positions 16-31 of control register 3 to become the current SASN, and the PSTD existing before the PSTD is replaced from the ASTE is placed in control register 7 to become the current SSTD. (The SASN and SSTD are set equal to the old PASN and PSTD, respectively.) PROGRAM CALL can be performed successfully only when the CPU is in the primary-space mode or access-register mode at the beginning of the operation and the subsystem-linkage control is one. In addition, pC-ss can be performed successfully only when the ASN-translation control, bit 12 of control register 14, is one. If any of these rules is violated, a special-operation exception is recognized in both the problem and supervisor states. A stack-full or stack-specification exception may be recognized during the stacking process. When, for Pc-ss, the primary space-switch-eventcontrol bit, bit 0 of control register 1, is one either before or after the execution of the instruction, a space-switch-event program interruption occurs after the operation is completed. A space-switchevent program interruption also occurs after the completion of a pc-ss operation if a PER event is reported. The operation is suppressed on all addressing and protection exceptions. The priority of recognition of program exceptions for the instruction is shown in Figure 10-16 on page 10-38. Condition Code: The code remains unchanged. Program Exceptions: In stacking PROGRAM CALL when bit 135 of the ETE (s) is one, the SASN is replaced by the PASN after the PASN is replaced from the ETE, and the SSTD is replaced by the PSTD after the PSTD is replaced from the ASTE. (The SASN and SSTD are set equal to the new PASN and PSTD, respectively.) The pc-ss operation is depicted in parts 1, 2, 3, and 4 of Figure 10-17 on page 10-40. PROGRAM CALL Serialization For both the pc-cp and pc-ss operations, a serialization and checkpoint-synchronization function is performed before the operation begins and again after the operation is completed. Special Conditions The basic PROGRAM CALL operation can be performed successfully only when the CPU is in the primary-space mode at the beginning of the operation and the subsystem-linkage control, bit 0 of the linkage-table designation, is one. Stacking • Access (fetch or store, except for key-controlled protection, linkage-stack entry) • Addressing (linkage-table designation in primary ASN-second-table entry, only when address-space-function control is one; linkagetable entry; entry-table entry; ASN-frrst-table entry, pc-ss only, and only when ASN translation occurs; ASN-second-table entry, pc-ss only) • AFX translation (pc-ss only, and only when ASN translation occurs) • ASN -translation specification (pc-ss only) • ASX translation (pc-ss only) • EX translation • LX translation • pc-translation specification • Privileged operation (AND of AKM and psw-key mask is zero in the problem state) • Space-switch event (pc-ss only) • Special operation • Stack full (stacking PC only) • Stack specification (stacking PC only) • Trace Chapter 10. Control Instructions 10-37 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to the CPU being in real mode, secondary-space mode, or home-space mode. 7.C Special-operation exception due to the CPU being in accessregister mode (only when address-space-function control is zero, and may be recognized instead at 8.B.2). 7.0 Special-operation exception due to subsystem-linkage control in linkage-table designation in control register 5 being zero (only when address-space-function control is zero). 8.A Trace exceptions. 8.B.1 Addressing exception for access to linkage-table designation in primary ASN-second-table entry (only when address-spacefunction control is one). 8.B.2 Special-operation exception due to subsystem-linkage control in linkage.-table designation in primary ASN-second-table entry being zero (only when address-space-function control is one). 8.B.3 LX-translation exception due to linkage-table entry being outside table. 8.B.4 Addressing exception for access to linkage-table entry. 8.B.5 LX-translation exception due to I bit (bit e) in linkage-table entry being one. 8.B.6 EX-translation exception due to entry-table entry being outside table. 8.B.7 Addressing exception for access to entry-table entry. 8.B.8 Special-operation exception due to the CPU being in accessregister mode (basic PC only, and may be recognized at 7.C if address-space-function control is zero). 8.B.9 PC-translation-specification exception due to invalid combination (bit 32 is zero and bits 33-39 not zeros) in entry-table entry. 8.B.1e Privileged-operation exception due to zero result from ANDing PSW-key mask and AKM in the problem state. 8.B.11 Special-operation exception due to ASN-translation control, bit 12 of control register 14, being zero (PC-ss only). Figure 10-16 (Part 1 of 2). Priority of Execution: PROGRAM CALL 10-38 ESA/370 Principles of Operation 8.B.12 Addressing exception for access to ASN-first-table entry (PC-ss only, and only when ASN translation occurs). 8.B.13 AFX-translation exception due to I bit (bit 0) in ASN-firsttable entry being one (PC-ss only, and only when ASN translation occurs). 8.B.14 ASN-translation-specification exception due to invalid ones (bits 28-31 or 26-31, depending on address-space-function control) in ASN-first-table entry (PC-ss only). 8.B.15 Addressing exception for access to ASN-second-table entry (PC-ss only). 8.B.16 ASX-translation exception due to I bit (bit 0) in ASN-secondtable entry being one (PC-ss only). 8.B.17 ASN-translation-specification exception due to invalid ones (bits 30, 31, 60-63) in ASN-second-table entry (PC-ss only). 8.B.18 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry (stacking PC only). Note: Exceptions 8.B.19-8.B.24 can occur only if there is not enough remaining free space in the current linkage-stack section. 8.B.19 Stack-specification exception due to remaining-free-space value in current linkage-stack entry not being a multiple of 8. 8.B.20 Access exceptions (fetch) for second word of the trailer entry of the current section. The entry is presumed to be a trailer entry; its entry-type field is not examined (stacking PC only). 8.B.21 Stack-full exception due to forward-section validity bit in the trailer entry being zero (stacking PC only). 8.B.22 Access exceptions (fetch) for entry descriptor of the header entry of the next section (stacking PC only). This entry is presumed to be a header entry; its entry-type field is not examined. 8.B.23 Stack-specification exception due to not enough remaining free space in the next section (stacking PC only). 8.B.24 Access exceptions (store) for second word of the header entry of the next section. If there is no exception, the header is now called the current entry. 8.B.25 Access exceptions (store) for entry descriptor of the current entry and for the new state entry (stacking PC only). 9. Space-switch event (PC-ss only). Figure 10-16 (Part 2 of 2). Priority of Execution: PROGRAM CALL Chapter 10. Control Instructions t 0-39 PC-Number Translation PROGRAM CALL Instruction CR5 if CRe.15 =e 'B218' H d. I '::nd-2 ! ~~~~~ss Primary-ASTE bits 96-127 if CRe.15 = 1 (x16 if CRe.15 = e) (x32 if CRe.15 = 1) ~ Linkage Table R I ETO ETL (x64) ~ Entry Table R EIA EP ASTE Adr. R: Address is real In stacking PC, PC number is placed in linkage stack Second 16 bytes of ETE exist only if CRe.15 = I *: **: Figure 10-17 (Part 1 of 4). Execution of PROGRAM CALL 10-40 ESA/370 Principles of Operation ** Basic PC-cp and PC-ss Entry-Table Entry a ~ lei , GR4 afterl , I EP Q-priv Op ~if zero in ~ problem state ~ before ~ CR3 CR4 before AX I \ I PASN I \ r~\~~N/~~ .+'41---'. PC-cp instruction complete \_1 PC-ss ASN translation +r-----.'--------------~ CR3 GR3 CRI before .----r------, afterl PKM SASN CR7 after .----r------, afterl PKM PASN PSTD r---------, SS_T_D_---' L - I_ _ PSW before GR14 ,...."T'----r--. afterlAI IA Figure 10-17 (Part 2 of 4). Execution of PROGRAM CALL Chapter 10. Control Instructions 10-41 Stacking PC-cp and PC-ss Entry-Table Entry E=1 K=1 o ~ EAX CRa after GR4 ~ ~ r-------, afterlL-_ _ EP_--, LS CRa before Q--.Priv Op ~if zero in problem state CR4 before PC-cp instruction complete • M=0 I PSW PC-cp, or Stkg. PC-ss and S=0 * ~LS CR7 r-------, SSTD If stacking PC-ss and S=1, SASN is replaced by new PASN, and SSTD is replaced by new PSTD Figure 10-17 (Part 3 of 4). Execution of PROGRAM CALL 10-42 \_1 CR1 before '---__PS...,T_D_--' SASN afterl *: \ PC-cp, or Stkg. PC-ss and S=0 * CR3 after PKM I I\ ~~\~~N/~~ 1 PSW before I LS ESA/370 Principles of Operation PC-ss ASN translation ASN Translation for PC-ss Entry-Table Entry ASN AKH EIA IAI L - -_ _l...--T-----lL-.l.-._ _ _ _ Ipl -l.-~ }m Adr·l~l E_P_ _-,--_EK_H--LI __ ~--~ ! CR14 (x4) (xl6 1f eRa. IS (x64 if CRa.lS • 1) • a) ~ ASN First Table I R ASTO 9 * ~ ASN Second Table -.+ ." R--' 1/ ATO lei AX STD / All /a/ LTD / ** -- L.... .- CRI afterL • PSTD I CR4 after [ 1 1---I PASN -] AX CRe.lS = a ~ CR5 afte~1 '-------------------------. CRe.IS • 1 LTD ~ or. P~ R: Address is real *: If CRa.IS • 1, ASTE address may be obtained by ASN translation or directly from ETE **: ASTE is 64 bytes if and CRe.IS • 1; last 48 bytes are not shown Figure 10-17 (Part 4 of 4). Execution of PROGRAM CALL Chapter 10. Control Instructions 10-43 Programming Note: To ensure predictable operation of pc-ss when the address-space-function control is one, the ASN-second-table-entry address in the entry-table entry must be the same as the one that would result from ASN translation of the ASN in the entry-table entry. PR-SS. The terms PR-CP and PR-SS do not apply when the state entry is a branch state entry. Program Return The sections "PASN Translation," "SASN Translation," "SASN Authorization," and "PROGRAM RETURN Serialization" apply only when the unstacked state entry is a program-call state entry. The functions described in those sections are not performed when the state entry is a branch state entry. PR [E] '0101' o 15 P ASN Translation The PSW, except for the PER-mask bit and the condition code, saved in the last linkage-stack state entry is restored as the current psw. The PER mask in the current psw remains unchanged. The resulting value of the condition code in the current psw is unpredictable. The contents of general registers 2-14 and access registers 2-14 also are restored from the state entry. When the entry-type code in the entry descriptor of the state entry is 0000101 binary, indicating a program-call state entry, the primary ASN (PASN), secondary ASN (SASN), psw-key mask (PKM), and extended authorization index (EAX) in the control registers also are restored from the state entry. When the entry-type code is 0000100 binary, indicating a branch state entry, the current PASN, SASN, PKM, and EAX remain unchanged. The last state entry is located, and information in it is restored, as described in the section "Unstacking Process" in Chapter 5, "Program Execution." The state entry is logically deleted from the linkage stack, and the linkage-stack-entry address in control register 15 is replaced by the address of the next preceding state or header entry. This also 1S described in the section "Unstacking Process." When the state entry is a program-call state entry, it causes a space-switching operation to occur if it contains a PASN that is not equal to the current PASN. When the state entry contains a PASN that is equal to the current PASN, the operation is called PROGRAM RETURN to current primary (PR-Cp); when the state entry contains a PASN that is not equal to the current PASN, the operation is called PROGRAM RETURN with space switching (PR-SS). PASN translation occurs in PR-sS. SASN translation and authorization may occur in either PR-CP or I 10-44 Key-controlled protection does not apply to accesses to the linkage stack, but low-address and page protection do apply. ESAj370 Principles of Operation If the new PASN is equal to the old PASN in bits 16-31 of control register 4, PASN translation is not performed, and the authorization index (AX), PASN, PSTD, and . primary-AsN-second-table-entry (primary-AsTE) origin in the control registers are not changed. If the new PASN is not equal to the old PASN, the new PASN is translated to locate a 64-byte ASTE. The ASN table-lookup process is described in the section "ASN Translation" in Chapter 3, "Storage." The exceptions associated with ASN translation are collectively called ASN-translation exceptions. These exceptions and their priority are described in Chapter 6, "Interruptions." Bits 64-95 of the ASTE are placed in control register 1 as the new PSTD. Bits 32-47 of the ASTE are placed in bit positions 0-15 of control register 4 as the new AX. Bits 1-25 of the ASTE address are placed in bit positions 1-25 of control register 5 as the new primary-AsTE origin, and zeros are placed in bit positions 0 and 26-31. SASN Translation If the new SASN is equal to the new PASN, the SSTD in control register 7 is set equal to the new PSTD in control register 1. If the new SASN is not equal to the new PASN, the new SASN is translated to locate a 64-byte ASTE. Bits 64-95 of the ASTE are placed in bit positions 0-31 of control register 7 as the new SSTD. SASN Authorization If the new SASN is not equal to the new PASN, the authority-table origin (ATO) from the ASTE for the new SASN is used as the base for a third table lookup. The new authorization index, bits 0-15 of control register 4, is used, after it has been checked against the authority-table length, as the index to locate the entry in the authority table. The authority-table lookup is described in the section "ASN Authorization" in Chapter 3, "Storage." PROGRAM RETURN Serialization A serialization and checkpoint-synchronization function is performed before the operation begins and again after the operation is completed (only when the un stacked state entry is a program-call state entry). Special Conditions The instruction can be executed successfully only when the CPU is in the primary-space mode or access-register mode at the beginning of the operation and the address-space-function control, bit 15 of control register 0, is one. In addition, the ASN -translation process can be performed, for either the PASN or the SASN, only when the ASN-translation control, bit 12 of control register 14, is one. If any of these rules is violated, a special-operation exception is recognized. A stack-empty, stack-operation, stack-specification, or stack-type exception may be recognized during the un stacking process. When, for PR-SS, the primary space-switch-event control, bit 0 of control register 1, is one either before or after the execution of the instruction, a space-switch-event program interruption occurs after the operation is completed. A space-switchevent program interruption also occurs after the completion of a PR-ss operation if a PER event is reported. The psw which is to be loaded by the instruction is not checked for validity before it is loaded. However, after loading, a specification exception is recognized, and a program interruption occurs, when the newly loaded psw contains a zero in bit position 12, or when the contents of bit positions 0, 2-4, and 24-31 are not all zeros, or when bit position 32 contains a zero and the contents of bit positions 33-39 are not all zeros. In these cases, the operation is completed, and the resulting instruction-length code is zero. The specification exception, which in this case is listed as a program exception in this instruction, is described in the section "Early Exception Recognition" in Chapter 6, "Interruptions." It may be considered as occurring early in the process of preparing to execute the following instruction. The operation is suppressed on all addressing and protection exceptions. The priority of recognition of program exceptions for the instruction is shown in Figure 10-18 on page 10-46. Resulting Condition Code: The code is unpredict- able. Program Exceptions: • Access (fetch and store, except key-controlled protection, linkage-stack entry) • Addressing (authority-table entry, if SASN translation occurs) • ASN translation (if PASN or SASN translation occurs) • Secondary authority (if SASN translation occurs) • Space-switch event • Special operation • Specification • Stack empty • Stack operation • Stack specification • Stack type • Trace Chapter 10. Control Instructions 10-45 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7. Special-operation exception due to the CPU'being in real mode, secondary-space mode, or home-space mode or the address-space-function control, bit 15 of control register 0, being zero. 8.A Trace exceptions. 8.B.1 Access exceptions (fetch) for entry descriptor of the current linkage-stack entry. Note: Exceptions 8.B.2-8.B.6 can occur only if the current entry is a header entry. 8.B.2 Stack-operation exception due to unstack-suppression bit in the header entry being one. 8.B.3 Access exceptions (fetch) for second word of the header entry. 8.B.4 Stack-empty exception due to backward stack-entry validity bit in the header entry being zero. 8.B.5 Access exceptions (fetch) for entry descriptor of the entry designated by the backward stack-entry address in the header entry. 8.B.6 Stack-specification exception due to the designated entry being a header entry. If there is no exception, the designated entry is now called the current entry. 8.B.7 Stack-type exception due to the current entry not being a state entry. 8.B.8 Stack-operation exception due to unstack-suppression bit being one in the current entry. 8.B.9 Access exceptions (fetch) for current entry, and access exceptions (store) for entry descriptor of the preceding entry. Note: Exceptions 8.8.10-8.8.14 and the event 9 can occur only if the current entry is a program-call state entry. 8.B.10 Special-operation exception due to the ASN-translation control, bit 12 of control register 14, being zero (if PASN or SASN translation occurs). Figure 10-18 (Part 1 of 2). Priority of Execution: PROGRAM RETURN 10-46 ESA/370 Principles of Operation 8.B.11 ASN-translation exceptions (if PASN or SASN translation . occurs). 8.B.12 Secondary-authority exception due to authority-table entry being outside table (if SASN translation occurs). 8.B.13 Addressi·ng exception for access to authority-table entry (if SASN translation occurs). 8.B.14 Secondary-authority exception due to S bit in authoritytable entry being zero (if SASN translation occurs). 9. Space-switch event (PR-ss only). Specification exception due to any PSW error of the type that causes an immediate interruption. 10. Figure 10-18 (Part 2 of 2). Priority of Execution: pROGRAM RETURN Programming Note: Because PROGRAM CALL cannot be executed successfully in the secondaryspace or home-space mode, PROGRAM RETURN is not intended to load a psw specifying one of these translation modes. PROGRAM RETURN, unlike SET ADDRESS SPACE CONTROL, does not recognize a space-switch event because of loading a psw that specifies the home-space mode. Program Transfer . PT [RRE] IB228 1 o 24 16 28 31 The contents of general register R1 are used as the new values for the psw-key mask, the PASN, and the SASN. The contents of general register R2 are used as the new values for the problem-state bit, addressing-mode bit, and instruction address in the current psw. Bits 16-23 of the instruction are ignored. General registers Rl and R2 have the following fonnat: PSW-Key Mask o ASN 16 LA~I R21 _________In_s_t_r_uc_t_i_on__A_d_dr_e_s_s______ o 1 ~lp~1 31 When the contents of bit positions 1'6-31 of general register Rl are equal to the current PASN, the operation is called PROGRAM TRANSFER to current primary (PT-Cp); when the fields are not equal, the operation is called PROGRAM TRANSFER with space switching (PT-SS). The contents of general register R2 are used to update the problem-state bit, the addressing-mode bit, and the instruction address of the current psw. Bit 31 of general register R2 is placed in the problem-state bit position, psw bit position 15, unless the operation would cause psw bit 15 to change from one to zero (problem state to supervisor state). If such a change would occur, a privileged-operation exception is recognized. Bits 0-30 of general register R2 replace the addressingmode bit and the instruction address, bits 32-62 of the current psw. Bit 63 of the psw is set to zero. Bits 0-15 of general register R1 are ANDed with the psw-key mask, bits 0-15 of control register 3, and the result replaces the psw-key mask. In both the PT-ss and PT-CP instructions, the ASN specified by bits 16-31 of general register R1 replaces the SASN in control register 3, and the SSTD in control register 7 is replaced by the fmal contents of control register 1. 31 Chapter 10. Control Instructions 10-47 PROGRAM TRANSFER to Current Primary (PT-cp) The PROGRAM TRANSFER to current primary (PT-cp) operation is depicted in part 1 of Figure 10-20 on page 10-51. The PT-Cp operation is completed when the common portion of the PROGRAM TRANSFER operation, described above, is completed. The authorization index, PASN, primary STD, and contents of control register 5 (linkage-table designation or primary-AsN-secondtable-entry origin) are not changed by PT-cp. PROGRAM TRANSFER with Space Switching (PT-ss) If the ASN in bits 16-31 of general register Rl is not equal to the current PASN, a PROGRAM TRANSFER with space switching (PT-SS) is specified, and the ASN is translated by means of a two-level table lookup. The PT-SS operation is depicted in parts 1 and 2 of Figure 10-20 on page 10-51. The PT-SS operation is completed as follows. For a PT-SS, the contents of bit positions 16-31 of general register Rl are used as an ASN, which is translated by means of a two-level table lookup. Bits 16-25 of general register Rl are a 10-bit AFX which is used to select an entry from the ASN frrst table. Bits 26-31 are a six-bit ASX which is used to select an entry from the ASN second table. The ASN table-lookup process is described in the section "ASN Translation" in Chapter 3, "Storage." The exceptions associated with ASN translation are collectively called "AsN-translation exceptions." These exceptions and their priority are described in Chapter 6, "Interruptions." The authority-table origin from the ASN-secondtable entry is used as the base for a third table lookup. The current authorization index, bits 0-15 of control register 4, is used, after it has been checked against the authority-table length, as the index to locate the entry in the authority table. The authority-table lookup is described in the section "ASN Authorization" in Chapter 3, "Storage. " The PT-SS operation is completed by placing bits 64-95 of the ASN-second-table entry in both the PSTD and SSTD positions, bit positions 0-31 of control registers I and 7, respectively. The contents 10-48 ESA/370 Principles of Operation of bit positions 32-47 of the ASN-second-table entry replace the authorization index in bit positions 0-15 of control register 4. When the address-spacefunction (ASF) control, bit 15 of control register 0, is zero, the contents of bit positions 96-127 of the ASN-second-table entry replace the LTD in bit positions 0-31 of control register 5. When the ASF control is one, bits 1-25 of the ASN-second-tableentry address are placed in bit positions 1-25 of control register 5 as the new primary-AsN-secondtable-entry origin, and zeros are placed in bit positions 0 and 26-31. The AS N, bits 16-31 of general register Rl, replaces the SASN and PASN in bit positions 16-31 of control registers 3 and 4. For both the PT-Cp and PT-ss operations, a serialization and checkpoint-synchronization function is performed before the operation begins and again after the operation is completed. Special Conditions The instruction can be executed only when the CPU is in the primary-space mode and the subsystemlinkage control, bit 0 of the linkage-table designation, is one. If the CPU is in the real mode, secondary-space mode, access-register mode, or home-space mode, or if the subsystem-linkage control is zero, a special-operation exception is recognized. Bit 31 of general register R2 is placed in the problem-state bit position, psw bit position 15, unless the operation would cause psw bit 15 to change from one to zero (problem state to supervisor state). If such a change would occur, a privileged-operation exception is recognized. The instruction is completed only if bits 0-7 of general register R2 specify a valid combination for psw bits 32-39. If bit 0 of general register R2 is zero and bits 1-7 are not zeros, a specification exception is recognized. In addition to the above requirements, when a PT-SS instruction is specified, the ASN-translation control, bit 12 of control register 14, must be one; otherwise, a special-operation exception is recognized. When, for PT-SS, the space-switch-event-control bit, bit 0 of control register 1, is one either before or after the execution of the instruction, a spaceswitch-event program interruption occurs after the A space-switch-event operation is completed. program interruption also occ~s after the co~ pletion of a PT-SS operation if a PER event IS reported. The operation is suppressed on all addressing exceptions. The priority of recognition of program exceptions for the instruction is shown in Figure 10-19 on page 10-50. Condition Code: The code remains unchanged. Program Exceptions: • Addressing (linkage-table designation m primary ASN-second-table entry, only when address-space-function control is one; authority-table entry, PT-ss only) • ASN translation (PT-SS only) , • Primary authority (PT-SS only) • . Privileged operation (attempt to set the supervisor state when in the problem state) • Space-switch event (PT-SS only) • Special operation • Specification • Trace Chapter 10. Control Instructions 10-49 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off or the CPU being in secondary-space mode, access-register mode, or homespace mode. 7.C Special-operation exception due to subsystem-linkage control in linkage-table designation in control register 5 being zero (only when address-space-function control is zero). 8.A Trace exceptions. 8.B.1 Addressing exception for access to linkage-table designation in primary ASN-second-table entry (only when address-spacefunction control is one). 8.B.2 Special-operation exception due to subsystem-linkage control in linkage-table designation in primary ASN-second-table entry being zero (only when address-space-function control is one). 8.B.3 Privileged-operation exception due to attempt to set the supervisor state when in the problem state. 8.B.4 Specification exception due to nonzero value in bits 0-7 of general register R2. 8.B.5 Special-operation exception due to the ASN-translation control, bit 12 of control register 14, being zero (PT-ss only). 8.B.6 ASN-translation exceptions (PT-ss only). 8.B.7 Primary-authority exception due to authority-table entry being outside table (PT-ss only). 8.B.8 Addressing exception for access to authority-table entry (PT-ss only). 8.B.9 Primary-authority exception due to P bit in authority-table' entry being zero (PT-ss only). 9. Space-switch event (PT-ss only). Figure 10-19. Priority of Execution: PROGRAM TRANSFER Programming Notes: 1. The operation of PROGRAM TRANSFER (PT) is such that it may be used to restore the CPU to the state saved by a previous PROGRAM CALL. This restoration is accomplished by issuing PT 3,14. Though general registers 3 and 14 are not restored to their original values, the PASN, psw-key mask problem-state bit, addressing mode, and instruction address are restored, and t 10-50 ESAj370 Principles of Operation the authorization index, PSTD, and LTD or primary-AsN-second-table-entry origin are made consistent with the restored PASN. 2. With proper authority, and while executing in a common area, PROGRAM TRANSFER may be used to change ·the primary address space to any desired space. The secondary address space is also changed to be the same as the new primary address space. TRANSFER designates general register 0, and branching occurs. 3. Unlike the RR-fonnat branch instructions, a value of zero in the R2 field for PROGRAM PT-cp and PT-ss PROGRAM TRANSFER Instruction El ~ CR3 before CR3 after I PKM SASN CRl before I (PT-cp only) CR7 afterl CR4 before PT-cp Instruction complete PSTD SSTD PT-ss See following figure Figure 10-20 (Part 1 of 2). Execution of PROGRAM TRANSFER Chapter 10. Control Instructions 10-51 PT-ss CR14 (x16 if CRa.15 • a) (x64 if CRa.15 • 1) (x4) ~ ASH Fi rst Tab 10 ~L R I (xI6) ~ ~ ASH Second Table R·--.I--r---·--..--,----,---,.-,------,,----------! LTD STD * (x4) CR4 AuthOrity Table t R CRI afterl PS CR7 afterl P~ ---'I S_S_TD_ _ L...._ _ CR4 ,----~--...., PASN afterl AX =a CRa.15 .Primary-authority exception if P bit is zero or if table length is exceeded CR5 _after =1 L...-___________________ . CRe.15 LTD or PASTEO l R: Address is real *: ASTE is 64 bytes if CRe.lS = 1: last 48 bytes are not $hown Figure 10-20 (Part 2 of 2). Execution of PROGRAM TRANSFER 10-52 ESA/370 Principles of Operation Program Exceptions: Purge ALB • Privileged operation PALB [RRE] IB248' Reset Re(erence Bit Extended 31 16 9 The ART-lookaside buffer (ALB) of this CPU is cleared of entries. No change is made to the contents of addressable storage or registers. Bits 16-31 of the instruction are ignored. The ALB appears cleared of its original contents beginning with the execution of the next sequential instruction. The operation is not signaled to any other CPU. A serialization function is performed. Condition Code: The code remains unchanged. Program Exceptions: • Privileged operation PTLB 9 [S] 111////////11/11/1 16 IB22AI 16 9 24 28 31 The reference bit in the storage key for the 4K-byte block that is addressed by the contents of general register R2 is set to zero. The contents of general register Rl are ignored. Bits 16-23 of the instruction are ignored. In the 24-bit addressing mode, bits 8-19 of general register R2 designate a 4K-byte block in real storage, and bits 0-7 and 20-31 of the register are ignored. In the 31-bit addressing mode, bits 1-19 of general register R2 designate a 4K-byte block in real storage, and bits 0 and 20-31 of the register are ignored. Because it is a real address, the address designating the storage block is not subject to dynamic address translation. The reference to the storage key is not subject to a protection exception. Purge TLB IB290 1 [RRE] 1////////////////1 31 The translation-Iookaside buffer (TLB) of this CPU is cleared of entries. No change is made to the contents of addressable storage or registers. Bits 16-31 of the instruction are ignored. The TLB appears cleared of its original contents beginning with the fetching of the next sequential instruction. The operation is not signaled to any other CPU. A serialization function is performed. The remaining bits of the storage key, including the change bit, are not affected. The condition code is set to reflect the state of the reference and change bits before the reference bit is set to zero. Resulting Condition Code: o 1 2 3 Reference bit Reference bit Reference bit Reference bit zero; change bit zero zero; change bit one one; change bit zero one; change bit one Program Exceptions: • Addressing (address specified by general register R2) • Privileged operation Condition Code: The code remains unchanged. Chapter 10. Control Instructions 10-53 special-operation exception is recognized. Also, the must be in the supervisor state when the operation is to set the home-space mode; otherwise, a privileged-operation exception is recognized. Set Address Space Control SAC 02 (B2) CPU [S] A serialization and checkpoint-synchronization function is perfonned before the operation begins and again after the operation is completed. IB219 1 16 2a a 31 Special Conditions Bits 20-23 of the second-operand address are used as a code to set the address-space-control bits in the psw. The second-operand address is not used to address data; instead, bits 20-23 fonn the code. Bits 0-19 and 24-31 of the second-operand address are ignored. Bits 20-21 of the second-operand address must be zeros; otherwise, a specification exception is recogriized. The following figure summarizes the operation of 31 When the CPU is in the home-space mode either before or after the operation, but not both before and after the operation, a space-switch-event program interruption occurs after the operation is completed if any of the following is true: ( I) the primary space-switch-event control, bit 0 of control register 1,· is one; (2) the home space-switch-event control, bit 0 of control register 13, is one; or (3) a PER event is to be indicated. Result in PSW Bits 16 and 17 The priority of recognition of program exceptions for the instruction is shown in Figure 10-21 on page 10-55. SET ADDRESS SPACE CONTROL: Second-Operand Address 2a a Code Name of Mode aaaa aaal aa1a aall Primary space Secondary space Access register Home space Invalid All others 24 ea Ie e1 11 Unchanged The address-space-function control, bit 15 of control register 0, must be one when the operation is to set the access-register mode; otherwise, a 10-54 ESA/370 Principles of Operation The operation is perfonned only when the secondary-space control, bit 5 of control register 0, is one and OAT is on. When either the secondaryspace control is zero or OAT is off, a specialoperation exception is recognized. The specialoperation exception is recognized in both the problem and supervisor states. Condition Code: The code remains unchanged. Program Exceptions: • Privileged operation (attempt to set the homespace mode in the problem state) • Space-switch event • Special operation • Specification 1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off or the secondary-space control, bit 5 of control register 0, being zero. 8. Privileged-operation exception due to attempt to set home-space mode when in problem state. 9. Special-operation exception due to the address-space-function control, bit 15 of control register 0, being 0 on an attempt to set access-register mode. 10. Specification exception due to nonzero value in bit positions 20-21 of second-operand address. 11. Space-switch event. clock. Only those bits of the operand are set in the clock that correspond to the bit positions which are updated by the clock; the contents of the remaining rightmost bit positions of the operand are ignored and are not preserved in the clock. In some models, starting at or to the right of bit position 52, the rightmost bits of the second operand are ignored, and the corresponding positions of the clock which are implemented are set to zeros. After the clock value is set, the clock enters the stopped state. The clock leaves the stopped state to enter the set state and resume incrementing under control of the TOD-clock-sync control (bit 2 of control register 0). When the bit is zero, the clock enters the set state at the completion of the instruction. When the bit is one, the clock remains in the stopped state either until the bit is set to zero or until any other running TO D clock in the configuration is incremented to a value of all zeros in bit positions 32-63. SET ADDRESS When the TO D clock is shared by another cPu, the clock remains in the stopped state under control of the TOD-dock-sync control bit of the CPU which set the clock. If, while the clock is stopped, it is set by another CPU, then the clock comes under control of the TOD-clock-sync control bit of the CPU which last set the clock. Programming Note: SET ADDRESS SPACE CONTROL is defmed in such a way that the mode to be set can be placed directly in the displacement field of the instruction or can be specified from the same bit positions of a general register as those in which the mode is saved by INSERT ADDRESS SPACE CONTROL. The value of the clock is changed and the clock is placed in the stopped state only if the manual TOD-clock control of any CPU in the configuration is set to the enable-set position. If the Too-clock control is set to the secure position, the value and the state of the clock are not changed. The two results are distinguished by condition codes 0 and I, respectively. Figure 10-21. Priority of Execution: SPACE CONTROL When the clock is not operational, the value and state of the clock are not changed, regardless of the setting of the TOD-clock control, and condition code 3 is set. Set Clock [S] Special Conditions 'B204' o 16 20 31 The current value of the TOD clock is replaced by the contents of the doubleword designated by the second-operand address, and the clock enters the stopped state. The doubleword operand replaces the contents of the clock, as determined by the resolution of the The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. Resulting Condition Code: o I 2 3 Clock value set Clock value secure Clock in not-operational state Chapter 10. Control Instructions 10-55 Program Exceptions: Set CPU Timer • Access (fetch, operand 2) • Privileged operation • Specification SPT Programming Note: In an installation with more than one CPU, each CPU may have a separate TOO clock, or more than one CPU may share a TOO clock, depending on the model. When multiple TOO clocks exist, special procedures are required to See the section synchronize the clocks. "Too-Clock Synchronization" in Chapter 4, "Control. " IB208 1 o 16 20 31 The current value of the CPU timer is replaced by the contents of the doubleword designated by the second-operand address. Only those bits of the operand are set in the CPU timer that correspond to the bit positions to be updated; the contents of the remaining rightmost bit positions of the operand are ignored and are not preserved in the CPU timer. Set Clock Comparator [S] IB206 1 o [S] Special Conditions 16 20 31 The current value of the clock comparator is replaced by the contents of the doubleword designated by the second-operand address. Only those bits of the operand are set in the clock comparator that correspond to the bit poSitions to be compared with the TOO clock; the contents of the remaining rightmost bit positions of the operand are ignored and are not preserved in the clock comparator. Special Conditions The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. The operation is suppressed on all addressing and protection exceptions. Condition Code: The code remains unchanged. Program Exceptions: • Access (fetch, operand 2) • Privileged operation • Specification Set Prefix [S] The operation is suppressed on all addressing and protection exceptions. IB210 1 Condition Code: The code remains unchanged. o Program Exceptions: The contents of the prefix register are replaced by the contents of bit positions 1-19 of the word at the location designated by the second-operand address. The ART-Iookaside buffer (ALB) and translationlookaside buffer (TLB) of this CPU are cleared of entries. • Access (fetch, operand 2) • Privileged operation • Specification 16 20 31 After the second operand is fetched, the value is tested for validity before it is used to replace the 10-56 ESAj370 Principles of Operation contents ~he prefix register. Bits 1-19 of the operand wi 12 rightmost zeros appended are used as an absol te address of the 4K-byte new prefix area in stor ge. The prefix value is treated as a 31-bit address, regardless of the addressing mode specified by bit 32 of the current psw. The 4K-byte block within the new prefix area is accessed; if it is not available in the configuration, an addressing exception is recognized, and the operation is suppressed. The access to the block is not subject to protection; however, the access may cause the reference bits to be set to ones. If the operation is completed, the new prefix is used for any interruptions following the execution of the instruction and for the execution of subsequent instructions. The contents of bit positions 0 and 20-31 of the operand are ignored. The ART-Iookaside buffer (ALB) and translationlookaside buffer (TLB) are cleared of entries. The ALB and TLB appear cleared of their original contents, beginning with the fetching of the next sequential instruction. A serialization function is perfonned before or after the operand is fetched and again after the operation is completed. Special Conditions The operand must be designated on a word boundary; otherwise, a specification exception is recognized. The operation is suppressed on all addressing and protection exceptions. Condition Code: The code remains unchanged. Set PSW Key from Address SPKA D2 (B2) [S] 'B20A' o 16 20 31 The four-bit psw key, bits 8-11 of the current PSW, is replaced by bits 24-27 of the second-operand address. The second-operand address is not used to address data; instead, bits 24-27 of the address fonn the new psw key. Bits 0-23 and 28-31 of the secondoperand address are ignored. Special Conditions In the problem state, the execution of the instruction is subject to control by the psw-key mask in control register 3. When the bit in the psw-key mask corresponding to the psw-key value to be set is one, the instruction is executed successfully. When the selected bit in the PS w -key mask is zero, a privileged-operation exception is recognized. In the supervisor state, any value. for the psw key is valid. Condition Code: The code remains unchanged. Program Exceptions: • Privileged operation (selected psw-key-mask bit is zero in the problem state) Programming Notes: 1. The fonnat of SET PSW KEY FROM ADDRESS Program Exceptions: • • • • Access (fetch, operand 2) Addressing (new prefix area) Privileged operation Specification permits the program to set the psw key either from the general register designated by the B2 field or from the D2 field in the instruction itself. 2. When one program requests another program to access a location designated by the requesting program, SET PSW KEY FROM ADDRESS can be used by the called program to verify that the requesting program is authorized to make this access, provided the storage location of the called program is not protected against fetching. The called program can perform the verification by replacing the psw key with the requesting-program psw key before making the access and subsequently Chapter 10. Control Instructions 10-57 restoring the called-program psw key to its original value. Caution must be exercised, however, in handling any resulting protection exceptions since such exceptions may cause the operation to be terminated. See TEST PROTECTION and the associated programming notes for an alternative approach to the testing of addresses passed by a calling program. Set Secondary ASN SSAR Rl [RRE] IB225 1 o 16 24 28 31 The ASN specified in bit positions 16-31 of general register Rl replaces the secondary ASN in control register 3, and the segment-table designation corresponding to that ASN replaces the SSTD in control register 7. Bits 16-23 and 28-31 of the instruction are ignored. The contents of bit positions 16-31 of general register Rl are called the new ASN. The contents of bit positions 0-15 of the register are ignored. First the new ASN is compared with the current PASN. If the new ASN is equal to the PASN, the operation is called SET SECONDARY ASN to current primary (SSAR-Cp). If the new ASN is not equal to the current PASN, the operation is called SET SECONDARY ASN with space switching (SSAR-SS). The SSAR-CP and SSAR-ss operations are depicted in Figure 10-23 on page 10-60. SET SECONDARY ASN to Current Primary (SSAR-cp) The new ASN replaces the SASN, bits 16-31 of control register 3; the PSTD, bits 0-31 of control register 1, replaces the SSTD, bits 0-31 of control register 7; and the operation is completed. SET SECONDARY ASN with Space Switching (SSAR-ss) The new ASN is translated by means of the ASN translation tables, and then the current AX, bits 0-15 of control register 4, is used to test whether 10-58 ESA/370 Principles of Operation the program is authorized to access the specified ASN. The new ASN is translated by means of a two-level table lookup. Bits 0-9 of the new ASN (bits 16-25 of the register) are a 10-bit AFX which is used to select an entry from the ASN fIrst table. Bits 10-15 of the new ASN (bits 26-31 of the register) are a six-bit ASX which is used to select an entry from the ASN second table. The two-level lookup is described in the section "ASN Translation" in Chapter 3, "Storage." The exceptions associated with ASN translation are collectively called "AsN-translation exceptions." These exceptions and their priority are described in Chapter 6, "Interruptions. " The AST entry obtained as a result of the second lookup contains the segment-table designation and the authority-table origin and length associated with the ASN. The authority-table ongm from the ASN secondtable entry is used as a base for a third table lookup. The current authorization index, bits 0-15 of control register 4, is used, after it has been checked against the authority-table length, as the index to locate the entry in the authority table. The authority-table lookup is described in the section "ASN Authorization" in Chapter 3, "Storage." The new ASN, bits 16-31 of general register Rl, replaces the SASN, bits 16-31 of control register 3. The segment-table designation, bits 64-95 of the AST entry, replaces the SSTD, bits 0-31 of control register 7. For both the SSAR-Cp and SSAR-ss operations, a serialization and checkpoint-synchronization function is performed before the operation begins and again after the operation is completed. Special Conditions The operation is performed only when the ASN-translation control, bit 12 of control register 14, is one and DAT is on. When either the ASN-translation-control bit is zero or DAT is off, a special-operation exception is recognized. The special-operation exception is recognized in both the problem and supervisor states. The priority of recognition of program exceptions for the instruction is shown in Figure 10-22. Condition Code: The code remains unchanged. Program Exceptions: • Secondary authority (SSAR-SS only) • Special operation • Trace • Addressing (authority-table entry, SSAR-ss only) • ASN translation (SSAR-SS only) 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to OAT being off, or the ASNtranslation control, bit 12 of control register 14, being zero. 8.A Trace exceptions. 8.B.1 ASN-translation exceptions (SSAR-ss only). 8.B.2 Secondary-authority exception due to authority-table entry being outside table (SSAR-ss only). 8.B.3 Addressing exception for access to authority-table entry (SSAR-ss only). 8.B.4 Secondary-authority exception due to S bit in authoritytable entry being zero (SSAR-ss only). Figure 10-22. Priority of Execution: SET SECONDARY ASN Chapter 10. Control Instructions 10-59 SET SECONDARY ASN Instruction CR14 (x4) (x16 if CRa.1S .. a) (x64 if CRa.1S • 1) ASN First Table (accessed for ~ SSAR-ss onlyJ L -_ _ _ _ _ _ _ _~~ •. ~_ _--~ R CR4 before (x16) M SSAR-cp ASN Second Table SSAR-ss ~ (accessed for SSAR-ss onlyJ R I ATO STD LTD * (x4) ~ R Authori ty Table (accessed for SSAR-ss only) CR1 before CR3 before PSTD PS (SSAR-cp only) (SSAR-ss only) CR7 ,..--------, after SS_T_O_ _--' I'-__ CR3 r - - - - y - - - - - , SASN afterl PKM Secondary-authority exception if S bit is zero or if table length is exceeded (SSAR-ss only) R: Address is real *: ASTE is 64 bytes if CRa.1S • 1; last 48 bytes are not shown Figure 10-23. Execution of SET SECONDARY ASN 10-60 ESAj370 Principles of Operation Bits 0-7 of the current PSW are replaced by the byte at the location designated by the second-operand address. Set Storage Key Extended [RRE] 'B22B' o I11111111I R. 24 16 Bits 8-15 of the instruction are ignored. I R, Special Conditions 28 31 The storage key for the 4K-byte block that is addressed by the contents of general register R2 is replaced by bits from general register R 1. Bits 16-23 of the instruction are ignored. In the 24-bit addressing mode, bits 8-19 of general register R2 designate a 4K-byte block in real storage, and bits 0-7 and 20-31 of the register are ignored. In the 31-bit addressing mode, bits 1-19 of general register R2 designate a 4K-byte block in real storage, and bits 0 and 20-31 of the register are ignored. Because it is a real address, the address designating the storage block is not subject to dynamic address translation. The reference to the storage key is not subject to a protection exception. The new seven-bit storage-key value is obtained from bit positions 24-30 of general register Rl. The contents of bit positions 0-23 and 31 of the register are ignored. When the sSM-suppression-control bit, bit 1 of control register 0, is one and the CPU is in the supervisor state, a special-operation exception is recognized. The value to be loaded into the psw is not checked for validity before loading. However, immediately after loading, a specification exception is recognized, and a program interruption occurs, if the contents of bit positions 0 and 2-4 of the psw are not all zeros. In this case, the instruction is completed, and the instruction-length code is set to 2. The specification exception,which is listed as a program exception for this instruction, is described in the section "Early Exception Recognition" in Chapter 6, "Interruptions." This exception may be considered as caused by execution of this instruction or as occurring early in the process of preparing to execute the subsequent instruction. The operation is suppressed on all addressing and protection exceptions. Condition Code: The code remains unchanged. Program Exceptions: A serialization and checkpoint-synchronization function is performed before the operation begins and again after the operation is completed. Condition Code: The code remains unchanged. • • • • Access (fetch, operand 2) Privileged operation Special operation Specification Signal Processor Program Exceptions: • Addressing (address specified by general register R2) • Privileged operation , AE ' Set System Mask SSM o R. 8 R3 12 16 B, D, 20 31 [S] '80' o I I I 8 16 20 31 An eight-bit order code and, if called for, a 32-bit parameter are transmitted to the CPU designated by the CPU address contained in the third operand. The result is indicated by the condition code and may be detailed by status assembled in the, frrstoperand location. Chapter 10. Control Instructions 10-61 The second-operand address is not used to address data; instead, bits 24-31 of the address contain the eight-bit order code. Bits 0-23 of the secondoperand address are ignored. The order code specifies the function to be performed by the addressed CPU. The assignment and defmition of order codes appear in the section "CPU Signaling and Response" in Chapter 4, "Control." The 16-bit binary number contained in bit positions 16-31 of general register R3 forms the CPU address. Bits 0-15 of the register are ignored. The general register containing the 32-bit parameter is Rl or Rl + 1, whichever is the odd-numbered register. It depends on the order code whether a parameter is provided and for what purpose it is used. The operands just described have the following formats: General register designated by R 1: When the order code is accepted and no nonzero status is returned, condition code 0 is set. When status information is generated by this CPU or returned by the addressed CPU, the status is placed in general register Rl, and condition code 1 is set. When the access path to the addressed CPU is busy, or the addressed CPU is operational but in a state where it cannot respond to the order code, condition code 2 is set. When the addressed CPU is not operational (that is, it is not provided in the installation, it is not in the configuration, it is in any of certain customerengineer test modes, or its power is oft), condition code 3 is set. Resulting Condition Code: o Order code accepted 1 2 3 Status stored Busy Not operational Program Exceptions: Status • Privileged operation o 31 General register designated by Rl or Rl + ever is the odd-numbered register: Programming Notes: 1, which- Parameter o 31 General register designated by R3: 1////////////////1 CPU Address o 16 31 Second-operand address: 11/////1//////1////1//// e 24 Order Code 31 A serialization function is performed before the operation begins and again after the operation is completed. 10-62 ESA/370 Principles of Operation 1. A more detailed discussion of the conditioncode settings for SIGNAL PROCFSSOR is contained in the section "CPU Signaling and Response" in Chapter 4, "Control." 2. To ensure that presently written programs will be executed properly when new facilities using additional bits are installed, only zeros should appear in the unused bit positions of the second-operand address and in bit positions 0-15 of general register R3. 3. Certain SIGNAL PROCESSOR orders are provided with the expectation that they will be ll;sed primarily in special circumstances. Such orders may be implemented with the aid of an auxiliary maintenance or service processor, and, thus, the execution time may take several seconds. Unless all of the functions provided by the order are required, combinations of other orders, in conjunction with appropriate programming support, can be expected to provide a specific function more rapidly. The emergency-signal, external-call, and sense orders are the only orders which are intended for frequent use. The following orders are intended for infrequent use, and performance therefore may be much slower than for fre- quently used orders: restart, set prefix, store status at address, start, stop, stop and store status, and all the reset orders. An alternative to the set-prefix order, for faster performance when the receiving CPU is not already stopped, is the use of the emergency-signal or externalcall order, followed by the execution of a SET PREFIX instruction on the addressed CPU. Clearing the TLB of entries is ordinarily accomplished more rapidly through the use of the emergency-signal or external-call order, followed by execution of the PURGE TLB instruction on the addressed CPu, than by use of the set-prefix order. Store Clock Comparator STCKC 02 (82) [S] '8207' o 16 20 31 The current value of the clock comparator is stored at the doubleword location designated by the second-operand address. Store Control STCTl Rl,R3,02(82) '86' o [RS] I I I RI 8 R3 12 82 16 02 20 31 The set of control registers starting with control register R 1 and ending with control register R3 is stored at the locations designated by the secondoperand address. The storage area where the contents of the control registers are placed starts at the location designated by the second-operand address and continues through as m.any storage words as the number of control registers specified. The contents of the control registers are stored in ascending order of their register numbers, starting with control register R 1 and continuing up to and including control register R3, with control register 0 following control register 15. The contents of the control registers remain unchanged. Special Conditions Zeros are provided for the rightmost bit positions of the clock comparator that are not compared with the TOO clock. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. Special Conditions Condition Code: The code remains unchanged. The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. Program Exceptions: Condition Code: The code remains unchanged. Program Exceptions: • Access (store, operand 2) • Privileged operation • Specification Store CPU Address • Access (store, operand 2) • Privileged operation • Specification [S] '8212' o 16 20 31 The CPU address by which this CPU is identified in a multiprocessing configuration is stored at the halfword location designated by the second-operand address. Chapter 10. Control Instructions 10...63 Bit positions 32-47 contain the model number of the CPU. Bit positions 48-63 contain zeros. Special Conditions The operand must be designated on a halfword boundary; otherwise, a specification exception is recognized. Special Conditions Condition Code: The code remains unchanged. The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. Program Exceptions: Condition Code: The code remains unchanged. • Access (store, pperand 2) • Privileged operation • Specification Program Exceptions: • Access (store, operand 2) • Privileged operation • Specification Store CPU ID [S] Programming Notes: I. The program should allow for the possibility that the CPU identification number may contain the digits A-F as well as the digits 0-9. 'B2e2' e 16 2e 31 Information identifying the CPU is stored at the doubleword location designated by the secondoperand address. 2. The CPU identification number, in conjunction with the model number, provides a unique CPU identification that can be used in associating results with an individual machine, particularly in regard to functional differences, performance differences, and error handling. The information stored has the following format: Store CPU Timer Version Code e CPU Identification Number [S] 31 8 'B2e9' e Model Number 32 eeeeeeeeeeeeeeee 48 63 Bit positions 0-7 contain the version code. The format and significance of the version code depend on the model. Bit positions 8-31 contain the CPU identification number, consisting of six four-bit digits. Some or all of these. digits are selected from the physical serial number stamped on the CPU. The contents of the cpu-identification-number field, in conjunction with the model number, permit unique identification of the CPU. t 0-64 ESA/370 Principles of Operation 16 2e 31 The current value of the CPU timer is stored at the doubleword location designated by the secondoperand address. Zeros are provided for the rightmost bit positions that are not updated by the CPU timer. Special Conditions The operand must be designated on a doubleword boundary; otherwise, a specification exception is recognized. Condition Code: The code remains unchanged. Program Exceptions: Program Exceptions: • Access (store, operand 1) • Privileged operation • Access (store, operand 2) • Privileged operation • Specification Programming Note: STORE THEN AND SYSTEM MASK permits the program to set selected bits in the system mask to zeros while retaining the original contents for later restoration. For example, it may be necessary that a program, which has no record of the present status, disable program-event recording for a few instructions. Store Prefix [S] IB2111 o 16 31 20 The contents of the prefix register are stored at the word location designated by the second-operand address. Zeros are provided for bit positions 0 and Store Then OR System Mask STOSM 01(B1),12 [SI] 12 IAOI B1 01 20-31. o 16 8 20 31 Special Conditions The operand must be designated on a word boundary; otherwise, a specification exception is recognized. Condition Code: The code remains unchanged. Special Conditions Program Exceptions: • Access (store, operand 2) • Privileged operation • Specification Store Then AND System Mask STNSM 01(B1),12 [SI] IAC I o 8 16 Bits 0-7 of the current PSW are stored at the frrstoperand location. Then the contents of bit positions 0-7 of the current psw are replaced by the logical OR of their original contents and the second operand. 20 31 Bits 0-7 of the current psw are stored at the frrstoperand location. Then the contents of bit positions 0-7 of the current psw are replaced by the logical AND of their original contents and the second operand. Special Conditions The operation is suppressed on addressing and protection exceptions. The value to be loaded into the psw is not checked for validity before loading. However, immediately after loading, a specification exception is recognized, and a program interruption occurs, if the contents of bit positions 0 and 2-4 of the psw are not all zeros. In this case, the instruction is completed, and the instruction-length code is set to 2. The specification exception, which is' listed as a program exception for this instruction, is described in the section "Early Exception Recognition" in Chapter 6, "Interruptions." This exception may be considered as caused by execution of this instruction or as occurring early in the process of preparing to execute the subsequent instruction. The operation is suppressed on addressing and protection exceptions. Condition Code: The code remains unchanged. Program Exceptions: • Access (store, operand 1) • Privileged operation • Specification Condition Code: The code remains unchanged. Chapter 10. Control Instructions 10-65 Programming Note: STORE THEN OR SYSTEM MASK permits the program to set selected bits in the system mask to ones while retaining the original contents for later restoration. For example, the program may enable the CPU for 1/0 interruptions without having available the current status of the external-mask bit. Test Access [RRE] 'B24C' 16 24 28 31 Store Using Real Address STURA [RRE] 'B246' 16 24 28 31 The contents of general register R1 are stored at the real-storage location addressed by the contents of general register R2. The access-list-entry token (ALET) in access register .R1 is tested for exceptions recognized during accessregister translation (ART). The extended authorization index (EAX) used is bits 0-15 of general register R2. The ALET is also tested for whether it designates the dispatchable-unit access list or the primary-space access list and for whether it is 00000000 or 00000001 hex. When R1 is 0, the actual contents of access register o are used in ART, instead of the 00000000 hex that is usually used. Bits 16-23 of the instruction are ignored. In the 24-bit addressing mode, bits 8-31 of general register R2 field designate a real-storage location on a word boundary, and bits 0-7 of the register are ignored. In the 31-bit addressing mode, bits 1-31 of general register R2 field designate a real-storage location on a word boundary, and bit 0 of the register is ignored. Because it is a real address, the address designating the storage word is not subject to dynamic address translation. Special Conditions The contents of general register R2 must designate a location on a word boundary; otherwise, a specification exception is recognized. Condition Code: The code remains unchanged. Bits 16-31 of general register R2 are ignored. Bits 16-23 of th~ instruction are ignored. The operation does not depend on the translation mode -- bits 5, 16, and 17 of the psw are ignored. When the ALET specified by means of the Rl field is other than 00000000 or 00000001 hex, the ART process is applied to the ALET. The EAX specified by means of the R2 field is called the effective EAX, and it is the EAX which is used by ART. When a situation exists that would normally cause one of the exceptions shown in the following table, the instruction is completed by setting condition code 3. Exception Name Cause ALET specification ALET bits 0-6 not zeros ALEN translation Access-list entry (ALE) outside list or invalid (bit 0 is one) ALE sequence ALE sequence number (ALESN) in ALET not equal to ALESN in ALE ASTE validity ASN-second-table entry (ASTE) invalid (bit 0 is one) ASTE sequence ASTE sequence number (ASTESN) in ALE not equal to ASTESN in ASTE Program Exceptions: • Addressing (address specified by general register R2) • Privileged operation • Protection (store, operand 2, key-controlled protection and low-address protection) • Specification 10-66 ESA/370 Principles of Operation Extended authority ALE private bit not zero, ALE authorization index (ALEAX) not equal to effective EAX, and secondary bit selected by effective EAX either outside authority table or zero When ART is completed without one of the above situations being recognized, the instruction is completed by setting condition code 1 or 2, depending on whether the effective access list is the dispatchable-unit access list or the primary-space access list, respectively. The effective access list is the dispatchable-unit access list if bit 7 of the ALET is zero, or it is the primary-space access list if bit 7 is one. ART, including the obtaining of the effective access-list designation, is described in the section "Access-Register-Translation Process" in Chapter 5, "Program Execution." During ART, the instruction can both use and form entries in the ART-Iookaside buffer (ALB). The segment-table designation that ART normally obtains is ignored. . When the ALET is 00000000 hex, the instruction is completed by setting condition code o. When the ALET is 0000000 I hex, the instruction is completed by setting condition code 3. An addressing exception is recognized when the address used by ART to fetch the effective access-list designation or the ALE, ASTE, or authority-table entry designates a location which is not available in the configuration. When it is necessary to access the authority table -- when the private bit in the ALE is not zero and the ALEAX in the ALE is not equal to the effective EAX -- an ASN-translationspecification exception is recognized when bits 30, 31, and 60-63 of the ASTE are not all zeros. The operation is suppressed on all addressing exceptions. The priority of recognition of program exceptions for -the instruction is shown in Figure 10-24 on page 10-68. Resulting Condition Code: o 1 2 3 Access-list-entry token (ALET) is 00000000 hex ALET designates the dispatch able-unit access list and does not cause exceptions in accessregister translation (ART) ALET designates the primary-space access list and does not cause exceptions in ART ALET is 00000001 hex or causes exceptions in ART Special Conditions Program Exceptions: The operation is performed only when the addressspace-function control, bit IS of control register 0, is one. When the address-space-function control is zero, a special-operation exception is recognized. • Addressing (effective access-list designation, access-list entry, ASN-second-table entry, or authority-table entry) • ASN-translation specification • Special operation Chapter 10. Control Instructions 10-67 1.-6. Exceptions with the same priority as the priority of programinterruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Special-operation exception due to address-space-function control, bit 15 of control register 0, being zero. 8. Condition code 0 due to access-list-entry-token (ALET) being 00000000 hex. 9. Condition code 3 due to ALET being 00000001 hex or ALET bits 0-6 not being all zeros. 10. Addressing exception for access to effective access-list designation. 11. Condition code 3 due to access-list entry (ALE) being outside the 1i st. 12. Addressing exception for access to ALE. 13. Condition code 3 due to ALE being invalid (bit 0 is 1) or access-list-entry sequence number (ALESN) in the ALET not being equal to the ALESN in the ALE. 14. Addressing exception for access to ASN-second-table entry (ASTE). 15. Condition code 3 due to ASTE being invalid (bit 0 is one) or ASTE sequence number (ASTESN) in the ALE not being equal to the ASTESN in the ASTE. 16. ASN-translation-specification exception due to bits 30, 31, and 60-63 of ASTE not being all zeros (only if authority-table access is required). 17. Addressing exception for access to authority-table entry. 18. Condition code 3 due to ALE private bit not being zero, ALE authorization index (ALEAX) not being equal to effective extended authorization index (EAX), and secondary bit selected by effective EAX being either outside the authority table or zero. 19. Condition code 1 if ALET bit 7 is zero; otherwise, condition code 2. Figure 10-24. Priority of Execution: TEST ACCESS Programming Notes: 1. pennits a called program to check whether an ALET passed from the calling program is authorized for use by means of the calling program's EAX. The calling program's EAX can be obtained from the last linkage-stack state entry by means of EXTRACT STACKED TEST ACCESS 10-68 ESA/370 Principles of Operation STATE. The called program can thus avoid perfonning an operation for the calling program, through the use of the called program's EAX, which the calling program is not authorized to perform by means of its own EAX. 2. When an ALET equal to 00000000 hex is passed during a program linkage performed by PROGRAM CALL with space switching (pc-ss), and the ALET conceptually designates the calling program's primary address space and the called program's secondary address space, the ALET must be changed to 0000000 I hex before it is used by the called program. Condition code 0 of TEST ACCESS indicates a 00000000 hex ALET so that the ALET can be changed to 0000000 I hex by the called program. 3. PROGRAM CALL to current primary (pc-cp) sets the secondary address space equal to the primary address space. pc-ss sets the secondary address space equal to the calling program's primary address space, except that stacking pc-ss sets it equal to the called program's primary address space when the secondary-AsN control in the entry-table entry used is one. In all these cases, a passed 0000000 I hex ALET that conceptually designates the calling program's secondary address space is not usable by the called program, even after any transformation (unless the operation was pc-cp and the calling program's PASN and SASN are equal). This is why TEST ACCESS sets condition code 3 when the tested ALET is 0000000 I hex. 4. After a Pc-ss, a passed ALET that conceptually designates an entry in the primary-space access list of the calling program is not usable by the called program. This is why TEST ACCESS sets condition code 2, instead of condition code I, when the tested ALET designates the primaryspace access list. S. The control program may manage the ASN-second-table entry in a way that causes a correctable ASTE-validity or ASTE-sequence exception situation to exist; that is, a situation which, if it were to cause a program interruption during access-register translation, would be corrected by the control program so that access-register translation could be completed successfully. In this case, the program should not use TEST ACCESS directly but should instead use a control-program service that uses TEST ACCESS and that corrects the situation, if possible, when condition code 3 is set. MVS/ESATM provides the TEST ART macro instruction for use instead of the direct use of TEST ACCESS. Test Block [RRE] 'B22C' o 16 24 28 31 The storage locations and storage key of a 4K-byte block are tested for usability, and the result of the test is indicated in the condition code. The test for usability is based on the susceptibility of the block to the occurrence of invalid checking-block code. Bits 16-23 of the instruction are ignored. The block tested is addressed by the contents of general register R2. The contents of general register Rl are ignored. A complete testing operation is necessarily performed only when the initial contents of general register 0 are zero. The contents of general register oare set to zero at the completion of the operation. If the block is found to be usable, the 4K bytes of the block are cleared to zeros, the contents of the storage key are unpredictable, and condition code 0 is set. If the block is found to be unusable, the data and the storage key are set, as far as is possible by the model, to a value such that subsequent fetches to the area do not cause a machine-check condition, and condition code lis set. In the 24-bit addressing mode, bits 8-19 of general register R2 designate a 4K-byte block in real storage, and bits 0-7 and 20-31 of the register are ignored. In the 31-bit addressing mode, bits 1-19 of general register R2 designate a 4K-byte block in real storage, and bits 0 and 20-31 of the register are ignored. The address of the block is a real address, and the accesses to the block designated by the secondoperand address are not subject to key-controlled and page protection. Low-address protection d?es apply. The operation is terminated on addressmg and protection exceptions. If termination occurs, the condition code and the contents of general register 0 are unpredictable. The contents of the MVS/ESA is a trademark of the International Business Machines Corporation. Chapter 10. Control Instructions 10-69 storage block and its associated storage key are not changed when these exceptions occur. Depending on the model, the test for usability may be performed (1) by alternately storing and reading out test patterns to the data and storage key in the block or (2) by reference to an internal record of the usability of the blocks which are available in the configuration, or (3) by using a combination of both mechanisms. In models in which an internal record is used, the block is indicated as unusable if a solid failure has been previously detected, or if intermittent failures in the block have exceeded the threshold implemented by the model. In such models, depending on the criteria, attempts to store mayor may not occur-. Thus, if block 0 is not usable, and no store occurs, low-address protection mayor may not be indicated. In models in which test patterns are used, TFST BLOCK may be interruptible. When an interruption occurs after a unit of operation, other than the last one, the condition code is unpredictable, and the contents of general register 0 may contain a record of the state of intermediate steps. When execution is· resumed after an interruption, the condition code IS ignored, but the contents of general register 0 may be used to determine the resumption point. If (1) TFST BLOCK is executed with an initial value other than zero in general register 0, or (2) the interrupted instruction is resumed after an interruption with a value in general register 0 other than the value which was present at the time of the interruption, or (3) the block is accessed by another CPU or by the channel subsystem during the execution of the instruction, then the contents of the storage block, its associated storage key, and general register 0 are unpredictable, along with the resultant condition-code setting. Invalid checking-block-code errors initially found in the block or encountered during the test do not normally result in machine-check conditions. The test-block function is implemented in such a way that the frequency of machine-check interruptions due to the instruction execution is not significant. However, if, during the execution of TFST BLOCK for an unusable block, that block is accessed by another CPU (or by the channel subsystem), error conditions may be reported both to this CPU and to the other CPU (or to the channel subsystem). 10-70 ESA/370 Principles of Operation A serialization function is performed before the block is accessed and again after the operation is completed (or _partially completed). The priority of the recognition of exceptions and condition codes is shown in Figure 10-25. Resulting Condition Code: o Block usable Block not usable 1 2 3 Program Exceptions: • Addressing (fetch and store, operand 2) • Privileged operation • Protection (store, operand 2, low-address protection only) 1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case. 7.A Access exceptions for second instruction halfword. 7.B Privileged-operation exception. 8. Addressing exception due to block not being available in the configuration.* 9.A Condition code 1, block not usable. 9.B Protection exception due to"low-address protection.* 10. Condition code 0, block usable and set to zeros. Explanation: * The operation is terminated on addressing and protection exceptions, and the condicode may be unpredictable. Figure 10-25. Priority of Execution: TEST B.LOCK Programming Notes: 1. The execution of TFST BLOCK on most models is significantly slower than that of the MOVE LONG instruction with padding; therefore, the instruction should not be used for the· normal case of clearing storage. 2. The program should use TEST BLOCK at initial program loading and as part of the varystorage-online procedure to determine if blocks of storage exist which should not be used. 3. The program should use TEST BLOCK when an uncorrected error is reported in either the data or storage key of a block. This is because in the execution of TEST BLOCK the attempt is made, as far as is possible on the model, to leave the contents of a block in a state such that subsequent prefetches or unintended references to the block do not cause machine-check conditions. The program may use the resulting condition code in this case to determine if the block can be reused. (The block could be indicated as usable if, for example, the error were an externally generated error or an indirect storage error.) This procedure should be followed regardless of whether the indirectstorage-error indication is reported. 4. The model mayor may not be successful in removing the errors from a block when TEST BLOCK is executed. The program therefore should take every reasonable precaution to avoid referencing an unusable block. For example, the program should not place the page-frame real address of an unusable block in an attached and valid page-table entry. 5. On some models, machine checks may be reported for a block even though the block is not referenced by the program. When a machine check is reported for a storage-key error in a block which has been marked as unusable by the program, it is possible that SET STORAGE KEY EXTENOED may be more effective than TEST BLOCK in validating the storage key. 6. The storage-operand references for TEST BLOCK may be multiple-access references. (See the section "Storage-Operand Consistency" m Chapter 5, "Program Execution.") The location designated by the frrst-operand address is tested for protection exceptions by using the access key specified in bits 24-27 of the secondoperand address. The second-operand address is not used to address data; instead, bits 24-27 of the address form the access key to be used in testing. Bits 0-23 and 28-31 of the second-operand address are ignored. The frrst-operand address is a logical address. When the CPU is in the access-register mode (when OAT is on and psw bits 16 and 17 are 01 binary), the frrst-operand address is subject to translation by means of both the access-register-translation (ART) and the dynamic-address-translation (OAT) processes. ART applies to the access register designated by the Bl field, and it obtains the segment-table designation to be used by OAT. When OAT is on but the CPU is not in the access-register mode, the frrst-operand address is subject to translation by OAT. In this case, OAT uses the segment-table designation contained in control register 1, 7, or 13 when the CPU is in the primary-space, secondaryspace, or home-space mode, respectively. When OAT is off, the frrst-operand address is a real address not subject to translation by either ART or OAT. When the CPU is in the access-register mode and a segment-table designation cannot be obtained by ART because of a situation that would normally cause one of the exceptions shown in the following table, the instruction is completed by setting condition code 3. Exception Name Cause ALET specification Access-list-entry-token (ALET) bits 0-6 not zeros ALEN translation Access-list entry (ALE) outside list or invalid (bit 0 is one) ALE sequence ALE sequence number (ALESN) in ALET not equal to ALESN in ALE ASTE validity ASN-second-table entry (ASTE) invalid (bit 0 is one) ASTE sequence ASTE sequence number (ASTESN) in ALE not equal to ASTESN in ASTE Test Protection [SSE] ~_'_E5_01_'~i~B_l~i~~~J o 16 20 32 36 47 Chapter 10. Control Instructions 10-71 Extended authority ALE private bit not zero, ALE authorization index (ALEAX) not equal to extended authorization index (EAX), and secondary bit selected by EAX either outside authority table or zero When the access register contains 00000000 hex or 00000001 hex, ART obtains the segment-table designation from control register 1 or 7, respectively, without accessing the access list. When the B 1 field designates access register 0, ART treats the access register as containing 00000000 hex and does not examine the actual contents of the access register. When ART is completed successfully, the operation is continued through the performance of OAT. When OAT is on and the frrst-operand address cannot be translated because of a situation that would normally cause a page-translation or segment-translation exception, the instruction is completed by setting condition code 3. When translation of the frrst-operand address can be completed, or when OAT is off, the storage key for the block designated by the frrst-operand address is tested against the access key specified in bits 24-27 of the second-operand address, and the condition code is set to indicate whether store and fetch accesses are permitted, taking into consideration all applicable proteGtion mechanisms. Thus, for example, if low-address protection is active and the frrst-operand effective address is less than 512, then a store access is not permitted. Page protection and fetch -protection override are also taken into account. The contents of storage, including the change bit, are not affected. Depending on the model, the reference bit for the frrst-operand address may be set to one, even for the case in which the location is protected against fetching. Special Conditions When the CPU is in the access-register mode, an addressing exception is recognized when the address used by ART to fetch the effective access-list designation or the ALE, ASTE, or authority-table entry designates a location which is not available in the configuration. When it is necessary to access the authority table -- when the private bit in the ALE is not zero and the ALEAX in the ALE is not equal to the EAX -- an ASN-translation-specification excep- t 0-72 ESAj370 Principles of Operation tion is recognized when bits 30, 31, and 60-63 of the ASTE are not all zeros. When OAT is on, an addressing exception is recognized when the address of the segment-table entry, the page-table entry, or the operand real address after translation designates a location which is not available in the configuration. Also, a translationspecification exception is recognized when the segment-table entry or page-table entry has a format error. When OAT is off, only the addressing exception due to the operand real address applies. For all of the above cases, the operation is suppressed. Resulting Condition Code: o 1 2 3 Fetching permitted; storing permitted Fetching permitted; storing not permitted Fetching not permitted; storing not permitted Translation not available Program Exceptions: • Addressing (effective access-list designation, access-list entry, ASN-second-table entry, authority-table entry, or operand 1) • ASN-translation specification • Privileged operation • Translation specification Programming Notes: 1. TEST PROTECTION permits a program to check the validity of an address passed from a calling program without incurring program exceptions. The instruction sets a condition code to indicate whether fetching or storing is permitted at the location designated by the frrst-operand address of the instruction. The instruction takes into consideration all of the protection mechanisms in the machine: key-controlled, page, and low-address protection and fetchprotection override. Additionally, since segment translation and page translation may be a program substitute for a protection violation, these situations are used to set the condition code rather than cause a program exception. When the CPU is in the access-register mode, TEST PROTECTION additionally permits the program to check the usability of an access-listentry token (ALET) in an access register without incurring program exceptions. The ALET is checked for validity (absence of an ALET-spec- ification, ALEN -translation, and ALE-sequence situation) and for being authorized for use by the program (absence of an ASTE-validity, ASTE sequence, and extended-authority situation). When DAT is off for LOAD REAL ADDRESS, the translation-specification exception for an invalid value of bits 8-12 of control register 0 occurs after instruction fetching as part of the execution portion of the instruction. This situation cannot occur for TEST PROTECTION since the operand address is a logical address and does not result in examination of control register 0 when DAT is off. When DAT is on, the exception would be recognized during instruction fetching. Since the instruction-fetching portion of an instruction is common for all instructions, descriptions of access exceptions associated with instruction fetching do not appear in the individual instruction defmitions. 2. See the programming notes under SET PSW KEY FROM ADDRESS for more details and for an alternative approach to testing validity of addresses passed by a calling program. The approach using TEST PROTECTION has the advantage of a test which does not result in interruptions; however, the test and use are separated in time and may not be accurate if the possibility exists that the storage key of the location in question can change between the time it is tested and the time it is used. 3. In the handling of dynamic address translation, TEST PROTECTION is similar to LOAD REAL AD DRESS in that the instructions do not cause page-translation and segment-translation exceptions. Instead, these situations are indicated by means of a condition-code setting. Similarly, access-register translation sets a condition code for certain situations when performed during either of the two instructions. Situations which result in condition codes 1, 2, and 3 for LOAD REAL ADDRESS result in condiThe tion code 3 for TEST PROTECTION. instructions also differ in several other respects. The frrst-operand address of TEST PROTECTION is a logical address and thus is not subject to dynamic address translation when DAT is off. The second-operand address of LOAD REAL ADDRESS is a virtual address which is always translated. TEST PROTECTION may use the TLB for translation of the address, whereas LOAD REAL AD DRESS does not use the TLB. (LOAD REAL AD DRESS is the only instruction which must perform dynamic address translation without use of the TLB.) Access-register translation applies to TEST PROTECTION only when the CPU is in the accessregister mode (DAT is on), whereas it applies to LOAD REAL ADDRESS when psw bits 16 and 17 are 01 binary regardless of whether DAT is on or off. When condition code 3 is set because of an exception situation in access-register translation, LOAD REAL ADDRESS, but not TEST PROTECTION, returns in a general register the program-interruption code assigned to the exception. When access-register translation is performed, both TEST PROTECTION and LOAD REAL ADDRESS may use the ART-Iookaside 'buffer (ALB). Trace '99' o I Rl I R, I 82 8 12 16 02 20 31 When explicit tracing is on (bit 31 of control register 12 is one), the second operand, which is a 32-bit word in storage, is fetched, and bit 0 of the word is examined. If bit 0 of the second operand is zero, a trace entry is formed at the real-storage location designated by control register 12. If explicit tracing is off (bit 31 of control register 12 is zero), or if bit 0 of the second operand is one, no trace entry is formed, and no trace exceptions are recognized. The trace entry is composed of an entry-type identifier, a count of the number of general registers whose contents are placed in the entry, bits 16-63 of the TOO clock, the second operand, and the contents of a range of general registers. The general registers are stored in ascending order of their register numbers, starting with general register Rl and continuing up to and including general register R3, with general register 0 following general register 15. The trace table and the trace-entry formats are described in the section "Tracing" in Chapter 4, "Control. " When a trace entry is made, a serialization and checkpoint-synchronization function is performed before the operation begins and again after the operation is completed. Chapter 10. Control Instructions 10-73 Special Conditions Condition Code: The code remains unchanged. A privileged-operation exception is recognized in the problem state, even when explicit tracing is off or bit 0 of the second operand is one. Program Exceptions: The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. It is unpredictable whether the specification exception is recognized when explicit tracing is off. It is unpredictable whether access exceptions are recognized for the second operand when explicit tracing is off. 10-74 ESA/370 Principles of Operation • • • • Access (fetch, operand 2) Privileged operation Specification Trace Programming Note: Bits 1-15 of the second operand are reserved for model-dependent functions and should therefore be set to zeros. Chapter 11. Machine-Check Handling Machine-Check Detection . . . . . . . Correction of Machine Malfunctions Error Checking and Correction CPU Retry . . . . . . . . . . . Effects of CPU Retry Checkpoint Synchronization Handling of Machine Checks during Checkpoint Synchronization Checkpoint-Synchronization Operations Checkpoint-Synchronization Action Channel-Subsystem Recovery Unit Deletion . . . . . . . Handling of Machine Checks Validation . . . . . . . . . Invalid CBC in Storage .. . Programmed Validation of Storage Invalid CBC in Storage Keys Invalid CBC in Registers Check-Stop State . . . . . . . System Check Stop Machine-Check Interruption Exigent Conditions Repressible Conditions Interruption Action . . . . . . . Point of Interruption . . . . . . Machine-Check-Interruption Code Subclass . . . . . . . . . . . . . . ...... . System Damage Instruction-Processing Damage System Recovery . . . . Timing- Facility Damage External Damage . . . . Vector-Facility Failure Degradation . . . . . . . Warning . . . . . . . . . Channel Report Pending Service-Processor Damage Channel-Subsystem Damage Subclass Modifiers . . . . Vector-Facility Source .. . Backed Up . . . . . . . . . Delayed Access Exception Synchronous Machine-Check-Interruption Conditions 11-2 11-2 11-2 11-2 11-3 11-3 11-3 11-3 11-4 11-4 11-4 11-4 11-5 11-6 11-6 11-7 11-10 11-11 11-11 11-11 11-11 11-12 11-12 11-14 11-14 11-15 11-15 11-16 11-16 11-16 11-16 11-17 11-17 11-17 11-17 11-17 11-17 11-18 11-18 11-18 11··18 Processing Backup Processing Damage Storage Errors Storage Error Uncorrected Storage Error Corrected Storage-Key Error Uncorrected Storage Degradation . . . . . . Indirect Storage Error . . . . . Machine-Check Interruption-Code Validity Bits . . . . . . . . . . PSW-MWP Validity . . . . . PSW Mask and Key Validity PSW Program-Mask and Condition-Code Validity " PSW-Instruction-Address Validity F ailing-Storage-Address Validity External-Damage-Code Validity Floating-Point- Register Validity General-Register Validity Control-Register Validity Storage Logical Validity Access-Register Validity CPU -Timer Validity . . . . Clock-Comparator Validity Machine-Check Extended Interruption Information . . . . . . . . . . . Register-Save Areas .. . Extenlal-Damage Code ... . Failing-Storage Address ... . Handling of Machine-Check Conditions .. Floating Interruption Conditions Floating Machine-Check-Interruption Conditions . . . . . . . . Floating I/O Interruptions Machine-Check Masking Channel-Report-Pending Subclass l\1ask . . . . . . . . . . . . Recovery Subclass Mask Degradation Subclass Mask ... External-Damage Subclass Mask Warning Subclass Mask . . . . . Machine-Check Logout . . . . . . . . Summary of Machine-Check Masking 11-18 11-19 11-19 11-19 11-19 11-19 11-19 11-20 11-20 11-20 11-20 11-21 11-21 11-21 11-21 11-21 11-21 11-21 11-21 11-21 11-21 11-21 11-22 11-22 11-22 11-22 11-23 11-23 11-23 11-23 11-23 11-24 11-24 11-24 11-24 11-24 11-24 11-24 11-18 The machine-check-handling mechanism provides extensive equipment-malfunction detection to ensure the integrity of system operation and to permit automatic recovery from some malfunctions. Equipment malfunctions and certain external dis- turbances are reported by means of a machinecheck interruption to assist in program-damage assessment and recovery. The interruption supplies the program with information about the extent of the damage and the location and nature of the Chapter 11. Machine-Check Handling 11-1 cause. Equipment malfunctions, errors, and other situations which can cause machine-check interruptions are referred to as machine checks. cause of dents. CPU delay and to keep a log of such inci- Error Checking and Correction Machine-Check Detection Machine-check-detection mechanisms may take many forms, especially in control functions for arithmetic and logical processing, addressing, For programsequencing, and execution. addressable information, detection is normally accomplished by encoding redundancy into the information in such a manner that most failures in the retention or transmission of the information result in an invalid code. The encoding normally takes the form of one or more redundant bits, called check bits, appended to a group of data bits. Such a group of data bits and the associated check bits are called a checking block. The size of the checking block depends on the model. The inclusion of a single check bit in the checking block allows the detection of any single-bit failure within the checking block. In this arrangement, the check bit is sometimes referred to as a "parity bit." In other arrangements, a group of check bits is included to permit detection of multiple errors, to permit error correction, or both. For checking purposes, the contents of the entire checking block, including the redundancy, are called the checking-block code (CBC). When a CBC completely meets the checking requirements (that is, no failure is detected), it is said to be valid. When both detection and correction are provided and a CBC is not valid bu, satisfies. the checking requirements for correction (the failure is correctable), it is said to be near-valid. When a CBC does not satisfy the checking requirements (the failure is uncorrectable), it is said to be invalid. Correction of Machine Malfunctions Fout mechanisms may be used to provide recovery from machine-detected malfunctions: error checking and correction, CPU retry, channelsubsystem recovery, and unit deletion. Machine failures which are corrected successfully mayor may not be reported as machine-check interruptions. If reported, they are system-recovery conditions, which permit the program to note the 11-2 ESA/370 Principles of Operation When sufficient redundancy is included in circuitry or in a checking block, failures can be corrected. For example, circuitry can be triplicated, with a voting circuit to determine the correct value by selecting two matching results out of three, thus correcting a single failure. An arrangement for correction of failures of one order and for detection of failures of a higher order is called error checking and correction (BCC). Commonly, BCC allows correction of single-bit failures and detection of double-bit failures. Depending on the model and the portion of the machine in which· BCC is applied, correction may be reported as system recovery, or no report may be given. Uncorrected errors in storage and in the storage key may be reported, along with a failing-storage address, to indicate where the error occurred. Depending on the situation, these errors may be reported along with system recovery or with the damage or backup condition resulting from the error. CPU Retry In some models, information about some portion of the state of the machine is saved periodically. The point in the processing at which this information is saved is called a checkpoint. The information saved is referred to as the checkpoint information. ,The action of saving the information is referred to as establishing a checkpoint. The action of discarding previously saved information is called invalidation of the checkpoint information. The length of the interval between establishing checkpoints is model-dependent. Checkpoints may be established at the beginning of each instruction or several times within a single instruction, or checkpoints may be established less frequently. Subsequently, this saved information may be used' to restore the machine to the state that existed at the time when the checkpoint was established. After restoring the appropriate portion of the machine state, processing continues from the checkpoint. The process of restoring to a checkpoint and then continuing is called CPU retry. CPU retry may be used for machine-check recovery, to effect nullification and suppression of instruction execution when certain program interruptions occur, and in other model-dependent situations. Effects of CPU Retry CPU retry is, in general, performed so that there is no effect on the program. However, change bits which have been changed from zeros to ones are not necessarily set back to zeros. As a result, change bits may appear to be set to ones for blocks which would have been accessed if restoring to the checkpoint had not occurred. If the path taken by the program is dependent on information that may be changed by another CPU or by a channel program or if an interruption occurs, then the fmal path taken by the program may be different from the earlier path; therefore, change bits may be ones because of stores along a path apparently never taken. less critical machine-check -interruption condition may be reported with the storage-logical-validity bit set to zero. A failure to successfully complete stores associated with the execution of an interruption, other than program or supervisor call, is reported as system damage. When the machine check occurs as part of a checkpoint-synchronization action before the execution of an instruction, the execution of the instruction is nullified. When it occurs before the execution of an interruption, the interruption condition, if the interruption is external, I/O, or restart, is held pending. If the checkpoint-synchronization operation was a machine-check interruption, then along with the originating condition, either the storage-logical-validity bit is set to zero or instruction-processing damage is also reported. Program interruptions, if any, are lost. Checkpoint-Synchronization Operations Checkpoint Synchronization Checkpoint synchronization consists in the following steps. 1. The CPU operation is delayed until all conceptually previous accesses by this CPU to storage have been completed, both for purposes of machine-check detection and as observed by other CPUs and by channel programs. 2. All previous checkpoints, if any, are canceled. 3. Optionally, a new checkpoint is established. The CPU operation is delayed until all of these actions appear to be completed, as observed by other CPUs and by channel programs. Handling of Machine Checks during Checkpoint Synchronization When, in the process of completing all previous stores as part of the checkpoint-synchronization action, the machine is unable to complete all stores successfully but can successfully restore the machine to a previous checkpoint, processing backup is reported. When, in the process of completing all stores as part of the checkpoint-synchronization action, the machine is· unable to complete all stores successfully and cannot successfully restore the machine to a previous checkpoint, the type of machine-checkinterruption condition reported depends on the origin of the store. Failure to successfully complete stores associated with instruction execution may be reported as instruction-processing damage, or some All interruptions and the execution of certain instructions cause a checkpoint-synchronization action to be performed. The operations which cause a checkpoint-synchronization action are called checkpoint-synchronization operations and include: • CPU reset • All interruptions: external, I/O, machine check, program, restart, and supervisor call • The BRANCH ON CONDITION (BCR) instruction with the M1 and R2 fields containing all ones and all zeros, respectively • The instructions LOAD PSW, SET STORAGE KEY EXTENDED, and SUPERVISOR CALL • All I/O instructions • The instructions MOVE TO PRIMARY, MOVE TO SECONDARY, PROGRAM CALL, PROGRAM TRANSFER, SET ADDRESS SPACE CONTROL, and SET SECONDARY ASN, and PROGRAM RETURN when the state entry to be unstacked is a program-call state entry • The three trace functions: branch tracing, ASN tracing, and explicit tracing Programming Note: The instructions which are defmed to cause the checkpoint-synchronization action invalidate checkpoint information but do not necessarily establish a new checkpoint. Additionally, the CPU may establish a checkpoint between any two instructions or units of operation, or within a single unit of operation. Thus, the point of interruption for the machine check is not necessarily at an instruction defmed to cause a checkpoint-synchronization action. Chapter 11. Machine-Check Handling t 1-3 Checkpoint-Synchronization Action For all interruptions except I/O interruptions, a checkpoint-synchronization action is performed at the completion of the interruption. For I/O interruptions, a checkpoint-synchronization action may or may not be performed at the completion of the interruption. For an interruptions except program, supervisor-call, and exigent machine-check interruptions, a checkpoint-synchronization action is also performed before the interruption. The fetch access to the new PSW may be performed either before or after the fust checkpoint-synchronization action. The store accesses and the changing of the current psw associated with the interruption are performed after the fust checkpoint-synchronization action and before the second. For all checkpoint-synchronization instructions except BRANCH ON CONDITION (BCR), I/O instructions, and SUPERVISOR CALL, checkpointsynchronization actions are performed before and after the execution of the instruction. For BCR, only one checkpoint-synchronization action is necessarily performed, and it may be performed either before or after the instruction address is updated. For SUPERVISOR CALL, a checkpointsynchronization action is performed before the instruction is executed, including the updating of the instruction address in the psw. The checkpoint-synchronization action taken after the supervisor-can interruption is considered to be part of the interruption action and not part of the instruction execution. For I/O instructions, a checkpoint-synchronization action is always performed before the instruction is executed and may or may not be performed after the instruction is executed. The three trace functions -- branch tracing, ASN tracing, and explicit tracing -- cause checkpointsynchronization actions to be performed before the trace action and after completion of the trace action. Channel-Subsystem Recovery When errors are detected in the channel subsystem, the channel subsystem attempts to analyze and recover the internal state associated with the 'various channel-subsystem functions and the state of the channel subsystem and various subchannels. This process, which is called channel-subsystem recovery, may result in a complete recovery or may result in the termination of one or more I/O operations and the clearing of the affected subchannels. 11-4 ESAj370 Principles of Operation Special channel-report-pending machine-checkinterruption conditions may be generated to indicate to the program the status of the channelsubsystem recovery. Malfunctions associated with the I/O operations, depending on the severity of the malfunction, may be reported by means of the I/o-interruption mechanism or by means of the channel-report-pending and channel-subsystem-damage machine-checkinterruption conditions. Unit Deletion In some models, malfunctions in certain units of the system can be circumvented by discontinuing the use of the unit. Examples of cases where unit deletion may occur include the disabling of all or a portion of a cache or of a translation-Iookaside buffer (TLB). Unit deletion may be reported as a degradation machine-check-interruption condition. Handling of Machine Checks A machine check is caused by a machine malfunction and not by data or instructions. This is ensured during the power-on sequence by initializing the machine controls to a valid state and by placing valid CBC in the CPU registers, in the storage keys, and in main storage. Designation of an unavailable component, such as a storage location, subchannel, or I/O device, does not cause a machine-check indication. Instead, such a condition is indicated by the appropriate program or I/O interruption or condition-code setting. In particular, an attempt to access a storage location which is not in the configuration, or which has power off at the storage unit, results in an addressing exception when detected by the CPU and does not generate a machine-check condition, even though'the storage location or its associated storage key has invalid CBC. Similarly, if the channel subsystem attempts to access such a location, an I/o-interruption condition indicating program check is generated rather than a machinecheck condition. A machine check is indicated whenever the result of an operation could be affected by information with invalid CBC, or when any other malfunction makes it impossible to establish reliably that an operation can be, or has been, performed correctly. When information with invalid CBC is fetched but not used, the condition mayor may not be indicated, and the invalid cac is preserved. When a machine malfunction is detected, the action taken depends on the model, the nature of the malfunction, and the situation in which the malfunction occurs. Malfunctions affecting operator-facility actions may result in machine checks or may be indicated to the operator. Malfunctions affecting certain other operations such as SIGNAL PROCESSOR may be indicated by means of a condition code or may result in a machine-checkinterruption condition. A malfunction detected· as part of an I/O operation may cause a machine-cheek-interruption condition, an I/o-error condition, or both. I/o-error conditions are indicated by an I/O interruption or by the appropriate condition-code setting during the execution of an I/O instruction. When the machine reports a failing-storage location detected during an I/O operation, both I/o-error and machine-check conditions may be indicated. The I/o-error condition is the primary indication to the program. The machine-check condition is a secondary indication, which is presented as system recovery together with a failing-storage address. Certain malfunctions detected as part of I/O instructions and I/O operations are reported by means of special .machine-check conditions called I/O machine-check conditions. Thus, malfunctions detected as part of an operation which is I/O related may be reported, depending on the error, in any of three ways: I/O-error condition, I/O machine-check condition, or non-I/O machine-check condition. In some cases the defmition requires the error to be reported by only one of these mechanisms; in other cases, anyone, or in some cases, more than one, may be indicated. Programming Note: Although the defmition for machine-check conditions is that they are caused by machine malfunctions and not by data and instructions, there are certain unusual situations in which machine-check conditions are caused by events which are not machine malfunctions. Two examples follow: 1. In some cases, the channel-report-pending machine-check-interruption condition indicates a non-error situation. For example, this·condition is generated at the completion of the function specified by RESET CHANNEL PATH. 2. Improper use of DIAGNOSE may result in machine-check conditions. Validation Machine errors can be generally classified as solid or intermittent, according to the persistence of the malfunction. A persistent machine error is said to be solid, and one that is not persistent is said to be intermittent. In the case of a register or storage location, a third type of error must be considered, called externally generated. An externally generated error is. one where no failure exists in the register or storage location but invalid cac has been introduced into the location by actions external to the location. For example, the value could be affected by a power transient, or an incorrect value may have been introduced when the information was placed at the location. Invalid CBC is preserved ·as invalid when information with invalid CBC is fetched or when an attempt is made to update only a portion of the checking block. When an attempt is made to replace the contents of the entire checking block and the block contains invalid CBC, it depends on the operation and the model whether the block remains with invalid CBC or is replaced. An operation which replaces the contents of a checking block with valid CBC, while ignoring the current contents, is called a validation operation. Validation is used to place a valid cac in a register or at a location which has an interrillttent or externally generated error. Validating a checking block does not ensure that a valid CBe will be observed the next time the checking block is accessed. If the failure is solid, validation is effective only if the information placed in the checking block is such that the failing bits are set to the value to which they fail. If an attempt is made to set the bits to the state opposite to that in which they fail, then the validation will not be effective. Thus, for a solid failure, validation is only useful to eliminate the error condition, even though the underlying failure remains, thereby reducing the exposure to additional reports. The locations, however, cannot be used, since invalid cac will result from attempts to store other values For an intermittent failure, at the location. however, validation is useful to restore a valid CBC such that a subsequent partial store into the checking block will be permitted. (A. partial store is a store into a checking block without replacing the entire checking block.) When a checking block consists of multiple bytes in storage, or multiple bits in CPU registers, the Chapter 11. Machine-Check Handling 11-5 invalid CBC can be made valid only when all of the bytes or bits are replaced simultaneously. For each type of field in the system, certain instructions are defmed to validate the field. Depending on the model, additional instructions may also perform validation; or, in some models, a register is automatically validated as part of the machine-cheek-interruption sequence after the original contents of the register are placed in the appropriate save area. When an error occurs in a checking block, the original information contained in the checking block should be considered lost even after validation. Automatic register validation leaves the contents unpredictable. Programmed and manual validation of checking blocks causes the contents to be changed explicitly. Programming Note: The machine-checkinterruption handler must assume that the registers require validation. Thus, each register should be loaded, using an instruction defmed to validate, before the register is used or stored. Invalid eae in Storage The size of the checking block in storage depends on the model but is never more than 4K bytes. When invalid CBC is detected in storage, a machinecheck condition may occur; depending on the circumstances, the machine-check condition may be system damage, instruction-processing damage, or system recovery. If the invalid CBC is detected as part of the execution of a channel program, the error is reported as an I/O-error condition. When a ccw, indirect-data-address word, or data is prefetched from storage, is found to have invalid CBC, but is not used in the channel program, the condition is normally not reported as an I/o-error condition. The condition mayor may not be reported as a machine-check-interruption condition. Invalid CBC detected during accesses to storage for other than CPU -related accesses may be reported as system recovery with storage error uncorrected indicated, since the primary error indication is reported by some other means. When the storage checking block consists of multiple bytes and contains invalid CBC, special storage-validation procedures are generally neces- 11-6 ESAj370 Principles of Operation sary to restore or place new information in the checking block. Validation of storage is provided with the manual load-clear and system-reset-clear operations and is also provided as a program function. Programmed storage validation is done a block at a time, by executing the privileged instruction TEST BLOCK. Manual storage validation by clear reset validates all blocks which are available in the configuration. A checkitig block with invalid CBC is never validated unless the entire contents of the checking block are replaced. An attempt to store into a checking block having invalid CBC, without replacing the entire checking block, leaves the data in the checking block (including the check bits) unchanged. Even when an instruction or a channel program input operation specifies that the entire contents of a checking block are to be replaced, validation mayor may not occur, depending on the operation and the model. Programming Note: Machine-check conditions may be reported for prefetched and unused data. Depending on the model, such situations may, or may not, be. successfully retried. For example, a BRANCH AND LINK (BALR) instruction which specifies an R2 field of zero will never branch, but on some models a prefetch of the location designated by register zero may occur: Access exceptions associated with this prefetch will not be reported. However, if an invalid checking-block code is detected, CPU retry may be attempted. Depending on the model, the prefetch may recur as part of the retry, and thus the retry will not be successful. Even when the CPU retry is successful, the performance degradation of such a retry is significant, and system recovery may be presented, normally with a failing-storage address. To avoid continued degradation, the program should initiate proceedings to eliminate use of the location and to validate the location. Programmed Validation of Storage Provided that an invalid CBC does not exist in the storage key associated with a 4K-byte block, the instruction TEST BLOCK causes the entire 4K-byte block to be set to zeros with a valid CBC, regardless of the current contents of the storage. TEST BLOCK thus removes an invalid CBC from a location in storage which has an intermittent, or one-time, failure. However, if a permanent failure exists in a portion of the storage, a subsequent fetch may fmd an invalid CBC. Invalid cae in Storage Keys Depending on the model, each storage key may be contained in a single checking block, or the accesscontrol and fetch-protection bits and the reference and change· bits may be in separate checking blocks. Figure 11-1 on page 11-8 describes the action taken when the storage key has invalid CBC. The figure indicates the action taken for the case when the access-control and fetch-protection bits are in one checking block and the reference and change bits are in a separate checking block. In machines where both fields are included in a single checking block, the action taken is the combination of the actions for each field in error, except that completion is pennitted only if an error in all affected fields permits completion. References to main storage to which key-controlled protection does not apply are treated as if an access key of zero is used for the reference. This includes such references as channel-program references during initial program loading and implicit references, such as interruption action and DAT-table accesses. Chapter 11. Machine-Check Handling 11-7 Action Taken on Invalid CBC Type of Reference For Access-Control and Fetch-Protection Bits For Reference and Change Bits SET STORAGE KEY EXTENDED Complete; validate. Complete; validate. INSERT STORAGE KEY EXTENDED PO; preserve. PO; preserve. RESET REFERENCE BIT EXTENDED PO or complete; preserve. PO; preserve. INSERT VIRTUAL STORAGE PO; preserve. KEY or TEST PROTECTION CPF; preserve. CPU pre fetch (informa- CPF; preserve. tion not used) CPF; preserve. Channel-program prefetch (information not used) IPF; preserve. IPF; preserve. Fetch, nonzero access MC; preserve. key MC or complete; preserve. Store l , nonzero access MC2; preserve. key MC and preserve; or comp1ete 3 and correct. Fetch, zero access key4 MC or complete; preserve. MC or complete; preserve. Store l , zero access key2 MC or complete; preserve. MC and preserve; or comp1ete 3 and correct. Explanation: 1 CPU virtua1- and logical-address store accesses are subject to page protection. When the page-protection bit is one, the location will not be changed; however, the machine may indicate a machine-check condition if the storage key or the data itself has invalid CBC. 2 The contents of the main-storage location are not changed. 3 The contents of the reference and change bits are set to ones if the "complete" action is taken. 4 The action shown for an access key 6f zero is also applicable to references to which key-controlled protection does not apply. Figure 11-1 (Part 1 of 2). Invalid CBC in Storage Keys 11-8 ESA/370 Principles of Operation Explanation (Continued): Complete The condition does not cause termination of the execution of the instruction and, unless an unrelated condition prohibits it, the execution of the instruction is completed, ignoring the error condition. No machine-check-damage conditions are reported, but system recovery may be reported. Correct The reference and change bits are set to ones with valid CBC. Preserve The contents of the entire checking block having invalid CBC are left unchanged. Validate The entire key is set to the new value with valid CBC. CPF Invalid CBC in the storage key for a CPU prefetch which is unused, or for instructions which do not examine the reference and change bits, may result in any of the following situations: The operation is completed; no machine-check condition is reported. The operation is completed; system recovery, with storage-key error uncorrected, is reported. Instruction-processing damage, with or without backup and with storage-key error uncorrected, is reported. IPF Invalid CBC in the storage key for a channel-program prefetch which is unused may result in any of the following: The I/O operation is completed; no machine-check condition is reported. The I/O operation is completed; system recovery, with storage-key error uncorrected, is reported. MC Same as PO for CPU references, but a channel-subsystem reference may result in the following combinations of I/O-error conditions and machine-check conditions: An I/O-error condition is reported; no machine-check condition is reported. An I/O-error condition is reported; system recovery, with or without storage-key error uncorrected, is reported. PO Instruction-processing damage, with or without backup and with or without storage-key error uncorrected, is reported. Note: When storage-key error uncorrected is reported, a failingstorage address mayor may not also be reported. Figure 11-1 (Part 2 of 2). Invalid CBC in Storage Keys Chapter ] 1. Machine-Check Handling 11-9 Invalid cae in Registers When invalid CBC is detected in a CPU register, a machine-check condition may be recognized. CPU registers include the general, floating-point, access, and control registers, the current PSW, the prefix register, the TOD clock, the CPU timer, and the clock comparator. When a machine-check interruption occurs, whether or not it is due to invalid CBC in a CPU register, the following actions affecting the CPU registers, other than the prefix register and the TOD-clock, are taken as part of the interruption. / 1. The contents of the registers are saved in assigned storage locations. Any register which is in error is identified by a corresponding validity bit of zero in the machine-checkinterruption code. Malfunctions detected during register saving do not result in additional machine-cheek-interruption conditions; instead, the correctness of all the information stored is indicated by the appropriate setting of the validity bits. 2. On some models, registers with invalid CBC are then validated, their actual contents being unpredictable. On other models, programmed validation is required. The prefix register and the TO D clock are not stored during a machine-check interruption, have no corresponding validity bit, and are not validated. On those models in which registers are not automatically validated as part of the machine-check interruption, a register with invalid CBC will not cause a machine-check-interruption condition unless the contents of the register are actually used. In these models, each register may consist of one or more checking blocks, but multiple registers are not included in a single checking block. When only a portion of a register is accessed, invalid CBC in the unused portion of the same register may cause a For machine-cheek-interruption condition. example, invalid CBC in the right half of a floatingpoint register may cause a machine-checkinterruption condition if a LOAD (LE) operation attempts to replace the left half, or short form, of the register. Invalid CBC associated with the prefix register cannot safely be reported by the machine-check 11-10 ESA/370 Principles of Operation interruption, since the interruption itself requires that the prefix value be applied to convert real addresses to the corresponding absolute addresses. Invalid CBC in the prefix register causes the CPU to enter the check-stop state immediately. On those models which do not validate registers during a machine-check interruption, the following instructions will cause validation of a register, provided the information in the register is not used before the register is validated. Other instructions, although they replace the entire contents of a register, do not necessarily cause validation. General registers are validated by BRANCH AND LINK (BAL, BALR) , BRANCH AND SAVE (BAS, BASR) , LOAD (LR), and LOAD ADDRESS. LOAD (L) and LOAD MULTIPLE validate if the operand is on a word boundary, and LOAD HALFWORD validates if the operand is on a halfword boundary. Floating-point registers are validated by LOAD (LDR) and, if the operand is on a doubleword boundary, by LOAD (LD). Access registers are validated by LOAD ACCESS MULTIPLE. Only the even-odd access-register pairs that are included in the set of access registers specified for the LOAD ACCESS MULTIPLE are validated. Thus, when a single access register is specified, or when a pair of access registers starting with an oddnumbered register is specified, no register is validated. Control registers may be validated either singly or in groups by using the instruction LOAD CONTROL. The CPU timer, clock comparator, and prefix register are validated by SET CPU TIMER, SET CLOCK COMPARATOR, and SET PREFIX, respectively. The TOD clock is validated by SET CLOCK if the TOD-clock control is in the enable-set position. Programming Note: Depending on the register, and the model, the contents of a register may be validated by the machine-check interruption or the model may require that a program execute a validating instruction after the machine-check interruption has occurred. In the case of the CPU timer, depending on the model, both the machine-check interruption and validating instructions may be required to restore the CPU timer to full working order. Check-Stop State In certain situations it is impossible or undesirable to continue operation when a machine error occurs. In these cases, the CPU may enter the check-stop state, which is indicated by the check-stop indicator. In general, the CPU may enter the check-stop state whenever an uncorrectable error or other malfunction occurs and the machine is unable to recognize a specific machine-check-interruption condition. The CPU always enters the check-stop state if any of the following conditions exists: • psw bit 13 is zero, and an exigent machine- check condition is generated. • During the execution of an interruption due to one exigent machine-check condition, another exigent machine-check condition is detected. • During a machine-check interruption, the machine-check-interruption code cannot be stored successfully, or the new psw cannot be fetched successfully. • Invalid CBC is detected in the prefix register. • A malfunction in the receiving CPU, which is detected after accepting the order, prevents the successful completion of a SIGNAL PROCESSOR order and the order was a reset, or the receiving CPU cannot determine what the order was. The receiving CPU enters the check-stop state. There may be many other conditions for particular models when an error may cause check stop. When the CPU is in the check-stop state, instructions and interruptions are not executed. The TOO clock is normally not affected by the check-stop state. The CPU timer mayor may not run in the check-stop state, depending on the error and the model. The start key and stop key are not effective in this state. The CPU may be removed from the check-stop state by CPU reset. In a multiprocessing configuration, a CPU entering the check -stop state generates a request for a malfunction-alert external interruption to all CPus in the configuration. Except for the reception of a malfunction alert, other CPus and the I/O system are normally unaffected by the check-stop state in a CPU. However, depending on the nature of the condition causing the check stop, other CPus may also be delayed or stopped, and channel subsystem and I/O activity may be affected. System Check Stop In a multiprocessing configuration, some errors, malfunctions, and damage conditions are of such severity that the condition causes all CPUs in the configuration to enter the check-stop state. This condition is called a system check stop. The state of the channel subsystem and I/O activity is unpredictable. Machine-Check Interruption A request for a machine-check interruption, which is made pending as the result of a machine check, is called a machine-check-interruption condition. There are two types of machine-check-interruption conditions: exigent conditions and repressible conditions. Exigent Conditions Exigent machine-check-interruption conditions are those in which damage has or would have occurred such that execution of the current instruction or interruption sequence cannot safely continue. Exigent conditions include two subclasses: instruction-processing damage and system damage. In addition to indicating specific exigent conditions, system damage is used to report any malfunction or error which cannot be isolated to a less severe report. Exigent conditions for instruction sequences can be either nullifying exigent conditions or terminating exigent conditions, according to whether the instructions affected are nullified or terminated. Exigent conditions for interruption sequences are terminating exigent conditions. The terms "nullification" and "termination" have the same meaning as that used in Chapter 6, "Interruptions," except that more than one instruction may be involved. Thus, a nullifying exigent condition indicates that the CPU has returned to the beginning of a unit of operation prior to the error. A terminating exigent condition means that the results of one or more instructions may have unpredictable values. Chapter 11. Machine-Check Handling 1t -1 t Repressible Conditions Repressible machine-check-interruption conditions are those in which the results of the instructionprocessing sequence have not been affected. Repressible conditions can be delayed, until the completion of the current instruction" or even longer, without affecting the integrity of CPU operation. Repressible conditions are of three groups: recovery, alert, and repressible damage. Each group includes one or more subclasses. A malfunction in the CPU, storage, or operator facilities which has been successfully corrected or circumvented internally without logical damage is called a recovery condition. Depending on the model and the type of malfunction, some or all recovery conditions may be discarded and not reported. Recovery conditions that are reported are grouped in one subclass, system recovery. A machine-cheek-interruption condition not directly related to a machine malfunction is called an alert condition. The alert conditions are grouped in two subclasses: degradation and warning. A malfunction resulting in an incorrect state of a portion of the system not directly affecting sequential CPU operation is called a repressible-damage condition. Repressible-damage conditions are grouped in six subclasses, according to the function affected: timing-facility damage, external damage, channel report pending, channel-subsystem damage, service-processor damage, and vector-facility failure. Programming Notes: 1. Even though repressible conditions are usually reported only at normal points of interruption, they may also be reported with exigent machine-check conditions. Thus, if an exigent machine-check condition causes an instruction to" be abnormally terminated and a machinecheck interruption occurs to report the exigent condition, any pending repressible conditions may also be reported. The meaningfulness of the validity bits depends on what exigent condition is reported. 2. Classification of damage as either exigent or repressible does not imply the severity of the damage. The distinction is whether action must be taken as soon as the damage is detected (exigent) or whether the CPU can continue processing (repressible). For a repressible 11-12 ESA/370 Principles of Operation condition, the current instruction can be completed before taking the machine-check interruption if the CPU is enabled for machine checks; if the CPU is disabled for machine checks, the condition can safely be kept pending until the CPU is again enabled for machine checks. For example, the CPU may be disabled for machine-check interruptions because it is handling an earlier instruction-processing-damage interruption. If, during that time, an 1/0 operation encounters a storage error, that condition can be kept pending because it is not expected to interfere with the current machine-check processing. If, however, the CPU also makes a reference to the area of storage containing the error before re-enabling machine-check interruptions, another instruction-processingdamage condition is created, which is treated as an exigent condition and causes the CPU to enter the check-stop state. 3. A repressible condition may be a floating condition. A floating repressible condition is eligible to cause an interruption on any CPU in the configuration. At the point when a CPU performs an interruption for a floating repressible condition, the condition is no longer eligible to cause an interruption on the remaining CPUs in the configuration. Interruption Action A machine-check interruption causes the following actions to be taken. The psw reflecting the point of interruption is stored as the machine-check old psw at reallocation 48. The contents of other registers are stored in register-save areas at real locations 216-231 and 288-511. Mter the contents of the registers are stored in register-save areas, depending on the model, the registers may be validated with the contents being unpredictable. A failing-storage address may be stored at real location 248, and an external-damage code may be stored at real location 244. A machine-checkinterruption code (MCIC) of eight bytes is placed at real location 232. The new psw is fetched from real location 112. Additionally, a machine-check logout may have occurred. The machine-generated addresses to access the old and new PSW, the MCIC, extended interruption information, and the fixedlogout area are all real addresses. The fields accessed during the machine-check interruption are summarized in Figure 11-2. Information Stored (Fetched) Old PSW New PSW (fetched) Machine-cheek-interruption code Register-save areas CPU timer Clock comparator Access registers 8-15 Floating-point registers 8, 2, 4, 6 General registers 8-15 Control registers 8-15 Extended interruption information External-damage code Failing-storage address Fixed-logout area Starting Length Location* in Bytes 8 8 48 112 232 8 216 224 288 352 384 448 8 8 64 32 64 64 244 248 256 4 4 16 Explanation: * All locations are in real storage. Figure 11-2. Machine-Cheek-Interruption Locations If the machine-check-interruption code cannot be stored successfully or the new PSW cannot be fetched successfully, the CPU enters the check-stop state. A repressible machine-check condition can initiate a machine-check interruption only if both psw bit 13 is one and the associated subclass mask bit, if any, in control register 14 is also one. When it occurs, the interruption does not terminate the execution of the current instruction; the interruption is taken at a normal point of interruption, and no program or supervisor-call interruptions are eliminated. If the machine check occurs during the execution of a machine function, such as a cpu-timer update, the tnachine-check interruption takes place after the machine function has been completed. When the CPU is disabled for a particular repressible machine-check condition, the condition remains pending. Depending on the model and the condition, multiple repressible conditions may be held pending for a particular subclass, or only one condition may be held pending for a particular subclass, regardless of the number of conditions that may have been detected for that subclass. When a repressible machine-check interruption occurs because the interruption condition is in a subclass for which the CPU is enabled, pending conditions in other subclasses may also be indicated in the same interruption code, even though the CPU is disabled for those subclasses. All indicated conditions are then cleared. If a machine check which is to be reported as a system-recovery condition is detected during the execution of the interruption procedure due to a previous machine-check condition, the systemrecovery condition may be combined with the other conditions, discarded, or held pending. An exigent machine-check condition can cause a machine-check interruption only when psw bit 13 is one. When a nullifying exigent condition causes a machine-check interruption, the interruption is taken at a normal point of interruption. When a terminating exigent condition causes a machinecheck interruption, the interruption terminates the execution of the current instruction and mayeliminate the program and supervisor-call interruptions, if any, .that would have occurred if execution had continued. Proper execution of the interruption sequence, including the storing of the old psw and other information, depends on the nature of the malfunction. When an exigent machine-check condition occurs during the execution of a machine function, such as a cpu-timer update, the sequence is not necessarily completed. If, during the execution of an interruption due to one exigent machine-check condition, another exigent machine check is detected, the CPU enters the check-stop state. If an exigent machine check is detected during an interruption due to a repressible machine-check condition, system damage is reported. When psw bit 13 is zero, an exigent machine-check condition causes the CPU to enter the check-stop state. Machine-cheek-interruption conditions are handled in the same manner regardless of whether the waitstate bit in the psw is one or zero: a machinecheck condition causes an interruption if the CPU is enabled for that condition. Machine checks which occur while the rate control is set to the instruction-step position are handled in the same manner as when the control is set to the process position; that is, recovery mechanisms are active, and machine-check interruptions occur when allowed. Machine checks occurring during a manual operation may be indicated to the operator, may generate a system-recovery condition, may result in system damage, or may cause a check stop, depending on the model. Chapter 11. Machine-Check Handling 11-13 Every reasonable attempt is made to limit the side effects of any machine check and the associated interruption. Normally, interruptions, as well as the progress Or'I/O operations, remain unaffected. The malfunction, however, may affect these activities, and, if the currently active psw has bit 13 set to one, the machine-check interruption will indicate the total extent of the damage caused, and not just the damage which originated the condition. Point of Interruption The point in the processing which is indicated by the interruption and used as a reference point by the machine to determine and indicate the validity of the status stored is referred to as the point of interruption. Because of the checkpoint capability in models with CPU retry, the interruption resulting from an exigent machine-cheek-interruption condition may indicate a point in the CPU processing sequence which is logically prior to the error. Additionally, the model may have some choice as to which point in the CPU processing sequence the interruption is indicated, and, in some cases, the status which can be indicated as valid depends on the point chosen. Only certain points in the processing may be used as a point of interruption. For repressible machine-check interruptions, the point of interruption must be after one unit of operation is completed and any associated program or supervisorcall interruption is taken, and before the next unit of operation is begun. Exigent machine-check conditions for instruction sequences are those in which damage has or would have occurred to the instruction stream. Thus, the damage can normally be associated with a point part way though an instruction, and this point is called the point of damage. In some cases there may be one or more instructions separating the point of damage and the point of interruption, and the processing associated with one or more instructions may be damaged. When the point of interruption is a point prior to the point of damage due to a nullifiable exigent machine-check condition' the point of interruption can be only at the same points as for repressible machine-check condi. tions. 11-14 ESAj370 Principles of Operation In addition to the point of interruption permitted for repressible machine-check conditions, the point of interruption for a terminating exigent machinecheck condition may also be after the unit of operation is completed but before any associated program or supervisor-call interruption occurs. In this case, a valid psw instruction address is dermed as that which would have been stored in the old psw for the program or supervisor-call interruption. Since the operation has been terminated, the values in the result fields, other than the instruction address, are unpredictable. Thus the validity bits associated with fields which are due to be changed by the instruction stream are meaningless when a terminating exigent machine-check condition is reported. When the point of interruption and the point of damage due to an exigent machine-check condition are separated by a checkpoint-synchronization function, the damage has not been isolated to a particular program, and system damage is indicated. Programming Note: When an exigent machinecheck-interruption condition occurs, the point of interruption which is chosen affects the amount of damage which must be indicated. An attempt is made, when possible, to choose a point of interruption which permits the minimum indication of damage. In general, the preference is the interruption point immediately preceding the error. When all the status information stored as a result of an exigent machine-cheek-interruption condition does not reflect the same point, an attempt is made, when possible, to choose the point of interruption so that the instruction address which is stored in the machine-check old psw is valid. Machine-Check-Interruption Code " On all machine-check interruptions, a machinecheck-interruption code (MCIC) is stored at the doubleword starting at real location 232 and has the format shown in Figure 11-3 on page 11-15. Bits in the MCIC which are not assigned, or not implemented by a particular model, are stored as zeros. S P S C E VD C S C v S S K D WM P I F E F G C S D D R o D D F G WP P K o S B o E C ESP SMA A 0 CPR R o T o 4 8 I AD E RA0 0 0 0 0 o0 0 0 13 16 24 26 31 CC 0 0 T C o 0 0 0 000 0 00000 e 0 0 ; 32 40 Bits o 1 2 4 5 6 7 8 9 10 11 13 14 16 17 18 19 20 21 22 23 24 26 27 28 29 31 32 33 34 46 47 Note: 46 48 56 63 Name System damage (SD) Instruction-processing damage (PD) System recovery (SR) Timing-facility damage (CD) External damage (ED) Vector-facility failure (VF) Degradation (DG) Warning (W) Channel report pending (CP) Service-processor damage (SP) Channel-subsystem damage (CK) Vector-facility source (VS) Backed up (B) Storage error uncorrected (SE) Storage error corrected (SC) Storage-key error uncorrected (KE) Storage degradation (DS) PSW-MWP validity (WP) PSW mask and key validity (MS) PSW program-mask and condition-code validity (PM) PSW-instruction-address validity (IA) Failing-storage-address validity (FA) External-damage-code validity (EC) Floating-point-register validity (FP) General-register validity (GR) Control-register validity (CR) Storage logical validity (ST) Indirect storage error (IE) Access-register validity (AR) Delayed-access exception (DA) CPU-timer validity (CT) Clock-comparator validity (CC) All other bits of the MCIC are unassigned and stored as zeros. Figure 11-3. Machine-Check Interruption-Code Format Subclass Bits 0-2 and 4-11 are the subclass bits which identify the type of machine-check condition causing the interruption. At least one of the subclass bits is stored as a one. When multiple errors have occurred, several subclass bits may be set to ones. System Damage Bit 0 (so), when one,· indicates that damage has occurred which cannot be isolated to one or more of the less severe machine-check subclasses. When system damage is indicated, the remaining bits in the machine-cheek-interruption code are not meaningful, and information stored in the register-save Chapter 11. Machine-Check Handling 11-15 areas and machine-check extended-interruption fields is not meaningful. System damage is a terminating exigent condition and has no subclass-mask bit. Instruction-Processing Damage Bit 1 (PD), when one, indicates that damage has occurred to the instruction processing of the CPU. The exact meaning of bit 1 depends on the setting of the backed-up bit, bit 14. When the backed-up bit is one, the condition is called processing backup. When the backed-up bit is zero, the condition is called processing damage. These two conditions are described in the section "Synchronous Machine-Cheek-Interruption Conditions" in this chapter. Instruction-processing damage can be a nullifying or a terminating exigent condition and has no subclass-mask bit. System Recovery Bit 2 (SR), when one, indicates that malfunctions were detected but did not result in damage or have been successfully corrected. Some malfunctions detected as part of an I/O operation may result in a system-recovery condition in addition to an I/o-error condition. The presence and extent of the system-recovery capability depend on the model. System recovery is a repressible condition. It is masked by the recovery subclass-mask bit, which is in bit position 4 of control register 14. Programming Notes: 1. System recovery may be used to report a failing-storage address detected by a CPU prefetch or by an 110 operation. 2. Unless the corresponding validity bits are ones, the indication of system recovery does not imply storage logical validity, or that the fields stored as a result of the machine-check interruption are valid. Timing-Facility Damage Bit 4 (CD), when one, indicates that damage has occurred to the TOD clock, the CPU timer, the clock comparator, or to the cpu-timer or clockcomparator external-interruption conditions. The timing~facility -damage machine-check condition IS set whenever any of the following occurs: 11-16 ESAj370 Principles of Operation 1. The TO D clock accessed by this CPU enters the error or not-operational state. 2. The CPU timer is damaged, and the CPU is enabled for cpu-timer external interruptions. On some models, this condition may be recognized even when the CPU is not enabled for cpu-timer interruptions. Depending on the model, the machine-check condition may be generated only as the CPU timer enters an error state. Or, the machine-check condition may be continuously generated whenever the CPU is enabled for cpu-timer interruptions, until the CPU timer is validated. 3. The clock comparator is damaged, and the CPU is enabled for clock-comparator external interruptions. On some models, this condition may be recognized even when the CPU is not enabled for clock-comparator interruptions. Timing-facility damage may also be set along with instruction-processing damage when an instruction which accesses the TOD clock, CPU timer, or clock comparator produces incorrect results. Depending on the model, the CPU timer or clock comparator may be validated by the interruption which reports the CPU timer or clock comparator as invalid. Timing-facility damage is a repressible condition. It is masked by the timing-facility subclass-mask bit, which is in bit position 6 of control register 14. Programming Note: Timing-facility-damage condi- tions for the CPU timer and the clock comparator are not recognized on most models when these facilities are not in use. The facilities are considered not in use when the CPU is disabled for the corresponding external interruptions (psw bit 7, or the subclass-mask bits, bits 20 and 21 of control register 0, are zeros), and when the corresponding set and store instructions are not executed. Timing-facility-damage conditions that are already pending remain pending, however, when the CPU is disabled for the corresponding external interruption. Timing-facility-damage conditions due to damage to the TOD clock are always recognized. External Damage Bit 5 (ED), when one, indicates that damage has occurred during operations not directly associated with processing the current instruction. When bit 5, external damage, is one and bit 26, external-damage-code validity, is also one, the external-damage code has been stored to indicate, in more detail, the cause of the external-damage machine-check interruption. When the external damage cannot be isolated to one or more of the conditions as defmed in the external-damage code, or when the detailed indication for the condition is not implemented by the model, external damage is indicated with bit 26 set to zero. The presence and e'xtent of reporting external damage, depend on the model. External damage is a repressible condition. It is masked by the external-damage subclass-mask bit, which is in bit position 6 of conttol register 14. Vector-Facility Failure Bit 6 (VF) of the machine-check-interruption code, when one, indicates that the vector facility has failed to such an extent that the service processor has made the facility not available. This bit may be set to' one, regardless of whether the vector-control bit, bit 14 of control register 0, is one or zero. Vector-facility failure is a repressible condition and has no subclass-mask bit. Degradation Bit 7 (DG), when one, indicates that continuous degradation of system performance, more serious than that indicated by system recovery, has occurred. Degradation may be reported when system-recovery conditions exceed a machinepreestablished threshold or when unit deletion has occurred. The presence and extent of the degradation-report capability depend on the model. Degradation is a repressible condition. It is masked by the degradation subclass-mask bit, which is in bit position 5 of control register 14. Warning Bit 8 (w), when one, indicates that damage is imminent in some part of the system (for example, that power is about to fail, or that a loss of cooling is. occurring). Whether warning conditions are recognized depends on the model. If the condition responsible for the imminent damage is removed before the interruption request is honored (for example, if power is restored), the request does not remain pending, and no interruption occurs. Conversely, the request is not cleared by the interruption, and, if the condition persists; more than one interruption may result from the same condition. Warning is a repressible condition. It is masked by the warning subclass-mask bit, which is in bit position 7 of control register 14. Channel Report Pending Bit 9 (cP), when one, indicates that a channel report, consisting of one or more channel-report words, has been made pending, and the contents of the channel-report words describe, in further detail, the effect of the malfunction and the results of analA channel report ysis or action performed. becomes pending when one of the following conditions has occurred: 1. Channel-subsysteln recovery has been completed. The channel-subsystem recovery may have been initiated with no prior notice to the program or may have been a result of a condition previously reported to the program. 2. The function specified by RESET CHANNEL PATH has been completed. The channel-report words which make up the channel report may be cleared, one at a time, by execution of the instruction STORE CHANNEL REPORT WORD, which is described in Chapter 14, "I/O Instructions." Bit 9 is meaningless when channel-subsystem damage is reported. Channel report pending is a floating repressible condition. It is masked by the channel-reportpending subclass-mask bit, which is in bit position 3 of control register 14. Service-Processor Damage Bit 10 (sp), when one, indicates that damage ha~ occurred to the service processor. Service-processor damage may be made pending at all CPus in the configuration, or it may be detected independently by each CPU. The presence and extent of reporting service-processor damage depend on the model. Service-processor damage is a repressible condition and has no subclass-mask bit. Channel-Subsystem Damage Bit 11 (CK), when one, indicates that an error or malfunction has occurred in the channel subsystem, or that the channel subsystem is in the check-stop state. The channel subsystem enters the check-stop state when a malfunction occurs which is so severe that the channel subsystem cannot continue, or if power is lost in the channel subsystem. Chapter 11. Machine-Check Handling 11-17 Channel-subsystem damage is a floating repressible condition and has no subclass-mask bit. Subclass Modifiers Bits 13 (vs), 14 (B), and 34 (DA) of the machinecheck-interruption code act as modifiers to the subclass bits. Vector-Facility Source Bit 13 (vs) of the machine-check-interruption code, when one, indicates that the vector facility is the source of the reported machine-check condition. Vector-facility source is reported together with instruction-processing damage. When this bit is one, the contents of vector-facility registers may have been damaged. This bit may be set to one regardless of whether the vector-control bit, bit 14 of control register 0, is . one or zero. Bit 13 is not meaningful when vector-facility failure is reported. Backed Up Synchronous Machine-Check-Interruption Conditions The instruction-processing damage and backed-up bits, bits 1 and 14 of the machine-checkinterruption code, identify, in combination, two conditions. Bit 1 Bit 14 Name of Condition 1 o 1 1 Processing damage· Processing backup Processing Backup The processing-backup condition indicates that the point of interruption is prior to the point, or points, of error. This is a nullifying exigent condition. When all of the other CPU -related-damage subclasses and modifiers of the machine-checkinterruption code are zero and all of the validity bits associated with CPU status are indicated as valid, the machine has successfully returned to a checkpoint prior to the malfunction, and no damage has yet occurred to the CPU. Bit 14 (B), when one, indicates that the point of interruption is at a checkpoint before the point of error. This bit is meaningful only when the instruction-processing-damage bit, bit 1, is also set to one. The presence and extent of the capabili~y to indicate a backed-up condition depend on the model. The subclass bits which must be zero for this to be the case are as follows: Delayed Access Exception The subclass-modifier bits which must be zero for this to be the case are as follows: Bit 34 (DA), when one, indicates that an access exception was detected during a storage access using DAT when no such exception was detected by an earlier test for access exceptions. Bit 34 is a modifier to instruction-processing damage (bit 1) and is meaningful only when bit 1 of the machine-check-interruption code is one. When bit 1 is zero, bit 34 has no meaning. The presence and extent of reporting delayed access exception depend on the model. Programming Note: The occurrence of a delayed access exception normally indicates that the program is using an improper procedure to update the DAT tables. 11-18 ESA/370 Principles of Operation MCIC Bit Name o System damage 4 Timing-facility damage 6 Vector-facility failure MCIC Bit Name 13 Vector-facility source 34 Delayed-access exception The validity bits in the machine-check-interruption code which must be one for this to be the case are as follows: MCIC Bit Fields Covered by Bit 20 psw MWP bits 21 psw mask and key 22 psw program mask and condition code 23 psw instruction address 27 Floating-point registers 28 General registers 29 Control registers 31 Storage logical validity (result fields within current checkpoint interval) 33 46 47 Access registers CPU timer Clock comparator Programming Note: The processing-backup condition is reported rather than system recovery to indicate that a malfunction or failure stands in the way of continued operation of the Cpu. The malfunction has not been circumvented, and damage would have occurred if instruction processing had continued. Processing Damage The processing-damage condition indicates that damage has occurred to the instruction processing of the cpu. The point of interruption is a point beyond some or all of the points of damage. Processing damage is a terminating exigent condition; therefore, the contents of result fields may be unpredictable and still indicated as valid. Processing damage may include malfunctions in program-event recording, monitor call, tracing, access-register translation, and dynamic address translation. Processing damage causes any supervisor-call-interruption condition and programinterruption condition to be discarded. However, the contents of the old psw and interruption-code locations for these interruptions may be set to unpredictable values. Storage Errors Bits 16-18 of the machine-cheek-interruption code are used to indicate an invalid CBC or a near-valid CBC detected in main storage or an invalid CBC in a storage key. Bit 19, storage degradation, may be indicated concurrently with bit 17. The failingstorage-address field, when indicated as valid, identifies a location within the storage checking block containing the error, or, for storage-key error uncorrected, within the block associated with the storage key. Bit 32, indirect storage error, may be set to one to indicate that the location designated by the failing-storage address is not the original source of the error. The storage-error-uncorrected and storage-keyerror-uncorrected bits do not in themselves indicate the occurrence of damage because the error detected may not have affected a result. The portion of the configuration affected by an invalid CBC is indicated in the subclass field of the machine-cheek-interruption code. Storage errors detected for a channel program, when indicated as I/o-error conditions, may also be reported as system recovery. CBC errors that occur in storage or in the storage key and that are detected on prefetched or unused data for a cpu program mayor may not be reported, depending on the model. Storage Error Uncorrected Bit 16 (SE) , when one, indicates that a checking block in main storage contained invalid CBC and that the information could not be corrected. The contents of the checking block in main storage have not been changed. The location reported may have been accessed or 'prefetched for this cpu or another CPU or a channel program, or it may have been accessed as the result of a model-dependent storage access. Storage Error Corrected Bit 17 (sc), when one, indicates that a checking block in main storage contained near-valid CBC and that the information has been corrected before being used. Depending on the model, the contents of the checking block in main storage mayor may not have been restored to valid CBC. The location reported may have been accessed or prefetched for this CPU or for another CPU or for a channel program, or it may have been accessed as the result of a model-dependent storage access. The presence and extent of the storage-error-correction capability depend on the model. This indication mayor may not be accompanied by an indication of storage degradation, bit 19 (os). Storage-Key Error Uncorrected Bit 18 (KE), when one, indicates that a storage key contained invalid CBC and that the information could not be corrected. The contents of the checking block in the storage key have not been changed. The storage key may have been accessed or prefetched for this CPU or for another cpu or for a channel program, or it may have been accessed as the result of a model-dependent storage access. Storage Degradation Bit 19 (os), when one, indicates that performance degradation has occurred for the reported storageerror-corrected condition. Storage degradation indicates that although the associated storage error has been corrected, the correction process involved a substantial amount of time. Thus, this bit indicates that use of the associated block of storage should be avoided, if possible. Chapter 11. Machine-Check Handling 11-19 The indication of storage degradation has meaning only when bit 17, storage error corrected, is also one. The presence and extent of reporting storage degradation depend on the model. Programming Note: Because storage degradation is reported with storage error corrected and, further-, more, because storage error corrected is normally reported with system recovery, the recovery subclass mask, bit 4 of control register 14, should be set to one in order for storage degradation to be indicated. Indirect storage Error Bit 32 (IE), when one, indicates that the physical main-storage location identified by the failingstorage address is not the original source of the error. Instead, the error originated in another level of the storage hierarchy and has been propagated to the current physical-storage portion of the storage hierarchy. Bit 32 is meaningful only when bit 16 or 18 (storage error uncorrected or storage-key error uncorrected) of the machine-check-interruption code is one. When bits 16 and 18 are both zeros, bit 32 has no meaning. For errors originating outside the storage hierarchy, the attempt to store is rejected, and the appropriate error indication is presented. When an error is detected during implicit movement of information inside the storage hierarchy, the action is not rejected and reported in this manner because the movement may be asynchronous and may be initiated as the result of an attempt to access completely unrelated information. Instead, errors in the contents of the source during implicit moving of information from one portion of the storage hierarchy to another may be preserved in the target area by placing a special invalid CBC in the checking block associated with the target location. These propagated errors, when detected later, are reported as indirect storage errors. The original source of such an error may have been in a cache associated with an I/O processor or a CPU, or the error may have been the result of a data-path failure in transmitting data from one portion of the storage hierarchy to another. Additionally, a propagated error may be generated during the movement of data from one physical portion of storage to another as the result of a storage-reconfiguration action. The presence and extent of reporting indirect storage error depend on the model. Programming Note: See the programming notes under TEST BLOCK in Chapter 10, "Control Instructions," for the action which should be taken after storage errors are reported. Machine-Check Interruption-Code Validity Bits Bits 20-24, 26-29, 31, 33, 46, and 47 of the machine-check-interruption code are validity bits. Each bit indicates the validity of a particular field in storage. With the exception of the storage-Iogicalvalidity bit (bit 31), each bit is associated with a field stored during the machine-check interruption. When a validity bit is one, it indicates that the saved value placed in the corresponding storage field is valid with respect to the indicated point of interruption and that no error was detected when the data was stored. When a validity bit is zero, one or more of the following conditions may have occurred: the original information was incorrect, the original information had invalid CBC, additional malfunctions were detected while storing the information, or none or only part of the information was stored. Even though the information is unpredictable, the machine attempts, when possible, to place valid CBC in the storage field and thus reduce the possibility of additional machine checks being caused. The validity bits for the floating-point registers, general registers, control registers, CPU timer, and clock comparator indicate the validity of the saved value placed in the corresponding save area. The information in these registers after the machinecheck interruption is not necessarily correct even when the correct value has been placed in the save area and the validity bit set to one. The use of the registers and the operation of the facility associated with the control registers, CPU timer, and clock comparator, are unpredictable until these registers are, validated. (See the section "Invalid CBC in Registers" earlier in this chapter.) PSW-MWP Validity Bit 20 (wP), when one, indicates that bits 12-15 of the machine-check old psw are correct. PSW Mask and Key Validity Bit 21 (MS), when one, indicates that the system mask, psw key, and miscellaneous bits of the machine-check old psw are correct. Specifically, this bit covers bits 0-11, 16, 17, and 24-31 of the psw. 11-20 ESA/370 Principles of Operation PSW Program-Mask and Condition-Code Validity Bit 22 (PM), when one, indicates that the program mask and condition code of the machine-check old psw are correct. PSW-Instruction-Address Validity Bit 23 (IA), when one, indicates that the addressing mode and instruction address (bits 32-63) of the machine-check old psw are correct. Falling-Storage-Address Validity Bit 24 (FA), when one, indicates that a correct failing-storage address has been placed at real location 248 after a storage-error-uncorrected, storage-key-error-uncorrected, or storage-errorcorrected condition has occurred. The presence and extent of the capability to identify the failingstorage location depend on the model. When no such errors are reported, that is, bits 16-18 of the machine-check-interruption code are zeros, the failing-storage address is meaningless, even though it may be indicated as valid. External-Damage-Code Validity Bit 26 (EC) , when one, and provided that bit 5, external damage, is also one, indicates that a valid external-damage code has been stored in the word at location 244. When bit 5 is zero, bit 26 has no meaning. Floating-Polnt-Register Validity Bit 27 (FP), when one, indicates that the contents of the floating-point-register save area at real locations 352-383 reflect the correct state of the floating-point registers at the point of interruption. General-Register Validity Bit 28 (OR), when one, indicates that the contents of the general-register save area at real locations 384-447 reflect the correct state of the general registers at the point of interruption. Control-Register Validity Bit 29 (CR), when one, indicates that the contents of the control-register save area at real locations 448- 511 reflect the correct state of the control registers at the point of interruption. Storage Logical Validity Bit 31 (ST), when one, indicates that the storage locations, the contents of which are modified by the instructions being executed, contain the correct information relative to the point of interruption. That is, all stores before the point of interruption are completed, and all stores, if any, after the point of interruption are suppressed. When a store before the point of interruption is suppressed because of an invalid CBC, the storage-logicalvalidity bit may be indicated as one, provided that the invalid CBC has been preserved as invalid. When instruction-processing damage is indicated but processing backup is not indicated, the storagelogical-validity bit has no tneaning. Storage logical validity reflects only the instructionprocessing activity and does not reflect errors in the state of storage as the result of I/O operations, or of the storing of the old psw and other interruption information. Access-Register Validity Bit 33 (AR), when one, indicates that the contents of the access-register save area at real locations 288-351 reflect the correct state of the access registers at the point of interruption. CPU-Timer Validity Bit 46 (CT), when one, indicates that the CPU timer is not in error and that the contents of the cpu-timer save area at reallocation 216 reflect the correct state of the CPU timer at the time the interruption occurred. Clock-Comparator Validity Bit 47 (cc), when one, indicates that the clock comparator is not in error and that the contents of the clock-comparator save area at real location 224 reflect the correct state of the clock comparator. Programming Note: The validity bits must be used in conjunction with the subclass bits and the backed -up bit in order to determine the extent of the damage caused by a machine-check condition. No damage has occurred to the system when all of the following are true: • The four psw-validity bits, the four registervalidity bits, the two timing-facility-validity bits, and the storage-logical-validity bit are all ones. • Subclass bits 0, 4, 5, 6, 10, and 11 are zeros. Chapter 11. Machine-Check Handling 11-21 • The instruction-processing-damage bit is zero or, if one, the backed-up bit is also one. External-Damage Code • The vector-facility-source bit and the delayedaccess-exception bit are zeros. The word at real location 244 is the externaldamage code. This field, when implemented and indicated as valid, describes the cause of external damage. The field is valid only when the externaldamage bit and the external-damage-validity bit (bits 5 and 26 in the machine-check-interruption code) are both ones. The presence and extent of reporting an external-damage code depend on the model. Machine-Check Extended Interruption Information As part of the machine-check interruption, in some cases, extended interruption information is placed in fixed areas assigned in storage. The contents of registers associated with the CPU are placed in register-save areas. For external damage, additional information is provided for some models by storing an external-damage code. When storage error uncorrected, storage error corrected, or storage-key error uncorrected is indicated, the failing-storage address is saved. Each of these fields has associated with it a validity bit in the machine-cheek-interruption code. If, for any reason, the machine cannot store the proper information in the field, the associated validity bit is set to zero. Register-Save Areas As part of the machine-check interruption, the current contents of the CPU registers, except for the prefix register and the TOO clock, are stored in six register-save areas assigned in storage. Each of these areas has associated with it a validity bit in the machine-check-interruption code. If, for any reason, the machine cannot store the proper information in the field, the associated validity bit is set to zero. The following are the six sets of registers and the real locations in storage where their contents are saved during a machine-check interruption. Locations 216-223 224-231 288-351 352-383 384-447 448-511 Registers CPU timer Clock comparator Access registers 0-15 Floating-point registers 0, 2, 4, 6 General registers 0-15 Control registers 0-15 The external-damage code has the following format: o0 0 0 0 xx 0 0 0 NF 0 I~ 0 0 '--------'--~-I o 8 10 31 Expanded storage Not Operational (XN): Bit 8, when one, indicates that the controller associated with some or all of the expanded storage in the configuration has become not operational. Expanded-storage-not-operational conditions are reported to all CPus in the configuration. Expanded-Storage Control Failure (XF): Bit 9, when one, indicates that a malfunction has been detected in a controller associated with some or all of the expanded storage in the configuration. When expanded-storage control failure is indicated, the blocks of the expanded storage contain either the proper contents or \a preserved error. Expanded-storage-control-failure conditions are reported to all CPus in the configuration. Reserved: Bits 0-7 and 10-31 are reserved for future expansion and are always set to zeros. Failing-Storage Address When storage error uncorrected, storage error corrected, or storage-key error uncorrected is indicated in the machine-cheek-interruption code, the associated address, called the failing-storage address, is stored in bit positions 1-31 of the word at real location 248. Bit 0 of that word is set to zero. The field is valid only if the failing-storage-address validity bit, bit 24 of the machine-checkinterruption code, is one. In the case of storage errors, the failing-storage address may designate any byte within the checking 11-22 ESA/370 Principles of Operation block. For storage-key error uncorrected, the failing-storage address may designate any address within the block of storage associated with the storage key that is in error. When an error is detected in more than one location before the interruption, the failing-storage address may designate any of the failing locations. The address stored is an absolute address; that is, the value stored is the address that is used to reference storage after dynamic address translation and prefixing have been applied. Handling of Machine-Check Conditions Floating Interruption Conditions An interruption condition which is made available to any CPU in a multiprocessing configuration is called a floating interruption condition. The frrst CPU that accepts the interruption clears the interruption condition, and it is no longer available to any other CPU in the configuration. Floating interruption conditions include servicesignal external-interruption and I/o-interruption conditions. Two machine-cheek-interruption conditions, channel report pending and channelsubsystem damage, are floating interruption conditions. Depending on the model, some machine-check-interruption conditions associated with system recovery and warning may also be floating interruption conditions. A floating interruption is presented to the frrst CPU in the configuration which is enabled for the interruption condition and can accept the interruption. A CPU cannot accept the interruption when it is in the check-stop state, has an invalid prefix, is perfonning an unending string of interruptions due to a psw-format error of the type that is recognized early, or is in the stopped state. However, a CPU with the rate control set to instruction step can accept the interruption when the start key is activated. Programming Note: When a CPU enters the check-stop state in a multiprocessing configuration, the program on another CPU can detennine whether a floating interruption may have been reported to the failing CPU and then lost. This can be accomplished if the interruption program places zeros in the real storage locations containing old psws and interruption codes after the interruption has been handled (or has been moved into another area for later processing). Mter a CPU enters the check-stop state, the program in another CPU can inspect the old-psw and interruption-code locations of the failing CPU. A nonzero value in an old psw or interruption code indicates that the CPU has been interrupted but the program did not complete the handling of the interruption. Floating Machlne-Check-Interruption Conditions Floating machine-cheek-interruption conditions are reset only by the manually initiated resets through the operator facilities. When a machine check occurs which prohibits completion of a floating machine-check interruption, the interruption condition is no longer considered a floating interruption condition, and system damage is indicated. Floating 1/0 Interruptions The detection of a machine malfunction by the channel subsystem, while in the process of presenting an I/o-interruption request for a floating I/O interruption, may be reported as channel report pending or as channel-subsystem damage. Detection of a machine malfunction by a CPU, while in the process of accepting a floating I/O interruption, is reported as system damage. Machine-Check Masking All machine-check interruptions are under control of the machine-check mask, psw bit 13. In addition, some machine-check conditions are controlled by subclass masks in control register 14. The exigent machine-check conditions (system damage and instruction-processing damage) are controlled only by the machine-check mask, psw bit 13. When psw bit 13 is one, an exigent condition causes a machine-check interruption. When psw bit 13 is zero, the occurrence of an exigent machine-check condition causes the CPU to enter the check-stop state. The repressible machine-check conditions, except vector-facility failure, channel-subsystem 'damage, and service-processor damage, are controlled both by the machine-check mask, psw bit 13, and by five subclass-mask bits in control register 14. If psw bit 13 is one and one of the subclass-mask bits is one, the associated condition initiates a machinecheck interruption. If a subclass-mask bit is zero, the associated condition does not initiate an interruption but is held pending. However, when a Chapter 11. Machine-Check Handling 11-23 machine-check interruption is initiated because of a condition for which the CPU is enabled, those conditions for which the CPU is not enabled may be presented along with the condition which initiates the interruption. All conditions presented are then cleared. Control register 14 contains mask bits that specify whether certain conditions can cause machinecheck interruptions; it has the following format: CRDEW MMMMM e 3 Degradation Subclass Mask Bit 5 (OM) of control register 14 controls degradation interruption conditions. This bit is initialized to zero. External-Damage Subclass Mask Bit 6 (EM) of control register 14 controls timingfacility-damage and external-damage interruption conditions. This bit is initialized to one. 7 Bits 3-7 of control register 14 are the subclass masks for repressible machine-check conditions. In addition, bit 0 of control register 14 is initialized to one, but is otherwise ignored by the machine. Programming Note: The program should avoid, whenever possible, operating with psw bit 13, the machine-check mask, set to zero, since any exigent machine-check condition which is recognized during this situation will cause the CPU to enter the check-stop state. In particular, the program should avoid executing I/O instructions or allowing I/O interruptions with psw bit 13 zero. Channel-Report-Pending Subclass Mask Bit 3 (eM) of control register 14 controls channe1report-pending interruption conditions. This bit is initialized to zero. 11-24 Recovery Subclass Mask Bit 4 (RM) of control register 14 controls systemrecovery interruption conditions. This bit is initialized to zero. ESAj370 Principles of Operation Warning Subclass Mask Bit 7 (WM) of control register 14 controls warning interruption conditions. This bit is initialized to zero. Machine-Check Logout As part of the machine-check interruption, some models may place model-dependent information in the fixed-logout area. This area is 16 bytes in length and starts at reallocation 256. Summary of Machine-Check Masking A summary of machine-check masking is given in Figure 11-4 on page 11-25 and Figure 11-5 on page 11-25. Machine-Check Condition MCIC Bit 0 1 2 4 5 6 7 8 9 10 11 Subclass System damage Instruction-processing damage System recovery Timing-facility damage External damage Vector-facility failure Degradation Warning Channel report pending Service-processor damage Channel-subsystem damage SubClass Mask Action When CPU Disabled for Subclass - Check stop Check stop RM EM EM Y P P P P P P P P - OM WM CM - Ex~lanation: - The condition does not have a subclass mask. P Indication is held pending. y Indication may be held pending or may be discarded. CM Channel-report-pending subclass mask (bit 3 of CR14). OM Degradation subclass mask (bit 5 of CR14). EM External-damage subclass mask (bit 6 of CR14). RM Recovery subclass mask (bit 4 of CR14). WM Warning subclass mask (bit 7 of CR14). Figure 11-4. Machine-Cheek-Condition Masking Bit Descri pti on Control State of Bit Register 14 on Initial Bit Position CPU Reset Channel-report-pending subclass mask Recovery subclass mask Degradation subclass mask External-damage subclass mask Warning subclass mask 3 4 5 6 7 0 0 0 1 0 Figure 11-5. Machine-Check Control-Register Bits Chapter 11. Machine-Check Handling 11-25 Chapter 12. Operator Facilities Manual Operation . . . . . . Basic Operator Facilities .., Address-Compare Controls Alter-and -Display Controls Architectural-Mode Indicator Architectural-Mode-Selection Controls Check-Stop Indicator IML Controls Interrupt Key Load Indicator Load-Clear Key Load- Nonnal Key Load-Unit-Address Controls 12-1 12-1 12-1 12-2 12-2 12-2 12-2 12-2 12-3 12-3 12-3 12-3 12-3 Manual Operation The operator facilities provide functions for the manual operation and control of the machine. The functions include operator-to-machine communication, indication of machine status, control over the setting of the Ton clock, initial program loading, resets, and other manual controls for operator intervention in nonnal machine operation. A model may provide additional operator facilities which are not described in this chapter. Examples are the means to indicate specific error conditions in the equipment, to change equipment configurations, and to facilitate maintenance. Furthennore, controls covered in this chapter may have additional settings which are not described here. Such additional facilities and settings may be described in the appropriate System Library publication. Manual Indicator Power Controls Rate Control Restart Key Start Key Stop Key Store-Status Key System-Reset-Clear Key System-Reset- Nonnal Key Test Indicator TOD-Clock Control Wait Indicator Multiprocessing Configurations 12-3 12-3 12-3 12-4 12-4 12-4 12-4 12-4 12-5 12-5 12-5 12-5 12-5 A machine malfunction that prevents a manual operation from being perfonned correctly, as defined for that operation, may cause the CPU to enter the check-stop state or give some other indication to the operator that the operation has failed. Alternatively, a machine malfunction may cause a machine-check-interruption condition to be recognized. Basic Operator Facilities Address-Compare Controls The address-compare controls provide a way to stop the CPU when a preset address matches the address used in a specified type of main-storage reference. Most models provide, in association with the operator facilities, a console device which may be used as an 110 device for operator communication with the program; this console device may also be used to implement some or all of the facilities described in this chapter. One of the address-compare controls is used to set up the address to be compared with the storage address. The operator facilities may be implemented on different models in various technologies and configurations. On some models, more than one set of physical representations of some keys, controls, and indicators may be provided, such as on multiple local or remote operating stations, which may be effective concurrently. 1. The nonnal position disables the addresscompare operation. Another control provides at least two positions to specify the action, if any, to be taken when the address match occurs: 2. The stop position causes the CPU to enter the stopped state on an address match. When the control is in this setting, the test indicator is on. Depending on the model and the type of reference, pending I/O, external, and machine-check interruptions mayor may not be taken before entering the stopped state. Chapter 12. Operator F acUities 12-1 A third control may specify the type of storage reference for which the address comparison is to be made. A model may provide one or more of the following positions, as well as others: 1. The any position causes the address comparison to be performed on all storage references. manual indicator may be turned off temporarily, and the start and restart keys may be inoperative. Addresses used to select storage locations for alterand-display operations are real addresses. The capability of specifying logical, virtual, or absolute addresses may also be provided. 2. The data-store position causes address compar- ison to be performed when storage is addressed to store data. 3. The I/O position causes address comparison to be performed when storage is addressed by the channel subsystem to transfer data or to fetch a channel-command or indirect-data-address word. Whether references to the measurement block, interruption-response block, channelpath-status word, channel-report word, subchannel-status word, subchannelinformation block, and operation-request block cause a match to be indicated depends on the model. 4. The instruction-address position causes address comparison to be performed when storage is addressed to fetch an instruction. The rightmost bit of the address setting mayor may not be ignored. The match is indicated only when the frrst byte of the instruction is fetched from the selected location. It depends on the model whether a match is indicated when fetching the target instruction of EXECUTE. Depending on the model and the type of reference, address comparison may be performed on virtual, real, or absolute addresses, and it may be possible to specify the type of address. In a multiprocessing configuration, it depends on the model whether the address setting applies to one or all CPUs in the configuration and whether an address match causes one or all cpus in the configuration to stop. Alter-and-Display Controls The operator facilities provide controls and procedures to permit the operator to alter and display the contents of locations in storage, the storage keys, the general, floating-point, access, and control registers, the prefix, and the psw. Before alter-and-display operations may be performed, the CPU must frrst be placed in the stopped state. During alter-and-display operations, the 12-2 ESA/370 Principles of Operation Architectural-Mode Indicator The architectural-mode indicator shows the architectural mode of operation (the ESA/370 mode or some other mode) selected by the last architecturalmode-selection operation. Architectural-Mode-Selection Controls / The architectural-mode-selection controls provide for the selection of either the ESA/370 architectural mode of operation or, possibly, some otherarchitectural mode of operation. Depending on the model, the architectural-mode selection may be provided as part of the 1M L operation or may be a separate operation. As part of the architectural-mode-selection process, all CPus and the associated channel-subsystem components in a particular configuration are placed in the same architectural mode. Check-Stop Indicator The check-stop indicator is on when the CPU is in the check-stop state. Reset operations normally cause the CPU to leave the check-stop state and thus tum off the indicator. The manual indicator may also be on in the check-stop state. IML Controls The IML controls provided with some models perform initial microprogram loading (IML). The IML operation, when provided, may be used to select the ESA/370 mode or, possibly, some other mode of operation. When· the IML operation is completed, the state of the affected CPus, channel subsystem, storage,. and operator facilities is the same as if a power-on reset had been performed, except that the value and state of the TOO clock are not changed. The IML controls are effective while the power is on. Interrupt Key Load-Unit-Address Controls When the interrupt key is activated, an externalinterruption condition indicating the interrupt key is generated. (See the section "Interrupt Key" in Chapter 6, "Interruptions.") The load-unit-address controls specify four hexadecimal digits, which provide the device number used for initial program loading. For details, see the section "Initial Program Loading" in Chapter 4, "Control." The interrupt key is effective when the CPU is in the operating or stopped state. It depends on the model whether the interrupt key is effective when the CPU is in the load state. Load Indicator The load indicator is on during initial program loading, indicating that the CPU is in the load state. The indicator goes on for a particular CPU when the load-clear or load-normal key is activated for that CPU and the corresponding operation is started. It goes off after the new psw is loaded successfully. For details, see the section "Initial Program Loading" in Chapter 4, "Control." Load-Clear Key Activating the load-clear key causes a reset operation to be performed and initial program loading to . be started by using the I/O device designated by the load-unit-address controls. Clear reset is performed on the configuration. For details, see the sections "Resets" and "Initial Program Loading" in Chapter 4, "Control." The load-clear key is effective when the CPU is in the operating, stopped, load, or check-stop state. Load-Normal Key Activating the load-normal key causes a reset operation to be performed and initial program loading to be started by using the I/O device designated by the load-unit-address controls. Initial CPU reset is performed on the CPU for which the load-normal key was activated, CPU reset is propagated to all other CPUs in the configuration, and a subsystem reset is performed on the remainder of the configuration. For details, see the sections "Resets" and "Initial Program Loading" in Chapter 4, "Control." The load-normal key is effective when the CPU is in the operating, stopped, load, or check-stop state. Manual Indicator The manual indicator is on when the CPU is in the stopped state. Some functions and several manual controls are effective only when the CPU is in the stopped state. Power Controls The power controls are used to turn the power on and off. The CPus, storage, channel subsystem, operator facilities, and I/O devices may all have their power turned on and off by common controls, or they may have separate power controls. When a particular unit has its power turned on, that unit is reset. The sequence is performed so that no instructions or I/O operations are performed until explicitly specified. The controls may also permit power to be turned on in stages, but the machine does not become operational until power on is complete. When the power is completely turned on, an IML operation is performed on models which have an IML function. A power-on reset is then initiated (see the section "Resets" in Chapter 4, "Control"). It depends on the model whether the architectural mode of operation can be selected when the power is turned on, or whether the mode-selection controls have to be used to change the mode after the power is on. Rate Control The setting of the rate control determines the effect of the start function and the manner in which instructions are executed. The rate control has at least two positions~ The normal position is the process position. Another position is the instruction-step position. When the rate control is set to the process position and the start function is performed, the CPU starts operating at normal speed. When the rate control is set to the instruction-step position and the wait-state bit Chapter 12. Operator F acUities 12-3 is zero, one instruction or, for interruptible instructions, one unit of operation is executed, and all pending allowed interruptions are taken before the CPU returns to the stopped state. When the rate control is set to the instruction-step position and the wait-state bit is one, no instruction is executed, but all pending allowed interruptions are taken before the CPU returns to the stopped state. For details, see the section "Stopped, Operating, Load, and Check-Stop States" in Chapter 4, "Control. " The test indicator is on while the rate control is not set to the process position. If the setting of the rate control is changed while the CPU is in the operating or load state, the results are unpredictable. Restart Key Activating the restart key initiates a restart interruption. (See the section "Restart Interruption" in Chapter 6, "Interruptions.") The restart key is effective when the CPU is in the operating or stopped state. The key is not effective when the CPU is in the check-stop state. It depends on the model whether the restart key is effective when any CPU in the configuration is in the load state. The effect is unpredictable when the restart key is activated while any CPU in the configuration is in the load state. In particular, if the CPU performs a restart interruption and enters the operating state while another CPU is in the load state, operations such as I/O instructions, the SIGNAL PROCESSOR instruction, and the INVALIDATE PAGE TABLE ENTRY instruction may not operate according to the defmitions given in this publication. Start Key Activating the start key causes the CPU to perform the start function. (See the section "Stopped, Operating, Load, and Check-Stop States" in Chapter 4, "Control.") The start key is effective only when the CPU is in the stopped state. The effect is unpredictable when the stopped state has been entered by a reset. Stop Key Activating the stop key causes the CPU to perform the stop function. (See the section "Stopped, Operating, Load, and Check-Stop States" in Chapter 4, "ControL") The stop key is effective only when the CPU is in the operating state. Operation Note: effect when: Activating the stop key has no • An unending string of certain program or external interruptions occurs. • The prefix register contains an invalid address. • The CPU is in the load or check-stop state. Store-Status Key Activating the store-status key initiates a storestatus operation. (See the section "Store Status" in Chapter 4, "Control.") The store-status key is effective only when the CPU is in the stopped state. Operation Note: The store-status operation may be used in conjunction with a standalone dump program for ~he analysis of major program malfunctions. For such an operation, the following sequence would be called for: 1. Activation of the stop or system-reset-normal key 2. Activation of the store-status key 3. Activation of the load-normal key to enter a standalone dump program The system-reset-normal key must be activated in step I when ( I) the stop key is not effective because a continuous string of interruptions is occurring, (2) the prefix register contains an invalid· address, or (3) the CPU is in the check-stop state. System-Reset-Clear Key Activating the system-reset-clear key causes a clearreset operation to be performed. Clear reset is propagated to all CPUs and storage units in the configuration, and a subsystem reset is performed on the remainder of the configuration. For details, see the section "Resets" in Chapter 4, "Control." The system-reset-clear key is effective. when the CPU is in the operating, stopped, load, or checkstop state. 12-4 ESAj370 Principles of Operation System-Reset-Normal Key Activating the system-reset-nonnal key causes a cPu-reset operation and a subsystem-reset operation to be perfonned. In a multiprocessing configuration, a CPU reset is propagated to all cpus in the configuration. For details, see the section "Resets" in Chapter 4, "Control." The system-reset-nonnal key is effective when the cpu is in the operating, stopped, load, or checkstop state. Test Indicator The test indicator is on when a manual control for operation or maintenance is in an abnonnal position that can affect the nonnal operation of a program. Setting the address-compare controls to the stop position or setting the rate control to the instruction-step position turns on the test indicator. The test indicator may be on when one or more diagnostic functions under the control of DIAGNOSE are activated, or when other abnonnal conditions occur. Operation Note: If a manual control is left in a setting intended for maintenance purposes, such an abnonnal setting may, among other things, result in false machine-check indications or cause actual machine malfunctions to be ignored. It may also alter other aspects of machine operation, including instruction execution, channel-subsystem operation, and the functioning of operator controls and indicators, to the extent that operation of the machine does not comply with that described in this publication. The abnonnal setting of a manual control causes the test indicator of the affected CPU to be turned on; however, in a multiprocessing configuration, the operation of other CPUs may' be affected even though their test indicators are not turned on. TOO-Clock Control When the TO D-clock control is not activated, that is, the control is set to the secure position, the state and value of the TO D clock are protected against unauthorized or inadvertent change by not permitting the instructions SET CLOCK or DIAGNOSE to change the state or value. When the TOD-clock control is activated, that is, the control is set to the enable-set position, alteration of the clock state or value by means of SET CLOCK or DIAGNOSE is permitted. This setting is momentary, and the control automatically returns to the secure position. In a multiprocessing configuration, activating the Too-clock control enables all TOD clocks in the configuration to be set. If there is more than one physical representation of the TO D-clock control, no TOO clock is secure unless all TOD-clock controls in the configuration are set to the secure position. Wait Indicator The wait indicator is on when the wait-state bit in the current psw is one. Multiprocessing Configurations In a multiprocessing configuration, one of each of the following keys and controls is provided for each CPU: alter and display, interrupt, rate, restart, start, stop, and store status. The load-clear key, loadnonnal key, and load-unit-address controls are provided for each CPU capable of performing I/O operations. Alternatively, a single set of initial-program-Ioading keys and controls may be used together with a control to select the desired CPU. There need not be more than one of each of the following keys and controls in a multiprocessing configuration: address compare, IML, power, system reset clear, system reset nonnal, and TO D clock. One check-stop, manual, test, and wait indicator is provided for each CPU. A load indicator is provided only on a CPU capable of perfonning I/O operations. Alternatively, a single set of indicators may be switched to more than one CPU. There need not be more than one architecturalmode indicator in a multiprocessing configuration. In a system capable of reconfiguration, there must be a separate set of keys, controls, and indicators in each configuration. Chapter 12. Operator Facilities 12-5 Chapter 13. 1/0 Overview Comparison among ESA/370, 370-XA and System/ 370 . . . . . . . The Channel Subsystem . . . . . . . Subchannels . . . . . . . . . . . . Attachment of Input/Output Devices Channel Paths Control Units I/O Devices I/O Addressing Channel-Path Identifier 13-1 13-2 13-2 13-3 13-3 13-4 13-4 13-5 13-5 Comparison among ESA/370, 370-XA and System/370 There is no difference between the input/output facilities provided in ESA/370 and the input/output facilities provided in 370-XA. "Input" and "output" are terms used to describe the transfer of information between I/O devices and main storage. An operation involving this kind of transfer is referred to as an input/output (I/O) operation. In 370-XI\. and in FSA/370, the I/O facilities are collectively called the channel subsystem. The channel subsystem has a different logical structure from that of the I/O facilities provided in System/370, with the result that I/O instructions, channels, channel sets, and I/O addressing are replaced for the 370-XI\. and E..<;1\./370 channel subsystem by a different set of I/O instructions, by logical device addressing, and by device-accessing mechanisms that together provide more function, flexibility, and extendibility. Compatibility with System/370 has been maintained in two areas: (1) ccws, IDAWS, and channel programs, and (2) the physical attachment of control units and I/O devices to the system. In System/370, with some exceptions, each channel has a single physical path and data-transfer mechanism between the channel and its attached control units, and the path and channel are often thought of as one. In 370-XA and ESI\./370, because the architecture permits up to 256 channel paths to be supported by the channel subsystem, the term "channel path" is specifically used whenever referring to the physical path between the channel subsystem and one or more control units. In most cases, the term "channel path" that is used in 370-XI\. and E..<;A/370 is synonymous with the System/370 term "channel" when "channel" is used Subchannel Number Device Number Device Identifier .. Execution of I/O Operations Start-Function Initiation Path Management . . . . Channel-Program Execution Conclusion of I/O Operations I/O Interruptions . . . . . . . 13-5 13-5 13-5 13-6 13-6 13-7 13-7 13-8 13-9 to mean the physical path for attachment of control units to the system. In System/370, a channel has (l) a unique channel address within its channel set and (2) logically separate and distinct facilities for communicating with its attached I/O devices and with the CPU to which it is connected. For example, when an I/O device is attached to more than one channel, each channel has a separate subchannel that can be used to communicate with the I/O device. Subchannels are never shared among channels, and each subchannel is associated with only one channel path. In 370-XA and 13SI\./370, however, a single channel subsystem having a single set of subchannels is provided. Each subchannel is uniquely associated with one I/O device, and that I/O device is uniquely associated with that one subchannel within the channel subsystem, regardless of the number of channel paths by which the I/O device is accessible to the channel subsystem. Therefore, the channel subsystem has both the attributes of a single channel -- a unique address (since there is only one, addressing is implicit) and a single set of subchannels for all its attached devices -- and the attributes of multiple channels, since it provides for up to 256 channel paths and for up to 64K devices. Although the logical structures of the I/O facilities provided by the two modes differ, channel programs that can be executed by System/370 channels can be executed by the channel subsystem. Control units that are designed to attach to System/370 channels by using the IBM I/O interface can attach to the channel subsystem by using the same I/O interface. This interface is described in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit Chapter 13. I/O Overview 13-1 Original Equipment Manufacturers' Information, GA22-6974. The Channel Subsystem The channel subsystem directs the flow of information between I/O devices and main storage. It relieves CPUs of the task of communicating directly with I/O devices and permits data processing to proceed concurrently with I/O processing. The channel subsystem uses one or more channel paths as the communication link in managing the flow of information to or from I/O devices. As part of I/O processing, the channel subsystem also executes a path-management operation, testing for channelpath availability, choosing an available channel path, and initiating execution of the I/O operation with the device. Within the channel subsystem are subchannels. One subchannel is provided for and dedicated to each I/O device accessible to the channel subsystem. Each subchannel provides information concerning the associated I/O device and its attachment to the channel subsystem. The subchannel also provides information concerning I/O operations and other functions involving the associated I/O device. The subchannel is the means by which the channel subsystem provides information about associated I/O devices to cpus, which obtain this information by executing I/O instructions. The actual number of sub channels provided depends on the model and the configuration; the maximum addressability is 64K. I/O devices are attached through control units to the channel subsystem by means of channel paths. Control units may be attached to the channel subsystem by more than one channel path, and an I/O device may be attached to more than one control unit. In all, an individual I/O device may be accessible to the channel subsystem by as many as eight different channel paths, depending on the model and the configuration. The total number of channel paths provided by a channel subsystem depends on the model and the configuration; the maximum addressability is 256. The performance of a channel subsystem depends on its use and on the system model in which it is implemented. Channel paths are provided with different data-transfer capabilities, and an I/O device designed,to transfer data only at a specific rate (a magnetic-tape unit or a disk storage, for example) 13-2 ESAj370 Principles of Operation can operate only on a channel path that can accommodate at least this data rate. The channel subsystem contains common facilities for the control of I/O operations. When these facilities are provided in the form of separate, autonomous equipment designed specifically to control I/O devices, I/O operations are completely overlapped with the activity in CPUs. The only mainstorage cycles required by the channel subsystem during I/O operations are those needed to transfer data and control information to or from the fmal locations in main storage, along with those cycles that may be required for the channel subsystem to access the subchanne1s. when they are implemented as part of nonaddressable main storage. These cycles do not delay CPU programs, except when both the CPU and the channel subsystem concurrently attempt to refer to the same main-storage area. Subchannels A subchannel provides the logical appearance of a device to the program. The subchannel contains the information required for sustaining a single I/O operation. The subchannel consists of internal storage that contains information in the form of a ccw address, channel-path identifier, device number, count, status indications, and I/o-interruption subclass code, as well as information on path availability and functions pending or being performed. I/O operations are initiated with a device by executing I/O instructions that designate the subchannel associated with the device. Each device has one subchannel per channel subsystem by which the device is accessible. Each device is assigned to a subchannel during an installation procedure. The device may be a physically identifiable unit, or it may be housed internal to a control unit. For example, in certain models of the IBM 3380 Direct-Access Storage, each actuator used in retrieving the data is considered to be a device. In all cases, a device, from the point of view of the channel subsystem, is an entity that is uniquely associated with one subchannel and that responds to selection by the channel subsystem by using the communication protocols defmed for the type of channel path by which it is accessible. In some models, subchannels are provided in blocks. In these models, more subchannels may be provided than there are attached devices. Subchannels that are provided but do not have devices assigned to them are not used by the channel subsystem to perfonn any function and are indicated by storing the associated device-number-valid bit as zero in the subchannel-infonnation block of the subchannel. The number of subchannels provided by the channel subsystem is independent of the number of channel paths to the associated devices. For example, a device accessible through alternate channel paths still is represented by a single subchannel. Each subchannel is addressed by using a 16-bit binary subchannel number. Mter the operation with the subchannel has been requested by executing START SUBCHANNEL, the CPU is released for other work, and the channel subsystem assembles or disassembles data and synchronizes the transfer of data bytes between the 1/0 device and main storage. To accomplish this, the channel subsystem maintains and updates an address and a count that describe the destination or source of data in main storage. Similarly, when an I/O device provides signals that should be brought to the attention of the program, the channel subsystem transfonns the signals into status infonnation and stores the information in the subchannel , where it can be retrieved by the program. Attachment of Input/Output Devices Channel Paths The channel subsystem communicates with 1/0 devices by means of channel paths between the channel subsystem and control units. A control unit may be accessible by the channel subsystem by more than one channel path. Similarly, an 1/0 device may be accessible by the channel subsystem through more than one control unit, each having one or more channel paths to the channel subsystem. Devices that are attached to the channel subsystem by multiple channel paths may be accessed by the channel subsystem by using any of the av,wable channel paths. Similarly, a device having the dynamic-reconnection feature and operating in multipath mode can be initialized to operate such that the device may choose any channel path to which it is attached when logically reconnecting to the channel subsystem to continue a chain of 1/0 operations. The defInition of the type of channel path used by the channel subsystem and the definition of the dynamic-reconnection feature are given in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. An 1/0 operation occurs on a channel path in one of two modes, depending on the facilities provided by the channel path and the 1/0 device. The modes are burst· and byte-multiplex. In burst mode, the 1/0 device monopolizes a channel path and stays logically connected to the channel path for the transfer of a burst of infonnation. No other device can communicate over the channel path during the time a burst is transferred. The burst can consist of a few bytes, a whole block of data, a sequence of blocks with associated control and status infonnation (the block lengths may be zero), or status information which monopolizes the channel path. The facilities of the channel path capable of operating in burst mode may be shared by a number of concurrently operating 1/0 devices. Some channel paths can tolerate an absence of data transfer for about a half minute during a burstmode operation, such as occurs when a long gap on magnetic tape is read. An equipment malfunction may be indicated when an absence of data transfer exceeds the prescribed limit. In byte-multiplex mode, the 1/0 device stays logically connected to the channel path only for a short interval of time. The facilities of a channel path capable of operating in byte-mUltiplex mode may be shared by a number of concurrently operating 1/0 devices. In this mode all I/O operations are split into short intervals of time during which only a segment of information is transferred over the channel path. During such an interval, only one device and its associated subchannel are logically connected to the channel path. The intervals associated with the concurrent operation of multiple I/O devices are sequenced in response to demands from the devices. The channel-subsystem facility associated with a subchannel exercises its controls for anyone operation only for the time required to transfer a segment of information. The segment can consist of a single- -byte of data, a few bytes of data, a status report from the device, or a control sequence used for the initiation of a new operation. Chapter 13. I/O Overview 13-3 Ordinarily, devices with high data-transfer-rate requirements operate with the channel path in burst mode, and slower devices run in byte-multiplex mode. Some control units have a manual switch for setting the desired mode of operation. For improved performance, some channel paths and control units are provided with facilities for high-speed transfer and data streaming. See the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974, for a description of those two facilities. The modes and features described above affect only the protocol used to transfer information over the channel path and the speed of transmission. No effects are observable by CPU or channel programs with respect to the way these programs are executed. Control Units A control unit provides the logical capabilities necessary to operate and control an I/O device and adapts the characteristics of each device so that it can respond to the standard form of control provided by the channel subsystem. Communication between the control unit and the channel subsystem takes place over a channel path. The control unit accepts control signals from the channel subsystem, controls the timing of data transfer over the channel path, and provides indications concerning the status of the device. The I/O device attached to the control unit may be designed to execute only certain limited operations, or it may execute many different operations. A typical operation is moving a recording medium and recording data. To accomplish its operations, the device needs detailed signal sequences peculiar to its type of device. The control unit decodes the commands received from the channel subsystem, interprets them for the particular type of device, and provides the signal sequence required for execution of the operation. A control unit may be housed· separately, or it may be physically and logically integrated with the I/O device, the channel subsystem, or a CPU. In the case of most electromechanical devices, a welldefmed interface exists between the device and the control unit because of the difference in the type of equipment the control unit and the device require. 13-4 ESAj370 Principles of Operation These electromechanical devices often are of a type where only one device of a group attached to a control unit is required to transfer data at a time (magnetic-tape units or disk-access mechanisms, for example), and the control unit is shared among a number of I/O devices. On the other hand, in some electronic I/O devices, such as the channel-tochannel adapter, the control unit does not have an identity of its· own. From the programmer's point of view, most functions performed by the control unit can be merged with those performed by the I/O device. Therefore, this publication normally makes no specific mention of the control-unit function; the execution of I/O operations is described as if the I/O devices communicated directly with the channel subsystem. Reference is made to the control unit only when emphasizing a function performed by it or when describing how the sharing of the control unit among a number of device~ affects the execution of I/O operations. 1/0 Devices An input/output (I/O) device provides external storage, a means of communication between dataprocessing systems, or a means of communication between a system and its environment. I/O devices include such equipment as card readers, card punches, magnetic-tape units, direct-access-storage devices (for example, disks), display units, typewriter-keyboard devices, printers, teleprocessing devices, and sensor-based equipment. An I/O device may be physically distinct equipment, or it may share equipment with other I/O devices. The term "I/O .device," as it is used in this publication, refers to an entity with which the channel subsystem can directly communicate. For example, the IBM 2540 Card Reader-Punch is considered to be two separate I/O devices from the point of view of" the channel subsystem since the reader portion and the punch portion are individually accessible. Most types of I/O devices, such as printers, card equipment, or tape devices, use external media, and these devices are physically distinguishable and identifiable. Other types are solely electronic and do not directly handle physical recording media. The channel-to-channel adapter, for example, provides for data transfer between two channel paths, and the data never reaches a physical recording medium outside main storage. Similarly, the IBM 3725 Communication Controller handles the trans- mission of infonnation between the data-processing system and a remote station, and its input and output are signals on a transmission line. In the simplest case, an I/O device is attached to one control unit and is accessible from one channel path. Switching equipment is available to make some devices accessible from two or more channel paths by switching devices among control units and by switching control units among channel paths. Such switching equipment provides multiple paths by which an I/O device may be accessed. Multiple channel paths to an I/O device are provided to improve perfonnance or 1/0 availability, or both, within the system. The management of multiple channel paths to devices is under the control of the channel subsystem and the device, but the channel paths may indirectly be controlled by the program. 1/0 Addressing Four different types of 1/0 addressing are provided by the channel subsystem for the necessary addressing of the various components: channelpath identifiers, subchannel numbers, device numbers, and, though not visible to programs, addresses dependent on the channel-path type. Channel-Path Identifier The channel-path identifier (CHPID) is a systemunique eight-bit value assigned to each installed channel path of the system. A CHPID identifies a physical channel path. A CHPID is specified by the second-operand address of RESET CHANNEL PATH and designates the physical channel path that is to be reset. The channel paths by which a device is accessible are identified in the subchannelinfonnation block (SCHIB), each by its associated CHPID, when STORE SUBCHANNEL is executed. The CHPID can also be used in operator messages when it is necessary to identify a particular channel path. A system model may provide as many as 256 channel paths. The maximum number of channel paths and the assignment of CHPIDS to channel paths depends on the system model. Subchannel Number A subchannel number is a system-unique 16-bit value used to address a subchannel. The subchannel is addressed by seven 1/0 instructions: CLEAR SUBCHANNEL, HALT SUBCHANNEL, MODIFY SUBCHANNEL, RESUME SUBCHANNEL, START SUBCHANNEL, STORE SUBCHANNEL, and TEST SUBCHANNEL. Each I/O device accessible to the channel subsystem is assigned a dedicated subchannel at installation time. All I/O functions relative to a specific I/O device are specified by the program by designating the subchannel assigned to the 1/0 device. Subchannels are always assigned subchannel numbers within a single range of contiguous numbers. The lowest-numbered subchannel is subchannel O. The highest-numbered subchannel of the channel subsystem has a subchannel number equal to one less than the number of subchannels provided. A maximum of 64K subchannels can be provided. Nonnally, subchannel numbers are only used in communication between the CPU program and the channel subsystem. Device Number Each subchannel that has an I/O device assigned to it also contains a system-unique parameter called the device number. The device number is a 16-bit value that is assigned as one of the parameters of the subchannel at the time the device is assigned to the subchannel. The device number provides a means to identify a device, independent of any limitations imposed by the system model, the configuration, or channelpath protocols. The device number is used in communications concerning the device that take place between the system and the system operator. For example, the device number is entered by the system operator to designate the input device to be used for initial program loading. Device Identifier A device identifier is an address not apparent to the program, that is used by the channel subsystem to communicate with I/O devices. The type of device identifier used depends on the specific channel-path type and the protocols provided. Each sub channel contains one or more device identifiers. The \;hannel-path type used by the channel subsystem is described in the System Library publica- Chapter 13. I/O Overview 13-5 tion IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. For this type of channel path, the device identifier is called a device address and consists of an eight-bit value. The device address identifies the particular I/O device and control unit associated with a subchannel. The device address may identify, for example, a particular magnetic-tape drive, diskaccess mechanism, or transmission line. Any number in the range 0-255 can be assigned as a device address. For further information about the I/o-device address used with the IBM I/O interface, see the publication referred to above. Programming Note: The device number is assigned at device-installation time and may have any value so long as it is system-unique. Device numbers may be assigned installation-unique values in multicomputer installations in order to avoid ambiguity, particularly where a device can be switched between two or more systems. In installations in which a system may be operated sometimes in System/370 and sometimes in the FSA/370, it is advisable to make the FSA/370 device number and System/370 I/O address equivalent to prevent operational problems in such mixed environments. Additionally, the user must observe any restrictions on device-number assignment that may be required by the control program, support programs, or the particular control unit or I/O device. Execution of 110 Operations I/O operations are initiated and controlled by information with three types of fonnats: the instruction START SUBCHANNEL, channel-command words (ccws), and orders. The START SUBCHANNEL instruction is executed by a CPU and is part of the CPU program that supervises the flow of requests for I/O operations from other programs that manage or process the I/O data. When START SUBCHANNEL is executed, parameters are passed to the target subchannel requesting that the channel subsystem perform a start function with the I/O device associated with the subchannel. The channel subsystem performs the start function by using information at the subchannel , including the informa- 13-6 ESA/370 Principles of Operation tion passed during the execution of the START SUBCHANNEL instruction, to fmd an accessible channel path to the device. Once the device has been selected, execution of an I/O operation is accomplished by the decoding and executing of a ccw by the channel subsystem and the I/O device. One or more ccws arranged for sequential execution form a channel program and are executed as one or more I/O operations, respectively. Both instructions and ccws are fetched from main storage, and their formats are common for all types of I/O devices, although the modifier bits in the command code of a ccw may specify devicedependent conditions for the execution of an operation at the device. Operations peculiar to a device, such as rewinding tape or positioning the access mechanism on a disk drive, are specified by orders which are decoded and executed by I/O devices. Orders may be transferred to the device as modifier bits in the command code of a control command, may be transferred to the device as data during a control or write operation, or may be made available to the device by other means. Start-Function Initiation CPU programs initiate I/O operations with the instruction START SUBCHANNEL. This instruction passes the contents of an operation-request block (ORB) to the subchannel. The contents of the ORB include the subchannel key, the address of the frrst ccw to be executed, and the format of the ccws. The ccw specifies the command to be executed and the storage area, if any, to be used. When the ORB contents have been passed to the subchannel, the execution of START SUBCHANNEL is complete. The results of the execution of the instruction are indicated by the condition code set in the program-status word. When facilities become available, the channel subsystem fetches the first ccw and decodes it according to the format bit specified in the ORB. If the format bit is zero, format-O (System/370-compatible) ccws are specified. If the format bit is one, format-l ccws are specified. Format-O and format-l ccws contain the same information, but the fields are arranged differently in the format-l ccw so that 31-bit addresses can be specified directly in the ccw. Path Management If the frrst ccw passes certain validity tests and does not have the suspend flag specified, the channel subsystem attempts device selection by choosing a channel path from the group of channel paths that are available for selection. A control unit that recognizes the device identifier connects itself logically to the channel path and responds to its selection. The channel subsystem subsequently sends the command-code part of the ccw over the channel path, and the device responds with a status byte indicating whether the command can be executed. The control unit may logically disconnect from the channel path at this time, or it may remain connected to initiate data transfer. I If the attempted selection does not occur as a result of either a busy indication or a path-notoperational condition, the channel subsystem attempts to select the device by an alternate channel path if one is available. When selection has been attempted on all paths available for selection and the busy condition persists, the operation remains pending until a path becomes free. If a path-not-operational condition is detected on one or more of the channel paths on which device selection was attempted, the program is alerted by a subsequent I/O interruption. The I/O interruption occurs either upon execution of the channel program (assuming the device was selected on an alternate channel path) or as a result of the execution being abandoned, path-not-operational conditions being detected on all of the channel paths on which device selection was attempted. Channel .. Program Execution If the command is initiated at the device and command execution does not require any data to be transferred to or from the device, the device may signal the end of the operation immediately on receipt of the command code. In operations that involve the transfer of data, the subchannel is set up so that the channel subsystem will respond to service requests from the device and assume further control of the operation. An 1/0 operation may involve the transfer of data to or from one storage area, designated by a single CCW, or to or from a number of noncontiguous storage areas. In the latter case, generally a list of CCws is used for execution of the I/O .operation, each ccw designating a contiguous storage area, and the ccws are coupled by data chaining. Data chaining is specified by a flag in the ccw and causes the channel subsystem to fetch another ccw upon the exhaustion or filling of the storage area designated by the current ccw. The storage area designated by a ccw fetched on data chaining pertains to the I/O operation already in progress at the I/O device, and the I/O device is not notified when a new ccw is fetched. Provision is made in the ccw format for the programmer to specify that, when the ccw is decoded, the channel subsystem request an I/O interruption as soon as possible, thereby notifying a CPU program that chaining has· progressed at least as far as that ccw in the channel program. To complement dynamic address translation ill cpus, ccw indirect data addressing is provided. A flag in the ccw specifies that an indirect-dataaddress list is to be used to designate the storage areas for that ccw. Each time the boundary of a 2K-byte block of storage is reached, the list is referenced to determine the next block of storage to be used. ccw indirect data addressing permits essentially the same ccw sequences to be used for a program running with dynamic address translation active in a CPU as would be used if the CPU were operating with equivalent contiguous real storage. ccw indirect data addressing permits the program to designate data blocks having absolute storage addresses up to 231 _1, independent of whether format-O or format-l ccws have been specified in the ORB. In general, execution of an I/O operation or chain of operations involves as many as three levels of participation: 1. Except for effects due to the integration of CPU and channel-subsystem equipment, a CPU is busy for the duration of the execution of START SUBCHANNEL, which lasts until the addressed sub channel has been passed the ORB contents. 2. The subchannel is busy for a new START SUBCHANNEL from the receipt of the ORB contents until the primary interruption condition is cleared at the subchannel. 3. The I/O device is busy from the initiation of the rrrst operation at the device until either the subchannel becomes suspended or the secondary interruption condition is placed at the subchannel. In the case of a suspended subchannel, the device again becomes busy when execution of the suspended channel program is resumed. Chapter 13. I/O Overview 13-7 Conclusion of 1/0 Operations The conclusion of an I/O operation normally is indicated by two status conditions: channel end and device end. The channel-end condition indicates that the I/O device has received or provided all data associated with the operation and no longer needs channel-subsystem facilities. This condition is called the primary interruption condition, and the channel end in this case is the primary status. Generally, the primary interruption condition is any interruption condition that relates to an I/O operation and that signals the conclusion at the subchannel of the I/O operation or chain of I/O operations. The device-end signal indicates that the I/O device has concluded execution and is ready to execute another operation. This condition is called the secondary interruption condition, and the device end in this case is the secondary status. Generally, the secondary interruption condition is any interruption condition that relates to an I/O operation and that signals the conclusion at the device of the I/O operation or chain of operations. The secondary interruption condition can occur concurrently with, or later than, the primary interruption condition. Concurrent with the primary or secondary interruption conditions, both the channel subsystem and the I/O device can provide indications of unusual situations. The conditions signaling the conclusion of an I/O operation can be brought to the attention of the program by I/O interruptions or, when the CPUs are disabled for I/O interruptions, by programmed interrogation of the channel subsystem. In the former case, these conditions cause storing of the I/o-interruption code, which contains information concerning the interrupting source. In the latter case, the interruption code is stored as a result of the execution of TEST PENDING INTERRUPTION. When the primary interruption condition is recognized, the channel subsystem attempts to notify the program, by means of an, interruption request, that a subchannel contains information describing the conclusion of an I/O operation at the subchannel. The information identifies the last ccw used and may provide its residual byte count, thus describing the extent of main storage used. Both the channel subsystem and the I/O device may provide additional indications of unusual conditions as part of either the primary or secondary interruption condi- 13-8 ESA/370 Principles of Operation tion. The information contained at the subchannel may be stored by the execution of TEST SUBCHANNEL or the execution of STORE SUBCHANNEL. This information, when stored, is called a subchannel-status word (scsw). Facilities are provided for the program to initiate execution of a chain of I/O operations with a single START SUBCHANNEL instruction. When the current ccw specifies command chaining and no unusual conditions have been detected during the operation, the receipt of the device-end signal causes the channel subsystem to fetch a new ccw. If the ccw passes certain validity tests and the suspend flag is not specified in the new ccw, execution of a new command is initiated at the device. If the ccw fails to pass the validity tests, the new command is not initiated, command chaining is suppressed, and the status associated with the new ccw causes an interruption condition to be generated. If the suspend flag is specified, execution of the new command is not initiated, and command chaining is concluded. Execution of the new command is initiated by the channel subsystem in the same way as the previous operation. The ending signals occurring at the conclusion of an operation caused by a ccw specifying command chaining are not made available to the program. When another I/O operation is initiated by command chaining, the channel subsystem continues execution of the channel program. If, however, an unusual condition has been detected , command chaining is suppressed, the channel program is terminated, an interruption condition is generated, and the ending signals causing the termination are made available to the program. The suspend-and-resume function provides the program with control over the execution of a channel program. The initiation of the suspend function is controlled by the setting of the suspendcontrol bit in the ORB. The suspend function is signaled to the channel subsystem during channelprogram execution by specifying the suspend (s) flag in the first ccw or in a ccw fetched during command chaining. Suspension occurs when the channel subsystem fetches a ccw with a valid S flag. The command in this ccw is not sent to the I/O device, and the device is signaled that the chain of commands is concluded. A subsequent RESUME SUBCHANNEL instruction informs the channel subsystem that the ccw that caused suspension may have been modi- fied and that the channel subsystem must refetch the ccw and examine the current setting of the suspend flag. If the suspend flag is found to be not specified in the ccw, the channel subsystem resumes execution of the chain of commands with the I/O device. Channel-program execution may be terminated prematurely by HALT SUBCHANNEL or CLEAR SUBCHANNEL. The execution of HALT SUBCHANNEL causes the channel subsystem to issue the halt signal to the I/O device and terminate channelprogram execution at the subchannel. When channel-program execution is terminated by the execution of HALT SUBCHANNEL, the program is notified of the termination by means of an I/o-interruption request. The interruption request is generated when the device presents status for the terminated operation. If, however, the halt signal was issued to the device during command chaining after the receipt of device end but before the next command was transferred to the device, the interruption request is generated after the device has been signaled. In the latter case, the device-status field of the scsw will contain zeros. The execution of CLEAR SUBCHANNEL clears the subchannel of indications of the channel program in execution, causes the channel subsystem to issue the clear signal to the I/O device, and causes the channel subsystem to generate an I/O interruption request to notify the program of the completion of the clear function. 1/0 Interruptions Conditions causing I/o-interruption requests are asynchronous to activity in cpus, and more than one condition can occur at the same time. The conditions are preserved at the subchannels until cleared by TEST SUBCHANNEL or CLEAR SUBCHANNEL, or reset by an I/o-system reset. When an I/o-interruption condition has been recognized by the channel subsystem and indicated at the subchannel, an I/o-interruption request is made pending for the I/o-interruption subclass specified at the subchannel. The I/o-interruption subclass for which the interruption is made pending is under programmed control through the use of MODIFY SUBCHANNEL. A pending I/O interruption may be accepted by any CPU that is enabled for interruptions from its I/o-interruption subclass. Each CPU has eight mask bits in control register 6 which control the enabling of that CPU for each of the eight I/o-interruption subclasses, with the I/O mask (bit 6) in the psw the master I/o-interruption mask for the CPU. When an I/O interruption occurs at a CPU, the I/o-interruption code is stored in the I/o-communication area of that CPU, and the I/o-interruption request is cleared. The I/o-interruption code identifies the sub channel for which the interruption was pending. The conditions causing the generation of the interruption request may then be retrieved from the subchannel explicitly by TEST SUBCHANNEL or by STORE SUBCHANNEL. A pending I/o-interruption request may also be cleared by TEST PENDING INTERRUPTION when the corresponding I/o-interruption subclass is enabled but the psw has I/O interruptions disabled or TEST SUBCHANNEL when the CPU is disabled for I/O interruptions from the corresponding I/o-interruption subclass. A pending I/o-interruption request may also be cleared by CLEAR SUBCHANNEL. Both CLEAR SUBCHANNEL and TEST SUBCHANNEL clear the preserved interruption condition at the subchannel as well. Normally, unless the interruption request is cleared by CLEAR SUBCHANNEL, the program executes TEST SUBCHANNEL to obtain information concerning the execution of the operation. Chapter 13. I/O Overview 13-9 Chapter 14. 1/0 Instructions 1/0-Instruction Formats 1/0-Instruction Execution Serialization Operand Access Condition Code Program Exceptions Instructions Clear Subchannel Halt Subchannel Modify Subchannel . \" 14-1 14-1 14-1 14-1 14-2 14-2 14-2 14-4 14-4 14-6 The I/O instructions include all instructions that are provided for the control of channel-subsystem operations. The I/O instructions are listed in All of the I/O Figure 14-1 on page 14-3. instructions are privileged instructions. Several I/O instructions result in the channel subsystem being signaled to perform functions asynchronous to the execution of the instructions. The description of each instruction of this type contains a section called "Associated Functions," which summarizes the asynchronous functions. I/O-Instruction Formats All I/O Reset Channel Path Resume Subchannel Set Address Limit Set Channel Monitor Start Subchannel .. Store Channel Path Status Store Channel Report Word Store Subchannel Test Pending Interruption Test Subchannel ..... 14-7 14-8 14-10 14-10 14-12 14-14 14-14 14-15 14-16 14-17 " subsystem-identification word has the following format: Subchannel Number 0000000000000001 16 31 Bits 16-31 form the binary number of the subchannel to be used for the function specified by the instruction. I/O-Instruction Execution instructions use the S format: Serialization Op Code 16 20 31 The use of the second-operand address and general registers 1 and 2 (as implied operands) depends on the I/O instruction. Figure 14-1 on page 14-3 defmes which operands are used to execute each I/O instruction. In addition, detailed information regarding operand usage appears in the description of each I/O instruction. All I/O instructions that reference a subchannel use the contents of general register 1 as an implied operand. For these I/O instructions, general register 1 contains the subsystem-identification word. The The execution of any I/O instruction causes serialization and checkpoint synchronization to occur. For a definition of the serialization of CPU operations, see the section "CPU Serialization" in Chapter 5, "Program Execution." Operand Access During execution of an I/O instruction, the order in which fields of the operand and fields of the subchannel (if applicable) are accessed is unpredictable. It is also unpredictable as to whether fetch accesses are made to fields of an operand or the subchannel (as applicable) when those fields are not needed to complete execution of the I/O instruction. (See the section "Relation Between Operand Accesses" in Chapter 5, "Program Execution.") Chapter 14. I/O Instructions 14-1 Condition Code During the execution of some I/O instructions, the results of certain tests are used to set one of four condition codes in the psw. The I/O instructions for which execution can result in the setting of the condition code are listed in Figure 14-1 on page 14-3. The condition code indicates the result of the execution of the I/O instruction. The general meaning of the condition code for I/O instructions is given below; the meaning of the condition code for a specific instruction appears in the description of that instruction. Condition Code 0: Instruction execution produced the expected or most probable result. (See the section "Deferred. Condition Code (CC)" on page 16-8 for a description of conditions that can be encountered subsequent to the presentation of condition code 0 that result in a nonzero deferred condition code.) Condition Code 1: Instruction execution produced the alternate or second-most-probable result, or status conditions were present that mayor may not have prevented the expected result. Condition Code 2: Instruction execution was ineffective because the designated subchannel or channel-subsystem facility was busy with a previously initiated function. Condition Code 3: Instruction execution was ineffective because the designated element was not operational or because some condition precluded initiation of the normal function. 14-2 ESAj370 Principles of Operation In situations where conditions exist that could cause more than one nonzero condition code to be set, priority of the condition codes is as follows: Condition code 3 has precedence over condition codes 1 and 2. Condition code 1 has precedence over condition code 2. Program Exceptions The program exceptions that the I/O instructions can encounter are access, operand, privilegedoperation, and specification' exceptions. Figure 14-1 on page 14-3 shows the exceptions that are applicable to each of the I/O instructions. The execution of the instruction is suppressed for privileged-operation, operand, and specification exceptions. Except as indicated otherwise in the section "Special Conditions" for each instruction, the instruction ending for access exceptions is as described in the section "Recognition of Access Exceptions" in Chapter 6, "Interruptions." Instructions \ The mnemonics, format, and operation codes of the I/O instructions are given in Figure 14-1 on page 14- J. The figure also indicates the conditions that can cause a program interruption and whether the condition code is set. In the detailed descriptions of the individual instructions, the mnemonic and the symbolic operand designation for the assembler language are shown with each instruction. In the case of START SUBCHANNEL, for example, SSCH is the mnemonic and D 2(B 2) the operand designation. Name Mnemonic Op Code Characteristics CLEAR SU8CHANNEL HALT SU8CHANNEL MODIFY SU8CHANNEL RESET CHANNEL PATH RESUME SU8CHANNEL CSCH HSCH MSCH RCHP RSCH S S S S S C C C C C P OP P OP P A SP OP P OP OP P ¢ ¢ ¢ ¢ ¢ GS GS GS G1 GS 8230 8231 82 8232 8238 8238 SET ADDRESS LIMIT SET CHANNEL MONITOR START SU8CHANNEL STORE CHANNEL PATH STATUS STORE CHANNEL REPORT WORD SAL SCHM SSCH STCPS STCRW S S S S S C ¢ ¢ ¢ ¢ ¢ G1 GM GS C OP P P OP P A SP OP P A SP P A SP ST ST 8237 823C 82 8233 82 823A 82 8239 STORE SU8CHANNEL TEST PENDING INTERRUPTION TEST SU8CHANNEL STSCH S TPI S TSCH S C C C P A SP OP P Al SP P A SP OP ¢ ¢ ¢ GS ST ST ST 82 8234 82 8236 82 8235 GS Explanation: ¢ Causes serialization and checkpoint synchronization. A Access exceptions for logical addresses. Al When the effective address is zero, it is not used to a~cess storage, and no access exceptions can occur, except that access exceptions may occur during access-register translation. 82 82 field designates an access register in the access-register mode. C Condition code is set. G1 Instruction execution includes the implied use of general register 1 as a parameter. GM Instruction execution includes the implied use of multiple general registers. General register 1 is used as a parameter, and general register 2 may be used as a parameter. GS Instruction execution includes the implied use of general register 1 as the subsystem-identification word. OP Operand exception. P Privileged-operation exception. S S instruction format. SP Specification exception. ST PER storage-alteration event. Figure 14-1. Summary of I/O Instructions Chapter 14. I/O Instructions 14-3 Clear Subchannel [S] CSCH 18230 1 o 11/111111111111111 16 31 The designated subchannel is cleared, the current start or halt function, if any, is terminated at the designated subchannel, and the channel subsystem is signaled to asynchronously perform the clear function at the designated subchannel and at the associated device. General register 1 contains the subsystemidentification word, which designates the subchannel that is to be cleared. When the subchannel becomes status-pending as a result of perfonning the clear function, data transfer, if any, with the associated device has been tenninated. The scsw stored when the resulting status is cleared by TEST SUBCHANNEL has the clear-function bit stored as one. If the channel subsystem can determine that the clear signal was issued to the device, the clear-pending bit is stored as zero in the scsw. Otherwise, the clear-pending bit is stored as one, and other indications are provided that describe in greater detail the condition (See the section that was encountered. "Interruption-Response Block" on page 16-6.) Measurement data is not accumulated and the device-connect time is not stored in the extendedstatus word for the subchannel for a start function that is terminated by CLEAR SUBCHANNEL. Special Conditions If a start or halt function is in progress, it is terminated at the subchannel. The subchannel is made no longer status-pending. All activity, as indicated in the activity-control field of the SCSw, is cleared at the subchannel, except that the subchannel is made clear-pending. Any functions in progress, as indicated in the functioncontrol field of the scsw, are cleared at the subchannel, except for the clear function which is to be perfonned because of the execution of this instruction. The channel subsystem is signaled to asynchronously perform the clear function. The clear function is sutnmarized below in the section "Associated Functions" and is described in detail in the section "Clear Function" on page 15-13. Condition code 0 is set to indicate that the actions described above have been taken. Associated Functions Subsequent to the execution of CLEAR SUBthe channel subsystem asynchronously performs the clear function. If conditions allow, the channel subsystem chooses a channel path and attempts to issue the clear signal to the device to tenninate the I/O operation, if any. The subchannel then becomes status-pending. Conditions encountered by the channel subsystem that preclude issuing the clear signal to the device do not prevent the subchannel from becoming status-pending (see the section "Clear Function" on page 15-13). CHANNEL, 14-4 ESA/370 Principles of Operation Condition code 3 is set and no other action is taken when the subchannel is not operational for CLEAR SUBCHANNEL. A subchannel is not operational for CLEAR SUBCHANNEL when the subchannel is not provided in the channel subsystem, has no valid device number assigned to it, or is not enabled. can encounter the program exceptions that are listed below. Bit positions 0-15 of general register 1 must contain the value 0001 hex; otherwise, an operand exception is recognized. CLEAR SUBCHANNEL Resulting Condition Code: o Function initiated 1 2 3 Not operational Program Exceptions: • Operand • Privileged operation Halt Subchannel [S] HSCH 18231 1 o 111111111111111111 16 31 The current start function, if any, is terminated at the designated subchannel, and the channel sub- system is signaled to asynchronously perform the halt function at the designated subchannel and at the associated device. General register contains the subsystemidentification word, which designates the subchannel that is to be halted. If a start function is in progress, it is tenrllnated at the subchannel. The subchannel is made halt-pending and the halt function is indicated at the subchannel. When HALT SUBCHANNEL is executed and the designated sub channel is subchannel-and-device-active and status-pending with intermediate status, the status-pending indication is eliminated (see the discussion of bits 24, 25, and 28 in the section "Activity Control (AC)" on page 16-13). The status-pending condition is reestablished as part of the halt function (see the section "Associated Functions" below). The channel subsystem is signaled to asynchronously perform the halt function. The halt function is summarized below in the section "Associated Functions" and is described in detail in the section "Halt Function" on page 15-14. Condition code 0 is set to indicate that the actions described above have been taken. Associated Functions Subsequent to the execution of HALT the channel subsystem asynchronously performs the halt function. If conditions allow, the channel subsystem chooses a channel path and attempts to issue the halt signal to the device to terminate the I/O operation, if any. The subchannel then becomes status-pending. SUBCHANNEL, When the subchannel becomes status-pending as a result of perfonrllng the halt function, data transfer, if any, with the associated device has been terminated. The scsw stored when the resulting status is cleared by TEST SUBCHANNEL has the haltfunction bit stored as one. If the halt signal was issued to the device, the halt-pending bit is stored as zero. Otherwise, the halt-pending bit is stored as one, and other' indications are provided that describe in greater detail the condition that was (See the section "Interruptionencountered. Response Block" on page 16-6 and the section "Halt Function" on page 15-14.) In some models, path availability is tested as part of the halt function (rather than as part of the execution of the instruction). In these models, when no channel path is available for selection, the halt signal is not issued, and the subchannel is made status-pending. When the status-pending condition is subsequently cleared by TEST SUBCHANNEL, the halt-pending bit is stored as one in the scsw. If a status-pending condition is eliminated during execution of HALT SUBCHANNEL, then this condition is reestablished along with the other status conditions when completion of the halt function is indicated to the program. The halt-pending condition may not be recognized by the channel subsystem if a status-pending condition has been generated. This situation could occur, for example, when alert status is presented or generated while the subchannel is already startpending or resume-pending, or when primary status is presented during the attempt to initiate the I/O operation for the fITst command as specified by the start function or implied by the resume function. If recognition of the status-pending condition by the channel subsystem has occurred logically prior to recognition of the halt-pending condition, the scsw, when cleared by TEST SUBCHANNEL, has the halt-pending bit stored as one. If measurement data is being accumulated when a start function is terminated by HALT SUBCHANNEL, the measurement data continues to be accumulated for the subchanne1 and reflects the extent of su bchannel and device usage required, if any, while perfonrllng the currently tenrllnated start function. The measurement data, if any, is accumulated in the measurement block for the sub channel or placed in the extended-status word, as appropriate, when the subchannel becomes status-pending with (See the section "Channelprimary status. Subsystem Monitoring" on page 17-1.) Special Conditions Condition code 1 is set and no other action is taken when the subchannel is status-pending alone or is status-pending with any combination of alert, primary, or secondary status. Condition code 2 is set and no other action is taken when the subchannel is busy for HALT SUBCHANNEL. The subchannel is busy for HALT SUBChapter 14. I/O Instructions 14-5 when a halt function or clear function is already in progress at the subchannel. CHANNBL Condition code 3 is set and no other action is taken when the subchannel is not operational for HALT SUBCHANNBL. A subchannel is not operational for HALT SUBCHANNBL when the subchannel is not provided in the channel subsystem, has no valid device number assigned to it, or is not enabled. In some models, a subchannel is also not operational for HALT SUBCHANNBL when no channel paths are available for selection by the device. (See the section "Channel-Path Availability" on page 15-12 for a description of channel paths that are available for selection.) HALT SUBCHANNEL can encounter the program exceptions listed below. Bit positions 0-15 of general register 1 must contain the value 0001 hex; otherwise, an operand exception is recognized. Resulting Condition Code: o 1 2 3 Function initiated Status-pending with other than intermediate status Busy Not operational Program Exceptions: Programming Note: After execution of HALT SUBthe status-pending condition indicating the completion of the halt function may be delayed for an extended period of time, for example, when the device is a magnetic-tape unit executing a rewind command. CHANNBL, Modify Subchannel [S] IB232 1 16 20 31 The information contained in the subchannelinformation block '(SCHIB) is placed in the program-modifiable fields of the subchannel. As a result, the program influences, for that subchannel, certain aspects of I/O processing relative to the clear, halt, resume, and start functions and certain 1/0 support functions. 14-6 The channel-subsystem operations that may be influenced due to placement of SCHIB information in the subchanne1 are: (1) I/O processing (E field), (2) interruption processing (interruption parameter and ISC field), (3) path management (0, LPM, and POM fields), and (4) monitoring and address-limitchecking facilities (measurement-block index and LM and MM fields). Bits 0-1 and 5-7 of word 1 and bits 0-31 of word 6 of the SCHIB operand must be specified as zeros, and bits 9-10 of word 1 must not both be ones. The remaining fields of the SCHIB are ignored and do not affect the processing of MODIFY SUBCHANNEL. (For further details, see the section "Subchannel-Information Block" on page 15-1.) Condition code 0 is set to indicate that the information from the SCHIB has been placed in the program-modifiable fields of the subchannel. Special Conditions Condition code 1 is set and no other action is taken when the subchannel is status-pending. (See, the section "Status Control (SC)" on page 16-16.) • Operand • Privileged operation o General register contains the subsystemidentification word, which designates the subchannel that is to be modified as specified by certain fields of the SCHIB. The second-operand address is the logical address of the SCHIB and is designated on a word boundary. ESA/370 Principles of Operation Condition code 2 is set and no other action is taken when a clear, halt, or start function is in progress at the subchannel. (See the section "Function Control (FC)" on page 16-12.) Condition code 3 is set and no other action is taken when the sub channel is not operational for MODIFY SUBCHANNBL. A subchannel is not operational for MODIFY SUBCHANNBL when the subchannel is not provided in the channel subsystem. MODIFY SUBCHANNEL can encounter the program exceptions listed below. In word I of the SCHIB, bits 0-1 and 5-7 must be zeros, and bits 9 and 10 must not both be ones; in word 6 of the SCHIB, bits 0-31 must be zeros; bits 0-15 of general register 1 must contain the value 000 I hex; otherwise, an operand exception is recognized. The execution of MODIFY SUBCHANNEL is suppressed on all addressing and protection exceptions. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. 1 are reserved and must contain zeros; otherwise, an operand exception is recognized. General register 1 has the following format: Resulting Condition Code: o SCHIB information placed in subchannel Status-pending Busy Not operational I 2 3 Program Exceptions: • • • • Access (fetch, operand 2) Operand Privileged operation Specification Programming Note: If a device signals I/o-error alert while the associated sub channel is disabled, the channel subsystem issues the clear signal to the device and discards the I/o-error-alert indication without generating an I/o-interruption condition. If a device presents unsolicited status while the associated subchannel is disabled, that status is discarded by the channel subsystem without generating an I/o-interruption condition. However, if the status presented contains unit check, the channel subsystem issues the clear signal for the associated sub channel and does not generate an I/o-interruption condition. This should be taken into account when the program uses MODIFY SUBCHANNEL to enable a sub channel. For example, the medium on the associated device that was present when the subchannel became disabled may have been replaced, and, therefore, the program should verify the integrity of that medium. [SJ 'B23B' o 1//1/11//11/1111/1 16 24 31 If conditions allow, the channel-path-reset facility is signaled to asynchronously perform the channelpath-reset function on the designated channel path. The channel-path-reset function is summarized below in the section "Associated Functions" and is described in detail in the section "Channel-Path Reset" on page 17-6. Condition code 0 is set to indicate that the channelpath-reset facility has been signaled. Associated Functions Subsequent to the execution of RESET CHANNEL PATH, the channel-path-reset facility asynchronously performs the channel-path-reset function. Certain indications are reset at all subchannels that have access to the designated channel path, and the reset signal is issued on that channel path. Any I/O functions in progress at the devices are reset, but only for the channel path on which the reset signal is received. An I/O operation or chain of I/O operations taking place in multipath mode may be able to continue to execute on other channel paths in the multipath group, if any. (See the section "Channel-Path-Reset Function" on page 15-43.) The result of performing the channel-path-reset function on the designated channel path is communicated to the program by means of a channel report (see the section "Channel Report" on page 17-14). Reset Channel Path RCHP o 31 The channel-path-reset facility is signaled to perform the channel-path-reset function at the designated channel path. General register 1 contains, in bit positions 24-31, the channel-path identifier (CHPID) of the channel path on which the channel-path-reset function is to be performed. Bit positions 0-23 of general register Special Conditions Condition code 2 is set and no other action is taken when, on some models, the channel-path-reset facility is busy performing the channel-path-reset function for a previous execution of the RESET CHANNEL PATH instruction. Condition code 3 is set and no other action is taken when, on some models, the designated channel path is not operational for the execution of RES ET CHANNEL PATH. On these models, the channel path is not operational for the execution of RESET Chapter 14. I/O Instructions 14-7 CHANNEL PATH when the designated channel path is not physically available. The channel subsystem is signaled to perform the resume function at the designated subchannel. If the channel-path-reset facility is busy and the designated channel path is not physically available, it depends on the model whether condition code 2 or 3 is set. General register contains the subsystemidentification word, which designates the subchannel at which the resume function is to be performed. RESET CHANNEL PATH can encounter the program exceptions listed below. Bit positions 0-23 of general register 1 must contain zeros; otherwise, an operand exception is recognized. The subchannel is made resume-pending. Resulting Condition Code: o Function initiated The channel subsystem is signaled to asynchronously perform the resume function. The resume function is summarized below in the section "Associated Functions" and is described in detail in the section "Start Function and Resume Function" on page 15-17. 1 2 3 Logically prior to the setting of condition code 0 and only if the subchannel is currently in the suspended state, path-not-operational conditions at the subchannel, if any, are cleared. Busy Not operational Program Exceptions: • Operand • Privileged operation Condition code 0 is set to indicate that the actions described above have been taken. Programming Notes: 1. To eliminate the possibility of a data-integrity exposure for devices that have the capability of generating unsolicited device-end status, 1/0 operations in progress with such devices on the channel path for which RESET CHANNEL PATH is to be executed must be terminated by execution of either HALT SUBCHANNEL or CLEAR SUBCHANNEL. Otherwise, subsequent to receiving the reset signal, the device may present an unsolicited device end that may be interpreted by the channel subsystem as a solicited device end and cause command chaining to occur. 2. If the status-verification facility is being used and RESET CHANNEL PATH is executed without frrst stopping all ongoing operations associated with the channel path being reset, erroneous device-status-check conditions may be detected. Resume Subchannel [S] RSCH IB238 1 e 14-8 1////////////////1 16 31 ESAj370 Principles· of Operation Associated Functions Subsequent to the execution of RESUME SUBthe channel subsystem asynchronously performs the resume function. Except when the subchannel is subchannel-active, if the execution of RESUME SUBCHANNEL results in the setting of condition code 0, performance of the resume function causes execution of a currently suspended channel program to be resumed with the associated device, provided that the suspend flag for the current ccw has been set to zero by the program. If the suspend flag remains set to one, execution of the channel program remains suspended. But, if the subchannel is subchannel-active at the time the execution of RESUME SUBCHANNEL results in the setting of condition code 0, then it is unpredictable whether execution of the current program is resumed or whether it is found by the resume function that the subchanne1 has become suspended in the interim. The subchannel is found to be suspended by the resume function· only if the subchannel is status-pending with intermediate status when the resume-pending condition is recognized by the channel subsystem. (See the section "Start Function and Resume Function" on page 15-17.) CHANNEL, Special Conditions Condition· code 1 is set and no other action is taken when the subchannel is status-pending. Condition code 2 is set and no other action is taken when the resume function is not applicable. The resume function is not applicable when the subchannel (I) has any function other than the start function alone specified, (2) has no function specified, (3) is resume-pending, or (4) does not have suspend control specified for the start function in progress. Condition code 3 is set and no other action is taken when the subchannel is not operational for the resume function.· A subchannel is not operational for the resume function if the subchannel is not provided in the channel subsystem, has no valid device number assigned to it, or is not enabled. RESUME SUBCHANNEL can encounter the program exceptions listed below. Bit positions 0-15 of general register 1 must contain the value 0001 hex; otherwise, an operand exception is recognized. Resulting Condition Code: o 1 2 3 Function initiated Status-pending Function not applicable Not operational Program Exceptions: • Operand • Privileged operation Programming Notes: 1. When channel-program execution is resumed from the suspended state, the device views the resumption as the beginning of a new chain of commands. When the suspension of channelprogram execution occurs and the device requires that certain commands be first or appear only once in a chain of commands (for example, direct-access-storage. devices), the program must ensure that the appropriate commands in the proper sequence are fetched by the channel subsystem after channel-program execution is resumed. One way the program can ensure proper sequencing of commands at the device is by allowing the I/O interruption to occur for an intermediate interruption condition due to suspension. It is not reliable to notify the program that the subchannel is suspended by using the PCI flag in the ccw that contains the S flag because the PCI I/O interruption may occur before the subchannel is suspended. The scsw would indicate that an I/O operation is in progress at the subchannel and device in this case. The suspend flag of the target ccw should be set to zero before RESUME SUBCHANNEL is executed; otherwise, it is possible that the resume-pending condition may be recognized and the ccw refetched while the suspend flag is still one, in which case the resume-pending condition would be reset, and the execution of the channel program would be suspended. If the suspend flag of the target ccw is set to zero before the execution of RESUME SUBCHANNEL, the channel program is not suspended, provided that the subchannel is not subchannelactive at the time the execution of RESUME SUBCHANNEL results in the setting of condition code O. If condition code 0 is set while the subchannel is still subchannel-active, it is unpredictable whether the resume-pending condition is recognized by the channel subsystem or whether it is found by the resume function that the subchannel has become suspended in the interim. The subchannel is found to be suspended by the resume function only if the subchannel is status-pending with intermediate status at the time the resume-pending condition is recognized. When the subchannel is suspended, the execution of TEST SUBCHANNEL, which clears the intermediate interruption condition' also clears the indication of resumepending. 2. Some models recognize a resume-pending condition only after a ccw having a valid S flag set to one is fetched. Therefore, if a subchannel is resume-pending and, during execution of the channel program, no ccw is fetched having a valid s flag set to one, the subchannel remains resume-pending until the primary interruption condition is cleared by TEST S~BCHANNEL. 3. Path availability is not tested during the execution of RESUME SUBCHANNEL. Instead, path availability is tested when the channel subsystem begins performance of the resume function. 4. The cpntents of the ccw fetched during performance of the resume function may be different from the contents of the same ccw when Chapter 14. I/O Instructions 14-9 it was previously fetched and contained a valid S flag. Set Address Limit SAL Special Conditions [S] IB237 1 e start function. For a description of the manner in which address-limit checking is performed, see the section "Address-Limit Checking" on page 17-12. 111111111111111111 16 can encounter the program exceptions listed below. The address in general register I must be designated on a 64K-byte boundary, and the leftmost bit of general register 1 must be zero; otherwise, an operand exception is recognized. SET ADDRESS LIMIT 31 The address-limit-checking facility is signaled to use the specified address as the address-limit value, and the specified address is passed to the facility. Condition Code: The code remains unchanged. Program Exceptions: • Operand • Privileged operation General register I contains the address to be used as the address-limit value. The address is designated on a 64K-byte boundary, and the leftmost bit of general register I is zero. Set Channel Monitor General register I has the following format: SCHM lei IB23CI Address-Limit Value e 1 31 Associated Functions The value that is used by the address-limit-checking facility when determining whether to permit or prohibit a data access is called the address-limit value. The initialized address-limit value is zero. The initial address-limit value is used by the addresslimit-checking facility until the facility recognizes a signal (caused by the execution of SET ADDRESS LIMIT) to use a specified address. The recognition of this specified address as the new address-limit value occurs asynchronously with respect to the execution of SET ADDRESS LIMIT. If address-limit checking is specified for a subchannel, then whether the specified address is used by the address-limit-checking facility (when determining whether to permit or prohibit a data access) depends on whether SET ADDRESS LIMIT was executed before, during, or after the execution of START SUBCHANNEL for that subchannel. If SET ADDRESS LIMIT is executed before START SUBCHANNEL, then the specified address is used by the address-limit-checking facility. If SET ADDRESS LIMIT is executed during or after the execution of START SUBCHANNEL, then it is unpredictable whether the specified address is used by the address-limit-checking facility for that particular 14-10 [S] ESA/370 Principles of Operation e 111111111111111111 16 31 The monitoring modes of the channel subsystem are made either active or inactive, depending on the setting of the measurement-mode-control bits in general register 1. Depending on the setting of the measurement-mode-control bit for measurementblock update, the channel subsystem is signaled to make the mode active, or the mode is made inactive. If the measurement-mode-control bit for is one, the measurement-block update measurement-block origin and the measurementblock key are passed to the channel subsystem. Depending on the setting of the measurementmode-control bit for device-connect time, the mode is made active or inactive. General register I has the following format: IMBK leeee eaeeeeee aeseesee eeeeselMlol e 4 30 31 Bit positions 0-3 of general register 1 contain the measurement-block key (MBK). When bit 30 is one MBK specifies the access key that is to be used by the channel subsystem when it accesses the measurement-block area. Otherwise, MBK is ignored. Bit 30 (M) of general register 1 is the measurementmode-control bit that controls the measurementblock-update mode. When bit 30 of general register 1 is one and conditions allow, the measurement-block-update facility is signaled to asynchronously make the measurement-blockupdate mode active. In addition, the MBO address (in general register 2) and the measurement-block key (MBK) (in general register 1) are passed to the measurement-block-update facility. Furthermore, when bit 30 is one, bit 0 of general register 2 must be zero. The asynchronous functions that are performed by the measurement-block-update facility are summarized below in the section "Associated Functions" and are described in detail in the section "Channel-Subsystem Monitoring" on page 17-1. When bit 30 of general register 1 is zero and conditions allow, the measurement-block-update mode is made inactive if it is active or remains inactive if it is inactive. The contents of bit positions 0-3 (MBK) of general register 1 and the contents of general register 2 are ignored. Bit 31 (D) of general register 1 is the measurementmode-control bit· that controls the device-connecttime-measurement mode. When bit 31 is one and conditions allow, the device-connect-timemeasurement mode is made active if it is inactive or remains active if it is active. When bit 31 is zero and conditions allow , the device-connect-timemeasurement mode is made inactive if it is active or remains inactive if it is inactive. The remaining bit positions of general register 1 are reserved and must contain zeros; otherwise, an operand exception is recognized. General register 2 has the following format: MBO Address (3 1 31 Bit 0 of general register 2 must be zero· when bit 30 (M) of general register 1 is one; otherwise, an operand exception is recognized. When bit 30 (M) of general register 1 is zero, bit 0 of general register 2 is ignored. Bit positions 1-31 of general register 2 contain the absolute address of the measurementblock origin (MBO). When bit 30 (M) of general register 1 is one the MBO address designates the beginning of the measurement-block area. The origin of the measurement-block area must be des- ignated on a 32-byte boundary. The MBO address is used by the channel subsystem to locate measurement blocks. When bit 30 (M) of general register 1 is zero, the contents of general register 2 are ignored. If the channel-subsystem timer that is used by the channel-sub system-monitoring facilities is in the error state, the state is reset. This happens independent of the setting of the two measurementmode-control bits. (See the section "ChannelSubsystem Timing" on page 17-1 for a description of the timing facilities. Associated Functions When the measurement-block-update facility is signaled (by means of SET CHANNEL MONITOR) to make the measurement-block-update mode active, the functions that are performed by the facility depend on whether or not the mode is already active when the signal is generated. If the measurement-block-update mode is inactive when the signal is generated, the mode remains inactive until the measurement-block-update facility recognizes the signal. When the measurementblock-update facility recognizes the signal, the measurement-block-update mode is made active, and the MBK and MBO associated with that signal (that is, the MBKand MBO that were passed when the signal was generated) are used to control the storing of measurement data. If the measurement-block-update mode is active when the signal is generated, the mode remains active, and the MBK and MBO associated with the execution of a previous SET CHANNEL MONITOR instruction continue to be used to control the of measurement data until the storing measurement-block-update facility recognizes the signal. When the measurement-block-update facility recognizes the signal, the MBK and MBO associated with that signal are used instead of the MBK and MBO associated with the execution of a previous SET CHANNEL MONITOR instruction. In either of the above cases, the measurementblock-update facility recognizes the signal during, or subsequent to, the execution of the SET CHANNEL MONITOR instruction that caused the signal to be generated and logically prior to the performance of any start function that is initiated by the subsequent execution of START SUBCHANNEL for a subchannel that is enabled for measurement by this Chapter 14. I/O Instructions 14-11 facility. If a subchannel that is enabled for, measurement by this facility already has a start function in progress when the signal is generated, it is unpredictable when measurement data for that subchannel is stored by using the MBK and MBO associated with that signal. While the measurement-block-update mode is active, performance measurements are accumulated for subchannels that are enabled for measurementblock update. Measurements for a subchannel are accumulated in a single 32-byte measurement block within the measureinent-block area. A subchannel is enabled for the measurement-block-update mode by setting the measurement-block-update-enable bit to one in the SCHIB and then executing MODIFY SUBCHANNEL for that subchannel. The measurement block that is used to accumulate measurements for a subchannel is determined by the measurement-block index that is contained in the subchannel. When the device-connect-time-measurement mode is active, measurements of the length of time that the device is actively communicating with the channel subsystem dutfu.g the execution of a channel program are accumulated for subchannels that are enabled for device-connect-time measurement. Measurements for a subchannel are provided in the ESW of the IRB. A subchannel is enabled for device-connect-time-measurement mode by setting the device-connect-timemeasurement-enable bit to one in the SCHIB and then executing MODIFY SUBCHANNEL for that subchannel. F or a more detailed description of the measurement-block-update mode, the format and contents of the measurement block, and the deviceconnect-time-measurement mode, see the section "Channel-Subsystem Monitoring" on page 17-1. Special Conditions CHANNEL MONITOR can encounter the program exceptions listed below. Bits 4-29 of general register 1 must be zeros; bits 1-31 of general register 2, the MBO address, must be designated on a 32-byte boundary when bit 30 (M) of general register 1 is one; and bit 0 of general register 2 must be zero when bit 30 (M) of general register 1 is one; otherwise, an operand exception is recognized. SET Condition Code: The code remains unchanged. 14-12 ESA/370 Principles of Operation Program Exceptions: • Operand • Privileged operation Programming Note: When the channel subsystem is initialized, the measurement-block-update and device-connect-time-measurement modes are made inactive. Start Subchannel [S] 'B233' o 16 20 31 The channel subsystem is signaled to asynchronously perform the start function for the associated device, and the execution parameters that are contained in the designated ORB are placed at the designated subchannel. (See the section "OperationRequest Block" on page 15-21.) General register contains the subsystemidelltification word, which designates the subchannel that is to be started. The second-operand address is the logical address of the ORB and is designated on a word boundary. The execution parameters contained in the ORB are placed at the subchannel. In some models, when START SUBCHANNEL is executed and the subchannel is status-pending with only secondary status, the status-pending condition is discarded at the subchannel. The subchannel is made start-pending, and the start function is indicated at the subchannel. Logically prior to the setting of condition code 0, path-not-operational conditions at the subchannel, if any, are cleared. The channel subsystem is signaled to asynchronously perform the start function. The start function is summarized below in the section "Associated Functions" and is described in detail in the section "Start Function and Resume Function" on page 15-17. Condition code 0 is set to indicate that the actions described above have been taken. Associated Functions Subsequent to the execution of START SUBCHANNEL, the channel subsystem asynchronously perfonns the start function. The contents of the ORB, other than the fields that must contain all zeros, are checked for validity. In some models, the fields of the ORB that must contain zeros are also checked asynchronously (rather than during the execution of the instruction). When invalid fields are detected asynchronously, the subchannel becomes status-pending with primary, secondary, and alert status and with deferred condition code 1 and program check indicated. (See the section "Program Check" on page 16-29.) In this situation, the 'I/O operation or chain of I/O operations is not initiated at the device, and the condition is indicated by the start-pending bit being stored as one when the scsw is cleared by the execution of TEST SUBCHANNEL. (See the section "Subchannel-Status Word" on page 16-6). In some models, path availability is tested asynchronously (rather than as part of the execution of the instruction). When no channel path is available for selection, the subchannel becomes statuspending with primary and secondary status and with deferred condition code 3 indicated. The I/O operation or chain of I/O operations is not initiated at the device, and this condition is indicated by the start-pending bit being stored as one when the scsw is cleared by the execution of TEST SUB- progress at thesubchannel (see the section "Function Control (FC)" on page 16-12). Condition code 3 is set and no other action is taken when the subchannel is not operational for START SUBCHANNEL. A subchannel is not operational for START SUBCHANNEL if the subchannel is not provided in the channel subsystem, has no valid device number assigned to it, or is not enabled. A subchannel is also not operational for START SUBCHANNEL, in some models, when no channel path is available for selection. In these models, the lack of an available channel path is detected as part of START SUBCHANNEL execution. In other models, channel path availability is only tested as part of the asynchronous start function. START SUBCHANNEL can encounter the program exceptions listed below. The execution of START SUBCHANNEL is suppressed on all addressing and protection exceptions. In word 1 of the ORB, bits 5-7, 13-15, and 25-31 must be zeros, in word 2 of the ORB, bit 0 must be 0; otherwise, in some models, an operand exception is recognized. In other models, an I/o-interruption condition is generated indicating program check as part of the asynchronous start function. CHANNEL. Bits 0-15 of general register I must contain 0001 hex; when the incorrect-Iength-indicationsuppression facility is not installed, bit 24 of word 1 of the ORB must be zero; otherwise, an operand exception is recognized. If conditions allow, a channel path is chosen and execution of the channel program that is designated in the ORB is initiated. (See the section "Start Function and Resume Function" on page 15-17.) The second operand must be designated on a word boundary; otherwise, a specification exception is recognized, and the execution of START SUBCHANNEL is suppressed. Special Conditions Resulting Condition Code: Condition code 1 is set and no other action is taken if the subchannel is status-pending when START SUBCHANNEL is executed. In some models, condition code 1 is not set when the subchannel is status-pending with only secondary status; instead, the status-pending condition is discarded. Condition code 2 is set and no other action is taken when a start, halt, or clear function is currently in o Function initiated 1 2 3 Status-pending Busy Not operational Program Exceptions: • • • • Access (fetch, operand 2) Operand Privileged operation Specification Chapter 14. I/O Instructions 14-13 operand must be designated on a 32-byte boundary; otherwise, a specification exception is recognized. Store Channel Path Status STeps [S] 02 (82) Condition Code: The code remains unchanged. IB23AI o 16 20 31 A channel-path-status word of up to 256 bits is stored at the designated location. The second-operand address is the logical address of the location where the channel-path-status word is to be stored and is designated on a 32-byte boundary. The channel-path-status word indicates which channel paths are actively communicating with a device at the time STORE CHANNEL PATH STATUS is executed. Bit positions 0-255 correspond, respectively, to the channel paths having the channel-path identifiers 0-255. Each of the 256 bits at the designated location is set to one, set to zero, or left unchanged, as follows: • For all channel paths in the configuration that are actively communicating with devices at the time STORE CHANNEL PATH STATUS is executed, the corresponding bits are stored as ones. • For all channel paths that are (1) provided in the system (PIM bit in the scsw is one) and (2) in the configuration, but not currently being used by the channel subsystem in actively communicating with devices, the corresponding bits are stored as zeros. • For all channel paths' that are not provided in the system .(PIM bit in the scsw is zero), the corresponding bits either are not stored or are stored as zeros. • For all channel paths in the configuration that are in the channel-path-terminal state or are not physically available (the corresponding PAM bit in the scsw is zero), the corresponding bits are stored as zeros. Special Conditions STORE CHANNEL PATH STATUS can encounter the program exceptions listed below. The execution of STORE CHANNEL PATH STATUS is suppressed on all addressing and protection exceptions. The second 14-14 ESAj370 Principles of Operation Program Exceptions: • Access (store, operand 2) • Privileged operation • Specification Programming Note: To ensure a consistent interpretation of channel-path-status-word bits, the program should, prior to the initial use of the area, store zeros at the location where the channel-pathstatus word is to be stored. Store Channel Report Word [S] IB239 1 o 16 28 31 A CRW containing information affecting the channel subsystem is stored at the designated location. The second-operand address is the logical address of the location where the CRW is to be stored and is designated on a word boundary. When a malfunction or other condition affecting channel-subsystem operation is recognized, a channel report (consisting of one or more CRWS) describing the condition is made pending for retrieval and analysis by the program. The channel report contains information concerning the identity and state of a facility of the channel subsystem following the detection of the malfunction or other condition. For a description of the channel report, the CRW, and program-recovery actions related to the channel subsystem, see the section "ChannelSubsystem Recovery" on page 17-13. When one or more channel reports are pending, the instruction causes a CR W to be stored at the designated location and condition code 0 to be set. A pending CRW can only be stored by executing STORE CHANNEL REPORT WORD and, once stored, is no longer pending. Thus, each pending CRW is presented only once to the program. When no channel reports are pending in the channel subsystem, execution of STORE CHANNEL REPORT WORD causes zeros to be stored at the designated location and condition code 1 to be set. Special Conditions STORE CHANNEL REPORT WORD can encounter the program exceptions listed below. The execution of STORE CHANNEL REPORT WORD is suppressed on all addressing and protection exceptions. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. Resulting Condition Code: o 1 CRW stored Zeros stored The information that is stored in the SCHIB consists of the path-management-control word, the scsw, and three words of model-dependent information. (See the section "Subchannel-Information Block" on page 15-1.) The execution of STORE SUBCHANNEL does not change any information contained in the subchannel. Condition code 0 is set to indicate that control and status information for the designated subchannel has been stored in the SCHIB. Whenever the execution of STORE SUBCHANNEL results in the setting of condition code 0, the information in the SCHIB indicates a consistent state of the subchannel. 2 3 Program Exceptions: • Access (store, operand 2) • Privileged operation • Specification Special Conditions Programming Notes: 1. General register contains the sub systemidentification word, which designates the subchannel for which the information is to be stored. The second-operand address is the logical address of the SCHIB and is designated on a word boundary. CRW overflow conditions may occur if STORE CHANNEL REPORT WORD is not executed to clear pending channel reports. If the overflow condition is encountered, one or more channelreport words have been lost. (See the section "Channel-Subsystem Recovery" on page 17-13 for details.) 2. A pending CRW can be cleared by any CPU in the configuration executing STORE CHANNEL REPORT WORD, regardless of whether a machine-check interruption has occurred in any Condition code 3 is set and no other action is taken when the designated subchannel is not operational for STORE SUBCHANNEL. A subchannel is not operational for STORE SUBCHANNEL if the subchannel is not provided in the channel subsystem. can encounter the program exceptions listed below. Bit positions 0-15 of general register 1 must contain the value 0001 hex; otherwise, an operand exception is recognized. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. STORE SUBCHANNEL Resulting Condition Code: CPu. o Store Subchannel SCHIB stored 1 STSCH 02(82) 2 3 [S] Not operational Program Exceptions: 18234 1 16 20 31 Control and status information for the designated subchannel is stored in the designated SCHIB. • • • • Access (store, operand 2) Operand Privileged operation Specification Chapter 14. I/O Instructions 14-15 Programming Notes: 1. Device status that is stored in the scsw may include device-busy, control-unit-busy, or control-unit-end indications. 2. The information that is stored in the SCHIB is obtained from the subchannel. The STORE SUBCHANNEL instruction does not cause the channel subsystem to interrogate the addressed device. 3. STORE SUBCHANNEL may be executed at any time to sample conditions existing at the subchannel, without causing any pending status conditions to be cleared. 4. Repeated execution of STORE SUBCHANNEL without an intervening delay (for example, to determine when a subchannel changes state) should be avoided because repeated accesses of the subchannel by the CPU may delay or prohibit access of the subchannel by the channel subsystem to update the subchannel. Pending I/o-interruption requests are accepted only for those I/o-interruption subclasses allowed by the I/o-interruption subclass mask in control register 6 of the CPU executing the instruction. If no I/o-interruption requests exist that are allowed by control register 6, the I/o-interruption code is not stored, the second-operand location is not modified, and condition code 0 is set. If a pending I/o-interruption request is accepted, the I/o-interruption code is stored, the pending I/o-interruption request is cleared, and condition code 1 is set. The I/o-interruption code that is stored is the same as would be stored if an I/O interruption had occurred. However, PSWs are not swapped, as when an I/o-interruption occurs. The I/o-interruption code that is stored during execution of the instruction is dermed as follows: Word a 1 Test Pending Interruption Subsystem-Identification Word Interruption Parameter 31 [S] TPI See the section "I/O-Instruction Formats" on page 14-1. Subsystem-Identification Word: 18236 1 o 16 20 31 The I/o-interruption code for a pending I/o-interruption at the subchannel is stored at the location designated by the second-operand address, and the pending I/o-interruption request is cleared. The second-operand address, when nonzero, is the logical address of the location where the I/o-interruption code is to be stored and is designated on a word boundary. If the second-operand address is zero, the I/o-interruption code is stored at reallocations 184-191. In this case, low-address protection and key-controlled protection do not apply. In this access-register mode when the secondoperand address is zero, it is unpredictable whether access-register translation occurs for access register B2. If the translation occurs, the resulting segmenttable designation is not used; that is, the interruption code still is stored in real locations 184-191. 14-16 ESA/370 Principles of Operation Interruption Parameter: Word 1 contains a fourbyte parameter which is specified by the program and which previously was passed to the subchannel in word 0 of the ORB or the PMCW. When a device presents alert status and the interruption parameter was not passed previously to the su bchannel by executing START SUBCHANNEL or MODIFY SUBCHANNEL, this field contains zeros. Special Conditions TEST PENDING INTERRUPTION can encounter the program exceptions listed below. The execution of TEST PENDING INTERRUPTION is suppressed on all addressing and protection exceptions. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. Resulting Condition Code: o 1 2 3 Interruption code not stored Interruption code stored Program Exceptions: • Access (store, operand address nonzero only) • Privileged operation • Specification Programming 2, second-operand Notes: 1. TEST PENDING INTERRUPTION should only be executed with a second-operand address of zero when 1/0 interruptions are masked off. Otherwise, an I/o-interruption code stored by the instruction may be lost if an I/o-interruption occurs. The I/o-interruption code that identifies the source of the I/o-interruption is stored at real locations 184-191, replacing the code that is stored by the· instruction. 2. In the access-register mode when the secondoperand address is zero, an access exception is recognized if access-register translation occurs and the access register is in error. This exception can be prevented by making the B2 field zero or by placing 00000000 hex, 00000001 hex, or any other valid contents in the access register. Test Subchannel o 82 16 20 The information that is stored in the IRB consists of the scsw, the extended-status word, and the (See the section extended-control word. "Interruption-Response Block" on page 16-6.) If the subchannel is status-pending the statuspending bit of the status-control field is stored as one. Whether or not the subchannel is statuspending has an effect on the functions that are performed when TEST SUBCHANNEL is executed. When the subchannel is status-pending and TEST SUBCHANNEL is executed, information (as described above) is stored in the IRB, followed by the clearing of certain conditions and indications that exist at the subchannel (as described in Figure 14-2 on page 14-18). If an I/o-interruption request is pending for the subchannel, the request is cleared. Condition code 0 is set to indicate that these actions have been taken. When the sub channel is not status-pending and TEST SUBCHANNEL is executed, information (as described above) is stored in the IRB, and no conditions or indications are cleared. Condition code 1 is set to indicate that these actions have been taken. [S] '8235' General register contains the sub systemidentification word, which designates the subchannel for which the information is to be stored. The second-operand address is the logical address of the IRB and is designated on a word boundary. 31 Control and status information for the subchannel is stored in the designated IRB. Figure 14-2 on page 14-18 describes which conditions and indications are cleared by TEST SUBCHANNEL when the subchannel is status-pending. All other conditions and indications at the subchannel remain unchanged. Chapter 14. I/O Instructions 14-17 can encounter the program exceptions listed below. When the execution of TEST SUBCHANNEL is terminated on addressing and protection exceptions, the state of the subchannel is not changed. Bit positions 0-15 of general register 1 must contain 0001 hex; otherwise, an operand exception is recognized. The second operand must be designated on a word boundary; otherwise, a specification exception is recognized. TEST SUBCHANNEL Subchannel Condition* Field Sec Status Alert Int Pri Status Status Status Status Pdg Pdg Pdg Pdg Pdg Alone Function Control C Nc C C C Activity Control Cp Nr Cp Cp Cp Status Control Cs Cs Cs Cs Cs N condition C Resulting Condition Code: o 1 IRB stored; subchannel status-pending IRB stored; subchannel not status-pending 2 Nr C C C Explanation: * Note that the rightmost column applies to status-pending when it is alone. The other four status-pending conditions result in the clearing actions given. These actions apply both whe'n a si ngl e status-pendi ng conditi on occurs and when a combination of the four status-pending conditions occurs. In the combination case, all the clearing actions of the individual cases apply. C Cleared. Cp The resume-, start-, halt-, clear-pending, and suspended conditions are cleared. Cs The status-pending condition is cleared. Nc Not changed unless function control indicates the halt function. If the halt function is indicated, conditions are cleared as for status-pending alone. Nr Not changed unless function control indicates either the halt function or the start function and activity control indicates resume pending and suspended. If the halt function is indicated, the conditions are cleared as for status-pending alone. If the start function is indicated and activity control indicates resume pending and suspended, the resume-pending condition and the N condition are cleared. Figure 14-2. Conditions and Indications Oeared at the Subchannel by TEST SUBCHANNEL Special Conditions Condition code 3 is set and no other action is taken when the subchannel is not operational for TEST SUBCHANNEL. A subchannel is not operational for TEST SUBCHANNEL if the subchannel is not provided, has no valid device number associated with it, or is not enabled. 14·18 ESA/370 Principles of Operation 3 Not operational Program Exceptions: • • • • Access (store, operand 2) Operand Privileged operation Specifisiation Programming Notes: 1. Device status that is stored in the scsw may include device-busy, control-unit-busy, or control-unit-end indications. 2. The information that is stored in the I RB is obtained from the subchannel. The TEST SUBCHANNEL instruction does not cause the channel subsystem to interrogate the addressed device. 3. When an I/O interruption occurs, it is the result of a status-pending condition at the subchannel, and typically TEST SUBCHANNEL is TEST SUBexecuted to clear the status. CHANNEL may also be executed at any other time to sample conditions existing at the subchannel. 4. Repeated execution of TEST SUBCHANNEL to determine when a start function has been completed should be avoided because there are conditions under which the completion of the start function mayor may not be indicated. For example, if the channel subsystem is holding an interface-control-check (I FCC) condition in abeyance (for any subchannel) because another subchannel is already status-pending, and if the start function being tested by TEST SUBCHANNEL has as the only path available for selection the channel path with the IFCC condition, then the start function may not be initiated until the status-pending condition in the other subchannel is cleared, allowing the IFCC condition to be indicated at the subchannel to which it applies. 5. Repeated execution of TEST SUBCHANNEL without an intervening delay, for example, to determine when a subchannel changes state, should be avoided because repeated accesses of the subchannel by the CPU may delay or prohibit access of the subchannel by the channel subsystem in updating the subchannel. 6. The priority of I/o-interruption handling by a CPU can be modified by execution of TEST SUBCHANNEL. When TEST SUBCHANNEL is executed and the designated subchannel has an I/o-interruption request pending, that I/o-interruption request is cleared and the scsw is stored, without regard to any previously established priority. The relative priority of the is remaining I/o-interruption requests unchanged. Chapter 14. I/O Instructions 14-19 Chapter 15. Basic 1/0 Functions Control of Basic 1/0 Functions . . . . Subchanne1-Information Block Path-Management-Control Word Subchannel-Status Word Model-Dependent Area . . . . . Summary of Modifiable Fields Channel-Path Allegiance . . . . . . Working Allegiance . . . . . . . Active Allegiance . . . . . . . . Dedicated Allegiance . . . . . . . . . . . .... . Channel-Path Availability Control-Unit Type . . . . . . . . . . . . Clear Function . . . . . . . . . . . . . . . . Clear-Function Path Management Clear-Function Subchannel Modification Clear-Function Signaling and Completion Halt Function . . . . . . . . . . . . . . . . . Halt-Function Path Management ... . Halt-Function Signaling and Completion Start Function and Resume Function Start-Function and Resume-Function Path Management ... Execution of 1/0 Operations . . . . . . . . Blocking of Data Operation-Request Block . . . . . Channel-Command Word Command Code . . . . . . . . . . 15-1 15-1 15-2 15-7 15-7 15-7 15-10 15-11 15-11 15-11 15-12 15-12 15-13 15-13 15-13 15-14 15-14 15-15 15-15 15-17 15-18 15-19 15-21 15-21 15-23 15-24 Some I/O instructions specify to the channel subsystem that a function is to be petformed. Collectively, these functions are referred to as the basic I/O functions. The basic I/O functions are the clear, halt, start, resume, and channel-path-reset functions. Control of Basic 1/0 Functions Information that is present at the subchannel controls how the clear, halt, resume, and start functions are petformed. This information is communicated to the program in the subchannel-information block during execution Of,STORESUBCHANNEL. Designation of Storage Area 15-25 Chaining . . . . . . . . . . . 15-26 Data Chaining . . . . . . 15-28 15-29 Command Chaining '" Skipping . . . . . . . . . . . 15-30 15-30 Program-Controlled Interruption CCW Indirect Data Addressing 15-31 Suspension of Channel-Program ............ . 15-32 Execution ............ . Commands 15-34 . . . . . . . . . . . . . . 15-35 Write .. . ........ . Read .. 15-35 Read Backward . . . . . 15-36 Control 15-36 Sense . . . . . . . ... . 15-37 . .... . Sense ID ... . 15-39 " ..... . 15-40 Transfer in Channel Command Retry . . . . . . . . . . 15-41 Concluding 1/0 Operations During 15-41 Initiation . . . . . . . . . . . . . . . Immediate Conclusion of 1/0 Operations 15-42 Concluding 1/0 Operations During Data Transfer . . . . . . . . . . . . . . . . . . 15-42 15-43 Channel-Path-Reset Function . . . . . . Channel-Path-Reset-Function Signaling 15-43 Channel-Path-Reset Function-Completion Signaling 15-44 Subchannel-Information Block The subchannel-information block (SCHIB) is the operand of the MODIFY SUBCHANNEL and STORE SUBCHANNEL instructions. The two rightmost bits of the SCHIB address are zeros, designating the SCHIB on a word boundary. The SCllIB contains three major fields: the path-management-control word (PMCW), the subchannel-status word (SCSW), and a model-dependent area. (Figure 15-1 on page 15-2 shows the format of the PMCW, and Figure 16-2 on page 16-7 shows the format of the scsw.) Chapter 15. Basic I/O Functions 15-1 STORE SUBCHANNEL is used to store the current PMCW, the SCSW, and model-dependent data of the designated subchannel. MODIFY SUBCHANNEL alters certain PMCW fields at the subchannel. When the program needs to change the contents of one or more of the PMCW fields, the normal procedure is (I) to execute STORE SUBCHANNEL to obtain the current contents, (2) to perform the required modifications to the PMCW in main storage, and (3) to execute MODIFY SUBCHANNEL to pass the new information to the subchannel. The SCHIB has the following format: e Interruption Parameter I I II eel ISC leea E LM Mt41 D T v 2 LPM PNOM MBI 3 Device Number LPUM PIM POM PAM 4 CHPID-a CHPID-1 CHPID-2 CHPID-3 5 CHPID-4 CHPID-5 CHPID-6 CHPID-7 6 aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa a 16 31 Figure 15-1. PMCW Format Word e 1 2 Path-Management-Control Word 3 Interruption Parameter: Bits 0-31 of word 0 contain the interruption parameter that is stored as word 1 of the interruption code. The interruption parameter can beset to any value by START SUBCHANNEL and MODIFY SUBCHANNEL. The initial value of the interruption parameter is zero. 4 5 6 7 8 Subchannel-Status Word 9 Ie 11 Model-Dependent Area 12 Path-Management-Control Word The path-management-control word (PMCW) has the format shown in Figure 15-1 when the subchannel is valid (see the section "Device Number Valid (V)" on page 15-4). I/O-Interruption Subclass Code: Bits 2-4 of word 1 contain a binary number (0-7) which corresponds to the bit position of the I/o-interruption subclassmask bit in control register 6 of each CPU in the configuration. The setting of that mask bit in control register 6 of a CPU controls the recognition of interruption requests relating to this subchannel by that CPU (see the section "Priority of Interruptions" on page 16-5). The ISC can be set to any value by MODIFY SUBCHANNEL. The initial value of the ISC is zero. Reserved: Bits 0-1 and 5-7 5-6 of word 1 are reserved and stored as zeros by STORE SUBCHANNEL. They must be zeros when MODIFY SUBCHANNEL is executed; otherwise, an operand exception is recognized. Enabled (E): Bit 8 of word 1, when one, indicates that the subchannel is enabled for all I/O functions. When the E bit is zero, status presented by the device is not made available to the program, and I/O instructions other than MODIFY SUBCHANNEL and STORE SUBCHANNEL that are executed for the designated sub channel cause condition code 3 to be set. The E bit can be either zero or one when MODIFY SUBCHANNEL is executed; initially, all subchannels are not enabled; IPL causes the IPL I/O device to become enabled. limit Mode (M): Bits 9-10 of word 1 defme the limit mode (LM) of the subchannel. The limit mode is used by the channel subsystem when 15-2 ESAj370 Principles of Operation address-limit checking is invoked for an I/O operation. (See the section "Address-Limit Checking" on page 17-12.) Address-limit checking is under the control of the address-limit-checking-control bit that is passed to the subchannel in the operationrequest block (ORB) during the execution of START SUBCHANNEL. (See the section "Address-LimitChecking Control (A)" on page 15-22. The definitions of these bits, whose values are used during data transfer, are as follows: Bit 9 o Bit 10 0 o 1 o Function Initialized value. No limit checking is performed for this subchannel. Data address must be equal to, or greater than, the current address limit. Data address must be less than the current address limit. Reserved. Bits 9 and 10 can contain any of the f!fst three bit combinations shown above when MODIFY SUBCHANNEL is executed. Specification of the reserved bit combination in the operand causes an operand exception to be recognized when MODIFY SUBCHANNEL is executed. Specification of the reserved bit combination in the operand causes an operand exception to be recognized when MODIFY SUBCHANNEL is executed. Measurement Mode Enable (MM): Bits 11 and 12 of word 1 enable the measurement-block-update mode and the device-connect-time-measurement mode, respectively, of the subchannel. These bits can contain any value when MODIFY SUBCHANNEL is executed; initially, neither measurement mode is enabled. The defmition of each of these bits is as follows: Bit 11 o Bit 12 o 1 Measurement-Block-Update Enable: Initialized value. The subchannel is not enabled for measurement-block update. Storing of measurement-block data does not occur. The subchannel is enabled for measurementblock update. If the measurement-blockupdate mode is active, measurement data is accumulated in the measurement block at the time channel-program execution is completed or suspended at the subchannel, provided no error conditions described by subchannel logout have been detected. If the measurement-block-update mode is inactive, no measurement-block data is stored. Device-Connect-Time-Measurement Enable: Initialized value. The subchanne1 is not enabled for device-connect-time measurement. Storing of the device-connect-time interval (DCTI) in the extended-status word (ESW) does not occur. The sub channel is enabled for deviceconnect-time measurement. If the deviceconnect-time-measurement mode is active and timing facilities are provided for the subchannel, the value of the DCTI is stored in the ESW when TEST SUBCHANNEL is executed after channel-program execution is completed or suspended at the subchannel, provided no error conditions described by subchannel logout have been detected. If the device-connect-time-measurement mode is inactive, no measurement values are stored in the ESW. The meaning of the measurement-mode (MM) enable bits described above applies when the timing-facility bit for the subchannel is one. When the timing-facility bit is zero, the effect of the MM bits is changed, as described below under "Timing Facility." (For more discussion on measurement modes, see the sections "Measurement-Block Update" on page 17-2 and "Device-Connect-Time Measurement" on page 17-5.) Multipath Mode (0): Bit 13 of word 1, when one, indicates that the sub channel operates in multipath mode when executing an I/O operation or chain of I/O operations. For proper operation in multipath mode when more than one channel path is available for selection, the associated device must have the dynamic-reconnection feature installed and Chapter 15. Basic I/O Functions 15-3 must be set up for multipath-mode operation. During performance of a start function in multipath mode, a device is allowed to request service from the channel subsystem over any of the channel paths indicated at the subchannel as· being available for selection (see the sections "Logical-Path Mask (LPM)" and "Path-Available Mask (PAM)" on page 15-7). Bit 13, when zero, indicates that the subchannel operates in single-path mode when executing an I/O operation or chain of I/O operations. In single-path mode, the entire start function is performed by using the channel path on which the fIrst command of the I/O operation or chain of I/O operations was accepted by the device. The D bit can be either zero or one when MODIFY SUBCHANNEL is executed; initially the subchannel is in single-path mode. Bit 14 of word 1, when one, indicates that the channel-sub system-timing facility is available for the subchannel and is under the control of the two measurement-mode-enable bits (MM) and SET CHANNEL MONITOR. Bit 14, when zero, indicates that the channel-subsystem-timing facility is not available for the subchannel. When bit 14 is zero, the START SUBCHANNEL count is the only measurement data that can be accumulated in the measurement block for the subchannel. Storing of the START SUBCHANNEL count is under the control of bit 11 and SET CHANNEL MONITOR, as described above under "Measurement Mode Enable." Similarly, if the T bit is zero, no deviceconnect-time-interval (DCTI) values can be measured for the subchannel. (See the sections "Measurement-Block Update" on page 17-2 and on "Device-Connect-Time Measurement" page 17-5.) Timing Facility (T): Device Number Valid (V): Bit 15 of word 1, when one, indicates that the device-number field (see below) contains a valid device nUlnber and that a device associated with this subchannel may be physically installed. Bit 15 when zero indicates that the subchannel is not valid, there ·is no I/O device currently associated With the subchannel, and the contents of all other defmed fields of the SCHIB are unpredictable. Device Number: Bits 16-31 of word 1 contain the binary representation of the four-digit hexadecimal device number of the device that is associated with this subchannel. The device number is a systemunique parameter that is assigned to the subchannel and the associated device when the device is installed. 15-4 ESAj370 Principles of Operation Logical.. Path Mask (LPM): Bits 0-7 of word 2 indicate the logical availability of channel paths to the associated device. Each bit of the LPM corresponds one-for-one, by relative bit position, with a CHPID located in an associated byte of words 4 and 5 of the SCHIB. (Each CHPID contains an 8-bit value which uniquely identifies the physical channel path.) A bit set to one means that the corresponding channel path is logically available; a zero means the corresponding channel path is logically not available. When a channel path is logically not available, the channel subsystem does not use that channel path to initiate performance of any clear, halt, resume, or start function, except when a dedicated allegiance exists for that channel path. When a dedicated allegiance exists at the subchannel for a channel path, the logical availability of the channel path is ignored whenever a clear, halt, resume, or start function is performed. (See the section "Channel-Path Allegiance" on page 15-10). If the subchannel is idle, the logical availability of the channel path is ignored whenever the control unit initiates a request to present alert status to the channel subsystem. The logical availability of a channel path associated with the subchannel can be changed by setting the corresponding LPM bit in the SCHIB and then executing MODIFY SUBCHANNEL, or by setting the corresponding LPM bit in the ORB and then executing START SUBCHANNEL. Initially, each installed channel path is logically available. Any of bits 8-15 of word 2, when one, indicates that a pathnot-operational condition has been recognized on the corresponding channel path. Each bit of the PNOM corresponds one-for-one, by relative bit position, with a CHPID located in an associated byte of words 4 and 5 of the SClIIB. (Each CHPID contains an 8-bit value which uniquely identifies the physical channel path.) The channel subsystem recognizes a path-not-operational condition when, during an attempted device selection in order to perform a clear, halt, resume, or start function, the device associated with the subchannel appears not operational on a· channel path that is operational for the subchannel. When a path-not-operational condition is recognized, the state of the channel path changes from operational for the subchannel to not operational for the subchannel. A channel path is operational for the subchannel if the associated device appeared operational on that channel path the last tune the channel subsystem attempted device selection in order to perform a clear, halt, resume, or start function. A device appears to be operational on a channel path when the device Path-Not-Operational Mask (PNOM): responds to an attempted device selection. A channel path is not operational for the subchannel if the associated device appeared not operational on that channel path the last time the channel subsystem attempted device selection in order to perform a clear, halt, resume, or start function. Any of bits 8-15 of word 2, when zero, indicates that a path-not-operational condition has not been recognized on the corresponding channel path. Initially, each of the eight possible channel paths associated with each subchannel are considered to be operational, regardless of whether the respective channel paths are installed or available; therefore, unless a _path-not-operational condition is recognized during initial program loading, the PMCW, if stored, contains a PNOM of all zeros if stored prior to executing a CLEAR SUBCHANNEL, HALT SUBCHANNEL, RESUME SUBCHANNEL, or START SUBCHANNEL instruction. Programming Note: The PNOM indicates those channel paths for which a path-not-operational condition has been recognized during the performance of the most recent clear, halt, resume, or start function. That is, the PNOM indicates which of the channel paths associated with the subchannel have made a transition from the operational to the notoperational state for the subchannel during the performance of the most recent clear, halt, resume, or start function. However, the transition of a channel path from the not-operational to the operational state for the subchannel is indicated in the POM. Therefore, the POM must be examined in order to determine whether any of the channel paths that are associated with a designated subchannel are operational for the subchannel. Furthermore, while performing either a start or resume function, the transition of a channel path from the not-operational to the operational state for the subchannel is recognized by the channel subsystem only during the initiation sequence for the frrst command specified by the start function or implied by. the resume function. Therefore, a channel path which is currently not operational for the subchannel can be used by the device associated with the subchannel when reconnecting to the channel subsystem in order to continue command chaining; however, the channel subsystem does not indicate a transition of that channel path from the not-operational to the operational state for the subchannel in the PO M. POM Value and Device State Before Selection Attempt Device State 1 OP NOP OP NOP Value of Specified Bit Subsequent to Selection Attempt POM POM PNOM2 SCSW Nbit e e 1 e e e e e e e 1 13 1 1 ·1 e Explanation: ~ Device state as it appears on the corresponding channel path. 2 Prior to the attempted device selection during the performance of either a start function or a resume function while the subchannel is suspended, the channel subsystem clears all existing path-not-operational conditions, if any, at the designated subchannel. 3 The N bit (bit 15, word e of the SCSW) is indicated to the program and the N condition is cleared at the subchannel when TEST SUBCHANNEL is executed the next time the subchannel is status-pending for other than intermediate status alone provided that it is not also suspended. NOP The device is not operational on the corresponding channel path. OP The device is operational on the corresponding channel path. Figure 15-2. Resulting POM, PNOM, and N-bit Values Subsequent to Selection Attempt Bits 16-23 of word 2 indicate the channel path that was last used for communicating or transferring information between the channel subsystem and the device. Each bit of the LPUM corresponds one-for-one, by relative bit position, with a CHPID located in an associated byte of words 4 and 5 of the SCI-lIB. (Each CHPID contains an 8-bit value which uniquely identifies the physical channel path.) Each bit of the LPUM is stored as zero except for the bit which corresponds to the channel path last used whenever one of the following occurs: Last-Path-Used Mask (LPUM): 1. The first command of a start or resume function is accepted by the device (see the section "Activity Control (AC)" on page 16-13). Chapter 15. Basic I/O Functions 15-5 2. The device and channel subsystem are actively cOnlmunicating when the suspend function is performed for .the channel program in execution. 3. Status has been accepted from the device that is recognized as an interruption condition, or a condition has been recognized that suppresses command chaining (see the section "Interruption Conditions" on page l6-2). 4. An interface-control-check condition has been recognized (see the section "Interface-Control Check" on page 16-32), and no subchannellogout information is currently present in the subchannel. The LPUM field of the PMCW contains the most recent setting. The initial value of the LPUM is zero. Path-Installed Mask (PIM): Bits 24-31 of word 2 indicate which of the channel paths 0-7 to the 1/0 device are physically installed. The PIM indicates the validity of the channel-path identifiers (see below) for those channel paths that are physically installed. Each bit of the PIM corresponds one-for-one, by relative bit position, with a CHPID located in an associated byte of words 4 and 5 of the SCHIB. (Each CHPID contains a value which uniquely identifies the physical channel path.) A PIM bit stored as one indicates that the corresponding channel path is installed. A PIM .bit stored as zero indicates that the correspondmg channel path is not installed. The PIM always reflects the full complement of installed paths to the device regardless of how the system is configured. Th~refore, some of the channel paths indicated in the PIM may not be physically available in that configuration, as indicated by the bit settings in the path-available mask (see below). The initial value of the PIM indicates all the physically installed channel paths to the device. Measurement-Block Index (MLI): Bits 0-15 of word 3 form an index value used by the measurement-block-update facility when the measurement-block-update mode is active (see the section "Set Channel Monitor" on page 14-10 and the subchannel is enabled for the mode (see the section "Measurement Mode Enable (MM)" on page 15-3). When the measurement-block index is used, five zero bits are appended on the right, ~d the result is added to the measurement-block-ongm address designated by SET CHANNEL MONITOR. The calculated address, called the measurementblock address, designates the beginning of a 32-byte 15-6 ESA/370 Principles of Operation storage area where 16 bytes of measurement data are stored (see the section "Measurement Block" on page 17-2). The MBI can contain any value when MODIFY SUBCHANNEL is executed; the initial value is zero. Bits 16-23 of word 3 indicate the last known operational state of the device on the corresponding channel paths. Each bit of the POM corresponds one-for-one, by relative bit position, with a CHPID located in an associated byte of words 4 and 5 of the SCHIB. (Each CHPID contains an 8-bit value which uniquely identifies the physical channel path.) If the associated device appeared operational on a channel path the last time the channel subsystem attempted device selection in order to perform a clear, halt, resume, or start function, then the channel path is operational for the subchannel, and the bit corresponding to the channel path in the POM is one. A device appears to be operational on a channel path when the device responds to an attempted device selection. A channel path is also operational for the subchannel if MODIFY SUBCHANNEL is executed and the bit corresponding to that channel path in the POM is specified as one. Path-Operational Mask (POM): If the associated device appeared not operational on a channel path the last time the channel subsystem attempted device selection in order to perform a clear, halt, resume, or start function, then the channel path is not operational for the subchannel, and the bit corresponding to the channel path in the POM is zero. A channel path is also not operational for the sub channel if MODIFY SUBCHANNEL is executed and the bit corresponding to that channel path in the PO M is specified as zero. If the device associated with the subchannel appears not operational on a channel path that is operational for the subchannel during an attempted device selection in order to perform a clear, halt, resume, or start function, then the channel subsystem recognizes a path-not-operational condition. If an scsw is subsequently stored, then bit 15 of word 1 is one, indicating the path-not-operational condition. When a path-not-operational condition is recognized, the state. of the channel path changes from operational for the subchannel to not operational for the subchannel. When the channel path is not operational for the subchannel , a path-not-operational condition cannot be recognized. Moreover, a channel path that is not operational for the subchannel may be available for selection; if the channel subsystem chooses that channel path while executing a pathmanagement operation, and if during the the attempted device selection, the device appears to be operational again on that channel path, then the state of the channel path changes from not operational for the subchannel to operational for the subchannel. The POM can contain any SUBCHANNEL is executed. value when MODIFY Initially, each of the eight possible channel paths associated with each subchannel are considered to be operational, regardless of whether the respective channel paths are installed or available; therefore, unless a pathnot-operational condition is recognized during initial program loading,the PMCW, if stored, contains a PO M of all ones if stored prior to executing a CLEAR SUBCHANNEL, HALT SUBCHANNEL, RESUME SUBCHANNEL, or START SUBCHANNEL instruction. Path-Available Mask (PAM): Bits 24-31 of word 3 indicate the physical availability of installed channel Each· bit of the PAM corresponds paths. one-for-one, by relative bit position, with a CHPID located in an associated byte of. words 4 and 5 of the SCHIB. (Each CHPID contains an 8-bit value which uniquely identifies the physical channel path.) A PAM bit of one indicates that the corresponding channel path is physically available for use in accessing the device. A PAM bit of zero indicates the channel path is not physically available for use in accessing the device. When a channel path is not physically available, it may, depending upon the model and the extent of failure, be used during performance of the reset-channel-path func.tion. A channel path which is physically available may become not physically available as a result of reconfiguring the system, or this may occur as a result of the performance of the channel-path-reset function. The initial value of the PAM reflects the set of channel paths by which the I/O device is physically accessible at the time of initialization. Note: The. change in the availability of a channel path affects all subchannels having access to that channel path. Whenever the setting of a PAM bit is referred to in conjunction with the availability status of a channel path, for brevity, reference is made in this chapter to a single PAM bit instead of to the respective PAM bits in all of the affected subchannels. Channel-Path Identifiers (CHPIDs): Words 4 and is valid if the corresponding PIM bit is one. Each valid CHPID contains the identifier of a physical channel path to a control unit by which the associated I/O device may be accessed. A unique CHPID is assigned to each physical channel path in the system. CHPID Different devices that are accessible by the same physical channel path have, in their respective subchannels, the same CHPID value. The CHPID value may, however, appear in each subchannel in different locations in the CHPID fields 0-7. Subchannels that share an identical set of channel paths have the same corresponding PIM bits set to ones. The channel-path identifiers (CHPIDS) for these channel paths are the same and occupy the same respective locations in each SCHIB. Reserved: Word 6 of the SCHIB is reserved and is stored as zero by STORE SUBCHANNEL. Bits 0-31 of word 6 of the SCHIB operand must be zeros, when MODIFY SUBCHANNEL is executed; otherwise, an operand exception is recognized. Subchannel-Status Word Words 7-9 contain a copy of the scsw. The format of the scsw is described in the section "Subchannel-Status Word" on page 16-6. The scsw is stored by executing either STORE SUBCHANNEL or TEST SUBCHANNEL (see the sections "Store Subchannel" on page 14-15 and "Test Subchannel" on page 14-17). Model-Dependent Area Words 10-12 contain model-dependent information . Summary of Modif.~ble Fields Figure 15-3 on page 15-8 lists the initial settings for fields in a subchannel whose device-numbervalid bit is set to one, and indicates what modifies the fields. All of the PMCW fields contain meaningful information when STORE SUBCHANNEL is executed and the designated subchannel is idle. Subchannel fields that the channel subsystem does not modify contain valid information whenever STORE SUBCHANNEL is executed, provided that the devicenumber-valid bit is one. The validity of the subchannel fields that are modifiable by the channel subsystem depends on the state of the subchannel at the time STORE SUBCHANNEL is executed. 5 contain eight one-byte channel-path identifiers corresponding to channel paths 0-7 of the PIM. A Chapter 15. Basic I/O Functions 15-7 Subchannel Field Program Modifies by Executing Initial Value 1 Modified by Channel Subsystem2 Interruption parameter Zeros MSCH,SSCH No I/O-interruption subclass code Zeros MSCH No Enabled Zero MSCH No Limit mode Zeros MSCH No Measurement mode Zeros MSCH Yes l Multipath mode Zero MSCH No Timing facil ity Installed value 4 None No Device number valid Installed value 4 None No Device number Installed value 4 None No Logical-path mask Path-instal led-mask value MSCH,SSCH No Path-not-operational, mask Zeros CSCH,SSCH,RSCH5 Yes Last-path-used mask Zeros CSCH Yes None No Path-installed mask Installed value 4 Measurement-block index Zeros MSCH No Path-operational mask Ones CSCH,MSCH,RSCH5 Yes None Yes 6 None No Path-available mask Installed values 4 Channel-path 10 0-7 Installed value 4 6 Subchannel-status word Zeros TSCH Yes Model-dependent area * None * Figure 15-3 (Part 1 of 2). Modification of Subchannel Fields 15-8 ESAj370 Principles of Operation Explanation: These fields are not meaningful if the subchanne1 is not valid. Initializing of a subchanne1 is performed when I/O-system reset occurs. (See the section "I/O-System Reset" in Chapter 17, "1/0 Support Functions.") One or more of the installed-value parameters that are unmodifiab1e by the program may be set when the subchanne1 is idle. In this case, all the program-modifiable fields are set to their initialized values, and the program is notified of such a change by a channel report. (See the section "Channe1-Report Word" in Chapter 17, "I/O Support Functions.") 2 Subchannel fields that are not normally modifiable by the channel subsystem may be modified by external means. When this occurs, the program is notified of the change by a channel report that is made pending at the time of the change. 3 When any of the following error conditions associated with the measurement-b1ock-update mode are detected, the measurement-b1ock-update mode is disabled by the channel subsystem (bit 11, word 1, of the SCHIB zero) in the affected subchannel. The device-connect-time-measurementenable bit (bit 12,word 1 of the SCHIB) is never modified by the channel subsystem. Measurement Measurement Measurement Measurement program check protection check data check key check 4 This information is entered when the channel-subsystem configuration is established. 5 The mask is modified by the resume function only when the subchanne1 is in the suspended state at the time RESUME SUBCHANNEL is executed. 6 The channel subsystem may modify the PAM to reflect changes in the system configuration caused by partitioning or unpartitioning channel paths because of reconfiguration or permanent failure of part of the I/O system. * Model-dependent. Figure 15-3 (Part 2 of 2). Modification of Subchannel Fields Chapter 15. Basic I/O Functions t 5-9 Programming Notes: 2. If, during the performance of a start function, a channel path becomes not physically available because a channel-path failure has been recognized, continued performance of the start function may be precluded. That is, the program mayor may not be notified, and the subchannel may remain in the subchannel-anddevice-active state until cleared by the performance of the clear function. have been set to zeros. The next START SUBCHANNEL causes the channel subsystem to again attempt device selection by choosing a channel path from among all of the channel paths that are available for selection. If device selection is not successful and all channel paths available for selection have again been chosen, deferred condition code 3 is set, but the N bit in the scsw is zero. The POM contains zeros in at least those bit positions that correspond to the channel paths that are available for (See the section "Channel-Path selection. Availability" on page 15-12 for a description of the term "available for selection.") When the N bit in the scsw is zero, the PNOM is also zero. 3. If the same MBI is placed in more than one subchannel by the program, the channelsubsystem-monitoring facility updates the same locations with measurement data relating to more than one subchannel. In this case, the values stored in the measurement data are unpredictable. (See the section "MeasurementBlock Update" on page 17-2.) 6. If the program is to detect path-not-operational conditions, the PNOM should be inspected following the execution of TEST SUBCHANNEL (which results in the setting of condition code zero and the valid storing of the N bit as one) and preceding the performance of another start, resume, halt, or clear function at' the subchannel. 1. System performance may be degraded if the LPM is not used to make channel paths for which a path-not-operational condition has been indicated in the PNOM logically not available. 4. Modification of the I/O configuration (reconfiguration) may be accomplished in various ways depending on the model. If the reconfiguration procedure affects the physical availability of a channel path, then any change in availability can be detected by executing STORE SUBCHANNEL for a subchannel that has access to the channel path and by subsequently examining the PAM bits of the SCHIB. 5. The defmitions of the PNOM, POM, and N bit are such that a path-not-operational condition is reported to the program only the frrst time the condition is detected by the channel subsystem after the corresponding PO M bit is set to one. \ For example, if the POM bit for every channel path available for selection is one and the device appears not operational on all corresponding channel paths while the channel subsystem is attempting to initiate a start function at the device, the channel subsystem makes the subchannel status-pending, with deferred condition code 3 and with the N bit stored as one. The PNOM in the SCHIB indicates the channel path or channel paths ,that appeared not operational, for which the corresponding PO M bits 15-10 ESA/370 Principles of Operation Channel-Path Allegiance The channel subsystem establishes allegiance conditions between subchannels and channel paths. The kind of allegiance established at a subchannel for a channel path or set of channel paths depends upon the state of the subchannel, the device, .and' the information, if any, transferred between the channel subsystem and device. The way in which path management is handled during the performance of a clear, halt, resume, or start function is determined by the kind of allegiance, if any, currently recognized between a subchannel and a channel path. Performing the clear function at a subchannel clears any currently existing allegiance condition in the subchannel for all channel paths. Performing the reset-channel-path function clears all currently existing allegiances for that channel path in all subchannels. When a channel path becomes not physically avail'able, all internal indications of prior allegiance conditions are cleared in all subchannels having access to the designated channel path. Working Allegiance A subchannel has a working allegiance for a channel path when the subchannel becomes deviceactive on that channel path. Once a working allegiance is established, the channel subsystem maintains the working allegiance at the subchannel for the channel path until either the subchannel is no longer device-active or a dedicated allegiance is recognized, whichever occurs earlier. Unless a dedicated allegiance is recognized, a working allegiance for a channel path is extended to the set of channel paths that are available for selection if the device is specified to be operating in multipath mode (that is, the multipath-mode bit is stored as one in the SCHIB). Otherwise, the working allegiance remains only for that channel path over which the start function was initiated. Once a working allegiance is established for a channel path or set of channel paths, the working allegiance is not changed until the subchannel is no longer device-active or until a dedicated allegiance is established. If the subchannel is operating in single-path mode, a working allegiance is maintained only for a single path. While a working allegiance exists at a subchannel, an active allegiance can occur only for a channel path for which the working allegiance is being maintained, unless the device is specified as operating in multipath mode. When the device is specified as operating in multipath mode, an active allegiance may also occur for a channel path that is not available for selection if the presentation of status by the device on that channel path causes an alert interruption condition to be recogriized. A working allegiance is cleared in any subchannel having access to a channel path if the channel path becomes not physically available. Active Allegiance A subchannel has an active allegiance established for a channel path no later than when active communication has been initiated on that channel path with an I/O device. The subchannel can have an active allegiance to only one channel path at a time. While the subchannel has an active allegiance for a channel path, the channel subsystem does not actively communicate with that device on any other channel path. When the channel subsystem accepts a no-longer-busy indication from the device that does not cause an interruption condition, this status does not constitute the initiation of active communication. An active allegiance at a subchannel for a channel path is terminated when the channe1 subsystem is no longer actively communicating with the I/O device on that channel path. A working allegiance can become an active allegiance. Dedicated Allegiance If a channel path is physically available (that is, the corresponding PAM bit is one), a dedicated allegiance may be recognized for that channel path. If a channel path is not physically available, a dedicated allegiance cannot be recognized for the corresponding channel path. The channel subsystem establishes a dedicated allegiance at the subchannel for a channel path when the subchannel becomes status-pending with alert status, and device status containing the unit-check indication is present at the subchannel. A dedicated allegiance is maintained until the sub channel is no longer startpending (unless it becomes suspended) or resumepending following performance of the next start function, clear function, or channel-path-reset function or the next resume function if applicable. If the subchannel becomes suspended, the dedicated allegiance remains until the resume function is initiated and the subchannel is no longer resumepending. Unless a clear or channel-path-reset function is performed, the sub channel establishes a working allegiance when the dedicated allegiance ends. This occurs when the sub channel becomes device-active. While a dedicated allegiance exists at a sub channel , only that channel path is available for selection until the dedicated-allegiance condition , is cleared. A dedicated allegiance can become an active allegiance. While a dedicated allegiance exists, an active allegiance can only occur for the same channel path. A currently existing dedicated allegiance is cleared at any sub channel having access to a channel path when the channel path becomes not physically available or whenever the device appears not operational on the channel path for which the dedicated allegiance exists. Chapter 15. Basic I/O Functions 15-11 Channel-Path Availability When a channel path is not physically available, the channel subsystem does not use the channel path to perform any of the basic I/O functions except, in some cases, the channel-path-reset function and does not respond to any control-unitinitiated requests on that same channel path. If a channel path is not physically available, the condition is indicated by the corresponding pathavailable-mask (PAM) bit being zero when STORE SUBCHANNEL is executed (see the section "PathAvailable Mask (PAM)" on page 15-7). Furthermore, if the channel path is not physically available for the subchannel designated by STORE SUBCHANNEL, then it is not physically available for any subchannel that has a device which is accessible by that channel path. Unless a dedicated allegiance exists at a subchannel for the channel path, a channel path becomes available for selection if it is logically available and physically available (as indicated by the bits in the LPM and PAM corresponding to the channel path being stored as ones when STORE SUBCHANNEL is executed). If a dedicated allegiance exists at a subchannel for the channel path, only that channel path is available for selection, and the setting of the corresponding LPM bit is ignored. If the channel path is currently being used and a dedicated allegiance exists at the subchannel for the channel path, selection of the device is delayed until the channel path is no longer being used. The availability status of the eight logical paths to the associated device described in Figure 15-4 is determined by the hierarchical arrangement of the corresponding bit values contained in the PIM, PAM, and LPM and by existing conditions, if any, recognized by the channel subsystem. Value of Bit Inl ChannelPath PIM PAM LPM Conditi on1 Channel-Path State 9 92 - X Not installed 1 9 - X Not physically available 1 1 93 X Not logically available 1 1 }3 Active Available for selection 4 1 1 1 Inactive Available for selection Explanation: 1 If the channel path is recogniz~d as being used in active comnunication with a device, the channel-path condition is described as active. If the channel path is recognized as not being used in active communication, the condition is described as inactive. 2 3 4 A PAM bit cannot have the value one when the corresponding PIM bit has the value zero. If a dedi cated all egi ance exi sts to the channel path at the subchannel, the state of the bit is ignored, and the channel path is considered to be available for selection. The channel path may appear to be active when a channel-path-terminal condition has been recognized. X Condition is not meaningful. - Bit value is not meaningful. Figure 15-4. Path Condition and Path-Availability Status for PIM, PAM, and LPM Values Control-Unit Type In the sections "Clear Function" on page 15-13, "Halt Function" on page 15-14, and "Start Function and Resume Function" on page 15-17 reference is made to type 1, type 2, and type 3 control units. For a description of these control-unit types, see the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. 15-12 ESAj370 Principles of Operation Clear Function Subsequent to the execution of CLEAR SUBCHANNEL, the channel subsystem perfonns the clear function. Perfonnance of the clear function consists in (1) executing a path-management operation, (2) modifying fields at the subchannel, (3) issuing the clear signal to the associated device, and (4) causing the sub channel to be made statuspending, indicating completion of the clear function. Clear-Function Path Management A path-management operation is executed as part of the clear function in order to examine channelpath cOl.lditions for the associated subchannel and to attempt to choose an available channel path on which the clear signal can be issued to the associated device. Channel-path conditions are examined in the following order: 1. If the channel subsystem is actively communicating or attempting to establish active communication with the device to be signaled, the channel path that is in use is chosen. 2. If the channel subsystem is in the process of accepting a no-longer-busy indication (which will not cause an interruption condition to be recognized) from the device to be signaled, and the associated subchannel has no allegiance to any channel path, the channel path that is in use is chosen. 3. If the associated subchannel has a dedicated allegiance for a channel path, that channel path is chosen. 4. If the associated subchannel has a working allegiance for one or more channel paths, one of those channel paths is chosen. 5. If the associated subchannel has no allegiance for any channel path, if a last-used channel path is indicated, and if that channel path is available for selection, that channel path is chosen. If that channel path is not available for selection, either no channel path is chosen or a channel path is chosen from the set of channel paths, if any, that are available for selection (as though no last-used channel path were indicated). 6. If the associated subchannel has no allegiance for any channel path, if no last-used channel path is indicated, and if there exist one or more channel paths that are available for selection, one of those channel paths is chosen. If none of the channel-path conditions listed above apply, no channel path is chosen. For item 4, for item 5 under the specified conditions, and for item 6, the channel subsystem chooses a channel path from a set of channel paths. In these cases the channel subsystem may attempt to choose a channel path, provided that the following conditions do not apply: 1. A channel-path-terminal condition exists for the channel path. 2. Another subchannel has an active allegiance for the channel path. 3. The device to be signaled is attached to a type-l control unit, and the subchannel for another device attached to the same control unit has an allegiance to the same channel path, unless the allegiance is a working allegiance and primary status has been accepted by that subchannel. 4. The device to be signaled is attached to a type-3 control unit, and the sub channel for another device attached to the same control unit has a dedicated allegiance to the same channel path. Clear-Function Subchannel Modification Path-management-control indications at the subchannel are modified during perfonnance of the clear function. Effectively, this modification occurs after the attempt to choose a channel path, but prior to the attempt to select the device to· issue the clear signal. The path-management-control indications that are modified are as follows: 1. The state of all eight possible channel paths at the subchannel is set to operational for the subchannel. 2. The last-path-used indication is reset to indicate no last-used channel path. 3. Path-not-operational conditions, if any, are reset. Chapter 15. Basic I/O Functions 15-13 Clear-Function Signaling and Completion Subsequent to the attempt to choose a channel path and the modification of the path-managementcontrol fields, the channel subsystem, if conditions allow, attempts to select the device to issue the clear signal. (See the section "Clear Signal" on page 17-5.) Conditions associated with the subchannel and the chosen channel path, if any, affect ( 1) whether an attempt is made to issue the clear signal, and (2) whether the attempt to issue the clear signal is successful. Independent of these conditions, the sub channel is subsequently set statuspending and the performance of the clear function is complete. These conditions and their effect on the clear function are described as follows: No Attempt Is Made to Issue the Clear Signal: The channel subsystem does not attempt to issue the clear signal to the device if any of the following conditions exist: 1. No channel path was chosen. (See the section "Clear-Function Path Management" on page 15-13.) 2. The chosen channel path is no longer available for selection. 3. A channel-path-terminal condition exists for the chosen channel path. 4. The chosen channel path is currently being used to actively communicate with a different device. 5. The device to be signaled is attached to a type-l control unit, and the subchannel for another device attached to the same control unit has an allegiance to the .same channel path, unless the allegiance is a working allegiance and primary status has been accepted by that subchannel. 6. The device to be signaled is attached to a type-3 control unit, and the subchannel for another device attached to the same control unit has a dedicated allegiance to the same channel path. If any of the conditions above exist, the subchannel remfl,ins clear-pending and is set status-pending, and the performance of the clear function is complete. 15-14 ESA/370 Principles of Operation The Attempt to Issue the Clear Signal Is Not Successful: When the channel subsystem attempts to issue the clear signal to the device, the attempt may not be successful because of the following conditions; 1. The control unit or device signals a busy condi- tion when the channel subsystem attempts to select the device to issue the clear signal. 2. A path-not-operational condition is recognized when the channel subsystem attempts to select the device to issue the clear signal. 3. An error condition is encountered when the channel subsystem attempts to issue the clear signal. If any of the conditions above exist and the channel subsystem either determines that the attempt to issue the clear signal was not successful or cannot determine whether the attempt was successful, the sub channel remains clear-pending and is set statuspending, and the perfonnance of the clear function is complete. The Attempt to Issue the Clear Signal Is Successful: When the channel sub~ystem determines that the attempt to issue the clear signal was successful, the subchannel is no longer clear-pending and is set status-pending, and the petformance of the clear function is complete. When the subchannel becomes status-pending, the I/O operation, if any, with the associated device has been terminated. Programming Note: Subsequent to the performance of the clear function, any nonzero status, except control-unit end alone, that is presented to the channel subsystem by the device is passed to the program as unsolicited alert status. Unsolicited status consisting of control-unit end alone or zero status is not presented to the program. Halt Function Subsequent to the execution of HALT the channel subsystem performs the halt function. Performance of the halt function consists in (1) executing a path-management operation, (2) issuing the halt signal to the associated device, and (3) causing the subchannel to be made status-pending, indicating completion of the halt function. SUBCHANNEL, Halt-Function Path Management 1. A channel-path-terminal condition exists for A 'path-management operation is executed as part of the halt function to examine channel-path conditions for the associated subchannel and to attempt to choose a channel path on which the halt signal can be issued to the associated device. 2. Another subchannel has an active allegiance for the channel path. Channel-path conditions are examined in the following order: . 1. If the channel subsystem is actively communicating or attempting to establish active communication with the device to be signaled, the channel path that is in use is chosen. 2. If the channel subsystem is in the process of accepting a no-longer-busy indication (which will not cause an interruption condition to be recognized) from the device to be signaled, and the associated subchannel has no allegiance to any channel path, the channel path that is in use is chosen. 3. If the associated subchannel has a dedicated allegiance for a channel path, that channel path is chosen. 4. If the associated subchannel has a working allegiance for one or more channel paths, one of those channel paths is chosen. 5. If the associated subchannel has no allegiance for any channel path, if a last-used channel path is indicated, and if that channel path is available for selection, that channel path is chosen. If that channel path is not available for selection, either no channel path is chosen or a channel path is chosen from the set of channel paths, if any, that are available for selection (as though no last-used channel path were indicated). 6. If the associated subchannel has no allegiance for any channel path, if no last-used channel path is indicated, and if there exist one or more channel paths that are available for selection, one of those channel paths is chosen. If none of the channel-path conditions listed above apply, no channel path is chosen. For item 4, for item 5 under the specified conditions, and for item 6 above, the channel subsystem chooses a channel path from a set of channel paths. In these cases the channel subsystem may attempt to choose a channel path for which the following / conditions do not apply: the channel path. 3. The device to be signaled is attached to a type-l control unit, and the subchannel for another device attached to the same control unit has an allegiance to the same channel path, unless the allegiance is a working allegiance and primary status has been accepted by that sub channel. 4. The device to be signaled is attached to a type-3 control unit, and the subchannel for another device attached to the same control unit has a dedicated allegiance to the same channel path. Halt-Function Signaling and Completion Subsequent to the attempt to choose a channel path, the channel subsystem, if conditions allow, . attempts to select the device to issue the halt signal. (See the section "Halt Signal" on page 17-5.) Conditions associated with thesubchannel and the chosen channel path, if any, affect (1) whether an attempt is made to issue the halt signal, (2) whether the attempt to issue the halt signal is successful, and (3) whether the subchannel is made status-pending to complete the halt function. These conditions and their effect on the halt function are described as follows: No Attempt Is Made to Issue the Halt Signal: The channel subsystem does not attempt to issue the halt signal to the device if any of the following conditions exist: 1. No channel path was chosen. (See the section "Halt-Function Path Management.") 2. The chosen channel path is no longer available for selection. 3. A channel-path-terminal condition exists for the chosen channel path. 4. The. associated sub channel is status-pending with other than intermediate status alone. 5. The device to be signaled is attached to a type-! control unit, and the sub channel for another device attached to the same control unit has an allegiance to the same channel path, unless the allegiance is a working alle- Chapter 15. Basic I/O Functions 15-15 giance and primary status has been accepted by that subchannel. 6. The device to be signaled is attached to a type-3 control unit, and the subchannel for another device attached to the same control unit has a dedicated allegiance to the same channel path. If the conditions described in items 3 on page 15-15, 5 on page 15-15, or 6 above exist, the associated subchannel remains halt-pending until those conditions no longer exist. When the conditions no longer exist (for the channel-path-terminal condition, when the condition no longer exists as a result of executing RESET CHANNEL PATH) the channel subsystem attempts to issue the. halt signal to the device. If any of the remaining conditions above exist, the subchannel remains halt-pending, is set statuspending, and the halt function is complete. The Attempt to Issue the Halt Signal Is Not Successful: When the channel subsystem attempts to issue the halt· signal to the device, the attempt may not be successful because of the following conditions: 1. The control unit or device signals a busy condi- tion when the channel subsystem attempts to select the device to issue the halt signal. 2. A path-not-operational condition is recognized when the channel subsystem attempts to select the device to issue the halt signal. 3. An error condition is encountered when the channel subsystem attempts to issue the halt signal. If the control unit or device signals a busy condition (item 1), the subchannel remains halt-pending until the internal indication. of busy is reset. When this event occurs, the channel subsystem again attempts to issue the halt signal to the device. If any of the remaining conditions above exists and the channel subsystem either determines that the attempt to issue the halt signal was not successful or cannot determine whether the attempt was successful, then the subchannel remains halt-pending and is set status~pending, and the halt function is complete. The Attempt to Issue the Halt Signal Is Successful: When the channel subsystem determines that the attempt to issue the halt signal was suc- 15-16 ESA/370 Principles of Operation cessful and ending status, if appropriate, has been received at the subchannel, the subchannel is no longer halt-pending and is set status-pending, and the halt function is complete. When the subchannel becomes status-pending, the 1/0 operation, if any, with the associated device has been terminated. The conditions that affect the receipt of ending status at the subchannel, and the effect of the halt signal at the device are described in the following discussion. When the subchannel is subchannel-and-deviceactive or only device-active during the performance of the halt function, the state continues until the sub channel is Inade status-pending because (1) the device has provided ending status or (2) the channel subsystem has determined that ending status is unavailable. When the subchannel is idle, start-pending, start-pending and resume-pending, suspended, or suspended and resume-pending, or when the halt signal is issued during command chaining after the receipt of device end but before the next command is transferred to the device, no operation is in progress at the device, and therefore no status is generated by the device as a result of receiving the halt signal. When the subchannel is neither sub channel active nor status-pending with intermediate status, and no errors are detected during the attempt to issue the halt signal to the device, an interruption condition indicating statuspending alone is generated after the halt signal is issued. The effect of the halt signal at the device depends partially on the type of device and its state. The effect of the halt signal on a device that is not active or that is executing a mechanical operation in which data is not transferred across the channel path, such as rewinding tape or positioning a diskaccess mechanism, depends upon the control-unit or device model. If the device is executing a type of operation that is unpredictable in duration or in which data is transferred across the channel path, the control unit interprets the signal as one to terminate the operation. Pending status conditions at the device are not reset. When the control unit recognizes the halt signal, it immediately ceases all communication with the channel subsystem until it has reached the normal ending point. The control unit then requests selection by the channel subsystem to present any generated status. If the sub channel is involved in the data-transfer portion of an 1/0 operation, data transfer is terminated during the performance of the halt function, and the device is logically disconnected from the channel path. If the halt function is addressed to a subchannel executing a chain of 1/0 operations and the device has already provided channel end for the current 1/0 operation, the channel subsystem causes the device to be disconnected and command chaining or command retry to be suppressed. If the subchannel is executing a chain of 1/0 operations with the device and the halt signal is issued during command chaining at a point after the receipt of device end for the previous 1/0 operation but before the next command is transferred to the device, the subchannel is made status-pending with primary and secondary status immediately after the halt signal is issued. The device-status field of the scsw contains zeros in this case. If the halt function is addressed to a subchannel that is startpending and the halt-pending condition is recognized before initiation of the start function, initiation of the start function is not attempted, and the subchannel becomes status-pending after the device has been signaled. When the subchannel is not executing an 1/0 operation with the associated device, the device is selected, and an attempt is made to issue the halt signal as the device responds. If the subchannel is in the device-active state, the subchannel becomes status-pending, only after receiving the device-end status frOln the halted device. If the sub channel is neither subchannel-and-device-active nor deviceactive, the subchannel becomes status-pending immediately after selecting the device and issuing the halt signal. The scsw for the latter case has the status-pending bit set to one (see the section "Status-Pending (Bit 31)" on page 16-18). The second interruption condition occurs if device-end status was not presented with the channel-end interruption condition. In this situation, the subchannel-key, command-address, and count fields of the associated scsw are not meaningful. When HALT SUBCHANNEL terminates an I/O operation, the method of termination differs from that used upon exhaustion of count or upon detection of programming errors to the extent that termination by HALT SUBCHANNEL is not contingent on the receipt of a service request from the associated device. Programming Notes: 1. When, after an operation is terminated by HALT SUBCHANNEL, the subchannel is statuspending with primary, primary and secondary, or secondary status, the extent of data transferred as described by the count field is unpredictable. 2. When the path that is chosen by the pathmanagement operation has a channel-pathterminal condition associated with it, the halt function remains pending until the condition no longer exists. Until the condition is cleared, the associated subchannel cannot be used to execute I/O operations, even if other channel paths become available for selection. CLEAR SUBCHANNEL can be executed to terminate the halt-pending condition and make the subchannel usable. The termination of an I/O operation by performing the halt function may result in two distinct interruption conditions. Start Function and Resume Function The frrst interruption condition occurs when the device generates the channel-end condition. The channel subsystem handles this condition as it would any other interruption condition from the device, except that the command address in the associated scsw designates the point at which the I/O operation is terminated, and the subchannelstatus bits may reflect unusual conditions that were detected. If the halt signal was issued before all data designated for the operation had been transferred, incorrect length is indicated, subject to the control of the sLI flag in the current ccw. The value in the count field of the associated scsw is unpredictable. Subsequent to execution of START SUBCHANNEL and RESUME SUBCHANNEL, the channel subsystem performs the start and resume functions, respectively, to initiate an I/O operation with the associated device. Performance of a start or resume function consists in: (1) executing a path-management operation, (2) executing an I/O operation or chain of I/O operations with the associated device, and (3) causing the subchannel to be made statuspending, indicating completion of the performance of the start function. (Completion of a start function is described in Chapter 16, "I/O Interruptions" on page 16-1.) The start function initiates the execution of a channel program that is designated in the ORB, which in turn is designated as the operand of START SUBCHANNEL, in contrast Chapter 15. Basic I/O Functions 15-17 to the resume function which initiates the execution of a suspended channel program, if any, beginning at the ccw that caused suspension; otherwise, the resume function is performed as if it were a start function (see the section "Resume-Pending (Bit 20)" on page 16-13). Start-Function and Path Management Resume-Functio~ A path-management operation is executed by the channel subsystem during the performance of either a start or resume function to choose an available channel path that can be used for device selection to initiate an 1/0 operation with that device. The actions taken are as follows: 1. If the subchannel is currently start-pending and device-active, the start function remains pending at the subchannel until the secondary status for the previous start function has been accepted from the associated device and the subchannel is made start-pending alone. When the status is accepted and it does not describe an alert interruption condition, the subchannel is not made status-pending, and the performance of the pending start function is subsequently initiated. If the status describes an alert interruption condition, the subchannel becomes status-pending with secondary and alert status, the pending start function is not initiated, deferred condition code 1 is set, and the start-pending bit remains one. If the subchannel is currently start-pending alone, the performance of the start function is initiated as described below. 2. If a dedicated allegiance exists at the subchannel for a channel path, the channel subsystem chooses that path for device selection. If a busy condition is encountered while attempting to select the device and a dedicated allegiance exists at the subchannel, the start function remains pending until the internal indication of busy is reset for that channel path. When the internal indication of busy is reset, the performance of the pending start function is initiated on that channel path. with other devices, or, alternatively, if the ch~el subsystem has encountered either a control-unit-busy or device-busy condition on one ortnore of those channel paths, or a combination of those conditions on one or more of those channel paths, the start function remains pending at the subchannel until a channel path, control unit, or device, as appropriate, becomes available. S. If (1) the start function is to be initiated on a channel path with a device attached to a type-l control unit and (2) no other device is attached to the same control unit whose subchannel has either a dedicated allegiance to the same channel path or a working allegiance to the same channel path where primary status has not been received for that subchannel, then that channel path is chosen if it is available for selection; otherwise, that channel path is not chosen. If, however, another channel path to the device is available for selection and if no allegiances exist as described above, that channel path is chosen. If no other channel paths are available for selection, the start or resume function, as appropriate, remains pending until a channel path becomes available. 6. If the device is attached to a type-3 control unit and if at least one other device is attached to the same control unit whose sub channel has a dedicated allegiance to the same channel path, another channel path that is available for selection may be chosen, or the start function remains pending until the dedicated allegiance for the other device is cleared. 7. If a channel path has been chosen and a busy indication is received during device selection to initiate execution of the fITst command of a pending channel program, the channel path over which the busy indication is received is not used again for that device or control unit (depending on the device-busy or control-unitbusy indication received) until the internal indication of busy is reset. 3. If no channel paths are available for selection and no dedicated allegiance exists in the subchannel for a channel path, a channel path is not chosen. 8. If, during an attempt to select the device in order to initiate execution of the fITst command specified for the start or implied for the resume function (as described in action 7), the channel subsystem receives a busy indication, it performs one of the following actions: 4. If all channel paths that are available for selection have been tried and one or more of them are being used to actively communicate a. If the device is specified to be operating in multipath mode and the busy indication received is device busy, then the start or 15-18 ESA/370 Principles of Operation resume function remains pending until the internal indication of busy is reset. (See the section "Multipath Mode (D)" on page 15-3.) b. If the device is specified to be operating in multipath mode and the busy indication received is control unit busy, or if the device is specified to be operating in singlepath mode, the channel subsystem attempts selection of the device by choosing an alternate channel path that is available for selection and continues the path-management operation until either the start or resume function is initiated or selection of the device has been attempted on all channel paths that are available for selection. If the start or resume function has not been initiated by the channel subsystem after all channel paths available for selection have been chosen, the start or resume function remains pending until the internal indication of busy is reset. c. If the subchannel has a dedicated allegiance, then action 2 on page 15-18 applies. 9. When, during the selection attempt to transfer the ftrst command, the device appears not operational and the corresponding channel path is operational for the subchannel, a path-notoperational condition is recognized and the state of the channel path changes at the subchannel from operational for the subchannel to not operational for the subchannel (see the "Path- Not-Operational Mask section (PNOM)" on page 15-4). The path-notoperational conditions at the subchannel, if any, are preserved until the subchannel next becomes clear-pending, start-pending, or resume-pending (if the sub channel was suspended), at which time the path-notoperational conditions are cleared. If, however, the corresponding channel path is not operational for the subchannel, a path-notoperational condition is not recognized. When the device appears not operational during the selection attempt to transfer the frrst command on a channel path that is available for selection, one of the following actions occurs: a. If a dedicated allegiance exists for that channel path, then it is the only channel path that is available for selection; therefore, further attempts to initiate the start or resume function are abandoned, and an interruption condition is recognized. b. If no dedicated allegiance exists and there are alternate channel paths available for selection which have not been tried, one of those channel paths is chosen to attempt device selection and transfer the frrst command. c. If no dedicated allegiance exists, no alternate channel paths are available for selection which have not been tried, and the device has appeared operational on at least one of the channel paths that were tried, the start or resume function remains pending at the subchannel until either a channel path, a control unit, or the device, as appropriate, becomes available. d. If no dedicated allegiance exists, no alternate channel paths are available for selection which have not been tried, and the device has appeared not operational on all channel paths that were tried, further attempts to initiate the start or resume function are abandoned, and an interruption condition is recognized. 10. When the subchannel is active and an I/O operation is to be initiated with a device, all device selections occur according to the LPUM indication if the multipath mode is not specified at the subchannel. For example, if command chaining is specified, the channel subsystem transfers the frrst and all subsequent commands describing a chain of I/O operations over the same channel path. Execution of 110 Operations After a channel path is chosen, the channel subsystem, if conditions allow, initiates execution of an I/O operation with the associated device. Execution of additional I/O operations may follow initiation and execution of the frrst I/O operation. The channel subsystem can execute seven commands: write, read, read backward, control, sense, sense ID, and transfer in channel. Each command, except transfer in channel, initiates a corresponding I/O operation. Except for periods while channelprogram execution is suspended at the subchannel (see the section "Suspension of Channel-Program Execution" on page 15-32), the subchannel is active from the acceptance of the frrst command until the primary interruption condition is recognized at the subchannel. If the primary interruption condition is recognized before the acceptance of the first command, the subchannel does not Chapter 15. Basic I/O Functions 15-19 become active. Normally, the primary interruption condition is caused by the channel-end signal or, in the case of command chaining, the channel-end signal for the last ccw of the chain. (See the section "Primary Interruption Condition" on page 16-4.) The device is active until the secondary interruption condition is recognized at the subchannel. Normally, the secondary interruption condition is caused by the device-end signal or, in the case of command chaining, the device-end signal for the last ccw of the chain. (See the section "Secondary Interruption Condition" on page 16-4.) An I/O operation or chain of operations is normally executed by the channel subsystem and the device operating in single-path mode. In single-path mode, all transfers of commands, data, and status for the I/O operation or chain of I/O operations occur on the channel path over which the frrst command was transferred to the device. Programming Note: I/O When the device has the dynamic-reconnection feature ins~alled, an I/O operation or chain of I/O operations may be executed in multipath mode; to operate in multipath mode, MODIFY SUBCHANNEL must have been previously executed for the subchannel with bit 13 of word 1 of the SCHIB specified as one. (See the section "Multipath Mode (D)" on page 15-3.) In addition, the device must be set up for multipath mode by execution of certain model-dependent commands appropriate to that type of device. The general procedures for handling multipath-mode operations are as follows: 1. Setup a. A set-multipath-mode type of command must be successfully executed by the device on each channel path that is to be a member of the multipath group being set up; otherwise, the multipath mode of operation may give unpredictable results at the subchannel.· If, for any reason, one or more physically available channel paths to the device are not included in the multipath group, these channel paths must not be available for selection while the subchannel is operating in multipath mode. A channel path can be made not available for selection by having the corresponding LPM bit set to zero either in the SCHIB prior to executing STORE SUBCHANNEL or in the 15-20 ESA/370 Principles of Operation ORB prior CHANNEL. to executing START SUB- b. When a set-multipath-mode type of command is transferred to a device, only a single channel path must be logically available in order to avoid alternate channelpath selection for the performance of that start function; otherwise, device-busy conditions may be detected by the channel subsystem on more than one channel path, which may cause unpredictable results for subsequent multipath-mode operations. This type of setup procedure should be used whenever the membership of a multipath group is changed. 2. Leaving Multipath Mode To leave mUltipath mode and continue processing in single-path mode, either of the following two procedures may be used: a. A disband-multipath-mode type of command may be executed for any channel This path of the multipath group. command must be followed either by (1) the execution of MODIFY SUBCHANNEL with bit 13 of word 1 of the SCH IB specified as zero, or by (2) the specification of only a single channel path as logically available in the LPM. A start function must not be performed at a subchannel operating in multipath mode with multiple channel paths available for selection while the device is operating in single-path mode; otherwise, unpredictable results may occur at the subchannel for that function or subsequent start functions. b. A resign-multipath-mode type of command is executed on each channel path of the multipath group (the reverse of the setup described in item 1). This command must be followed by either (1) the execution of MODIFY SUBCHANNEL with bit 13 of word 1 of the SCHIB specified as zero, or (2) the specification of only a single channel path as logically available in the LPM. No start function may be performed at a subchannel operating in multipath mode with multiple channel paths available for selection while the device is operating in single-path mode; otherwise, unpredictable results may occur at the subchannel for that or subsequent start functions. request is cleared by execution of TEST PENDING INTERRUPTION. Blocking of Data Data recorded by an I/O device is divided into blocks. The length of a block depends on the device; for example, a block can be a card, a line of printing, or the infonnation recorded between two consecutive gaps on magnetic tape. The maximum amount of infonnation that can be transferred in one I/O operation is one block. An I/O operation is terminated when the associated main-storage area is exhausted or the end of the block is reached, whichever occurs first. For some operations, such as writing on a magnetic-tape unit or at an inquiry station, blocks are not defmed, and the amount of infonnation transferred is controlled only by the program. Operation-Request Block The operation-request block (ORB) is the operand of START SUBCHANNEL. The ORB specifies the parameters to be used in controlling that particular start function. These parameters include the interruption parameter, the subchannel key, the address of the frrst CCW, operation-control bits, and a specification of the logical availability of channel paths. The contents of the ORB are placed at the designated subchannel during the execution of START SUBCHANNEL, prior to the setting of condition code O. If the execution of START SUBCHANNEL results in the setting of a nonzero condition code, the contents of the ORB have not been placed at the designated subchannel. The two rightmost bits of the ORB address must be zeros, placing the ORB on a word boundary; otherwise, a specification exception is recognized. The fonnat of the ORB is as follows: ----------------------, o ILl Key 2 0000000 Channel-Program Address o 31 The fields in the ORB are defmed as follows: Interruption Parameter: Bits 0-31 of word 0 are preserved unmodified in the subchannel until replaced by a subsequent START SUBCHANNEL or MODIFY SUBCHANNEL instruction. These bits are placed in word I of the interruption code when an I/O interruption occurs and when an interruption Bits 0-3 of word 1 fonn the subchannel key for all fetching of ccws, IDAWS, and output data and for the storing of input data associated with the start function initiated by START SUBCHANNEL. This key is matched with a storage key during these storage references. For details, see the section "Key-Controlled Protection" in Chapter 3, "Storage." Subchannel Key: Suspend Control (S): Bit 4 of word I controls the perfonnance of the suspend function for the channel program identified in the ORB. The setting of the S bit applies to all CCws of the channel progran1 designated by the ORB (see the section "Commands" on page 15-34). When bit 4 is one, suspend control is specified, and channel-program suspension occurs when a valid suspend flag is detected in a ccw. If bit 4 is zero, suspend control is not specified, and the presence of the suspend flag in any ccw of the channel program causes a program-check condition to be recognized. Reserved: Bits 5-7 of word I are reserved for future use and must be zeros; otherwise, either an operand exception or a program-check condition is recognized. Format Control (F): Bit 8 of word I specifies the fonnat of the channel-command words (ccws) which make up the channel program designated by the channel-program-address field. If bit 8 of word 1 is zero, fonnat-O CCws are specified. If bit 8 is one, fonnat-l ccws are specified. (See the section "Channel-Command Word" on page 15-23, for the defmition of the ccw fonnats). Prefetch Control (P): Bit 9 of word 1 specifies whether or not unlimited prefetching of cCWs is allowed for the channel program. If this bit is zero, no prefetching is allowed, except in the case of data chaining on output, where the prefetching of one ccw describing a data area is allowed. If tIns bit is one, unlimited prefetching is allowed. Initial-Status-Interruption Control (I): Bit 10 of word 1 specifies whether or not the channel subsystem must verify to the program that the device has accepted the frrst command associated with a start or resume function. If the I bit is specified as one in the ORB, then when initial status is received and the subchannel becomes active, indicating that the frrst command has been accepted for this start Chapter 15. Basic I/O Functions 15-21 or resume function, the z bit (see the section "Zero Condition Code (Z)" on page 16-11) is set to one at this subchannel, and the subchannel becomes status-pending with intennediate status. If the sub channel does not become active -- for example, when the device signals channel end immediately upon receiving the frrst command, command chaining is not specified in the ccw, and command retry is not signaled -- the commandaccepted condition (z bit set to one) is not generated; instead, the subchannel becomes statuspending with primary status; intennediate status may also be indicated in this case when the command is accepted if the frrst ccw contained the PCI flag. Address-limit-Checking Control (A): Bit 11 of word 1 specifies whether or not address-limit checking is specified for the channel program. If this bit is zero, no address-limit checking is perfonned for the execution of the channel program, independent of the setting of the limit-mode bits in the subcbannel (see the section "Limit Mode (M)" on page 15-2). If this bit is one, address-limit checking is allowed for the channel program, subject to the setting of the limit-mode bits in the subchannel. Suppress-Suspended-Interruption Control (U): Bit 12 of word 1, when one, specifies that the channel subsystem is to suppress the generation of an intermediate interruption condition due to suspension if the subchannel becomes suspended. When bit 12 is zero, the channel subsystem generates an intermediate interruption condition whenever the subchannel becomes suspended during execution of the channel program. Reserved: Bits 13-15 of word 1 are reserved for future use and must be zeros; otherwise, an operand exception or a program-check condition is recognized. logical-Path Mask (lPM): Bits 16-23 of word 1 are preserved unmodified in the subchannel and specify to the channel subsystem which of the logical paths. 0-7 are to be considered logically available, as viewed by the program. A bit setting of one means that the corresponding channel path is logically available; a zero specifies that the corresponding channel path is logically not available. If 15-22 ESA/370 Principles of Operation a channel path is specified by the program as being logically not available, the channel subsystem does not use that channel path to perform clear, halt, resume, or start functions when requested by the program, except when a dedicated-allegiance condition exists for that channel path. If a dedicatedallegiance condition exists, the setting of the LPM is ignored, and a resume, start, halt, or clear function is perfonned by using the channel path having the dedicated -allegiance. Incorrect-length-Suppression Mode (l): When the incorrect-length-indication-suppression facility is installed and bit 8 of word 1 is one, then bit 24 of word 1, when one, specifies the incorrect-1engthsuppression mode. If the subchannel is in this mode when an immediate operation occurs (that is, a device signals the channel-end condition during the initiation sequence) and the current ccw contains a nonzero value in bits 16-31, indication of an incorrect-length condition is suppressed. When the incorrect-length-indication-suppression facility is installed and bit 8 of word 1 is one, then bit 24 of word 1, when zero, specifies the incorrectlength-indication mode. If the subchannel is in this mode when an immediate operation occurs (that is, a device signals the channel-end condition during the initiation sequence) and the current ccw contains a nonzero value in bits 16-31, indication of an incorrect-length condition is recognized. Command chaining is suppressed unless the SLI flag in the ccw is one and the chain-data flag is zero. When the incorrect-Iength-indication-suppression facility is installed and bit 8 of word 1 is zero, the value of bit 24 is ignored by the channel subsystem, and the subchannel is in the incorrect-Iengthsuppression mode. When the incorrect-length-indication-suppression facility is not installed and bit 24 of word 1 is zero, the subchannel is in the incorrect-Iengthsuppression mode. When the incorrect-Iengthindication-suppression facility is not installed, bit 24 must be zero; otherwise, an operand exception is recognized. Reserved: Bits 25-31 of word 1 are reserved for future use and must be set to zeros; otherwise, an operand exception or a program-check condition is recognized. Bits 0-31 of word 2 designate the location of the frrst ccw in absolute storage. Bit 0 of word 2 must be zero; otherwise, an operand exception or a program-check condition is recognized. If format-O ccws have been specified in bit 8 of word 1, then bits 1-7 must also be zeros; otherwise, a program-check condition is recognized. Channel·Program Address: The three rightmost bits of the channel-program address must be zeros, designating the ccw on a doubleword boundary; otherwise, a program-check condition is recognized. If the channel-program address designates a location protected against fetching or designates a location outside the storage of the particular installation, the start function is not initiated at the device. In this situation, the subchannel becomes status-pending with primary, secondary, and alert status. Programming Notes: I. Bit positions of the 0 RB which presently are specified to contain zeros may in the future be assigned for the control of new functions. 2. The interruption parameter may contain any information, but ordinarily the information is of significance to the program handling the I/O interruption. the I/O operation (see the section "Data Chaining" on page 15-28). When chaining is not specified, a ccw is no longer current after TEST SUBCHANNEL clears the start-function bit in the subchannel. The location of the frrst ccw of the channel program is designated in the ORB that is the operand of START SUBCHANNEL. The frrst ccw is fetched subsequent to the execution of the instruction. The format of the ccws fetched by the channel subsystem is specified by bit 8 of word I of the ORB. Each additional ccw in the channel program is obtained when the ccw is needed. Fetching of the ccws by the channel subsystem does not affect those locations in main storage. ccws have either of two different formats, format 0 or format 1. The two formats do not differ in the information contained in the ccw but only in the arrangement of the fields within the ccw. The formats are defmed as follows: Format a a The channel-command word (ccw) specifies the command to be executed and, for commands initiating certain I/O operations, it designates the storage area associated with the operation, the action to be taken whenever transfer to or from the area is completed' and other options. I 31 8 Flags 32 Channel-Command Word Data Address Icmd cOdel lallllllllli 39 Count 63 48 Format 1 Icmd cOdel a lal Flags lal Count 15 Data Address 32 A channel program consists of one or more ccws that are logically linked such that they are fetched by the channel subsystem and executed in the sequence specified by the CPU program. Contiguous ccws are linked by the use of the chain-data or chain-command flags, and noncontiguous ccws may be linked by a ccw specifying the transfer-inchannel command. As each ccw is executed, it is recognized as the current ccw. A ccw becomes current (I) when it is the frrst ccw of a channel program and has been fetched, (2) when, during command chaining, the new ccw is logically fetched, or (3) when, during data chaining, the new ccw takes over control of 31 63 Format-O CCws can be located anywhere in the frrst 16,777,216 bytes of main storage. Format-I ccws can be located anywhere in main storage. Bit 39 (format 0) or bit IS (format 1) of every ccw other than a format-O ccw specifying transfer in channel must be zero. Additionally, if indirect dat"a address~g is specified, bits 30-31 (format 0) or bits 62-63 (format 1) of the ccw must be zeros, designating a word boundary, and bit 0 of the frrst entry of the indirect-data-address list must be zero. Otherwise, a program-check condition may be generChapter 15. Basic I/O Functions 15-23 ated (see the section "CCW Indirect Data Addressing" on page 15-31). Detection of this condition during data chaining causes the I/O device to be signaled to conclude the operation. When the absence of these zeros is detected during command chaining or subsequent to the execution of START SUBCHANNEL, the new operation is not initiated, and an interruption condition is generated. The contents of bit positions 40-47 of a fonnat-O ccw are ignored. Program-Controlled-Interruption (PCI) Flag: Bit 36 (fonnat 0) or bit 12 (format 1), when one, causes the channel subsystem to generate an intermediate interruption condition when the ccw takes control of the I/O operation. When the PCI flag bit is zero, nonnal operation takes place. Indirect-Data-Address (IDA) Flag: Bit 37 (format 0) or bit 13 (format 1), when one, specifies indirect data addressing. Bit 38. (format 0) or bit 14 (fonnat 1), when one, specifies suspension of channel-program execution. When valid, it causes channel-program execution to be suspended prior to execution of the ccw containing the S flag. The S flag is valid when bit 4, word 1 of the associated ORB is one. Suspend (S) Flag: The fields in the ccws are defmed as follows: Command Code: Bits 0-7 (both fonnats) specify the operation to be executed. Bits 8-31 (fonnat 0) or bits 33-63 (fonnat 1) designate a location in absolute storage. It is the frrst location referred to in the area designated by the ccw. If a byte count of zero is specified' this field is not checked. Data Address: Bit· 32 (fonnat 0) or bit 8 (fonnat 1), when one, specifies chaining of data. It causes the storage area designated by the next ccw to be used with the current I/O operation. When the CD flag is one in a ccw, the chain-command and suppress-length-indication flags (see below) are ignored. Chain-Data (CD) Flag: Bit 33 (fonnat 0) or bit 9 (fonnat 1), when one, and when the CD flag and S flag are both zeros, specifies chaining of commands. It causes the operation specified by the command code in the next ccw to be initiated on nonnal cOlllpletion of the current operation. Chain-Command (CC) Flag: Bit 34 (fonnat 0) or bit 10 (fonnat 1) controls whether an incorrect-length condition is to be indicated to the program. When this bit is one and the CD flag is zero, the incorrect-length indication is suppressed. When both the cc and SLI flags are ones, and the CD flag is zero, command chaining takes place, regardless of the presence of an incorrect-length condition. This bit should be specified in all ccws where suppression of the incorrect-length indication is desired. Count: Bits 48-63 (fonnat 0) or bits 16-31 (fonnat 1) specify the number of bytes in the storage area designated by the ccw. Programming Note: Bit 39 of a fonnat-O CCW or bit 15 of a fonnat-l ccw, which presently must be zero, may in the future be assigned for the control of new functions. It is recommended, therefore, that this bit position not be set to one for the purpose of obtaining an intentional program-check indication. Command Code The command code, bit positions 0-7 of the ccw, specifies to the channel subsystem and the I/O device the operation to be executed. A detailed description of each command appears in the section "Commands" on page 15-34. Suppress-length-Indication (Sll) Flag: The two rightmost bits or, when these bits are zeros, the four rightmost bits of the command code identify the operation to the channel subsystem. The channel subsystem distinguishes among the following four operations: Output forward (write, control) Input forward (read, sense, sense ID) Input backward (read backward) Branching (transfer in channel) The channel subsystem ignores the leftmost bits of Skip (SKIP) Flag: Bit 35 (fonnat 0) or bit 11 (fonnat 1), when one, specifies the suppression of transfer of information to ~torage during a read, read-backward, sense ID, or sense operation. 15-24 ESAj370 Principles of Operation the command code, except in a fonnat-l ccw specifying transfer in channel. In this situation, all bits of the command code are decoded by the channel subsystem. Commands that initiate 1/0 operations (write, read, read backward, control, sense, and sense ID) cause all eight bits of the command code to be transferred to the control unit. In these command codes, the leftmost bit positions contain modifier bits. The modifier bits specify to the device how the command is to be executed. They may, for example, cause the device to compare data received during a write operation with data previously recorded, and they may specify such conditions as recording density and parity. For the control command, the modifier bits may contain the order code specifying the control function to be executed. The meaning of the modifier bits depends on the type of 1/0 device and is specified in the System Library publication for the device. The command-code assignment is listed in Figure 15-5. The symbol x indicates that the bit position is ignored; m identifies a modifier bit. Code xxxx mmmm mmmm mmmm mmmm mmmm 1 lIe xxxx a a aa mmmm Designation of Storage Area The main-storage area associated with an 1/0 operation is defmed by one or more ccws. A ccw defmes an area by designating the address of the frrst byte to be transferred and the number of consecutive bytes contained in the area. The address of the location which designates the frrst byte of data is specified in the data-address field of the ccw. The number of bytes contained in the storage area is specified in the count field. In write, read, control, sense, and sense-ID operations, storage locations are used in ascending order of addresses. As information is transferred to or from main storage, the address from the address field is incremented, and the count from the count field is decremented. The read-backward operation places data in storage in a descending order of addresses, and both the count and the address are decremented. When the count reaches 0, the storage area defmed by the ccw is exhausted. Comnand aaaa m mal mm 1 a 11a a m mIl a1ae a1aa 1a a a 1aaa 1a a a Invalid Write Read Read backward Control Sense Sense ID Transfer in channell Transfer in channe1 2 Invalid 3 EXl:!lanation: m Modifier bit x Ignored 1 Format-a CCW 2 Format-l CCW 3 Format-l CCW with any of bits a-3 nonzero Figure 15-5. Command-Code Assignment Whenever the channel subsystem detects an invalid command code during the initiation of command execution, the program-check-interruption condition is generated and channel-program execution is terminated. The command code is ignored during data chaining, unless it specifies transfer in channel. Any main-storage location available to the start function can be used in the transfer of data to or from an 1/0 device, provided in both cases that the location is not protected against that type of reference. Format-O ccws can be located in any available part of the frrst 16M bytes of storage, and format-l ccws may be located in any part of available storage, provided that the location is not protected against a fetch-type reference. When the channel subsystem attempts to refer to 'a protected location, the protection-check condition is generated, and the device is, signaled to terminate the operation. A main-storage locati~ l& available if it is provided and access to it is noi J>l'evented by the addresslimit-checking facility. If a main-storage location is not available, it is said to have an invalid address. If the channel subsystem refers to a location not provided in the system, the program-check condition is generated. When the frrst ccw designated by the channel-program address is at a nonexistent location, the start function is not initiated at the device, the status portion of the scsw is updated with the program-check indication, and the subchannel becomes status-pending with primary, secondary, and alert status, and deferred condition code 1 is indicated. Invalid data addresses, as well as any invalid ccw addresses detected on chaining or subsequent to the execution of START S U BCHANNEL, cause the channel subsystem to signal Chapter 15. Basic I/O Functions 15-25 the device to conclude the operation the next time the device requests or offers a byte of data or status. In this situation, the subchannel is made status-pending with program check indicated in the subchannel status; the device status is a function of the status received from the device. The programcheck condition causes command chaining and command retry to be suppressed. During an output operation, the channel subsystem may fetch data from main storage before the time the I/O device requests the data. Any number of bytes specified by the current ccw may be prefetched and buffered. When data chaining during an output operation, the channel subsystem may fetch one ccw describing a data area at any time during the execution of the current ccw. If unlimited prefetching is allowed by the setting of the prefetch-control bit in the ORB, then any number of cCWs may be prefetched by the channel subsystem. When the I/O operation uses data and ccws from locations near the end of the available storage, such prefetching may cause the channel subsystem to Invalid refer to locations that do not exist. addresses detected during prefetching of data or CCWs do not affect the execution of the operation and do not cause error indications until the I/0 operation actually attempts to use the information. If the operation is concluded by the I/O device or by execution of HALT SUBCHANNEL or CLEAR SUBCHANNEL before the invalid information is needed, the condition is not brought to the a!tention of the program. The count field in the ccw can specify any number of bytes up to 65,535. In format-O ccws, the count field is always nonzero unless the command code specifies transfer in channel, in which case the count field is ignored. In format-l ccws, the count field may contain the value zero unless data chaining is specified or the ccw is fetched while data chaining. Whenever (I) the count field in a format-l ccw is zero, (2) data chaining is either not specified or is not in effect, and (3) data transfer is requested by the device, the device is signaled to stop, and the I/O operation is terminated. The channel subsystem sets the incorrect-length condition if the SLI flag is not one in the ccw. No data is transferred. If the device does not request data transfer, the operation proceeds to the normal ending point. If a zero byte count is contained in a format-O ccw which does not specify transfer in channel, or if a zero byte count is contained in a format-l ccw 15-26 ESA/370 Principles of Operation that specifies data chaining or was fetched while data chaining, a program-check condition is recognized, and the subchannel is made status-pending with combinations of primary, secondary, and alert status as a function of the state of the subchannel and the status received from the device. Note: For a description of the storage area associated with a ccw when indirect data addressing is invoked, see the section "CCW Indirect Data Addressing" on page 15-31. Chaining When the channel subsystem has completed the transfer of information specified by a CCW, it can continue performing the start function by fetching a new ccw. Such fetching of a new ccw is called chaining, and the ccws belonging to such a sequence are said to be chained. Chaining takes place between cCWs located in successive doubleword locations in storage. It proceeds in an ascending order of addresses; that is, the address of the new ccw is obtained by adding 8 to the address of the current ccw. Two chains of ccws located in noncontiguous storage areas can be coupled for chaining purposes by a transfer-inchannel command. All ccws in a chain apply to the I/O device that is associated with the subchannel designated by the original START SUBCHANNEL instruction. Two types of chaining are provided: chaining of data and chaining of commands. Chaining is controlled by the chain-data (CD) and chain-command (cc) flags in conjunction with the suppress-Iengthindication (SLI) flag in the ccw. These flags specify the action to be taken by the channel subsystem upon the exhaustion of the current ccw and upon receipt of ending status from the device, as shown in Figure 15-6 on page 15-27. The specification of chaining is effectively propagated through a transfer-in-channel command. When, in the process of chaining, a transfer-inchannel command is fetched, the ccw designated by the transfer-in-channel command is used for the type of chaining specified in the ccw preceding the transfer-in-channel command. The CD and cc flags are ignored in a format-O ccw specifying the transfer-in-channel command. In a format-l ccw specifying the transfer-in-channel command, the CD and cc flags must be zeros; otherwise, a program-check condition is recognized. Action at the Subchannel upon Exhaustion of Count or Receipt of Channel End Immediate Operation Flags in Current CCW Incorrect-LengthSuppression Model CCW CD CC SLI Count;e e e e e e e e 1 1 e 1 End, NIL End, NIL CC CC 1 - - End, NIL 1 Nonimmediate Operation Incorrect-LengthIndication Mode CCW Count=e CCW Count;e CCW Count=e CE Not Received Count Not Exhausted CE and CE Received Received End, NIL End, NIL CC CC End, IL End, NIL End, IL CC End, NIL End, NIL CC CC Stop, IL Stop,NIL Stop, IL Stop, CC End, NIL End, NIL CC CC PC End, IL PC CD Count Exhausted * End, IL End, NIL End, IL CC End, IL Explanation: The selected bit is ignored and may be either zero or one. * These situations cannot validly occur. When data chaining is specified, the new CCW takes control of the operation after transferring the last byte of data designated by the current CCW, but before the next request for data or status transfer from the device. The new CCW (which cannot contain a count of zero unless a program-check condition is also recognized) is in control of the operation. The count field must contain a nonzero value when format-a CCWs are specified; otherwise, the operation is terminated with a program-check condition. CC Command chaining is performed by the channel subsystem upon receipt of device end. CD The chain-data flag causes the channel subsystem to immediately fetch a new CCW for the same operation. The operation continues unless the CCW thus fetched has a count field of zero, in which case the operation is terminated with a program-check condition. CE Channel end from the device which indicates end of block. End Operation is terminated. IL Incorrect length is indicated with the subsequent interruption condition generated at the subchannel. NIL Incorrect length is not indicated with the subsequent interruption condition generated at the subchannel. PC These situations cannot validly occur. The channel subsystem recognizes a program-check condition when a CCW is fetched that has the chain-data flag set to one and a count field of zero. Stop Device is signaled to terminate data transfer, but subchannel remains subchannel-active until channel end is received. Figure 15-6. Subchannel Chaining Action Chapter IS. Basic I/O Functions 15-27 Programming Note: When bit 9 of word 1 of the ORB is one, unlimited fetching of chained ccws by the channel subsystem is permitted. When prefetching is allowed by the ORB, no modification of the channel program should be performed after START SUBCHANNEL is execute<.! and before the primary interruption condition for the operation has been received unless the subchannel is currently suspended and is not resume-pending. Data Chaining During data chaining, the new ccw fetched by the channel subsystem defmes a new storage area for the original I/O operation. Execution of the operation at the I/O device is not affected. When all data designated by the current ccw has been transferred to main storage or to the device, data chaining causes the operation to continue, using the storage area designated by the new ccw. The contents of the command-code field of the new ccw are ignored, unless they specify transfer in channel. the current ccw has been placed in main storage. On an output operation, the channel subsystem may fetch the new ccw from main storage before data chaining occurs. Any programming errors in the prefetched ccw, however, do not affect the execution of the operation until all data designated by the current ccw has been transferred to the I/O device. If the device concludes the operation before all data designated by the current ccw has been transferred, the conditions associated with the prefetched ccw are not indicated to the program. Unlimited prefetching is allowed under the control of the prefetch bit specified in the ORB. (See the section "Prefetch Control (P)" on page 15-21.) When unlimited prefetching is not allowed and an output operation is specified, only one ccw describing a data area may be prefetched. If a prefetched ccw specifies transfer in channel, only one more ccw may be fetched before the exhaustion of the current ccw. Programming Notes: Data chaining is consid~red to occur immediately after the last byte of data designated by the current ccw has been transferred to main storage or to the device. When the last byte of the data transfer has been placed in main storage or accepted by the device, the new ccw takes over the control of the operation. If the device sends channel end after exhausting the count of the current ccw but before transferring any data to or from the storage area designated by the new ccw, the scsw associated with the concluded operation pertains to the new ccw. If programming errors are detected in the new ccw or during its fetching, the error indication is generated, and the device is signaled to conclude the operation when it attempts to transfer data designated by the new ccw. If the device signals the channel-end condition before transferring any data designated by the new ccw, program check or protection check is indicated in the scsw associated with the termination. The contents of the scsw pertain to the new ccw unless the address of the new ccw is invalid, the location is protected against fetching, or programming errors are detected in an intervening transfer-in-channel command. A data address referring to a nonexistent or protected area causes an error indication only after the I/O device has attempted to transfer data to or from the invalid location. Data chaining during an input operation causes the new ccw to be fetched when all data designated by 15-28 ESA/370 Principles of Operation 1. If the ORB does not specify unlimited prefetching, no prefetching of ccws is performed, except in the case of data chaining on an output operation where one ccw describing a data area may be prefetched at a time. If the ORB for the I/O operation specifies that prefetching is allowed, any number of ccws may be prefetched and buffered in the channel subsystem. The same actions for signaling errors and terminating operations take place when unlimited prefetching is allowed by the 0 RB as when it is not allowed. Therefore, neither the program nor the I/O device is aware of any differences whether or not prefetching of ccws is being performed by the channel subsystem. When prefetching has been specified in the after after self-describing channel programs have been used, is unpredictable. (See note 2 for the definition of self-describing channel programs.) ORB, the result of modifications to ccws START SUBCHANNEL has been executed or 2. Data chaining may be used to rearrange information as it is transferred between main storage and an I/O device. Data chaining permits blocks of information to be transferred to or from noncontiguous areas of storage, and, when used in conjunction with the skipping function, data chaining allows the program to place in main storage specified portions of a block of data. When, during an input operation, the program specifies data chaining to a location in which data has been placed under the control of the current ccw, the channel subsystem, in fetching the next ccw, fetches the new contents of the location. This is true even if the location contains the last byte transferred under the control of the current ccw. When a channel program data-chains to a ccw placed in storage by the ccw specifying data chaining, the input block is said to be self-describing. A self-describing block contains one or more ccws that designate storage locations and counts for subsequent data in the same input block. The use of self-describing blocks is equivalent to the use of unchecked data. An 1/0 datatransfer malfunction that affects validity of a block of infonnation is signaled only at the completion of data transfer. The error condition nonnally does not prematurely terminate or otherwise affect the execution of the operation. Thus, there is no assurance that a ccw read as data is valid until the operation is completed. If the ccw thus read is in error, use of the ccw in the current operation may cause subsequent data to be placed at wrong locations in main storage with resultant destruction of its contents, subject only to the control of the protection key and the addresslimit-checking facility, if used. 3. When, during data chaining, a device transfers data by using the data-streaming feature, an overrun or chaining-check condition may be recognized when a small byte-count value is specified in the ccw. The minimum acceptable number of bytes that can be specified varies as a function of the system model and system activity. Command Chaining During command chaining, the new ccw fetched by the channel subsystem specifies a new 1/0 operation. The channel subsystem fetches the new ccw upon the receipt of the device-end signal for the current operation. If the new ccw does not specify an S flag and if no unusual conditions are detected, the channel subsystem initiates the new operation. The presence of the S flag or unusual conditions causes command chaining to be suppressed. When command chaining takes place, the completion of the current operation does not cause an 1/0 interruption, and the count indicating the amount of data transferred during the current operation is not made available to the program. For operations involving data transfer, the new command always applies to the next block of data at the device. Command chaining takes place and the new operation is initiated only if no unusual conditions have been detected in the current operation. In particular, the channel subsystem initiates a new 1/0 operation by command chaining upon receipt of a status byte containing only the following bit combinations: (1) device end, (2) device end and status modifier, (3) device end and channel end, and (4) device end, channel end, and status modifier. In the frrst two cases, channel end is signaled before device end, with all other status bits zeros. If a condition such as attention, unit check, unit exception, incorrect length, program check, or protection check has occurred, the sequence of operations is concluded, and the status associated with the current operation causes an interruption condition to be generated. The new ccw in this case is not fetched. The incorrect-length condition does not suppress command chaining if the current ccw has the SLI flag set to one. An exception to sequential chaining of ccws occurs when the 1/0 device presents the status-modifier condition with the device-end signal or channel-end and device-end signals. When command chaining is specified and no unusual conditions have been detected, or when command retry has been previously signaled and an immediate retry could not be performed, the combination of status-modifier and device-end bits causes the channel subsystem to alter the sequential execution of ccws. If command chaining was specified, status modifier and device end cause the channel subsystem to fetch and chain to the ccw whose main-storage address is 16 higher than that of the ccw that specified chaining. If command retry was previously signaled and immediate retry could not be performed, the status causes the channel subsystem to command chain to the ccw whose storage address is 8 higher than that of the ccw for which retry was initially signaled. When both command and data chaining are specified, the fIrst ccw associated with the operation specifies the operation to be executed, and the last ccw specifies whether another operation follows. Programming Note: Command chaining makes it possible for the program to initiate transfer of multiple blocks of data by executing a single START SUBCHANNEL instruction. It also permits a subchannel to be set up for execution of other commands, such as positioning the disk-access mechanism, and for data-transfer operations without Chapter 15. Basic I/O Functions 15-29 interference by the program at the end of each operation. Command chaining, in conjunction with the status-modifier condition, permits the channel subsystem to modify the normal sequence of operations in response to signals provided by the I/O device. Skipping Skipping causes the suppression of main-storage references during an I/O operation. It is defmed only for read, read-backward, sense ID, and sense operations, and is controlled by the skip flag, which can be specified individually for each ccw. When the skip flag is one, skipping occurs; when it is zero, normal operation takes place. The setting of the skip flag is ignored in all other operations. Skipping affects only the handling of information by the channel subsystem. The operation at the 1/0 device proceeds normally, and information is transferred. The channel subsystem keeps updating the count but does not place the information in main storage. Chaining is not precluded by skipping. In the case of data chaining, normal operation is resumed if the skip flag in the new ccw is zero. No checking for invalid or protected data addresses takes place during skipping. Programming Note: Skipping, when combined with data! chaining, permits the program to place in main storage specified portions of a block of information from an 1/0 device. Program-Controlled Interruption The program-controlled-interruption (PCI) function permits the program to cause an 1/0 interruption during execution of an 1/0 operation. The function is controlled by the PCI flag of the ccw. Neither the value of the PCI flag nor the associated interruption request affects the execution of the current operation. The value of the PCI flag can be one either in the frrst ccw designated for the current start or resume function or in a ccw fetched during chaining. If the PCI flag is one in a ccw that has become current, the subchannel becomes status-pending with intermediate status, and an I/o-interruption request is generated. The point at which the subchannel becomes status-pending depends on the progress of the current start or resume function as follows: 15"-30 ESA/370 Principles of Operation 1. If the PCI flag is one in the frrst ccw associated with a start function or a resume function, the subchannel becomes status-pending with intermediate status only after the command has been accepted. 2. If the PCI flag is one in a ccw which has become current while data chaining, the subchannel becomes status-pending with intermediate status after all data designated by the preceding ccw has been transferred. 3. If the PCI flag is one in a ccw which has become current while command chaining, the subchannel becomes status-pending with intermediate status as that ccw becomes current. In all cases, if the subchannel is enabled for 1/0 interruptions, the point of interruption depends on the current activity in the system and may be delayed. No predictable relationship exists between the point at which the interruption request is generated because of the PCI flag and the extent to which data transfer has been completed to or from the area designated by the ccw. However, all the fields within the scsw pertain to the same instant. An intermediate interruption condition that is made pending because of a PCI flag remains pending during chaining if not cleared by TEST SUBCHANNEL or CLEAR SUBCHANNEL. If another ccw containing a PCI flag that is one becomes current prior to the clearing of the intermediate interruption condition, only one interruption condition is preserved. An intermediate interruption may occur while the subchannel is subchannel-and-device-active with the operation specified by the ccw causing the intermediate interruption condition or with the operation specified by a ccw that has subsequently become current. If the intermediate interruption condition is not cleared prior to the conclusion of the operation or chain of operations, the condition is indicated together with the primary interruption condition at the conclusion of the operation or chain of operations. The intermediate interruption condition may be cleared by TEST SUBCHANNEL while the subchannel is subchannel-active. If the scsw stored by TEST SUBCHANNEL indicates that the subchannel is status-pending with intermediate status and the operation or chain of operations has not been concluded (that is, the activitycontrol field indicates subchannel-and-device-active or suspended), then the ccw-address field contains an address which is 8 higher than the address of the most recent ccw to become current and have a PCI flag that is one, or the ccw-address field contains an address which is 8 higher than a ccw which has subsequently become current. Unless the scsw also contains the primary-status bit set to one, the device-status field contains zeros, and the count is unpredictable. Subchannel-status conditions other than PCI may be indicated when the scsw is stored. If the subchannel is not also status-pending with primary status, these conditions mayor may not be indicated again. If the subchannel-status condition is detected while prefetching and the operation or chain of operations is concluded before the condition affects an operation, the condition is reset and is not indicated when the subchannel subsequently becomes status-pending with primary status. If the subchannel-status condition affects an operation, the condition is indicated when the subchannel becomes status-pending with primary status. If the program-controlled-interruption condition remains pending until the operation or chain of operations is concluded at the subchannel, a single interruption request exists. When TEST SUBCHANNEL is subsequently executed, the statuscontrol field of the scsw stored indicates both the primary interruption condition and the intermediate interruption condition, and the PCI bit of the subchannel-status field is one. The value of the PCI flag is inspected in every ccw except for those CCWs that specify the transfer-inchannel command. The PCI flag is ignored during initial program loading. Programming Notes: 1. The program-controlled interruption provides. a means of alerting the program to the progress of chaining during an I/O operation. It permits programmed dynamic main-storage allocation. 2. A ccw with a PCI flag that has a value of one may, if retried because of command retry, cause multiple PCI interruptions to occur. (See the section "Command Retry" on page 15-41.) CCW Indirect Data Addressing CCW indirect data addressing permits a single channel-command word to control the transfer of data that spans noncontiguous pages in real main storage. The use of ccw indirect data addressing also allows the program to designate data addresses above 16M for both format-O and format-l CCws. CCW indirect data addressing is specified by a flag in the ccw which, when one, indicates that the data address is not used to directly address data. Instead, the address points to a list of words, called indirect-data-address words (IDAWS), each of which contains an absolute address designating a data area within a 2K-byte block of main storage. When the indirect-data-addressing bit in the ccw is one, the data-address field of the ccw designates the location of the rust IDAW to be used for data transfer for the command. Additional IDAws, if needed for completing the data transfer for the CCW, are in successive locations in storage. The number of IDAWS required for a ccw is determined by the count field of the ccw and by the data address in the initial IDAW. When, for example, the ccw count field specifies 4K bytes and the rust IDAW designates a location in the middle of a 2K-byte block, three JDAWS are required. Each IDAW is used for the transfer of up to 2K bytes. The IDAW designated by the ccw can designate any location. Data is then transferred, for read, write, control, sense ID, and sense commands, to or from successively higher storage locations or, for a read-backward command, to successively lower storage locations, until a 2K -byte block boundary is reached. The control of data transfer is then passed to the next IDAW. The second and any subsequent IDAWs must designate, depending on the command, the rust or last byte (for read . backward) of a 2K-byte block. Thus, for read, write, control, sense ID, and sense commands, these IDAWS have zeros in bit positions 21-31. For a read-backward command, these IDAWS have ones in bit positions 21-31. Except for the unique restrictions on the designation of the data address by the IDAW, all other actions taken for the data address, such as for protected storage and invalid addresses, and the actions taken for data prefetching are the same as when indirect data addressing is not used. Chapter 15. Basic I/O Functions 15-31 pertaining to the current CCW or 'a prefetched ccw may be prefetched. The number of IDAws that can be prefetched cannot exceed that required to satisfy the count in the ccw that points to the IDAws. An IDAW takes control of data transfer when the last byte has been transferred for the previous IDAW. The same actions take place as with data chaining regarding when an IDAW takes control of data transfer during an I/O operation. That is, when the count for the ccw has not reached zero, a new IDAW takes control of the data transfer when the last byte has been transferred for the previous IDAW for that ccw, even in situations where (1) channel end, (2) channel end and device end, or (3) channel end, device end, and status modifier are received prior to transfer of any data bytes pertaining to the new IDAW. IDAWS A prefetched IDAW does not take control of an I/O operation if the count in the ccw has reached zero with the transfer of the last byte of data for the previous IDAW for that ccw. Program or access errors detected in prefetched IDAWS are not indicated to the program until the IDAW takes control of data transfer. However, when the channel subsystem detects an invalid CBC on the contents of a prefetched IDAW or its associated key, the condition may be indicated to the program, when detected, before the IDAW takes control of data transfer. For a description of the indications provided when an invalid CBC is detected on the contents of an IDAW or its associated key, see the section "ChannelControl Check" on page 16-31. The format of the IDAW and the significance of its fields are as follows: Data Address 31 (3 Bit 0 is reserved for future use and must be zero. Otherwise, a program-check condition may be recognized, as described below. Bits 1-31 designate the location of the frrst byte to be used in the data transfer. In the frrst IDAW for a CCW, any location can be designated. F or subsequent IDAWS, depending on the command, either the frrst or the last location of a 2K -byte block located on a 2K -hyte boundary must be designated. For read, write, control, and sense commands, the location at the beginning of the block must be designated; that is, bits 21-31 of the IDAW must be 15-32 ESA/370 Principles of Operation zeros. For a read-backward command, the location at the end of the block must be designated; that is, bits 21-31 of the IDAW must be all ones. Improper data-address designation causes the program-check condition to be generated and the operation to be terminated. When the IDA flag of the ccw is set to one and any of the following conditions occurs: 1. The address in the ccw does not designate the frrst IDAW on an integral word boundary, 2. The address in the ccw designated a storage location which is not available, 3. Access to the storage location designated by the address in the ccw is prohibited by protection, or 4. Bit 0 of the frrst IDA W is not zero, then, depending on the tnodel, one of the following two actions is taken independent of the setting of the skip flag: 1. The above conditions are checked before initiating the operation at the device. If any of these conditions is recognized, initiation of the I/O operation does not occur, and the subchannel is made status-pending with primary, secondary, and alert status. 2. The operation is initiated at the device prior to checking for these conditions. If the device attempts to transfer data, the device is signaled to terminate the I/O operation, and the subchannel is made status-pending with primary, secondary, and alert status as a function of the subchannel state and the status presented by the device. Suspension of Channel-Program Execution The suspend function, when used in conjunction with RESUME SUBCHANNEL, provides the program with a means to stop and restart the execution of a channel program. The initiation of the suspend function is controlled by the setting of the suspendcontrol bit in the ORB (bit 4 of word 1). The suspend function is signaled when suspend control has been specified for the subchannel in the ORB and a ccw containing a valid S flag set to one becomes the current ccw. The flag can be indicated either in the frrst ccw of the channel program or in a ccw fetched while command chaining. The S flag is not valid and causes a program-check con- dition to be recognized if (1) the ORB contains the suspend-control bit set to zero, or (2) the ccw is fetched while data chaining (see the section "Data Chaining" on page 15-28, concerning the handling of programming errors detected during data chaining). Upon recognition of the suspend function, suspension of channel-program execution occurs when the ccw becomes current (see the section "ChannelCommand Word" on page 15-23, for a deftnition of when a ccw becomes current). If suspension occurs during command chaining, the device is signaled that command chaining is no longer in effect. signals that the ccw which caused channel-program suspension may have been modifted, that the ccw must be refetched, and that the contents of the ccw must be examined to determine the settings of the flags. If the S flag is one, execution of that ccw does not occur. If the ccw is valid and the S flag in the ccw is zero, execution is initiated (see the section "Resume Subchannel" on page 14-8 and the section "Start Function and Resume Function" on page 15-17). RESUME SUBCHANNEL When a valid ccw that contains a valid S flag becomes the current ccw during command chaining and the resume-pending condition is not recognized, the suspend function is performed and . causes the following actions to occur in the order given: 1. The device is signaled that the chain of operations has been concluded. 2. Channel-program execution is suspended at the subchannel; all prefetched IPAWS, ccws, and data are discarded; and the subchannel is set up such that the resume function can be performed when the subchannel is next recognized to be resume-pending. 3. If the measurement-block-update mode is active and the subchanne1 is enabled for the mode, the accrued values of the measurement data, including the start-subchannel and sample count, are added to the accumulated values in the measurement block for the subchannel. The start-subchannel count is the only measurement data which is updated in the measurement block if the channel-subsystem-timing facility is not available for the subchannel. (See the section "Channel-Subsystem Monitoring" on page 17-1, for qlore information.) 4. The subchannel is placed in the suspended state. 5. If the sub channel is not resume-pending at this point, the intermediate interruption condition due to suspension is recognized if the suppresssuspended-interruption bit of the ORB is zero; otherwise, the resume function is performed. When a valid ccw that contains a· valid S flag becomes the current ccw during command chaining and the resume-pending condition is recognized, the resume function is performed instead of the suspend function. When the first ccw of a channel program contains a valid S flag and the resume-pending condition is not recognized, the suspend function is performed and causes the following actions to occur in the order given: 1. Channel-program execution is suspended prior to selection of the device. 2: The sub channel is set up such that the resume function can be performed when the subchannel is next recognized to be resumepending. 3. If the measurement-block-update mode is active and the subchannel is enabled for the mode, the SSCH + RSCH count is incremented and the accrued\function-pending time (a function of the setting of the timing-facility bit) is added to the accumulated value in the measurement block for the sub channel. 4. The subchannel is placed in the suspended state. 5. If the subchannel is not resume-pending at this point, the sub channel is made status-pending with intermediate status due to suspension if the suppress-suspended-interruption-control bit of the ORB is zero; otherwise, the resume function is performed. When the frrst ccw of a channel program contains a valid S flag and the resume-pending condition is recognized, the resume function is performed instead of the suspend function. Programming Notes: 1. The execution of MODIFY SUBCHANNEL and completes with condition code 2 set if the designated subchannel is suspended. The start function is indicated at the subchannel while the sub channel is in the suspended state. START SUBCHANNEL Chapter 15. Basic I/O Functions 15-33 2. In certain situations, normal resumption of the execution of a channel program which has been suspended may not be desired. Normal termination of the suspended channel-program execution may be accomplished by: a. Executing HALT the subchannel SUBCHANNEL designating b. Modifying the ccws in storage such that when channel-program execution is resumed, the command transferred to the device is a control command with all modifier bits specified as zeros (no-operation) and with the chain-command flag specified as zero; and then executing RESUME SUBCHANNEL. 3. If the suspended interruption is suppressed, the N condition and DCTI values applicable to the preceding subchannel-active period are not made available to the program. The execution of RESUME SUBCHANNEL when the subchannel is in the suspended state causes path-notoperational conditions and the N condition to be reset to zeros. Path-not-operational conditions and the N condition are not reset when RESUME SUBCHANNEL is executed and the designated subchannel is not in the suspended state. Commands Figure 15-7 lists the command codes for the seven commands and indicates which flags are defmed for each command. Except for a format-l ccw specifying transfer in channel, the flags are ignored for all commands for which they are not defmed. The flags are reserved in a format-l ccw specifying transfer in channel and must be zeros. Name Flags Code Write Read Read backward Control Sense Sense ID Transfer in channel MMMM MMMM MMMM MMMM MMMM 111e MMal MM1 e 11a e MM1 1 e lea e 1a e XXXX 1 a a a CD CC SLI CD CC SLI CD CC SLI CD CC SLI CD CC SLI CD CC SLI (See note PCI IDA SK PCI IDA SK PCI IDA PCI IDA SK PCI IDA SK PCI IDA below) S S S S S S EXJ;!lanation: CC CD IDA M PCI S SK SLI X Note: Chain command Chain data Indirect data addressing Modifier bit Program-controlled interruption Suspend Skip Suppress-length indication Ignored in a format-a CCWj must be zero in a format-l CCW Flags are ignored in a format-a transfer-inchannel CCW and must be zeros in a format-l transfer-in-channel CCW. Figure 15-7. Command Codes All flags have individual significance, except that the· cc and SLI flags are ignored when the CD flag is set to one. The presence of the SLI flag is ignored for immediate operations involving format-O ccws, in which case the incorrect-length indication is suppressed regardless of the setting of the flag. The incorrect-length indication may be suppressed for immediate operations when executing a format-l ccw, depending on the incorrect-Iengthsuppression mode. The PCI flag is ignored during initial program loading. All flags, except the PCI flag, are ignored when the S flag is one. Each command is described below, with an illustration of its ccw formats. Programming Notes: 1. A malfunction that affects the validity of data transferred in an I/O operation is signaled at the end of the operation by means of unit check or channel-data check, depending on whether the device (control unit) or the channel subsystem detected the error. In order to make use of the checking facilities provided in the system, data read in an input operation should not be used until the end of the operation has been reached and the validity of the data has been checked. Similarly, on writing, the copy of data in main storage should not be destroyed until the program has verified that no malfunction 15·34 ESAj370 Principles of Operation affecting the transfer and recording of data was detected. 2. An error condition may be recognized and the I/O operation terminated when 256 or more chained commands are executed with a device and none of the executed commands result in the transfer of any data. When this condition is recognized, program check is indicated. count in the ccw. Every operation terminated under count control causes the incorrect-length indication, unless the indication is suppressed by the SLI flag. Read Format 8 3. All ccws that require suppression of incorrectlength indications must use the SLI flag. MMMMMM18 Data Address Write Format e e s CCS K P I D C L I C D S 8 11111/11 I PI A Data Address e 31 8 CCS P I D C L I C D S 8 11111/11 I I A 32 31 8 48 35 32 48 48 35 Count 63 Format 1 Count S 48 63 C C S KP I MMMMMM18 D C L I C D S e I PI A Count Format 1 8 CCS P I MMMMMMe1 D C L / C D S e I I A e 8 11 8 11 16 31 Count 16 31 lal Data Address 32 63 Data Address 32 63 A write operation is initiated at the I/O device, and the subchanne1 is set up to transfer data from main storage to the I/O device. Data is fetched from storage in an ascending order of addresses, starting with the location designated by the ccw. A ccw used in a write operation is inspected for the CD, CC, SLI, PCI, IDA, and S flags. The setting of the skip flag is ignored. Bit positions 0-5 of the ccw contain modifier bits. Programming Note: When writing on devices for which the block length is not dermed, such as a magnetic-tape unit or an inquiry station, the amount of data written is controlled only by the A read operation is initiated at the I/O device, and the subchannel is set up to transfer data from the For devices such as device to main storage. magnetic-tape units, disk storage, and card equipment, the bytes of data within a block are provided in the same sequence as written by means of a write command. Data is placed in storage in an ascending order of addresses, starting with the location designated by the ccw. A read command code containing zeros for the six modifier bits is also called an initial-read command. This command is used by those devices that can perform the initial-program-loading function if the command is the fITst to be executed after a systemreset signal is received. A ccw used in a read operation is inspected for every one of the seven flags -- CD, CC, SLI, SKIP, Chapter 15. Basic I/O Functions 15-35 PCI, IDA, and s. Bit positions 0-5 of the ccw contain modifier bits. Format 8 Read Backward 1~~J11 a Format Control 8 Oata Address MMMM11aa 31 8 CCS K P I o CLI C0 S I PI A 32 a 11111111 48 35 48 35 63 MMMMMM11 8 S CCS K 8 lal PI C0 S I PI A oCLI 8 11 Count 8 16 lei 31 Oata Address 32 63 A read-backward operation is initiated at the I/O device, and the subchannel is set up to transfer data from the device to main storage. On magnetic-tape units, read backward causes reading to be performed with the tape moving backward. The bytes of data within a block are sent in a sequence opposite to that on writing. The bytes are placed in storage in a descending order of addresses, starting with the location designated by the ccw. The bits within an eight-bit byte are in the same order as sent to the device on writing. A ccw used in a read-backward operation is inspected for every one of the seven flags -- CD, CC, SLI, SKIP, PCI, IDA, and s. Bit positions 0-3 of the ccw contain modifier bits. 15-36 ESA/370 Principles of Operation 48 CCS P I oCL I C0 S I I A Format 1 MMMM1188 Count 63 Format 1 Count 48 31 8 CCS P I o C L I C 0 S 8 11111111 I I A 32 s Oata Address 32 8 11 Count 8 16 31 Data Address 63 A control operation is initiated at the I/O d~vice, and the subchannel is set up to transfer data from main storage to the device. The device interprets the data as control information. The control information, if any, is fetched from storage in an ascending order of addresses, starting with the A control address designated in the ccw. command may be used to initiate at the device an I/O operation not involving transfer of data, such as backspacing or rewinding magnetic tape or positioning a disk-access mechanism. For many control functions, the entire operation is specified by the modifier bits in the command code, and the function is performed over the channel path as an immediate operation (see the section "Immediate Conclusion of 110 Operations" on page 15-42). If the command code does not specify the entire control function, the data-address field of the ccw designates the location containing the required additional information. This control information may include an order code further specifying the operation to be executed or an address, such as the disk address· for the seek function, and is transferred in response to requests by the device. A control-command code containing zeros for the six modifier bits is defmed as a no-operation. If the command is accepted, the no-operation order causes the addressed device to respond with channel end and device end without causing any action at the device. The order can be executed as an immediate operation, or the device can delay the status until after the initiation sequence is completed. Other operations that can be initiated by means of the control command depend on the type of I/O device. These operations and their codes are specified in the System Library publication for the device. A ccw used in a control operation is inspected for the CD, CC, SLI, PCI, IDA, and S flags. The setting of the skip flag is ignored. Bit positions 0-5 of the ccw contain modifier bits. Sense Format 9 2. If the subchannel is in the incorrect-Iengthsuppression mode, if the chain-data flag in the current ccw is zero, and if the operation is executed as an immediate operation, then incorrect length is not indicated, regardless of the setting of the S LI flag. If the sub channel is in the incorrect-Iengthindication mode, if the chain-data flag in the current ccw is zero, and if the operation is executed as an immediate operation, then incorrect length is indicated if the count field of the current ccw specifies a nonzero value, unless suppressed by the SLI flag of the ccw; incorrect length is not indicated, however, if the count field of the ccw specifies a value of zero. If a new ccw that has a count field of zero is fetched during data chaining or if a ccw is fetched with the chain-data flag set to one and a count field of zero, then a program-check condition is recognized by the channel subsystem. 31 8 s CCS K P I D C L I C D S 9 IIIIIIII I PI A 32 35 49 Count 63 48 Format 1 S Programming Notes: 1. Since a format-l ccw with a count of zero is valid, the program can use the ccw count field to specify that no data be transferred to the I/O device. If the device requests a data transfer, the device is signaled to terminate data transfer. If the SLI and chain-command flags are also specified, and no unusual conditions are encountered subsequent to signaling the device to terminate data transfer, then the new operation is initiated upon receipt of device end from the device. Data Address MMMM9199 CCS K P I MMMM9199 D C L I C D S 9 Count I PI A 9 8 11 16 31 Data Address lal 32 63 A sense operation is initiated at the I/O device, and the subchannel is set up to transfer sense data from the device to storage. The data is placed in storage in an ascending order of addresses, starting with the location designated by the ccw. The basic sense command is specified when the modifier bits are all zeros. Data transferred during a basic sense operation provides information concerning both unusual conditions detected by the device and the status of the device. The information provided by the basic sense command is more detailed than that supplied by the device-status byte and may describe reasons for the unit-check indication. It may also indicate, for example, if the device is in the not-ready state, if the tape unit is in the fue-protected state, or if magnetic tape is positioned beyond the end-of-tape mark. The f11'st six bits of the f11'st sense-data byte (sense byte 0) are common to all I/O devices. The six bits, when set to ones, designate the following: Chapter 15. Basic I/O Functions - t 5-37 Bit 0 1 2 3 4 5 Designation Command reject Intervention required Bus-out check Equipment check Data check Overrun The following is the meaning of the frrst six bits: Command Reject: The device has detected a pro- gramming error. A command has been received which the device is not designed to execute, such as read backward transferred to a direct-access-storage device, or which the device cannot execute because of its present state, such as write transferred to a ftle-protected tape unit. The program may have required use of an optional feature or may have specified invalid control data. An example of invalid control data which is treated as an extension of the command is an invalid seek argument that is transferred to a direct-access-storage device. Command reject is also indicated when an invalid sequence of commands is recognized by the device, such as write to a direct-access-storage device without previously designating the data block. Intervention Required: The last operation could not be executed because of a condition requiring some type of intervention at the device. This bit set to one indicates conditions such as an empty hopper in a card punch or the printer being out of paper. It is also set to one when the addressed device is in the not-ready state, is in test mode, or on some control units when the device is not provided on the control unit~·· The device has received a data byte or a command code with invalid CBC over the channel path. During writing, bus-out check indicates that incorrect data may have been recorded at the device, but the condition does not cause the operation to be terminated prematurely unless the operation is such that an error precludes meaningful continuation of the operation. Invalid CBC detected on the command code or control information causes the operation to be immediately terminated and suppresses checking for command-reject and intervention-required conditions. Bus-Out Check: 15-38 ESA/370 Principles of Operation Equipment Check: During the last operation, the device has detected equipment'malfunctioning, such as an invalid card-hole count or a printer-buffer parity error. Data Check: The device has detected a data error other than one included in bus-out check. Data check identifies errors associated with the recording medium and includes conditions such as reading an invalid card code or detecting invalid parity on data recorded on magnetic tape. On an input operation, data check indicates that incorrect data may have been placed in main storage. The device forces correct parity on data sent to the channel subsystem. On writing, this condition indicates that incorrect data may have ~een recorded at the device. Unless the operation IS of a type where the error precludes meaningful continuation, data errors on reading and writing do not cause the operation to be terminated prematurely. Overrun: The overrun condition occurs when the channel subsystem fails to respond to the control unit in the anticipated time interval to a request for service from the 1/0 device. When the total activity initiated by the program exceeds the capability of the channel subsystem, an overrun may occur when data is transferred to or from a control unit that is either using the data-streaming feature or is not buffered. An overrun condition also may occur when the device receives the new command too late during command chaining. The data-streaming feature is described in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. Refer to the System Library publication for the device for information concerning the availability of the datastreaming feature for that device. All information significant to the use of the device normally is provided in the first sense byte. Any ~it posit~ons following those used for programming information may contain diagnostic information, and the total number of sense bytes provided by the qevice for the basic sense command (command code 04 hex) may extend up to 32 bytes, as needed. The number and the meaning of the sense bytes extending beyond the frrst sense byte depend on the type of I/O device. The basic sense command initiates a sense operation on all devices and cannot cause the commandreject, intervention-required, data-check, or overrun bit to be set to one. If the control unit detects an equipment malfunction, or invalid parity on the sense-command code, the equipment-check or busout-check bit is set to one, and unit check is indicated in the device-status byte. Format. 1 Devices that can provide special diagnostic sense information or that can be instructed to perform other special functions by use of the sense command may defme modifier bits for the control of these functions. The special sense operations may be initiated by a unique combination of modifier bits (see the section "Sense ID"), or a group of codes may specify the same function. Any remaining sense-command codes may be considered invalid, thus causing the unit-check indication, or may cause the same action as the basic sense command, depending on the type of device. a The sense information pertaining to the last I/O operation or device action may be reset any time after the completion of a· sense command addressed to that device. Except for the no-operation command, any other command addressed to the device may be allowed to reset the sense information, provided that the busy bit is not included in the initial status. The sense information may also be changed as a result of asynchronous actions, for example, when the device changes from the notready to the ready state. A ccw used in a sense operation is inspected for every one of the seven flags -- CD, CC, SLI, SKIP, PCI, IDA, and s. Bit positions 0-3 of the ccw contain modifier bits. Illaalaa 31 63 The control unit and I/O device may properly execute the sense-ID cotnlnand, may execute the command as the basic sense command, or may reject the sense-ID command with unit-check status, depending on the control-unit and I/o-device model. The sense-ID command does not initiate anyoperations other than the sensing of the type/model number. If the control unit and I/O device are available, then the sense-ID command is executed even if the I/O device is absent or not ready. Basic sense data may be reset as a result of executing the sense-ID command. 6 Data Address 16 Execution of the sense- 10 command proceeds exactly as for a read command, except that the data is obtained from sensing indicators rather than from a record source. The data transferred can be up to seven bytes in length. 1,2 3 4,5 11100100 11 32 o Fonnat 0 8 Count Data Address Bytes Sense ID S C C S KP I DC L I C DS a I PI A Contents FFhex Control-unit type number Control-unit model' number I/o-device type number I/o-device model number All unused sense bytes are set to zeros. a 8 31 s C C S KP I D C L I C D S a ////1/// I PI A 32 35 4a Count 48 63 Bytes 1 and 2 contain the four-decimal-digit control-unit type number that corresponds directly with the control-unit type number attached to the control unit. Byte 3 contains the control-unit model number, if applicable. If not applicable, byte 3 is a byte of all zeros. Bytes 4 and 5 contain the four-decimal-digit I/o-device type number that corresponds directly Chapter 15. Basic I/O Functions 15-39 with the l/o-deviGe type number attached to the I/O device. Byte 6 contains the I/o-device model number, if applicable. If not applicable, byte 6 is a byte of all zeros. Transfer in Channel Format a CCW Address 31 8 Whenever a control unit is not separately addressable from the attached I/O device or I/O devices, the response to the sense-ID command is a concatenation of the control-unit type number and the I/o-device type number. If a control unit can be addressed separately from the attached I/O device or I/O devices, then the response to the sense-ID command depends on the unit addressed. If the control unit is addressed, the response to the sense-ID command is as follows: llytes o 1,2 3 (;ontents FF hex Control-unit type number Control-unit model number The response consists of the control-unit type and model number, with. normal ending status presented after byte 3. If the I/O device is addressed, the response to the sense-ID command is as follows: Bytes o 1,2 3 (;ontents FF hex I/o-device type number I/o-device model number The response consists of the I/o-device type and model number, with normal ending status presented after byte 3. F or communication controllers utilizing indirect addressing to end devices,and for cases where the control unit and device are not distinct, the sense data source is the same as if a control unit were being addressed. A ccw used in a sense-IDoperation is inspected for every flag -- CD, CC, SLI, SKIP, PCI, IDA, and s. 1/1//1//1////1/1///////11/////////1111111/1////// 32 63 Format 1 laeeeHlae I e 8 lal 32 Zeros 31 CCW Address 63 The next ccw is fetched from the location in absolute main storage designated by the data-address field of the ccw specifying transfer in channel. The transfer-in-channel command does not initiate any I/O operation, and the I/O device is not signaled of the execution of the command. The purpose of the transfer-in-channel command is to provide chaining between ccws not located in adjacent doubleword locations in an ascending order of addresses. The command can occur in both data and command chaining. Bits 29-31 (format 0) or bits 61-63 (format 1) of a ccw that specifies the transfer-in-channel command must be zeros, designating a ccw on a doubleword boundary. Furthermore, a ccw specifying transfer in channel may not be fetched from a location designated by an immediately preceding transfer in channel. When either of these errors is detected or when an invalid address is designated in the transfer-in-channel command, the program-check condition is generated. When a ccw which specifies the transfer-in-channel command designates a ccw at a location protected against fetching, the protection-check condition is generated. Detection of these errors during data chaining causes the operation at the I/O device to be terminated and an interruption condition to be generated, whereas during command chaining it causes only an interruption condition to be generated. The contents of the second half of the format-O ccw, bit positions 32-63, are ignored. Similarly, 15~40 ESAj370 Principles of Operation the contents of bit positions 0-3 of the format-O ccw are ignored. Bit positions 0-3 and 8-32 of the format-l ccw must contain zeros; otherwise, a program-check condition is generated. Command Retry The channel subsystem has the capability to perform command retry, a procedure that causes a command to be retried without requiring an I/O interruption. This retry is initiated by the control unit presenting either of two status-bit combinations by means of a special sequence. When immediate retry can be performed, it presents a channel-end, unit-check, and status-modifier status-bit combination, together with device end. When immediate retry cannot be performed, the presentation of device end is delayed until the control unit is prepared. When device end is presented alone, the previous command is transferred again. If device end is accompanied by status modifier, command retry is not performed, and the channel subsystem command-chains to the ccw following the one for which command retry was signaled (see the section "Status Modifier" on page 16-23). When the channel subsystem is not capable of performing command retry due to an error condition, or when any status bit other than device end or device end and status modifier accompanies the requested cOriunand-retry initiation, the retry is suppressed, and the subchannel becomes status-pending. The scsw stored by TEST SUBCHANNEL contains the channel-end, unit-check; and status-modifier status indications, along with any other appropriate status. Programming Note: The following possible results of a command retry must be anticipated by the program: 1. A ccw containing a PCI may, if retried because of command retry, cause multiple PCI interruptions to occur. 2. If a ccw used in an operation is changed before that operation has been successfully completed, the results are unpredictable. Concluding -1/0 Operations During Initiation After the designated subchannel has been determined to be in a state such that START SUBCHANNEL can be executed, certain tests are performed on the validity of the information specified by the program and on the logical availability of the associated device. This testing occurs during or subsequent to the execution of START SUBCHANNEL and during command chaining and command retry. A data-transfer operation is initiated at the subchannel and device only when no programming or equipment errors are detected by the channel subsystem and when the device responds with zero status during the initiation sequence. When the channel subsystem detects or the device signals any unusual condition during the initiation of an I/O operation, the command is said to be not accepted. In this case, the sub channel becomes statuspending with primary, secondary, and alert status. Deferred condition code 1 is set, and the startpending bit remains set to one. Conditions that preclude the initiation of an I/O operation are detailed in the scsw stored by TEST SUBCHANNEL. In this situation, the device is not started, no interruption conditions are generated subsequent to TEST SUBCHANNEL, and the subchannel is idle. The device is immediately available for the initiation of another operation, provided the command was not rejected because of the busy or not-operational condition. When an unusual condition causes a command to be not accepted during the initiation of an I/O operation by command chaining or command retry, an interruption condition is generated, and the subchannel becomes status-pending with combinations of primary, secondary, and alert status as a function of the status signaled by the device. The status describing the condition remains at the subchannel until cleared by TEST SUBCHANNEL. The conditions are indicated to the program by means of the corresponding status bits in the scsw. A path-notoperational condition recognized during command chaining is signaled to the program by means of an interface-control-check indication. The new I/O operation at the device is not started. is executed independent of its associated device.- Tests on most program-specified information, on device availability and unit status, START SUBCHANNEL Chapter 15. Basic I/O Functions 15-41 and on most error conditions are performed subsequent to the execution of START SUBCHANNEL. When any conditions are detected that preclude performance of the start function, an interruption condition is generated by the channel subsystem and placed at the subchannel, causing it to become status-pending. Immediate Conclusion of 1/0 Operations During the initiation of an 1/0 operation, the device can accept the command and signal the channel-end condition immediately upon receipt of the command code. An 1/0 operation causing the channel-end condition to be signaled during the initiation sequence is called an immediate operation. Status generated by the device for the immediate command, when command chaining is not specified and command retry is not signaled, causes the subchannel to become status-pending with combinations of primary, secondary, intermediate, and alert status as a result of information specified in the ORB and ccw and status presented by the device. If the immediate operation is the frrst operation of the channel program, deferred condition code I is set and accompanies the status indications. If intermediate status is indicated, the indication can occur only as a result of the ccw having the PCI flag set to one (see the section "Program-Controlled Interruption" on page 15-30). Whenever command chaining is specified after an immediate operation and no unusual conditions have been detected during the execution, or when co~and retry occurs for an immediate operation, an mterruption condition is not generated. The subsequent commands in the chain are handled normally, and, usually, the channel-end condition for the last ccw generates a primary interruption condition. If device end is signaled with channel end, a secondary interruption condition is also generated. Whenever immediate completion of an 1/0 operation is signaled, no data has been transferred to or from the device, and the data address in the ccw is not checked for validity. If the subchannel is in the incorrect-length-suppression mode, incorrect length is not indicated to the program, and command chaining is performed when specified. If the subchannel is in the incorrect-length-indication mode incorrect length and command chaining are unde; control of the SLI and chain-command flags. The 15-42 ESA/370 Principles of Operation conditions which cause the incorrect-length indication to be suppressed are summarized in Figure 15-6 on page 15-27. Programming Note: I/O operations for which the entire operation is specified in the command code may be executed as immediate operations. Whether the command is executed as an immediate operation depends on the operation and type of device. Concluding 1/0 Operations During Data Transfer When the subchannel has been passed the contents of an ORB, the sub channel is said to-be startpending. When the I/O operation has been initiated and the command has been accepted, the subchannel becomes subchannel-and-device active and remains in that state unless ( I) the channel subsystem detects an equipment malfunction, (2) the operation is concluded by execution of CLEAR SUBCH~NNEL or HALT SUBCHANNEL, or (3) status which causes a primary interruption condition to be recognized (usually channel end) is accepted from the device. When command chaining and ~ommand retry are not specified or when chaining IS suppressed because of unusual conditions, the status that is recognized as primary status causes the operation at the subchannel to be concluded and an interruption condition to be generated. The status bits in the associated scsw indicate primary stat~s and the unusual conditions, if any. The deVice can present status that is recognized as primary status at any time after the initiation of the I/O operation, and the presentation of status may occur before any data has been transferred. For operations not involving data transfer the device normally controls the timing of' the channel-end condition. The duration of datatransfer operations may be variable and may be controlled by the device or the channel subsystem. Excluding equipment errors, and the execution of the CLEAR SUBCHANNEL, HALT SUBCHANNEL, and RESET CHANNEL PATH instructions, the channel subsystem signals the device to conclude execution of an I/O operation during data transfer whenever any of the following conditions occurs: • The storage areas designated for the operation are exhausted or filled. • A program-check condition is detected. • A protection-check condition is detected. • A chaining-check condition is detected. • A channel-control~check condition is detected that does not affect the control of the I/O operation. The frrst of these conditions occurs when the channel subsystem has decremented the count to zero in the last ccw associated with the operation. A count of zero indicates that the channel subsystem has transferred all information specified by the I/O operation. The other four conditions are due to errors and cause premature conclusion of data transfer. In either case, the conclusion is signaled in response to a service request from the device and causes data transfer to cease. If the device has no blocks defmed for the operation (such as writing on magnetic tape), it concludes the operation and presents channel-end status. The device can control the duration of an operation and the timing of channel end by blocking of data. On certain operations for which blocks are defmed (such as reading on magnetic tape), the device does not present channel-end status until the end of the block is reached, regardless of whether the device has been previously signaled to conclude data transfer. Checking for the validity of the data address is performed only as data is transferred to or from main storage. When the initial data address in the ccw is invalid, no data is transferred during the operation, and the device is signaled to conclude the operation in response to the first service request. On writing, devices such as magnetic-tape units request the frrst byte of data before any mechanical motion is started and, if the initial data address is invalid, the operation is terminated by the channel subsystem before the recording medium has been advanced. However, since the operation has been initiated at the device, the device presents channel-end status, causing the channel subsystem to recognize a primary interruption condition. Subsequently, the device also presents device-end status, causing the channel subsystem to recognize a secondary interruption condition. Whether a block at the device is advanced when no data is transferred depends on the type of device. When command chaining takes place, the subchannel is in the subchannel-and-device-active state from the time the frrst I/O operation is initiated at the device until the device presents channel-end status for the last I/O operation of the chain. The subchannel remains in the device-active state until the device presents the device-end status for the last I/O operation of the chain. Any unusual conditions cause command chaining to be suppressed and a primary interruption condition to be generated. The unusual conditions can be detected by either the channel subsystem or the device, and the device can provide the indications with channel end, control-unit end, or device end. When the channel subsystem is aware of the unusual condition by the time the channel-end status for the operation is accepted, the chain is ended as if the operation during which the condition occurred were the last operation of the chain. The device-end status is recognized as a secondary interruption condition whether presented together with the channel-end status or separately. If the device presents unit check or unit exception together with either control-unit end or device end as status. which causes the channel subsystem to recognize the primary interruption condition, then the subchannel-and-device-active state of the subchannel is terminated, and the sub channel is made status-pending with primary, secondary, and alert status. Intermediate status may also be indicated if an intermediate interruption condition previously existed at the subchannel for the initial-statusinterruption condition or the PCI condition and that condition still remains pending at the subchannel. The channel-end status which was presented to the channel subsystem previously when command chaining was signaled is not made available to the program. Channel-Path-Reset Function Subsequent to the execution of RESET CHANNEL PATH, the channel-path-reset function is performed. Perforrp.ance of the function consists in: ( 1) issuing the reset signal on the designated channel path and (2) causing a channel report to be made pending, indicating completion of the channel-path-reset function. Channel-Path-Reset-Function Signaling The channel subsystem issues the reset signal on the designated channel path. As part of this operation, the'following actions are taken: 1. All internal indications associated with control unit busy, device busy, and allegiance conditions for the designated channel path are reset. Chapter 15. Basic I/O Functions 15-43 These indications are reset at all subchannels that have access to the designated channel path. The reset function has no other effect on subchannels, including those having I/O· operations in progress. 2. If the channel path fails to respond properly to the reset signal (see the section "I/O-System Reset" on page 17-6, for a detailed description) or, because of a malfunction, the reset signal could not be issued, the channel path is made physically not available at each applicable subchannel. 3. If an I/O operation is in progress at the device and the device is actively communicating on the channel path in the execution of that I/O operation when the reset signal is received on that channel path, the I/O operation is reset, and the control unit and device immediately terminate current communication with the channel subsystem. (To avoid possible misinterpretation of unsolicited device-end status, programming measures can be taken as described in programming note 2.) 4. If an I/O operation is in progress in multipath mode at the device and the device is not currently communicating over the channel path in execution of that I/O operation when the reset signal is received, then the I/O operation mayor may not be reset depending on whether another ch~el path is available for selection in the same multipath group for the device. If there is at least one other channel path in the multipath group for the device that is available for selection, the I/O operation is not reset. However, the channel path on which the system reset is received is removed from the current set of channel paths that form the multipath group. If the channel path on which the reset signal is received is either the only channel path of a multipath group or the device is operating in single-path mode, the I/O operation is reset. 5. The channel-path-reset function causes I/O operations to be terminated at the device as described above; however, I/O operations are never terminated at the subchannel by the channel-path-reset function. If an I/O operation is in progress at the subchannel and the channel path designated for the perform~ ance of the channel-path-reset function is being used for that I/O operation, the subchannel mayor may not accurately reflect the progress of the I/O operation up to that instant. The subchannel 15-44 ESA/370 Principles of Operation remains in the state that exists at the time the channel-path-reset function is performed until the state is changed because of some action taken by the program or by the device. Channel-Path-Reset Function-Completion Signaling Mter the reset signal has been issued and an· attempt has been made to issue the reset signal, or after it has been determined that the reset signal cannot be issued, the channel-path-reset function is completed. (See the section "Reset Signal" on page 17-6.) As a result of the channel-path-reset function being performed, a channel report is made pending (see the section "Channel-Subsystem Recovery" on page 17-13) to report the results. If the channel path responds properly to the system-reset signal, the channel report indicates that the channel path has been initialized and is physically available for use. If the reset signal was issued but either the channel path failed to respond properly or the channel path was already not physically available at each sub channel having access to the channel path, the channel report indicates that the channel path has been initialized but is not physically available for use. If, because of a malfunction or because the designated channel path is not in the configuration, the reset signal could not be issued, the channel report indicates that. the channel path has not been initialized and is not physically available for use. Programming Notes: I. If an I/O operation is in progress in multipath mode when the channel-path-reset function is performed on a channel path of the multipath group, it is possible for the I/O operation to be continued on a remaining channel path of the group. 2. When the performance of the channel-pathreset function causes the I/O operation at the device to be reset, unsolicited device-end status presented by the device, if any, may be erroneously interpreted_ by the channel subsystem to be chaining status and thus cause the channel subsystem to continue the chain of commands. If this situation occurs, the device-end status is not made available to the program and the device is selected again by the channel subsystem; however, the device may interpret the initiation sequence as the beginning of a new channel program instead of command chaining. This possibility can be avoided by executing CLEAR SUBCHANNEL or HALT SUBCHANNEL, designating the affected subchannels, prior to executing RESET CHANNEL PATH. 3. Execution of the channel-path-reset function may, on some models, cause overruns to occur on other channel paths. 4. Even though reset is signaled on the designated channel path, allegiances to that channel path by one or more devices may not have been reset because of a malfunction at a control unit or a malfunction at the physical channel path to the control unit. Chapter 15. Basic I/O Functions 15-45-- Chapter 16. 1/0 Interruptions Interruption Conditions . . . . . . . . Intermediate Interruption Condition Primary Interruption Condition Secondary Interruption Condition Alert Interruption Condition Priority of Interruptions Interruption Action . . . . . . Interruption-Response Block Subchannel-Status Word Subchannel Key Suspend Control (S) .. Extended-Status-Word Format (L) Deferred Condition Code (CC) Format (F) . . . . . . . . . . . . . Prefetch (P) . . . . . . . . . . . . . Initial-Status-Interruption Control (I) Address-Limit-Checking Control (A) Suppress-Suspended Interruption (U) Subchannel-Control Field Zero Condition Code (Z) Extended Control (E) Path Not Operational (N) Function Control (FC) Activity Control (AC) Status Control (SC) CCW-Address Field Device-Status Field 16-2 16-4 16-4 16-4 16-4 16-5 16-5 16-6 16-6 16-8 16-8 16-8 16-8 16-10 16-11 16-11 16-11 16-11 16-11 16-11 16-11 16-12 16-12 16-13 16-16 16-18 16-23 When an I/O operation or sequence of I/O operations initiated by the execution of START SUBCHANNEL is ended, the channel subsystem and the device generate status conditions. The generation of these conditions can be brought to the attention of the program by means of an I/O interruption or by means of the execution of the TEST PENDING INTERRUPTION instruction. TEST PENDING INTERRUPTION instruction or the TEST PENDING ZONE INTERRUPTION instruction. (During certain abnormal situations, these conditions can be brought to the attention of the program by means of a machine-check interruption. See the section "Channel-Subsystem Recovery" on page 17-13 for details.) The status conditions, as well as an address and a count indicating the extent of the operation sequence, are presented to the program in the form of a subchannel-status word (scsw). The scsw is stored in an interruption-response 16-23 16-23 16-24 16-25 16-25 16-26 I 16-26 ' 16-27 16-28 16-28 16-28 16-29 16-30 16-30 16-31 16-32 16-33 16-33 16-36 16-36 16-36 16-40 16-40 16-40 16-41 16-42 16-43 Attention Status Modifier Control-Unit End Busy Channel End Device End Unit Check Unit Exception Subchannel-Status Field Program-Controlled Interruption Incorrect Length Program Check ... Protection Check .. Channel-Data Check Channel-Control Check Interface-Control Check Chaining Check Count Field . . . . . . . . Extended-Status Word ... . Extended-Status Format 0 Subchannel Logout Extended-Report Word Failing-Storage Address Extended-Status Format 1 Extended-Status Format 2 Extended-Status Format 3 Extended-Control Word ... block (IRB) CHANNEL. during the execution of TEST SUB- Normally an I/O operation is in execution until the device signals pritnary interruption status. Primary interruption status can be signaled during initiation of an I/O operation, or later. An I/O operation can be terminated by the channel subsystem performing a clear or halt function when it detects an equipment malfunction, a program check, a chaining check, a protection check, or an incorrect-length condition, or by performing a clear, halt, or channel-path-reset function as a result of the execution of CLEAR SUBCHANNEL, HALT SUBCHANNEL, or RESET CHANNEL PATH, respectively. I/O interruptions provide a means for the CPU to change its state in response to conditions that occur at I/O devices or subchannels. These conditions can be caused by the program, by the channel subsystem, or by an external event at the device. Chapter 16. I/O Interruptions 16-1 Interruption Conditions The conditions causing requests for I/O interruptions to be initiated are called I/o-interruption conditions. When an interruption condition is recognized by the channel subsystem, it is indicated at the appropriate sub channel. The subchannel is then said to be status-pending. The subchannel becoming status-pending causes the channel subsystem to generate an I/o-interruption request. An I/o-interruption request can be brought to the attention of the program only once. An I/o-interruption request remains pending until it is accepted by a CPU in the configuration, is withdrawn by the channel subsystem, or is cleared by means of the execution of TEST PENDING INTERRUPTION, TEST PENDING ZONE INTERRUPTION, TEST SUBCHANNEL, or CLEAR SUBCHANNEL, or by means of subsystem reset. When a CPU accepts an interruption request and stores the associated interruption code, the interruption request is cleared. Alternatively, an I/o-interruption request can be cleared by means of the execution of TEST PENDING INTERRUPTION. TEST PENDING INTERRUPTION or TEST PENDING ZONE INTERRUPTION. In all cases, the sub channel remains status-pending until the associated interruption condition is cleared when TEST SUBCHANNEL is executed or when the sub channel is reset. An I/o-interruption condition is normally cleared by means of the execution of TEST SUBCHANNEL. If TEST SUBCHANNEL is executed, designating a sub channel that has an I/o-interruption request pending, both the interruption request and the interruption condition at the subchannel are cleared. The interruption request and the interruption condition can also be cleared by CLEAR SUBCHANNEL. A device-end status condition generated by the I/O device and presented following the conclusion of the last I/O operation of a start function is reset at the subchannel by the channel subsystem without generating an I/o-interruption condition or I/o-interruption request if the subchannel is currently start-pending and if the status contains device end either alone or accompanied by control-unit end. If any other status bits accompany the device-end status bit, then the channel subsystem generates an I/o-interruption request with deferred condition code 1 indicated. 16-2 ESA/370 Principles of Operation When an I/O operation is terminated because of an unusual condition detected by the channel subsystem during the command initiation sequence, status describing the interruption condition is placed at the subchannel, causing it to become status-pending. If the unusual condition is detected by the device, the device-status field of the associated scsw identifies the condition. When command chaining takes place, the generation of status by the device does not cause an interruption, and the status is not made available to . the program. When the channel subsystem detects· any of the following interruption conditions, it initiates a request for an I/O interruption without necessarily communicating with, or having received the status byte from, the device: • A programming error associated with the contents of the ORB passed to the subchannel by the previous execution of START SUBCHANNEL • A valid suspend flag in the ftrst ccw fetched that initiates channel-program execution for either START SUBCHANNEL or RESUME SUBCHANNEL, and suppress suspended interruption not specified in the 0 RB • A progratnming error associated with the frrst ccw or frrst IDAW These interruption conditions from the subchannel, except for the suspended condition, can be accompanied by other subchannel-status indications, but the device-status indications are all stored as zeros. The channel subsystem issues the clear signal to the device when status containing unit check is presented to a subchannel that is disabled or when the device is not associated with any subchannel. However, if the presented status does not contain unit check, the status is accepted by the channel subsystem and discarded without causing the subchannel to become status-pending. An interruption condition caused by the device may be accompanied by multiple device-status conditions. Further, more than one interruption condition associated with the same device can be accepted by the channel subsystem without an intervening I/O interruption. As an example, when the channel-end condition is not cleared at the device by the time device end is generated, both conditions may be cleared at the device concurrently and indicated in the scsw together. Altema- tively, channel-end status may have been previously accepted at the subchannel, and an I/O interruption may have occurred; however, the associated statuspending condition may not have been cleared by TEST SUBCHANNEL by the time device-end status was accepted at the subchannel. In this situation, the device-end status may be merged with the channel-end status without causing an additional I/O interruption. Whether an interruption condition may be merged at the subchannel with other existing interruption conditions depends upon whether the interruption condition is unsolicited or solicited. The sub channel and device status associated with an unsolicited interruption condition is never merged with that of any currently existing interruption condition. If the sub channel is currently status-pending, the unsolicited interruption condition is held in abeyance in either the channel subsystem or the device, as appropriate, until the status-pending condition has been cleared. Solicited Interruption Condition: A solicited inter- ruption condition is any interruption condition generated as a direct consequence of performing or attempting to perform a clear, halt, resume, or start function. Solicited interruption conditions include any interruption condition generated while the subchannel is either subchannel-and-device-active or device-active. The subchannel and device status associated with a solicited interruption condition may be merged at the subchannel with that of another currently existing solicited interruption condition. Figure 16-1 describes the interruption condition that results from any combination of bits in the status-control field of the scsw. Unsolicited Interruption Condition: An unsolicited interruption condition .is any interruption condition which is unrelated to the performance of a clear, halt, resume, or start function. An unsolicited interruption condition is identified at the subchannel as alert status. An· unsolicited interruption condition can be generated only when the subchannel is not device-active. Status-Control Field Alert Primary Secondary Intermediate Status-pending Resulting interruption condition Status-Control-Bit Combinations 1 1 1 1 1 1 1 1 1 1 1 1 S S 0 0 0 0 0 0 1 1 E S 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 S S - 1 1 S 0 0 0 1 1 1 1 1 1 S S S 0 0 0 0 0 1 1 1 0 1 1 1 1 S S - 0 0 0 1 1 S 0 0 0 0 1 S EXElanation: - Combination does not occur. E Unso 1i cited or solicited interruption condition. S Solicited interruption condition. 0 Indicates the bit stored as zero. 1 Indicates the bit stored as one. Figure 16-1. Interruption Condition for Status-Control-Bit Combinations Chapter 16. I/O Interruptions t 6-3 Intermediate Interruption Condition An intermediate interruption condition is a solicited interruption condition that indicates that an event for which the program had previously requested notification has occurred. An intermediate interruption condition is described by solicited subchannel status, the Z bit, the subchannel-suspended condition, or any combination of the three. An intermediate interruption condition can occur only after it has been requested by the program through the use of flags in the ORB or a ccw. Depending on the state of the sub channel , execution or suspension of the 1/0 operation continues, unaffected by the setting of the intermediate-status bit. An intermediate interruption condition can be indicated only together with one of the following indications: 1. Subchannel-active 2. Status-pending with primary status alone 3. Status-pending with primary status together with alert status or secondary status or both 4. Suspended If only the intermediate-status bit and the statuspending bit of the status-control field are ones during the execution of TEST SUBCHANNEL, the device-status field is zero. Primary Interruption Condition A primary interruption condition is a solicited interruption condition that indicates the performance of the start function is completed at the subchannel. A primary interruption condition is described by the scsw stored as a result of executing TEST SUBCHANNEL while the subchannel is status-pending with primary status. Once the primary interruption condition is indicated at the subchannel, the channel subsystem is no longer actively participating in the 1/0 operation by transferring commands or data. When a subchannel is 16-4 ESAj370 Principles of Operation status-pending with a primary interruption condition, execution of any of the following instructions results in the setting of a nonzero condition code: HALT SUBCHANNEL, RESUME SUBCHANNEL, MODIFY. SUBCHANNEL, and START SUBCHANNEL. Once the primary interruption condition is cleared by executing TEST SUBCHANNEL, the subchannel accepts the START SUBCHANNEL instruction. (See the section "Start Subchannel" on page 14-12.) Secondary Interruption Condition A secondary interruption condition is a solicited interruption condition that normally indicates the completion of an 1/0 operation at the device. A secondary interruption condition is also generated by the channel subsystem if the start function is terminated because a solicited alert interruption condition is recognized prior to initiating the frrst 1/0 operation at the device. A secondary interruption condition is described by the scsw stored as a result of executing TEST SUBCHANNEL while the sub channel is status-pending with secondary status. Once the channel subsystem has accepted status from the device that causes a secondary interruption condition to be recognized, the start function is completed at the device. Alert Interruption Condition An alert interruption condition is either a solicited interruption condition that indicates the occurrence of an unusual condition in a halt, resume, or start function or an unsolicited interruption condition that describes a condition unrelated to the performance of a halt, resume, or start function. An alert interruption condition is described by the scsw stored as a result of executing TEST SUBCHANNEL while the subchannel is status-pending with alert status. An alert interruption condition may be generated by either the channel subsystem or the device. Nonzero alert status is always brought to the attention of the program. Whenever the subchannel is idle and zero status is presented by the device, the status is discarded. Priority of Interruptions All requests fo'r an I/O interruptio'n are asynchro'nous to' any activity in any CPU, and interruptio'n requests asso'ciated with mo're than o'ne subchannel can exist at the same time. The prio'rity o'f interruptio'ns is co'ntro'lled by two' types o'f mechanisms -- o'ne establishes within the channel subsystem the prio'rity amo'ng interruptio'n requests fro'm subchannels asso'ciated with the same I/o-interruptio'n subclass, and another establishes within a given CPU the prio'rity amo'ng requests fro'm subchannels o'f different I/o-interruptio'n subclasses. The channel subsystem requests an I/O interruptio'n o'nly after it has established prio'rity amo'ng requests fro'm its subchannels. The co'nditio'ns resPo'nsible fo'r the requests are preserved at the subchannels until cleared by a CPU executing TEST SUBCHANNEL o'r CLEAR SUBCHANNEL o'r until I/o-system reset is perfo'rmed. The assignment o'f prio'rity amo'ng requests fo'r interruptio'n fro'm subchannels o'f the same I/o-interruptio'n subclass is in the o'rder that the need fo'r interruptio'n is reco'gnized by the channel subsystem. The o'rder o'f reco'gnitio'n by the channel subsystem is a functio'n o'f the type o'f interruptio'n co'nditio'n and the type o'f channel path. Fo'r the type o'f channel path used by the channel subsystem, the o'rder depends o'n the electrical Po'sitio'n o'f the device o'n the channel path to' which it is attached. A device's electrical Po'sitio'n o'n the I/O interface is no't related to' its device address. The assignment o'f prio'rity amo'ng requests fo'r interruptio'n fro'm subchannels o'f different l/o-interruptio'n subclasses is made by the CPU acco'rding to' the numerical value o'f the I/o-interruptio'n subclass co'des (with zero' having highest prio'rity), in Co'njunctio'n with the I/o-interruptio'n subclass mask in co'ntrol register 6. The numerical value o'f the I/o-interruptio'n subclass co'de is directly related to' the bit Po'sitio'n in the I/o-interruptio'n subclass mask in co'ntro'l register 6 o'f a CPU. If in any CPU an I/o-interruptio'n subclass-mask bit is zero', then all subchannels having an I/o-interruptio'n subclass co'de numerically equal to' the asso'ciated positio'n in the mask register are said to' be masked o'ff in the respective CPU. Therefo're, a CPU accepts the highest-prio'rity l/o-interruptio'n request fro'm a subchannel which has the Io'west-numbered I/o-interruption subcl~ss co'de that is no't masked o'ff by a corresPo'nding bit in co'ntro'l register 6 o'f that CPU. When the highest-priority interruptio'n request is accepted by a CPU, it is cleared So' that the interruptio'n request is no't accepted by any o'ther CPU in the co'nfiguratio'n. The prio'rity o'f interruptio'n handling can be mo'dified by executio'n o'f either TEST SUBCHANNEL o'r CLEAR SUBCHANNEL. When either o'f these instructio'ns is executed and the designated subchannel has an interruptio'n request pending, that interruptio'n request is cleared, witho'ut regard to' any previous established prio'rity. The relative prio'rity o'f the remaining interruptio'n requests is unchanged. Programming Notes: 1. The I/o-interruptio'n subclass mask is in co'ntro'l register 6, which has the follo'wing fo'rmat: Reserved e 8 31 2. Co'ntrol register 6 is set to' all zero's during initial CPU reset. Interruption Action An I/O interruptio'n can o'ccur o'nly when the I/o-interruptio'n subclass-mask bit asso'ciated with the subchannel is o'ne and the CPU is enabled fo'r I/O interruptio'ns. The interruptio'n o'ccurs at the co'mpletio'n o'f a unit o'f o'peratio'n (see the sectio'n "Po'int o'f Interruptio'n" in Chapter 5, "Pro'gram Executio'n"). If the channel subsystem establishes the prio'rity among requests fo'r interruptio'n fro'm subchannels while the CPU is disabled fo'r I/O interruptio'ns, the interruptio'n o'ccurs immediately after co'mpletio'n o'f the instructio'n enabling the CPU and befo're the next instructio'n is executed, pro'vided that the I/o-interruptio'n subclass-mask bit asso'ciated with the subchannel is o'ne. Alternatively, if the channel subsystem establishes the prio'rity amo'ng requests fo'r interruptio'n fro'm subchannels while the I/o-interruptio'n subclass-mask bit is zero' fo'r each subchannel which is status-pending, the interruptio'n o'ccurs immediately after co'mpletio'n o'f the instructio'n which sets at least o'ne o'f the I/o-interruptio'n subclass-mask bits to' o'ne, pro'vided that the CPU is also' enabled fo'r I/O interruptio'ns. This interruptio'n is asso'ciated with the highest-prio'rity I/o-interruptio'n request, as established by the CPU. Chapter 16. I/O Interruptions 16·5 If the channel subsystem has not established the priority among requests for interruption from the subchannels by the time the interruption is allowed, the interruption does not necessarily occur immediately after completion of the instruction enabling the CPU. A delay can occur regardless of how long the interruption condition has existed at the subchannel. The interruption causes the current psw to be stored as the old psw at reallocation 56 and causes the I/o-interruption code associated with the interruption to be stored at reallocations 184-191 of the CPU allowing the interruption. Subsequently, a new psw is loaded from real location 120, and processing resumes in the CPU state indicated by that psw. The subchannel causing the interruption is identified by the interruption code. The I/o-interruption code has the following format when it is stored: The interruption-response block (IRB) is the operand of TEST SUBCHANNEL. The two rightmost bits of the IRB address are zeros, designating the IRB on a word boundary. The IRB contains three the subchannel-status word, the major fields: extended-status word, and the extended-control word. The format of the IRB is as follows: Word e Subchannel-Status Word 1 2 3 4 5 Extended-Status Word 6 7 8 I Hex. Dec. B8 184 Subsystem-Identification Word BC 188 Interruption Parameter e 31 Bits 2-4 of the interruption-identification word contain a value in the range 0-7 that specifies the interruption-subclass code (ISC) associated with the subchannel for which the pending interruption request is cleared. Bits 8-15 of the interruption-identification word contain a value in the range 0-255 specifying the zone number associated with the subchannel for which the pending interruption request is cleared. While a CPU is accepting an interruption request, no other CPU can accept an interruption request from a subchannel of the same I/o-interruption subclass. However, other CPUs may accept a pending interruption request from a subchannel of a different I/o.,interruption subclass. Mter the interruption has occurred, other CPus can accept a pending interruption request from a subchannel of the same I/o-interruption subclass, if any remain. Programming Note: The I/o-interruption subclass code for all subchannels is set to zero by I/o-system reset. It may be set to any of the values 0-7 by executing MODIFY SUBCHANNEL. (The operation of the instruction is described in the section "Modify Subchannel" on page 14-6.) 16-6 Interruption-Response Block ESAj370 Principles of Operation Extended-Control Word I 151L--_ _I The length of the subchannel-status and extendedstatus words is 12 bytes and 20 bytes, respectively. The length of the extended-control word is 32 bytes. When the extended-control bit (bit 14, word 0) of the scsw is zero, words 8-15 of the interruption-response block mayor may not be stored. Subchannel-Status Word The subchannel-status word (scsw) provides to the program indications describing the status of a subchannel and its associated device. If performance of a halt, resume, or start function has occurred, the scsw may describe the conditions under which the operation was concluded. The scsw is stored when TEST SUBCHANNEL is executed and the designated subchannel is operational. The scsw is placed in words 0-2 of the IRB that is designated as the TEST SUBCHANNEL operand. When STORE SUBCHANNEL is executed, the scsw is stored in words 7-9 of the subchannelinformation block (described in the section "Subchannel-Information Block" on page 15-1). Figure 16-2 on page 16-7 shows the format of the scsw and summarizes its contents. Word o Key SC AC CCW Address 1 2 Device Status 4 Word 0 0-3 4 5 6-7 8 9 10 11 12 13 14 15 16 17-19 20-26 27-31 Word 1 0-31 Word 2 0-7 8-15 16-31 Sch Status 8 Count 16 20 27 31 Subchannel key Suspend control (S) ESW Format (L) Deferred condition code (CC) Format (F) Prefetch (P) Initial-status interruption control (I) Address-l imi t-checki ng control (A) Suppress-suspended interruption (U) Zero condition code (Z) Extended control (E) Path not operat i ona 1 (N) Reserved (0) Functi on control (FC) (bit 17, start function; bit 18, halt function; bit 19, clear function) Activity control (AC) (bit 20, resume-pending; bit 21, start-pending; bit 22, halt-pending; bit 23, clear-pending; bit 24, subchannel-active; bit 25, device-active; bit 26. suspended) Status control (SC) (bit 27, alert status; bit 28, intermediate status; bit 29, primary status; bit 30, secondary status; bit 31, status-pending) CCW address Device status (bit 0, attention; bit 1, status modifier; bit 2, control-unit end; bit 3, busy; bit 4, channel end; bit 5, device end; bit 6, unit check; bit 7, unit exception) Subchannel status (Sch Status) (bit 8, program-controlled interruption; bit 9, incorrect length; bit 10, program check; bit 11, protection check; bit 12, channel-data check; bit 13, channel-control check; bit 14, interface-control check; bit 15, chaining check) Count Figure 16-2. SCSW Format Chapter 16. I/O Interruptions 16-7 The contents of the subchannel-status word (scsw) depend on the state of the subchannel when the scsw is stored. Depending on the state of the subchannel and the device, the specific fields of the scsw may contain (I) information pertaining to the last operation, (2) information unrelated to the execution of an operation, (3) zeros, or (4) a value of no meaning. The following descriptions indicate when an scsw field contains meaningful information. Subchannel Key When the start-function bit (bit 17 of word 0) is one, bits 0-3 of word 0 contain the access key used during performance of the associated start function. These bits are identical with the key specified in the ORB (bits 0-3 of word 1). The subchannel key is meaningful only when the start-function bit (bit 17 of word 0) is one. Suspend Control (S) When the start-function bit (bit 17 of word 0) is one, bit 4 of word 0, when one, indicates that the suspend function can be initiated at the subchannel. Bit 4 is meaningful only when bit 17 is one. If bit 17 is one and bit 4 is one, channel-program exe. cution can be suspended if the channel subsystem recognizes a valid s flag which is set to one in a ccw. If bit 4 is zero, channel-program execution cannot be suspended, and if an S flag set to one in a ccw is recognized, a program-check condition is recognized. Extended-Status-Word Format (L) When the status-pending bit (~it 31 of word 0) is one, bit 5 of word 0, when one, indicates that a format-O ESW has been stored. A format-O ESW is stored when an interruption condition containing one of the following indications is cleared by TEST SUBCHANNEL: Channel-data check Channel-control check Interface-control check Measurement-block-program check Measurement-block-data check Measurement-block-protection check The extended-status-word-format bit is meaningful whenever the subchannel is status-pending. The extended-status information that is used to fonn a format-O ESW is cleared at the subchannel by TEST SUBCHANNEL or CLEAR SUBCHANNEL. 16-8 ESA/370 Principles of Operation Deferred Condition Code (CC) When the start-function bit (bit 17 of word 0) is one and the status-pending bit (bit 31 of word 0) is also one, bits 6-7 of word 0 indicate the general reason that the subchannel was status-pending when TEST SUBCHANNEL or STORE SUBCHANNEL was executed. The deferred condition code is meaningful when the subchannel is status-pending with any combination of status and only when the start-function bit of the function-control field in the scsw is one. The meaning of the deferred condition code for each value when the subchannel is status-pending is given m Figure 16-3 on page 16-10. The deferred condition code, if not zero, is used to indicate whether conditions have been encountered that preclude the subchannel becoming subchanneland-device-active while the subchannel is either start-pending or suspended. Deferred Condition Code 0: A normal I/O inter- ruption has taken place. Deferred Condition Code 1: Status is present in the scsw that was presented by the associated device or generated by the channel subsystem subsequent to the setting of condition code 0 for START SUBCHANNEL or RESUME SUBCHANNEL. If only the alert-status bit and. the status-pending bit of the status-control field of the scsw are ones, the status present is not related to the execution of a channel program. If the intermediate-status bit, the primary-status bit, or both are ones, then the status is related to the execution of the channel program specified by the most recently/executed START SUBCHANNEL instruction or implied by the most recently executed RESUME SUBCHANNEL instruction. (See the section "Immediate Conclusion of I/O Operations" on page 15-42.) If the secondarystatus bit is one and the primary-status bit is zero, the status present is related to the channel program specified by the START SUBCHANNEL instruction or implied by the RESUME SUBCHANNEL instruction that preceded the most recently' executed START SUBCHANNEL instruction. Deferred Condition Code 2: This code does not occur and is reserved for future use. Deferred Condition Code 3: An attempted device selection has occurred, and the device appeared not operational on all of the channel paths that were available for selection of the device. A device appears not operational when it does not respond to a selection attempt by the channel subsystem. This occurs when the control unit is not provided in the system, when power is off in the control unit, or when the control unit has been logically switched off the channel path. The notoperational state is also indicated when the control unit is provided and is capable of attaching the device, but the device has not been installed and the control unit is not designed to recognize the device being selected as one of its attached devices. (See also the section "I/O Addressing" on page 13-5.) A deferred condition code 3 also can be set by the channel subsystem if no channel paths to the device are available for selection. (See Figure 16-3 on page 16-10.) Programming Notes: 1. If, during performance of a start function, the I/O device being selected is not installed or has been logically removed from the control unit, but the associated control unit is operational and the control unit recognizes the I/O device being selected as one of its I/O devices (for example, access mechanism 7 on the IBM 3830 Storage Control that has only access mechanisms 0-3 installed), the control unit, depending upon the model, either fails to rec- ognize the address of the I/O device or considers the I/O device to be not ready. In the former case, a path-not-operational condition is recognized, subject to the setting of the pathoperational mask. (See the section "PathOperational Mask (POM)" on page 15-6.) In the latter case, the not-ready condition is indicated when the control unit responds to the selection and indicates unit check whenever the not-ready state precludes successful initiation of the operation at the I/O device. In this case, unit-check status is indicated in the scsw, the subchannel becomes status-pending with primary, secondary, and alert status, and with deferred condition code 1 indicated. (See the section "Unit Check" on page 16-26.) Refer to the System Library publication for the control unit to determine how the condition is indicated. 2. The deferred condition code is 1 and the statuscontrol field contains the status-pending and intermediate-status bits or the status-pending, intermediate-status, and alert-status bits as ones when HALT SUBCHANNEL has been executed and the designated subchannel is suspended and status-pending with intermediate status. If the alert-status bit is one, then sub channellogout information was generated as a result of attempting to issue the halt signal to the device. Chapter 16. I/O Interruptions 16-9 Bit 6 Bit 7 Status Control 1 o o A IPS X AI P - X Meaning Normal I/O interruption A - PSX A- P - X - IPS X - I P- X - - PSX - - P- X o 1 Either an immediate operation, with chaining not specified, has ended normally, or the setting of som~ status condition precluding the initiation or resumption of a requested I/O operation at the device. A IPS X AI P - X A I - - X2 A - PSX A - P- X A - - SX A- - - X - I PS X - I P- X - I - - X2 - - PSX - - P- X - - - S X3 ____ X3 2 1 o Reserved Reserved 1 1 - - PSx - IPS x The device is not operational on any available path or, if a dedicated-allegiance condition exists, the device is not operational on the path to which the dedicated allegiance is owed. Explanation: 1 2 3 A I P S X - The allowed combinations of status-control-bit settings when the start-function bit is one in the function-control field. The condition is encountered after the execution of HALT SUBCHANNEL when the subchannel is currently suspended. The condition is encountered after the execution of HALT SUBCHANNEL when the subchannel is currently start-pending. . Alert status. Intermediate status. Primary status. Secondary status. Status-pending. Bit is zero. Figure 16-3. Deferred-Condition-Code Meaning for Status-Pendip.g Subchannel Format (F) When the start-function bit (bit 17 of word 0) is one, bit 8 of word 0 indicates the format of the ccws associated with an I/O operation. The format bit is meaningful only when bit 17 is one. If bit 8 of word 0 is zero, format-O ccws are indicated. If it is one, format-1 ccws are indicated. (See the 16-10 ESA/370- Principles of Operation section "Channel-Command Word" on page 15-23 for the description of the two CCW formats.) Prefetch (P) When the start-function bit (bit 17 of word 0) is one, bit 9 of word 0 indicates whether or not unlimited prefetching of CCws is allowed. The prefetch bit is meaningful only when bit 17 is one. If bit 9 is zero, prefetching of one ccw describing a data area is allowed during output-data-chaining operations and is not allowed during any other operations. If bit 9 is one, unlimited prefetching of ccws is allowed. dition whenever the subchannel is suspended during execution of the associated channel program. The suppress-suspended-interruption bit is meaningful only when bit 17 is one. Inltial-Status-Interruption Control (I) When the start-function bit (bit 17 of word 0) is one, bit 10 of word 0, when one, indicates that the channel subsystem is to generate an intermediate interruption condition if the subchannel becomes subchannel-active (see the section "Initial-StatusInterruption Control (I)" on page 15-21). Bit 10 of word 0, when zero, indicates that the subchannel becoming subchannel-active is not to cause an intermediate interruption condition to be generated. Zero Condition Code (Z) Bit 13 of word 0, when one, indicates that the subchannel has become subchannel-active and the channel subsystem has recognized an initial-statusinterruption condition at the subchannel. The z bit is meaningful only when the intermediate-status bit (bit 28 of word 0) and the start-function bit (bit 17 of word 0) are both ones. The program requests the intermediate interruption condition by means of the ORB. An 1/0 interruption that results from that request may be due to the channel subsystem performing either a start function or a resume function. (See the section "Zero Condition Code (Z)" for details of the indication given by the channel subsystem when the intermediate interruption condition is cleared by TEST SUBCHANNEL). Address-Llmlt-Checking Control (A) When the start-function bit (bit 17 of word 0) is one, bit 11 of word 0, when one, indicates that the channel subsystem has been requested by .the program to perform address-limit checking, subject to the setting of the limit mode at the subchannel (see the section "Address-Limit-Checking Control (A)" on page 15-22). The address-limit-checkingcontrol bit is meaningful only when bit 17 is one. Suppress-Suspended Interruption (U) When the start-function bit (bit 17 of word 0) is one, bit 12 of word 0, when one, indicates that the channel subsystem has been requested by the program to suppress the generation of a subchannel-suspended interruption condition when the subchannel is suspended (see the section "Suppress-Suspended-Interruption Control (U)" on page 15-22). When bit 12 is zero, the channel subsystem generates an intermediate interruption con- Subchannel-Control Field The following subchannel-control-information descriptions apply to the subchannel-control field (bits 13-31 of word 0) of the scsw. If the initial-status-interruption-control bit (bit 10, word 1 of the ORB) is one when START SUBCHANNEL is executed, then the subchannel becoming subchannel-active causes the subchannel to be made status-pending with intermediate status indicating the initial-status-interruption condition. The initial-status-interruption condition remains at the subchannel until the intermediate interruption condition is cleared by the execution of TEST SUBCHANNEL or CLEAR SUBCHANNEL. If the initialstatus-interruption-control bit of the ORB is zero when START SUBCHANNEL is executed, then the subchannel becoming subchannel-active does not cause an intermediate interruption condition to be generated, and the initial-status-interruption condition is not recognized. Extended Control (E) Bit 14 of word 0, when one, indicates that modeldependent information is stored in the extendedcontrol word (ECW). When bit 14 is zero, the contents of words 0-7 of the ECW, if stored, are unpredictable. The E bit is meaningful whenever the subchannel is status-pending with alert status either alone or together with primary status, secondary status, or both. Programming Note: During execution of TEST SUBCHANNEL, the storing of words 0-7 of the ECW is a model-dependent function subject to the setting of bit 14 as described above. Therefore, the program should always provide sufficient storage to accommodate the storing of a 64-byte IRB. Chapter 16. I/O Interruptions 16-11 Path Not Operational (N) Bit 15 of word 0, when one, indicates that the N condition has been recognized by the channel subsystem. The N condition, in turn, indicates that one or more path-not-operational conditions have been recognized. The channel subsystem recognizes a path-not-operational condition when, during an attempted device selection in order to perform a clear, halt, resume, or start function, the device associated with the subchannel appears not operational on a channel path that is operational for the subchannel. A channel path is operational for the subchannel if the associated device appeared operational on that channel path the last time the channel subsystem attempted device selection in order to perform a clear, halt, resume, or start function. A channel path is not operational for the subchannel if the associated device appeared not operational on that channel path the last time the channel subsystem attempted device selection in order to perform a clear, halt, resume, or start function. A device appears to be operational on a channel path when the device responds to an attempted device selection. The N bit is meaningful whenever the statuscontrol field contains one of the indications listed below, and at least one basic I/O function is also indicated at the subchannel: • Status-pending with any combination primary, secondary, or alert status of • Status-pending alone • Status-pending with intermediate status when the subchannel is also suspended The N condition is reset whenever the execution of TEST SUBCHANNEL results in the setting of condition code 0 and the above. N bit is meaningful as described indicated by storing the path-not-operational bit as a one during the execution of TEST S U BCHANNEL. When a path-not-operational condition has been recognized and the channelprogram execution subsequently becomes suspended, the path-not-operational condition does not remain pending if channel-program execution is subsequently resumed. Instead, the old indication is lost, and the path-notoperational indication, if any, pertains to the attempt by the channel subsystem to resume channel-program execution. Function Control (FC) The function-control field indicates the basic I/O functions that are indicated at the subchannel. This field may indicate the acceptance of as many as two functions. The function-control field is contained in bit positions 17-19 of the frrst word of the scs w. The function -control field is meaningful at an installed subchannel whenever the subchannel is valid (see the section "Device Number Valid (V)" on page 15-4). The function-control field contains all zeros whenever both the activity- and statuscontrol fields contain all zeros. The meaning of the individual bits is as follows: When one, bit 17 indicates that a start function has been requested and is either pending or in progress at the subchannel. A start function is requested by executing START SUBCHANNEL: A start function is indicated at the subchannel when condition code 0 is set during the execution of START SUBCHANNEL. The start function indication is cleared at the subchannel when TEST SUBCHANNEL is executed and the subchannel is either status-pending alone, or status-pending with any combination of alert, primary, or secondary status. The start function indication is also cleared at the subchannel during the execution of Start Function (Bit 17): CLEAR SUBCHANNEL. Notes: 1. A path-not-operational condition does not imply a malfunctioning channel path. A malfunctioning channel path causes the generation of an error indication, such as interface-control check. 2. When a path-not-operational condition has been recognized and the subchannel subsequently becomes status-pending with only intermediate status, the path-not-operational condition continues to be recognized until the subchannel becomes status-pending with primary status or becomes suspended and is 16-12 ESA/370 Principles of Operation Halt Function (Bit 18): When one, bit 18 indicates that a halt function has been requested and is either pending or in progress at the subchannel. A halt function is requested by executing HALT SUBCHANNEL. A halt function is indicated at the subchannel when condition code 0 is set for HALT SUBCHANNEL. The halt function indication is cleared at the subchannel when the next status-pending condition which occurs is cleared by execution of TEST SUBCHANNEL. The next status-pending condition depends on the state of the subchannel when HALT SUBCHANNEL is executed. If the subchannel is subchannel-active when HALT SUBCHANNEL is executed, then the next status-pending condition is status-pending with at least primary status indicated. If the subchannel is device-active when HALT SUBCHANNEL is executed, then the next status-pending condition is status-pending with at least secondary status indicated. If the subchannel is suspended and status-pending with intermediate status when HALT SUBCHANNEL is executed, then the next status-pending condition is status-pending with intermediate status. If the subchannel is idle when HALT SUBCHANNEL is executed, then the next status-pending condition is status-pending alone. The halt function indication is also cleared at the subchannel during the execution of CLEAR SUBCHANNEL. In normal operations, this function is indicated together with bit 17; that is, there is a start function either pending or in progress which is to be halted. Clear Function (Bit 19): When one, bit 19 indicates that a clear function has been requested and is either pending or in progress at the subchannel. A clear function is requested by executing CLEAR SUBCHANNEL. A clear function is indicated at the subchannel when condition code 0 is set for CLEAR SUBCHANNEL (see the section "Clear Subchannel" on page 14-4). The clear function indication is cleared at the subchannel when the resulting statuspending condition is cleared by TEST SUBCHANNEL. Activity Control (AC) The activity-control field is contained in bit positions 20-26 of the frrst word of the scsw. This field indicates the current progress of a basic I/O fu?ction previously accepted at the subchannel. By usmg the contents of this field, the program can determine the degree of completion of the basic I/O function. The activity-control field is meaningful at an installed subchannel whenever the subchannel is valid (see the section "Device Number Valid (V)" on page 15-4). However, if an IFCC or CCC condition is detected during the performance of a basic I/O function and that function is indicated as pending, I/O operations may 9r may not have been executed at the device. The activity-control bits are defmed as follows: Bit 20 21 22 23 24 25 26 Designation Resume-pending Start-pending Halt-pending Clear-pending Subchannel-active Device-active Suspended When an scsw is stored that has the status-pending bit of the status-control field zero and all zeros in the activity-control field, the subchannel is said to be idle or in the idle state. Note: All conditions that are represented by the bits in the function-control field and by the resumepending, start-pending, halt-pending, clear-pending, subchannel-active, and suspended bits in the activity-control field are reset at the subchannel when TEST SUBCHANNEL is executed and the subchannel (1) is status-pending alone, (2) is statusp~nding with primary status, (3) is status-pending WIth alert status, or (4) is status-pending with intermediate status and is also suspended. Resume-Pending (Bit 20): When one, bit 20 indicates that the subchannel is resume-pending. The channel subsystem mayor may not be in the process of performing the start function. The subchannel becomes resume-pending when condition code 0 is set for RESUME SUBCHANNEL. The point at which the sub channel is no longer resumepending is a function of the subchannel state existing when the resume-pending condition is recognized and the state of the device if channelprogram execution is resumed. If the subchannel is in the suspended state when the resume-pending condition is recognized, the ccw that caused the suspension is refetched the . ' settmg of the suspend flag is examined, and one of the following actions is taken by the channel subsystem: 1. If the ccw suspend flag is one, the device is not selected, the subchannel is no longer resume-pending, and channel-program execution remains suspended. 2. If the ccw suspend flag is zero, the channel subsystem attempts to resume channel-program execution by performing a modified start function. The resumption of channel-program execution appears to the device as the initiation of a new channel-program execution. The resume function causes the channel subsystem to execute the path-management operation as if a new start function were being initiated, using the 0 RB parameters previously passed to the subchannel by START SUBCHANNEL with the exception that the channel-program address is the address of the ccw that previously caused suspension of channel-program execution. Th~ subchannel remains resume-pending when, durmg the performance of the start function , Chapter 16. I/O Interruptions 16-13 the channel subsystem (I) determines that it is not possible to attempt to initiate the 1/0 operation for the frrst command, (2) determines that an attempt to initiate the 1/0 operation for the frrst command does not result in the command being accepted, or (3) detects an IFCC or CCC condition and is unable to determine whether the frrst command has been accepted. (See the section "Start Function and Resume Function" on page 15-17.) The subchannel is no longer resume-pending when any of the following events occurs: a. While performing the start function, the subchannel becomes subchannel-anddevice-active or device-active only, or the frrst command is accepted with channel-end and device-end initial status and the ccw does not specify command chaining. b. CLEAR SUBCHANNEL c. TEST SUBCHANNEL d. is executed. clears any combination of primary, secondary, and alert status or clears the status-pending condition alone. SUBCHANNEL clears intermediate status while the subchannel is suspended. TEST If the subchannel is not in the suspended state when the resume-pending condition is recognized, the ccw suspend flag of the most recently fetched ccw, if any, is examined and one of the following actions is taken by the channel subsystem: 3. If a ccw has not been fetched or the suspend flag of the most recently fetched ccw is zero, the subchannel is no longer resume-pending, and the resume function is not performed. 4. If the suspend flag of the most recently fetched ccw is one, the subchannel is no longer resume-pending, and the ccw is refetched. The subchannel proceeds with channel-program execution if the suspend flag of the refetched ccw is zero. The subchannel suspends channel-program execution if the suspend flag of the refetched ccw is one. Some models recognize a resume-pending condition only after a ccw having a valid S flag set to one is fetched. Therefore, if a subchannel is resumepending and, during execution of the channel program, no ccw is fetched that has a valid S flag set to one, the subchannel remains resume-pending until the primary interruption condition is cleared by TEST SUBCHANNEL. Start-Pending (Bit 21): When one, bit 21 indicates that the subchannel is start-pending. The channel subsystem mayor may not be in the process of performing the start function. The subchannel becomes start-pending when condition code 0 is set for START SUBCHANNEL. The subchannel remains start-pending when, during the performance of the start function, the channel subsystem ( I) determines that it is not possible to attempt to initiate the 1/0 operation for the frrst command, (2) determines that an attempt to initiate the 1/0 operation for the frrst command does not result in the command being accepted, or (3) detects an IFCC or CCC condition and is unable to determine whether the frrst command has been accepted. (See the section "Start Function and Resume Function" on page 15-17.) The subchannel becomes no longer start-pending when any of the following occurs: I. While performing the start function, the subchannel becomes subchannel-and-device-active or device-active only, or the first command is accepted with channel-end and device-end initial status and the ccw does not specify command chaining. 2. The subchannel becomes suspended because of a valid suspend flag in the frrst ccw. 3. CLEAR SUBCHANNEL 4. TEST SUBCHANNEL is executed. clears any combination of primary, secondary, and alert status or clears the status-pending condition alone. Halt-Pending (Bit 22): When one,bit 22 indicates that the subchannel is halt-pending. The channel subsystem mayor may not be in the process of performing the halt function. The subchannel becomes halt-pending when condition code 0 is set for HALT SUBCHANNEL. The subchannel remains halt-pending when, during the performance of the halt function, the channel subsystem (I) determines that it is not possible to attempt to issue the halt signal to the device, (2) determines that the attempt to issue the halt signal to the device is not successful, or (3) detects an IFCC or ccc condition and is unable to determine whether the halt signal is issued to the device. (See the section "Halt Function" on page 15-14.) The subchannel is no longer halt-pending when any of the following occurs: 16-14 ESA/370 Principles of Operation 1. While performing the halt function, the channel subsystem determines that the halt signal has been issued to the device. 2. CLEAR SUBCHANNEL 3. TEST SUBCHANNEL 4. is executed. clears any combination of primary, secondary, and alert status or clears the status-pending condition alone. clears intermediate status while the subchannel is suspended. TEST .SUBCHANNEL Clear-Pending (Bit 23): When one, bit 23 indicates that the subchannel is clear-pending. The channel subsystem may. or may not be in the process of performing the clear function. The subchannel becomes clear-pending when condition code 0 is set for CLEAR SUBCHANNEL. The subchannel remains clear-pending when, during performance of the clear function, the channel subsystem ( 1) determines that it is not possible to attempt to issue the clear signal to the device, (2) determines that the attempt to issue the clear signal to the device is not successful, or (3) detects an IFCC or CCC condition and is unable to determine whether the clear signal is issued to the device. (See the section "Clear Function" on page 15-13.)· The subchannel is no longer clear-pending when either of the following occurs: 1. While performing the clear function, the channel subsystem determines that the clear signal has been issued to the device. 2. TEST SUBCHANNEL clears the status-pending condition alone. Subchannel-Actlve (Bit 24): When one, bit 24 indicates that the subchannel is subchannel-active. A subchannel is said to be subchannel-active when an I/O operation is currently in execution at the subchannel. The subchannel becomes subchannelactive when the ftrst command is accepted for any of the following initial-status combinations and the start function or resume function is not immediately concluded at the subchannel. (See the section "Immediate Conclusion of I/O Operations" on page 15-42.) 1. All zeros 2. Unit check, status modifier, and channel end when used to indicate command retry (delayed). (See the section "Command Retry" on page 15-41.) 3. Unit check, status modifier, channel end, and device end when used to indicate command retry (immediate). (See the section "Command Retry" on page 15-41.) 4. Channel end when the chain-command flag is one in the ccw 5. Channel end and device end when the chaincommand flag is one in the ccw 6. Channel end, device end, and status modifier when the chain-command flag is one in the ccw The subchannel is no longer subchannel-active when any of the following occurs: 1. The subchannel becomes suspended. 2. The subchannel becomes status-pending with primary status. 3. CLEAR SUBCHANNEL is executed. 4. The device appears not operational during performance of a halt function. The subchannel does not become subchannel-active during performance of the function specified by either a HALT SUBCHANNEL or a CLEAR SUBCHANNEL instruction. Device-Active (Bit 25): When one, bit 25 indicates that the subchannel is device-active. A subchannel is said to be device-active when an I/O operation is currently in progress at the associated device. The subchannel becomes device-active when the ftrst command is accepted for: 1. One of the combinations of initial status listed above in the section "Subchannel-Active (Bit 24)" 2. Initial status of channel end with neither busy nor device end, and command chaining is not specified in the ccw. (See the section "Immediate Conclusion of I/O Operations" on page 15-42.) The subchannel is no longer device-active when any of the following occurs: 1. The subchannel becomes suspended. 2. The subchannel becomes status-pending with secondary status. 3. CLEAR SUBCHANNEL is executed. 4. The device appears not operational during performance of a halt function. Chapter 16. I/O Interruptions 16-15 If the subchannel is not start-pending or if the status accepted from the device also describes an alert condition, the subchannel becomes statuspending with secondary status. Mter the status has been accepted from the device, the device is capable of accepting a command for executing a new I/O operation. If the subchannel is start-pending and the status is device end or device end with controlunit end, then the channel subsystem discards the status and performs the start function for the new channel program. (See the section "Start Function and Resume Function" on page 15-17) In this situation, the subchannel does not become statuspending with the secondary interruption condition, and the status is not made available to the program. The subchannel does not become device-active during performance of the functions specified by either a HALT SUBCHANNEL or a CLEAR SUBCHANNEL instruction. Suspended (Bit 26): When one, bit 26 indicates that the subchannel is suspended. A subchanne1 is said to be suspended when channel-program execution is currently suspended. The subchannel becomes suspended as part of the suspend function. (See the section "Suspension of Channel-Program Execution" on page 15-32.) The subchannel is no longer suspended when any of the following occurs: 1. As part of the resume function following the execution of RESUME SUBCHANNEL when the subchannel becomes subchannel-and-deviceactive or device-active only, or the frrst command is accepted for channel-end and device-end initial status, with or without status modifier, and the ccw does not specify command. chaining. 2. CLEAR SUBCHANNEL 3. TEST SUBCHANNEL 4. TEST SUBCHANNEL is executed. clears any combination of primary, secondary, and alert status or clears the status-pending condition alone. clears intermediate status while the halt function is specified. Programming Note: When an scsw is stored by STORE SUBCHANNEL or TEST SUBCHANNEL following CLEAR SUBCHANNEL but prior to the subchannel becoming status-pending, and the subchannel-active bit (bit 24 of word 0) is stored as 0, this does not mean that data transfer has stopped for the device. The program cannot determine 16-16 ESAj370 Principles of Operation whether data transfer has stopped until the subchannel becomes status-pending as a result of performing the clear function. Status Control (SC) The status-control field is contained in bit positions 27-31 of the frrst word of the scsw. This field provides the program with a summary-level indication of the interruption condition described by either subchannel or device status, the Z bit, or, in the case of the subchannel-suspended interruption, the suspended bit (bit 26). More than one summary indication may be signaled as a result of existing conditions at the subchannel. Whenever the subchannel is enabled (see the section "Enabled (E)" on page 15-2) and at least bit 31 is one, the subchannel is said to be status-pending. Whenever the subchanne1 is disabled, the subchannel is not made status-pending. Bit 31 of scsw word 0 is meaningful at an installed sub channel whenever the subchannel is valid (see section "Device Number Valid (V)" on page 15-4); bits 27-30 are meaningful when bit 31 is one. The status-control bits are defmed as follows: When one (and when the status-pending bit is also one), bit 27 indicates an alert interruption condition exists. In such a case, the subchanne1 is said to be status-pending with alert status. An alert interruption condition is recognized when alert status is present at the subchannel. Alert status may be subchannel status or device status. Alert status is status generated by either the channel subsystem or the device under any of the following conditions: Alert Status (Bit 21): • The subchannel is idle (activity-control bits 20-26 and status-control bit 31 are zeros). • The subchannel is start-pending, and the status condition precludes initiation of the I/O operation. • The subchannel is subchannel-and-deviceactive, and the status condition has suppressed command. chaining or would have suppressed command chaining if chaining had been specified (see the section "Chaining" on page 15-26). • The subchannel is subchannel-and-deviceactive, command chaining is not specified, execution of the channel program has just been concluded, and the status presented by the device is attempting to alter the sequential execution of commands (see the section "Status Modifier" on page 16-23). • The subchannel is device-active only, and the status presented by the device is other than device end, control-unit end, or device end and control-unit end. • The subchannel is suspended (bit 26 is one). If the subchannel is start~pending when an alert interruption condition is recognized, the subchannel becomes status-pending with alert status, deferred condition code 1 is set, the start-pending bit remains one, and execution of the pending 1/0 operation is not initiated. When TEST SUBCHANNEL is executed and stores an scsw with the alert-status bit and the statuspending bit as ones in the IRB, the alert interruption condition is cleared at the subchannel. The alert interruption condition is also cleared during execution of CLEAR SUBCHANNEL. Whenever alert status is present at the subchannel, it is brought to the~ attention of the program. Examples of alert status include attention, device end (which signals a transition from the not-ready to the ready state), incorrect length, program check, and unit check. Intermediate Status (Bit 28): When one (and when the status-pending bit is also one), bit 28 indicates an intermediate interruption condition exists. In such a case, the subchannel is said to be status-pending with intermediate status. Intermediate status can be indicated when the z bit (of the subchannel-control field), the suspended bit (of the activity-control field), or the PCI bit (of the subchannel-status field) is one. When the initial-status-interruption-control bit is one in the ORB, the subchannel becomes statuspending with intermediate status (the z bit indicated) only after initial status is received for the frrst ccw of the channel program and the subchannel is subchannel-active. If the subchannel does not become subchannel-active, the Z condition is not generated. When suspend control is specified and the generation of an intermediate interruption condition due to suspension is not suppressed in the ORB, then the subchannel can become status-pending with intermediate status due to suspension if a ccw becomes current that contains the suspend flag set to one. When the suspend flag is specified in the " frrst ccw of a channel program, channel-program execution is suspended and the subchannel becomes status-pending with intermediate status (the suspended bit indicated) before the command in the frrst ccw is transferred to the device. When the suspend flag is specified in a ccw fetched during command chaining, channel-program execution is suspended and the subchannel becomes status-pending with intermediate status (the suspended bit indicated) only after execution of the preceding ccw is complete. When the PCI flag is specified in a ccw, the gen~r ation of an intermediate interruption condition due to PCI depends on whether the ccw is the frrst ccw of the channel program. When the PCI flag is specified in the frrst ccw of a channel program, the subchannel becomes status-pending with intermediate status (the PCI bit indicated) only after initial ,status is received for the first ccw of the channel program indicating the command has been accepted. When the PCI flag is specified in a ccw fetched while chaining, the subchannel becomes status-pending with intermediate status (the PCI bit indicated) only after execution of the preceding ccw is complete. If chaining occurs before an interruption condition containing PCI is cleared by TEST SUBCHANNEL, the condition is carried over to the next ccw. This carryover occurs during both data and command chaining, and, in either case, the condition is propagated through the transfer-inchannel command. If the subchannel is status-pending with intermediate status when HALT SUBCHANNEL is executed, the intermediate interruption condition remains at the subchannel, but the interruption request, if any, is withdrawn, and the subchannel becomes no longer status-pending. The subchannel remains no longer status-pending until performance of the halt function has ended. The subchannel then becomes status-pending with intermediate status indicated (possibly together with any combination of primary, secondary, and alert status). When TEST SUBCHANNEL is executed and stores an scsw with the intermediate-status bit and the status-pending bit as ones in the IRB, the intermediate interruption condition is cleared at the subchannel. The intermediate interruption condition is also cleared at the subchannel during the execution of CLEAR SUBCHANNEL. Primary status (Bit 29): When one (and when the status-pending bit is also one), bit 29 indicates a primary interruption condition exists. In such a case, the subchannel is said to be status-pending with primary status. A primary interruption condiChapter 16. I/O Interruptions 16-17 tion is a solicited interruption condition that indicates the completion of the start function at the subchannel. The primary interruption condition is described by the scsw stored. When an I/O operation is terminated by HALT SUBCHANNEL but the halt signal is not issued to the device because the device appeared not operational, the subchannel is made status-pending with primary status (and secondary status) with both the subchannel-status field and the device-status field set to zero. When TEST SUBCHANNEL is executed and stores an scsw with the primary-status bit and the statuspending bit as ones in the IRB, the primary interruption condition is cleared at the subchannel. The primary interruption condition is also cleared at the subchannel during the execution of CLEAR SUBCHANNEL. Secondary Status (Bit 30): When one (and when the status-pending bit is also one), bit 30 indicates a secondary interruption condition exists. In such a case, the sub channel is said to be status-pending with secondary status. A secondary interruption condition is a solicited interruption condition that normally indicates the completion of the I/O operation at the device. The secondary interruption condition is described by the scsw stored. I/O operation is terminated by HALT SUBCHANNEL but the halt signal is not issued to the When an device because the device appeared not operational, the subchannel is made status-pending with secondary status (and primary status if the subchannel is also subchannel-active) with zeros for subchannel and device status. When TEST SUBCHANNEL is executed and stores an scsw with the secondary-status bit as one in the I RB, the secondary interruption condition is cleared at the subchannel. The secondary interruption condition is also cleared at the subchannel during execution of CLEARSUBCHANNEL. Status-Pending (Bit 31): When one, bit 31 indicates that the subchannel is status-pending and that information describing the cause of the interruption condition is available to the program. The subchannel becomes status-pending whenever intermediate, primary, secondary, or alert status is generated. When HALT SUBCHANNEL is executed, designating a subchannel that is idle, the subchannel becomes status-pending subsequent to per- 16-18 ESA/370 Principles of Operation formance of the halt function to notify the program that the halt function has been completed. When TEST SUBCHANNEL is executed, thus storing an scsw with the status-pending bit as one in the IRB, the status-pending condition is cleared at the subchannel. The status-pending condition is also cleared at the subchannel during the execution of CLEAR SUBCHANNEL. When CLEAR SUBCHANNEL is executed, and the designated subchannel is operational' the subchannel becomes status-pending subsequent to performance of the clear function to notify the program that the clear function has been completed. Note: The status-pending bit, in conjunction with the remaining bits of the status-control field, indicates the type of status condition. For example, if bits 29 and 31 are ones, the subchannel is statuspending with primary status. Alternatively, if only bit 31 is one, then the subchannel is said to be status-pending or status-pending alone. If only bit 31 is one in the status-control field, the settings of all bits in the subchannel- and device-status fields are unpredictable. If bit 31 is not one, then the remaining bits of the status-control field are not meaningful. CCW-Address Field Bits 1-31 of word 1 form an absolute address. The address indicated is a function of the subchannel state when the scsw is stored, as indicated in Figure 16-4 on page 16-19. When the subchannelstatus field indicates channel-control check, channel-data check, or interface-control check, the ccw-address field is usable for recovery purposes if the ccw-address field-validity flag in the ESW is one. Programming Note: When a ccw address, either detected in the channel-program address (see the "Channel-Program Address" on section page 15-23) or generated during chaining, would cause the channel subsystem to fetch a ccw from a location greater than 16,777,215 while format-O ccws are specified for the operation, the invalid address is stored in the ccw-address field of the scsw without truncation. If the invalid address causes the channel subsystem, while chaining, to fetch a ccw from a location greater than 2,147,483,647 while in 31-bit addressing mode, the rightmost 31 bits of the invalid address are stored in the ccw-address field. Subchannel State 1 Start-pending (UUUU0/AIPSX)3 CCW Address 2 Unpredictable Start-pending and device-active (UUUU0/AIPSX)3 Unpredictable Subchannel-and-device-active (UUUU0/AIPSX)3 Device-active only (UUUU0/AIPSX) Suspended (YYYYY/AIPSX)3 Unpredictable Unpredictable See note 1 Channel-program address + 8 Status-pending (l0001/AIPSX) because of unsolicited alert status from the device while the subchannel was start-pending 3 Status-pending (0Yll1/AIPSX) because the device appeared not operational on all paths3 Channel-program address + 8 Status-pending (10011/AIPSX) because of solicited alert status from the device while the subchannel was start-pending and deviceactive 3 Channel-program address + 8 Status-pending (10111/AIPSX) because of solicited alert status generated by the channel subsystem while the subchannel was start-pending 3 or start-pending and deviceactive 3 See note 2 • Status-pending (01001/AIPSX) for the program- CCW + 8 of the CCW that contained the last recognized PCI, or 8 higher than controlled-interruption condition while the subchannel was subchannel-and-device active 3 a CCW which has subsequently become current Status-pending (81881/AIPSX) for the initialstatus-interruption condition while the subchannel was subchannel-and-device active 3 CCW + 8 of the CCW causing the intermediate interruption condition, or a CCW which has subsequently become current Status-pending (lYIYl/AIPSX); termination occurred because of program check caused by one of the following conditions: 3 Bit 24, word 1 of ORB set to one; incorrect-length-indication-suppression facility not installed Channel-program address + 8 Unused bits in ORB not set to zeros Channel-program address + 8 Invalid CCW-address specification in transfer in channel (TIC) Address of TIC + 8 Invalid CCW-address specification in the channel-program address in the ORB Channel-program address + 84 Figure 16-4 (Part 1 of 4). CCW Address as Function of Subchannel State Chapter 16. I/O Interruptions 16-19 Subchannel State 1 CCW Address 2 Invalid CCW address in TIC Address of TIC + 8 Invalid CCW address in the channel-program address in the ORB Channel-program address Invalid CCW address while chaining Invalid CCW address + 8 Invalid command code Address of invalid CCW + 85 Invalid count Address of invalid CCW + 85 Invalid IDAW-address specification Address of invalid CCW + 85 Invalid IDAW address in a CCW Address of invalid CCW Invalid IDAW address while sequentially fetching IDAWs Address of currert CCW + 8 Invalid data-address specification, format 1 Address of invalid CCW + 85 Invalid data address in a CCW Address of invalid CCW + 85 Invalid data address while sequentially accessing storage Address of current CCW + 8 Invalid data address in IDAW Address of current CCW + 8 Invalid IDAW specification Address of current CCW + 8 84 + + 85 Invalid CCW, format 0 or 1, for a CCW other Address of invalid CCW + 85 than a TIC Invalid suspend flag -- CCW fetched during data chaining has suspend flag set to one Address of invalid CCW + 8 Invalid suspend flag -- CCW has suspend flag set to one, but suspend contrel was not specified in the ORB Address of invalid CCW + 8 Invalid CCW, format 1, for a TIC Address of TIC + B Invalid sequence -- two TICs Address of second TIC + 8 Invalid sequence -- 256 or more CCWs without data transfer Address of 256th CCW + B Status-pending (lYIYl/AIPSX); termination occurred because of protection check detected as follows: 3 On a CCW access Address of the protected CCW On data or an InAW access Address of current CCW Figure 16-4 (Part 2 of 4). CCW Address as Function of Subchannel State 16-20 ESAj370 Principles of Operation + B + 85 Subchannel State 1 CCW Address 2 Status-pending (lYIYl/AIPSX); termination occurred because of chaining check 3 Address of current CCW + 8 Status-pending (YYIYl/AIPSX); termination occurred under count contro1 3 Address of current CCW + 86 Status-pending (lYIYl/AIPSX); operation prematurely terminated by the device because of alert status 3 Address of current CCW + 86 Status-pending (YYYYl/AIPSX) after termination by HALT SUBCHANNEL and the activity-controlfield bits indicated below set to ones: Status-pending alone Unpredictable Start-pending 3 Unpredictable Device-active and start-pending 3 Unpredictable Device-active Unpredictable Subchannel-active and device-active 3 ccw Suspended CCW + 8 of CCW causing suspension Suspended and resume-pending Unpredictable + 8 of the last executed CCW Status-pending (88881/AIPSX) after termination Unpredictable by CLEAR SUBCHANNEL Status-pending (YYIYl/AIPSX); operation completed normally at the subchanneP CCW + 8 of the last executed CCW6 Status-pending (80011/AIPSX) Unpredictable Status-pending (10001/AIPSX) Unpredictable Status-pending (88881/AIPSX) Unpredictable Status-pending (lYlll/AIPSX); command chaining Address of current CCW + 86 suppressed because of alert status other than channel-control check or interface-control check 3 Status-pending (lYYYl/AIPSX) because of alert status for channel-control check or interface-control check 3 See note 36 Status-pending (lYIYl/AIPSX) because of channel-data check 3 Address of current CCW + 86 Figure 16-4 (Part 3 of 4). CCW Address as Function of Sub channel State Chapter 16. I/O Interruptions 16-21 Explanation: 1 The meaning of the notation used in this column is as follows: A Alert status I Intermediate status P Primary status S Secondary status X Status-pending The possible combination of status-control-bit settings is shown to the left of the "/" symbol by the use of these symbols: e Corresponding condition is not indicated. 1 Corresponding condition is indicated. U Unpredictable. The corresponding condition is not meaningful when the subchannel is not status-pending. Y The corresponding condition is not significant and is indicated as a function of the subchannel state. 2 A CCW becomes current when (1) it is the first CCW of a channel program and has been fetched, (2) while command chaining, the previous CCW is no longer current and the new CCW has been fetched, or (3) in the case of data chaining, the new CCW takes over control of the I/O operation (see the section "Data Chaining" in Chapter 15, "Basic I/O Functions"). If chaining is not specified or is suppressed, a CCW is no longer current and becomes the last-executed CCW when secondary status has been accepted by the channel subsystem. During command chaining, a CCW is no longer current when device-end status has been accepted or, in the case of data chaining, when the last byte of data for that CCW has been accepted. 3 The subchannel may also be resume-pending. 4 The stored address is the channel-program address (in the ORB) + 8 even though it is either invalid or protected. 5 The stored address is the address of the current CCW + 8 even though it is either invalid or protected. 6 Incorrect length is indicated as a function of the setting of the suppress-length-indication flag in the current CCW (see the section "Channel-Command Word" in Chapter 15, "Basic I/O Functions"). Notes: 1. Unless the subchannel is also resume-pending, the address stored is the address of the CCW that caused suspension, plus 8. Otherwise, the address stored is unpredictable. 2. The address of the CCW is given as a function of the alert status indicated. For example, if a program-check or protection-check condition is recognized, the CCW address stored is the same as for the entry for program check or protection check, respectively, in this table. Alternatively, if alert status for interface-control check or channel-control check is indicated, the CCW address stored is either the channel-program address (in the ORB) + 8 or invalid as specified by the field-validity flags in the subchannel logout. 3. Bit 21 of the subchannel-logout information when stored as one, indicates that the address is CCW + 8 of the last-fetched CCW if the command for the CCW has not been accepted by the device. If the command .has been accepted by the device at the time the error condition is recognized, then the address stored is the address of the CCW + 8 of the last executed CCW. Figure 16-4 (Part 4 of 4). CCW Address as Function of Subchannel State t 6-22 ESA/370 Principles of Operation Device-Status Field Device-status conditions are generated by the I/O device and are presented to the channel subsystem over the channel path. The timing and causes of these conditions for each type of device are specified in the System Library publication for the device. The device-status field is meaningful whenever the subchannel is status-pending with any combination of primary, secondary, intermediate, or alert status. Whenever the subchannel is statuspending with intermediate status alone, the devicestatus field is zero. When the subchannel-status field indicates channel-control check, channel-data check, or interface-control check, the device-status field is usable for recovery purposes if the devicestatus field-validity flag in the ESW is one. When the subchannel is status-pending with deferredcondition code 3 indicated, the contents of the device-status field are not meaningful. If, within a system, the 1/0. device is accessible from more than one channel path, status related to channel-sub system-initiated operations in singlepath mode (solicited status) is signaled over the initiating channel path. Devices operating in multipath mode may signal solicited status over any channel path that belongs to the same path group as the initiating channel path. The handling of conditions not associated with 1/0 operations (unsolicited alert status), such as attention, unit exception, arid device end due to transition from the not-ready to the ready state, depends on the type of device and condition and is specified in the _System Library publication for the device. The channel subsystem does not modify the status bits received from the I/O device. These bits appear in the scsw as received over the channel path. Attention Attention is generated when the device detects an asynchronous condition that is significant to the program. The condition may also be described by qther status indications that accompany attention. Attention is interpreted by the program and is not associated with the initiation, execution, or conclusion of an I/O operation. The device can signal the attention' condition to the channel subsystem when no operation is in progress at the 1/0 device. Attention can be indicated with device end upon completion of an operation, and it can be presented to the channel subsystem during the initiation of a new I/O operation. When the device signals attention during the initiation of an operation, the operation is not initiated. Attention accompanying device end causes command chaining and command retry to be suppressed. , An I/O device may present attention accompanied by device end and unit exception when a transition is made from the not-ready to the ready state (see the section "Device End" on page 16-26). Status Modifier Status modifier is generated by the device when the device cannot provide its current status in response to interrogation by the channel subsystem, when the control unit is busy, when the normal sequence of commands has to be modified, or when command retry is to be initiated. When the device is interrogated and the statusmodifier condition signaled, in the absence of any other status bit, this indicates that the device cannot provide its current status. The interruption condition, which may be pending at the device, is not cleared. The 2702 Transmission Control is an example of a type of device that cannot provide its current status as a result of channel-subsystem interrogation. -Presence of status modifier and device end means that the normal sequence of commands must be modified. The handling of this set of bits by the channel subsystem depends on the operation. If command chaining is specified in the current ccw and no unusual conditions have been detected, presence of status modifier and device end causes the channel subsystem to fetch and chain to the ccw whose main-storage address is 16 higher than that of the current ccw. If the I/O device signals the status-modifier condition at a time when no command chaining is specified, or when any unusual conditions have been detected, no action is taken by the channel subsystem, and the statusmodifier bit is placed in the scsw. Status modifier is presented in combination with unit check and channel end to initiate the command-retry procedure. Control units that recognize special conditions which must be brought to the attention of the program present status modifier along with other status indications in order to modify the meaning Chapter 16. I/O Interruptions 16-23 of the status. The status presented is unrelated to the execution of an 1/0 operation. When status modifier is generated together with the busy status bit, it indicates that the busy condition pertains to the control unit associated with the addressed 1/0 device. The control unit appears busy when it is executing a type of operation that precludes the acceptance and execution of any command and may appear busy when it contains status or sense information for a device other than the one addressed. The status may be control-unit end or channel end following the performance of the halt function. The busy state occurs for operations such as backspace tape fue, in which case the control unit remains busy after providing channel end for operations concluded by HALT SUBCHANNEL. The busy state temporarily occurs on the IBM 3705 Communication Controller after initiation of an operation on a device accommodated by the control unit. A control unit accessible from two or more channel paths appears busy to the other channel paths when it is communicating with any of the channel paths. Control-Unit End Control-unit end indicates that the control unit has become available for use for another operation. The control-unit-end condition is provided only by control units shared by 1/0 devices or control units .accessible by two or more channel paths, and only when orie or both of the following conditions have occurred: 1. The channel subsystem had previously caused the control unit to be interrogated while the control unit was busy. The control unit is considered to have been interrogated in the busy state when a command has been transferred to a device on the control unit, and the control unit had' responded with busy and status modifier in the device status byte. 2. The control unit detected an unusual condition during the portion of the . operation after channel end had been signaled to the channel subsystem. The indication of the unusual condition accompanies control-unit end. However, the signaling of control-unit end and device end does not necessarily describe an unusual condition. The two conditions described above are reset by the reset signal and the clear signal. Therefore, if one of these signals occurs before control-unit end is generated, no' control-unit end is generated. If 16-24 ESA/370 Principles of Operation control-unit end has been generated but not presented to the channel subsystem by the time one of the signals occurs, the pending control-unit end is reset. If the control unit remains busy with the execution of an operation after signaling channel end but has not detected any unusual conditions and has not been interrogated by the channel subsystem, control-unit end is not generated. Similarly, control-unit end is not provided when the control unit has been interrogated and could perform the indicated function. The latter case is indicated by the absence of busy and status modifier in the response to the interrpgation. When the busy condition of the control unit is temporary, control-unit end may be included with busy and status modifier in response to the interrogation even though the control unit has not yet been freed. The busy condition is considered to be temporary if its duration is 2 milliseconds or less. If a temporary busy condition is indicated, the channel subsystem assumes the responsibility to periodically reinterrogate the control unit until it is no longer busy. The IBM 3705 Communications Controller is an example of a device in which the control unit may be busy temporarily and which includes control-unit end with busy and 'status modifier. The control-unit end condition can be signaled with channel end, with device end, or between the two. Control-unit end may be signaled at other times and may be accompanied by other status bits. When control-unit end is signaled in the absence of any other status, the status may be identified with any device recognized by the control unit. For control units attaching more than a single 1/0 device, a pending control-unit end for one 1/0 device does not necessarily preclude initiation of new operations with other attached devices. Whether the control unit allows initiation of other operations is at the option of the control unit. When control-unit end is presented to the channel subsystem subsequent to the acceptance of channel end and is accompanied by other status indications, command chaining is suppressed, if specified, and an interruption condition may be generated indicating one or more of the following conditions: 1. A secondary interruption condition, in the lowing cases: fol~ a. Control-unit end accompanied by device end and other status indications, or b. Control-unit end accompanied by only device end while the subchannel is not start-pending. 2. An alert interruption condition, in the following cases: a. Control-unit end accompanied by device end while the subchannel is subchannelactive, or b. Control-unit end accompanied by status other than device end. 3. A primary interruption condition if the subchannel is subchannel-active. When control-unit end alone is presented to the channel subsystem, the channel subsystem resets internal indications of control unit busy and discards the control-unit-end status without recognizing an interruption condition, unless all of the following conditions are met: 1. Control-unit end is presented on the channel path with which the channel subsystem is maintaining a working allegiance for this subchannel. 2. The device is not operating in multipath mode (see the section "Multipath Mode (D)" on page 15-3). 3. The subchannel active. is subchannel-and-device- 4. Channel-end status has been previously presented, and command chaining is specified. If all of the above conditions are met, the channel subsystem suppresses corrunand chaining and recognizes an interruption condition indicating primary, secondary, and alert status. In addition, when the status-verification facility is installed and active, the device-status-check bit is set to one. Control-unit end presented with channel end is unusual status and causes the channel subsystem to suppress command chaining, if specified, and recognize an interruption condition for the subchannel with primary and alert status indicated. Busy Busy indicates that the device cannot execute the command because (1) it is executing a previously initiated operation, (2) it has pending status which must be presented to the channel subsystem, (3) the device is currently inaccessible because of a busy shared facility existing between the control unit and device, as in the case of the string-switch feature on the IBM 3830 Model 2, or (4) a selfinitiated function is being perfonned. The pending status for the addressed device, if any, accompanies the busy indication. If the busy condition applies to the control unit, busy is accompanied by status modifier. Whenever the device indicates that a busy condition exists and it is unable to execute an operation, the device responds to the channel subsystem when it becomes no longer busy (see the section "Device End" on page 16-26). Channel End Channel end is caused by the completion of the portion of an I/O operation involving transfer of data or control information between the I/O device and the channel subsystem. Each I/O operation initiated at the I/O device causes one and only one channel end for an I/O operation. The channel-end condition is not generated when prograrruning errors or equipment malfunctions are detected during initiation of the operation. When command chaining takes place, only the channel end of the last operation of the chain is made available to the program. The channel-end condition is not made available to the program when a chain of commands is prematurely concluded because of an unusual condition indicated with device end or during the initiation of a chained command. The instant within an I/O operation when channel end is generated depends on the operation and the type of device. For operations such as writing on magnetic tape, the channel-end condition occurs when the block has been written. On devices that verify the writing, channel end mayor may not be delayed until verification is perfonned, depending on the device. When magnetic tape is being read, the channel-end condition occurs when the gap on tape reaches the read-write head. On devices equipped with buffers, such as the'IBM 3211 Printer Modell, the channel-end condition occurs upon completion of data transfer between the channel subsystem and the buffer. During control. operations, channel end is generated when the control Chapter 16. I/O Interruptions 16-25 information has been transferred to the devices, although, for short operations, the condition may be delayed until completion of the operation. Operations that do not cause any data to be transferred can provide the channel-end condition during the initiation sequence. Channel end is presented in combination with status modifier and unit check by means of a special sequence to initiate the command-retry procedure. Device End Device end is indicated (I) when the completion of an I/O operation occurs at the I/O device, (2) when the device signals that a transition from the notready to the ready state has occurred, (3) when the termination of an activity has occurred which previously caused a response of busy to the channel subsystem, and (4) when the I/O device signals that an asynchronous condition has been recognized. Device end normally indicates that the I/O device has become available for use for another operation. Each I/O operation initiated at the I/O device causes one and only one device end for an I/O operation. The device-end condition is not generated when any programming or equipment malfunction is detected during initiation of the operation. When command chaining is specified and the suspend flag is zero in the next ccw, receipt of the device-end signal, in the absence of' any unusual conditions, causes the channel subsystem to initiate transfer of the next command. When command chaining takes place, the only device end made available to the program is that of the last operation of the chain, unless an unusual condition is detected during the initiation of a chained command. If an unusual condition is detected during the initiation of a chained command, the subchannel becomes status-pending with primary and secondary status, and with the scsw indicating the unusual condition without including the device-end indication. The device-end condition associated with an 1/0 operation is generated either simultaneously with the channel-end condition or later. For data transfer on some I/O devices, the I/O operation is completed at the time channel end is generated, and both device end and channel end occur together. The time at which device end is presented depends upon the I/o-device type and the kind of command executed. For most I/O devices, device end is presented when the the I/O operation is completed at the I/O device. In some cases, for reasons of performance, device end is presented before the I/O 16-26 ESA/370 Principles of Operation operation has actually been completed at the I/O device. However, in all cases, when device end is presented, the I/O device is available for execution of an immediately following ccw if command chaining was specified in the previous ccw. On buffered devices, such as an IBM 3211 Printer Modell, the device-end condition occurs upon completion of the mechanical operation. When device end is generated later than channel end for the last I/O operation of a channel program, the program may elect to request the initiation of another start function prior to receiving the device-end indication. If the device-end indication is solicited and the subchannel is start-pending for a new start function, the device-end indication is discarded by the channel subsystem, and the pending I/O operation is initiated. For control operations, device end is generated at the completion of the operation at the device. The operation may be completed at the time' channel end is generated or later. When the device makes a transition from the notready to the ready state, either device end or device end, attention, and unit exception are indicated. Refer to the System Library publication for the device to determine which indication is given. Unit Check Unit check indicates that the I/O device has detected an unusual condition that is detailed by the information available to a sense command. Unit check may indicate that a programming or an equipment error has been detected, that the not-ready state of the device has affected the execution of the command, or that an exceptional condition other than the one identified by unit exception has occurred. The unit-check bit provides a summary indication of the conditions identified by sense data. An error condition causes the unit-check indication when it occurs during the execution of a command, during some activity associated with an I/O operation, or when an unusual condition is detected that is unrelated to execution of an I/O operation. Unless the error condition pertains to the activity initiated by a command or is of immediate significance to the program, the condition does not cause the program to be alerted after device end has been signaled to the channel subsystem; a malfunction may, however, cause the device to become not ready. If an error condition of immediate significance to the program occurs while there is no I/O operation in progress, unit check is presented together with attention, control-unit end, or device end as unsolicited alert status. Unit check is presented in combination with channel end and status modifier to initiate the command-retry procedure. Unit check is indicated when the existence of the not-ready state precludes a satisfactory execution of the command, or when the command, by its nature, tests the state of the device. When no status condition is pending for the addressed device at the control unit, the control unit signals unit check when a command is transferred to a device in the not-ready state. In the case of no-operation, the command is rejected, and channel end and device end do not accompany unit check. Programming Notes: Unless the command is designed to cause unit check, such as rewind and unload on magnetic tape, unit check is not indicated if the command is properly executed, even though the device has become not ready during or as a result of the operation. Similarly, unit check is not indicated if the command can be executed when the device is in the not-ready state. Selection of a device in the notready state does not cause a unit-check indication when the sense command is transferred, and when the addressed device contains status. If the device detects during the initiation sequence that the command cannot be executed, unit check is presented to the channel subsystem and appears without channel end or device end. Such device status indicates that no action has been taken at the device in response to the command. If the condition precluding proper execution of the operation occurs after the command has been accepted, unit check is accompanied by channel end, or device end, depending on when the condition was detected. Any errors associated with an operation, but detected after device end has been signaled to the channel subsystem, are indicated by signaling unit check with attention. During the initiation sequence, if the device is already active or already contains status, errors such as invalid command code or invalid CBC for the command code do not cause the device to present unit check. Under these circumstances, the device responds by presenting the busy bit together with the previously existing status, if any. The invalid CBC for the command code or the invalid command code is not indicated. Conclusion of an operation with the unit-check indication causes command chaining and command retry to be suppressed. 1. Unit-check status presented either in the absence of or accompanied by other status indicates only that sense information is available to the basic sense command. Presentation of either channel end and unit check or channel end, device end, and unit check does not provide any indication as to the kind of conditions encountered by the control unit, the state of the I/O device, or whether execution of the I/O operation ever was initiated even though the command may have been accepted. Descriptions of these conditions are provided in the sense information. 2. START SUBCHANNEL, RESUME SUBCHANNEL, HALT SUBCHANNEL, or CLEAR SUBCHANNEL may be executed for a subchannel whose associated device is attached to the same control unit that is currently holding sense data pertaining to a unit-check condition signaled by another attached device. The channel subsystem ensures that no sense data is lost. The performance of the function specified by the START SUBCHANNEL, RESUME SUBCHANNEL, or HALT SUBCHANNEL instruction may be delayed, however, until the sense data has been cleared from the control unit, or it may not take place at all, as in the case of CLEAR SUBCHANNEL. The sense data may be retrieved (or reset) by executing START SUBCHANNEL for the sub channel that presented unit check. Sense information is also reset if the execution of CLEAR SUBCHANNEL results in a clear signal being issued on the channel path on which unit check was presented, or if the RESET CHANNEL PATH instruction is executed, designating the channel path on which unit check was presented. Unit Exception Unit exception is caused when the I/O device detects a condition that usually does not occur. Unit exception includes a condition such as recognition of a tape mark and does not necessarily indicate an error. During execution of an I/O operation, unit exception has only one meaning for any particular command and type of device. The unit-exception condition can be generated only when the device is executing an I/O operation, or Chapter 16. I/O Interruptions l6-27 when the device is involved with some activity associated with an I/O operation and the condition is of immediate significance to the program. If the device detects during the initiation sequence that the operation cannot be executed, unit exception is presented and appears without channel end or device end. Such unit status indicates that no action has been taken at the device in response to the command. If the condition precluding normal execution of the operation occurs after the command has been accepted, unit exception is accompanied by channel end, or device end, depending on when the condition was detected. Any unusual conditions associated with an operation, but detected after device end has been cleared, are indicated by signaling unit exception with attention. If the I/O device responds with busy status to a command, the generation of unit exception is suppressed even when execution of that command usually causes unit exception to be indicated. or other activity in the system. (See the section Interruption" on "Program-Controlled page 15-30.) Detection of the PCI condition does not affect the progress of the I/O operation. Incorrect Length Incorrect length occurs when the number of bytes contained in the storage areas assigned for the I/O operation is not equal to the number of bytes requested or offered by the I/O device. Incorrect length is indicated for one of the following reasons: Long Block on Input: During a read, readbackward, or sense operation, the device attempted to transfer one or more bytes to main storage after the assigned main-storage areas were filled. The extra bytes have not been placed in main storage. The count in the scsw is zero. Concluding an operation with the unit-exception indication causes command chaining and command retry to be suppressed. Long Block on Output: During a write or control operation, the device requested one or more bytes from the channel subsystem after the assigned main-storage areas were exhausted. The count in the scsw is zero. Some I/O devices present unit exception accompanied by device end and attention whenever the device makes the transition from the not-ready to the ready state (see the section "Device End" on page 16-26). Short Block on I nput: The number of bytes transferred during a read, read-backward, or sense operation is insufficient to fill the main-storage areas assigned to the operation. The count in the scsw is not zero. S ubchannel-Status Field The device terminated a write or control operation before all information contained in the assigned main-storage areas was transferred to the device. The count in the scsw is not zero. Subchannel-status conditions are detected and indicated in the scsw by the channel subsystem. . Except for the conditions caused by equipment malfunctioning, they can occur only while the channel subsystem is involved with the performance of a halt, resume, or start function. The subchannel-status field is meaningful whenever the subchannel is status-pending with any combination of pr4nary, secondary, intermediate, or alert status. When the subchannel is status-pending with deferred condition code 3 indicated, the contents of the subchanne1-status field are not meaningful. Program-Controlled Interruption An intermediate interruption condition is generated after a ccw with the program-controlledinterruption (PCI) flag set to one becomes the current ccw. The I/O interruption due to the PCI flag may be delayed an unpredictable amount of time because of masking of the interruption request 16-28 ESAj370 Principles of Operation Short Block on Output: The incorrect-length indication is suppressed when the current ccw has the SLI flag set to one and the CD flag set to zero. The indication does not occur for operations rejected during the initiation sequence. The indication also does not occur for immediate operations when the count field is nonzero and the subchannel is in the incorrectlength-suppression mode. Presence of the incorrect-length condition suppresses command chaining unless the SLI flag in the ccw is one or unless the condition occurs in an immediate operation when the sub channel is in the incorrect-length -suppression mode. Program Check Program check occurs when programming errors are detected by the channel subsystem. The condition can be due to the following causes: Invalid CCW-Address Specification: The channel-program address (CPA) or the transfer-inchannel command does not designate the ccw on a doubleword boundary, or bit 0 of the CPA or bit 32 of a format-l ccw specifying the transfer-inchannel command is not zero. Invalid CCW Address: The channel subsystem has attempted to fetch a ccw from a main-storage location which is not available. An invalid ccw address can occur because the· program has designated an invalid address in the channel-programaddress field of the ORB or in the transfer-inchannel command or because, on chaining, the channel subsystem attempts to fetch a ccw from an unavailable location. A main-storage location is unavailable either because the absolute address does not correspond to a physical location or because a format-O ccw has been specified in the ORB and the absolute address designates a location greater than 16,777,215. Invalid Command Code: There are zeros in the four rightmost bit positions of the command code in the ccw designated by the CPA or in a ccw fetched on command chaining. The command code is not tested for validity during data chaining. Invalid Count, Format 0: A ccw, which is other than a ccw specifying transfer in channel, contains zeros in bit positions 48-63. Invalid Count, Format 1: A ccw that specifies data chaining or a ccw fetched while data chaining contains zeros in bit positions 16-31. Invalid IDAW-Address Specification: Indirect data addressing is specified, and the contents of the data-address field in the ccw do not designate the frrst IDAW on an integral word boundary; that is, bits 30-31 (format 0) or bits 62-63 (format 1) are not zeros. Invalid IDAW Address: The channel subsystem has attempted to fetch an IDAW from a mainstorage location which is not available. An invalid IDAW address can occur because the program has designated an invalid address in a ccw that specifies indirect data addressing or because the channel subsystem, on sequentially fetching IDAWS, attempts to fetch from an unavailable location. A main-storage location is unavailable either because the absolute address does not correspond to a physical location or because a format-O ccw has been specified in the ORB and the absolute address designates a location greater than 16,777,215. Invalid Data-Address Specification: Bit 32 of a format-I ccw is not zero. Invalid Data Address: When one of the following conditions is detected, an invalid data address is recognized by the channel subsystem. I. Use of the data address has caused the channel subsystem to attempt to wrap from the maximum storage address to zero. 2. Use of the data address has caused the channel subsystem to attempt to wrap from zero to the maximum storage address during a readbackward operation. 3. The channel subsystem has attempted to transfer data to or from a storage location which is either not available or is outside the addressing range specified by SET ADDRESS LIMIT and the limit mode at the subchannel. An invalid data address can occur because the program has designated an invalid address in the ccw or in an IDAW, or because an address-limit violation is detected when the address exceeds the boundary address specified by SET ADDRESS LIMIT, or because the channel subsystem, on sequentially accessing storage, attempted to access an unavailable location. A main-storage location is unavailable either because the absolute address does not correspond to a physical location or because a format-O ccw has been specified in the ORB, indirect data addressing has not been specified, and the absolute address designates a location greater than 16,777,215. Note: The maximum storage address is determined as a function of whether 24-bit or 31-bit addressing is used. If format-O ccws are specified in the ORB, the maximum storage address recognized by the channel subsystem is 16,777,215 unless indirect data addressing is specified. Otherwise, the maximum storage address is 2,147,483,647. If format-I ccws are specified in the ORB, the maximum storage address recognized by the channel subsystem is 2,147,483,647. Invalid IDAW Specification: Bit 0 of the IDAW is not zero, or the second or a subsequent IDAW does not designate the location of the beginning or, for Chapter 16. I/O Interruptions 16-29 read-backward operations, the location of the ending byte of a 2K-byte block. Invalid CCW, Format 0: A ecw other than a eew specifying transfer in channel does not contain a zero in bit position 39. Invalid CCW, Format 1: A ecw other than a eew specifying transfer in channel does not contain a zero in bit position 15, or a ecw specifying transfer in channel does not contain zeros in bit positions 0-3 and 8-31. Invalid Suspend Flag: A format-O or format-l eew fetched during data chaining, other than a eew specifying transfer in channel, does not contain a zero in bit position 38 or 14, respectively. A eew other than a eew specifying transfer in channel does not contain a zero in bit position 38 for a format-O eew or bit position 14 for a fonnat-l eew, and suspend control was not specified in the 0 RB (bit 4 of word 1). Invalid ORB Format: Word 1 of the ORB does not contain zeros in bit positions 5-7, 13-15, and 25-31. If the incorrect-Iength-indication-suppression facility is not installed, then bit 24 of word 1 of the ORB must also be zero. Invalid Sequence: The channel subsystem has fetched two successive ecws both of which specify transfer in channel, or, depending on the model, a sequence of 256 or more ecws with command chaining specified was executed by the channel subsystem and did not result in the transfer of any data to or from an I/O device. Detection of the program-check condition during the initiation of an operation at the device causes the operation to be suppressed and the subchannel to be made status-pending with primary, secondary, and alert status. When the condition is detected after the I/O operation has been initiated at the device, the device is signaled to conclude the operation the next time the device requests or offers a byte of data or status. In this situation, the subchannel is made status-pending as a function of the status received from the device. The program-check condition causes command chaining and command retry to be suppressed. 16-30 ESAj370 Principles of Operation Protection Check Protection check occurs when the channel subsystem attempts a storage access that is prohibited by the protection mechanism. Protection applies to the fetching of eews, IDAws, and output data, and to the storing of input data. The sub channel key provided in the ORB is used as the access key for storage accesses associated with an I/O operation. Detection of the protection-check condition during the fetching of the frrst eew or IDAW causes the operation to be suppressed and the subchannel to be made status-pending with primary, secondary, and alert status. When protection check is detected after the I/O operation has been initiated at the device, the device is signaled to conclude the operation the next time it requests or offers a byte of data or status. However, if an access violation occurs when the channel subsystem is in the process of fetching either a new IDAW or a new eew while data chaining and if the device signals the channel-end condition before transferring any data designated by the new eew or IDAW, then the status is accepted, and the subchannel becomes status-pending with primary and alert status and with protection check indicated. Other indications may accompany the protection-check indication as a function of the operation specified by the eew, the status received from the device, and the current state of the subchannel. The protection-check condition causes command chaining and command retry to be suppressed. Channel-Data Check Channel-data check indicates that an uncorrected storage error has been detected in regard to data, contained in main storage, that is currently used in the execution of an I/O operation. The condition may be indicated when detected, even if the data is not used when prefetched. Channel-data check is indicated when data or the associated key has an invalid checking-block code (eBe) in main storage when that data is referenced by the channel subsystem. On an input operation, when the channel subsystem attempts to store less than a complete checking block, and invalid eBC is detected on the checking block in storag~, the contents of the location remain unchanged, with invalid CBC. On an output operation, whenever channel-data check is indicated, no bytes from the checking block with invalid eBe are transferred to the device. During a storage access, the maximum number of bytes that can be transferred is model-dependent. If a channel-data-check condition is recognized during that storage access, the number of bytes transferred to or from storage may not be detectable by the channel subsystem. Consequently, the number of bytes transferred to or from storage may not be correctly reflected by the residual count. However, the residual count that is stored in the scsw, when used in conjunction with the storageaccess code and the ccw address, designates a byte location within the page in which the channel-datacheck condition was recognized. A condition indicated as channel-data check causes the current operation, if any, to be terminated. The subchannel becomes status-pending with primary and alert status or with primary, secondary, and alert status as a function of the status received from the device. The count and address fields of the scsw stored by TEST SUBCHANNEL pertain to the operation terminated. The extendedstatus-word-format bit is one, and subchannellogout information is stored in the ESW when TEST SUBCHANNEL is executed. Whenever the channel-data-check condition pertains to prefetched data, the failing-storage-addressvalidity flag (bit 6 of the ERW) is one. An absolute address of a location within the checking block for which the channel-data-check condition is generated is stored in the failing-storage-address field in word 2 of the ESW. Uncorrectable storage or key errors detected on prefetched data while the sub channel is startpending cause the operation to be canceled before initiation at the device. In this case, the subchannel is made status-pending with primary, secondary, and alert status, with channel-data check indicated, and with the failing-storage address stored in word 2 of the ESW. Channel-control check may also indicate that an error has been detected in the information transferred to or from main storage during an I/O operation. However, when this condition is detected, the error has occurred inboard of the channel path: in the channel subsystem or in the channel path between the channel subsystem and main storage. Detection of the channel-control-check condition causes the current operation, if any, to be terminated immediately. The subchannel is made statuspending with primary and alert status or with primary, secondary, and alert status as a function of the type of termination, the current subchannel state, and the device status presented, if any. The count and data-address fields of the scsw stored by TEST SUBCHANNEL pertain to the operation terminated. The extended-status-word-format bit is one and subchannel-Iogout information is stored in the ESW when TEST SUBCHANNEL is executed. Whenever the channel-control-check condition pertains to an invalid CBC detected on a prefetched ccw, a prefetched IDAW, or the key associated with the prefetched ccw or the prefetched IDAW, an extended-report word containing bit 6 set to one and the failing-storage address is stored in the ESW when TEST SUBCHANNEL is executed. Channel-control-check conditions encountered while prefetching when the subchannel is startpending cause the operation to be canceled before initiation at the device. In this case, the subchannel is made status-pending with primary, secondary, and alert status, with channel-control check indicated, and with the failing-storage address stored in the extended-status word. Channel-Control Check If a subchannel is halt-pending and the channel subsystem encounters a channel-control-check condition while performing the halt function for that subchannel , the subchannel remains halt-pending unless the channel subsystem can determine that the halt signal was issued. The subchannel remains halt-pending even if the channel subsystem was attempting to issue the halt signal and is unable to determine if the halt signal was issued. Channel-control check is caused by any machine malfunction affecting channel-subsystem controls. The condition includes invalid CBC on a ccw, an IDAW, or the respective associated key. The condition may be indicated when an invalid CBC is detected on a prefetched CCW, IDAW, or the respective associated key, even if that ccw or IDAW is not used. If a subchannel is start-pending or resume-pending and the channel subsystem encounters a channelcontrol-check condition while performing the start function for that subchannel, the subchannel remains start-pending or resume-pending unless the channel subsystem can determine that the fust command was accepted. The subchannel remains Whenever channel-data check is indicated, no measurement data for the subchannel is stored. Chapter 16. 110 Interruptions 16-31 start-pending or resume-pending even if the channel subsystem was attempting to initiate the I/O operation for the frrst command and is unable to determine if the command was accepted. If the channel subsystem is unable to detennine whether the frrst command was accepted, the subchannel is made status-pending with at least alert and primary status. In some situations in which a channel-subsystem malfunction exists, the channel-control-check condition may be reported as a machine-check condition. Whenever channel-control check is indicated, no measurement data for the subchannel is stored. Programming Note: If the status-control field of the scsw indicates that the subchannel is statuspending with alert status but the field-validity flags of the scsw indicate that the device-status field is not usable for error-recovery purposes, the program should assume that the channel-control-check condition occurred while the channel subsystem was accepting alert status from the device and take the appropriate action for alert status, even though the status itself has been lost. Interface-Control Check Interface-control check indicates that an invalid signal has occurred on the channel path. The condition is detected by the channel subsystem and usually indicates malfunctioning of an I/O device. Interface-control check can occur for the following reasons: 1. A data or status byte received from a device while the subchannel is subchannel-and-deviceactive or device-active has an invalid checkingblock code. 2. The status byte received from a device while the subchannel is idle, start-pending, suspended, or halt-pending has an invalid checking-block code. 3. A device responded with an address other than the address designated by the channel subsystem during initiation of an operation. 4. During command chaining, the device appeared not operational. 5. A signal from an I/O device either did not occur or occurred at an invalid time or had an invalid duration. 16-32 ESA/370 Principles of Operation 6. The channel subsystem recognized the I/o-error-alert condition (see the section "I/O-Error Alert (A)" on page 16-39). 7. ESW bit 26, device-status check, is set to one. Detection of the interface-control-check condition causes the current operation, if any, to be terminated immediately, and the subchannel is made status-pending with alert status, primary and alert status, secondary and alert status, or primary, secondary, and alert status as a function of the type of termination, the current subchannel state, and the device status presented, if any. The extendedstatus-word-format bit is one and subchannellogout information is stored in the ESW when TEST SUBCHANNEL is executed. If a subchannel is halt-pending and the channel subsystem encounters an interface-control-check condition while performing the halt function for that subchannel, the subchannel remains haltpending unless the channel subsystem can determine that the halt signal was issued. The subchannel remains halt-pending even if the channel subsystem was attempting to issue the halt signal and is unable to determine if the halt signal was issued. If a subchannel is start-pending or resume-pending and the channel subsystem encounters an interfacecontrol-check condition while performing the start function for that subchannel, the subchannel remains start-pending or resume-pending unless the channel subsystem can determine that the frrst cornmand was accepted. The subchannel remains start-pending or resume-pending even if the channel subsystem was attempting to initiate the I/O operation for the first command and is unable to determine if the command was accepted. If the channel subsystem is unable to determine whether the frrst command was accepted, the subchannel is made status-pending with at least alert and primary status. If, while initiating a signaling sequence with the channel subsystem for the purpose of presenting status or transferring data, the device presents an address with invalid parity, the error condition is not made available to the program since the identity of the device and associated subchannel are unknown. Whenever interface-control check is indicated, no measurement data for the subchannel is stored. If the status-control field of the scsw indicates that the subchannel is statuspending with alert status but the field-validity flags of the scsw indicate that the device-status field is not usable for error-recovery purposes, the program should assume that the interface-control-check condition occurred while the channel subsystem was accepting alert status from the device and take the appropriate action for alert status, even though the status itself has been lost. tion. It causes command chaining to be suppressed. Programming Note: Chaining Check Chaining check is caused by channel-subsystem overrun during data chaining on input operations. The condition occurs when the I/o-data rate is too high for the particular resolution of data addresses. Chaining check cannot occur on output operations. Detection of the chaining-check condition causes the I/O device to be signaled to conclude the opera- Count Field C Bits 16-31 of word 2 contain the residual count. The count is to be used in conjunction with the original count specified in the last ccw and, upon existing conditions (see depending Figure 16-4 on page 16-19), indicates the number of bytes transferred to or from the area designated by the ccw. The count field is meaningful whenever the subchannel is status-pending with primary status which consists of either ( 1) device status only or (2) device status together with subchannel status of incorrect length only, PCI only, or both. In Figure 16-5 on page 16-34, the contents of the count field are listed for all cases where the subchannel is either start-pending, subchannel-anddevice-active, device-active, suspended, or statuspending. Chapter 16. I/O Interruptions 16-33 Subchannel State 1 Count Start-pending (UUUU8/AIPSX)2 Not meaningfu1 3 Start-pending and status-pending (l8YY1/AIPSX) 2 Not meaningfu1 3 Start-pending and status-pending (88111/AIPSX) Not meaningfu1 3 because the device appeared not operational on all paths 2 Start-pending and device actiye (UUUU8/AIPSX)2 Not meaningfu1 3 Suspended (YYYYY/AIPSX)2 Not meaningfu13 Subchannel-and-device-active (UUUU8/AIPSX)2 Not meani ngfu13 Device-active (UUUU8/AIPSX) Not meaningfu1 3 Status-pending (81881/AIPSX) because of program-control led-interruption condition or initial-status interruption Not meaningfu1 3 Status-pending (lYIYl/AIPSX); termination occurred because of: 2 Program check Protection check Chaining check Channel-control check Interface control check Channel-data check Not Not Not See Not See meani ngfu13 meaningfu1 3 meaningfu1 3 note 1 meaningfu13 note 2 Status-pending (YYIYl/AIPSX)j termination occurred under count contro12 Correct Status-pending (Y8811/AIPSX)2 Not meaningfu13 Status-pending (lYIYl/AIPSX)2 Correct; residual count of last used CCW Status-pending (lYlll/AIPSX)j cOlnmand chaining Correct; residual count of last used suppressed because of alert status 2 CCW Status-pending (YYYYl/AIPSX)j after termination Unpredictable by HALT SUBCHANNEL2 Status-pending (88881/AIPSX)j after termination Not meaningfu1 3 by CLEAR SUBCHANNEL Status-pending (YYIYl/AIPSX)j operation completed normally at the subchanne1 2 Correct; indicates the residual count Figure 16-5 (Part 1 of 2). Contents of Count Field in the SCSW 16-34 ESA/370 Principles of Operation Count Subchannel State 1 Status-pending (IYlll/AIPSX); command chaining Correct; original count of CCW terminated because of alert status 2 specifying the new I/O operation Status-pending (19991/AIPSX) because of alert status Not meaningful 3 Explanation: 1 In situations where more than a single condition exists because of, for example, alert status that is described by program check and unit check, the entry appearing first in the table takes precedence. The meaning of the notation in this column is as follows: A I P S X Alert status Intermediate status Primary status Secondary status Status-pending The allowed combination of status-control-bit settings is shown to the left of the 1\ / " symbol. Bit settings are specified as follows: 9 Corresponding condition is not indicated. 1 Corresponding condition is indicated. U Unpredictable. The corresponding condition is not meaningful when the subchannel is not status-pending. Y Corresponding condition is not significant and is indicated as a function of the subchannel state. 2 3 The subchannel may also be resume-pending. The contents of the count field are not meaningful because the count field is not valid when the SCSW is stored and the subchannel is in the given state. Notes: 1. The count is unpredictable unless IDAW check is indicated, in which case the count may not correctly reflect the number of bytes transferred to or from main storage but will (when used in conjunction with the CCW address) designate a byte location within the page in which the channel-control-check condition was recognized. 2. During a storage access, the maximum number of bytes that can be stored by a channel subsystem is model-dependent. If a channel-data-check condition is recognized during that access, the number of bytes transferred to or from storage may not be detectable by the channel subsystem. Consequently, the number of bytes transferred to or from storage may not be correctly reflected by the residual count. However, the residual count that is stored when used in conjunction with the storage-access code and the CCW address designates a byte location within the page in which the channel-data-check condition was recognized. Figure 16-5 (Part 2 of 2). Contents of Count Field in the SCSW Chapter 16. I/O Interruptions 16-35 Extended-Status Word The extended-status word (ESW) provides additional information to the program about the subchannel and its associated device. The ESW is placed in words 3-7 of the IRB designated by the second operand of TEST SUBCHANNEL when TEST SUBCHANNEL is executed and the subchannel designated is operational. If the subchannel is statuspending or status-pending with any combination of primary, secondary, intermediate, or alert status (except as noted in the next paragraph) when TEST SUBCHANNEL is executed, the ESW may have one of the following types of extended-status formats: Format Description Subchannellogout in word 0, an ERW in o word 1, a failing-storage address or zeros in word 2, and zeros in words 3-4 Zeros in bytes 0 and 2-3 of word 0, the LPUM in byte 1 of word 0, and zeros in words 1-4 Zeros in byte 0, the LPUM in byte 1, and 2 the device-connect time in bytes 2-3 of word 0; zeros in words 1-4 Zeros in byte 0, the LPUM in byte 1, and 3 unpredictable values in bytes 2 and 3 of word 0; zeros in words 1-4 Bytes 0-3 of word 0 of the ESW contain unpredictable values if any of the following conditions IS met: 1. The subchannel is not status-pending. 2. The subchannel is status-pending alone, and the extended-status-word·format bit is zero. 3. The subchannel is status-pending with intermediate status alone for other than the intermediate .interruption condition due to suspension. The type of extended-status format stored depends upon conditions existing at the subchannel at the time TEST SUBCHANNEL is executed. The conditions under which each of the types of formats is stored are described in the remainder of this section. Extended-Status Format 0 The ESW stored by TEST SUBCHANNEL is a format-O ESW when the extended-status-wordformat bit (bit 5, word 0 of the scsw) is one and the subchannel is status-pending with any combination of status as defmed in Figure 16-6 on page 16-40. In this case, subchannel~logout infor- 16-36 ESA/370 Principles of Operation mation and an ERW are stored in the extendedstatus word. Subchannel logout provides detailed model-independent information, relating to a subchannel and describing equipment errors detected by the channel subsystem. The information is provided to aid the recovery of an I/O operation, a device, or both. Whenever subchannel logout is provided, the error conditions relate only to the subchannel reporting the error. If I/O operations involving other subchannels have been affected by the error condition, those subchannels also provide An similar subchannel-Iogout information. extended-report word provides additional information relating to the cause of the malfunction. A format-O ESW has this format: e Subchannel Logout 1 Extended-Report Word 2 Failing-Storage Address 3 Zeros 4 Subchannel Logout The subchannellogout has this format: lei e LPUM ESF 1 8 16 22 24 26 31 Extended-Status Flags (ESF): Any of the bits 1-7, when one, specify that an error-check condition has been detected by the channel subsystem. The following indications are provided in the ESP field: Key Check: Bit 1, when one, indicates that the channel subsystem, when accessing data, when attempting to update the measurement block, or when attempting to fetch either a ccw or an IDAW, has detected an invalid checking-block code (CBC) on the associated storage key. The channel-data-check bit (bit 12 of word 2 of the scsw), the measurementblock data-check bit (bit 3 of word 0 of the ESW), the ccw-check bit (bit 5 of word 0 of the ESW), or the IDAw-check bit (bit 6 of word 0 of the ESW) identifies the source of the key error. Note: This condition may be indicated to the program when an invalid checking-block code on a key is detected but the data, ccw, or IDAW is not used when prefetching. In this case, the failing-storage-address-validity bit (bit 6 of the ERW) is one, indicating that an absolute address of a location within the invalid CBC is stored in word 2 of the ESW. Measurement-Block Program Check: Bit 2, when one, indicates that the channel subsystem, in attempting to update the measurement block, has detected an invalid absolute address when combining the measurement-block origin with the measurement-block index for this subchannel. Measurement-Block Data Check: Bit 3, when one, indicates that a malfunction has been detected involving the data of the measurement block in main storage. (See the section "Measurement Block" on page 17-2.) Measurementblock data check is indicated when the measurement block is updated and an invalid checking-block code (CBC) is detected on the storage used to contain the measurement data or on the associated key. When invalid CBC on the associated key is detected, the keycheck bit, bit 1 of the ESF field, is also stored as one. Measurement-Block Protection Check: Bit 4, when one, indicates that the channel subsystem, when attempting to update the measurement block, has been prohibited from accessing the measurement block because the storage key does not match the measurement-block key (see the section "Measurement Block" on page 17-2.) The key provided by SET CHANNEL MONITOR is used for the access of storage associated with measurement-blockupdate operations (see the section "Set Channel Monitor" on page 14-10). Whenever any of the measurementcheck conditions, bits 2-4, is indicated, the channel subsystem sets the sub channel measurement-block-update-enable bit to zero, disabling the storing of measurement data for the sub channel (see the section "Measurement Mode Enable (MM)" on page 15-3). Note: CCW Check: Bit 5, when one, indicates that an invalid CBC on the contents of the ccw or its associated key has been detected. When either of these conditions is detected, the I/O operation is terminated, the subchannel becomes status-pending with primary and alert status, the extended-status-word-format bit in the scsw is stored as one, and channelcontrol check is indicated in the sub channelstatus field. The subchannel also becomes status-pending with secondary status as a function of the type of termination or status received from the device. When invalid CBC on the associated key is detected, the keycheck bit, bit 1 of the ESP field, is also stored as one. Note: This condition may be indicated to the program when an invalid checking-block code on the contents of a prefetched ccw is detected but the ccw is not used. In this case, the failing-storage-address-validity bit (bit 6 of the ERW) is one, indicating that an absolute address of a location within the invalid CBC is stored in word 2 of the ESW. IDAW Check: Bit 6, when one, indicates that an invalid CBC on the contents of an IDA W or its associated key has been detected. When either of these conditions is detected, the I/O operation is terminated with the device, the sub channel becomes status-pending with primary and alert status, the extended-statusword-format bit in the scsw is one, and channel-control check is indicated in the subchannel-status field. The sub channel also becomes status-pending with secondary status as a function of the type of termination or status received from the device. When invalid CBC on the associated key is detected, the key-check bit, bit 1 of the ESF field, is also one. Note: This condition may be indicated to the program when an invalid checking-block code on the contents of a prefetched IDAW is detected but the IDAW is not used. In this case, the failing-storage-address-validity bit (bit 6 of the ERW) is one, indicating that an absolute address of a location within the invalid CBC is stored in word 2 of the ESW. Detection of a channel-data-check condition does not cause the ccw-check and IDAw-check bits to be stored as ones. Reserved: Bit 7 is stored as zero. Last-Path-Used Mask (LPUM): Bits 8-15 indicate the channel path that was last used for communicating or transferring information between the channel subsystem and the device. The bit corresponding to the channel path in use is set whenever one of the following occurs: Chapter 16. I/O Interruptions 16-37 1. The fll'st command of a start-subchannel function is accepted by the device (see the section "Activity Control (AC)" on page 16-13). 2. The device and channel subsystem are actively communicating when the channel subsystem performs the suspend function for the channel program in execution. 3. The channel subsystem accepts status from the device that is recognized as an interruption condition, or a condition has been recognized that suppresses command chaining (see the Conditions" on section "Interruption page 16-2). 4. The channel subsystem recognizes an interfacecontrol-check condition (see the section "Interface-Control Check" on page 16-32), and no subchannel-Iogout infonnation is currently present at the subchannel. The LPUM field contains the most recent setting and is valid whenever the FSW contains infonnation in one of the formats 0-3 (see the section "Extended-Status Word" on page 16-36) and the scsw is stored. When subchannel-Iogout information is present in the FSW, a zero LPuM-fieldvalidity flag indicates that the LPUM setting is not consistent with the other subchannel-logout indications. Field-Validity Flags (FVF): Bits 17-21 indicate the validity of the information stored in the corresponding fields of either the scsw or the extendedstatus word. When the validity bit is one, the corresponding field has been stored and is usable for recovery purposes. When the validity bit is zero, the corresponding field is not usable. This bit-significant field has meaning when channel-data check, channel-control check, or interface-control check is indicated in the scsw. When these checks are not indicated, this field, as well as the termination-code and sequence-code fields, has no meaning. Further, when these checks are not indicated, the last-path-used-mask, devicestatus, and ccw-address fields are all valid. The fields are defmed as follows: 17 18 19 20 21 Last-path-used mask Termination code Sequence code Device status ccw address 16-38 ESA/370 Principles of Operation storage-Access Code (SA): Bits 22-23 indicate the type of storage access that was being perfonned by the channel subsystem at the time of error. It pertains only to the access of storage for the purpose of fetching or storing data during execution of an I/O operation. This encoded field has meaning only when channel-data check, channelcontrol check, or interface-control check is indicated in the subchannel status. The access-code assignments are as follows: 00 01 10 11 Access type unknown Read Write Read backward Bits 24-25 indicate the This type of termination that has occurred. encoded field has meaning only when channel-data check, channel-control check, or interface-control check is indicated in the scsw. The types of termination are as follows: Termination Code (TC): 00 01 10 11 Halt signal issued Stop, stack, or normal termination Clear signal issued Reserved When at least one channel check is indicated in the scsw but the termination-code-fie1d-validity flag is zero, it is unpredictable which, if any, termination has been signaled to the device. If more than one channel-check condition is indicated in the scsw, the device may have been signaled one or more termination codes that are the same or different. In this situation, if the termination-code-field-validity flag is one, the termination code indicates the most severe of the terminations signaled to the device. The termination codes, in order of increasing severity, are: stop, stack, or nonnal termination (01); halt signal issued (00); and clear signal issued (10). Device-Status Check (D): When the statusverification facility is installed, bit 26, when one, indicates that the subchannel logout in the FSW resulted from the channel subsystem detecting device status that had valid CBC but that contained a combination of bits that was inappropriate when the status byte was presented to the channel subsystem. When the device-status-check bit is one, the interface-control-check status bit is set to one. If, additionally, bit 20 of the subchannel-10gout field has been stored as one, then the status byte in error has been stored in the device-status field of the scsw. If the status-verification facility is not installed, bit 26 is stored as zero. end, device end, and status modifier, or (4) all zeros. Bit 27, when one, indicates that a malfunction of a system component which mayor may not have been directly related to any activity involving subchannels or I/O devices has occurred. Subsequent to this occurrence, the activity related to this subchannel and the associated I/O device was affected and caused the subchannel to be set status-pending with either channel-control check or interface-control check. 011 At least one byte of data has been transferred between the channel subsystem and the device. This code may be used when the channel path is in an idle or polling state. I/O·Error Alert (A): Bit 28, when one, indicates that subchannel logout in the ESW resulted from the signaling of I/o-error alert. The I/o-error-alert signal indicates that the control unit or device has detected a malfunction that must be reported to the channel subsystem. The channel subsystem, in response, issues a clear signal and, except as described in the next paragraph, causes interfacecontrol check to be set and extended-status-format-O (logout) information to be stored in the ESW. 1. When the command address is updated during command chaining or during the initiation of a start function or resume function at the device Secondary Error (E): When I/o-error alert is signaled and the subchannel has previously been set disabled or no subchannel is associated with the device, the clear signal is issued to the device, and the I/o-error-alert indicatio:tl is ignored by the channel subsystem. Bits 29-31 identify the I/O sequence in ,progress at the time of error. The sequence code pertains only to I/O operations initiated by execution of START SUBCHANNEL or RESUME SUBCHANNEL. This encoded field has meaning only when channel-data check, channelcontrol check, or interface-control check is indicated in the scsw. Sequence Code (SC): The sequence-code assignments are: 000 Reserved 001 A nonzero command byte has been sent by the channel subsystem, but device status has not yet been analyzed by the channel subsystem. This code is set during the initiation sequence. 010 The command has been accepted by the device, but no data has been transferred. This code is set during the initiation sequence, if the initial status is ( 1) channel end alone, (2) channel end and device end, (3) channel 100 The command in the current ccw (1) has not yet been sent to the device, (2) was sent but not accepted by the device, or (3) was sent and accepted but command-retry status was presented. This code is set when one of the following conditions occurs: 2. When, during the initiation sequence, the status includes attention, control-unit end, unit check, unit exception, busy, status modifier (without channel end and device end), or device end (without channel end) 3. When command retry is signaled 4. When the channel subsystem interrogates the device in the process of clearing an interruption condition S. When the channel subsystem signals the conclusion of the chain of operations to the device during command chaining while performing the suspend function 101 The command in the current ccw has been accepted, but data transfer is unpredictable. This code applies from the time a device is logically connected to a channel path until the time it is determined that a new sequence code applies. This code may also be used when the channel subsystem places a channel path in the polling or idle state and it is impossible to determine that code 010 or 011 applies. It may also be used at other times when a channel path cannot distinguish between code 010 or 011. 110 Reserved 111 Reserved Figure 16-6 on page 16-40 dermes the relationship between indications provided as subchannel-10gout data and the appropriate scsw bits. Chapter 16. I/O Interruptions 16-39 Logout Condition for SCSW Indication of1 Subchanne1-Logout Condition Indicated CDC Key check Measurement-b1ock-program check 2 Measurement-b10ck-data check 2 Measurement-b1ock-protection check 2 CCW check IDAW check Last-path-used mask' Field-validity flags Termination code' Device-status check Secondary error I/O-error alert Sequence code 3 CCC V V - - - - V V V - - V V V V V - - V - - V V IFCC - - - V V V V V V V Explanation: - No relationship. 1 When more than one SCSW indication is signaled, the subchanne1-1ogout conditions that are valid are the logical OR for each of the respective SCSW indications. 2 Only one measurement-block check may be indicated in a specific subchannel logout. , This field has a field-validity flag. CCC Channel-control check. CDC Channel-data check. IFCC Interface-control check. Bit setting valid. V stored in word 2 of the ESW an absolute address of a location within the invalid CBC. When an ERW is stored with bit 6 set to zero, the channel subsystem has not detected an invalid CBC while prefetching data, a CCW, or an IDAW, and zeros are stored in word 2 of the ESW. The remaining bits of the ERW are currently reserved and are stored as zeros when the ERW is stored. Failing-Storage Address Word 2 of the extended-status word fonns an absolute address. When the channel subsystem has detected an invalid CBC, and the failing-storageaddress-validity flag (bit 6 of the ERW) is one, the address contained in the failing-storage-address field designates a byte location within the checking block associated with the invalid CBC. When the failingstorage-address-validity flag is zero, this field contains zeros. Extended-Status Format 1 The ESW stored by TEST SUBCHANNEL is a fonnat-l ESW when the following conditions are met: 1. The extended-status-word-fonnat bit (bit 5, word 0 of the scsw) is zero. 2. The subchannel status-control field has the status-pending bit (bit 31, word 0 of thescsw) set to one, together with: Figure 16-6. Relationship between Subchannel-Logout Data and SCSW Bits a. The primary-status bit (bit 29, word 0 of the scsw) alone, or Extended-Report Word The extended-report word provides infonnation to the program describing specific conditions that may exist at the device, subchannel , or channel subsystem. The extended-report word is stored when the extended-status-word-fonnat bit (bit 5, word 0 of the scsw) is one. b. The primary-status bit and other statuscontrol bits, or c. The intennediate-status bit (bit 28, word 0 of the scsw) and the suspended bit (bit 26, word 0 of the scsw). 3. At least one of the following conditions is indi- cated: The ERW has this fonnat: device-connect-time-measurement a. The mode is inactive. b. The channel-subsystem-timing facility is not available for the subchannel. c. The subchannel is not enabled for the device-connect-time-measurement mode. Falllng-Storage-Address-Validity Flag (F): Bit 6, when one, indicates that the channel subsystem has detected an invalid CBC on a ccw, a data address, an IDAW, or the respective associated key and has 16-40 ESAj370 Principles of Operation Zeros are stored in bytes 0 and 2-3 of word 0, and the LPUM is stored in byte 1 of word O. Zeros are stored in words 1-4. The device-connect-time-measurement mode is made inactive when SET CHANNEL MONITOR is executed and bit 31 of general register 1 is zero. A format-1 ESW A format-2 :1 has this format: I : I I 4~1 e I LPUM Zeros 16 41~ e has this format: LPUM OCTI Zeros I I __~__~______~1 8 16 31 I __~__~______~I 8 ESW 31 For a defmition of the LPUM, see the section "Last-Path-Used Mask (LPUM)" on page 16-37. Last-Path-Used Mask (LPUM): Extended-Status Format 2 The ESW stored by TEST SUBCHANNEL is a format- 2 ESW when the following conditions are met: 1. The extended-status-word-format bit (bit 5, word 0 of the scsw) is zero. 2. The channel-sub system-timing facility is available for the subchannel. 3. The subchannel is enabled for the deviceconnect-time-measurement mode. 4. The device-connect-time-measurement mode is active. 5. The subchannel status-control field has the status-pending bit (bit 31, word 0 of the scsw) set to one, together with: a. The primary-status bit (bit 29, word 0 of the scsw) alone, or b. The primary-status bit and other statuscontrol bits, or Last-Path-Used Mask (LPUM): For a defmition of the LPUM, see the "Last-Path-Used Mask (LPUM)" on page 16-37. Oevice-Connect-Tlme Interval (OCTI): Bits 16-31 contain the binary count of time increments accumulated by the channel subsystem during the time that the channel subsystem and the device were actively communicating and the subchannel was subchannel-active. The time increment of the OCTI is 128 microseconds. If the above conditions for the storing of the nCTI value in the ESW are met but the device-connecttime-measurement mode was made active by SET CHANNEL MONITOR subsequent to execution of START SUBCHANNEL for this subchanne1, the OCTI value stored is greater than or equal to zero and less than or equal to the correct nCTI value. Note: The OCTI value stored in the ESW is the same as that used to update the corresponding measurement-block data for the subchannel if the measurement-block-update mode is in use for the subchannel. If the measurement-block-update mode for the channel subsystem is active and the subchanne1 is enabled for the device-connect-timemeasurement mode but no nCTI value is stored in the ESW (because of the presence of sub channellogout information), or if the nCTI is zero, then corresponding nothing is added to the measurement-block data. c. The intermediate-status bit (bit 28, word 0 of the scsw) and the suspended bit (bit 26, word 0 of the scsw). Zeros are stored in byte 0 of word 0, the LPUM is stored in byte 1 of word 0, and the device-connect time is stored in bytes 2-3 of word O. Zeros are stored in words 1-4. Chapter 16. I/O Interruptions 16-4 t Extended-Status Format 3 Subchannel Conditions When IRB Is Stored The FSW stored by TFST SUBCHANNEL is a format-3 FSW when the extended-status-wordformat bit (bit 5, word 0 of the scsw) is zero and the subchannel is status-pending with ( 1) secondary status, alert status, or both when primary status is not also present, or (2) intermediate status when the subchannel is not suspended. Zeros are stored in byte 0 of word 0, and the LPUM is stored in byte 1 of word O. Bytes 2-3 of word 0 contain unpredictable values. Zeros are stored in words 1-4. A format-3 FSW : I has this fonnat: LPUM XXXXXXXX XXXXXXXX I Subchannel:" Status Word Path-ManagementControl Word ExtendedStatus Word (ESW) , Word 0 DeviceConnectStatusDeviceTimeControl Sus- ConnectMsrmntContents Field pen- TimeTiming- ModeL ded Msrmnt Facility Enable For- Bytes AIPSX Bit Bit t10de Bit Bit mat 0,1,2,3 ----a /////////////////////////////////// /////////////////////////////// aaaal a /////////////////////////////// U ////////////////////////// a ////////////////////////// a18a1 Inactive ///////////////// //1///// a /1////1/ 1 a **** ZMZZ 1 Active a 1 I 4~1__~__~__~__~I o 8 16 24 31 An "x" in the format indicates the bit may be zero or one. Figure 16-7 summarizes the conditions at the subchannel under which each type of information is stored in the FSW. ZMDD 1/////1/ 1 ZHZZ //// Inactive ///////////////// /1////1/ //// **1*1 //// a 1/// a //// Active Last-Path-Used Mask (LPUM): For a defInition of the LPUM, see the section "Last-Path-Used Mask (LPUM)" on page 16-37. 2 1 I Zeros /1// //// a 1 1 2 ZMDD ZM** 1*aa1 a /////////////////////////////// ////////////////////1//////1/// 3 a /1////1/////////1////////////1/ ****1 1 //////11///1/1//1///1/11/////// a RRRR **a11 Ex~lanation: - Defined to be not me~ningful when X is zero. * Bits may be zeros or ones. I Information not relevant in this situation. A Alert status. 0 Accumulated device-connect-time-interval (OCTI) value stored in bytes 2 and 3. I Intermediate status. L Extended-status-word format. M Last-path-used mask (LPUM) stored in byte 1. P Primary status. R Subchannel-logout information stored in word a. S Secondary status. U No format defined. X Status-pending. Z Bits are stored as zeros. Figure 16-7. Information Stored in ESW 16-42 ESA/370 Principles of Operation Extended-Control Word SCSW Word 0 The extended-control word provides additional information to the program describing conditions that may exist at the channel subsystem, subchannel, or device. The extended-control (E) bit (bit 14, word 0 of the scsw), when one, indicates that model-dependent information has been stored in the extended-control word. Bits l 14 o o 1 1 The extended-control word may be stored only when the extended-status-word-format bit (bit 5, word 0 of the scsw) is also stored as one. The information provided in the extended-control word is as follows: 5 3 o 1 ECW Words 0-7 Unpredictable 2 Unpredictable 2 Model-dependent information 3 1 The combination 01 is reserved for future use. 2 If stored, the value of these words is unpredictable. Unused bits in the model-dependent information are stored as zeros. Chapter 16. I/O Interruptions 16-43 Chapter 17. 1/0 Support Functions Channel-Subsystem Monitoring Channel-Subsystem Timing Channel-Subsystem Timer Measurement-Block Update Measurement Block Time-Interval-Measurement Accuracy Device-Connect-Time Measurement Signals and Resets Signals Halt Signal Clear Signal Reset Signal Resets . . . . . 17-1 17-1 17-2 17-2 17-2 17-4 17-5 17-5 17-5 17-5 17-5 17-6 17-6 The I/O support functions are those functions of the channel subsystem that are not directly related to the initiation or control of I/O operations. The following I/O support functions are described in this chapter: channel-subsystem monitoring, signals and resets, externally initiated functions, status verification, address-limit checking, configuration alert, and channel-subsystem recovery. Channel-Subsystem Monitoring Monitoring facilities are provided in the channel subsystem so that the program can retrieve measured values on performance for a designated subchannel. The use of these facilities is under program control by means of the execution of the SET CHANNEL MONITOR instruction. Additionally, each subchannel can be selectively enabled to use the facilities by means of the execution of the MODIFY SUBCHANNEL instruction. The channel-subsystem-monitoring facilities include the zone-measurement facility, alternatemeasurement facility, channel-subsystem-timing facility, measurement-block-update facility, and device-connect-time-measurement facility. The measurement-block-update facility and the deviceconnect-time-measurement facility are logically distinct ~d operate independent of one another. Each of the facilities that constitute the channelsubsystem-monitoring facilities is described in this chapter. Channel-Path Reset I/O-System Reset Externally Initiated Functions Initial Program Loading Reconfiguration of the I/O System Status Verification . . . . . . . . . . . Address-Limit Checking . . . . . . . . . Configuration Alert . . . . . . . . . . . . Incorrect-Length-Indication Suppression Channel-Subsystem Recovery Channel Report Channel-Report Word . 17-6 . 17-6 17-10 17-10 17-12 17-12 17-12 17-13 17-13 17-13 17-14 17-15 Channel-Subsystem Timing The channel-sub system-timing facility provides the channel subsystem with the capability of measuring the elapsed time required for performing several different phases in processing a start function initiated by START SUBCHANNBL. These elapsed-time measurements are used by both the measurement-blockupdate facility and the device-connect-timemeasurement facility to provide subchannel performance information to the program. While every channel subsystem has a channelsubsystem-timing facility, it mayor may not be provided for use with all subchannels. Subchannels for which the facility is provided have the timingfacility bit (bit 14 of word 1) stored as one in the associated subchannel-information block. (See the section "Timing Facility (T)" on page 15-4.) If the channel-subsystem-timing facility is not provided for the subchannel, its timing-facility bit is stored as zero. Subchannels that do not have the channelsubsystem-timing facility provided are those for which the characteristics of the associated device, the manner in which it is attached to the channel subsystem, or the channel-subsystem resources required to support the device are such that use of the channel-subsystem~timing facility is precluded. The channel-subsystem-iiming facility consists of at least one channel-subsystem timer and the associated logic and storage required for computing and recording the elapsed-time intervals for use by the two measurement facilities. The aspects of the Chapter 17. I/O Support Functions 17-1 channel-subsystem-timing facility that are of importance to the program are described below. Channel-Subsystem Timer Each channel-subsystem timer is a binary counter that is not accessible to the program. The channelsubsystem timer is incremented by adding a one to the rightmost bit position every 128 microseconds. When incrementing the channel-subsystem timer causes a carry out of the leftmost bit position, the carry is ignored, and counting continues from zero. No indications are generated as a result of the overflow. Just as every CPU has access to a TOO clock, every channel subsystem has access to at least one channel-subsystem timer. When multiple channelsubsystem timers are provided, synchronization among these timers is also provided, creating the effect that all the timing facilities of the channel subsystem share a single timer. Synchronization among these timers may be supplied either through some TOO clock or independently by the channel subsystem. If the TO 0 clocks are not synchronized, the elapsed times measured by the channel-subsystem-timing facility may, depending upon the model, have unpredictable values for some or all of the subchannels, depending on the particular channelsubsystem timer and the way the associated devices are physically attached to the system. The values are unpredictable for those devices attached to the system by separately configurable channel paths whose associated CPU TOO clocks are not synchronized. Synchronization: If either the measurementblock-update mode or device-connect-timemeasurement mode is active and any of the channel-subsystem timers are found to be out of synchronization, a channel-subsystem-timer-sync check is recognized, and a channel report is generated to alert the program (see the section "Channel-Subsystem Recovery" on page 17-13). If neither of these modes is active, the lack of synchronization is not recognized. Measurement-Block Update The measurement-block-update facility provides the program with the capability of accumulating performance information for subchannels that are enabled for the measurement-block-update mode when the measurement-block-update mode is active. A subchannel is enabled for measurementblock-update mode by setting bit 11 of word 1 of the SCHIB operand to one and then executing MODIFY SUBCHANNEL. Measurement-blockupdate mode is made active by executing SET CHANNEL MONITOR when bit 30 of general register 1 is one. When the measurement-block-update mode is active and the subchannel is enabled for the measurement-block-update mode information is accumulated in a measurement block associated with the subchannel. A measurement block is a 32-byte area in main storage that is associated with a subchannel for the purpose of accumulating measurement data. The program specifies a contiguous area of absolute storage, referred to as the measurement-block area, and subdivides this area into 32-byte blocks, one block for each subchannel for which measurement data is to be accumulated. The measurement-block-update facility uses the measurement-block index contained at the subchannel in conjunction with the measurementblock origin established by the execution of SET CHANNEL MONITOR to compute· the absolute address of the measurement block associated with a subchannel. Measurement data is stored in the measurement block associated with the subchannel each time an I/O operation or chain of I/O operations initiated by START SUBCHANNEL is suspended or completed. The completion of an I/O operation or chain of I/O operations is normally signaled by the primary interruption condition. Five fields are dermed in the measurement block in which measurement data is accumulated by the measurementblock-update facility: SSCH + RSCH count, sample count, device-connect time, function-pending time, and device-disconnect time. Measurement Block The measurement block is a 32-byte area at the location designated by the program, using the measurement-block origin in conjunction with the measurement-block index. The measurement block contains the accumulated values of the measurement data described below. When the measurement-block-update mode is active and the subchannel is enabled for measurement-block 17-2 ESA/370 Principles of Operation update, the measurement-block-update facility accumulates the values for the measurement data that accrue during the execution of an I/O operation or chain of I/O operations initiated by START SUBCHANNEL. When the I/O operation or chain of I/O operations is suspended or completed at the subchannel and no error condition is encountered, the accrued values are added to the accumulated values in the measurement block for that subchannel. If an error condition is detected and subchannel-Iogout information is stored in the extended-status word (ESW), the accrued values are not added to the accumulated values in the measurement block for the subchannel, and the two count fields are not incremented. If any of the accrued time values is detected to exceed the internal storage provided for accruing these values, none of the accrued values are added to the measurement block for the subchannel, the sample count is not incremented, but the SSCH + RSCH count is incremented. Accesses to the measurement block by the measurement-block-update facility, in order to accumulate measurement data at the suspension or completion of an I/O function, appear blockconcurrent to CPUs. CPU accesses to the block, either fetches or stores, are inhibited during the time the measurement-block update is being performed by the measurement-block-update facility. SSCH + RSCH Count: Bits 0-15 of word 0 are used as a binary counter. When either the suspend function is performed or the primary interruption condition is recognized during the performance of'a start function, the counter is incremented by adding one in bit position 15, and the measurement data is stored. The counter wraps around from the maximum value of 65,535 to O. The program is not alerted when counter overflow occurs. If the measurement-block-update mode is active and the subchannel is enabled for measuring, the SSCH + RSCH count is incremented even when the lack of measured values for an individual start function precludes the updating of the sample count and words 1-3, or when the timing-facility bit for the subchannel is zero. The SSCH + RSCH count is not incremented if the measurement-block-update mode is inactive, if the subchannel is not enabled for the measurement-block update, or if subchannel-Iogout information has been generated for the start function. Sample Count: Bits 16-31 of word 0 are used as a binary counter. When words 1, 2, and 3 of the measurement block are updated, the counter is incremented by adding one in bit position 31. On some models, certain conditions may preclude the measurement-block-update facility obtaining the accrued values of the measurement data for an individual start function, even when the measurementblock-update mode is active and the subchannel is enabled for that mode. In this situation, the sample-count field is not incremented. The measurement block has the following format: Word e SSCH+RSCH countl Sample Count 1 Device-Connect Time 2 Function-Pending Time 3 Devi~e-Disconnect Time The counter wraps around from the maximum value of 65,535 to O. The program is not alerted when counter overflow occurs. This field is not updated if the channel-subsystem-timing facility is not provided for the subchannel. The System Library publication for the system model specifies the conditions, if any, that preclude the updating of the sample count and words I, 2, and 3 of the measurement block. 4 5 Reserved 6 7 Device-Connect Time: Bits 0-31 of word 1 contain the accumulation of measured deviceconnect-time intervals. The device-connect-time interval (DCTI) is the sum of the time intervals measured whenever the device is logically connected to a channel path for purposes of transferring information. between it and the channel subsystem. Chapter 17. 1/0 Support Functions t 7-3 The time intervals are measured using a resolution of 128 microseconds. The accumulated value is modulo approximately 152.71 hours, and the program is not alerted when an overflow occurs. This field is not updated if (1) the channelsubsystem-timing facility is not provided for the subchannel, (2) the measurement-block-update mode is inactive, or (3) any of the three time values accrued for the current start function has been detected to exceed the internal storage in which it was accrued. Accumulation of device-connect-time intervals for a subchannel and storing this data in the ESW are not affected by whether the measurement-block-update mode is active. (See the section "Device-ConnectTime Measurement" on page 17-5.) Function-Pending Time: Bits 0-31 of word 2 contain the accumulated SSCH- and RscH-functionpending time. Function-pending time is the time interval between acceptance of the start function (or resume function if the subchannel is in the suspended state) at the subchannel and acceptance of the fust command associated with the initiation or resumption of channel-program execution at the device. When channel-program execution is suspended because of a suspend flag in the ftrst ccw of a channel program, the suspension occurs prior to transferring the ftrst command to the device. In this case, the function-pending time accumulated up to that point is added to the value in the function-pending-time field of the measurement block. Function-pending time is not accrued while the subchannel is suspended. Function-pending time begins to be accrued again, in this case, when RESUME SUBCHANNEL is subsequently executed while the designated subchannel is in the suspended state. The function-pending-time interval is measured using a resolution of 128 microseconds. The accumulated value is modulo approximately 152.71 hours, and the program is not alerted when an overflow occurs. This field is not updated if the channel-subsystem-timing facility is not provided for the subchannel. Bits 0-31 of word 3 contain the accumulated device-disconnect time. Device-disconnect time is the sum of the time intervals measured whenever the device is logically disDevice-Disconnect Time: 17-4 ESA/370 Principles of Operation connected from the channel subsystem while the subchannel is subchannel-active. Device-disconnect time is not accrued while the subchannel is in the suspended state. Devicedisconnect time begins to be accrued again, in this case, on the fust device disconnection after channelprogram execution has been resumed at the device (the subchannel is again subchannel-active). The device-disconnect-time interval is measured by using a resolution of 128 microseconds. The accumulated value is modulo approximately 152.71 hours; the program is not alerted when an overflow occurs. This field is not updated if the channelsubsystem-timing facility is not provided for the subchannel. Words 4-7 of the measurement block are not updated, but are reserved for future use. Time-Interval-Measurement Accuracy On some models, when time intervals are to be measured and condition code 0 is set for START SUBCHANNEL (or RESUME SUBCHANNEL in the case of a suspended subchannel), a period of latency may occur prior to the initiation of the function-pending time measurement. The System Library publication for the system model specifies the mean latency value and variance for each of the measured time intervals. Programming Notes: 1. Excessive delays may be encountered by the channel subsystem when attempting to update measurement data if the program is concurrently accessing the same measurement-block area. A programming convention should ensure that the storage block designated by SET CHANNEL MONITOR is made read-only while the measurement-block-update mode is active. 2. To ensure that programs written to support measurement functions are executed properly, the program should initialize all the measurement blocks to zeros prior to making the measurement-block-update mode active. Only zeros should appear in the unused words (words 4-7) of the measurement blocks. 3. When the incrementing of an accumulated value causes a carry to be propagated out of bit position 0, the carry is ignored, and accumulating continues from zero on. Device-Connect-Time Measurement Signals The device-connect-time-measurement facility provides the program with the capability of retrieving the length of time that a device is actively communicating with the channel subsystem while executing a channel program. The measured length of time that the device is actively communicating on a channel path during the execution of a channel program is called the device-connect-time interval (OCTI). If the channel-subsystem-timing facility is available for the subchannel, the OCTI value is passed to the program in the extended-status word (ESW) at the completion of the operation when TEST SUBCHANNEL (1) clears the primary interruption condition or (2) clears the intermediate interruption condition alone while the subchannel is suspended. The DCTI value passed in the ESW pertains to the previous subchannel-active period. The storing of the DCTI value in the ESW is under program control by means of the measurement.;. mode-control bit for device-connect time as specified by the execution of SET CHANNEL MONITOR, and by the device-connect-time-measurementenable bit as specified by the execution of MODIFY SUBCHANNEL. However, the DCTI value is not stored in the ESW if the start function initiated by START SUBCHANNEL is terminated because of an error condition that is described by subchannel logout (see the section "Subchannel Logout" on page 16-36). In this case, the extended-statusword-format bit of the scsw is stored as one, indicating that the ESW contains subchannel-Iogout information describing the error condition. See the section "Subchannel Logout" on page 16-36 for the description of the subchannel-Iogout information. If the accrued DCTI value exceeded 8.388608 seconds during the previous subchannel-active period, then the maximum value (FFFF hex) is passed in the ESW. The request that the channel subsystem initiate a signaling sequence is made by one of the following: Signals and Resets During system operation, it may become necessary to terminate an I/O operation or to reset either the I/O system or a portion of the I/O system. (The I/O system consists of the channel subsystem plus all of the attached control units and devices.) Various signals and resets are provided for this purpose. Three signals are provided for the channel subsystem to notify an I/O device to terminate an operation or perform a reset function or both. Two resets are provided to cause the channel subsystem to reinitialize certain information contained either at the I/O device or at the channel subsystem. 1. The program executing the CLEAR SUBCHANNEL, HALT SUBCHANNEL, or RESET CHANNEL PATH instruction 2. The I/O device signaling I/o-error alert 3. The channel subsystem itself upon detecting certain error conditions or equipment malfunctions The three signals are the halt signal, the clear signal, and the reset signal. Halt Signal The halt signal is provided so the channel subsystem can terminate an I/O operation. The halt signal is issued by the channel subsystem as part of the halt function performed subsequent to the execution of HALT SUBCHANNEL. The halt signal is also issued by the channel subsystem when certain error conditions are encountered. The halt signal results in the channel subsystem using the interfacedisconnect sequence control dermed in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. Clear Signal The clear signal is provided so the channel subsystem can terminate an I/O operation and reset status and control information contained at the device. The clear signal is issued as part of the clear function performed subsequent to the execution of CLEAR SUBCHANNEL. The clear signal is also issued by the channel subsystem when certain error conditions or equipment malfunctions are detected by the I/O device or the channel subsystem. The clear signal results in the channel subsystem using the selective-reset sequence control dermed in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. If an I/O operation is in progress at the device and the device is actively communicating over a channel path in the execution of that I/O operation when a clear signal is Jeceived on that channel path, the device immediately disconnects from that channel path. Data transfer and any operation using the facilities of the control unit are immediately concluded, and the I/O device is not necessarily posi- Chapter 17. I/O Support Functions 17-5 tioned at the beginning of a block. Mechanical motion not involving the .use of the control unit, such as rewinding magnetic tape or positioning a disk-access mechanism, proceeds to the normal stopping point, if possible. The device may appear busy until termination of the mechanical motion or the inherent cycle of operation, if any, whereupon it becomes available. Status information in the device and control unit is reset, but an interruption condition may be generated upon the completion of any mechanical operation. Reset Signal The reset signal is provided so the channel subsystem can reset all I/O devices on a channel path. The reset signal is issued by the channel subsystem as part of the channel-path-reset function performed subsequent to the execution of RESET CHANNEL PATH. The reset signal is also issued by the channel subsystem as part of the I/o-systemreset function. The reset signal results in the channel subsystem using the system-reset sequence control dermed in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. Resets Two resets are provided so the channel subsystem can reinitialize certain information contained at either the I/O device or the channel subsystem. The request that the channel subsystem initiate one of the reset functions is made by one of the following: 1. The program executing the RESET CHANNEL PATH instruction 2. The operator activating a system-reset-clear or system-reset-normal key or a load-clear or load-normal key 3. The channel subsystem itself upon detecting certain error conditions or equipment malfunctions The resets are channel-path reset and I/o-system reset. Channel-Path Reset The channel-path-reset facility provides a mechanism to reset certain indications that pertain to a , designated channel path at all associated subchannels. Channel-path reset occurs when the channel subsystem performs the channel-path-reset function (See the initiated by RESET CHANNEL PATH. section "Reset Channel Path" on page 14-7.) All internal indications of dedicated allegiance, control 17-6 ESA/370 Principles of Operation unit busy, and device busy that pertain to the designated channel path are cleared in all subchannels, and reset is signaled on that channel path. The receipt of the reset signal by control units attached to that channel path causes all operations in progress and all status, mode settings, and allegiance pertainirig to that channel path of the control unit and its attached devices to be reset. (See also the description of the system-reset-signal actions in the section "I/O-System Reset.") The results of. the channel-path-reset function on the designated channel path are communicated to the program by means of a subsequent machinecheck-interruption condition generated by the channel subsystem (see the section "Channel- . Subsystem Recovery" on page 17-13). I/O-System Reset The I/o-system-reset function is performed when the channel subsystem is powered on, when· initial program loading is initiated manually (see the section "Initial Program Loading" on page 17-10), and when the system-reset-clear or system-resetnormal key is activated. The I/o-system-reset function cannot be initiated under program control; it must be initiated manually. I/o-system reset may fail to complete due to malfunctions detected at the channel subsystem or at a channel path. I/o-system reset is performed as part of subsystem reset, which also resets all floating interruption requests, including pending I/O interruptions. (See the section "Subsystem Reset" in Chapter 4, "Control. ") Detailed descriptions of the effects of I/o-system reset on the various components of the I/O system appear later in this chapter. I/o-system reset provides a means for placing the channel subsystem and its attached I/O devices in the initialized state. I/o-system reset affects only the channel-subsystem configuration in which it is performed, including all channel-subsystem components configured to that channel subsystem. I/o-system reset has no effect on any system components that are not part of the channel-subsystem configuration that is being reset. The effects of I/o-system reset on the configured components of the channel subsystem are described in the following sections. Channel-Subsystem State: I/o-system reset causes the channel subsystem to be placed in the initialized state, with all the channel-subsystem components in the states described in the following sections. All operations in progress are terminated and reset, and all indications of prior conditions are reset. These indications include status information, interruption conditions (but not pending interruptions), dedicated-allegiance conditions, pending channel reports, and all internal information regarding prior conditions and operations. In the initialized state, the channel -subsystem has no activity in progress and is ready .to perfoml the inltial-program-loading (IPL) function or respond to I/O instructions, as described in Chapter 14, "I/O Instructions"- on page 14-1. Units and Devices: I/o-system reset causes -a reset signal to be sent on all configured channel paths, including those which are not physically available (as indicated by the PAM bit being zero) because of a permanent error condition detected earlier. When the reset signal is received by a control unit, control-unit functions in progress, control-unit status, control-unit allegiance, and control-unit modes for the resetting channel path are reset. Device operations in progress, device status, device allegiance, and the device mode for the resetting channel path are also reset. Control-unit and device mode, allegiance, status, and I/O functions in progress -for other channel paths are not affected. Control -For devices that are operating in single-path mode, an operation can be in progress for, at most, one channel path. Therefore, if the reset signal is received on that channel path, the operation in progress is reset. Devices that have the dynamicreconnection feature and are operating in multipath mode, however, have the capability to establish an allegiance to a group of channel paths during an I/O operation, where all the channel paths of the path group are configured to the same channel subsystem. If an operation is in progress for a device that is operating in multipath mode and the reset signal is received on one of the channel paths of that path group, then the operation in progress is reset for the resetting channel path only. Although the operation in progress cannot continue on the resetting channel path, it can continue on the other channel paths of the path group, subject to the following restrictions: 1. If the device is actively communicating with the channel subsystem on a channel path when it receives the reset signal on that channel path, then the operation is reset unconditionally, regardless of path groups. 2. If the operation is in progress in multipath mode but the path group consists only of the resetting path, then the operation is reset. 3. Except as noted in item 2, if the operation in progress is currently in a disconnected state (device not actively communicating with the channel subsystem) or is active on another channel path of a path group,. system reset has no effect _upon continued execution of the operation. A control unit is completely reset after the reset sign3.1 has been received on all its channel paths, provided no new activity is initiated at the control unit between the receipt of the frrst and last reset signal. "Completely reset" means that the current operation, if any, at the control unit is terminated and that control-unit allegiance, control-unit status, and the control-unit mode, if any, are reset. An I/O device is completely reset after the reset signal has been received on all channel paths of all control units by which the device is accessible, provided no new activity is initiated at the device between the receipt of the frrst and last reset signal. "Completely reset" means that the current operation, if any, at the device is terminated and that device allegiance, device status, and the device mode are reset. In summary, system reset always causes an operation in progress to be reset for the channel path on which the reset signal is received. If the resetting channel path is the only channel path for which the operation is in progress, then the operation is completely reset. If a device is actively communicating on a channel path over which the reset signal is received, then the operation in progressjis unconditionallyand completely reset. The reset signal is not received by control units and devices on channel paths from which the control unit has been partitioned. A control unit is partitioned from a channel path by means of an enable/disable switch on the control unit for each channel path by which it is accessible. Multitagged, unsolicited status, if any, remains pending at the control unit for such a channel path in this case. However, from the point of view of the program, the control unit and device appear to be completely reset if the reset signal is received by the control unit on all the channel paths by which it is currently accessible. Chapter 17. I/O Support Functions 17-7 The resultant reset state of individual control units and devices is described in the System Library publication for the control unit. I/o-system reset causes a reset signal to be sent on all configured channel paths and causes the channel subsystem to be placed in the reset and initialized state, as described in the previous sections. As a result of these actions, all communication between the channel subsystem and its attached control units and devices is terminated and the components reset, and all configured channel paths are made quiescent or are deconfigured. The channel subsystem uses the system-reset sequence control dermed in the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974, to bring the channel paths into the quiescent state. Channel Paths: Subchannels: I/o-system reset causes all operations on all subchannels to be concluded. Status information, all interruption conditions (but not pending interruptions), dedicated -allegiance conditions' and internal indications regarding prior conditions and operations at all subchannels are reset, and all valid subchannels are placed in the initialized state. In the initialized state, the subchannel parameters of all valid subchannels have their initial values. The initial values of the following subchannel parameters are zeros: • • • • • • • • • Interruption parameter I/o-interruption subclass code (ISC) Enabled Limit mode Multipath mode Measurement mode Path-not-operational mask Last-path-used mask Measurement-block index The initial values of the following subchannel parameters are assigned as part of the installation procedure for the device associated with each valid subchannel: • Timing facility • Device number • Logical-path mask (same value as pathinstalled mask) • Path-installed mask • Path-available mask • Channel-path ID 0-7 17-8 ES~/370 Principles of Operation The values assigned may depend upon the particular system model and the configuration; dependencies, if any, are described in the System Library publication for the system model. Programming considerations may further constrain the values assigned. The initial value of the path-operational mask is all ones. The device-number-valid bit is one for all subchannels having an assigned I/O device. The initial value of the model-dependent area of the subchannel-information block is described in the System Library publication for the system model. The initial value of the subchannel-status word and extended-status word is all zeros. The initialized state of the subchannel is the state specified by the initial values for the subchannel parameters described above. The description of the subchannel parameters can be found in the section "Subchannel-Information Block" on page 15-1; the section "Subchannel-Status Word" on page 16-6; and in the section "Extended-Status Word" on page 16-36. Facility: I/o-system reset causes the channel-path-reset facility to be reset. A channel-path-reset function initiated by RESET CHANNEL PATH, either pending or in progress, is overridden by I/o-system reset. The machinecheck-interruption condition, which normally signals the completion of a channel-path-reset function, is not generated for a channel-path-reset function that is pending or in progress at the time Ifo-system reset occurs. Channel·Path-Reset I/o-system reset causes the address-limit-checking facility to be reset. The address-limit value is initialized to all zeros and validated. Address-Limit-Checking Facility: Channel-Subsystem-Monitoring Facilities: I/o-system reset causes the channel-subsystemmonitoring facilities to be reset. The measurementblock-update mode and the device-connect-timemeasurement mode, if active, are made inactive. The measurement-block origin and the measurement-block key are both initialized to zeros and validated. Pending Channel Reports: I/o-system reset causes pending channel reports to be reset. \ I I/o-system reset does not necessarily affect the contents of the channelsubsystem timer. In models that provide channelsubsystem-timer checking, I/o-system reset may cause the channel-subsystem timer to be validated. Channel.Subsystem Timer: Area Affected Channel-subsystem state Control units and devices Channel paths Subchannels Interruption parameter I/O-interruption subclass code (ISC) Enabled bit Limit-mode bits Timing-facility bit Multipath-mode bit Measurement-mode bits Device-number-valid bit Device number Logical-path mask Path-not-operational mask Last-path-used mask Path-installed mask Measurement-block index Path-operational mask Path-available mask Channel-path ID 0-7 Subchannel-status word Extended-status word Model~dependent area Channel-path-reset facility Address-limit-checking facility Address-limit value Channel-subsystem-monitoring facility Measurement-block-updatemode Device-connect-time-measurement mode Measurement-block origin Measurement-block key Pending channel-report words Channel-subsystem timer Pending 1/0 Interruptions: I/o-system reset does not affect pending I/O interruptions. However, during subsystem reset, I/O interruptions are cleared concurrently with the performance of I/o-system reset. See the section "Subsystem Reset" in Chapter 4, "Control." Effect of I/O-System Resetl Reset and initialized Reset Quiescent or deconfigured 2 Reset and initialized Zeros 3 Zeros 3 Zer0 3 Zeros 3 Installed value 3 Zer0 3 Zeros 3 Installed value 3 Installed value 3 Equal to path-installed mask value 3 Zeros 3 Zeros 3 Installed value 3 Zeros 3 Ones 3 Installed value 3 4 Installed value 3 Zeros 3 Zeros 3 Model-dependent3 Reset Reset and initialized Zeros 3 Reset and initialized Inactive 3 Inactive 3 Zeros 3 Zeros 3 Cleared Unchanged/validated Explanation: 1 For a detailed description of the effect of I/O-system reset on each area, see the text. 2 Channel-path malfunctions may cause a channel path to be deconfigured. 3 Initialized value. 4 Also subject to model-dependent configuration controls, if any. Figure 17-1. Summary of I/O-System-Reset Actions Chapter 17. I/O Support Functions 17-9 Externally Initiated Functions I/o-system reset, which is an externally initiated function, is described in the section "I/O-System Reset" on page 17-6. Initial Program Loading Initial program loading (IPL) provides a manual means for causing a program to be read from a designated device and for initiating execution of that program. Some models may provide additional controls and indications relating to IPL; this additional information is specified in the System Library publication for the model. IPL is initiated manually by setting the load-unitaddress controls to a four-digit number to designate an input device and by subsequently activating the load-clear or load-normal key. Activating the load-clear key causes a clear reset to be performed on the configuration. Activating the load-normal key causes an initial CPU reset to be performed on this CPU, CPU reset to be propagated to all other CPUs in the configuration, and a subsystem reset to be performed on the remainder of the configuration. In the loading part of the operation, after the resets have been performed, this CPU enters the load state. This CPU does not necessarily enter the stopped state during performance of the reset. The load indicator is on while the CPU is in the load state. • Subsequently, if conditions allow, a read operation is initiated from the designated input device and associated subchannel. The read operation is executed as if a START SUBCHANNEL instruction were executed that designated (1) the subchannel corresponding to the device number specified by the load-unit-address controls and (2) an ORB containing all zeros, except for a byte of all ones in the logical-path mask field. The ORB parameters are interpreted by the channel subsystem as follows: Interruption parameter: all zeros Subchannel key: all zeros Suspend control: zero (suspension not allowed) ccw format: zero ccw prefetch: zero (prefetching not allowed) 17-10 ESAj370 Principles of Operation Initial-status-interruption control: zero (no request) Address-limit-checking control: zero (no checking) Suppress suspended interruption: zero (suppression not allowed) Logical-path mask: ones (all channel paths logically available) Incorrect-length-suppression mode: zero (ignored because format-O ccws are specified) Channel-program address: absolute address 0 The frrst ccw to be executed may be either an actuat ccw stored at absolute location 0, or the frrst ccw to be executed may be implied. In either case, the effect is as if a format-O ccw were executed that had this format: Loc. ee eeeeeele eeeeeeee eeeeeeeeeeeeeeee e4 e11eeeee 1IIIIIIIIeeeeeeeeeee11eee 8 16 31 In the illustration above, the ccw specifies a read command with the modifier bits zeros, a data address of 0, a byte count of 24, the chaincommand flag one, the suppress-incorrect-Iengthindication flag one, the chain-data flag zero, the skip flag zero, the program-controlled-interruption (PCI) flag zero, the indirect-data-address (IDA) flag zero, and the suspend flag zero. The ccw fetched, as a result of command chaining, from location 8 or 16, as well as any subsequent ccw in the IPL sequence, is interpreted the same as a ccw in any I/O operation, except that any PCI flags that are specified in the IPL channel program are ignored. At the time the subchannel is made start-pending for the IPL read, it is also enabled, which ensures proper handling of subsequent status from the device by the channel subsystem and facilitates subsequent I/O operations using the IPL device. (Except for the subchannel used by the IPL I/O operation, each subchannel must frrst be made enabled by MODIFY SUBCHANNEL before it can accept a start function or any status from the device.) When the IPL subchannel becomes statuspending for the last operation of the IPL channel program, no I/o-interruption condition is generated. Instead, the subsystem 10 is stored in absolute locations 184-187, zeros are stored in absolute locations 188-191, and the subchannel is cleared of the pending status as if TEST SUBCHANNEL had been executed, but without storing info1lllation usually stored in an IRB. If the subchannel-status field is all zeros and the device-status field contains only the channel-end indication, with or without the device-end indication, the IPL I/O operation is considered to be completed successfully. If the device-end status for the IPL I/O operation is provided separately after channel-end status, it causes an I/o-interruption condition to be generated. When the IPL I/O operation is completed successfully, a new psw is loaded from absolute locations 0-7. If the psw loading is successful and if no malfunctions are recognized which preclude the completion of IPL, then the CPU leaves the load state, and the load indicator is turned off. If the rate control is set to the process position, the CPU enters the operating state, and CPU operation proceeds under control of the new psw. If the rate control is set to the instruction-step. position, the CPU enters the stopped state, with the manual indicator on, after the new psw has been loaded. If the IPL I/O operation or the psw loading is not completed successfully, the CPU remains in the load state, and the load indicator remains on. IPL does not complete when any of the following occurs: • No subchannel contains a valid device number equal to the IPL device number specified by the load-unit-address controls. • A malfunction is detected in the CPU, main storage, or channel subsystem which precludes the completion of IPL. • Unsolicited alert status is presented by the device subsequent to the subchannel becoming start-pending for the IPL read and before the IPL subchannel becomes subchannel-active. The IPL read operation is not initiated in this case. • The IPL device appeared not operational on all available channel paths to the device, or there were no available channel paths. • The IPL device presented a status byte containing indications other than channel end, device end, status modifier, control-unit end, control unit busy, device busy, or retry status Whenever during the IPL I/O operation. control-unit end, control unit busy, or device busy is presented in the status byte, nonnal path-management actions are taken. • A subchannel-status indication other than PCI was generated during the IPL I/O operation. • The psw loaded from absolute locations 0-7 has a psw-format error of the type that is recognized early. Except in the cases of no corresponding subchannel for the device number entered or a machine malfunction, the subsystem ID of the IPL device is stored in absolute locations 184-187; otherwise, the contents of these locations are unpredictable. In all cases of unsuccessful IPL, the contents of absolute locations 0-7 are unpredictable. Subsequent to a successful IPL, the subchannel parameters contain the normal values as if an actual START SUBCHANNEL had been executed, designating the ORB as described above. Programming Notes: 1. The information read and placed at absolute locations 8-15 and 16-23 may be used as ccws for reading additional information during the IPL I/O operation: the ccw at location 8 may specify reading additional ccws elsewhere in storage, and the ccw at absolute location 16 may specify the transfer-in-channel command, causing transfer to these ccws. 2. The status-modifier bit has its normal effect during the IPL I/O operation, causing the channel subsystem to fetch and chain to the ccw whose address is 16 higher than that of the current ccw. This applies also to the initial chaining that occurs after completion of the read operation specified by the implicit ccw. 3. The psw that is loaded at the completion· of the IPL operation may be provided by the fust eight bytes of the IPL I/O operation or may be placed at absolute locations 0-7 by a subsequent ccw. 4. Activating the load-nonnal key implicitly specifies the use of the fust 24 bytes of main storage and the eight bytes at absolute locations 184-191. Since the remainder of the IPL program may be placed in any part of storage, it is possible to preserve such areas of storage as may be helpful in debugging or recovery. When the load-clear key is activated, the IPL program starts with a cleared machine in a known state, except that information on external storage remains unchanged. 5. When the psw at absolute location 0 has bit 14 set to one, the CPU is placed in the wait state after the IPL operation is completed; at that Chapter 17. I/O Support Functions 17-11 point, the load and manual indicators are off, and the wait indicator is on. Reconfiguration of the 1/0 System Reconfiguration of the I/O system is handled in a model-dependent manner. For example, changes may be made under program control, by using the model-dependent DIAGNOSE instruction; or manually, by using system-operator configuration controls; or by using a combination of DIAGNOSE and manual controls. The method used depends on the system model. The System Library publication for the system model specifies how the changes are made. The partitioning of channel paths because of reconfiguration is indicated by the setting of the PAM bits in the SCHIB stored if jSTORE SUBCHANNEL is executed (see the section "PathAvailable Mask (PAM)" on page 15-7). Status Verification The status-verification facility provides the channel subsystem with a means of indicating that a device has presented a device-status byte that has valid csc but that contained a combination of bits that was inappropriate when the status byte was presented to the channel subsystem. The indication provided to the program in the ESW by the channel subsystem is called device-status check. When the channel subsystem recognizes a device-status-check condition, an interface-control-check condition is also recognized. For a summary of the status combinations considered to be appropriate or inappropriate, see the System Library publication IBM System/360 and System/370 I/O Interface Channel to Control Unit OEMI, GA22-6974. Address-Limit Checking The address-limit-checking facility provides a storage-protection mechanism for I/O data accesses to storage that augments key-controlled protection. When address-limit checking is used, absolute storage is divided into two parts by a programcontrolled address-limit value. I/O data accesses can then be optionally restricted to only one of the two parts of absolute storage by the limit mode at each subchannel. The address-limit constraint operates at a higher priority than key-controlled protection so that I/O data accesses to the protected part of main storage are prevented even when the subchannel key is zero or matches the key in storage. 17-12 ESA/370 Principles of Operation The address-limit-checking facility consists of the following elements: • The I/0 instruction SET ADDRESS LIMIT. • The limit mode at each subchannel. • The address-limit-checking-control bit in the ORB. Execution of SET ADDRESS LIMIT passes the contents of general register 1 to the address-limitchecking facility to be used as the address-limit value. Bits 0 and 16-31 of general register 1 must contain zeros to designate a valid absolute address on a 64K-byte boundary; otherwise, an operand exception is recognized, and execution of the instruction is suppressed. The limit mode at each subchannel indicates the manner in which address-limit checking is to be performed. The limit mode is set by placing the desired value in bits 9-10 of word 1 in the SCHIB and executing MODIFY SUBCHANNEL. The settings of these bits in the SCHIB have the following meanings: 00 No limit checking (initialized value). 01 Data address must be equal to or greater than the current address limit. 10 Data address must be less than the current address limit. 11 Reserved. This combination of limit-mode bits causes an operand exception· to be recognized when MODIFY SUBCHANNEL is executed. The address-limit-checking-control bit in the ORB (bit 11 of word 1) specifies whether address-limit checking is to be used for the start function that is accepted when execution of START SUBCHANNEL causes the contents of the ORB to be passed to the sub channel. If the address-limit-checking-control bit is zero when the contents of the ORB are passed, address-limit checking is not ·specified for that start function. If the bit is one, address-limit checking is specified and is under the control of the current address limit and the current setting of the limit mode at the sub channel. During the performance of the start function, an attempt to access an absolute storage location for data that is protected by an address limit (either high or low) is recognized as an address-limit violation, and the access is not allowed. A programcheck condition is recognized, and channel-program I execution is terminated, just as when an attempt is made to access an invalid address. Configuration Alert The configuration-alert facility provides a detection mechanism for devices that are not associated with a subchannel in the configuration. The configuration-alert facility notifies the program by means of a channel report that a device which is not associated with a subchannel has attempted to communicate with the program. Each device must be assigned to a subchannel during an installation procedure; otherwise, the channel subsystem is unable to generate an I/o-interruption condition for the device. This is because the I/o-interruption code contains the subchannel number which identifies the particular device causing the I/o-interruption condition. When a device that is not associated with a subchannel attempts to communicate with the channel subsystem, ~the configuration-alert facility generates a channel report in which the unassociated device is identified. For a description of the means by which the program is notified of a pending channel report and how the information in the channel report is retrieved, see the section "Channel Report" on page 17-14. Incorrect-Length-Indication Suppression The incorrect-length-indication-suppression facility allows the indication of incorrect length for immediate operations to be suppressed in the same manner when using format-l ccws as when using format-O CCws or ccws in the System/370 mode. When the incorrect-length-indication-suppression facility is installed, bit 24, word 1 of the ORB specifies whether the channel subsystem is to suppress the indication of incorrect length for an immediate operation when format-l ccws are used or whether this indication will remain under the control of the SLI flag of the current ccw (as is the case for ccws not executed as immediate operations). This bit provides the capability for a channel program to operate in the same manner regarding the indication of incorrect length regardless of whether format-O or format-l ccws are used. Channel-Subsystem Recovery The channel subsystem provides a recovery mechanism for extensive detection of malfunctions and other conditions to ensure the integrity of channelsubsystem operation and to achieve automatic recovery of some malfunctions. Various reporting methods are used by the channel-subsystem recovery mechanism to assist in program recovery, maintenance, and repair. The method used to report a particuiar malfunction or other condition is dependent upon the severity of the malfunction or other condition and the degree to which the malfunction or other condition can be isolated. A malfunction or other condition in the channel subsystem may be indicated to the program by information being stored by one of the following methods: 1. Information is provided in the IRB describing a condition that has been recognized by either the channel subsystem or device that must be brought to the attention of the program. Generally, this information is made available to the program by the execution of TEST SUBCHANNEL, which is usually executed in response to the occurrence of an I/O interruption. (See "Interruption Action" on page 16- 5,. for a defmition of the information stored, as well as Chapter 6, "Interruptions.") 2.. Information is provided in a channel report describing a machine malfunction affecting the identified facility within the channel subsystem. This information is made available to the program by the execution of STORE CHANNEL REPORT WORD, which is usually executed in response to the occurrence of a machine-check (See Chapter 11, "Machineinterruption. Check Handling," for a description of the machine-check-interruption mechanism and the contents of the machine-check-interruption code.) 3. Information is provided in a channel report describing a malfunction or other condition affecting a collection of channel-subsystem facilities. This information is made available to the program as indicated in item 2. 4. Information is provided in the machine-checkinterruption code (MCIC) describing a malfunction affecting the continued operational integrity of the channel subsystem. (See the section "Channel-Subsystem Damage" in Chapter 11, "Machine-Check Handling.") Chapter 17. I/O Support Functions 17-13 5. Infonnation is provided in the MCIC describing a malfunction affecting the continued operational integrity of a process or of the system. (See the sections "Instruction-Processing Damage" and "System Damage" in Chapter 11, "Machine-Check Handling.") associated machine-check interruption does not occur. A machine-check interruption indicating that a channel report is pending occurs only if the machine-check mask (psw bit 13) and the channelreport-pending subclass mask (bit 3 of control register 14) are both ones. Channel reports are used to report malfunctions or other conditions only when the use of the I/o-interruption facility is not appropriate and in preference to reporting channel-subsystem damage, instruction-processing damage, or system damage. If the channel report that is made pending is not an initial channel report, a machine-cheek-interruption condition is not generated. The CRW that is presented to the program in response to the frrst STORE CHANNEL REPORT WORD instruction that is executed after a machine-check interruption mayor may not be part of the initiaJ. channel report that caused the machine-check condition to be generated. A pending channel-report word is cleared by any CPU executing STORE CHANNEL REPORT WORD~ regardless of whether a machine-check interruption has occurred in any CPU. If a CRW is not pending and STORE CHANNEL REPORT WORD is executed, condition code I is set, and zeros are stored at the location designated by the secondoperand address. During execution of STORE CHANNEL REPORT WORD as a result of receiving a machine-check interruption, condition code 1 may be set, and zeros may be stored because ( I) the related channel report has been cleared by another CPU or (2) a malfunction occurred during the generation of a channel report. In the latter case, if, during a subsequent attempt, a valid channel report can be made pending, an additional machine-checkinterruption condition is generated. Channel Report When a malfunction or other condition affecting elements of the channel subsystem has been recognized, a channel report is generated. Execution of recovery actions by the program or by external means may be required to gain recovery from the error condition. The channel report indicates the source of the channel report and the recovery state to the extent necessary for detennining the proper recovery action. A channel report consists of one or more channel-report words (CRWS) that have been generated from an analysis of the malfunction or other condition. The inclusion of two or more CRWs within a channel report is indicated by the chaining flag being stored as one in all of the CRWS of the channel report except the last one in the chain." . When a channel report is made pending by the channel subsystem for retrieval and analysis by the program (by means of the execution of STORE CHANNEL REPORT WORD), a malfunction or other condition that affects the normal operation of one or more of the channel-subsystem facilities has been recognized. If the channel report that is made pending is an initial channel report, a machinecheck-interruption condition is generated that indicates one or more CRWS are pending at the channel subsystem. A channel report is initial either if it is the frrst channel report to be generated after the most recent I/o-system reset or if no previously generated reports are pending and the last STORE CHANNEL REPORT WORD instruction that was executed resulted in the setting of condition code I, indicating that no channel report was pending. When the machine-check interruption occurs and bit 9 of the machine-cheek-interruption code (channel report pending) is one, a channel report is pending. If the program clears the frrst CRW of a channel report before the associated machine-check interruption has occurred, some models may reset the machine-cheek-interruption condition, and the 17-14 ESAj370 Principles of Operation When a channel report consists of mUltiple chained CRWS, they are presented to the program in the same order that they are placed in the chain by the channel subsystem as the result of consecutive executions of STORE CHANNEL REPORT WORD. If, for example, the frrst CRW of a chain is presented to the program as a result of executing STORE CHANNEL REPORT WORD, then the CRW that is presented as a result of the next execution of STO RE CHANNEL REPORT WORD is the second CRW of the same chain, and not a CRW that is part of another channel report. Channel reports are not presented to the program in any special order, except for channel reports whose ftrst or only CRW indicates the same reporting-source code and the same reporting-source ID. These channel reports are presented to the program in the same order that they are generated by the channel subsystem, but they are not necessarily presented consecutively. For example, suppose the channel subsystem generates channel reports A, B, and C, in that order. The frrst CRW of channel reports B and C indicates the same reporting-source code and the same reportingsource ID. Channel report B is presented to the program before channel report C is presented, but channel report A may be presented after channel report B and before channel report C. Programming Notes: I. The information that is provided in a single CRW may be made obsolete by another CRW that is subsequently generated for the same channel-subsystem facility. Therefore, the information that is provided in one channel report should be interpreted in light of the information provided by all of the channel reports that are pending at a given instant. "2. A machine-cheek-interruption condition is not always generated when a channel report is made pending. The conditions that result in a machine-check-interruption condition being generated are described earlier in this section. 3. After a machine-check interruption has occurred with bit 9 of the machine-checkinterruption code set to one, STORE CHANNEL REPORT WORD should be executed repeatedly until all of the pending channel reports have been cleared and condition code I has been set. 4. A cRw-overflow condition can occur if the program does not execute successive STORE CHANNEL REPORT WORD instructions in a timely manner after the machine-check interruption occurs. 5. The number of CRWS that can be pending at the same time is model-dependent. During the existence of an overflow condition, CRws that would have otherwise been made pending are lost and are never presented to the program. Channel-Report Word The channel-report word (CRW) provides information to the program that can be used to facilitate the recovery of an I/O operation, a device, or some element of the channel subsystem, such as a channel path or sub channel. The format of the CRW is as follows. Bits 0 and 8-9 are reserved and are always stored as zeros. 1 2 3 4 8 Ie 16 subsystem to be solicited if it is made pending as the direct result of some action that is taken by the program. When bit I is zero, the CRW is unsolicited and has been made pending as the result of an action taken by the channel subsystem that is independent of the program. Bit 2, when one, indicates that a cRw-overflow condition has been recognized since this CRW became pending and that one or more CRWs have been lost. This bit is one in the CRW that has most recently been set pending when the overflow condition is recognized. When bit 2 is zero, a cRw-overflow condition has not been recognized. Overflow (R): A CRW that is part of a channel report is not made pending, even though the overflow condition does not exist, if an overflow condition prevented a previous CRW of that report from being made pending. Chaining (C): Bit 3, when one, and when the overflow flag is zero, indicates chaining of associated CRWs. Chaining of CRWs is indicated whenever a malfunction or other condition is described by more than a single CRW. The chaining flag is zero if the channel report is described by a single CRW or if the CRW is the last CRW of a channel report. The chaining flag is not meaningful if the overflow bit, bit 2, is one. Reporting-Source Code (RSC): Bits 4-7 identify the channel-subsystem facility that has been associated with the malfunction or other condition. Some facilities are further identified in the reporting-source-identification field (see below). The following combinations of bits identify the facilities: 4 0 0 0 I Bits 5 0 0 I 0 6 I I 0 0 7 Designation 0 I 0 I Monitoring facility Subchannel Channel path Configuration-alert facility All other bit combinations in the reporting-sourcecode field are reserved. Reporting-source 10 e Solicited CRW (S):. Bit I, when one, indicates a solicited CRW. A CRW is considered by the channel 31 Chapter 17. I/O Support Functions 17-15 Error-Recovery Code (ERC): Bits 10-15 contain the error-recovery code which defmes the recovery state of the channel-subsystem facility identified in the reporting-source code. This field, when used in conjunction with the reporting-source code, can be used by the program to determine whether the identified facility has already· been recovered and is available for use or whether recovery actions are still required. The following error-recovery codes are possible: Bits 10 11 12 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 15 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 State Available Initialized Temporary error Installed parameters initialized Terminal Permanent error with facility not initialized Permanent error with facility initialized All other bit combinations in theerror-recoverycode field are reserved. The specific ineaning of each .error-recovery code depends on the particular reporting-source code that accompanies it in a CRW. The error-recovery codes are defmed as follows: Available: The identified facility is in the same state that the program would expect if the CRW had not been generated. The identified facility is in the same state that existed immediately following the I/o-system reset that was part of the most recent system IPL. Initialized: Temporary: The identified facility is not operating in a normal manner or has recognized the occurrence of an abnormal event. It is expected that subsequent actions either will restore the facility to 17-16 ESA/370 Principles of Operation normal operation or will record the appropriate information describing the abnormal event. This state is the same as the initialized state, except that one or more parameters that are associated witl:- the facility and that are not modifiable by the program may have been changed Installed Parameters Initialized: Terminal: The identified facility is' in a state such that an operation which was in progress can neither be completed nor terminated in the normal manner. Permanent Error With Facility Not Initialized: The identified facility is in a state of malfunction, and the channel subsystem has not caused a reset function to be perfonned for that facility. Permanent Error With Facility Initialized: The identified facility is in a state of malfunction, and the channel subsystem has caused or may have caused a reset function to be performed for that facility. Reporting-Source ID (RSID): Bits 16-31 contain the reporting-source ID which· may, depending upon the malfunction or other condition and on the reporting-source code, either further identify the affected channel-subsystem facility or provide additional information describing the malfunction or other condition. The RSID field has the following format as a function of the bit settings of the reporting-source code. Reporting-Source Code 4 6 7 5 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 0 Note: xxxx xxxx xxxx xxxx yyyy yyyy Reporting-Source ID Bits 16-31 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 yyyy yyyy 0000 0000 yyyy yyyy Subchannel number Channel-path ID (CHPID) Appendix A. Number Representation and Instruction-Use Examples Number Representation . . . . . . . . . . . . A-2 Binary Integers . . . . . . . . . . . . . . . . A -2 Signed Binary Integers . . . . . . . . . . A -2 Unsigned Binary Integers . . . . . . . . A-4 Decimal Integers . . . . . . . . . . . . . . . A-S Floating-Point Numbers . . . . . . . . . . A-S Conversion Example . . . . . . . . . . . . A-7 Instruction-Use Examples . . . . . . . . . . . A-7 Machine Format . . . . . . . . . . . . . . . A-7 Assembler-Language Format . . . . . . . . A-7 Addressing Mode in Examples . . . . . A-8 General Instructions . . . . . . . . . . . . . . A -8 Add Halfword (AH) . . . . . . . . . . . . . A-8 AND (N, NC, NI, NR) . . . . . . . . . . A-8 NI Example . . . . . . . . . . . . . . . . A-8 Linkage Instructions (BAL, BALR, BAS, BASR, BASSM, BSM) . . . . . . . . . . A-8 Other BALR and BASR Examples A-IO Branch and Stack (BAKR) . . . . . . . . A-IO BAKR Example 1 . . . . . . . . . . . A-ll BAKR Example 2 . . . . . . . . . . . A-ll BAKR Example 3 . . . . . . . . . . . A-12 Branch on Condition (BC, BCR) . . . . A-12 A-12 Branch on Count (BCT, BCTR) Branch on Index High (BXH) . . . . . . A-13 BXH Example 1 . . . . . . . . . . . . A-I3 BXH Example 2 . . . . . . . . . . . . A-13 A-I4 Branch on Index Low or Equal (BXLE) BXLE Example 1 . . . . . . . . . . . A-I4 BXLE Example 2 . . . . . . . . . . . A-14 Compare Halfword (CH) . . . . . . . . . A-IS Compare Logical (CL, CLC, CLI, CLR) A-IS CLC Example . . . . . . . . . . . . . A-IS CLI Example . . . . . . . . . . . . . . A -16 CLR Example . . . . . . . . . . . . . A-16 Compare Logical Characters under Mask . . . . . . . . . . . . . . . . . . A-16 (CLM) Compare Logical Long (CLCL) . . . . . A -17 . . . . . . . . A-18 Convert to Binary (CVB) Convert to Decimal (CVD) . . . . . . . A-18 Divide (D, DR) . . . . . . . . . . . . . . A-19 Exclusive OR (X, XC, XI, XR) . . . . . A-19 XC Example . . . . . . . . . . . . . . A-I9 XI Example . . . . . . . . . . . . . . . A-20 Execute (EX) . . . . . . . . . . . . . . . A-21 Insert Characters under Mask (ICM) .. A-21 Load (L, LR) . . . . . . . . . . . . . . . A-22 Load Address (LA) . . . . . . . . . . . . A-22 Load Halfword (LH) . . . . . . . . . . . A-23 Move (MVC, MVI) . . . . . . . . . . . . A-23 MVC Example . . . . . . . . . . . . . MVI Example . . . . . . . . . . . . . Move Inverse (MVCIN) . . . . . . . . . Move Long (MVCL) . . . . . . . . . . . Move Numerics (MVN) . . . . . . . . . Move with Offset (MVO) . . . . . . . . Move Zones (MVZ) . . . . . . . . . . . Multiply (M, MR) . . . . . . . . . . . . Multiply Halfword (MH) . . . . . . . . . OR (0, OC, 01, OR) . . . . . . . . . . . 01 Example . . . . . . . . . . . . . . . Pack (PACK) . . . . . . . . . . . . . . . Shift Left Double (SLDA) . . . . . . . . Shift Left Single (SLA) . . . . . . . . . . Store Characters under Mask (STCM) Store Multiple (STM) '" . . . . . . . . Test under Mask (TM) . . . . . . . . . . Translate (TR) . . . . . . . . . . . . . . . Translate and Test (TRT) . . . . . . . . Unpack (UNPK) . . . . . . . . . . . . . Decimal Instructions . . . . . . . . . . . . . Add Decimal (AP) . . . . . . . . . . . . Compare Decimal (CP) . . . . . . . . . . Divide Decimal (DP) . . . . . . . . . . . Edit (ED) . . . . . . . . . . . . . . . . . . Edit and Mark (EDMK) . . . . . . . . . ........ . Multiply Decimal (MP) Shift and Round Decimal (SRP) Decimal Left Shift . . . . . . . . . . . Decimal Right Shift . . . . . . . . . . Decimal Right Shift and Round '" Multiplying by a Variable Power of 10 Zero and Add (ZAP) . . . . . . . . . . . Floating-Point Instructions . . . . . . . . . Add Normalized (AD, ADR, AE, AER, AXR) . . . . . . . . . . . . . . . . . . . Add Unnormalized (AU, AUR, AW, AWR) . . . . . . . . . . . . . . . . . . . Compare (CD, CDR, CE, CER) ... . Divide (DD, DDR, DE, DER) . . . . . Halve (HDR, HER) . . . . . . . . . . . Multiply (MD, MDR, ME, MER, MXD, MXDR, MXR) . . . . . . . . . . . . . Floating-Point- Number Conversion Fixed Point to Floating Point· . . . . Floating Point to Fixed Point Multiprogramming and Multiprocessing Examples . . . . . . . . . . . . . . . . . . . Example of a Program Failure Using OR Innrnediate ............... . A-23 A-24 A-24 A-2S A-2S A-26 A-26 A-27 A-27 A-28 A-28 A-28 A-28 A-29 A-29 A-30 A-30 A-30 A-3I A-33 A-33 A-33 A-33 A-34 A-34 A-3S A-36 A-36 A-36 A-37 A-37 A-37 A-38 A-38 Appendix A. Number Representation and Instruction-Use Examples A-I A-38 A-39 A-39 A-40 A-40 A-40 A-41 A-41 A-4I A-42 A-42 Conditional Swapping Instructions (CS, CDS) . . . . . . . . . . . . . . . . . . . A-43 Setting a Single Bit . . . . . . . . . . . A-43 Updating Counters .. A-44 Bypassing Post and Wait . A-44 A-44 Bypass Post J:.toutine Bypass Wait Routine A-45 Lock/Unlock . . . . . . . . . . . . . . . . A-45 Lock/Unlock with LIFO Queuing for Contentions . . . . . . . . . . . . . . A-45 Lock/Unlock with FIFO Queuing for Contentions A-46 Free-Pool Manipulation . . . . . . A-47 Number Representation The following addition examples illustrate two'scomplement arithmetic and overflow conditions. Only eight bit positions are used. Binary Integers 1. Signed Binary Integers Signed binary integers are most commonly represented as halfwords (16 bits) or words (32 bits). In both ,lengths, the leftmost bit (bit 0) is the sign of the number. The remaining bits (bits 1-15 for halfwords and 1-31 for words) are used to specify the magnitude of the number. Binary integers are also referred to as fixed-point numbers, because the . radix point (binary point) is considered to be fixed at the right, and any scaling is done by the programmer. Positive binary integers are in true binary notation with a zero sign bit. Negative binary integers are in two's-complement notation with a one bit in the sign position. In all cases, the bits between the sign bit and the leftmost significant bit of the integer are the same as the sign bit (that is, all zeros for positive numbers, all ones for negative numbers). +92 = 0101 1100 2. 3. 4. 6. 00000000 00011010 from 1 00000000 00000000 Negative binary integers are changed to positive in the same manner. A -2 ESA/370 Principles of Operation -57 = 1100 0111 -35 = 1101 1101 -92 = 1010 0100 No overflow -- carry into leftmost position and carry out +26 0 000 00e0 0001 1010 Invert 1 111 1111 1110 0101 Add 1 1 This is equivalent to subtracting the number: +35 = 0010 0011 -57 = 1100 0111 -22 = 1110 1010 Sign change only -- no carry into leftmost position and no carry out 5. 1 111 1111 1110 0110 (Two's complement form) (S is the sign bit.) +57 = 0011 1001 -35 = 1101 1101 +22 = 0001 0110 No overflow -- carry into leftmost position and carry out Negative binary integers are formed in two'scomplement notation by inverting each bit of the positive binary integer and adding one. As an example using the halfword format, the binary number with the decimal value + 26 is made negative (-26) in the following manner: -26 +57 = 0011 1001 +35 = 0010 0011 +57 = 0011 1001 +92 = 0101 1100 +149 =*1001 0101 *Overflow -- carry into leftmost position, no carry out -57 = 1100 0111 -92 = 1010 0100 -149 =*0110 1011 *Overflow -- no carry into leftmost position but carry out The presence or absence of an overflow condition may be recognized from the carries: • There is ~o overflow: 1. If there is no carry into the leftmost bit position and no carry out (examples I and 3). 2. If there is a carry into the leftmost position and also a carry out (examples 2 and 4). • There is an overflow: 1. If there is a carry into the leftmost position but no carry out (example 5). 2. If there is no carry into the leftmost position but there is a carry out (example 6). The following are l6-bit signed binary integers. The fust is the maximum positive l6-bit binary integer. The last is the maximum negative l6-bit 231-1 = 2 147 483 647 = 0 111 216 65 536 = 0 000 20 1 = 0 00e o 0 = 0 000 _20 -1 = 1 111 _21 -2 = 1 111 _216 -65 536 = 1 111 -231+1 = -2 147 483 647 = 1 00e _2 31 = -2 147 483 648 = 1 0e0 1111 0000 0e00 0000 1111 1111 1111 0e00 e000 1111 e00e e000 e000 1111 1111 1111 e000 e000 1111 0e01 0000 0000 1111 1111 1111 0000 0000 binary integer (the negative l6-bit binary integer with the greatest absolute value). 215 -1 = 32,767 = 0 111 1111 1111 1111 20 1 = 0 000 0000 0000 0001 o 0 = 0 000 0000 0000 0000 _20 -1 = 1 111 1111 1111 1111 _2 15 = -32,768 = 1 000 0000 0000 0000 Figure A-I illustrates several 32-bit signed binary integers arranged in descending order. The fust is the maximum positive binary integer that can be represented by 32 bits, and the last is the maximum negative binary integer that can be represented by 32 bits. 1111 0000 0000 0000 1111 1111 00e0 0000 0000 1111 0000 0000 0000 1111 1111 0000 0000 0000 1111 eee0 0ee0 0ee0 1111 1111 0ee0 00e0 00e0 1111 0000 0001 0000 1111 1110 0e00 0001 0000 Figure A-I. 32-Bit Signed Binary Integers Appendix A. Number Representation and Instruction-Use Examples A-3 Unelgned Binary Integers Certain instructions, such as ADD LOGICAL, treat binary integers as unsigned rather than signed. Unsigned binary integers have the same fonnat as signed binary integers, except that the leftmost bit is interpreted as another numeric bit rather than a sign bit. There is no complement notation because all unsigned binary integers are considered positive. The following examples illustrate the addition of unsigned binary integers. Only eight bit positions are used. The examples are numbered the same as the corresponding examples for signed binary integers. 1. 3. 234 = 111e 1e1e 4. 5. 6. 199 = 11ee e111 164 = 1e1e e1ee 363 =*e11e 1e11 *Carry out of leftmost position 57 = ee11 1ee1 221 = 11e1 11e1 A carry out of the leftmost bit position mayor may not imply an overflow, depending on the application. 278 =*eeel e11e *Carry out of leftmost position 1111 eeee 1111 eeee eeee eeee Figure A-2. 32-Bit Unsigned Binary Integers A-4 57 = ee11 1ee1 92 = e1e1 nee 149 = 1ee1 e1e1 57 = ee11 1ee1 35 = ee1e ee11 232-1 4 294 967 295 = 1111 2 147 483 648 = 1eee 231 231_1 2 147 483 647 = e111 65 536 = eeee 216 1 = eeee 2° e = eeee e = 199 = 11ee e111 221 = 11tH 11e1 42e =*le1e e1ee *Carry out of leftmost position 92 = e101 11ee 2. 35 = ee1e ee11 199 = 11ee e111 ESAj370 Principles of Operation 1111 eeee 1111 eeee eeee eeee Figure A-2 illustrates several 32-bit unsigned binary integers arranged in descending order. 1111 eeee 1111 eeel eeee eeee 1111 eeee 1111 aeee aeee aeee 1111 eeee 1111 eeee eeee eaee 1111 eeee 1111 eeae eeee eeee 1111 eeee 1111 eeee eeel eeee Decimal Integers The following are some examples of decimal integers shown in hexadecimal notation: Decimal integers consist of one or more decimal digits and a sign. Each digit and the sign are represented by a 4-bit code. The decimal digits are in binary-coded decimal (Bcn) form, with the values 0-9 encoded as 0000-1001. The sign is usually represented as 1100 (c hex) for plus and 1101 (n hex) for minus. These are the preferred sign codes, which are generated by the machine for the results of decimal-arithmetic operations. There are also several alternate sign codes (1010, 1110, and 1111 for plus; 1011 for minus). The alternate sign codes are accepted by the machine as valid in source operands but are not generated for results. Decimal Value Decimal integers may have different lengths, from one to 16 bytes. There are two decimal formats: packed and zoned. In the packed format, each byte contains two decimal digits, except for the rightmost byte, which contains the sign code in the right half. For decimal arithmetic, the number of decimal digits in the packed format can vary from one to 31. Because decimal integers must consist of whole bytes and there must be a sign code on the right, the number of decimal digits is always odd. If an even number of significant digits is desired, a leading zero must be inserted on the left. eeeee In the zoned format, each byte consists of a decimal digit on the right and the zone code 1111 (F hex) on the left, except for the rightmost byte where the sign code replaces the zone code. Thus, a decimal integer in the zoned format can have from one to 16 digits. The zoned format may be used directly for input and output in the extended binary-coded-decimal interchange code (EBCDIC), except that the sign must be separated from the rightmost digit and handled as a separate character. For positive (unsigned) numbers, however, the sign can simply be represented by the zone code of the rightmost digit because the zone code is one of the acceptable alternate codes for plus. In either format, negative decimal integers are represented in true notation with a separate sign. As for binary integers, the radix point (decimal point) of decimal integers is considered to be fixed at the right, and any scaling is done by the programmer. Packed Format +123 Zoned Format 12 3C F1 F2 C3 or or 12 3F F1 F2 F3 -4321 e4 32 10 F4 F3 F2 01 +eeee5e ee ee e5 ec Fe Fe Fe Fe F5 ce or or ee ee e5 eF Fe Fe Fe Fe F5 Fe 70 07 -7 ee ee ec Fe Fe Fe Fe ce or or ee ee eF Fe Fe Fe Fe Fe Under some circumstances, a zero with a minus sign (negative zero) is produced. For example, the multiplicand: ee 12 3D (-123) times the multiplier: ec (+e) generates the product: ee e0 eo (-e) because the product sign follows the algebraic rule of signs even when the value is zero. A negative zero, however, is equivalent to a positive zero in that they compare equal in a decimal comparison. Floating-Point Numbers A floating-point number is expressed as a hexadecimal fraction multiplied by a separate power of 16. The term floating point indicates that the placement, of the radix (hexadecimal) point, or scaling, is automatically maintained by the machine. The part of a floating-point number which represents the significant digits of the number is called the fraction. A second part specifies the power (exponent) to which 16 is raised and indicates the location of the radix point of the number. The fraction and exponent may be represented by 32 bits (short format), 64 bits (long format), or 128 bits (extended format). Appendix A. Number Representation and Instruction-Use Examples A-5 istic can vary from 0 to 127, permitting the exponent to vary from -64 through 0 to + 63. This provides a scale multiplier in the range of 16-64 to 16 + 63. A nonzero fraction, if normalized, -has a value less than one and _greater than or equal to 1/16, so that the range covered by the magnitude M of a normalized floating-point number is: Short Floating-Point Number S Characteristic 6-Digit 'ractionl o 1 B I 31 Long Floating-Point Number 16- 65 S M< 16 63 II----------~-----/------~ S Characteristic o 1 14-Digit Fraction /-------..1 In decimal terms: 16- 65 is approximately 5.4 x 10- 79 63 B 16 63 is approximately 7.2 x 10 75 More precisely, Extended Floating-Point Number High-Order Part IT----------~-----/------~ High-Order Leftmost 14 Digits S Characteristic of 2B-Digit Fraction o /------l 1 B 63 16- 65 IS M S (1 - 16- 6 ) x 16 63 In the long format: 16- 65 S M S (1 - 16- 14 ) x 16 63 In the extended format: Low-Order Part rI-----------.------/------~ Low-Order Rightmost 14 Digits S Characteristic of 2B-Digit Fraction /-------l 72 64 In the short format: 127 A floating-point number has two signs: one for the fraction and one for the exponent. The fraction sign, which is also the sign of the entire number, is the leftmost bit of each format (0 for plus, 1 for minus). The numeric part of the fraction is in true notation regardless of the sign. The numeric part is contained in bits 8-31 for the short format, in bits 8-63 for the long format, and in bits 8-63 followed by bits 72-127 for the extended format. The exponent sign is obtained by expressing the exponent in excess-64 notation; that is, the exponent is added as a signed number to 64. The resulting number is called the characteristic. It is located in bits 1-7 for all formats. The character- 16- 65 S M S (1 - 16- 28 ) x 16 63 Within a given fraction length (6, 14, or 28 digits), a floating-point operation will provide the greatest precision if the fraction is normalized. A fraction is normalized when the leftmost digit (bit positions 8, 9, 10, and 11) is nonzero. It is unnormalized if the leftmost digit contains all zeros. If normalization of the operand is desired, the floating-point instructions that provide automatic normalization are used. This automatic normalization is accomplished by left-shifting the fraction (four bits per shift) until a nonzero digit occupies the leftmost digit position. The characteristic is reduced by one for each digit shifted. Figure A-3 illustrates sample normalized short floating-point numbers. The last two numbers represent the smallest and the largest positive normalized numbers. 1.0 = +1/16x16 1 = 0 100 0001 0001 0000 0000 0000 0.5 = +B/16x16° = 0 100 0000 1000 0000 00000000 1/64 = +4/16x16- 1 = 0 011 1111 0100 0000 0000 0000 0.0 = +0 x16- 64 = 0 000 0000 0000 0000 0000 0000 -15.0 = -15/16x16 1 = 1 100 0001 1111 0000 0000 0000 79 5.4x10- = +1/16x16- 64 = 0 000 0000 0001 0000 0000 0000 7.2x10 75 = (1-16- 6 )x16 63 = 0 111 1111 1111 1111 1111 1111 Figure A-6 A-3. Normalized Short Floating-Point Numbers ESA/370 Principles of Operation 0000 0000 0000 0000 0000 0000 1111 00002 00002 00002 00002 00002 00002 11112 Conversion Example Convert the decimal number 59.25 to a short floating-point number. (In another appendix are tables for the conversion of hexadecimal and decimal integers and fractions.) 1. The number is separated into a decimal integer and a decimal fraction. 59.25 = 59 plus 0.25 2. The decimal integer is converted to its hexadecimal representation. 59u = 3B16 3. The decimal fraction is converted to its hexadecimal representation. o. 25 u = 0. 41 6 4. The integral and fractional parts are combined and expressed as a fraction times a power of 16 (exponent). 3B.416 = 0.3B416 X 16 2 5. The characteristic is developed from the exponent and converted to binary. base + exponent = characteristic 64 + 2 = 66 = 1000010 6. The fraction is converted to binary and grouped hexadecimally. .3B416 = .0011 1011 0100 7. The characteristic and the fraction are stored in the short format. The sign position contains the sign of the fraction. S Char o 1000010 Fraction 0011 1011 0100 0000 0000 0000 Examples of instruction sequences that may be used to convert between signed binary integers and floating-point numbers are shown in the section "Floating-Point-Number Conversion" later in this appendix. Instruction-Use Examples The following examples illustrate the use of many of the unprivileged instructions. Before studying one of these examples, the reader should consult the instruction description. The instruction-use ex~ples are written principally for assembler-language progranuners, to be used in conjunction with the appropriate assemblerlanguage publications. Most examples present one particular instruction, both as it is written in an assembler-language statement and as it appears when assembled in storage (machine format). Machine Format All machine-format values are given in hexadecimal Storage notation unless otherwise specified. addresses are also given in hexadecimal. Hexadecimal operands are shown converted into binary, decimal, or both if such conversion helps to clarify the example for the reader. Assembler-Language Format In assembler-language statements, registers and lengths are presented in decimal. Displacements, immediate operands, and masks may be shown in decimal, hexadecimal, or binary notation; for example, 12, X I C I, and B I 11 00 I represent the same value. Whenever the value in a register or storage location is referred to as "not significant," this value is replaced during the execution of the instruction. When ss-format instructions are written in the assembler language, lengths are given as the total number of bytes in the field. This differs from the machine defmition, in which the length field specifies the number of bytes to be added to the field address to obtain the address of the last byte of the field. Thus, the machine length is one less than the assembler-language length. The assembler program automatically subtracts one from the length specified when the instruction is assembled. In some of the examples, symbolic addresses are used in order to simplify the examples. In assembler-language statements, a symbolic address is represented as a mnemonic term written in all capitals, such as FLAGS, which may denote the address of a storage location containing data or program-control information. When symbolic addresses are used, the assembler supplies actual base and displacement values according to the progranuner's specifications. Therefore, the actual values for base and displacement are not shown in the assembler-language format or in the machinelanguage format. For assembler-language formats, in the labels that designate instruction fields, the letter "S" is used to indicate the combination of base and displacement fields for an operand address. (For example, S2 represents the combina- Appendix A. Number Representation and Instruction-Use Examples A-7 tion of B2 and D2.) In the machine-language format, the base and displacement address components are shown as asterisks (++++). AND (N, NC, NI, NR) Addressing Mode In Examples Except where otherwise specified, the examples assume the 24-bit addressing mode. When the Boolean operator AND is applied to two bits, the result is one when both bits are one; otherwise, the result is zero. When two bytes are ANDed, each pair of bits is handled separately; there is no connection from one bit position to another. The following is an example of ANDing two bytes: General Instructions First-operand byte: Second-operand byte: 0011 01012 0101 11002 (See Chapter 7 for a complete description of the general instructions.) Result byte: 0001 01002 Add Halfword (AH) The ADD HALFWORD instruction algebraically adds the contents of a two-byte field in storage to the contents of a register. The storage operand is expanded to 32 bits after it is· fetched and before it is used in the add operation. The expansion consists in propagating the leftmost (sign) bit 16 positions to the left. For example, assume that the contents of storage locations 2000-2001 are to be added to register 5. Initially: Register 5 ,?ontains 00 00 00 19 = 2510. Storage locations 2000-2001 contain FF FE -210. Register 13 contains 00 00 01 50. The format of the required instruction is: Machine Format 4A R1 5 X2 B2 Machine Format Op Code 12 94 FE B1 01 = Register 12 contains 00 00 18 00. Op Code NI Example A frequent use of the AND instruction is to set a particular bit to zero. For example, assume that storage location 4891 contains 0100 00112. To set the rightmost bit of this byte to zero without affecting the other bits, the following instruction can be used (assume that register 8 contains 00 00 48 90): 02 Del 66el Assembler Format Op Code D1(B1),12 NI 1(8),X'FE' When this instruction is executed, the byte in storage is ANDed with the immediate byte (the 12 field of the instruction): Location 4891: Immediate byte: 0100 00112 1111 11102 Assembler Format Result: 0100 00102 Op Code R1,02(X2,B2) The resulting byte, with bit 7 set to zero, is stored back in location 4891. Condition code 1 is set. AH 5,X'6B0'(13,12) Linkage Instructions (BAL, BALR, Mter the instruction is executed, register 5 contains 00 00 00 17 = 231 a. Condition code 2 is set to indicate a result greater than zero. A-8 ESA/370 Principles of Operation BAS,BASR, BASSM, BSM) Four unpriVileged instructions (BRANCH AND LINK, BRANCH AND SAVE, BRANCH AND SAVE AND SET MODE, and BRANCH AND SET MODE) are available, together with the unconditional branch (BRANCH ON CONDITION with a mask of 15), to provide linkage between subroutines. BRANCH AND LINK (BAL or BALR) is provided primarily for compatibility with programs written for System/370; BRANCH AND SAVE (BAS or BASR) is recommended instead .for programs which are to be executed using FSA/370. The instructions BRANCH AND SAVE AND SET MODE (BASSM) and BRANCH AND SET MODE (BSM) provide subroutine linkage together with switching between the 24-bit and the 31-bit addressing modes. The use of these instructions is discussed in a programming note at the end of the section "Subroutine Linkage without the Linkage Stack" in Chapter 5, "Program Execution." (See also the semiprivileged instruction BRANCH AND STACK.) For comparison with the RR-format instructions, the results of two RX -format instructions are also shown. The format of the BAL instruction is: Machine Format Op Code RI X2 B2 5 9 6 45 02 0901 Assembler Format Op Code Rl,02(X2,B2) The following example compares the operation of these instructions and of the unconditional~branch instruction BRANCH ON CONDITION (Be or BCR with a mask of 15). Assume that· each instruction in tum is located at the current instruction address, ready to be executed next. For the fIrst set of examples, the addressing-mode bit, psw bit 32, is initially zero (24-bit addressing in effect). For the second set, psw bit 32 is initially one (31-bit addressing). Assume also that general register 5 is to receive the linkage information, and that general register 6 contains the branch address. 5,(:)((:),6) BAL The BAS instruction has the same format, but the op code is 4D. The BCR instruction specifies only one register: Machine Format Op Code MI R2 F 6 (:)7 The format of the BALR instruction is: Machine Format Op Code Assembler Format Rl R2 5 6 (:)5 Op Code MI,R2 BCR 15,6 Assume that: Assembler Fonnat Register 5 contains BB BB BB BB. Op Code Rl,R2 Register 6 contains 82 46 8A CEo BALR 5,6 psw bits 32-63 contain The other linkage instructions in the RR format have the same format but different op codes: BASR (:)0 BASSM (:)C BSM (:)B 00 00 10 D6 (for 24-bit addressing). 80 00 10 D6 (for 31-bit addressing). Condition code is 012. Program mask is 11002. Appendix A. Number Representation and Instruction-Use Examples A-9 The effect of executing each instruction in tum is as follows: Other BALR and BASR Examples 24-Bit Mode Initially Instruction Register 5 8efore 88 88 88 8B 00 00 10 06 8CR 15,6 8AL 5,0(0,6) 8AS 5,0(0,6) 8ALR 5,6 8ASR 5,6 8ASSM 5,6 8SM 5,6 88 9C 00 5C 00 00 38 88 00 00 00 00 00 88 88 10 10 10 10 10 88 8B OA OA 08 08 08 8B PSW (32-63) 00 00 00 00 00 82 82 46 46 46 46 46 46 46 8A 8A 8A 8A 8A 8A 8A CE CE CE CE CE CE CE 31-Bit Mode Initially Instruction Register 5 8efore 88 88 88 8B 80 00 10 06 8CR 15,6 SAL 5,0(0,6) 8AS 5,0(0,6) 8ALR 5,6 8ASR 5,6 8ASSM 5,6 8SM 5,6 88 80 80 80 80 80 88 88 00 00 00 00 00 88 88 10 10 10 10 10 88 8B OA OA 08 08 08 8B PSW (32-63) 82 82 82 82 82 82 82 46 46 46 46 46 46 46 8A 8A 8A 8A 8A 8A 8A CE CE CE CE CE CE CE Note that a value of zero in the R2 field of any of the RR-format instructions indicates that the branching function is not to be performed; it does not refer to register o. Likewise, a value of zero in the Rl field of the BSM instruction indicates that the old value of psw bit 32 is not to be saved and that register 0 is to be left unchanged. Register 0 can be designated by the R1 field of instructions BAL, BALR, BAS, BASR, and BASSM, however. In the RX -format branch instructions, branching occurs independent of whether there is a value of zero in the B2 field or X2 field of the instruction. However, when the field is zero, instead of using the contents of general register 0, a value of zero is used for that component of address generation. Programming Note: It should be noted that execution of BAL in the 24-bit addressing mode results in bit 0 of register 5 being set to one. This is because the ILC for an Rx-format instruction is 10. This is the only case in which bit zero of the return register does not correctly reflect the addressing mode of the caller. Thus, BSM may be used to return for BALR, BAS, BASR, and BASSM in both the 24-bit and the 31-bit addressing modes, but it A-IO cannot be used to return if the program was called by using BAL in the 24-bit addressing mode. ESA/370 Principles of Operation The BALR or BASR instruction with the R2 field set to zero may be used to load a register for use as a base register. For example, in the assembler language, the two statements: 8ALR USING 15,0 *,15 or 8ASR USING 15,0 *,15 indicate that the address of the next sequential instruction following the BALR or BASR instruction will be placed in register 15, and that the assembler may use register 15 as a base register until otherwise instructed. (The USING statement is an "assembler instruction" and is thus not a part of the object program.) Branch and Stack (BAKR) The semiprivileged BRANCH AND STACK instruction facilitates linkage between subroutines by saving status in a linkage-stack state entry (sometimes called a branch state entry to distinguish it from a program-call state entry). When BRANCH AND STACK has been used, the return from the called program is made by means of the PROGRAM RETURN instruction. PROGRAM RETURN restores access registers 2-14, general registers 2-14, and the psw with values saved in the state entry, except that it leaves the PER mask unchanged and sets the condition code to an unpredictable value. The use of BRANCH AND STACK is discussed in the section "Branching Using the Linkage Stack" in Chapter 5, "Program Execution." BRANCH AND STACK can be used to perform a calling linkage, or it can be used at or near the entry point of the called program, depending on whether the R1 field of the instruction is zero or nonzero, respectively. If the Rl field is zero, bits 32-63 of the psw saved in the state entry indicate the current addressing mode (24-bit or 31-bit) and the address of the next sequential instruction after the BRANCH AND STACK instruction or an EXECUTE instruction. If the Rl field is nonzero, bits 32-63 of the psw saved in the state entry are set. with a value generated from the contents of general register Rl: bit 32 of the psw is set equal to bit 0 of the register, and bits 1-31 of the PSWare set with an address generated from bits 1-31 of the register under the control of bit 0 of the register. Bits 32-63 of the psw saved in the state entry are referred to in the following examples as the return value. The branch address for the instruction is generated from the contents of general register R2 under the control of the current addressing mode. Bit 0 of general register R2 does not affect the operation. If the R2 field of the instruction is zero, the operation is performed without branching. . In addition to saving a complete psw (except with an unpredictable PER mask) in the state entry, BRANCH AND STACK saves the new value of bits 32-63 of the current psw in the state entry. Bits 32-63 are referred to in the following examples as the branch value. The results in the four cases are as follows: Return Value 1. 2. 3. 4. 00 00 80 80 00 00 00 00 Branch Value and PSW (32-63) 10 10 10 10 OA OA OA OA 00 00 82 82 46 46 46 46 8A 8A 8A 8A CE CE CE CE BAKR Example 2 This example shows BAKR used in a called program. BAKR does not perform a branch, and the return is to be as specified in general register R 1. The format of the BAKR instruction is: Machine Format Op Code The following examples contain cases in which bit 32 of the current psw is either zero or one (24-bit or 31-bit addressing) before BRANCH AND STACK is executed and in which bit 0 of the general register designated by a nonzero Rl or R2 field is either zero or one. B240 The format of the BAKR Op Code Op Code o B240 6 Rl,R2 BAKR 5,0 Assume four cases of initial values, as follows: instruction is: Machine Format o Assembler Format BAKR Example 1 This example shows BAKR used in a calling program. BAKR performs a branch, and the return is to be to the next sequential instruction. 5 Register 5 . PSW (32-63) 1. 2. 3. 4. 04 04 84 84 00 00 00 00 10 10 10 10 06 06 06 06 00 82 00 82 46 46 46 46 8A 8A 8A 8A CE CE CE CE The results in the four cases are as follows: Assembler Format Op Code Return Value Rl,R2 BAKR 0,6 Assume four cases of initial values, as follows: 1. 2. 3. 4. 00 00 84 84 00 00 00 00 Branch Value and PSW (32-63) 10 10 10 10 06 06 06 06 00 82 00 82 46 46 46 46 8A 8A 8A 8A 02 02 02 02 PSW (32-63) Register 6 1. 2. 3. 4. 00 00 80 80 00 00 00 00 10 10 10 10 06 06 06 06 02 82 02 82 46 46 46 46 8A 8A 8A 8A CE CE CE CE Appendix A. NU!1lber Representation and Instruction-Use Examples A-tt· BAKR Example 3 This example shows BAKR used in a called program. BAKR perfonns a branch, and the return is to be as specified in general register Rl. Condition Code o 1 2 3 The fonnat of the BAKR instruction is: Op Code 5 Mask Value 8 4 2 1 For example, assume that an ADD (A or AR) operation has been perfonned and that a branch to address 6050 is desired if the sum is zero or less (condition code is 0 or 1). Also assume: Machine Fonnat B240 Instruction (Mask) Bit 8 9 10 11 6 Register 10 contains 00 00 so 00. Register 11 contains 00 00 10 00. Assembler Fonnat The RX fonn of the instruction performs the required test (and branch if necessary) when written as: Op Code Rl,R2 BAKR 5,6 Machine Format Assume eight cases of initial values, as follows: 1. 2. 3. 4. 5. 6. 7. 8. Register 5 Register 6 PSW (32-63) 04 04 04 04 84 84 84 84 06 06 86 86 06 06 86 86 00 82 00 82 00 82 00 82 00 00 00 00 00 00 00 00 10 10 10 10 10 10 10 10 06 06 06 06 06 06 06 06 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 00 00 00 00 00 00 00 00 46 46 46 46 46 46 46 46 8A 8A 8A 8A 8A 8A 8A 8A CE CE CE CE CE CE CE CE The results in the eight cases are as follows: Return Value 1. 2. 3. 4. 5. 6. 7. 8. 00 00 00 00 84 84 84 84 00 00 00 00 00 00 00 00 Branch Value and PSW (32-63) 10 10 10 10 10 10 10 10 06 06 06 06 06· 06 06 06 00 86 00 86 00 86 00 86 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 00 00 00 00 00 00 00 00 Branch on Condition (BC, BCR) The BRANCH ON CONDITION instruction tests the condition code to see whether a branch should or should not occur. The branch occurs only if the current condition code corresponds to a one bit in a mask specified by the instruction. A-12 ESAj370 Principles of Operation Op Code 47 Ml X2 C B B2 02 A 1 050 1 Assembler Format Op Code Ml,02(X2,B2) BC 12,X ' 50 1 (11,10) A mask of 121 e means that there are ones in instruction bits 8 and 9 and zeros in bits 10 and 11, so that branching takes place when the condition code is either 0 or 1. A mask of 15 would indicate a branch on any condition (an unconditional branch). A mask of zero would indicate that no branch is to occur (a nooperation). (See also the section on "Linkage Instructions (BAL, BALR, BAS, BASR, BASSM, BSM)" for an example of the BCR instruction.) Branch on Count (BCT, BCTR) The BRANCH ON COUNT instruction is often used to execute a program loop for a specified number of times. For example, assume that the following represents some lines of coding in an assemblerlanguage program: Machine Format LUPE AR 8,1 Op Code BACK BCT 6,LUPE BCT 46 4 6 Rl X2 B2 6 9 A B2 A 02 Iaeel Assembler Format Op Code R1,R3,02(B2) BXH instruction is: Machine Format Op Code R3 86 where register 6 contains 00 00 00 03 and the address of LUPE is 6826. Assume that, in order to address this location, register lOis used as a base register an4 contains 00 00 68 00. The format of the R1 4,6,O(10) When the instruction is executed, frrst the contents of register 6 are added to register 4, second the sum is compared with the contents of register 7, and third the decision whether to branch is made. After execution: D2 9261 Register 4 contains 00 00 00 8C = 14010. Assembler Format Registers 6 and 7 are unchanged. Op Code R1,02(X2,B2) BCT 6,X ' 26 1 (0,10) The effect of the coding is to execute three times the loop defmed by the instructions labeled LUPE through BACK, while register 6 is decremented from three to zero. Branch on Index High (BXH) BXH Example 1 The BRANCH ON INDEX HIGH instruction is an index-incrementing. and loop-controlling instruction that causes a branch whenever the sum of an index value and an increment value is greater than some compare value. For example, assume that: = Register 4 contains 00 00 00 8A the index. Register 6 contains 00 00 00 02 increment. The format of the BXH instruction is: = = 210 = the Register 7 contains 00 00 00 AA the compare value. Register 10 'contains 00 00 71 30 address. 13811:1 = 17010 Since the new value in register 4 is not yet greater than the value in register 7, the branch to address 7130 is not taken. Repeated use of the instruction will eventually cause the branch to be taken when the value in register 4 reaches 17210. BXH Example 2 When the register used to contain the increment is odd, that register also becomes the compare-value register. The following assembler-language subroutine illustrates how this may be used to search a table. Table 2 Bytes 2 Bytes ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 FUNCT1 FUNCT2 FUNCT3 FUNCT4 FUNCT5 FUNCT6 = = the branch Assume that: Register 8 contains the search argument. Register 9 contains the width of the table in bytes (00 00 00 04). Register 10 contains the length of the table in bytes (00 00 00 18). Register 11 contains the starting address of the table. Appendix A. Number Representation and Instruction-Use Examples A-t3 Register 14 contains the return address to the main program. As the following subroutine is executed, the argument in register 8 is successively compared with the arguments in the table, starting with argument 6 and working backward to argument 1. If an equality is found, the corresponding function replaces the argument in register 8. If an equality is not found, zero replaces the argument in register 8. SEARCH LNR 9,9 NOTEQUAL BXH 10,9,LOOP NOT FOUND SR 8,8 BCR 15,14 CH 8,O(1O,11) LOOP BC 7,NOTEQUAL LH 8,2(10,11) BCR 15,14 The first instruction (LNR) causes the value in register 9 to be made negative. After execution of this instruction, register 9 contains FF FF FF FC = -41 e. Considering the case when no equality is found, the BXH instruction will be executed seven times. Each time BXH is executed, a value of -4 is added to register 10, thus reducing the value in register 10 by 4. The new value in register 10 is compared with the -4 value in register 9. The branch is taken each time until the value in register lOis -4. Then the .branch is not taken, and the SR instruction sets register 8 to zero. Branch on Index low or Equal. (BXlE) The BRANCH ON INDEX LOW OR EQUAL instruction performs the same operation as BRANCH ON INDEX HIGH, except that branching occurs when the sum is lower than or equal to (instead of higher than) the compare value. As the instruction which increments and tests an index value in a program loop, BXLE is useful at the end of the loop and BXH at the beginning. The following assembler-language routines illustrate loops with BXLE. aXLE Example 1 Assume that a group of ten 32-bit signed binary integers are stored at consecutive locations, starting at location GROUP. The integers are to be added together, and the sum is to be stored at location SUM. A·14 ESAj370 Principles of Operation SR LA SR LA LA LOOP A BXLE ST 5,5 6,GROUP 7,7 8,4 9,39 5,O(7,6) 7,8,LOOP 5,SUM Set sum to zero Load first address Set index to zero Load increment 4 Load compare value Add integer to sum Test end of loop Store sum The two-instruction loop contains an ADD (A) instruction which adds each integer to the contents of general register 5. The ADD ,instruction uses the contents of general register 7 as an index value to modify the starting address obtained from register 6. Next, BXLE increments the index value by 4, the increment previously loaded into register 8, and compares it with the compare value in register 9, the odd register of this even-odd pair. The compare value was previously set to 39, which is one less than the number of bytes in the data area; this is also the address, relative to the starting address, of the rightmost byte of the last integer to be added. When the last integer has been added, BXLE increments the index value to the next relative address (40), which is found to be greater than the compare value (39) so that no branching takes place. aXLE Example 2 The technique illustrated in Example 1 is restricted to loops containing instructions in the RX instruction format. That format allows both a base register and an index register to be specifted (double indexing). For instructions in other formats, where an index register cannot be specifted, the previous technique may be modifted by having the address itself serve as the index value in a BXLE instruction and by using as the compare value the address of the last byte rather than its relative address. The base register then provides the address directly at each iteration of the loop, and it is not necessary to specify a second register to hold the index value (single indexing). In the following example, an AND (NI) instruction in the SI. instruction format sets to zero the rightmost bit of each of the same group of integers as in Example 1, thus making all of them even. The 12 field of the NI instruction contains the byte X I FE I , which consists of seven ones and a zero. That byte is ANDed into byte 3, the rightmost byte, of each of the integers in tum. LA LA LA LOOP NI BXLE 6,GROUP 8,4 9,GROUP+39 3(6),X'FE' 6,8,LOOP Load first address Load increment 4 Load compare value AND immediate Test end of loop The technique shown in Example 2 does not work, however, on an ESA/370 system when it is in the 31-bit addressing mode and the data is located at the rightmost end of a 31-bit address space. In this case, the compare value would be set to 231 _1, which is the largest possible 32-bit signed binary value. The reason the technique does not work is that the BXLE and BXH instructions treat their operands as 32-bit signed binary integers. When the address in general register 6 reaches the value 231 _4, BXLE increments it to a value that is interpreted as _2 31 , rather than 231 , and the comparison remains low, which causes looping to continue indefmitely. propagated to the left), and compared with the contents of register 4. Because the two numbers are equal, condition code 0 is set. Compare logical (Cl, ClC, Cll, ClR) The COMPARE LOGICAL instruction differs from the signed-binary comparison instructions (c, CH, CR) in that all quantities are handled as unsigned binary integers or as unstructured data. CLC Example The COMPARE LOGICAL (CLC) instruction can be used to perform the byte-by-byte comparison of storage fields up to 256 bytes in length. For example, assume that the following two fields of data are in storage: Field 1 This situation can be avoided by not allowing data areas to extend to the rightmost location in a 31-bit address space or by using other techniques; these may include double indexing when possible, as in Example 1, or starting at the end and stepping downward through the data area with a negative increment. 1886 1891 Field 2 1900 190B Compare Halfword (CH) The COMPARE HALFWORD instruction compares a 16-bit signed binary integer in storage with the contents of a register. For example, assume that: Register 4 contains FF FF 80 00 = -32,76811:). Register 13 contains 00 01 60 50. Also assume: Register 9 contains 00 00 18 80. Register 7 contains 00 00 19 00. Storage locations 16080-16081 contain 8000 -32,768le. Execution of the instruction: Machine Format When the instruction: Op Code L D5 0B Machine Format Op Code 49 R1 X2 4 B2 D2 9 I aS61 7 I aS01 o Assembler Format Op Code D1(L,Bl),D2(B2) Assembler Format CLC Op Code Rl,02(X2,B2) CH 4,X'30 1 (0,13) is executed, the contents of locations 16080-16081 are fetched, expanded to 32 bits (the sign bit is sets condition code 1, indicating that. the contents of field 1 are lower in value than the contents of field 2. Appendix A. Number Representation and Instruction-Use Examples A-IS Because the collating sequence of the EBCDIC code is determined simply by a logical comparison of the bits in the code, .the CLC instruction can be used to collate EBCDIc-coded. fields. For example, in EBCDIC, the above two' data fields are: Field 1: JOHNSON,A.B. Field 2: JOHNSON,A.C. Cli Example The COMPARE LOGICAL (CLI) instruction compares a byte from the instruction stream with a byte· from storage. For example, assume that: Storage location 1703 contains 7E. Execution of the instruction: 95 AF 01 Assembler Format Op Code 01(Bl),12 CLI 4,7 If, instead, the signed-binary comparison instruction COMPARE (CR) had been executed, the contents of register 4 would have been interpreted as + 1 and the contents of register 7 as -1. Thus, the first operand would have been higher, so that condition code 2 would have been set. The COMPARE LOGICAL CHARACTERS UNDER MASK (CLM) instruction provides a means of comparing bytes selected from a generru register to a contiguous field of bytes in storage. The M3 field of the CLM instruction is a four-bit/ mask that selects zero to four bytes from a general register, each mask bit corresponding, left to right, to a register byte. In the comparison, the register bytes corresponding to ones in the mask are treated as a contiguous field. The operation proceeds left to right. For example, assume that: Machine Format B1 CLR Compare logical Characters under Mask (ClM) Register 10 contains 00 00 17 00. 12 Op Code Rl,R2 sets condition code 1. Condition code 1 indicates that the f11'st operand is lower than the second. Condition code I indicates that JOHNSON,A.B. should precede JOHNSON,A.C. for the fields to be in alphabetic sequence. Op Code Assembler Format Storage locations 10200-10202 contain FO BC 7B. 3(18),X'AF' sets condition code I, indicating that the f11'st operand (the quantity in main st9rage) is lower than the second (immediate) operand. ClR Example Register 12 contains 00 01 00 00. Register 6 contains FO BC SC 7B. Execution of the instruction: Machine Format Assume that: Register 4 contains 00 00 00 0 I = I. Register 7 contains FF FF FF FF = 232 - 1. Op Code Rl M3 SO 6 0 B2 C 02 I 2eal Execution of the instruction: Assembler Format Machine Format Op Code 15 Rl R2 4 7 Op Code Rl,M3,02(B2) CLM 6,B'1181',X'288'(12) causes the following comparison: A-16 ESA/370 Principles of Operation Register 6: Mask M3: F0 1 BC 1 F0 BC 5C 0 Since the CLCL instruction may be interrupted during execution, the interrupting program must preserve the contents of the four registers for use when the instruction is resumed. 7B 1 7B The following instructions set up two register pairs to control a text-string comparison. For example, assume: Storage locations 10200-10202: Operand 1 Address: 2080016 Length: l00 H) Because the selected bytes are equal, condition code ois set. Operand 2 Address: 20A0016 Length: 132 H) Compare Logical Long (CLCL) The COMPARE LOGICAL LONG (CLCL) instruction is used to compare two operands in storage, byte by byte. Each operand can be of any length. Two even-odd pairs of general registers (four registers in all) are used to locate the operands and to control the execution of the CLCL instruction, as illustrated in the following diagram. The first register of each pair must be an even register, and it contains the storage address of an operand. The odd register of each pair contains the length of the operand it covers, and the leftmost byte of the second-operand odd register contains a padding byte which is used to extend the shorter operand, if any, to the same length as the longer operand. The following illustrates the assignment of registers: Rl (even) R2 (even) R2+1 (odd) Register 12 contains 00 0200 00. The setup instructions are: LA 4,X' 800'(12) LA 5,100 LA 8,X'AOO'(12) LA 9,132 ICM 9,B'1000',3(12) Set register 4 to start of frrst operand Set register 5 to length of frrst operand Set register 8 to start of second operand Set register 9 to length of second operand Insert padding byte in leftmost byte position of register 9 o 8 31 Register pair 4,5 defmes the frrst operand. Bits 8-31 of register 4 contain the storage address of the start of an EBCDIC text string, and bits 8-31 of register 5 contain the length of the string, in this case 100 bytes. o 8 31 o 8 31 Register pair 8,9 defmes the second operand, with bits 8-31 of register 8 containing the. starting location of the second operand and bits 8-31 of register 9 containing the length of the second operand, in this case 132 bytes. Bits 0-7 of register 9 contain an EBCDIC blank character (X '40') to pad the shorter operand. In this example, the padding byte is used in the frrst operand, after the 100th byte, to compare with the remaining bytes in the second , operand. o 8 31 Rl+1 (odd) Padding Byte Address: 2000316 Length: 1 Value: 4016 With the register pairs thus set up, the fonnat of the CLCL instruction is: Appendix A. Number Representation and Instruction-Use Examples A-l7 Machine Fonnat Op Code 0F Convert to Binary (CVB) Rl R2 4 8 Assembler Fonnat Op Code Rl,R2 CLCL 4,8 When this instruction is executed, the comparison starts at the left end of each operand and proceeds to the right. The operation ends as soon as an inequality is detected or the end of the longer operand is reached. If this CLCL instruction is interrupted after 60 bytes have compared equal, the operand lengths in registers 5 and 9 will have been decremented to 40 and 72, respectively. The operand addresses in registers 4 and 8 will have been incremented to X 12083C I and XI 20A3C I; the leftmost byte of registers 4 and 8 will have been set to zero. The padding byte X 140 1 remains in register 9. When the CLCL instruction is reexecuted with these register contents, the comparison resumes at the point of interruption. Now, assume that the instruction is interrupted after 110 bytes. That is, the frrst 100 bytes of the second operand have compared equal to the frrst operand, and the next 10 bytes of the second operand have compared equal to the padding byte (blank). The residual operand lengths in registers 5 and 9 are 0 and 22, respectively, and the operand addresses in registers 4 and 8 are X 120864 1 (the value when the frrst operand was exhausted) and XI 20A6E 1 (the current value for the second operand). When the comparison ends, the condition code is set to 0, 1, or 2, depending on whether the first operand is equal to, less than, or greater than the second operand, respectively. When the operands are unequal, the addresses in registers 4 and 8 indicate the bytes that caused the mismatch. The CONVERT TO BINARY instruction converts an eight-byte, packed-decimal number into a signed binary integer and loads the result into a general register. After the conversion operation is completed, the number is in the proper fonn for use as an operand in signed binary. arithmetic. For example, assume: Storage locations 7608-760F contain a decimal number in the packed fonnat: 00 00 00 00 00 25 59 4C ( + 25,594). The contents of register 7 are not significant. Register 13 contains 00 00 76 00. The fonnat of the conversion instruction is: Machine Fonnat Op Code 4F ESA/370 Principles of Operation X2 7 0 o \ e9a\ Assembler Fonnat Op Code Rl,02(X2,B2) CVB 7,8(0,13) After the instruction is executed, register 7 contains 000063 FA. Convert to Decimal (CVD) The CONVERT TO DECIMAL instruction is the opposite of the CONVERT TO BINARY instruction. CVD converts a signed binary integer in a register to packed decimal and stores the eight-byte result. For example, assume: Register 1 contains the signed binary integer: 00 00 OF OF. Register 13 contains 00 00 76 00. The fonnat of the instruction is: Machine Fonnat Op Code 4E A-IS Rl Rl 1 X2 e B2 02 0 e0a\ After the instructions listed above are executed: Assembler Format Op Code R1,02(X2,B2) CVO Register 6 contains 00 00 00 14 = 201 e = the remainder. 1,8(0,13) Mer the instruction is executed, storage locations 7608-760F contain 00 00 00 00 00 03 85 5C (+ 3855). The plus sign generated is the preferred plus sign, 11002. Divide (D, DR) Register 7 contains 00 00 00 2D quotient. = 451 e = the Note that if the dividend had not been frrst placed in register 6 and shifted into register 7, register 6 might not have been filled with the proper dividend-sign bits (zeros in this example), and the DIVIDE instruction might not have given the expected results. Exclusive OR (X, XC, XI, XR) The DIVIDE instruction divides the dividend in an even-odd register pair by the divisor in a register or in storage. Since the instruction assumes the dividend to be 64 bits long, it is important frrst to extend a 32-bit dividend on the left with bits equal to the sign bit. For example, assume that: Storage locations 3550-3553 contain 00 00 08 DE = 227010 (the dividend). When the Boolean operator EXCLUSIVE OR is applied to two bits, the result is one when either, but not both, of the two bits is one; otherwise, the result is zero. When two bytes are EXCLUSIVE oRed, each pair of bits is handled separately; there is no connection from one bit position to another. The following is an example of the EXCLUSIVE OR of two bytes: Storage locations 3554-3557 contain 00 00 00 32 = 50u) (the divisor). First-operand byte: 0011 01012 Second-operand byte: 0101 11002 The initial contents of registers 6 and 7 are not significant. Result byte: Register 8 contains 00 00 35 50. XC Example The EXCLUSIVE OR (XC) instruction can be used to exchange the contents of two areas in storage without the use of an intermediate storage area. For example, assume two three-byte fields in storage: The following assembler-language statements load the registers properly and perform the divide operation: Statement Comments 6,0(0,8) L SROA 6,32(0) 6,4(0,8) 0 50 R1 6 DIVIDE instruc- Fie 1d 1 35B Iee 117 199 360 I 362 1801141011 Field 2 Execution of the instruction (assume that register 7 contains 00 00 03 58): Machine Format Machine Format Op Code 359 Places 00 00 08 DE into register 6. Shifts 00 00 08 DE into register 7. Register 6 is filled with zeros (sign bits). Performs the division. The machine format of the above tion is: 0110 10012 X2 o B2 02 Op Code L 07 02 7 I ee11 7 I 9GSI Appendix A. Nu~ber Representation and Instruction-Use Examples A-19 Assembler Format Op Code 01(L,B1),02(B2) XC 1(3,7),8(7) Field 1 is EXCLUSIVE oRed with field 2 as follows: Field 1: Field 2: eeeeeeee eee1e111 1ee1eeee2 = ee 17 ge16 eeeeeeee eee1e1ee eeeeeee12 = ee 14 e116 Result: eeeeeeee eeeeee11 1ee1eee12 = ee e3 9116 The result replaces the former contents of field 1. Condition code 1 is set to indicate a nonzero result. Now, execution of the instruction: Machine Format Op Code L 07 02 Assembler Format Field 1: Field 2: eeeeeeee eeeeee11 1ee1eee12 = ee e3 9116 eeeeeeee eee1e111 1ee1eeee2 = ee 17 ge16 Result: eeeeeeee eee1e1ee eeeeeee12 = ee 14 e116 The result. of this operation replaces the former contents of field 1. Field 1 now contains the original value of field 2. Condition code 1 is set to indicate a nonzero result. XI Example A frequent use of the EXCLUSIVE OR (XI) instruction is to invert a bit (change a zero bit to a one or a one bit to a zero). For example, assume that storage location 8082 contains 0110 10012. To invert the leftmost and rightmost bits without affecting any of the other bits, the following instruction can be used (assume that register 9 contains 00 00 80 80): Machine Format Op Code 12 97 81 B1 01 Op Code D1(L,B1),02(B2) XC 8(3,7) ,1(7) Assembler Format Op Code 01(B1),12 pro~uces the following result:. Field 1: Field 2: eeeeeeee eeeeee11 1ee1eee12= ee e3 9116 eeeeeeee eee1e1ee eeeeeee12 = ee 14 e116 Result: eeeeeeee eee1e111 1ee1eeee2 = ee 17 ge16 The result of this operation replaces the former contents of field 2. Field 2 now contains the original value of field. 1. Condition code 1 is set to indicate a nonzero result. Lastly, execution of the instruction: XI 2(9),X ' 81 1 When the instruction is executed, the byte in storage is EXCLUSIVE oRed with the immediate byte (the 12 field of the instruction): Location 8082: 0110 10012 Immediate byte: 1000 00012 Result: 1110 10002 The resulting byte is stored back in location 8082. Condition code 1 is set to indicate a nonzero result. Machine Format Op Code L 07 02 Assembler Format Op Code 01(L,Bl),02(B2) XC 1(3,7),8(7) produces the following result: A-20 ESAj370 Principles of Operation Notes: 1. With the XC instruction, fields up to 256 bytes in length can be exchanged. 2. With the XR instruction, the contents of two registers can be exchanged. 3. Because the x instruction operates storage to register only, an exchange cannot be made solely by the use of x. 4. A field EXCLUSIVE oRed with itself is cleared to zeros. 5. For additional examples of the use of EXCLUSIVE OR, see the section "Floating-PointNumber Conversion" later in this appendix. Execute (EX) The EXECUTE instruction causes one target instruction in main storage to be executed out of sequence without actually branching to the target instruction. Unless the R1 field of the EXECUTE instruction is zero, bits 8-15 of the target instruction are 0 Red with bits 24-31 of the R1 register before the target instruction is executed. Thus, EXECUTE may be used to supply the length field for an ss instruction without modifying the ss instruction in storage. For example, assume that a MOVE (MVC) instruction is the target that is located at address 3820, with a format as follows: L 02 00 Instruction byte: Register byte: 0000 00002 = 00 0000 00112 = 03 Result: 0000 00112 = 03 causing the instruction at 3820 to be executed as if it originally were: Machine Format Op Code L 02 03 B1 01 B2 02 Assembler Format Op Code 01(L,Bl),02(B2) Machine Format Op Code When the instruction at 5000 is executed, the rightmost byte of register 1 is oRed with the second byte of the target instruction: B1 01 B2 MVC 02 3(4,12) ,0(13) However, after execution: Register 1 is unchanged. Assembler Format The instruction at 3820 is unchanged. Op Code 01(L,Bl),02(B2) The contents of the four bytes starting at location 90AO have been moved to the four bytes starting at location 8916. MVC 3(1,12),0(13) where register 12 contains 00 00 89 13 and register 13 contains 00 00 90 AO. Further assume that at storage address 5000, the following EXECUTE instruction is located: Machine Format Op Code 44 R1 X2 1 o B2 02 A I eeel Insert Characters under Mask (ICM) The INSERT CHARACTERS UNDER MASK (ICM) instruction may be used to replace all or selected bytes in a general register with bytes from storage and to set the condition code to indicate the value of the inserted field. For example, if it is desired to insert a three-byte address from FIELDA into register 5 and leave the leftmost byte of the register unchanged, assume: Assembler Format Op Code R1,02(X2,B2) EX The CPU next executes the instruction at address 5004 (psw bits 40-63 contain 00 50 04). Machine Format 1,0(0,10) where register 10 contains 00 00 38 20 and register 1 contains 00 OF FO 03. Op Code Rl M3 BF 5 7 * * * * Appendix A. Number Representation and Instruction-Use Examples A-21 Assembler Format The contents of register 10 are not significant. Op Code R1,M3,S2 Storage locations 21003-21006 contain 00 00 ABCD. ICM 5,B I 0111 1 , FJElDA FIElDA: Register 5 (before): Register 5 (after): Condition code (after): To load register 10, the can be used: FE DC BA 12 34 56 78 12 FE DC BA 1 (leftmost bit of inserted fi e1d is one) Op Code 58 R1 A X2 5 Assembler Format Machine Format Op Code R1,D2(X2,B2) R1 M3 BF 6 9 Load Address (LA) Op Code R1,M3,S2 6,B I 1001 1 ,FIElDB FIElDB: Register 6 (before): Register 6 (after): Condition code (after): 12 00 12 2 34 00 OO 00 00 00 34 (inserted field is nonzero with leftmost zero bit) When the mask field contains 1111, the ICM instruction produces the same result as LOAD (L) (provided that the indexing capability of the RX format is not needed), except that ICM also sets the condition code. The condition-code setting is useful when an all-zero field (condition code 0) or a leftmost one bit (condition code 1) is used as a flag. Load (L, LR) The LOAD instruction takes four bytes from storage or from a general register and place them unchanged into a general register. For example, assume that the four bytes starting with location 21003 are to be loaded into register 10. Initially: Register 5 contains 00 02 00 00. Register 6 contains 00 00 10 03. A - 22 eeel After the instruction is executed, register 10 contains 00 00 AB CD. Assembler Format ICM 6 10,O(5,6) l * * * * form .of the instruction Machine Format As another example: Op Code RX ESA/370 Principles of Operation The LOAD ADDRESS instruction provides a convenient way to place a nonnegative binary integer up to 409510 in a register without frrst defming a constant and then using it as an operand. For example, the following instruction places the number 20481 e in register 1: Machine Format Op Code 41 R1 1 X2 ° B2 02 o I aeel Assembler Format Op Code R1,D2(X2,B2) lA 1,2048(0,0) The LOAD ADDRESS instruction can also be used to increment a register by an amount up to 409510 specified in the D 2 field. Depending on the addressing mode, only the rightmost 24 or 31 bits of the sum are retained, however. The leftmost bits of the 32-bit result are set to zeros. For example, assume that register 5 contains 00 12 34 56. The instruction: Assembler Fonnat Machine Fonnat Op Code Rl X2 B2 02 41 5 0 5 I eeAI Op Code Rl,02(X2,B2) LH Assembler Fonnat After the instruction is executed, register 6 contains 00 00 00 20. If locations 1803-1804 had contained a negative number, for example, A7 B6, a minus sign would have been propagated to the left, giving FF FF A 7 B6 as the fmal result in register 6. Op Code Rl,02(X2,B2) LA 6, 0 (0, 14) 5,10(0,5) adds 10 (decimal) to the contents of register 5 as follows: Register 5 (old): 00 12 34 56 00 00 00 0A 02 field: Register 5 (new): 00 12 34 60 The register may be specified as either B 2 or X 2. Thus, the instruction LA 5,1 O( 5,0) produces the same result. Move (MVC, MVI) MVC Example The MOVE (MVC) instruction can be used to move data from one storage location to another. For example, assume that the following two fields are in storage: 2052 2048 As the most general example, the instruction LA 6,10(5,4) fonns the sum of three values: the contents of register 4, the contents of register 5, and a displacement of 10 and places the 24-bit or 31-bit sum with zeros appended on the left in register 6. Fi~ld Load Halfword (LH) Also assume: The LOAD HALFWORD instruction places unchanged a halfword from storage into the right half of a register. The left half of the register is loaded with zeros or ones according to the sign (leftmost bit) of the halfword. For example, assume that the two bytes in storage locations 1803-1804 are to be loaded into register 6. Also assume: The contents of register 6 are not significant. 3840 3848 IF1 IF21F31F41 FS IF61F71F81F91 Register I contains 00 00 20 48. Register 2 contains 00 00 38 40. With the following instruction, the frrst eight bytes of field 2 replace the frrst eight bytes of field 1: Machine Fonnat Op Code L B1 02 97 1 01 eeel B2 2 D2 eeal Register 14 contains 00 00 18 03. Locations 1803-1804 contain 00 20. The instruction required to load the register is: Code 48 Op Code 01(L,Bl),02(B2) MVC Machine Fonnat O~ Assembler Fonnat Rl X2 B2 6 a E 02 0(8,1) ,0(2) After the instruction is executed, field 1 becomes: eael 2048 Fi~ld 2052 IF1 IF21F31F41FSIF61F71F81C91CAICBI Field 2 is unchanged. Appendix A. Number Representation and Instruction-Use Examples A-23 MVC can also be used to propagate a byte through a field by starting the fIrst-operand field one byte location to the right of the second-operand field. For example, suppose that an area in storage starting with address 358 contains the following data: 358 360 Machine Format Op Code 12 81 92 S8 1 01 I 6e61 Assembler Format Op Code 01(81),12 With the following MVC instruction, the zeros in location 358 can be propagated throughout the entire field (assume that register 11 contains 00 00 03 58): Machine Format Op Code L 02 07 Assembler Format Op Code 01(L,81),D2(82) MVC 1(8,11),0(11) Because MVC is executed as if one byte were processed at a time, the above instruction, in effect, takes the byte at address 358 and stores it at 359 (359 now contains 00), takes the byte at 359 and stores it at 35A, and so on, until the entire field is filled with zeros. Note that an MV I instruction could have been used originally to place the byte of zeros in location 358. MVI 0(1),C'$' may be used, in conjunction. with the instruction EDIT AND MARK, to insert the EBCDIC code for a dollar symbol at the storage address contained in general register 1 (see also the example for EDIT AND MARK). Move Inverse (MVCIN) The MOVE INVERSE (MVCIN) instruction can be used to move data from one storage location to another while reversing the order of the bytes within the field. For example, assume that the following two fields are in storage: 2048 Fi~ld 2052 ICIIC21C31C41csIC61c71calc91cAIcai 3840 Fi~ld 3848 IF1 IF21F31F41FSIF61F71 FS IF91 Also assume: Register 1 contains 00 00 20 48. Notes: 1. Although the field occupying locations 358-360 contains nine bytes, the length coded in the assembler format is equal to the number of moves (one less than the field length). 2. The order of operands is important even though only one field is involved. MVI Example The MOVE (MVI) instruction places one byte of information from the instruction stream into storage. For example, the instruction: Register 2 contains 00 00 3840. With the following instruction, the fIrst eight bytes of field 2 replace the fIrst eight bytes of field I: Machine Format Op Code L E8 07 Assembler Format Op Code D1(L,81),02(82) MVCIN 0(8,1),7(2) A-24 ESA/370 Principles of Operation After the instruction is executed, field I becomes: 2048 Fi~ld 2052 IFSIF71F61FSIF41F31F21F1IC91CAICBI Field 2 is unchanged. Note: This example uses the same general registers, storage locations, and original values as the fust example for MVC. For MVCIN, the secondoperand address must designate the rightmost byte of the field to be moved, in this case location 3847. This is accomplished by means of the 7 in the 02 field of the instruction. Move long (MVel) The MOVE LONG (MVCL) instruction can be used for moving data in storage as in the fust example of the MVC instruction, provided that the two operands do not overlap. MVCL differs from MVC in that the address and length of each operand are specified in an even-odd pair of general registers. Consequently, MVCL can be used to move more than 256 bytes of data with one instruction. As an example, assume: Register 2 contains 00 OA 00 00. Register 3 contains 00 00 08 00. Register 8 contains 00 06 00 00. Register 9 contains 00 00 08 00. Execution of the instruction: If register 3 had contained FO 00 04 00, only the 1,02411:) bytes from locations AOOOO-A03FF would have been moved to locations 60000-603FF. The remaining locations 60400-607FF of the fust operand would have been filled with 1,024 copies of the padding byte X I FO I, as specified by the leftmost byte of register 3. Bits 8-31 of register 2 would have been incremented by 4001 6, bits 8-31 of register 8 would have been incremented by 8001 6, and bits 0-7 of registers 2 and 8 would have been set to zeros. Bits 8-31 of registers 3 and 9 would still have been decremented to zero. Condition code 2 would have been set to indicate that the fust operand was longer than the second. The technique for setting a field to zeros that is illustrated in the second example of MVC cannot be used with MVCL. If the registers were set up to attempt such an operation with MVCL, no data movement would take place and condition code 3 would indicate destructive overlap. Instead, MVCL may be used to clear a storage area to zeros as follows. Assume register 8 and 9 are set up as before. Register 3 contains only zeros, specifying zero length for the second operand and a zero padding byte. Register 2 is not used to access storage, and its contents are not significant. Executing the instruction MVCL 8,2 causes locations 60000-607FF to be filled with zeros. Bits 8-31 of register 8 are incremented by 80016, and bits 0-7 of registers 2 and 8 are set to zeros. Bits 8-31 of register 9 are decremented to zero, and condition code 2 is set to indicate that the fust operand is longer than the second. Machine Format Op Code Rl R2 8 2 0E Move Numerics (MVN) Two related instructions, MOVE NUMERICS and MOVE ZONES, may be used with decimal data in the zoned format to operate separately on the rightmost four bits (the numeric bits) and the leftmost four bits (the zone bits) of each byte. Both are similar to MOVE (MVC), except that MOVE NUMERICS moves only the numeric bits and MOVE ZONES moves only the zone bits. Assembler Format Op Code Rl,R2 MVCL 8,2 moves 2,04810 bytes from locations AOOOO-A07FF to locations 60000-607FF. Bits 8-31 of registers 2 and 8 are incremented by 80016, and bits 0-7 of registers 2 and 8 are set to zeros. Bits 8-31 of registers 3 and 9 are decremented to zero. Condition code 0 is set to indicate that the operand lengths are equal. To illustrate the operation of the MOVE NUMERICS instruction, assume that the following two fields are in storage: 7090 7093 Field A IC61C71csIC91 Appendix A. Number Representation and Instruction-Use Examples A-25 7041 7046 After the instruction: Machine Format Op Code L1 L2 3 2 B1 Also assume: F1 Register 14 contains 00 007090. C 01 B2 02 I geel Ige91 F Register 15 contains 00 00 70 40. After the instruction: Op Code 01(L1,B1),02(L2,B2) Machine Format Op Code L 01 03 MVO Op Code 01(L,B1),02(B2) Move Zones (MVZ) 1(4,15),0(14) is executed, field 7041 0(4,12),0(3,15) is executed, the storage locations 5600-5603 contain 01 23 45 6C. Note that the second operand is extended on the left with one zero to fill out the frrst-operand field. Assembler Format MVN Assembler Format B becomes: 7046 The numeric bits of the bytes at locations 7090-7093 have been stored in the numeric bits of the bytes at locations 7041-7044. The contents of locations 7090-7093 and 7045-7046 are unchanged. The MOVE ZONES instruction can operate on overlapping or nonoverlapping fields, as can the instructions MOVE (MVC) and MOVE NUMERICS. When operating on nonoverlapping fields, MOVE ZONES works like the MOVE NUMERICS instruction (see its example), except that MOVE ZONES moves only the zone bits of each byte. To illustrate the use of MOVE ZONES with overlapping fields, assume that the following data field is in storage: 800 805 Move with Offset (MVO) may be used to shift a packeddecimal number an odd number of digit positions or to concatenate a sign to an unsigned packeddecimal number. MOVE WITH OFFSET Assume that the three-byte unsigned packeddecimal number in storage locations 4500-4502 is to be moved to locations 5600-5603 and given the sign of the packed-decimal number ending at location 5603. Also assume: Register 12 contains 00 00 56 00. Register 15 contains 00 00 45 00. Also aSSUlne that register 15 contains 00 00 08 00. The instruction: Machine Format Op Code L 03 04 F I e911 F I eeel Assembler Format Op Code 01(L,B1),02(B2) MVZ 1 (5, 15) , 0 ( 15) Storage locations 5600-5603 contain 77 88 99 OC. Storage locations 4500-4502 contain 12 34 56. A-26 ESAj370 Principles of Operation propagates the zone bits from the byte at address 800 through the entire field, so that the field becomes: Assembler Format 805 800 Op Code Rl,R2 MR Multiply (M, MR) Assume that a number in register 5 is to be multiplied by the contents of a four-byte field at address 3750. Initially: 6,7 multiplies the number in register 7 by itself and places. the result in the pair of registers 6 and 7: Register 6 contains 00 00 00 01. Register 7 contains 00 OA 00 19. The contents of register 4 are not significant. Register 5 contains 00 00 00 9A the multiplicand. = 15410 = Multiply Halfword (MH) The MULTIPLY HALFWORD instruction is used to multiply the contents of a register by a two-byte field in storage. For example, assume that: Register 11 contains 00 00 06 00. Register 12 contains 00 00 30 00. = 2110 = Storage locations 3750-3753 contain 00 00 00 83 = 13110 = the multiplier. Register 11 contains 00 00 00 15 multiplicand. The instruction required for performing the multiplication is: Register 14 contains 00 00 01 00. Machine Format Storage locations 2102-2103 contain FF D9 = -3910 = the multiplier. Op Code 5C Rl X2 4 B B2 02 the Register 15 contains 00 00 20 00. The instruction: Machine Format Op Code Assembler Format 4C Op Code Rl,02(X2,B2) M Rl X2 B2 B E F 02 8021 4,X'150'(11,12) Assembler Format After the instruction is executed, the product is in the register pair 4 and 5: MH Register 4 contains 00 00 00 00. Register 5 contains 00 00 4E CE Op Code Rl,02(X2,B2) = 20,17410. Storage locations 3750-3753 are unchanged. The RR format of the instruction can be used to square the number in a register. Assume that register 7 contains 00 01 00 05. The contents of register 6 are not significant. The instruction: 11,2 (14,15) multiplies the two numbers. The product, FF FF FC CD = -81910, replaces the original contents of register 11. Only the rightmost 32 bits of a product are stored in a register; any significant bits on the left are lost. No program interruption occurs on overflow. Machine Format Op Code lC Rl R2 6 7 Appendix A. Number Representation and Instruction-Use Examples A-27 1000 OR (0, OC, 01, OR) When the Boolean operator OR is applied to two bits, the result is one when either bit is one; otherwise, the result is zero. When two bytes are oRed, each pair of bits is handled separately; there is no connection from one bit position to another. The following is an example of oRing two bytes: First-operand byte: Second-operand byte: 0011 ~1012 0101 11002 Result byte: 0111 11012 01 Example A frequent use of the 0 R instruction is to set a particular bit to one. For example, assume that storage location 4891 contains 0100 00102. To set the rightmost bit of this byte to one without affecting the other bits, the following instruction can be used (assume that register 8 contains 00 00 4890): 1003 Also assume that register 12 contains 00 00 10 00. After the instruction: Machine Format Op Code F2 L1 L2 3 3 B1 01 96 e1 8 1 ee11 B2 02 I c I Beel c Iesel Op Code 01(L1,B1),02(L2,B2) PACK 0(4,12),0(4,12) is executed, the result in locations 1000-1003 is in the packed-decimal format: 1000 12 01 Assembler Format Machine Format Op Code B1 Packed number 1003 le91el12314C1 Notes: 1. This example illustrates the operation of PACK when the fust- and second-operand fields overlap completely. Assembler Format Op Code 01(B1),12 01 1(8),X ' 011 When this instruction is executed, the byte in storage is 0 Red with the immediate byte (the 12 field of the instruction): Location 4891: Immediate byte: 0100 00102 0000 00012 Result: 0100 00112 The resulting byte with bit 7 set to one is stored back in location 4891. Condition code 1 is set. Pack (PACK) Assume that storage locations 1000-1003 contain the following zoned-decimal number that is to be converted to a packed-decimal number and left in the same location: A-28 ESA/370 Principles of Operation 2. During the operation, the second operand was extended on. the left with zeros. Shift Left Double (SLDA) The SHIFf LEFf DOUBLE instruction shifts the 63 numeric bits of an even-odd register pair to the left, leaving the sign bit unchanged. Thus, the instruction performs an algebraic left shift of a 64-bit signed binary integer. For example, if the contents of registers 2 and 3 are: 00 7F 0A 72 FE DC BA 98 = 00000000 01111111 00001010 01110010 11111110 11011100 10111010 100110002 The instruction: 7F 9A 72 a9 Machine Format Op Code Rl SF 2 9age1e1e 91119919 9a9999992 Condition code 2 is set to indicate that the result is greater than zero. I1111I e I elFI If a left shift of nine places had been specified, a significant bit would have been shifted out of bit position 1. Condition code 3 would have been set to indicate this overflow and, if the fixed-pointoverflow mask bit in the psw were one, a fixedpoint overflow interruption would have occurred. Assembler Format Op Code Rl,D2(B2) SLDA = a1111111 2,31(e) results in registers 2 and 3 both being left-shifted 31 bit positions, so that their new contents are: 7F 6E 50 4C ee ee ee ee = e1111111 e11el11e e1el11e1 e1ee11ee eeeeeeee eeeeeeee eeeeeeee eeeeeeee2 Because significant bits are shifted out of bit position 1 of register 2, overflow is indicated by setting condition code 3, and, if the fixed-point-overflow mask bit in the psw is one, a fixed-point-overflow program interruption occurs. Store Characters under Mask (STCM) may be used to place selected bytes from a register into storage. For example, if it is desired to store a three-byte address from general register 8 into location FIELD3, assume: STORE CHARACTERS UNDER MASK (STCM) Machine Format Op Code Rl M3 S2 BE 8 7* * ** Shift Left Single (SLA) The SHIFf LEFf· SINGLE instruction is similar to SHIFf LEFf DOUBLE, except that it shifts only the 31 numeric bits of a single register~ Therefore, this instruction performs an algebraic left shift of a 32-bit signed binary integer. For example, if the contents of register 2 are: ee 7F eA 72 = eegeeeee 91111111 ee991919 9111ge192 Register Format Op Code Rl,M3,S2 STeM 8,B ' e1111,FIELD3 Register 8: FIELD3 (before): FIELD3 (after): 12 34 56 78 not significant 34 56 78 The instruction: As ,another example: Machine Format Machine Format Op Code 8B Rl 2 1////1 I a aesl Op Code Rl M3 BE 9 5 Assembler Format Register Format Op Code Rl,D2(B2) Op Code SLA STCM 2,8(e) results in register 2 being shifted left eight bit positions so that its new contents are: '* '* '* * R~,M3,S2 9,B ' e1e1 1,FIELD2 Register 9: e1 23 45 67 FIELD2 (before): not significant FIELD2 (after): 23 67 Appendix A. Number Representation and Instruction-Use Examples A-29 Machine Format Store Multiple (STM) Assume that the contents of general registers 14, 15, 0, and 1 are to be stored in consecutive four-byte fields starting with location 4050 and that: Op Code 12 B1 91 C3 7 01 GG91 Register 14 contains 00 0025 63. Register 15 contains 00 01 27 36. Register 0 contains 12 43 00 62. Register 1 contains 73 26 12 57. Register 6 contains 00 0040 00. The initial contents of locations 4050-405F are not significant. The STORE MULTIPLE instruction allows the use of just one instruction to store the contents of the four registers: 90 R1 Op Code 01(B1),12 9(7),B I 11000011 1 TM The instruction tests only those bits of the byte in storage for which the mask bits are ones: FB = 1111 10112 Mask = 1100 00112 Test = 11xx xxl12 Condition code 3 is set: all selected bits in the test result are ones. (The bits marked "x" are ignored.) Machine Format Op Code Assembler Format R3 E B2 02 1 If location 9999 had contained B9, the test would have been: B9 Mask = 1011 10012 1100 00112 Assembler Format Op Code R1,R3,02(B2) Test = 10xx xx012 14,1,X'50' (6) Condition code 1 is set: the selected bits are both zeros and ones. After the instruction is executed: If location 9999 had contained 3C, the test would have been: STM Locations 4050-4053 contain 00 00 25 63. Locations 4054·4057 contain 00 01 27 36. 3C = 0011 11002 Mask = 1100 00112 Locations 4058-405B contain 1243 00 62. Test = 00xx xx002 Locations 405C-405F contain 73 26 12 57. Condition code 0 is set: all selected bits are zeros. Test under Mask (TM) The TEST UNDER MASK instruction examines selected bits of a byte and sets the condition code accordingly. For example, assume that: Storage location 9999 contains FB. Register 7 contains 00 00 99 90. Assume the instruction to be: Note: Storage location 9999 remains unchanged. Translate (TR) The TRANSLATE instruction can be used to translate data from any character code to any other desired code, provided that each character code consists of eight bits or fewer. An appropriate translation table is required in storage. In the following example, EBCDIC code is translated to ASCII code. The fust step is to create a 256-byte table in storage locations 1000-1 OFF. This table contains the characters of the ASCII code in the sequence of the binary representation of the A-30 ESAj370 Principles of Operation EBCDIC code; that is, the ASCII representation of a character is placed in storage at the starting address of the table plus the binary value of the EBCDIC representation of the same character. For simplicity, the example shows only the part of the table containing the decimal digits: 10F0 leF9 1381311321331341351361371381391 Assume that the four-byte field at storage location 2100 contains the EBCDIC code for the digits 1984: Locations 2100-2103 contain F 1 F9 F8 F4. Register 12 contains 00 00 21 00. Translate and Test (TRT) The TRANSLATE AND TEST instruction can be used to scan a data field for characters with a special meaning. To indicate which characters have a special meaning, a table similar to the one used for the TRANSLATE instruction is set up, except that zeros in the table indicate characters without any special meaning and nonzero values indicate characters with a special meaning. Figure A-4 that follows has been set up to distinguish alphameric characters (A to Z and 0 to 9) from blanks, certain special symbols, and all other characters which are considered invalid. EBCDIC coding is assumed. The 256-byte table is assumed stored at locations 2000-20FF. Register 15 contains 00 00 10 00. 912 3 4 5 6 7 8 9 ABe 0 E F As the instruction: 200_ 49 49 40 40 49 40 49 40 49 40 40 40 49 40 40 49 Machine Format Op Code L DC 63 BIOI B2 201_ 49 40 49 49 49 49 49 40 49 40 49 49 49 49 40 40 02 202_ 40 40 49 40 40 40 40 49 40 40 41:) 40 49 40 41:) 40 C 0001 F 6001 203_ 40 40 40 40 40 40 49 40 40 40 49 40 40 40 41:) 40 204_ 04 49 40 49 40 40 40 49 40 4e 40 08 40 oe 1G 40 Assembler Format 205 14 40 40 40 40 49 49 40 40 40 40 18 lC 20 40 49 Op Code Dl(L,Bl),D2(B2) 206_ 24 28 40 40 40 40 40 40 40 40 40 2C 40 49 40 40 f-- f--- TR -- 207_ 40 40 40 40 49 40 40 49 40 40 40 30 34 38 3C 40 0(4,12),0(15) 208_ 40 49 40 49 49 40 49 49 49 40 40 40 41:) 49 41:) 49 is executed, the binary value of each EBCDIC byte is added to the starting address of the table, and the resulting address is used to fetch an ASCII byte: 209_ 41:) 40 40 40 40 40 49 40 40 40 40 4a 41:) 40 40 49 20A_ 49 40 40 40 4e 40 49 49 49 49 40 40 40 4e 41:) 49 Table starting address: First EBCDIC byte: le00 F1 29B 40 40 40 4e 49 40 40 40 49 40 41:) 40 4a 49 41:) 49 Address of ASCII byte: 10Fl 40 00 el:) oe 09 00 00 00 09 00 40 41:) 41:) 4e 40 40 Mter execution of the instruction: 20E_ 40 40 eo 00 oe 00 00 00 00 00 40 40 40 40 40 40 -- 40 00 el:) 09 00 ao 00 a0 09 00 41:) 40 41:) 49 40 40 Locations 2100-2103 contain 31 39 38 34. Thus, the ASCII code for the digits 1984 has replaced the EBCDIC code in the four-byte field at storage location 2100. 20F_ 00 00 e0 00 00 00 00 00 00 00 40 40 41:) 40 40 40 Note: If the character codes in the statement being translated occupy a range smaller than 00 through FF 15, a table of fewer than 256 bytes can be used. Figure A-4. Translate and Test Table The _table entries for the alphameric characters in EBCDIC are 00; thus, the letter A (code C1) corresponds to byte location 20C 1, which contains 00. The 15 special symbols have nonzero entries from 0416 to 3C16 in increments of 4. Thus, the blank Appendix A. Number Representation and Instruction-Use Examples A-31 (code 40) has the entry 041 IS, the period (code 4B) has the entry 081 &, and so on. All other table positions have the entry 401 & to indicate an invalid character. The table entries are chosen so that they may be used to select one of a list of 16 words containing addresses of different routines to be entered for each special symbol or invalid character encountered during the scan. Assume that this list of 16 branch addresses is stored at locations 3004-3043. Starting at storage location CA80, there is the following sequence of 2110 EBCDIC characters, where "b" stands for a blank. Locations CA80·CA94: UNPKbPRO UT(9) ,WORD(5) Also assume: Register 1 contains 00 00 CA 7F. Register 2 contains 00 00 30 00. Register 15 contains 00 00 20 00. As the instruction: Machine Fonnat Op Code DO L . B1 14 01 I B2 02 I 1 ee11 F eeel Assembler Fonnat Op Code 01(L,Bl),02(B2) TRT 1(21,1),0(15) is executed, the value of the first source byte, the EBCDIC code for the letter U, is added to the starting address of the table to produce the address of the table entry to be examined: . Table starting address First source byte (U) 2000 E4 Address of table entry 20E4 A-32 ESAj370 Principles of Operation Because zeros were placed in storage location 20E4, no special action occurs. The operation continues with the second and subsequent source bytes until it reaches the blank in location CA84. When this symbol is reached, its value is added to the starting address of the table, as usual: Table starting address Source byte (blank) 2000 Address of table entry 2040 40 Because location 2040 contains a nonzero value, the following actions occur: The address of the source byte, 00CA84, is placed in the rightmost 24 bits of register 1. The table entry, 04, is placed in the rightmost eight bits of register 2, which now contains 00 003004. Condition code 1 is set (scan not completed). The TRANSLATE AND TEST instruction may be followed by instructions to branch to the routine at the address found at location 3004, which corresponds to the blank character encountered in the scan. When this routine is completed, program control may return to the TRANSLATE AND TEST instruction to continue the scan, except that the length must fust be adjusted for the characters already scanned. For this purpose, the TRANSLATE AND TEST may be executed by the use of an EXECUTE instruction, which supplies the length specification from a general register. In this way, a complete -statement scan can be perfonned with a single TRANSLATE AND TEST instruction used repeatedly by means of EXECUTE, and without modifying any instructions in storage. In the example, after the ftfst execution of TRANSLATE AND TEST, register 1 contains the address of the last source byte translated. It is then a simple matter to subtract this address from the address of the last source byte (CA94) to produce a length specification. This length minus one is placed in the register that is referenced as the R1 field of the EXECUTE instruction. (Note that the length code in the machine format is one less than the total number of bytes in the field.) The second-operand address of the EXECUTE instruction points to the TRANSLATE AND TEST instruction, which is the same as illustrated above, except for the length (L) which is set to zero. Machine Format Unpack (UNPK) Assume that storage locations 2501-2502 contain a signed, packed-decimal number that is to be unpacked and placed in storage locations 1000-1004. Also assume: Op Code FA L1 L2 2 3 B1 C 01 0gel Register 12 contains 00 00 10 00. Assembler Format Register 13 contains 00 00 25 00. Op Code 01(L1,B1),02(L2,B2) Storage locations 2501-2502 contain 12 3D. The initial contents of storage locations 1000-1004 are not significant. AP B2 0 02 I 0e01 0(3 t 12)t0(4,13) After the instruction: is executed, the storage locations 2000-2002 contain 73 88 5C; condition code 2 is set to indicate that the result is greater than zero. Note that: Machine Format Op Code L1 L2 1. Because the two numbers had different signs, they were in effect subtracted. F3 4 B1 01 B2 02 2. Although the second operand is longer than the ftrst operand, no overflow interruption occurs because the result can be entirely contained within the frrst operand. 1 Assembler Format Op Code 01(L1tB1)t02(L2,B2) UNPK Compare Decimal (CP) 0(5,12),1(2,13) is executed, the storage locations 1000-1004 contain FO FO F1 F2 D3. Assume that the signed, packed-decimal contents of storage locations 700-703 are to be) algebraically compared with the signed, packed-decimal contents of locations 500-502. Also assume: Register 12 contains 00 00 06 00. Decimal Instructions Register 13 contains 00 00 03 00. (See Chapter 8 for a complete description of the decimal instructions.) Storage locations 700-703 contain 17 25 35 6D. Storage locations 500-502 contain 72 14 2D. After the instruction: Add Decimal (AP) Machine Format Assume that the signed, packed-decimal number at storage locations 500-503 is to be added to the signed, packed-decimal number· at locations 2000-2002. Also assume: Op Code F9 Ll L2 3 2 B1 C 01 B2 10al 0 02 20el Register 12 contains 00 00 20 00. Register 13 contains 00 00 05 00. Assembler Format Storage locations 2000-2002 contain 38 46 OD (a negative number). Op Code 01(L1tB1)t02(L2tB2) Storage locations 500-503 contain 01 12 34 5C (a positive number). After the instruction: CP X'100 1 (4,12),X'200 1 (3,13) is executed, condition code I is set, indicating that the frrst operand (the contents of locations 700-703) is less than the second. Appendix A. Number Representation and Instruction-Use Examples A-33 Divide Decimal (DP) Edit (ED) Assume that the signed, packed-decimal number at storage locations 2000-2004 (the dividend) is to be divided by the signed, packed-decimal number at locations 3000-3001 (the divisor). Also assume: Before decimal data in the packed format can be used in a printed report, digits and signs must be converted to printable characters. Moreover, punctuation marks, such as commas and dechnal points, may have to be inserted in appropriate places. The highly flexible EDIT instruction performs these functions in a single instruction execution. Register 12 contains 00 0020 00. Register 13 contains 00 00 30 00. Storage locations 2000-2004 contain 0 I 23 45 678C. Storage locations 3000-3001 contain 32 ID. After the instruction: This example shows step-by-step one way that the ED IT instruction can be used. The field to be edited (the source) is four bytes long; it is edited against a pattern 13 bytes long. The following symbols are used: Machine Format Op Code Ll L2 FO 4 1 B1 01 B2 Symbol Meaning b (Hexadecimal 40) ( (Hexadecimal 21) d (Hexadecimal 20) Blank character Significance starter Digit selector 02 C a9al 0 ee91 Assembler Format Assume that register 12 contains: Op Code 01(Ll,Bl),02(L2,B2) 00 00 10 00 and that the source and pattern fields are: OP is executed, the dividend is entirely replaced by the signed quotient and remainder, as follows: 2eee Locations 2004 1200 la2 1203 1s7 H6CI 2a00-2e94 13s146100101lsci quotient I L+ remainder Pattern Notes: 1. Because the dividend and divisor have different signs, the quotient receives a negative sign. 2. The remainder receives the sign of the dividend and the length of the divisor. 3. If an attempt were made to divide the dividend by the one-byte field at location 3001, the quotient would be too long to fit within the four bytes allotted to it. A decimal-divide exception would exist, causing a program. interruption. A-34 Source ESA/370 Principles of Operation 1000 100C 14912912el6BI2al2112014BI2al291491C31091 b d d , d ( d • d d b C R Execution of the instruction: Machine Format Op Code L DE 0C B1 C 01 a0el B2 C 02 29al If the number in the source field is changed to the negative number 00 00 02 6D and the original pattern is used, the edited result this time is: Assembler Format Op Code Dl(L,Bl),D2(B2) ED e(13,12),X'2ee ' (12) Pattern leec alters the pattern field as follows: 14el4el4el4s14el4elFel4BIF21F614elc31091 - Significance Indicator (Before/ Pattern Digit After) b d d e 2 , d 5 7 4 ( d d d b C R 2 6+ off/off off/off off/on (2) on/on on/on on/on on/on on/on on/on on/off(3) off/off off/off off/off b b b b b be. Rule Location leee-leeC leave(l) fi 11 digit leave digit digit digit leave digit digit fill fi 11 fi 11 bdd,d(d.ddbCR bbd,d(d.ddbCR bb2,d(d.ddbCR same bb2,5(d.ddbCR bb2,57d.ddbCR bb2,574.ddbCR same bb2,574.2dbCR bb2,574.26bCR same bb2,574.26bbR bb2,574.26bbb Notes: 2 6 b C R This pattern field prints as: e.26 CR The significance starter forces the significance indicator to the on state and hence causes a leading zero and the decimal point to be preserved. Because the minus-sign code has no effect on the significance indicator, the characters CR are printed to show a negative (credit) amount. Condition code 1 is set (number less than zero). Edit and Mark (EDMK) Thus, after the instruction is executed, the pattern field contains the result as follows: The EDIT AND MARK instruction may be used, in addition to the functions of EDIT, to insert a currency symbol, such as a dollar sign, at the appropriate position in the edited result. Assume the same source in storage locations 1200-1203, the same pattern in locations 1000-1 OOC, and the same contents of general register 12 as for the EDIT instruction above. The previous contents of general register 1 (GRl) are not significant; a LOAD AD 0 RESS instruction is used to set up the first digit position that is forced to print if no significant digits occur to the left. Pattern The instructions: 1. This character is the fill byte. 2. First nonzero decimal source digit turns on significance indicator. 3. Plus sign in the four rightmost bits of the byte turns off significance indicator. leec leee 1~1~1~lool~I~I~I~I~lrnl~I~I~1 b b 2 ,57 4 • 2 6 b b b This pattern field prints as: LA EDMK BCTR 2,574.26 The source field remains unchanged. Condition code 2 is set because the number was greater than zero. MVI Load address of forced significant digit into GRI 0(13, 12),X 1200 1(12) Leave address of fITst significant digit in GRI Subtract 1 from 1,0 address in G Rl Store dollar sign at O(I),C'$' address in G Rl 1,6(0,12) produce the following results for the two examples under EDIT: Appendix A. Number Representation and Instruction-Use Examples A-35 sets up a new multiplicand m storage locations Pattern leee leec 1300-1304: 13ee 14915BIF216BIF51F71F414BIF21F614e14e14el 13e4 leeleel381461901 Multiplicand (new) b $ 2 , 574 . 2 6 b b b Now, after the instruction: This pattern field prints as: Machine Format $2,574.26 Condition code 2 is set to indicate that the number edited was greater than zero. Op Code FC L1 L2 B1 4 1 D1 B2 D2 4 I 1eel 6 I eeel Pattern 1eee leec 14el4el4el4el4el5BIFel4BIF21F614ejc31091 b b b b b $ e . 2 6 b C R This pattern field prints as: $e.26 CR Condition code 1 is set because the number is less than zero. Multiply Decimal (MP) Assume that the signed, packed-decimal number in storage locations 1202-1204 (the multiplicand) is to be multiplied by the signed, packed-decimal number in locations 500-501 (the multiplier). 12e2 12e4 Multiplicand 1381461eol 5ee 5el Multiplier ~ The multiplicand must fust be extended to have at least two bytes of leftmost zeros, corresponding to the multiplier~ length, so as to avoid a data exception during the multiplication. ZERO AND ADD can be used to move the multiplicand into a longer field. Assume: Register 4 contains 00 00 12 00. Assembler Format Op Code D1(L1,B1),D2(L2,B2) MP X' 1ee ' (5,4),0(2,6) is executed, storage locations 1300-1304 contain the product: 01 23 45 66 OC. Shift and Round Decimal (SRP) The SHIFf AND ROUND DECIMAL (SRP) instruction can be used for shifting decimal numbers in storage to the left or right. When a number is shifted right, rounding can also be done. Decimal Left Shift In this example, the contents of storage location FIELDt are shifted three places to the left, effectively multiplying the contents of FIELD! by 1000. FIELDl is six bytes long. The following instruction performs the operation: Machine Fonnat Op Code Fe L1 S1 13 B2 5 Assembler Format Op Code Sl(L1),S2,I3 SRP FIELD1(6),3,e Register 6 contains 00 00 05 00. Then execution of the instruction: FIELDl (before): 0e 01 23 45 67 BC ZAP X' 100 1 (5,4),2(3,4) FIELD1 (after): A-36 ESA/370 Principles of Operation 12 34 56 78 ee ec The second-operand address in this instruction specifies the shift amount (three places). The rounding digit, 13, is not used in a left shift, but it must be a valid decimal digit. Mter execution, condition code 2 is set to show that the result is greater than zero. Decimal Right Shift and Round In this example, the contents of storage location FIELD3 are shifted three places to the right and rounded, in effect dividing by 1000 and rounding up. FIELD3 is four bytes in length. Machine Format Decimal Right Shift In this example, the contents of storage location FIELD2 are shifted one place to the right, effectively dividing the contents of FIELD2 by 10 and discarding the remainder. FIELD2 is five bytes in length. The following instruction perfonns this operation: Op Code L1 13 S1 82 D2 r 00111101 Machine Fonnat Op Code L1 13 S1 82 D2 6-bit two's complement for -3 Assembler Format r 00111111 SRP 6-bit two's complement for -1 Assembler Fonnat Op Code S1(L1),S2,I3 SRP 01 23 45 67 BC FIELD 2 (after): 00 12 34 56 7C The six-bit two's complement of a number, n, can be specified as 64 - n. In this example, a right shift of one is represented as 64 - 1. Condition code 2 is set. FIELD 3 (before): 12 39 60 0D FIELD 3 (after): 00 01 24 0D Condition code 1 is set because the result is less than zero. In the SRP instruction, shifts to the right are specified in the second-operand address by negative shift values, which are represented as a six-bit value in two's complement form. i FIELD3(4),64-3,5 The shift amount (three places) is specified in the D2 field. The 13 field specifies a rounding digit of 5. The rounding digit is added to the last digit shifted out (which is a 6), and the carry is propagated to the left. The sign is ignored during the addition. FIELD2(5),64-1,0 FIELD 2 (before): Op Code S1(L1),S2,I3 Multiplying by a Variable Power of 10 Since the shift value specified by the SRP instruction specifies both the direction and amount of the shift, the operation is equivalent to_multiplying the decimal ftrst operand by 10 raised to the power specified by the shift value. If the shift value is to be variable, it may be specified by the B 2 field instead of the displacement D 2 of the SRP instruction. The general register designated by B 2 should contain the shift value (power of 10) as a signed binary integer. Appendix A. Number Representation and Instruction-Use Examples A-37 A fixed scale factor modifying the variable power of 10 may be specified by using both the B2 field (variable part in a general register) and the D 2 field (fixed part in the displacement). The SRP instruction uses only the rightmost six bits of the effective address D2(B2) and interprets them as a six-bit signed binary integer to control the left or right shift as in the preceding shift examples. Add Normalized (AD, ADR, AE, AER, AXR) The ADD NORMALIZED instruction performs the addition of two floating-point numbers and places the normalized result in a floating-point register. Neither of the two numbers to be added must necessarily be in normalized form before addition occurs. For example, assume that: FPR6 contains the unnormalized number C3 08 21 00 00 00 00 00 = -82.116 = -130.0611:) approximately. Zero and Add (ZAP) Assume that the signed, packed-decimal number at storage locations 4500-4502 is to be moved to locations 4000-4004 with four leading zeros in the result field. Also assume: Storage locations 2000-2007 contain the normalized number 41 12 34 56 00 00 00 00 + 1.2345616 = + 1.1410 approximately. Register 9 contains 00 0040 00. Register 13 contains 00 00 20 00. Storage locations 4000-4004 contain 12 34 56 7890. Storage locations 4500-4502 contain 38 46 OD. The instruction: Machine Format Op Code Mter the instruction: 7A Machine Format Op Code F8 L1 L2 B1 4 2 9 01 eeel B2 9 5eel Op Code 01(L1,B1),02(L2,B2) ZAP 0(5,9),X'500'(3,9) is executed, the storage locations 4000-4004 contain 00 00 38 46 OD; condition code 1 is set to indicate a negative result without overflow. Note that, because the frrst operand is not checked for valid sign and digit codes, it may contain any combination of hexadecimal digits before the operation. Floating-Point Instructions (See Chapter 9 for a complete description of the floating-point instructions.) In this section, the abbreviations FPRO, FPR2, FPR4, and FPR6 stand for floating-point registers 0, 2,4, and 6 respectively. A-38 ESAj370 Principles of Operation X2 6 o B2 02 o I aeel 02 Assembler Format Op Code Rl,02(X2,B2) AE Assembler Format I R1 6,0(0,13) performs the short-precision addition of the two operands, as follows. The characteristics of the two numbers (43 and 41) are compared. Since the number in storage has a characteristic that is smaller by 2, it is right-shifted two hexadecimal digit positions. One guard digit is retained on the right. The fractions of the two numbers are then added algebraically: Fraction GOI FPR6 -43 08 21 00 Shifted number from storage +43 00 12 34 5 Intermediate sum Left-shifted sum 1 -43 08 0E CB B -42 80 EC BB Guard digit Because the intermediate sum is unnormalized, it is left-shifted to form the normalized floating-point number -80.ECBB16 = -128.921(:) approximately. Combining the sign with the characteristic, the result is C2 80 EC BB, which replaces the left half of FPR6. The right half of FPR6 and the contents of storage locations 2000-2007 are unchanged. Condition code 1 is set to indicate a result less than zero. If the long-precision instruction AD were used, the result in FPR6 would be C2 80 BC BA AO 00 00 00. Note that use of the long-precision instruction would avoid a loss of precision in this example. Add Unnormalized (AU, AUR, AW, AWR) The ADD UNNORMALIZED instruction operates the same as the ADD NORMALIZED instruction, except that the fmal result is not normalized. For example, using the the same operands as in the example for ADD NORMALIZED, when the shortprecision instruction: Machine Format Op Code 7E Rl X2 B2 6 0 0 Compare (CD, CDR, CE, CER) Assume that FPR4 contains 43 00 00 00 00 00 00 00 (zero), and FPR6 contains 35 12 34 56 78 9A BC DE (a positive number). The contents of the two registers are to be· compared using a longprecision co MP ARE instruction. Machine Format Op Code Rl R2 4 6 29 Assembler Format Op Code Rl,R2 COR 4,6 The number with the smaller characteristic, which is in register FPR6, is right-shifted 43 - 35 hex (67 - 53 decimal) or 14 digit positions, so that the two characteristics agree. The shifted number is 43 00 00 00 00 00 00 00, with a guard digit of one. Therefore, when the two numbers are compared, condition code 1 is set, indicating that operand I in FPR4 is less than operand 2 in FPR6. 02 eeel Assembler Format Op Code Rl,02(X2,B2) AU 6,0(0,13) is executed, the two numbers are added as follows: Fraction GOl FPR6 -43 08 21 00 Shifted number from storage +43 00 12 34 5 Intermediate sum 1 -43 08 0E CB B Guard di git The guard digit participates in the addition but is discarded. The unnormalized sum replaces the left half of FPR6. Condition code 1 is set because the result is less than zero. The truncated result in FPR6 (C3 08 OE CB 00 00 00 00) shows a loss of a significant digit when compared to the result of short-precision normalized addition. If the example is changed to a second operand with a characteristic of 34 instead of 35, so that FPR6 contains 34 12 34 56 78 9A BC DE, the operand is right-shifted 15 positions, leaving all fractiqn digits and the guard digit as zeros. Condition code 0 is set, indicating equality. This example shows that two floating-point numbers with different characteristics or fractions may compare equal if the numbers are unnormalized or zero. As another example of comparing unnormalized floating-point numbers, 41 00 12 34 56 78 9A BC compares equal to all numbers of the form 3F 12 34 56 78 9A BC OX (X represents any hexadecimal digit). When the COMPARE instruction is executed, the two rightmost digits are shifted right two places, the 0 becomes the guard digit, and the X does not participate in the comparison. However, when two normalized floating-point numbers are compared, the relationship between numbers that compare equal is unique: each digit in one number must be the same as the corresponding digit in the other number. Appendix. A. Number Representation and Instruction-Use Examples A-39 - Divide (DD, DDR, DE, DER) Assume that the frrst operand (the dividend) is in FPR2 and the second operand (the divisor) in FPRO. If the operands are in the short-precision format, the resulting quotient is returned to FPR2 by the instruction: Case c shows a number being divided by 4.0. Case D divides the same number by 2.0, and case E divides the result of case D again by 2.0. The results of cases c and E differ in the rightmost hexadecimal digit position, which illustrates an effect of result truncation. Halve (HDR, HER) Machine Format Op Code Rl R2 2 0 3D produces the same result as floating-point with a divisor of 2.0. Assume FPR2 contains the long-precision number + 48 30 00 00 00 00 00 OF. The following HALVE instruction produces the result + 48 18 00 00 00 00 00 07 in FPR2: HALVE DIVIDE Assembler Format Machine Format Op Code Rl,R2 OER Op Code 2,0 Rl R2 2 2 24 Several examples of short-precision floating-point division, with the dividend in F PR2 and the divisor . in FPRO, are shown below. For case A, the result, which replaces the dividend, is obtained in the following steps. 7.2522F Assembler Format Op Code Rl,R2 HDR .1234001.821000 7F6C00 2,2 Multiply (MD, MDR, ME, MER, MXD, MXDR, MXR) 2A400 0 24680 0 For this .example, the following long-precision operands are in FPRO and FPR2: 5D80 00 5B04 00 FPR9: FPR2: 27C 000 246 800 -33 606060 60606069 -5A 200000 20000020 A long-precision product is generated by the instruction: 35 8000 24 6800 Machine Format Op Code 11 18009 11 10C09 Rl R2 o 2C 2 7409 Case A B C D E A-40 FPR2 Before (Dividend) FPRB (Divisor) FPR2 After (Quotient) -43 +42 +48 +48 +48 +43 +45 +41 +41 +41 -42 +3D +47 +48 +47 082100 101010 30000F 30000F 180007 001234 111111 400000 200000 200000 ESA/370 Principles of Operation 72522F F0F0F0 C0003C 180007 C00038 Assembler Format Op Code Rl,R2 MDR 0,2 If the operands were not already normalized, the instruction would frrst normalize them. It then generates an intermediate result cons~sting of. the full 28-digit hexadecimal product fractIOn obtamed by multiplying the 14-digit hexadecimal operand fractions, together with the appropriate sign and a characteristic that is the sum of the operand characteristics less 64 (40 hex): The fraction multiplication is performed as follows: TW031: This is an unnormalized long floating-point number with the characteristic 4E, which corresponds to a radix point (hexadecimal point) to the right of the number. The following instruction sequence performs the conversion: .60606060606060 .20000020000020 X C0C0C0C0C0C0C00 C0C0C0C0C0C0C0 C0C0C0C0C0C0C0 MVC Attaching the sign and characteristic to the fraction gives: +40 0C0C0C 18181824 1818180C 0C0C00 Because this intermediate product has a leading zero, it is then normalized. The truncated fmal result placed in FPRO is: +4C C0C0C1 81818241 Floating-Point-Number Conversion The following examples illustrate one method of converting between binary fixed-point numbers (32-bit signed binary integers) and normalized floating-point numbers. Conversion must provide for the different representations used with negative numbers: the two's-complement form for signed binary integers, and the signed-absolute-value form for the fractions of floating-point numbers. Fixed Point to Floating Point The method used here inverts the leftmost bit of the 32-bit signed binary integer, which is equivalent to adding 231 to the number and considering the result to be positive. This changes the number from a signed integer in the range 231 - 1 through _2 31 to an unsigned integer in the range 232 - I through O. Mter conversion to the long floatingpoint fonnat, the value 231 is subtracted again. Assume that general register 9 (G R9) contains the integer -59 in two's-complement form: GR9: FF FF FF C5 Further, assume two eight-byte fields in storage: TEMP, Jor use as temporary storage, and TW031 , which ~ontains the floating-point constant 231 in the following format: LD SD Result GR9: 7FFF FFCS 9,TEMP+4 TEMP: xxxx xxxx 7FFF FFC5 TEMP(4),TW031 TEMP: 4EOO 0000 7FFF FFCS 2,TEMP FPR2: 4EOO 0000 7FFF FFC5 2,TW031 FPR2: C23B 0000 0000 0000 9,TW031 + 4 ST .0C0C0C181818241818180C0C0C00 4E 00 00 00 80 00 00 00 The EXCLUSIVE OR (X) instruction inverts the leftmost bit in general register 9, using the right half of the constant as the source for a leftmost one bit. The next two instructions assemble the modified number in an unnormalized long floating-point format, using the left half of the constant as the plus sign, the characteristic, and the leading zeros of the fraction. LOAD (LD) places the number unchanged in floating-point register 2. The SUBTRACT NORMALIZED (SD) instruction performs the fmal two steps by subtracting 231 in floating-point form and normalizing the result. Floating Point to Fixed Point The procedure described here consists basically in reversing the steps of the previous procedure. Two additional considerations must be taken into account. First: the floating-point number may not be an exact integer. Truncating the excess hexadecimal digits on the right requires shifting the number one digit position farther to the right than desired for the fmal result, so that the units digit occupies the position of the guard digit. Second: the floating-point number may have to be tested as to whether it is outside the range of numbers representable as a 32-bit signed binary integer. Assume that floating-point register 6 contains the number 59.251 a = 3B.416 in normalized form: FPR6: 42 3B 40 00 00 00 00 00 Further, assume three eight-byte fields in storage: TEMP, for use as temporary storage, and the con- Appendix A. Number Representation and Instruction-Use Examples A·41 stants 232 (TW032) and 231 lowing fO,rmats: TW032: TW031R: (TW031R) in the fol- 4E 00 00 01 00 00 00 00 4F 00 00 00 0S 00 00 00 The constant TW031 R is shifted right one more position than the constant TW031 of the previous example, so as to force the units digit into the guard-digit position. The following instruction sequence performs the integer truncation, range tests, and conversion to a signed binary integer in general register 8 (GRS): Result SD BC AW BC STD XI L 6,TW031R FPR6: C87F FFFF C500 0000 II,OVERFLOW Branch to overflow routine if result is greater than or equal to zero 6,TW032 FPR6: 4EOO 0000 8000 003B 4,OVERFLOW Branch to overflow routine if result is less than zero 6,TEMP TEMP: 4EOO 0000 8000 003B TEMP+4,X'80' TEMP: 4EOO 0000 0000 003B 8,TEMP+4 GR8: 0000003B The SUBTRACT NORMALIZED (SD) instruction shifts the fraction of the number to the right until it lines up with TW031 R, which causes the fraction digit 4 to fall to the right of the guard digit and be lost; the result of subtracting 231 from the remaining digits is renormalized. The result should be less than zero; if not, the original number was too large in the positive direction. The frrst BRANCH ON CONDITION (BC) performs this test. Multiprogramming and Multiprocessing Examples '" When two or more programs sharing common storage locations are being executed concurrently in a multiprogramming or multiprocessing environment, one program may, for example, set a flag bit in the common-storage area for testing by another program; It should be noted that the instructions AND (NI or NC), EXCLUSIVE OR (XI or XC), and OR (01 or oc) could be used to set flag bits in a multiprogramming environment; but the same instructions may cause program logic errors in a multiprocessing configuration where two or more cpus can fetch, modify, and store data in the same storage locations simultaneously. Example of a Program Failure Using OR Immediate Assume that two independent programs try to set different bits to one in a common byte in storage. The following example shows how the use of the instruction OR immediate (01) can fail to accomplish this, if the programs are executed simultaneously on two different cpus. One of the possible error situations is depicted. Execution of instruction 01 FLAGS t X'01' on CPU A FLAGS X'00' Fetch FLAGS X'00' GRS. A-42 ESA/370 Principles of Operation Store X'01' into FLAGS OR X'S0' into X'00' X'00' X'S0' The ADD UNNORMALIZED (AW) instruction adds 232: 231 to correct for the previous subtraction and another 231 to change to an all-positive range. The second BC tests for a result less than zero, showing that the original number was too large in the negative direction. The unnormalized result is placed in temporary storage by the STORE (STD) instruction. There the leftmost bit of the binary integer is inverted by the EXCLUSIVE OR (XI) instruction to subtract 231 and thus convert the unsigned number to the signed format. The final result is loaded into Fetch FLAGS X'00' X'00' X'00' OR X'01' into X'00' Execution of instruction 01 FLAGS t X'S0' on CPU B Store X'S0' into FLAGS X'01' FLAGS should have value of X'Sl' following both updates. The problem shown here is that the value stored by the 01 instruction executed on CPU A overlays the value that was stored by CPU B. The X' 80 I flag bit was erroneously turned off, and the data is now invalid. The COMPARE AND SWAP instruction has been provided to overcome this and similar problems. Conditional Swapping Instructions (CS, CDS) The COMPARE AND SWAP (cs) and COMPARE DOUBLE AND SWAP (CDS) instructions can be used in multiprogramming or multiprocessing environments to serialize access to counters, flags, control words, and other common storage areas. The following examples of the use of the COMPARE AND SWAP and COMPARE DOUBLE AND SWAP instructions illustrate the applications for which the instructions are intended. It is important to note that these are examples of functions that can be performed by programs while the CPU is enabled for interruption (multiprogramming) or by programs that are being executed in a multiprocessing configuration. That is, the routine allows a program to modify the contents of a storage location while the CPU is enabled, even though the routine may be interrupted by another program on the same CPU that will update the location, and even though the possibility exists that another CPU may simultaneously update the same location. The COMPARE AND SWAP instruction frrst checks the value of a storage location and then modifies it only if the value is what the program expects; normally this would be a previously fetched value. If the value in storage is not what the program expects, then the location is not modified; instead, the current value of the location is loaded into a general register, in preparation for the program to loop back and try again. During the execution of COMPARE AND SWAP, no other CPU can perform a store access or interlocked-update access at the specified location. Setting a Single Bit The following instruction sequence shows how the COMPARE AND SWAP instruction can be used to set a single bit in storage to one. Assume that the frrst byte of a word in storage called "WORD" contains eight flag bits. LA 6,X'B0 1 SLL 6,24 Put bit to be ORed into GR6 Shift left 24 places to align the byte to be ORed with the location of the flag bits within WORD L 7,WORD Fetch current flag values Load flags into GRB RETRY LR B,7 Set bit to one OR B,6 CS 7,B,WORD Store new flags if current flags unchanged, or refetch current flag values if changed BC 4,RETRY If new flags are not stored, try again The format of the is: COMPARE AND SWAP instruction Machine Format Op Code BA Rl R3 S2 7 Assembler Format Op Code Rl,R3,S2 CS 7,8,WORD The COMPARE AND SWAP instruction compares the frrst operand (general register 7 containing the current flag values) to the second operand in storage (WORD) while no CPU other than the one executing the COMPARE AND SWAP instruction is permitted to perform a store access or interlockedupdate access at the specified storage location. If the comparison is successful, indicating that the flag bits have not been changed since they were fetched, the modified copy in general register 8 is stored into WORD. If the flags have been changed, the compare will not be successful, and their new values are loaded into gener~l register 7. The conditional branch (BC) instruction tests the condition code and reexecutes the flag-modifying instructions if the COMPARE AND SWAP instruction indicated an unsuccessful comparison (condition code 1). When the COMPARE AND SWAP instruction is successful (condition code 0), the flags contain valid data, and the program exits from the loop. The branch to RETRY will be taken only if some other program modifies the contents of WORD. Appendix A. Number Representation and Instruction-Use Examples A-43 1ms type of a loop differs from the typical "bitspin" loop. In a bit-spin loop, the program continues to loop until the bit changes. In this example, the program continues to loop only if the value does change during each iteration. If a number of CPUs simultaneously attempt to modify a single location by using the sample instruction sequence, one CPU will fall through on the rust try, another wi11loop once, and so on until all cpus have succeeded. CPU A GR7 GR8 CPU B Comments GR7 GR8 CNTR 16 16 16 16 16 17 17 17 Updating Counters In this example, a 32-bit counter is updated by a program using the COMPARB AND SWAP instruction to ensure that the counter will be correctly updated. The original value of the counter is obtained by loading the word containing the counter into general register 7. 1ms value is moved into general register 8 to provide a modifiable copy, and general register 6 (containing an increment to the counter) is added to the modifiable copy to provide the updated counter value. The COMPARB AND SWAP instruction is used to ensure valid storing of the counter. The program updating the counter checks the result by examining the condition code. The condition code 0 indicates a successful update, and the program can proceed. If the counter had been changed between the time that the program loaded its original value and the time that it executed the COMPARB AND SWAP instruction, the execution would have loaded the new counter value into general register 7 and set the condition code to I, indicating an unsuccessful update. The program must then repeat the update sequence until the execution of the COMPARB AND SWAP instruction results in a successful update. 17 18 18 Bypassing Post and Wait Bypass Post Routine The following routine allows the svc "POST" as used in MVS/ESA to be bypassed whenever the correspondmg WAIT has not yet been executed, provided that the supervisor WAIT and POST routines use COMPARB AND SWAP to manipulate event control blocks (BCBS). Initial Conditions: GRO contains the POST code. GRl contains the address of the BCB. GRS contains 40 00 00 0016 HSPOST OR L LTR BC The following instruction sequence performs the above procedure: Put increment (1) into GR6 Put original counter value into GR7 LOOP LR 8,7 Set up copy in GR8 to modify AR 8,6 Increment copy CS 7,8,CNTR Update counter in storage BC 4,LOOP If original value had changed, update new value LA 6,1 L 7,CNTR The following shows two Cpus, A and B, executing this instruction sequence simultaneously: both CPus attempt to add, one to CNTR. A-44 ESAj370 Principles of Operation CPU A loads GR7 and GR8 from CNTR CPU B loads GR7 and GR8 from CNTR CPU B adds one to GR8 CPU A adds one to GR8 CPU A executes CSj successful match, store CPU B executes CS; no match, GR7 changed to CNTR value CPU B loads GR8 from GR7, adds one to GR8 CPU B executes CS; successful match, store PSVC 0,5 3,0(1) 3,3 4,PSVC CS 3,0,0(1) BC 8,EXITHP POST (1),(0) Set bit 1 of GR1 to to one GR3 = contents of ECB ECB marked 'waiting'? Yes, execute post SVC No, store post code Continue ECB address is in GR1, post code in GR0 EXITHP [Any instruction] The following routine may be used in place of the previous HSPOST routine if it is assumed that bit I of the contents of GRO is already set to one and if the BCB is assumed to contain zeros when it is not marked "WAITING." HSPOST SR CS BC POST EXITHP [Any SRR must use either the LIFO queuing scheme or the FIFO scheme; the two cannot be mixed. When more complex queuing is required, it is suggested that the queue for the SRR be locked using one of the two methods shown. 3,3 3,O,O(1) 8,EXITHP (1),(O) instruction] Bypass Walt Routine A BYPASS WAIT function, corresponding to the BYP ASS POST, does not use the cs instruction, but the FIFO LOCK/UNLOCK routines which follow assume its use. HSWAIT TM BC 0(1),X'40' 1,EXITHW If bit 1 ;s one, then ECB is already posted; branch to exit WAIT ECB=(1) EXITHW [Any instruction] Lock/Unlock When a common storage area larger than a doubleword is to be updated, it is usually necessary to provide special interlocks to ensure that a single program at a time updates the common area. Such an area is called a serially reusable resource (SRR). In general, updating a list, or even scanning a list, cannot be safely accomplished without frrst "freezing" the list. However, the COMPARE AND SWAP and COMPARE DOUBLE AND SWAP instructions can be used in certain restricted situations to perform queuing and list manipulation. Of prime importance is the capability to perform the lock/unlock functions and to provide sufficient queuing to resolve contentions, either in a LIFO or FIFO manner. The lock/unlock functions can then be used as the interlock mechanism for updating an SRR of any complexity. The lock/unlock functions are based on the use of a "header" associated with the SRR. The header is the common starting point for determining the states of the SRR, either free or in use, and also is used for queuing requests when contentions occur. Contentions are resolved using WAIT and POST. The general programming technique requires that the program that encounters a "locked" SRR must "leave a mark on the wall" indicating the address of an EeB on which it will WAIT. The "unlocking" program sees the mark and posts the ECB, thus permitting the waiting program to continue. In the two examples given, all programs using a particular Lock/Unlock with LIFO Queuing for Contentions The header consists of a word, that is, a four-byte field aligned on a word· boundary. The word can contain zero, a positive value, or a negative value. • A zero value indicates that the serially reusable resource (SRR) is free. • A negative value indicates that the SRR is in use but no additional programs are waiting for the SRR. • A positive value indicates that the SRR is in use and that one or more additional programs are waiting for the SRR. Each waiting program is identified by an element in a chained list. The positive value in the header is the address of the element most recently added to the list. Each element consists of two words. The frrst word is used as an ECB; the second word is used as a pointer to the next element in the list. A negative value in a pointer indicates that the element is the last element in the list. The element is required only if the program fmds the SRR locked and desires to be placed in the list. The following chart describes the action taken for LIFO LOCK and LIFO UNLOCK routines. The routines following the chart allow enabled code to perform the actions described in the chart. Action Functi on Header Contains Header Contains Header Contains Positive Value Negative Value Zero LIFO LOCK (the incoming element is at location A) SRR is free. Set the header to a negative value. Use the SRR. SRR is in use. Store the contents of the header into location A+4. Store address A into the header. WAIT: the ECB is at location A. LIFO UNLOCK Error Some program is waiting for the SRR. Move the poi nter from the "last in" element into the header. POST: the ECB is in the Rlast in" element. The list is empty. Store zeros into the header. The SRR is free. Appendix A. Nu~ber Representation and Instruction-Use Examples A-45 LIFO LOCK Routine: Initial Conditions: contains the address of the incoming element. GRt G R2 contains the address of the header. LLOCK SR ST LNR TRYAGN CS GR3 = 0 Initialize the ECB GR0 =a negative value Set the header to a negative value if the header contains zeros Did the header contain BC 8,USE zeros? ST 3,4(1) No, store the value of the header into the pointer in the incoming element CS 3,1,0(2) Store the address of the incoming element into the header LA 3,0(0) GR3 = 0 BC 7,TRYAGN Did the header get updated? WAIT ECB=(l) Yes, wait for the resource; the ECB is in the incoming element [Any instruction] USE 3,3 3,0(1) 0,1 3,0,0(2) LIFO UNLOCK Routine: Initial Conditions: G R2 contains the address of the header. GR1 = the contents of the header LTR 1,1 Does the header contain a A negative value? BC 4,B No, load the pointer from L 0,4(1) CS 1,0,0(2) the "last in" element and store it in the header BC 7,A Did the header get updated? POST (1) Yes, post the "last in" element BC 15,EXIT Continue B SR 0,0 The header contains a negCS 1,0,0(2) ative value; free the BC 7,A header and continue EXIT [Any instruction] LUNLK L 1,0(2) Note that the LOAD instruction L 1,0(2) at location LUNLK would have to be CS I, I ,0(2) if it were not for the rule concerning storage-operand consistency. This rule requires the LOAD instruction to fetch a four-byte operand aligned on a word boundary such that, if another CPU changes the word being fetched by an operation which is also at least word- A -46 ESA/370 Principles of Operation consistent, either the entire new or the entire old value of the word is obtained, and not a combination of the two. (See the section "Storage-Operand Consistency" in Chapter 5, "Program Execution.") Lock/Unlock with FIFO Queuing for Contentions The header always contains the address of the most recently entered elemet;lt. The header is originally initialized .to contain the address of a posted ECD. Each program using the serially reusable resource (SRR) must provide an element regardless of whether contention occurs. Each program then enters the address of the element which it has provided into the header, while simultaneously it removes the address previously contained in the header. Thus, associated with any particular program attempting to use the SRR are two elements, called the "entered element" and the "removed element." The "entered element" of one program becomes the "removed element" for the immediately following program. Each program then waits on the removed element, uses the SRR, and then posts the entered element. When no contention occurs, that is, when the second program does not attempt to use the SRR until after the frrst program is fmished, then the POST of the frrst program occurs before the WAIT of the second program. In this case, the bypass-post and bypass-wait routines described in the preceding section are applicable. For simplicity, these two routines are shown only by name rather than as individual instructions. In the example, the element need be only a single word, that is, an ECB. However, in actual practice, the element could be made larger to include a pointer to the previous element, along with a program identification. Such information would be useful in an error situation to permit starting with the header and chaining through the list of elements to fmd the program currently holding the SRR. It should be noted that the element provided by the program remains pointed to by the header until the next program attempts to lock. Thus, in general, the entered element cannot be reused by the program. However, the removed element is available, so each program gives up one element and gains a new one. It is expected that the element removed by a particular program during one use of the SRR would then be used by that program as the entry element for the next request to the SRR. It should be noted that, since the elements are exchanged from one program to the next, the elements cannot be allocated from storage that would be freed and reused when the program ends. It is expected that a program would obtain its fust element and release its last element by means of the routines described in the section "Free-Pool Manipulation" in this appendix. The following chart describes the action taken for FIFO LOCK and FIFO UNLOCK. Function FIFO LOCK (the incoming element is at 1ocati on A) FIFO UNLOCK Action Store address A into the header. WAIT; the ECB is at the location addressed by the old contents of the header. POST; the ECB is at location A. The following routines allow enabled code to perform the actions described in the previous chart. FIFO Lock Routine: Initial conditions: G R3 contains the address of the header. GR4 contains the address, A, of the element currently owned by this program. This element becomes the entered element. FLOCK LR 2,4 GR2 now contains address of element to be entered SR 1,1 GR1 = 0 ST 1,0(2) Initialize the ECB GR1 = contents of the L 1,0(3) header TRYAGN CS 1,2,0(3) Enter address A into header while rememberBC 7,TRYAGN ing old contents of header into GR1; GRl now contains address of removed element Removed element becomes LR 4,1 new currently owned element HSWAIT Pel'form bypass-wai t routine; if ECB already posted, continue; if not, wait; GR1 contains the address of the ECB USE [Any instruction] FIFO Unlock Routine: Initial conditions: contains the address of the removed element, obtained during the FLOCK routine. GR2 G RS contains 40 00 00 001 6 1,2 Place address of entered element in GR1; GR1 = address of ECB to be posted SR 0,0 GR0 = 0; GR0 has a post code of zero OR 0,5 Set bit 1 of GR0 to one HSPOST Perform bypass-post routine; if ECB has not been waited on, then mark posted and continue; if it has been waited on, then post CONTI NUE [Any instruction] FUNLK LR Free-Pool Manipulation It is anticipated that a program will need to add and delete items from a free list without using the lock/unlock routines. This is especially likely since the lock/unlock routines require storage elements for queuing and may require working storage. The lock/unlock routines discussed previously allow simultaneous lock routines but permit only one unlock routine at a time. In such a situation, multiple additions and a single deletion to the list may all occur simultaneously, but multiple deletions cannot occur at the same time. In the case of a chain of pointers containing free storage buffers, multiple deletions along with additions can occur simultaneously. In this case, the removal cannot be done using the COMPARE AND SWAP instruction without a certain degree of exposure. Consider a chained list of the type used in the LI FO lock/unlock example. Assume that the fust two elements are at locations A and B, respectively. If one program attempted to remove the fust element and was interrupted between the fourth and fUth instructions of the LUNLK routine, the list could be changed so that elements A and C are the fust two elements when the interrupted program resumes execution. The COMPARE AND SWAP instruction would then succeed in storing the value B into the header, thereby destroying the list. The probability of the occurrence of such list destruction can be reduced to near zero by appending to the header a counter that indicates Appendix A. NUf!lber Representation and Instruction-Use Examples A-47 the number of times elements have been added to the list. The use of a 32-bit counter guarantees that the list will not be destroyed unless the following events occur, in the exact sequence: ADD TO FREE LIST Routine: Initial Conditions: GR2 contains the address of the element to be added. 1. An unlock routine is interrupted between the fetch of the pointer from the first element and the update of the header. GR4 contains the address of the header. 3. The element referenced in 1 is added to the list. O,1,O(4) GR0,GR1 = contents of the header TRYAGN ST O,O(2) Point the new element to the top of the list LR 3,1 Move the count to .GR3 BCTR 3,O Decrement the count CDS O,2,O(4) Update the header BC 7,TRYAGN 4. The unlock routine interrupted in 1 resumes execution. DELETE FROM FREE LIST Routine: 2. The list is manipulated, including the deletion of the element referenced in 1, and exactly 232 _1 additions to the list are performed. Note that this takes on the order of days to perform in any practical situation. The following routines use such a counter in order to allow multiple, simultaneous additions and removals at the head of a chain of pointers. The list consists of a doubleword header and a chain of elements. The first word of the header contains a pointer to the frrst element in the list. The second word of the header contains a 32-bit counter indicating the number of additions that have been made to the list. Each element contains a pointer. to the next element in the list. A zero value indicates the end of the list. The following chart describes the free-pool-list manipulation. Action Function Header • a,Count Header • A,Count ADD TO LIST (the incoming element is at location A) Store the first word of the header into location A. Store the address A into the first word of the header. Decrement the second word of the,header by one. DELETE FROM LIST The list is empty. Set the first word of the header to the value of the contents of location A. Use element A. The following routines allow enabled code to perform the free-pool-list manipulation described in the above chart. A-48 ESA/370 Principles of Operation ADDQ LM Initial conditions: GR4 contains the address of the header. DELETQ LM 2,3,O(4) TRYAGN LTR BC 2,2 8, EMPTY O,O(2) L USE LR CDS BC [Any GR2,GR3 = contents of the header Is the list empty? Yes, get help No, GR0 = the pointer from the first element Move the count GR1 Update the header 1,3 2,O,O(4) 7,TRYAGN instruction] The address of the removed element is in GR2 Note that the LM (LOAD MULTIPLE) instructions at locations ADDQ and DELETQ would have to be CDS (COMPARE DOUBLE AND SWAP) instructions if it were not for the rule concerning storage-operand consistency. This rule requires the LOAD MULTIPLE instructions to fetch an eight-byte operand aligned on a doubleword boundary such that, if another CPU changes the doubleword being fetched by an operation which is also at least doublewordconsistent, either the entire new or the entire old value of the doubleword is obtained, and not a combination of the two. (See the section "Storage,Operand Consistency" in Chapter 5, "Program Execution. ") Appendix B. Lists of Instructions The following figures list instructions by name, mnemonic, and operation code. Some models may offer instructions that do not appear in the figures, such as those provided for assists or as part of special or custom features. E EO EU EX FK 00 The operation codes for the vector facility and for interpretive execution are not included in this appendix. See the publications Enterprise Systems Architecture/370 and System/370 Vector Operations, SA22-7125, and IBM System/370 Extended Architecture Interpretive Execution, SA22-7095, for operation codes associated with these facilities. 01 02 OM OS The operation code 00 hex with a two-byte instruction format is allocated for use by the program when an indication of an invalid operation is required. It is improbable that this operation code will ever be assigned to an instruction implemented in the CPU. Explanation of Symbols In "Characteristics" and "Page" Columns: ¢ ¢1 $ A A1 AI AS AT B Bl B2 BP e D DF DK DM Causes serialization and checkpoint synchronization. Causes serialization and checkpoint synchronization when the M1 and R2 fields contain all ones and all zeros, respectively. Causes serialization. Access exceptions for logical addresses. Access exceptions; not all access exceptions may occur; see instruction description for details. Access exceptions for instruction address. ASN-translation-specification and specialoperation exceptions. ASN-translation-specification exception. PER branch event. Bl field designates an access register in the access-register mode. B2 field designates an access register in the access-register mode. B2 field designates an access register when psw bits 16 and 17 have the value 01. Condition code is set. Data exception. Decimal-overflow exception. Decimal-divide exception. Depending on the model, DIAONOSE may generate various program exceptions and may change the condition code. IF II IK 11 14 L LS MD MI MK MO OP P Q R Rl RR RRE RS RX S SE SF SI SO SP E instruction format. Exponent-overflow exception. Exponent-underflow exception. Execute exception. Floating-point-divide exception. Instruction execution includes the implied use of general register O. Instruction execution includes the implied use of general register 1. Instruction execution includes the implied use of general register 2. Instruction execution includes the implied use of multiple general registers. Instruction execution includes the implied use of general register 1 as the subsystemidentification word. Fixed-point-overflow exception. Interruptible instruction. Fixed-point-divide exception. Access register 1 is implicitly designated in the access-register mode. Access register 4 is implicitly designated in the access-register mode. New condition code is loaded. Significance exception. Designation of access registers in the access-register mode is model-dependent. Move-inverse facility. Move-with-source-or-destination-key facility. Monitor event. Operand exception. Privileged-operation exception. Privileged-operation exception for semiprivileged instructions. PER general-register alteration event. Rl field designates an access register in the access-register mode. R2 field designates an access register in the access-register mode. RR instruction format. RRE instruction format. RS instruction format. RX instruction format. S instruction format. Special operation, stack-empty, stackspecification, and stack-type exceptions. Special-operation, stack-full, and stackspecification exceptions. SI instruction format. Special-operation exception. Specification exception. • Appendix B. Lists of Instructions 8-1 SS SSE ST SU SW T U U. UB z· B-2 ss instruction format. SSE instruction format. PER storage-alteration event. PER store-using-real-address event. Special-operation exception and spaceswitch event. Trace exceptions (which include trace table, addressing, and low-address protection). Condition code is unpredictable. R. field designates an access register unconditionally. R2 field designates an access register unconditionally. R. and R, fields designate access registers unconditionally, and B2 field designates an access register in the access-register mode. Additional exceptions and events for PROGRAM CALL (which include AFX -translation, ASN -translation,specification, ASX -translation, EX -translation, Lx-translation, pc-translation- ESA/370 Principles of Operation specification, special-operation, stack-full, and stack-specification exceptions and space-switch event). Additional exceptions and events for PROGRAM TRANSFER (which include AFX -translation, ASN -translationspecification, ASX -translation, primaryauthority, and special-operation exceptions and space-switch event). Additional exceptions for SET SECONDARY ASN (which include AFX translation, ASN-translation specification, ASX translation, secondary authority, and special operation). Additional exceptions and events for PROGRAM RETURN (which include AFx-translation, ASN-translationspecification, ASX -translation, secondaryauthority, special-operation, stack-empty, stack-operation, stack-specification, and stack-type exceptions and space-switch event). Name ADD ADD ADD DECIMAL ADD HALFWORD ADD LOGICAL ADD ADD ADD ADD ADD LOGICAL NORMALIZED NORMALIZED NORMALIZED NORMALIZED ADD ADD ADD ADD ADD NORMALIZED (short) UNNORMALIZED (long) UNNORMALIZED (long) UNNORMALIZED (short) UNNORMALIZED (short) (extended) (long) (long) (short) AND AND AND (character) AND (immediate) BRANCH AND LI NK BRANCH BRANCH BRANCH BRANCH BRANCH AND AND AND AND AND BRANCH BRANCH BRANCH BRANCH BRANCH AND STACK ON CONDITION ON CONDITION ON COUNT ON COUNT Mnemonic AR A AP AH ALR RR RX SS RX RR C C C C C AL AXR ADR AD AER RX RR RR RX RR C C XP C C C SP SP A SP SP EO EO EO EO AE AWR AW AUR AU RX RR RX RR RX C C C C C A SP EU EO SP EO EO A SP SP EO EO A SP NR N NC NI BALR RR RX SS SI RR C C C C A A A LI NK BAL SAVE BASR BAS SAVE SAVE AND SET MODE BASSM SET MODE BSM BAKR BCR BC BCTR BCT A A A lA B2 5A ST Bl B2 FA B2 4A R IE R 7-8 7-8 8-5 7-8 7-9 LS LS LS LS B2 5E 36 2A B2 6A 3A 7-9 9-7 9-7 9-7 9-7 LS LS LS LS LS B2 7A 2E B2 6E 3E B2 7E 9-7 9-8 9-8 9-8 9-8 IF IF 0 OF IF R R \ A R EU EU EU EU 14 B2 54 ST Bl B2 04 ST Bl 94 05 BR 7-9 7-9 7-9 7-9 7-10 BR BR BR BR BR 45 00 40 0C 0B 7-10 7-11 7-11 7-11 7-12 B ST B B BR BR B240 07 47 06 46 10-5 7-12 7-12 7-13 7-13 A 86 87 B230 19 B2 59 7-14 7-14 14-4 7-15 7-15 29 B2 69 39 B2 79 B21A 9-9 9-9 9-9 9-9 7-15 R R T RX RR RX RR RR T T Al RRE RR RX RR RX SF T ¢1 BRANCH ON INDEX HIGH BXH RS BRANCH ON INDEX LOW OR EQUAL BXLE RS CSCH S C CLEAR SUBCHANNEL CR COMPARE RR C COMPARE C RX C BR BR OP P COMPARE COMPARE COMPARE COMPARE COMPARE (long) (long) (short) (short) AND FORM CODEWORD CDR CD CER CE CFC RR RX RR RX S C C C C C SP A SP SP A SP A SP II COMPARE COMPARE COMPARE COMPARE COMPARE AND SWAP DECIMAL DOUBLE AND SWAP HALFWORD LOGICAL CS CP CDS CH CLR RS SS RS RX RR C C C C C A SP 0 A A SP A Figure Op Page Code No. Characteristics ¢ GS GM $ $ R R ST 11 B2 Bl B2 R ST B2 B2 BA F9 BB 49 15 7-19 8-5 7-19 7-20 7-21 B-1 (Part 1 of 6). Instructions Arranged by Name Appendix B. Lists of Instructions B-3 Mnemonic Name COMPARE COMPARE COMPARE COMPARE COMPARE LOGICAL LOGICAL LOGICAL LOGICAL LOGICAL (character) (immediate) C. UNDER MASK LONG CONVERT TO BINARY CONVERT TO DECIMAL COPY ACCESS DIAGNOSE DIVIDE CL CLC CLI CLM CLCL RX SS SI RS RR C C C C C A A A A A SP II CVB RX CVD RX CPYA RRE A A OM DR Op Page Code No. Characteristics B2 55 B1 B2 05 95 B1 B2 BD R1 R2 0F R 0 IK R SP 4F 4E B24D 83 IK R 10 7-23 7-24 7-24 10-7 7-25 IK FK FK FK FK R\ B2 50 B22D 20 B2 60 3D 7-25 9-9 9-9 9-9 9-9 ST P OM RR B2 B2 U1 U2 MD \ DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE 7-21 7-21 7-21 7-21 7-22 0 DXR DDR DO DER RX RRE RR RX RR A SP SP SP A SP SP DIVIDE (short) DIVIDE DECIMAL EDIT ED IT AND MARK EXCLUSIVE OR DE DP ED EDMK XR RX SS SS C SS C RR C A SP EU EO FK A SP 0 OK A 0 A 0 G1 B2 70 ST B1 B2 FD ST B1 B2 DE R ST B1 B2 OF R 17 9-9 8-6 8-6 8-10 7-25 EXCLUSIVE OR EXCLUSIVE OR (character) EXCLUSIVE OR (immediate) EXECUTE EXTRACT ACCESS X XC XI EX EAR RX C SS C SI C RX RRE A A A AI SP B2 57 ST B1 B2 07 ST B1 97 44 R U2 B24F 7-25 7-25 7-25 7-26 7-27 EXTRACT PRIMARY ASN EXTRACT SECONDARY ASN EXTRACT STACKED REGISTERS EXTRACT STACKED STATE HALT SUBCHANNEL EPAR ESAR EREG ESTA HSCH RRE RRE RRE RRE C S C B226 B227 U1 U2 B249 B24A B231 10-7 10-8 10-8 10-9 14-4 HALVE (long) HALVE (short) INSERT ADDRESS SPACE CONTROL INSERT CHARACTER INSERT CHARACTERS UNDER MASK HDR HER lAC IC ICM RR RR RRE C RX RS C INSERT PROGRAM MASK INSERT PSW KEY INSERT STORAGE KEY EXTENDED INSERT VIRTUAL STORAGE KEY INVALIDATE PAGE TABLE ENTRY IPM IPK ISKE IVSK IPTE RRE S RRE RRE RRE LOAD LOAD LOAD (long) LOAD (long) LOAD (short) LR L LOR LD LER RR RX RR RX RR (extended) (long) (long) ·(short) ESA/370 Principles of Operation EO EO EO EO R EX SO SO A1 SE A1 SP SE OP P R R R R Q Q ¢ GS SP EU SP EU SO Q R R R A A G2 Q P A1 A1 P A1 SO Q- A R R R $ R R A Figure 8-1 (Part 2 of 6). Instructions Arranged by Name 8-4 EU EU EU EU SP SP SP 24 34 B224 B2 43 B2 BF 9-11 9-11 10-12 7-27 7-27 B222 B20B B229 R2 B223 B221 7-28 10-12 10-13 10-13 10-14 18 B2 58 28 B2 68 38 7-28 7-28 9-12 9-12 9-12 Name Mnemonic LOAD LOAD LOAD LOAD LOAD (short) ACCESS MULTIPLE ADDRESS ADDRESS EXTENDED ADDRESS SPACE PARAMETERS LE LAM LA LAE LASP RX RS RX RX SSE C LOAD LOAD LOAD LOAD LOAD AND TEST AND TEST (long) AND TEST (short) COMPLEMENT COMPLEMENT (long) LTR LTDR LTER LCR LCDR RR RR RR RR RR C C C C C SP SP LOAD LOAD LOAD LOAD LOAD COMPLEMENT (short) CONTROL HALFWORD MULTIPLE NEGATIVE LCER LCTL LH LM LNR RR C RS RX RS RR C SP P A SP A A LOAD LOAD LOAD LOAD LOAD NEGATIVE NEGATIVE POSITIVE POSITIVE POSITIVE LNDR LNER LPR LPDR LPER RR RR RR RR RR C C C C C SP SP LOAD LOAD LOAD LOAD LOAD PSW REAL ADDRESS ROUNDED (ext. to long) ROUNDED (long to short) USING REAL ADDRESS LPSW LRA LRDR LRER LURA S L RX C RR RR RRE P A SP P Al AT SP EO SP EO P Al SP MODIFY STACKED STATE MODIFY SUBCHANNEL MONITOR CALL MOVE (character) MOVE (immediate) MSTA MSCH MC MVC MVI RRE S C SI SS SI Al SP SE P A SP OP SP A A MOVE MOVE MOVE MOVE MOVE INVERSE LONG NUMERICS TO PRIMARY TO SECONDARY MVCIN MVCL MVN MVCP MVCS SS MI A A SP II RR C SS A SS C Q A SO SS C Q A SO MOVE MOVE MOVE MOVE MOVE WITH DESTINATION KEY WITH KEY WITH OFFSET WITH SOURCE KEY ZONES MVCDK MVCK MVO MVCSK MVZ SSE MK Q A SS C Q A SS A SSE MK Q A SS A MR M MXR MXDR MXD RR RX RR RR RX (long) (short) (long) (short) MULTIPLY MULTIPLY MULTIPLY (extended) MULTIPLY (long to extended) MULTIPLY (long to extended) Figure Op Page Code No. Characteristics A SP A SP B2 78 UB 9A 41 Ul BP 51 E500 Bl R R P Al SP AS R IF 12 22 32 13 23 R SP 33 B2 B7 B2 48 B2 98 11 R R R IF B2 82 BP B1 25 35 B24B 10-24 10-25 9-14 9-14 10-27 B247 B2 B232 AF ST Bl B2 02 ST Bl 92 10-27 14-6 7-32 7-32 7-32 SP A SP SP EU EO SP EU EO A SP EU EO ¢ R R ST ST Bl B2 E8 R ST Rl R2 0E ST Bl B2 01 ST DA ST DB ¢ ¢ GM ST ST ST ST ST GM R R 9-12 10-23 7-30 7-31 7-31 9-13 9-13 7-31 9-13 9-13 R GS MO 7-30 9-12 9-12 7-30 9-12 21 31 10 20 30 SP SP ¢ 9-12 7-28 7-29 7-29 10-16 Bl Bl Bl Bl Bl B2 B2 B2 B2 B2 E50F 09 F1 E50E 03 lC B2 5C 26 27 B2 67 7-33 7-33 7-37 10-29 10-29 10-30 10-31 7-37 10-32 7-38 7-38 7-38 9-14 9-14 9-14 B-1 (Part 3 of 6). Instructions Arranged by Name Appendix B. Lists of Instructions 8-5 Name MULTIPLY MULTIPLY MULTIPLY MULTIPLY MULTIPLY Mnemonic MDR MD MER ME MP RR RX RR RX SS MULTIPLY HALFWORD OR OR OR (character) OR (immediate) MH OR 01 RX RR RX SS SI PACK PROGRAM CALL PROGRAM RETURN PROGRAM TRANSFER PURGE ALB PACK PC PR PT PALB SS S E U RRE RRE (long) (long) (short to long) (short to long) DECIMAL 0 OC SP A SP SP A SP A SP SET SET SET SET SET ADDRESS LIMIT ADDRESS SPACE CONTROL CHANNEL MONITOR CLOCK CLOCK COMPARATOR SAL SAC SCHM SCK SCKC S S S S S SET SET SET SET SET CPU TIMER PREFIX PROGRAM MASK PSW KEY FROM ADDRESS SECONDARY ASN SPT SPX SPM SPKA SSAR S S RR L S RRE SET STORAGE KEY EXTENDED SET SYSTEM MASK SHIFT AND ROUND DECIMAL SHIFT LEFT DOUBLE SHIFT LEFT DOUBLE LOGICAL SSKE SSM SRP SLDA SLDL RRE S SS C RS C RS SHIFT SHIFT SHIFT SHIFT SHIFT LEFT SINGLE LEFT SINGLE LOGICAL RIGHT DOUBLE RIGHT DOUBLE LOGICAL RIGHT SINGLE SLA SLL SRDA SRDL SRA RS C RS RS C RS RS C SHIFT RIGHT SINGLE LOGICAL SIGNAL PROCESSOR START SUBCHANNEL STORE STORE (long) SRL SIGP SSCH ST STD RS RS C S C RX RX 8-6 EO EO EO EO R R R A A A 9-14 9-14 9-14 9-14 8-10 B2 4C 16 B2 56 ST B1 B2 06 ST B1 96 7-39 7-40 7-40 7-40 7-40 ST B1 B2 F2 7-40 Z1 T ¢ GM B R ST B218 10-34 A1 Z4 T ¢2 B R ST 0101 10-44 Q A1 SP Z2 T ¢ B B228 10-47 P B248 10-52 $ A P P P A1 P $ OP ¢ Gl OP ¢ GS OP SP SW OP P P A SP P A SP P Ul ¢ Gl ¢ ¢ GM Q C 2C B2 6C 3C B2 7C ST B1 B2 FC Q Al P A SP P A SP A1 za T ¢ P A1 ¢ P A SP SO 0 OF A SP IF SP IF P $ P A SP OP A A SP ¢ GS 10-53 14-7 10-53 14-8 7-41 B237 B219 B23C B2 B204 B2 B206 14-10 10-54 14-10 10-55 10-56 B22B B2 80 ST B1 F0 8F R 80 R R R R R R SP SP B20D B23B B22A B238 B24E B2 B208 10-56 B2 B210 10-56 04 7-41 B20A 10-57 B225 10-58 $ Q 8-1. (Part 4 of 6). Instructions Arranged by Name ESA/370 Principles of Operation EU EU EU EU 0 A C C C C PURGE TLB PTLB S RESET CHANNEL PATH RCHP S C RESET REFERENCE BIT EXTENDED RRBE RRE C RESUME SUBCHANNEL RSCH S C SET ACCESS SAR RRE Figure Op Page Code No. Characteristics R R ST ST 10-61 10-61 8-11 7-42 7-42 . 8B 89 8E 8C 8A 7-43 7-43 7-43 7-44 7-44 88 7-45 10-61 14-12 7-45 9-16 AE B2 B233 B2 50 B2 60 Mnemonic Name STORE STORE STORE STORE STORE (short) ACCESS MULTIPLE CHANNEL PATH STATUS CHANNEL REPORT WORD CHARACTER STE STAM STCPS STCRW STC RX RS S S C RX A A PA PA A STORE STORE STORE STORE STORE CHARACTERS UNDER MASK CLOCK CLOCK COMPARATOR CONTROL CPU ADDRESS STCM STCK STCKC STCTL STAP RS S C S RS S A A P A SP P A SP P A SP STORE STORE STORE STORE STORE CPU 10 CPU TIMER HALFWORD MULTIPLE PREFIX STIDP STPT STH STM STPX S S RX RS S P A SP P A SP A A P A SP STORE SUBCHANNEL STORE THEN AND SYSTEM MASK STORE THEN OR SYSTEM MASK STORE USING REAL ADDRESS SUBTRACT STSCH STNSM STOSM STURA SR S C SI SI RRE RR C P A SP OP PA P A SP P A1 SP SUBTRACT SUBTRACT SUBTRACT SUBTRACT SUBTRACT DECIMAL HALFWORD LOGICAL LOGICAL S SP SH SLR SL RX SS RX RR RX C C C C C A A A SUBTRACT SUBTRACT SUBTRACT SUBTRACT SUBTRACT NORMALIZED NORMALIZED NORMALIZED NORMALIZED NORMALIZED SXR SDR SO SER SE RR RR RX RR RX C C C C C SP SP A SP SP A SP SWR SW SUR SU SVC RR RX RR RX RR C C C C SP A SP SP A SP TAR TS TB TPI TPROT RRE S RRE S SSE C C C C C TSCH TM TRACE TR TRT S C SI C RS SS SS C (ext.) (long) (long) (short) (short) SUBTRACT UNNORMALIZED SUBTRACT UNNORMALIZED SUBTRACT UNNORMALIZED SUBTRACT UNNORMALIZED SUPERVISOR CALL TEST TEST TEST TEST TEST ACCESS AND SET BLOCK PENDING INTERRUPTION PROTECTION TEST SUBCHANNEL TEST UNDER MASK TRACE TRANSLATE TRANSLATE AND TEST Figure (long) (long) (short) (short) Op Page Code No. Characteristics SP SP SP SP ST ST ST ST ST B2 UB B2 B2 B2 70 9B B23A B239 42 9-16 7-45 14-14 14-14 7-45 ST ST ST ST ST B2 B2 B2 B2 B2 BE B205 B207 B6 B212 7-46 7-46 10-63 10-63 10-63 ST ST ST ST ST B2 B2 B2 B2 B2 B202 B209 40 90 B211 10-64 10-64 7-47 7-47 10-65 ST B2 B234 ST B1 AC ST B1 AD SU B246 1B R 14-15 10-65 10-65 10-66 7-48 B2 ST B1 B2 B2 R R B2 R 5B FB 4B 1F 5F 7-48 8-12 7-48 7-48 7-48 ¢ ¢ $ ¢ GS IF IF 0 OF IF R A EU EU EU EU EU EO EO EO EO EO LS LS LS LS LS 37 2B B2 6B 3B B2 7B 9-16 9-16 9-16 9-16 9-16 EO EO EO EO LS LS LS LS 2F B2 6F 3F B2 7F 0A 9-17 9-17 9-17 9-17 7-49 ¢ A1 AS A P A1 II P A1 SP P A1 P A SP OP A T P A SP A A 8-1 (Part 5 of 6). Instructions Arranged by Name U1 $ $ G0 ¢ ¢ GS B24C B2 93 B22C R ST B2 B236 B1 E501 ST ST B2 B235 91 99 ST B1 B2 DC R B1 B2 DO B1 ¢ GM 10-66 7-49 10-69 14-16 10-71 14-17 7-50 10-73 7-50 7-51 --Appendix B. Lists of Instructions B-7 Name UNPACK UPDATE TREE ZERO AND ADD Figure 8-8 .. Mnemonic UNPK 55 UPT E C ZAP 55 C Characteristics A A 5P II 0 OF A 8-1 (Part 6 of 6). Instructions Arranged by Name ESA/370 Principles of Operation GM Op Page Code No. 5T Bl B2 F3 7-52 R 5T 14 0102 7-52 5T Bl B2 F8 8-12 Mnemonic Name A AD ADR AE DIAGNOSE ADD ADD NORMALIZED (long) ADD NORMALIZED (long) ADD NORMALIZED (short) RX RX RR RX OM C C C C AER AH AL ALR AP ADD ADD ADD ADD ADD NORMALIZED (short) HALFWORD LOGICAL LOGICAL DECIMAL RR RX RX RR SS C C C C C A A AR AU AUR AW AWR ADD ADD ADD ADD ADD UNNORMALIZED UNNORMALIZED UNNORMALIZED UNNORMALIZED RR RX RR RX RR C C C C C A SP SP A SP SP AXR BAKR BAL BALR BAS ADD NORMALIZED (extended) BRANCH AND STACK BRANCH AND LI NK BRANCH AND LI NK BRANCH AND SAVE BASR BASSM BC BCR BCT BRANCH BRANCH BRANCH BRANCH BRANCH BCTR BSM BXH BXLE C BRANCH ON COUNT RR BRANCH AND SET MODE RR BRANCH ON INDEX HIGH RS BRANCH ON INDEX LOW OR EQUAL RS COMPARE RX C CD CDR CDS CE CER COMPARE COMPARE COMPARE COMPARE COMPARE (long) (long) DOUBLE AND SWAP (short) (short) RX RR RS RX RR CFC CH CL CLC CLCL COMPARE COMPARE COMPARE COMPARE COMPARE AND FORM CODEWORD HALFWORD LOGICAL LOGICAL (character) LOGICAL LONG CLI CLM CLR CP CPYA COMPARE LOGICAL (immediate) COMPARE LOGICAL C. UNDER MASK COMPARE LOGICAL COMPARE DECIMAL COPY ACCESS Figure Op Page Code -No. Characteristics (short) (short) (long) (long) RR C XP RRE RX RR RX P OM A IF A SP EU EO SP EU EO A SP EU EO LS LS LS SP EU EO IF LS R R R 0 OF A MD 83 B2 5A B2 6A 2A B2 7A R IF EO EO EO EO LS LS LS LS SP EU EO SF T LS 10-7 7-8 9-7 9-7 9-7 3A B2 4A B2 5E IE ST Bl B2 FA 9-7 7-8 7-9 7-9 8-5 lA B2 7E 3E B2 6E 2E 7-8 9-8 9-8 9-8 9-8 R B ST BR BR BR 36 B240 45 05 40 9-7 10-5 7-10 7-10 7-11 BR BR B B BR 00 0C 47 07 46 7-11 7-11 7-12 7-12 7-13 BR BR BR BR A 06 0B 86 87 B2 59 7-13 7-12 7-14 7-14 7-15 C C C C C A SP SP A SP A SP SP B2 69 29 B2 BB B2 79 39 9-9 9-9 7-19 9-9 9-9 S RX RX SS RR C C C C C A SP II A A A A SP II SI RS RR SS RRE C C C C A A Al T AND SAVE RR AND SAVE AND SET MODE RR ON CONDITION RX ON CONDITION RR ON COUNT RX T T ¢1 A R ST $ GM R 11 R B2 B2 Bl B2 Rl R2 B21A 49 55 05 0F 7-15 7-20 7-21 7-21 7-22 95 B2 BD 15 Bl B2 F9 Ul U2 B24D 7-21 7-21 7-21 8-5 7-24 B1 0 B-2 (Part 1 of 6). Instructions Arranged by Mnemonic Appendix B. Lists of Instructions 8-9 Mnemonic Name CR CS CSCH CVB CVD COMPARE COMPARE AND SWAP CLEAR SUBCHANNEL CONVERT TO BINARY CONVERT TO DECIMAL RR C RS C S C RX RX 0 00 DDR DE DER DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE RX RX RR RX RR A SP A SP EU SP EU A SP EU SP EU DP DR DXR EAR ED DIVIDE DECIMAL DIVIDE DIVIDE (extended) EXTRACT ACCESS EDIT SS RR RRE RRE SS C OK A SP 0 SP IK SP EU EO FK EDMK EPAR EREG ESAR ESTA EDIT AND MARK EXTRACT PRIMARY ASN EXTRACT STACKED REGISTERS EXTRACT SECONDARY ASN EXTRACT STACKED STATE SS C RRE RRE RRE RRE C SO A1 SE Q SO A1 SP SE EX HDR HER HSCH lAC EXECUTE HALVE (long) HALVE (short) HALT SUBCHANNEL INSERT ADDRESS SPACE CONTROL RX RR RR S C RRE C AI SP SP EU SP EU OP P Q SO IC ICM IPK IPM IPTE INSERT CHARACTER INSERT CHARACTERS UNDER MASK INSERT PSW KEY INSERT PROGRAM MASK INVALIDATE PAGE TABLE ENTRY RX RS C S RRE RRE ISKE IVSK L LA LAE INSERT STORAGE KEY EXTENDED INSERT VIRTUAL STORAGE KEY LOAD LOAD ADDRESS LOAD ADDRESS EXTENDED RRE RRE RX RX RX LAM LASP LCDR LGER LCR LOAD LOAD LOAD LOAD LOAD ACCESS MULTIPLE ADDRESS SPACE PARAMETERS COMPLEMENT (long) COMPLEMENT (short) COMPLEMENT RS SSE RR RR RR LCTL LD LOR LE LER LOAD LOAD LOAD LOAD LOAD CONTROL (long) (long) (short) (short) RS RX RR RX RR (long) (long) (short) (short) Ii A SP P A A ESAj370 Principles of Operation R ST $ OP 0 ¢ GS IK R ST A 0 A 0 EO EO EO EO IK FK FK FK FK R ( ~ GS R A A G2 P Al R R R R $ P Al Q Al SO R R R R A C C C C A SP P Al SP AS SP SP P A SP A SP SP A SP SP 7-25 9-9 9-9 9-9 9-9 8-6 7-25 9-9 7-27 8-6 R 44 24 34 B231 B224 7-26 9-11 9-11 14-4 10-12 B2 43 B2 BF B20B B222 8221 7-27 7-27 10-12 7-28 10-14 B229 10-13 R2 8223 10-13 82 58 7-28 41 7-29 U1 BP 51 7-29 B1 IF B2 50 B2 60 20 B2 70 3D R ST B1 B2 OF 8-10 R B226 10-7 R U1 U2 B249 10-8 R 8227 10-8 R B24A 10-9 EX Q 7-15 7-19 14-4 7-23 7-24 ST B1 B2 FD 10 B22D U2 B24F R ST B1 B2 DE Gl ¢ 19 B2 BA B230 B2 4F B2 4E R Q Figure 8-2 (Part 2 of 6). Instructions Arranged by Mnemonic 8-10 Op Page Code No. Characteristics UB 9A E500 23 33 13 7-28 10-16 9-12 9-12 7-30 B2 B7 B2 68 28 B2 78 38 10-23 9-12 9-12 9-12 9-12 Mnemonic LH LM LNDR LNER LNR LOAD LOAD LOAD LOAD LOAD HALFWORD MULTIPLE NEGATIVE (long) NEGATIVE (short) NEGATIVE RX RS RR C RR C RR C LPDR LPER LPR LPSW LR LOAD LOAD LOAD LOAD LOAD POSITIVE (long) POSITIVE (short) POSITIVE PSW RR RR RR S RR LRA LRDR LRER LTDR LTER LOAD LOAD LOAD LOAD LOAD REAL ADDRESS ROUNDED (ext. to long) ROUNDED (long to short) AND TEST (long) AND TEST (short) LTR LURA M MC MD LOAD AND TEST LOAD USING REAL ADDRESS MULTIPLY MONITOR CALL MUL TIPLY (long) RR C RRE RX SI RX MDR ME MER MH MP MULTIPLY MULTIPLY MULTIPLY MULTIPLY MULTIPLY RR RX RR RX SS MR MSCH MSTA MVC MVCDK MULTIPLY MODIFY SUBCHANNEL MODIFY STACKED STATE MOVE (character) MOVE WITH DESTINATION KEY RR SP S C P A SP OP Al SP SE RRE SS A SSE MK Q A MVCIN MVCK MVCL MVCP MVCS MOVE MOVE MOVE MOVE MOVE INVERSE WITH KEY LONG TO PRIMARY TO SECONDARY SS SS RR SS SS MVCSK MVI MVN MVO MVZ MOVE MOVE MOVE MOVE MOVE WITH SOURCE KEY (immediate) NUMERICS WITH OFFSET ZONES SSE SI SS 55 55 MXD MXDR MXR N NC MULTIPLY (long to extended) MULTIPLY (long to extended) MULTIPLY (extended) AND AND (character) Figure (long) (short to long) (short to long) HALFWORD DECIMAL Op Page Code No. Characteristics Name B2 48 B2 98 21 31 11 7-3(:) 7-31 9-13 9-13 7-31 2(:) 3(:) 1(:) B2 82 18 9-13 9-13 7-31 1(:)-24 7-28 R BP B1 25 35 22 32 1(:)-25 9-14 9-14 9-12 9-12 R R R 12 B24B B2 5C AF B2 6C 7-3(:) 1(:)-27 7-38 7-32 9-14 R R A A SP SP R C C C L SP SP IF P A SP R ¢ R P Al RX C RR RR RR C RR C AT SP SP SP SP P Al SP A SP SP A SP EU EO SP A SP SP A A SP MI C C C C RX RR RR RX C SS C EO EO MO EU EO EU EO EU EO 2C B2 7C 3C R B2 4C ST B1 B2 FC 0 A QA A SP II SO QA SO QA MK Q A A A A A A SP EU EO SP EU EO SP EU EO A A R ¢ GS GM lC B2 B232 ST B247 ST B1 B2 02 ST B1 B2 E50F ST Bl B2 E8 ST Bl B2 09 R ST R1 R2 0E ST DA ST DB ¢ ¢ GM ST ST ST 5T ST Bl Bl Bl Bl Bl B2 E50E 92 B2 01 B2 Fl B2 03 B2 67 27 26 B2 54 R ST Bl B2 04 9-14 9-14 9-14 7-39 8-1(:) 7-38 14-6 1(:)':'27 7-32 10-30 7-33 10-31 7-33 10-29 10-29 10-32 7-32 7-37 7-37 7-38 9-14 9-14 9-14 7-9 7-9 8-2 (Part 3 of 6). Instructions Arranged by Mnemonic Appendix B. Lists of Instructions 8-11 Mnemonic NI NR Name 01 AND (immedi ate) AND OR OR (character) OR (immediate) SI RR RX SS SI OR PACK PALB PC PR OR PACK PURGE ALB PROGRAM CALL PROGRAM RETURN RR C SS RRE S E U PT PTLB RCHP RRBE RSCH PROGRAM TRANSFER RRE PURGE TLB S RESET CHANNEL PATH S C RESET REFERENCE BIT EXTENDED RRE C RESUME SUBCHANNEL S C S SAC SAL SAR SCHM SUBTRACT SET ADDRESS SPACE CONTROL SET ADDRESS LIMIT SET ACCESS SET CHANNEL MONITOR RX C S S RRE S SCK SCKC SD SDR SE SET CLOCK SET CLOCK COMPARATOR SUBTRACT NORMALIZED (long) SUBTRACT NORMALIZED (long) SUBTRACT NORMALIZED (short) S S RX RR RX C SER SH SIGP SL SLA SUBTRACT NORMALIZED (short) SUBTRACT HALFWORD SIGNAL PROCESSOR SUBTRACT LOGICAL SHIFT LEFT SINGLE RR RX RS RX RS C C C C C SLDA SLDL SLL SLR SP SHIFT LEFT DOUBLE SHIFT LEFT DOUBLE LOGICAL SHIFT LEFT SINGLE LOGICAL SUBTRACT LOGICAL SUBTRACT DECIMAL RS C RS RS RR C SS C SPKA SPM SPT SPX SR SET PSW KEY FROM ADDRESS SET PROGRAM MASK SET CPU TIMER SET PREFIX SUBTRACT S RR L S S RR C SRA SRDA SRDL SRL SRP SHIFT SHIFT SHIFT SHIFT SHIFT RS C RS C RS RS SS C 0 OC RIGHT SINGLE RIGHT DOUBLE RIGHT DOUBLE LOGICAL RIGHT SINGLE LOGICAL AND ROUND DECIMAL Op Page Code No. Characteristics C C C C C C C C A ST B1 R R A A A 94 14 B2 56 ST B1 B2 06 ST B1 96 R 16 ST B1 B2 F2 B248 $ Zl T ¢ GM B R ST B218 Z4 T ¢2 B R ST 0101 A P Q Al Al Q Al SP Z2 T ¢ P $ P P Al P B OP ¢ G1 OP ¢ GS A IF R P SP SW OP ¢ ¢ G1 P OP ¢ GM Q P A SP P A SP A SP EU EO SP EU EO A SP EU EO A P $ IF SP SP A 10-47 10-53 14-7 10-53 14-8 B2 5B B219 B237 Ul B24E B23C 7-48 10-54 14-10 7-41 14-10 B2 B204 10-55 B2 B206 10-56 B2 6B 9-16 2B 9-16 B2 7B 9-16 LS A IF R R R R 3B B2 4B AE B2 5F 8B R R R R 8F 8D 89 1F ST B1 B2 FB D DF Q P A SP P A SP $ IF A R R R R R SP SP 0 OF Figure B-2 (Part 4 of 6). Instructions Arranged by Mnemonic 8-12 ESAj370 Principles of Operation 7-40 7-40 10-52 10-34 10-44 B228 B20D B23B B22A B238 LS LS LS SP EU EO IF 7-9 7-9 7-40 7-40 7-40 ST Bl 9-16 7-48 10-61 7-48 7-43 7-42 7-42 7-43 7-48 8-12 B20A 04 B2 B208 B2 B210 1B 10-57 7-41 10-56 10-56 7-48 8A 8E 8C 88 F0 7-44 7-43 7-44 7-45 8-11 Mnemonic Name SSAR SSCH SSKE SSM ST SET SECONDARY ASN START SU8CHANNEL SET STORAGE KEY EXTENDED SET SYSTEM MASK STORE RRE S C RRE S RX Al Z3 T P A SP OP P Al P A SP SO A STAM STAP STC STCK STCKC STORE STORE STORE STORE STORE ACCESS MULTIPLE CPU ADDRESS CHARACTER CLOCK CLOCK COMPARATOR RS S RX S C S A SP P A SP A A P A SP STCM STCPS STCRW STCTL STD STORE STORE STORE STORE STORE CHARACTERS UNDER MASK CHANNEL PATH STATUS CHANNEL REPORT WORD CONTROL (long) RS S S C RS RX A PA PA PA A STE STH STIDP STM STNSM STORE STORE STORE STORE STORE (short) HALFWORD CPU ID MULTIPLE THEN AND SYSTEM MASK RX RX S RS SI STOSM STPT STPX STSCH STURA STORE STORE STORE STORE STORE THEN OR SYSTEM MASK CPU TIMER PREFIX SU8CHANNEL USING REAL ADDRESS SI S S S C RRE SU SUR SVC SW SWR SU8TRACT UNNORMALIZED SU8TRACT UNNORMALIZED SUPERVISOR CALL SU8TRACT UNNORMALIZED SU8TRACT UNNORMALIZED SXR TAR T8 TM TPI SU8TRACT NORMALIZED (ext.) TEST ACCESS TEST 8LOCK TEST UNDER MASK TEST PENDING INTERRUPTION RR RRE RRE SI S TPROT TR TRACE TRT TS TEST PROTECTION TRANSLATE TRACE TRANSLATE AND TEST TEST AND SET TSCH UNPK UPT X XC TEST SU8CHANNEL UNPACK UPDATE TREE EXCLUSIVE OR EXCLUSIVE OR (character) Figure Op Page Code No. Characteristics (short) RX C (short) RR C RR (long) RX C (long) RR C C C C C C ST 8225 82 8233 8228 82 80 82 50 10-58 14-12 10-61 10-61 7-45 ST ST ST ST ST U8 82 82 82 82 98 8212 42 8205 8207 7-45 10-63 7-45 7-46 10-63 ST ST ST ST ST 82 82 82 82 82 8E 823A 8239 86 60 7-46 14-14 14-14 10-63 9-16 A SP A P A SP A PA ST ST ST ST ST 81 82 82 82 82 70 40 8202 90 AC 9-16 7-47 10-64 7-47 10.;.65 PA PA PA PA P Al ST 81 AD 10-65 ST 82 8209 10-64 ST . 82 8211 10-65 ST 82 8234 14-15 SU 8246 10-66 ¢ ¢ ¢ GS $ SP SP SP SP ¢ ¢ SP SP SP SP OP SP ¢ A SP SP EO EO A SP SP . EO EO GS LS LS 82 7F 3F 0A 82 6F 2F ¢ LS LS 9-17 9-17 7-49 9-17 9-17. SP EU EO LS Al AS P A1 II $ G'0 A P A1 SP ¢ 37 824C R 822C 81 91 ST 82 8236 SSE C SS RS SS C S C P A1 A P A SP A A 81 E501 10-71 ST 81 82 DC 7-50 99 10-73 R 81 82 DD 7-51 ST 82 93 7-49 S C SS E C RX C SS C P A SP OP A A SP II A A T ¢ GM $ ¢ GS GM Ul ST 82 8235 ST 81 82 F3 R ST 14 0102 R 82 57 ST 81 82 D7 9-16 10-66 10-69 7-50 14-16 14-17 7-52 7-52 7-25 7-25 8-2 (Part 5 of 6). Instructions Arranged by Mnemonic Appendix 8. Lists of Instructions B-13 Mnemonic XI XR ZAP Figure 8-14 EXCLUSIVE OR (immediate) EXCLUSIVE OR ZERO AND ADD SI C RR C SS C ST B1 A R A 0 OF 8-2 (Part 6 of 6). Instructions Arranged by Mnemonic ESA/370 Principles of Operation Op Page Code No. Characteristics Name 97 17 ST B1 B2 F8 7-25 7-25 8-12 Op Code Name 0101. 0102 04 05 06 PROGRAM RETURN UPDATE TREE SET PROGRAM MASK BRANCH AND LI NK BRANCH ON COUNT 07 0A 0B 0C 00 BRANCH ON CONDITION BCR SUPERVISOR CALL SVC BRANCH AND SET MODE BSM BRANCH AND SAVE AND SET MODE BASSM BRANCH AND SAVE BASR RR RR RR RR RR 0E 0F 10 12 MOVE LONG COMPARE LOGICAL LONG LOAD POSITIVE LOAD NEGATIVE LOAD AND TEST MVCL CLCL LPR LNR LTR RR RR RR RR RR C C C C C 13 14 15 16 17 LOAD COMPLEMENT AND COMPARE LOGICAL OR EXCLUSIVE OR LCR NR CLR OR XR RR RR RR RR RR C C C C C 18 19 lA IB lC LOAD COMPARE ADD SUBTRACT MULTIPLY LR CR AR SR MR RR RR C RR C RR C RR 10 IE IF 20 21 DIVIDE ADD LOGICAL SUBTRACT LOGICAL LOAD POSITIVE (long) LOAD NEGATIVE (long) DR ALR SLR LPDR LNDR RR RR RR RR RR 22 23 24 25 26 LOAD AND TEST (long) LOAD COMPLEMENT (long) HALVE (long) LOAD ROUNDED (ext. to long) MULTIPLY (extended) LTDR LCDR HDR LRDR MXR 27 28 29 2A 2B MULTIPLY (long to extended) LOAD (long) COMPARE (long) ADD NORMALIZED (long) SUBTRACT NORMALIZED (long) 2C 20 2E 2F 30 MULTIPLY (long) DIVIDE (long) ADD UNNORMALIZED (long) SUBTRACT UNNORMALIZED (long) LOAD POSITIVE (short) 11 Figure Mnemonic PR UPT SPM BALR BCTR Page No. Characteristics E U E C RR L RR RR Al Z4 T ¢2 B R ST A SP II GM R ST 14 T BR BR ¢l ¢ B BR BR BR T T A SP A SP 10-44 7-52 7-41 7-10 7-13 7-12 7-49 7-12 7-11 7-11 IF R ST Rl R2 7-33 R Rl R2 7-22 R 7-31 R 7-31 R 7-30 IF R R II II R R R IF IF R R R SP SP IK R R R 7-30 7-9 7-21 7-40 7-25 7-28 7-15 7-8 7-48 7-38 SP SP 7-25 7-9 7-48 9-13 9-13 RR C RR C RR RR RR SP SP SP EU SP EO SP EU EO 9-12 9-12 9-11 9-14 9-14 MXDR LOR CDR ADR SDR RR RR RR C RR C RR C SP EU EO SP SP SP EU EO SP EU EO· LS LS 9-14 9-12 9-9 9-7 9-16 MDR DDR AWR SWR LPER RR RR RR C RR C RR C SP EU EO SP EU EO FK SP EO LS SP EO LS SP 9-14 9-9 9-8 9-17 9-13 C C C C B-3 (Part 1 of 6). Instructions Arranged by Operation Code Appendix B. Lists of Instructions B-15 Op Code Name Mnemonic 31 32 33 34 35 LOAD NEGATIVE (short) LOAD AND TEST (short) LOAD COMPLEMENT (short) HALVE (short) LOAD ROUNDED (long to short) LNER LTER LCER HER LRER RR C RR C RR C RR RR SP SP SP SP EU SP EO 36 37 38 39 3A ADD NORMALIZED (extended) SUBTRACT NORMALIZED (ext.) LOAD (short) COMPARE (short) ADD NORMALIZED (short) AXR SXR LER CER AER RR RR RR RR RR SP EU EO SP EU EO SP SP SP EU EO 3B 3C 3D 3E 3F SUBTRACT NORMALIZED (short) MULTIPLY (short to long) DIVIDE (short) ADD UNNORMALIZED (short) SUBTRACT UNNORMALIZED (short) SER MER DER AUR SUR RR C RR RR RR C RR C 40 41 42 43 44 STORE HALFWORD LOAD ADDRESS STORE CHARACTER INSERT CHARACTER EXECUTE STH LA STC IC EX RX RX RX RX RX 45 46 47 48 49 BRANCH AND LINK BRANCH ON COUNT BRANCH ON CONDITION LOAD HALFWORD COMPARE HALFWORD BAL BCT BC LH CH RX RX RX RX RX C 4A 4B 4C 40 4E ADD HALFWORD SUBTRACT HALFWORD MULTIPLY HALFWORD BRANCH AND SAVE CONVERT TO DECIMAL AH SH MH BAS CVD RX C RX C RX RX RX 4F 50 51 54 55 CONVERT TO BINARY STORE LOAD ADDRESS EXTENDED AND COMPARE LOGICAL CVB ST LAE N CL RX RX RX RX C RX C A A 56 57 58 59 5A OR EXCLUSIVE OR LOAD COMPARE ADD 0 X L' C A RX RX RX RX RX A A A A A 5B 5C 50 5E 5F SUBTRACT MUL TIPLY DIVIDE ADD LOGICAL SUBTRACT LOGICAL S M 0 AL SL RX C RX RX RX C RX C Page No. Characteristics C XP C C C 9-13 9-12 9-12 9-11 9-14 LS LS LS 9-7 9-16 9-12 9-9 9-7 SP EU EO LS SP EU EO SP EU EO FK SP EO LS SP LS EO 9-16 9-14 9-9 9-8 9-17 A ST R A A AI SP C C C C ST R EX A A A A A IF IF BR BR B R 7-10 7-13 7-12 B2 7-30 B2 7-20 R R R BR B2 7-8 B2 7-48 B2 7-39 7-11 B2 7-24 A A A ST 0 A A SP A SP A A Figure 8-3 (Part 2 of 6). Instructions Arranged by Operation Code 8-16 ESA/370 Principles of Operation IK B2 7-47 7-29 B2 7-45 B2 7-27 7-26 R ST. R R R R R B2 B2 Ul BP B2 B2 7-23 7-45 7-29 7-9 7-21 7-40 7-25 7-28 7-15 7-8 7-48 7-38 7-25 7-9 7-48 IF R B2 B2 B2 B2 B2 IF R R R R R B2 B2 B2 B2 B2 IK Op Code Name Mnemonic 60 67 68 69 6A STORE (long) MULTIPLY (long to extended) LOAD (long) COMPARE (long) ADD NORMALIZED (long) STD MXD LD CD AD RX RX RX RX C RX C A A A A A SP SP EU EO SP SP SP EU EO 6B 6C 60 6E 6F SUBTRACT NORMALIZED (long) MUL TIPLY (long) DIVIDE (long) ADD UNNORMALIZED (long) SUBTRACT UNNORMALIZED (long) SO MD DO AW SW RX C RX RX RX C RX C A A A A A 70 78 79 7A 7B STORE (short) LOAD (short) COMPARE (short) ADD NORMALIZED (short) SUBTRACT NORMALIZED (short) STE LE CE AE SE RX RX RX C RX C RX C A SP A SP A SP A SP EU EO A SP EU EO 7C 7D 7E 7F 80 MULTIPLY (short to long) DIVIDE (short) ADD UNNORMALIZED (short) SUBTRACT UNNORMALIZED (short) SET SYSTEM MASK ME DE AU SU SSM RX RX RX C RX C S 82 83 86 87 88 LOAD PSW DIAGNOSE BRANCH ON INDEX HIGH BRANCH ON INDEX LOW OR EQUAL SHIFT RIGHT SINGLE LOGICAL LPSW S BXH RS BXLE RS SRL RS 89 8A 8B 8C 8D SHIFT SHIFT SHIFT SHIFT SHIFT SLL SRA SLA SRDL SLDL RS RS C RS C RS RS 8E 8F 90 91 92 SHIFT RIGHT DOUBLE SHIFT LEFT DOUBLE STORE MULTIPLE TEST UNDER MASK MOVE (immediate) SRDA SLDA STM TM MVI RS C RS C RS SI C SI A A A 93 94 95 96 97 TEST AND SET AND (immediate) COMPARE LOGICAL (immediate) OR (immediate) EXCLUSIVE OR (immediate) TS NI CLI XI S SI SI SI SI A A A A A 98 99 9A 9B AC LOAD MULTIPLE TRACE LOAD ACCESS MULTIPLE STORE ACCESS MULTIPLE STORE THEN AND SYSTEM MASK LM TRACE LAM STAM STNSM RS RS RS RS SI Figure LEFT SINGLE LOGICAL RIGHT SINGLE LEFT SINGLE RIGHT DOUBLE LOGICAL LEFT DOUBLE LOGICAL 01 Page No. Characteristics L DM A A A A PA ST LS B2 B2 B2 B2 B2 9-16 9-14 9-12 9-9 9-7 SP EU EO LS SP EU EO SP EU EO FK LS SP EO SP LS EO B2 B2 B2 B2 B2 9-16 9-14 9-9 9-8· 9-17 LS LS B2 B2 B2 B2 B2 9-16 9-12 9-9 9-7 9-16 SP EU EO SP EU EO FK SP EO LS SP LS EO SP SO B2 B2 B2 B2 B2 9-14 9-9 9-8 9-17 10-61 P A SP P DM ST ¢ BR BR R C C C C C IF R R R R R 7-43 7-44 7-43 7-44 7-42 IF R R 7-43 7-42 ST B2 7-47 B1 7-50 ST B1 7-32 SP SP SP SP A P A SP A SP A SP PA B2 10-24 MD 10-7 7-14 7-14 7-45 ST B2 7-49 ST B1 7-9 B1 7-21 ST B1 7-40 ST B1 7-25 $ R T ¢ B2 7-31 10-73 UB 7-28 ST UB 7-45 ST B1 10-65 8-3 (Part 3 of 6). Instructions Arranged by Operation Code Appendix B. Lists of Instructions B-17 Op Code Name Mnemonic Page No. Characteristics AD AE AF B1 B202 STORE THEN OR SYSTEM MASK SIGNAL PROCESSOR MONITOR CALL LOAD REAL ADDRESS STORE CPU 10 STOSM SIGP MC LRA STIDP SI RS C SI RX C S P A SP P SP P A1 AT P A SP B204 B205 B206 B207 B208 SET CLOCK STORE CLOCK SET CLOCK COMPARATOR STORE CLOCK COMPARATOR SET CPU TIMER SCK STCK SCKC STCKC SPT S S S S S C C PA A PA PA PA B209 820A B20B 8200 8210 STORE CPU TIMER SET PSW KEY FROM ADDRESS INSERT PSW KEY PURGE TL8 SET PREFIX STPT SPKA IPK PTLB SPX S S S S S . B211 8212 8218 8219 821A STORE PREFIX STORE CPU ADDRESS PROGRAM CALL SET ADDRESS SPACE CONTROL COMPARE AND FORM CODEWORD STPX STAP PC SAC CFC S S S S S 8221 8222 8223 8224 8225 INVALIDATE PAGE TABLE ENTRY INSERT PROGRAM MASK INSERT VIRTUAL STORAGE KEY INSERT ADDRESS SPACE CONTROL SET SECONDARY ASN IPTE IPM IVSK lAC SSAR RRE RRE RRE RRE C RRE 8226 8227 8228 B229 B22A EXTRACT PRIMARY ASN EXTRACT SECONDARY ASN PROGRAM TRANSFER INSERT STORAGE KEY EXTENDED RESET REFERENCE BIT EXTENDED EPAR ESAR PT ISKE RRBE 822B 822C B22D B230 B231 SET STORAGE KEY EXTENDED TEST BLOCK DIVIDE (extended) CLEAR SUBCHANNEL HALT SUBCHANNEL 8232 8233 8234 8235 8236 8237 8238 B239 823A 823B MO R ST SP ST $ B2 B2 B2 B2 B2 10-55 7-46 10-56 10-63 10-56 ST P A SP ST B2 10-64 10-57 10-12 10-53 B2 10-56 ST ST GM B R ST B2 10-65 B2 10-63 10-34 10-54 11 7-15 Q Q G2 R $ $ P A SP P A SP Q A1 Z1 T Q SP SW A SP II P A1 ¢ ¢ GM R 10-14 7-28 R2 10-13 10-12 10-58 $ Q A1 Q R R R A1 SO SO Z3 T RRE RRE RRE RRE RRE C Q Q Q A1 SO SO SP Z2 T SSKE TB DXR CSCH HSCH RRE RRE C RRE S C S C P A1 P A1 P P SP EU EO FK OP ¢ GS ¢ GS OP MODIFY SU8CHANNEL START SUBCHANNEL STORE SUBCHANNEL TEST SU8CHANNEL TEST PENDING INTERRUPTION MSCH SSCH STSCH TSCH TPI S S S S S C C C C C PA PA PA PA P A1 SP SP SP SP SP SET ADDRESS LIMIT RESUME SU8CHANNEL STORE CHANNEL REPORT WORD STORE CHANNEL PATH STATUS RESET CHANNEL PATH SAL RSCH STCRW STCPS RCHP S S S S S C C C 10-65 10-61 7-32 BP 10-25 B2 10-64 SP SP SP P P A SP C ST B1 R $ ¢ R R 10-7 10-8 10-47 10-13 10-53 B ¢ P A1 P A1 10-61 10-69 9-9 14-4 14-4 ¢ II $ G0 OP OP OP OP ¢ ¢ ¢ ¢ ¢ GS GS GS GS OP P OP P P A SP P A SP OP P ¢ ¢ ¢ ¢ ¢ G1 GS Figure B-3 (Part 4 of 6). Instructions Arranged by Operation Code B-18 ESA/370 Principles of Operation R ST ST ST ST ST G1 82 82 82 B2 82 14-6 14-12 14-15 14-17 14-16 14-10 14-8 B2 14-14 82 14-14 14-7 Op Code Name Mnemonic Page No. Characteristics B23C B240 B246 B247 B248 SET CHANNEL MONITOR BRANCH AND STACK STORE USING REAL ADDRESS MODIFY STACKED STATE PURGE ALB SCHM BAKR STURA MSTA PALB S RRE RRE RRE RRE ¢ GM OP Al SF T B ST P Al SP SU Al SP SE ST P $ B249 B24A B24B B24C B24D EXTRACT STACKED REGISTERS EXTRACT STACKED STATE LOAD USING REAL ADDRESS TEST ACCESS COPY ACCESS EREG ESTA LURA TAR CPYA RRE RRE C RRE RRE C RRE Al SE Al SP SE P Al SP Al AS B24E B24F B6 B7 BA SET ACCESS EXTRACT ACCESS STORE CONTROL LOAD CONTROL COMPARE AND SWAP SAR EAR STCTL LCTL CS RRE RRE RS RS RS C P A SP P A SP A SP BB BD BE BF D1 COMPARE DOUBLE AND SWAP COMPARE LOGICAL C. UNDER MASK STORE CHARACTERS UNDER MASK INSERT CHARACTERS UNDER MASK MOVE NUMERICS CDS CLM STCM ICM MVN RS C RS C RS RS C SS A SP A A A A D2 D3 D4 D5 D6 MOVE (character) MOVE ZONES AND (character) COMPARE LOGICAL (character) OR (character) MVC MVZ NC CLC OC SS SS SS C SS C SS C A A A A A D7 D9 DA DB DC EXCLUSIVE OR (character) MOVE WITH KEY MOVE TO PRIMARY MOVE TO SECONDARY TRANSLATE XC MVCK MVCP MVCS TR SS SS SS SS SS C C C C A QA QA QA A DD DE DF E500 E501 TRANSLATE AND TEST TRT EDIT ED EDIT AND MARK EOMK LOAD ADDRESS SPACE PARAMETERS LASP TEST PROTECTION TPROT SS SS SS SSE SSE C C C C C A A 0 A 0 P Al SP AS P Al E50E E50F E8 F0 F1 MOVE WITH SOURCE KEY MOVE WITH DESTINATION KEY MOVE INVERSE SHIFT AND ROUND DECIMAL MOVE WITH OFFSET MVCSK MVCOK MVCIN SRP MVO SSE MK Q A SSE MK Q A SS MI A SS C A SS A F2 F3 Fa F9 FA PACK UNPACK ZERO AND ADD COMPARE DECIMAL ADD DECIMAL PACK UNPK ZAP CP AP SS SS SS C SS C SS C Figure P 14-10 10-5 10-66 10-27 10-52 Ul U2 10-8 10-9 10-27 Ul 10-66 Ul U2 7-24 R R R Ul R A A A A A U2 B2 B2 B2 ST $ R ST $ R ST B2 B2 ST B2 B2 R ST Bl B2 7-41 7-27 10-63 10-23 7-19 7-19 7-21 7-46 7-27 7-37 ST Bl B2 7-32 ST B1 B2 7-38 ST B1 B2 7-9 B1 B2 7-21 ST B1 B2 7-40 SO SO ST B1 B2 7-25 ST B1 B2 10-31 ST 10-29 ST 10-29 ST BI B2 7-50 ¢ ¢ GM G1 GM GM 0 0 0 0 DF OF OF R B1 B2 ST B1 B2 R ST B1 B2 B1 B1 ST ST ST ST ST B1 B1 B1 B1 B1 7-51 8-6 8-10 10-16 10-71 B2 10-32 B2 10-30 B2 7-33 8-11 B2 7-37 ST B1 B2 7-40 ST B1 B2 7-52 ST B1 B2 8-12 B1 B2 8-5 ST B1 B2 8-5 8-3 (Part 5 of 6). Instructions Arranged by Operation Code Appendix B. Lists of Instructions B-19 Op Code FB FC FD Name SUBTRACT DECIMAL MULTIPLY DECIMAL DIVIDE DECIMAL Mnemonic SP MP DP Characteristics SS C SS SS 0 OF A A SP 0 A SP 0 OK Figure B-3 (Part 6 of 6). Instructions Arranged by Operation Code B·20 ESA/370 Principles of Operation Page No. ST B1 B2 8-12 ST B1 B2 8-10 ST B1 B2 8-6 Appendix C. Condition-Code Settings This appendix lists the condition-code setting for instructions in 370-XA which set the condition code. In addition to those instructions listed which set the condition code, the condition code is set unpredictably by PROGRAM RETURN, and it may be changed by DIAGNOSE and the target of EXECUTE. The condition code is loaded by LOAD psw, by SET PROGRAM MASK, and by an interruption. The condition code is set to zero by initial CPU reset and is loaded by the successful conclusion of the initial-program-Ioading sequence. The condition codes for the vector facility are· not included in this appendix. See the publication Enterprise Systems Architecture/370 and System/370 Vector Operations, SA22-7125, for the condition codes set by vector instructions. Some models may offer instructions which set the condition code and do not appear in this document, such as those provided for assists or as part of special or custom features. Condition Code Instruction ADD, ADD HALFWORD ADD DECIMAL ADD LOGICAL 0 ( ADD NORMALIZED ADD UNNORMALIZED AND CLEAR SUBCHANNEL Zero Zero Zero, no carry Zero Zero 1 2 3 zero zero Not zero, no carry < zero < zero > > zero zero Zero, carry > zero > zero Overflow Overflow Not zero, carry Not zero -- -- High High OCB=0: high OCB=l : low -- -- -- High < < -- -- COMPARE (gent f1 pt) COMPARE HALFWORD COMPARE AND FORM CODEWORD Zero Function initiated Equal Equal Equal COMPARE AND SWAP Equal Low Low OCB=0: low OCB=l: high Not equal COMPARE COMPARE COMPARE COMPARE UNDER COMPARE Equal Equal Equal Equal Low Not equal Low Low -- High High --- Equal Low High -- Zero Zero Branch state entry Function initiated < zero Not zero Program-call state entry Status-pending with other than intermediate status Secondary-space mode Fi rst bi tone > DECIMAL DOUBLE AND SWAP LOGICAL LOGICAL CHARACTERS MASK LOGICAL LONG EDIT, EDIT AND MARK EXCLUSIVE OR EXTRACT STACKED STATE HALT SUBCHANNEL INSERT ADDRESS SPACE CONTROL Primary-space mode INSERT CHARACTERS UNDER MASK All zeros Figure -- -- -.-- Not operational zero Busy -- -- --- ---Not operational Access-register Home-space mode mode First bit zero -- C-l (Part 1 of 3). Summary of Condition-Code Settings Appendix C. Condition-Code Settings C-l Condition Code e Instruction LOAD ADDRESS SPACE PARAMETERS Parameters loaded LOAD LOAD LOAD LOAD Zero Zero Zero Zero AND TEST (gen, fl pt) COMPLEMENT (gen) COMPLEMENT (fl pt) NEGATIVE (gen, fl pt) 2 1 Primary ASN Secondary ASN Space-switch not available not available event or not authorized < zero > zero -< zero > zero Overflow < zero > zero -< zero --- --- zero zero PT entry invalid LOAD POSITIVE (gen) LOAD POSITIVE (fl pt) LOAD REAL ADDRESS Zero Zero Translation available MODIFY SUBCHANNEL SCHIB informa- Status-pending Busy tion placed in subchannel Length high Length equal Length low MOVE LONG MOVE TO PRIMARY, MOVE TO SECONDARY MOVE WITH KEY OR Figure C-2 Overflow -- ST designation not available or length violation Not operational Destructive overlap =< 256 -- -- Length > 256 Length Zero =< 256 --Not zero --- Length > 256 -- Busy Not operational Function initiated RESET REFERENCE BIT R bit zero, C bit zero EXTENDED RESUME SUBCHANNEL Function initiated Set SET CLOCK SHIFT AND ROUND DECIMAL Zero SHIFT LEFT (DOUBLE/SINGLE) Zero SHIFT RIGHT (DOUBLE/SINGLE) Zero STORE CHANNEL REPORT WORD STORE CLOCK STORESUBCHANNEL ST entry invalid > > Length RESET CHANNEL PATH SIGNAL PROCESSOR START SUBCHANNEL 3 Order accepted Function initiated CRW stored Set SCHIB stored R bit zero, R bit one, C bit one C bit zero Status pending Function not applicable Secure -> zero < zero < zero > zero < zero > zero Status stored Busy Status-pending Busy Zeros stored Not set -- C-l (Part 2 of 3). Summary of Condition-Code Settings ESAj370 Principles of Operation -- Error -- -- R bit one, C bit one Not operational Not operational Overflow Overflow -Not operational Not operational -- Not operational Not operational Condition Code Instruction e SUBTRACT, SUBTRACT HALFWORD Zero SUBTRACT DECIMAL Zero SUBTRACT LOGICAL -- SUBTRACT NORMALIZED SUBTRACT UNNORMALIZED Zero Zero TEST ACCESS ALET e TEST AND SET TEST BLOCK TEST PENDING INTERRUPTION Left bit zero Usable Interruption code not stored Can fetch, can store IRB stored; subchannel statuspending TEST PROTECTION TEST SUBCHANNEL 2 1 zero zero Not zero, no carry < zero < zero < < zero zero Zero, carry > zero > zero > > 3 Overflow Overflow Not zero, carry --- DU access list, PS access list, ALET 1 or no exceptions no exceptions exceptions Left bit one -, -Not usable --Interruption --code stored Can fetch, Cannot fetch, Translation not cannot store cannot store avail abl e IRB stored; Not operational -subchannel not statuspending TEST UNDER MASK TRANSLATE AND TEST UPDATE TREE All zeros All zeros Equal Mixed -Complete Incomplete Not equal or -no comparison ZERO AND ADD Zero < zero > zero All ones -- Method 2, GR5 nonzero, GRe negative Overflow Explanation: zero zero 256 256 High Low length OCB > < =< > Result greater than zero Result less than zero Equal to, or less than, 256 Greater than 256 First operand high First operand low Length of first operand Operand-control bit Figure C-l (Part 3 of 3). Summary of Condition-Code Settings Appendix C. Condition-Code Settings C-3 Appendix D. Comparison Between 370-XA and ESA/370 New Facilities in ESA/370 . . . . .. Access Registers . . . . . . . . . .. Home Address Space . Linkage Stack . . . . . . . . . . . . . . Load and Store Using Real Address Move with Source or Destination Key Private Space . . . . . Comparison of Facilities . . . . . . Summary of Changes . . . . . . . New Instructions Provided ... Comparison of PSW Formats . . . . . . New Control-Register Assignments ... New Assigned Storage Locations New Exceptions . . . . . . . . . . Change to Secondary-Space Mode '0 • • • • •• D-l D-l D-l D-l D-2 D-2 D-2 D-2 D-2 D-2 D-3 D-3 D-3 D-3 D-4 This appendix provides (1) a list of the facilities that are new in ESA/370 and not provided in 370-XA, (2) a description of the handling in ESA/370 of the facilities available in 370-XA, (3) a list of changes between 370-XA and ESA/370, and (4) a list of how 370-XA facilities are affected by the new translation modes in ESA/370. New Facilities in ESA/370 The .following facilities are new in ESA/370 and are not provided in 370-XA. Access registers, home address space, linkage stack, and load and store using real address are provided by all ESA/370 models. Move with source or destination key and private space are provided by some ESA/370 models. Access Registers Sixteen access registers and a translation mode named the access-register mode allow designation of storage operands in up to sixteen different address spaces by means of the B fields of instructions and the R fields of certain instructions. The dispatchable-unit and primary-space access lists contain the addressing capabilities that are usable by means of the access registers. The use of an access-list entry is controlled by the extended authorization index in control register 8. Changes to ASN-Second-Table Entry and ASN Translation . . . . . . . . . . Changes to Entry-Table Entry and PC-Number Translation . . . . . Changes to PROGRAM CALL . . Changes to SET ADDRESS SPACE CONTROL . . . . . . . . . . . . . Effects in New Translation Modes Effects on Interlocks for Virtual-Storage References . . . . . . . . . . . . . . . . Effect on INSERT ADDRESS SPACE CONTROL . . . . . . . . . . . . . Effect on LOAD REAL ADDRESS Effect on TEST PENDING INTERRUPTION . . . . . . . . Effect on TEST PROTECTION D-4 D-4 D-4 D-4 D-4 D-5 D-5 D-5 D-5 D-5 Instructions are provided for exammmg and changing the contents of the access registers and for purging the access-register-translation-Iookaside buffer. Home Address Space A translation mode named the home-space mode allows the control program to quickly gain control in and access the home address space, which is where the control program keeps the principal control blocks for a dispatchable unit. The spaceswitch event can indicate a transfer of control to or from the home address space. Linkage Stack A bit in the entry-table entry controls whether PROGRAM CALL performs the 370-XA, or basic, operation or the stacking operation. The stacking operation allows increased status changing, and it saves status in a linkage-stack state entry, from which status is restored by the PROGRAM RETURN instruction. The linkage stack can also be used in a branch-type linkage. Instructions are provided for examining and changing the contents of the last state entry and for testing the contents of an access register by means of a specified- extended authorization index. Appendix D. Comparison Between 370-XA and ESAj370 D-l Load and Store Using Real Address Summary of Changes Instructions are provided for loading and storing from a general register through the use of a real address. The storing operation can be indicated by a store-using-real-address PER event. This section summarizes the changes between 370-XA and BSA/370. Most of these changes are simply additions in BSA/370 beyond 370-XA or apply only when the BSA/370 address-space-function (ASF) control, bit 15 of control register 0, is one. Some of the changes apply regardless of the value of the ASF control. Move with Source or Destination Key Instructions are provided for moving data with a specified access key that applies to the references to either the source or the destination storage area; the psw key applies to the references to the other storage area. A bit in the segment-table designation can be set to one to prevent the use of translation-lookasidebuffer entries for common segments and to prevent the application of low-address protection and fetchprotection override to the specified address space. Comparison of Facilities Figure D-l shows the facilities offered in and how each facility is provided in BSA/370. 370-XA Facility 370-XA Avail abil i ty in ESA/370 B1 ES MI Basic 370-XA facilities Expanded storage Move inverse Vector V Explanation: B ES MI V D·2 D-1. Availability ESA/370 Instruction Name Mne- Op Availamonic Code bil ity BRANCH AND STACK COPY ACCESS EXTRACT ACCESS EXTRACT STACKED REGISTERS EXTRACT STACKED STATE BAKR CPYA EAR EREG ESTA B24a B24D B24F B249 B24A B1 B B B1 B1 LOAD ACCESS MULTIPLE LOAD ADDRESS EXTENDED LOAD USING REAL ADDRESS MODIFY STACKED STATE MOVE WITH DESTINATION KEY LAM LAE LURA MSTA MVCDK 9A 51 B24B B247 E5aF B B B B1 MK MOVE WITH SOURCE KEY PROGRAM RETURN PURGE ALB SET ACCESS STORE ACCESS MULTIPLE MVCSK PR PALB SAR STAM E5aE alaI B248 B24E 9B MK B1 B STORE USING REAL ADDRESS TEST ACCESS STURA B246 TAR B24C B B1 B B Explanation: Compatibility for privileged programs is not provided when the address-spacefunction control, bit 15 of control register 0, is one. Basic in ESA/370 mode. Provided in both 370-XA and ESA/370 as the expanded-storage facility. Provided in both 370-XA and ESA/370 as the move-inverse facility. Provided in both 370-XA and ESA/370 as the vector facility. Figure Figure D-2 shows those instructions which are basic or optional in BSA/370 but not provided in 370-XA. All 370-XA instructions are provided in BSA/370. Private Space 1 New Instructions Provided of 370-XA ESA/370 Principles of Operation Facilities in 1 B MK Figure Instruction can be executed successfully only when the address-space-function control, bit 15 of control register a, is one. Instruction is basic. Move-wi th-source-or-desti nati on-key facil ity. D-2. New Instructions Provided In 370-XA, psw bit 16 is the address-space control, and a one in bit position 17 of the psw is invalid. In BSA/370, psw bits 16 and 17 are the addressspace control. is zero, control register 5 contains the linkage-table designation. In FSA/370 when the ASF control is one, control register 5 contains the primary ASN-second-table-entry origin, and the linkage-table designation is in the primary ASN -second-table entry. New Control-Register Assignments New Assigned Storage Locations Figure 0-3 shows those assignments of controlregister bits and fields that are new in FSA/370 compared to 370-XA. Figure 0-4 shows those storage locations that are assigned in ESA/370 and not assigned in 370-XA. Comparison of PSW Formats Ctrl Reg Bits Name of Bit or Field Name of Field 0 15 Address-space-function control 1 1 0 23 Primary space-switch-event control 1 Primary private-space control 2 1-25 Dispatchable-unit-control-table origin 5 1-25 Primary-ASN-second-table-entry origin 2 7 23 8 0-15 Extended authorization index 9 4 Exception access identification PER access identification Machine-check access-register save area Store-status access-register save area 15 2 Figure A 288 64 * The first number is the address, the second the length. A Absolute location. R Real location. Secondary private-space control Store-using-real-address-event mask Home Home Home Home space-switch-event control segment-table origin private-space control segment-table length D-4. New Assigned Storage Locations Bit 33 of the machine-check-interruption code, the access-register-validity bit, is assigned in FSA/370 and not assigned in 370-XA. 1-28 Linkage-stack-entry address Explanation: 1 R 160 1 R 161 1 R 288 64 Explanation: Figure 0 13 1-19 13 23 13 25-31 13 Assigned Storage Location and Length* Only the name of this bit is new. The bit has the same position and function as the space-switch-event control of 370-XA. This assignment applies only if bit 15 of control register 0 is one. If bit 15 is zero, control register 5 contains the linkage-table designation as in 370-XA. In both 370-XA and FSA/370, the translationexception identification is stored at real locations 144-147 during a program interruption due to a segment-translation or page-translation exception. In 370-XA, bits 20-31 of this translation-exception identification are unpredictable. In ESA/370, bits 20-29 are unpredictable, and bits 30-31 are set to identify the type of virtual address that caused the exception. New Exceptions D-3. New Control-Register Assignments In 370-XA, and in FSA/370 when the address-spacefunction (ASF) control, bit 15 of control register 0, Figure 0-5 on page 0-4 shows those new exceptions that may be recognized in ESA/370 and are not recognized in 370-XA. APPetldix D. Comparison Between 370-XA and ESA/370 D-3 J Exception Name ALET specification l ALEN translation l ALE sequence l ASTE validityl ASTE sequence l Extended authorityl Stack fu11 2 Stack empty2 Stack specification 2 Stack type 2 Stack operation 2 Interruption Code (hex) e028 e029 e02A e028 e02C e020 e03e e031 e032 e033 e034 Explanation: May be recognized during access-register translation. 2 May be recognized during linkage-stack operations. 1 Figure D-5. New Exceptions Change to Secondary-Space Mode Changes to Entry-Table Entry and PC-Number Translation In 370-XA, and in FSA/370 when the address-spacefunction (ASF) control, bit 15 of control register 0 is zero, the entry-table entry has a length of 16 bytes. In FSA/370 when the ASF control is one, the entrytable entry has a length of 32 bytes. pc-number translation is affected by this change and also by the change to the location of the linkage-table designation described in "New Control Register Assignments" in this appendix. Changes to PROGRAM CALL In 370-XA, and in FSA/370 when the address-spacefunction (ASF) control, bit 15 of control register 0 is zero, a space-switching PROGRAM CALL obtains the address of the ASN-second-table entry for the new primary address space by means of ASN translation. In FSA/370 when the ASF control is one, PROGRAM CALL obtains the address of the ASN-second-table entry either by means of ASN translation or directly from the entry-table entry, and which of these occurs is unpredictable. In 370-XA in the secondary-space mode, it is unpredictable whether instructions are fetched from the primary address space or the secondary address space. In FSA/370 in the secondary-space mode, instructions are fetched from the primary address space. In 370-XA, and in FSA/370 when the ASF control is zero, PROGRAM CALL performs the 370-XA operation, called the basic operation. In FSA/370 when the ASF control is one and the pc-type bit, bit 128 of the 32-byte entry-table entry, is one, PROGRAM CALL performs a different operation, called the stacking operation. Changes to ASN-Second-Table Entry and ASN Translation Changes to SET ADDRESS SPACE CONTROL In 370-XA, and in FSA/370 when the address-spacefunction (ASF) control, bit 15 of control register 0 is zero, the ASN-second-table entry has a length of 16 bytes and is aligned on a 16-byte boundary. In FSA/370 when the ASF control is one, the ASN-second-table entry has a length of 64 bytes and is aligned on a 64-byte boundary. ASN translation is affected by this change. In 370-XA, for SET ADDRFSS SPACE CONTROL, bit 22 of the second-operand address must be zero; otherwise, a specification exception is recognized. In FSA/370, bit 22 may be one in order to specify the setting of either the access-register mode or the home-space mode, depending on bit 23. Effects in New Translation Modes FSA/370 has two new translation modes named the access-register mode and the home-space mode. These modes result when DAT is on and psw bits 16 and 17 are 01 or 11 binary, respectively. This section summarizes the effects of the new translation modes on operations that would otherwise D-4 ESA/370 Principles of Operation be the same as in 370-XA. For ADDRESS, the effect applies whether off. LOAD REAL DAT is on or Effects on Interlocks for Virtual-Storage References In 370-XA and ESA/370, in the real mode, primaryspace mode, or secondary-space .mode, when a store is made to a location from which a succeeding instruction is fetched and the same effective address is used for both the store and the fetch, the results of the store appear to be completed before the fetch. Thus, it is possible for an instruction to modify the next succeeding instruction in storage. In ESA/370, in the access-register mode or homespace mode, an instruction that is a store-type operand of a preceding instruction may appear to be fetched before the store occurs. Thus, it is not assured that an instruction can modify the succeeding instruction. In 370-XA and ESA/370, for those instructions which alter the contents of storage and have more than one operand, the instruction defmition normally describes the results that are obtained when the operands overlap in storage. In 370-XA, and in ESA/370 in other than the access-register mode, operand overlap is recognized if the effective addresses of the two operands are the same. In ESA/370, in the access-register mode, recognition of operand overlap additionally requires that the effective space designations of the two operands be the same. The effective space designation for an operand is the contents of the access register used to access the operand, except that, if access register ois used, the contents are treated as being all zeros. Effect on INSERT ADDRESS SPACE CONTROL Effect on LOAD REAL ADDRESS In 370-XA, when LOAD REAL ADDRESS sets any of condition codes 1-3, indicating an exception situation, it places an address related to the situation in general register R 1, and it sets bit 0 of the register to zero. Condition code 3 indicates that the segmenttable or page-table length is exceeded. In ESA/370, when psw bits 16 and 17 are 01 binary, condition code 3 may alternatively indicate an· exception situation encountered during access-register translation, in which case the interruption code assigned to the exception is placed in general register R 1, and bit 0 of the register is set to one. Effect on TEST PENDING INTERRUPTION In 370-XA and ESA/370, a zero second-operand address of TEST PENDING INTERRUPTION specifies a store at real locations 184-191. In this case, in ESA/370 in the access-register mode, it is unpredictable whether access-register translation occurs for the access register designated by the B 2 field. If access-register translation occurs and the access register is in error, an exception is recognized. If the translation occurs and there is no exception, the resulting segment-table designation is not used; that is, the store still occurs at reallocations 184-191. Effect on TEST PROTECTION In 370-XA, TEST PROTECTION sets condition code 3 if it encounters an exception situation during dynamic address translation. In ESA/370 in the access-register mode, TEST PROTECTION may alternatively set condition code 3 because of an exception situation encountered during access-register translation. In 370-XA, INSERT ADDRESS SPACE CONTROL sets bit 22 of general register R 1 to zero, and it sets the condition code to 0 or 1. In ESA/370, because of the new translation modes, INSERT ADDRESS SPACE CONTROL may set bit 22 to one, and it may set the condition code to 2 or 3. Appendix D. Comparison Between 370-XA and ESAj370 D-5 Appendix E. Comparison Between System/370 and 370-XA New Facilities in 370-XA E-I E-l Bimodal Addressing .... 31-Bit Logical Addressing E-l 31-Bit Real and Absolute Addressing E-l Page Protection . . . . . . . . . . . . E-l Tracing . . . . . . . . . . . . . . . . . E-2 Incorrect-Length-Indication Suppression . E-2 Status Verification .. E-2 E-2 Comparison of Facilities Summary of Changes E-3 This appendix provides ( 1) a list of the facilities that are new in 370-XA and not provided in System/370, (2) a description of the handling in 370-XA of the facilities available in System/370, and (3) a list of changes between System/370 and 370-XA. New Facilities in 370-XA The following facilities are new in 370-XA and are not provided in System/370. Bimodal Addressing Two modes of operation are provided: a 24-bit addreSSing m()de, for the execution of old prograniS, and a 31-bit addressing mode. The mode is controlled by bit 32 in the PSW, and unprivileged instructions are provided that examine and set the mode. These instructions conveniently permit combining old programs, which must operate in the 24-bit addressing mode, and new programs which can take advantage of the 31-bit addressing mode. 3i-Bit Logical Addressing The 31-bit logical addressing includes the ability to perform either 24-bit or 31-bit address arithmetic for operand address generation and includes extensions to the following addresses, which are always 31 bits, regardless of the addressing mode: • • • • Instruction address in psw bits 33-63 PER starting address in control register 10 PER ending address in control register 11 Translation-exception identification stored at reallocations 144-147 Changes in Instructions Provided Input/Output Comparison .... Comparison of PSW Formats .. Changes in Control-Register Assignments Changes in Assigned Storage Locations SIGNAL PROCESSOR Changes . Machine-Check Changes . . . . . . . . Changes to Addressing Wraparound Changes to LOAD REAL ADDRESS Changes to 31-Bit Real Operand Addresses E-3 E-4 E-5 E~6 E-6 E-7 E-7 E-8 E-8 E-8 • PER address stored at reallocations 152-155 • Monitor code stored at reallocations 156-159 • Entry instruction address in the entry-table entry 3i-Bit Real and Absolute Addressing The following fields provide the leftmost part of 31-bit addresses, or the entire address, as appropriate, regardless of the setting of the addressing mode. Except where indicated, the addresses are real. • Prefix register (absolute) • Primary segment-table origin· in control register 1 • Linkage-table origin in control register 5 • Secondary segment-table origin· in control register 7 • ASN-frrst-table origin in control register 14 • Page-table origin in tbe segment-table entry • Page-frame real address in the page-table entry • ASN-second-table origin in the AFT entry • Segment-table origin· f linkage-table origin, and authority-table origin in the AST entry • Entry-table origin in the linkage-table entry • Address in ronnat-l CCws (absolute) ·Unpredictable whether address is real or absolute Page Protection A page-protection bit is provided in the page-table entry. Page protection can be used in a manner similar to the System/370 segment protection, which is not included in 370-XA. Appen4ix E. Comparison Between Systemj370 and 370-XA E-l Tracing Comparison of Facilities Included are a trace-table ongm, branch trace control, ASN trace control, and explicit tracecontrol bits in control register 12. Also included are the instruction TRACE and a new programinterruption condition called trace-table exception. When branch tracing is on, a trace entry is made for the successful execution of the following instructions: Figure E-l shows the facilities offered in System/370 and whether or not each facility is provided in 370-XA. • when the R2 field is BRANCH AND LINK (BALR) nonzero • BRANCH AND SAVE (BASR) when the R2 field is nonzero • BRANCH AND SAVE AND SET MODE (BASSM) when the R2 field is .nonzero When ASN tracing is ·on, an entry is made in the trace table for each execution of the following instructions: • PROGRAM CALL • PROGRAM TRANSFER • SET SECONDARY ASN When explicit tracing is on, execution of causes a trace entry to be made. TRACE Incorrect-Length-Indicatlon Suppression The incorrect-Iength-indication-suppression facility allows the indication of incorrect length to be suppressed when using format-l ccws in ·the same manner as when using format-O ccws or System/370 ccws. Bit 24 of word 1 of the ORB provides the capability of indicating or suppressing recognition of incorrect length for an immediate operation. Status Verification The status-verification facility provides an indication (bit 26 of the subchannel logout in the extended-status word) when the channel subsystem detects device status with a combination of bits that was inappropriate at the time status was presented. System/379 Facility Conmercial instruction set Block-multiplexer channels Branch and save Byte-multiplexer channels Channel indfrect data addressing Channel-set switching Clear I/O Conmand retry Conditional swapping CPU timer and clock comparator o Direct control Dual address space Expanded storage Extended Extended-precision floating.PQinr Extended real addressing External signals Fast release Floating point Halt device I/O extended logout Limited Channel logout Move inverse Multiprocessing PSW-key handling Recovery extensions Segment protection Selector channels Service signal Start-I/O-fast queuing ESA/370 Principles of Operation p1 F B F B F F B B B - p2 ES p3 B R4 - F B F F MI B5 B - R6 F B F Storage-key-instruction extensions Storage-key 4K-byte block Suspend and resume Test block Translation B Vector 31-bi t IDAWs· V B Figure E-2 Availability in 379-XA p7 F B p8 E-l (Part 1 of 2). Availability of System/370 Facilities in 370-XA Summary of Changes Explanation: - Not provided in 370-XA. 1 The following items, which are part of the basic computing function in System/37B, are not provided in 37B-XA: BC mode, interval timer, and 2K-byte protection blocks. Also see the following instructions lists for those instructions basic in System/370 which are not provided in 370-XA. 2 All of the dual-address-space facility is provided except for DAS tracing. 3 See the following instruction list for those instructions that are part of the System/37B extended facility and that are provided in 370-XA. 4 Replaced with 31-bit real addressing. 5 With the exception of the inclusion of more than one CPU, all the functions associated with the System/370 multiprocessing facility are basic. 6 Replaced by page protection. 7 Only single-key 4K-byte protection blocks are provided, but the storage-key-exception control is not. e The 370-XA translation provides only the 4K-byte page size and only the 1M-byte segment size. See also the following instruction lists. B Basic in 370-XA. ES Provided in both System/37B and 370-XA as the expanded-storage facility. F Not provided, but a comparable function is provided by the channel subsystem. MI Provided in both System/370 and 370-XA as the move-inverse facility. P Partially available in 370-XA. R Replaced with a comparable facility. V Provided in both System/370 and 370-XA as the vector facility. Figure Changes in Instructions Provided The following figures show those instructions which are optional or not provided in either System/370 or 370-XA. Those instructions which are basic in both System/370 and 370-XA are not shown. Instruction Name* Op System/ ~lnemonic Code 379 379-XA BRANCH AND SAVE BRANCH AND SAVE BRANCH AND SAVE AND SET MODE BRANCH AND SET MODE COMPARE AND FORM CODEWORD BASR BAS BASSt1 BSM CFC 90 40 9C 9B B21A BS BS COMPARE AND SWAP COMPARE DOUBLE AND SWAP DIVIDE (extended) INSERT PROGRAM MASK MOVE INVERSE UPDATE TREE CS CDS DXR IPM MVCIN UPT BA BB B22D B222 Ea 9192 SW SW - - - MI - B B B B B B B B B MI B Explanation: * B BS MI SW Figure Instruction is not provided. Those instructions which are part of the floatingpoint and extended-precision floating-point facilities in System/379 are basic in 379-XA and are not shown. Similarly, those unprivileged instructions which are part of the vector facility are not shown. Instruction is basic. Branch-and-save facility. Move-inverse facility. Conditional-swapping facility. E-2. Unprivileged Instructions Provided E-l (Part 2 of 2). Availability of Systemj370 Facilities in 370-XA Appendix E. Comparison Between Systemj370 and 370-XA E-3 Instruction Name* Mne- Op System/ monic Code 370 370-XA - CONNECT CHANNEL SET DISCONNECT CHANNEL SET EXTRACT PRIMARY ASN EXTRACT SECONDARY ASN INSERT ADDRESS SPACE CONTROL CONCS DISCS EPAR ESAR lAC B200 B201 B226 B227 B224 CS CS OU DU DU INSERT PSW KEY INSERT STORAGE KEY INSERT STORAGE KEY EXTENDED INSERT VIRTUAL STORAGE KEY INVALIDATE PAGE TABLE ENTRY IPK ISK ISKE IVSK IPTE B20B 09 B229 B223 B221 PK B EK DU EF ADDRESS SPACE PARAMETERS LASP REAL ADDRESS LRA TO PRIMARY MVCP TO SECONDARY MVCS WI TH KEY MVCK E500 B1 DA DB 09 DU TR DU DU DU B B LOAD LOAD MOVE MOVE MOVE - B B B B - B B B B B B PROGRAM CALL PROGRAM TRANSFER PURGE TLB READ DIRECT RESET REFERENCE BIT PC PT PTLB ROD RRB B218 B228 B2ElD 85 B213 DU DU TR DC TR B B B RESET REFERENCE BIT EXTENDED SET ADDRESS SPACE CONTROL SET CLOCK COMPARATOR SET CPU TIMER SET PREFIX RRBE SAC SCKC SPT SPX B22A B219 82El6 B208 B210 EK DU CK CK MP B B B B B SET PSW KEY FROM ADDRESS SET SECONDARY ASN SET STORAGE KEY SET STORAGE KEY EXTENDED SIGNAL PROCESSOR SPKA SSAR SSK SSKE SIGP B29A B225 El8 B22B AE PK DU B EK. MP B B STORE STORE STORE STORE STORE STCKC STAP STPT STPX STNSM B297 B212 B299 B211 AC CK MP CK MP TR B B B B B STOSM T8 TPROT TRACE WRD AD B22C E591 99 84 TR TB EF B B B B CLOCK COMPARATOR CPU ADDRESS CPU TIMER PREFIX THEN AND SYSTEM MASK STORE THEN OR SYSTEM MASK TEST BLOCK TEST PROTECTION TRACE WRITE DIRECT - DC - - - B B - Explanation: * 8 CK CS DC DU EF EK MP PK T8 TR Figure E-4 Instruction is not provided. Those privileged instructions which are part of the vector facility are not shown. Instruction is basic. CPU-timer and clock-comparator facility. Channel-set-switching facility. Direct-control facility. Dual-address-space facility. Extended facility. Storage-key-instruction-extension facility. Multiprocessing facility. PSW-key-handling facility. Test-block facility. Translation facility. E-3. Control Instructions Provided ESA/370 Principles of Operation Instruction Name Mne- Op System/ monic Code 379 37El-XA CLEAR CHANNEL CLEAR I/O HALT DEVICE HALT I/O RESUME I/O CLRCH CLRIO HDV HIO RIO 9FEl1 9DEl1 9EEl1 9EElO 9C02 RE B HD B SR - START I/O START I/O FAST RELEASE STORE CHANNEL 10 TEST CHANNEL TEST I/O SIO SIOF STIDC TCH TIO 9COO 9CEl1 82El3 9F90 9DOEl B FR 8 B B - CLEAR SUBCHANNEL HALT SUBCHANNEL MODIFY SU8CHANNEL RESET CHANNEL PATH RESUME SUBCHANNEL CSCH HSCH MSCH RCHP RSCH B23El B231 8232 8238 B238 - B B B 8 B SET ADDRESS LIMIT SET CHANNEL MONITOR START SUBCHANNEL STORE CHANNEL PATH STATUS STORE CHANNEL REPORT WORD SAL SCHM SSCH STCPS STCRW B237 B23C B233 B23A B239 - B B B B B STORE SUBCHANNEL TEST PENDING INTERRUPTION TEST SU8CHANNEL STSCH B234 TPI B236 TSCH 8235 - B B 8 - - - Explanation: - 8 FR HD RE SR Figure Instruction is not provided. Instruction is basic. Performs the SIOF function only when the fastrelease facility is installed in the channel. Performs the HDV function only when the halt-device facility is installed in the channel. Performs the CLRCH function only when the recoveryextension facility is installed in the channel. Suspend-and-resume facility. E-4. I/O Instructions Provided Input/Output Comparison The channel subsystem has a different logical structure from that of the I/O facilities provided in System/370, with .the result that I/O instructions, channels, channel sets, and I/O addressing are replaced in 370-XA by a new set of I/O instructions, by logical device addressing, and by deviceaccessing mechanisms. Compatibility with System/370 has been maintained in the ccws (format 0), 31-bit IDAWS, and channel programs. In System/370, subchannels are not shared among channels, and each subchannel is associated with only one channel path. In 370-XA, each subchannel is uniquely associated with one I/O device, and that I/O device is uniquely associated with that one subchannel within the channel subsystem, regardless of the number of channel paths by which the I/O device is accessible to the channel subsystem. Functions are provided in the channel subsystem in to detect malfunctions and recover from them if possible.. Malfunctions are reported to the program by means of a channel report. 370-XA In System/370, I/O interruptions are accepted only by the CPU to which the channel set is currently connected. The I/O interruption causes the I/O address identifying the channel and device causing the interruption to be stored at locations 186-187, and the measurement byte to be stored at real location 185. In 370-XA, I/O interruptions can be accepted by any CPU in the configuration. The subsystem ID and I/o-interruption parameter are stored in the doubleword at reallocation 184. Associated with the new I/O instructions is a new program-interruption condition called operand exception. Comparison of PSW Formats Figure E-5 shows those bits and fields in the psw which are different between System/370 and 370-XA. Name of Bit or Field PER Mask OAT Mode EC Mode Bit 12 = 0 (BC Mode) Bit 12 = 1 (EC Mode) Address-space control Addressing mode Instruction address PSW System/ Bit 370 370-XA 1 5 TR TR 12 B TR 16 32 DU * B - B B - B1 B B B Explanation: - Mode is not provided. * The instruction address is in PSW bits 4063 in System/370 and bits 33-63 in 370-XA. 1 In 370-XA, PSW bit 12 must be one, and the term "EC mode" is not used. B Basic. DU Provided as part of the dual-address-space facility. TR Provided as part of the translation faci lity. Figure E-S. Comparison of PSW Formats Append:ix E. Comparison Between Systemj370 and 370-XA E-5 Changes in Control-Register Assignments Changes in Assigned Storage Locations Figure E-6 shows those bits and fields in the control registers which are different between System/370 and 370-XA. Figure E-7 shows those assigned storage locations where I changes have been made between System/370 and 370-XA. Control-Register Position for Name of Bit or Field System/37a Block-multiplexing control Fetch-protection override Storage-key-exception control Page-fault-assist control Interval-timer subclass mask a.a a.7 9.13 9.24 External-signal subclass mask Space-switch-event control Primary segment-table origin Primary segment-table length Channel masks 9.26 1.31 1.8-1.25 1. a-I. 7 2.a-2.31 37a-XA - a.6 - - La 1.1-1.19 1. 25-1. 31 - 5.1-5.24 6.9-6.7 7.25-7.31 7.1-7.19 la.l-la.31 PER ending address Branch-trace control Trace-entry address ASN-trace control Explicit-trace control 11. 8-11. 31 11.1-11.31 12.a 12.1-12.29 12.3a 12.31 Check-stop control Synchronous-HCEl control I/O-extended-logout control Channel-report-pending subclass mask Asynchronous-HCEl control Asynchronous-fixed-log control ASN-first-table origin HCEl address 14.a 14.1 14.2 - - - 14.3 14.8 14.9 14.29-14.31 14.13-14.31 15.8-15.28 - Explanation: - System/ 370 370-XA Channel-status word Channel-address word Interval timer Trace-table designation Channel ID 64 72 80 84 168 8 4 4 4 4 IOEL address Limited channel logout Subsystem ID Measurement byte I/O address 172 176 44184 4 12- I/O-interruption parameter Region code Fixed-logout area Store-status model-dependent save area CPU identity 188 4 252 4 256 96 256 16 268 4 - - 185 186 795 - 1- Explanation: * Field is not provided. The first number is the address) the second the length. Bit or field is not provided. Figure E-6 Name of Field - linkage-table origin 5.8-5.24 I/O-interruption subclass mask Secondary segment-table length 7.a-7.7 Secondary segment-table origin 7.8-7.25 PER starting address 19.8-1a.31 - Assigned Storage Location and Length* for Figure E-6. Differences in Control-Register Assignments ESA/370 Principles of Operation E-7. Differences in Assigned Storage Locations SIGNAL PROCESSOR Changes Machine-Check Changes Figure E-8 and Figure E-9 show those SIGNAL PROCESSOR orders and status codes where changes have been made between System/370 and 370-XA. In addition to these changes, a parameter is provided as part of the SIGNAL PROCESSOR instruction in 370-XA. The parameter is used by the storestatus-at-address and set-prefix orders. Figure E-I0 summarizes those bits and fields in the machine-cheek-interruption code (MCIC) where changes have been made between System/370 and 370-XA. In addition to these changes, the region code, the machine-cheek-extended logout, and asynchronous fixed logouts have been eliminated in 370-XA. Order Code MCIC Bits System/ 370 370-XA Name of Order Initial program reset Program reset Initial microprogram load Set prefix Store status at address - 07 08 0A - - 00 0E Machine-Cheek-Interruption Condition or Field Explanation: Interval-timer damage Channel report pending Channel-subsystem damage Delayed Region-code validity Logout validity MCEL length - Explanation: - - Order is not provided. - Figure 'E-8. Signal-Processor Orders System/ 370 370-XA 3 - - 15 25 30 48-63 9 11 - - Condition or field is not provided. Figure E-IO. Machine-Check-Interruption-Code Bits Bit Position. Name of Status Bit System/370 370-XA Incorrect state Invalid parameter Not ready - 28 22 23 - Explanation: - Status bit is not provided. Figure E-9. Signal-Processor Status Bits Appendix E. Comparison Between Systemj370 and 370-XA E-7 Changes to Addressing Wraparound Changes to LOAD REAL ADDRESS In System/370, addresses wrap from 224 - 1 to zero (or vice versa). In 370-XA, for the 24-bit addressing mode, effective addresses wrap from 224 - 1 to zero (or vice versa). For the 31-bit addressing mode, effective addresses wrap from 231 - 1 to zero (or vice versa). Except as noted below, real and absolute addresses wrap from 231 - 1 to zero. For LOAD REAL ADDRFSS, the addressing of DAT tables is changed to be unpredictable with respect to whether prefixing is applied and to be unpredictable with respect to whether an addressing exception is recognized or wraparound occurs when the calculated address of a page-table or segment-table entry exceeds 231 - 1. In 370-XA, the following items cause an I/O program check instead of wraparound: • Successive CCws of a ccw list • Successive IDAWS of an IDAW list • Successive bytes of I/O data For DAT-table entries, it is model-dependent whether addresses wrap or cause an addressing exception. Changes to 31-Bit Real Operand Addresses The following instructions operate by using 31-bit real addresses in System/370. In 370-XA, these instructions operate under control of the addressing mode, bit 32 of the psw. As a result, in the 24-bit addressing mode, these instructions operate by using 24-bit addresses. • • • • E-8 ESAj370 Principles of Operation INSERT STORAGE KEY EXTENDED RFSET REFERENCE BIT EXTENDED SET STORAGE KEY EXTENDED TFST BLOCK Appendix F. Table of Powers of 2 PLUS 1 2 4 8 0 1 2 3 16 32 64 128 4 5 6 -7 8 9 10 MINUS 1. 0.5 0.25 0.125 0.0625 0.03125 0.01562 5 0.00781 25 11 0.00390 0.00195 - 0.00097 0.00048 4,096 8,192 16,384 32,768 12 13 14 15 0.00024 0.00012 0.00006 0.00003 41406 20703 10351 05175 25 125 5625 78125 65,536 131,072 262,144 524,288 16 17 18 19 0.00001 0.00000 0.00000 0.00000 52587 76293 38146 19073 89062 94531 97265 48632 5 25 625 8125 1,048,576 2,097,152 4,194,304 8,388,608 20 21 22 23 0.00000 0.00000 0.00000 0.00000 09536 04768 02384 01192 74316 37158 18579 09289 40625 20312 5 10156 25 55078 125 16,777,216 33,554,432 67,108,864 134,217,728 24 25 26 27 0.00000 0.00000 0.00000 0.00000 00596 00298 00149 00074 04644 02322 01161 50580 77539 38769 19384 59692 0625 53125 76562 5 38281 25 268,435,456 536,870,912 1,073,741,824 2,147,483,648 28 29 30 31 0.00000 0.00000 0.00000 0.00000 00037 00018 00009 00004 25290 62645 31322 65661 29846 14923 57461 28730 19140 09570 54785 77392 625 3125 15625 57812 5 4,294,967,296 8,589,934,592 17,179,869,184 34,359,738,368 32 33 34 35 0.00000 0.00000 0.00000 0.00000 00002 00001 00000 00000 32830 16415 58207 29103 64365 32182 66091 83045 38696 69348 34674 67337 28906 14453 07226 03613 25 125 5625 28125 68 719,476,736 137:438,953,472 274,877,906,944 549,755,813,888 36 37 -38 39 0.00000 0.00000 0.00000 - 0.00000 00000 00000 00000 00000 14551 07275 03637 01818 91522 95761 97880 98940 83668 41834 70917 35458 51806 25903 12951 56475 64062 5 32031 25 66015625 83007 8125 1,099,511,627,776 2,199,023,255,552 4,398,046,511,104 8,796;093,022,208 40 41 42 43 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00909 00454 00227 00113 49470 74735 37367 68683 17729 08864 54432 77216 28237 64118 32059 16029 91503 95751 47875 73937 90625 95312 5 97656 25 98828 125 17,592,186,044,416 35,184,372,088,832 70,368,744,177,664 140,737,488,355,328 44 45 46 47 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00056 00028 00014 00007 84341 42170 21085 10542 88608 94304 47152 73576 08014 04007 02003 01001 86968 43484 71742 85871 99414 49707 24853 12426 0625 03125 51562 5 75781 25 281,474,976,710,656 562,949,953,421,312 1,125,899,906,842,624 2,251,799,813,685,248 48 49 50 51 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00003 00001 00000 00000 55271 77635 88817 44408 36788 68394 84197 92098 00500 00250 00125 50062 92935 46467 23233 61616 56213 78106 89053 94526 37890 68945 34472 67236 625 3125 65625 32812 5 4,503,599,627,370,496 9,007,199,254,740,992 18,014,398,509,481,984 36,028,797,018,963,968 52 53 54 55 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00000 00000 00000 00000 22204 11102 05551 02775 46049 23024 11512 55756 25031 62515 31257 15628 30808 65404 82702 91351 47263 23631 11815 05907 33618 66809 83404 91702 16406 08203 54101 27050 25 125 5625 78125 72,057,594,037,927,936 144,115,188,075,855,872 288,230,376,151,711,744 576,460,752,303,423,488 56 57 58 59 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00000 00000 00000 00000 01387 00693 00346 00173 77878 88939 94469 47234 07814 03907 51953 75976 45675 22837 61418 80709 52953 76476 88238 44119 95851 97925 48962 24481 13525 56762 78381 39190 39062 69531 34765 67382 5 25 625 8125 1,152,921,504,606,846,976 2,305,843,009,213,693,952 4,611,686,018,427,387,904 9,223,372,036,854,775,808 60 61 62 63 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00000 00000 00000 00000 00086 00043 00021 00010 73617 36808 68404 84202 37988 68994 34497 17248 40354 20177 10088 55044 72059 36029 68014 34007 62240 81120 90560 45280 69595 34797 17398 08699 33691 66845 83422 41711 40625 70312 5 85156 25 42578 125 18,446,744,073,709,551,616 64 0.00000 00000 00000 00005 42101 08624 27522 17003 72640 04349 70855 71289 0625 256 512 1,024 2,048 Figure 625 3125 65625 82812 5 F -1 (Part 1 of 2). Powers of 2 Appendix F. Table of Powers of 2 F-1 18,446,744,073,709,551,616 36,893,488,147,419,103,232 73,786,976,294,838,206,464 147,573,952,589,676,412,928 64 65 66 67 295,147,905,179,352,825,856 590,295,810,358,705,651,712 1,180,591,620,717,411,303,424 2,361,183,241,434,822,606,848 4,722,366,482,869,645,213,696 9,444,732,965,739,290,427,392 18,889,465,931,478,580,854,784 37,778,931,862,957,161,709,568 68 69 70 71 72 73 74 75 75,557,863,725,914,323,419,136 151,115,727,451,828,646,838,272 302,231,454,903,657,293,676,544 604,462,909,807,314,587,353,088 76 77 78 79 1,208,925,819,614,629,174,706,176 2,417,851,639,229,258,349,412,352 4,835,703,278,458,516,698,824,704 9,671,406,556,917,033,397,649,408 19,342,813,113,834,066,795,298,816 38,685,626,227,668,133,590,597,632 77,371,252,455,336,267,181,195,264 154,742,504,910,672,534,362,390,528 80 81 82 83 84 85 86 87 309,485,009,821,345,068,724,781,056 618,970,019,642,690,137,449,562,112 1,237,940,039,285,380,274,899,124,224 2,475,880,078,570,760,549,798,248,448 4,951,760,157,141,521,099,596,496,896 9,903,520,314,283,042,199,192,993,792 19,807,040,628,566,084,398,385,987,584 39,614,081,257,132,168,796,771,975,168 79,228,162,514,264,337,593,543,950,336 158,456,325,028,528,675,187,087,900,672 316,912,650,057,057,350,374,175,801,344 633,825,300,114,114,700,748,351,602,688 88 89 90 91 92 93 94 95 96 97 98 99 1,267,650,600,228,229,401,496,703,205,376 2,535,301,200,456,458,802,993,406,410,752 5,070,602,400,912,917,605,986,812,821,504 10,141,204,801,825,835,211,973,625,643,008 20,282,409,603,651,670,423,947,251,286,016 40,564,819,207,303,340,847,894,502,572,032 81,129,638,414,606,681,695,789,005,144,064 162,259,276,829,213,363,391,578,010,288,128 100 101 102 103 104 105 106 107 324,518,553,658,426,726,783,156,020,576,256 649,037,107,316,853,453,566,312,041,152,512 1,298,074,214,633,706,907,132,624,082,305,024 2,596,148,429,267,413,814,265,248,164,610,048 108 109 110 111 5,192,296,858,534,827,628,530,496,329,220,096 112 113 20,769,187,434,139,310,514,121,985,316,880,384 114 41,538,374,868,278,621,028,243,970,633,760,768 115 10,384,5~3,717,069,655,257,060,992,658,440,192 83,076,749,736,557,242,056,487,941,267,521,536 166,153,499,473,114,484,112,975,882,535,043,072 332,306,998,946,228,968,225,951,765,070,086,144 664,613,997,892,457,936,451,903,530,140,172,288 116 117 118 119 1,329,227,995,784,915,872,903,807,060,280,344,576 2,658,455,991,569,831,745,807,614,120,560,689,152 5,316,911,983,139,663,491,615,228,241,121,378,304 10,633,823,966,279,326,983,230,456,482,242,756,608 21,267,647,932,558,653,966,460,912,964,485,513,216 42,535,295,865,117,307,932,921,825,928,971,026,432 85,070,591,730,234,615,865,843,651,857,942,052,864 170,141,183,460,469,231,731,687,303,715,884,105,728 120 121 122 123 124 125 126 127 340,282,366,920,938,463,463,374,607,431,768,211,456 128 Figure F-2 F -1 (Part 2 of 2). Powers of 2 ESAj370 Principles of Operation Appendix G. Hexadecimal Tables The following tables aid in converting hexadecimal values to decimal values, or the reverse. Direct Conversion Table This table provides direct conversion of decimal and hexadecimal numbers in these ranges: Hexadecimal Decimal 000 to FFF 0000 to 4095 To convert numbers outside these ranges, and to convert fractions, use the hexadecimal and decimal conversion tables that follow the direct conversion table in this Appendix. 00_ 01_ 02_ 03_ 04_ 05_ 06_ 07_ 08_ 09_ OA_ OB_ OC_ OD_ OE_ OF_ 10_ 11_ 12_ 13_ 14_ 15_ 16_ 17_ 18_ 19_ lA_ 1B_ lC_ ID_ lE_ IF_ 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0016 0032 0048 0064 0080 0096 0112 0128 0144 0160 0176 0192 0208 0224 0240 0001 0017 0033 0049 0065 0081 0097 0113 0129 0145 0161 0177 0193 0209 0225 0241 0002 0018 0034 0050 0066 0082 0098 0114 0130 0146 0162 0178 0194 0210 0226 0242 0003 0019 0035 0051 0067 0083 0099 0115 0131 0147 0163 0179 0195 0211 0227 0243 0004 0020 0036 0052 0068 0084 0100 0116 0132 0148 0164 0180 0196 0212 0228 0244 0005 0021 0037 0053 0069 0085 0101 0117 0133 0149 0165 0181 0197 0213 0229 0245 0006 0022 0038 0054 0070 0086 0102 0118 0134 0150 0166 0182 0198 0214 0230 0246 0007 0023 0039 0055 0071 0087 0103 0119 0135 0151 0167 0183 0199 0215 0231 0247 0008 0024 0040 0056 0072 0088 0104 0120 0136 0152 0168 0184 0200 0216 0232 0248 0009 0025 0041 0057 0073 0089 0105 0121 0137 0153 0169 0185 0201 0217 0233 0249 0010 0026 0042 0058 0074 0090 0106 0122 0138 0154 0170 0186 0202 0218 0234 0250 0011 0027 0043 0059 0075 0091 0107 0123 0139 0155 0171 0187 0203 0219 0235 0251 0012 0028 0044 0060 0076 0092 0108 0124 0140 0156 0172 0188 0204 0220 0236 0252 0013 0029 0045 0061 0077 0093 0109 0125 0141 0157 0173 0189 0205 0221 0237 0253 0014 0030 0046 0062 0078 0094 0110 0126 0142 0158 0174 0190 0206 0222 0238 0254 0015 0031 0047 0063 0079 0095 0111 0127 0143 0159 0175 0191 0207 0223 0239 0255 0256 0272 0288 0304 0320 0336 0352 0368 0384 0400 0416 0432 0448 0464 0480 0496 0257 0273 0289 0305 0321 0337 0353 0369 0385 0401 0417 0433 0449 0465 0481 0497 0258 0274 0290 0306 0322 0338 0354 0370 0386 0402 0418 0434 0450 0466 0482 0498 0259 0275 0291 0307 0323 0339 0355 0371 0387 0403 0419 0435 0451 0467 0483 0499 0260 0276 0292 0308 0324 0340 0356 0372 0388 0404 0420 0436 0452 0468 0484 0500 0261 0277 0293 0309 0325 0341 0357 0373 0389 0405 0421 0437 0453 0469 0485 0501 0262 0278 0294 0310 0326 0342 0358 0374 0390 0406 0422 0438 0454 0470 0486 0502 0263 0279 0295 0311 0327 0343 0359 0375 0391 0407 0423 0439 0455 0471 0487 0503 0264 0280 0296 0312 0328 0344 0360 0376 0392 0408 0424 0440 0456 0472 0488 0504 0265 0281 0297 0313 0329 0345 0361 0377 0393 0409 0425 0441 0457 0473 0489 0505 0266 0282 0298 0314 0330 0346 0362 0378 0394 0410 0426 0442 0458 0474 0490 0506 0267 0283 0299 0315 0331 0347 0363 0379 0395 0411 0427 0443 0459 0475 0491 0507 0268 0284 0300 0316 0332 0348 0364 0380 0396 0412 0428 0444 0460 0476 0492 0508 0269 0285 0301 0317 0333 0349 0365 0381 0397 0413 0429 0445 0461 0477 0493 0509 0270 0286 0302 0318 0334 0350 0366 0382 0398 0414 0430 0446 0462 0478 0494 0510 0271 0287 0303 0319 0335 0351 0367 0383 0399 0415 0431 0447 0463 0479 0495 0511 Appendix G. Hexadecimal Tables G-l 0 1 2 3 4 5 6 7 8 9 A B C D E F 20_ 21_ 22_ 23_ 24_ 25_ 26_ 27_ 28_ 29_ 2A_ 2B_ 2C_ 2D_ 2E_ 2F_ 0512 0528 0544 0560 0576 0592 0608 0624 0640 0656 0672 0688 0704 0720 0736 0752 0513 0529 0545 0561 0577 0593 0609 0625 0641 0657 0673 0689 0705 0721 0737 0753 0514 0530 0546 0562 0578 0594 0610 0626 0642 0658 0674 0690 0706 0722 0738 0754 0515 0531 0547 0563 0579 0595 0611 0627 0643 0659 0675 0691 0707 0723 0739 0755 0516 0532 0548 0564 0580 0596 0612 0628 0644 0660 0676 0692 0708 0724 0740 0756 0517 0533 0549 0565 0581 0597 0613 0629 0645 0661 0677 0693 0709 0725 0741 0757 0518 0534 0550 0566 0582 0598 0614 0630 0646 0662 0678 0694 0710 0726 0742 0758 0519 0535 0551 0567 0583 0599 0615 0631 0647 0663 0679 0695 0711 0727 0743 0759 0520 0536 0552 0568 0584 0600 0616 0632 0648 0664 0680 0696 0712 0728 0744 0760 0521 0537 0553 0569 0585 0601 0617 0633 0649 0665 0681 0697 0713 0729 0745 0761 0522 0538 0554 0570 0586 0602 0618 0634 0650 0666 0682 0698 0714 0730 0746 0762 0523 0539 0555 0571 0587 0603 0619 0635 0651 0667 0683 0699 0715 0731 0747 0763 0524 0540 0556 0572 0588 0604 0620 0636 0652 0668 06"84 0700 0716 0732 0748 0764 0525 0541 0557 0573 0589 0605 0621 0637 0653 0669 0685 0701 0717 0733 0749 0765 0526 0542 0558 0574 0590 0606 0622 0638 0654 0670 0686 0702 0718 0734 0750 0766 0527 0543 0559 0575 0591 0607 0623 0639 0655 0671 0687 0703 0719 0735 0751 0767 30_ 31_ 32_ 33_ 34_ 35_ 36_ 37_ 38_ 39_ 3A_ 3B_ 3C_ 3D_ 3E_ 3F_ 0768 0784 0800 0816 0832 0848 0864 0880 0896 0912 0928 0944 0960 0976 0992 1008 0769 0785 0801 0817 0833 0849 0865 0881 0897 0913 0929 0945 0961 0977 0993 1009 0770 0786 0802 0818 0834 0850 0866 0882 0898 0914 0930 0946 0962 0978 0994 1010 0771 0787 0803 0819 0835 0851 0867 0883 0899 0915 0931 0947 0963 0979 0995 1011 0772 0788 0804 0820 0836 0852 0868 0884 0900 0916 0932 0948 0964 0980 0996 1012 0773 0789 0805 0821 0837 0853 0869 0885 0901 0917 0933 0949 0965 0981 0997 1013 0774 0790 0806 0822 0838 0854 0870 0886 0902 0918 0934 0950 0966 0982 0998 1014 0775 0791 0807 0823 0839 0855 0871 0887 0903 0919 0935 0951 0967 0983 0999 1015 0776 0792 0808 0824 0840 0856 0872 0888 0904 0920 0936 0952 0968 0984 1000 1016 0777 0793 0809 0825 0841 0857 0873 0889 0905 0921 0937 0953 0969 0985 1001 1017 0778 0794 0810 0826 0842 0858 0874 0890 0906 0922 0938 0954 0970 0986 1002 1018 0779 0795 0811 0827 0843 0859 0875 0891 0907 0923 0939 0955 0971 0987 1003 1019 0780 0796 0812 0828 0844 0860 0876 0892 0908 0924 0940 0956 0972 0988 1004 1020 0781 0797 0813 0829 0845 0861 0877 0893 0909 0925 0941 0957 0973 0989 1005 1021 0782 0798 0814 0830 0846 0862 0878 0894 0910 0926 0942 0958 0974 0990 1006 1022 0783 0799 0815 0831 0847 0863 0879 0895 0911 0927 0943 0959 0975 0991 1007 1023 0 1 2 3 4 5 6 7 8 9 A B C D E F 1024 1040 1056 1072 1088 1104 1120 1136 1152 1168 1184 1200 1216 1232 1248 1264 1025 1041 1057 1073 1089 1105 1121 1137 1153 1169 1185 1201 1217 1233 1249 1265 1026 1042 1058 1074 1090 1106 1122 1138 1154 1170 1186 1202 1218 1234 1250 1266 1027 1043 1059 1075 1091 1107 1123 1139 1155 1171 1187 1203 1219 1235 1251 1267 1028 1044 1060 1076 1092 1108 1124 1140 1156 1172 1188 1204 1220 1236 1252 1268 1029 1045 1061 1077 1093 1109 1125 1141 1157 1173 1189 1205 1221 1237 1253 1269 1030 1046 1062 1078 1094 1110 1126 1142 1158 1174 1190 1206 1222 1238 1254 1270 1031 1047 1063 1079 1095 1111 1127 1143 1159 1175 1191 1207 1223 1239 1255 1271 1032 1048 1064 1080 1096 1112 1128 1144 1160 1176 1192 1208 1224 1240 1256 1272 1033 1049 1065 1081 1097 1113 1129 1145 1161 1177 1193 1209 1225 1241 1257 1273 1034 1050 1066 1082 1098 1114 1130 1146 1162 1178 1194 1210 1226 1242 1258 1274 1035 1051 1067 1083 1099 1115 1131 1147 1163 1179 1195 1211 1227 1243 1259 1275 1036 1052 1068 1084 1100 1116 1132 1148 1164 1180 1196 1212 1228 1244 1260 1276 1037 1053 1069 1085 1101 1117 1133 1149 1165 1181 1197 1213 1229 1245 1261 1277 1038 1054 1070 1086 1102 1118 1134 1150 1166 1182 1198 1214 1230 1246 1262 1278 1039 1055 1071 1087 1103 1119 1135 1151 1167 1183 1199 1215 1231 1247 1263 1279 1280 1296 1312 1328 1344 1360 1376 1392 1408 1424 1440 1456 1472 1488 1504 1520 1281 1297 1313 1329 1345 1361 1377 1393 1409 1425 1441 1457 1473 1489 1505 1521 1282 1298 1314 1330 1346 1362 1378 1394 1410 1426 1442 1458 1474 1490 1506 1522 1283 1299 1315 1331 1347 1363 1379 1395 1411 1427 1443 1459 1475 1491 1507 1523 1284 1300 1316 1332 1348 1364 1380 1396 1412 1428 1444 1460 1476 1492 1508 1524 1285 1301 1317 1333 1349 1365 1381 1397 1413 1429 1445 1461 1477 1493 1509 1525 1286 1302 1318 1334 1350 1366 1382 1398 1414 1430 1446 1462 1478 1494 1510 1526 1287 1303 1319 1335 1351 1367 1383 1399 1415 1431 1447 1463 1479 1495 1511 1527 1288 1304 1320 1336 1352 1368 1384 1400 1416 1432 1448 1464 1480 1496 1512 1528 1289 1305 1321 1337 1353 1369 1385 1401 1417 1433 1449 1465 1481 1497 1513 1529 1290 1306 1322 1338 1354 1370 1386 1402 1418 1434 1450 1466 1482 1498 1514 1530 1291 1307 1323 1339 1355 1371 1387 1403 1419 1435 1451 1467 1483 1499 1515 1531 1292 1308 1324 1340 1356 1372 1388 1404 1420 1436 1452 1468 1484 1500 1516 1532 1293 1309 1325 1341 1357 1373 1389 1405 1421 1437 1453 1469 1485 1501 1517 1533 1294 1310 1326 1342 1358 1374 1390 1406 1422 1438 1454 1470 1486 1502 1518 1534 1295 1311 1327 1343 1359 1375 1391 1407 1423 1439 1455 1471 1487 1503 1519 1535 40_ 41_ 42_ 43_ 44_ 45_ 46_ 47_ 48_ 49_ 4A_ 4B_ 4C_ 4D_ 4E_ 4F_ 50_ 51_ 52_ 53_ 54_ 55_ 56_ 57_ 58_ 59_ 5.L 5B_ 5C_ 5D_ 5E_ 5F_ G·2 ESAj370 Principles of Operation 60_ 61_ 62_ 63_ 64_ 65_ 66_ 67_ 68_ 69_ 6A6B_ 6C_ 6D_ 6E_ 6F_ 70_ 71_ 72_ 73_ 74_ 75_ 76_ 77_ 78_ 79_ 7A_ 7B_ 7C_ 7D_ 7E_ 7F_ 80_ 81_ 82_ 83_ 84_ 85_ 86_ 87_ 88_ 89_ 8A_ 8B_ 8C_ 8D_ 8E_ 8F_ 90_ 9L 92_ 93_ 94_ 95_ 96_ 97_ 98_ 99_ 9A_ 9B_ 9C_ 9D_ 9E_ 9F_ 0 1 2 3 4 5 6 7 8 9 A B C D E F 1536 1552 1568 1584 1600 1616 1632 1648 1664 1680 1696 1712 1728 1744 1760 1776 1537 1553 1569 1585 1601 1617 1633 1649 1665 1681 1697 1713 1729 1745 1761 1777 1538 1554 1570 1586 1602 1618 1634 1650 1666 1682 1698 1714 1730 1746 1762 1778 1539 1555 1571 1587 1603 1619 1635 1651 1667 1683 1699 1715 1731 1747 1763 1779 1540 1556 1572 1588 1604 1620 1636 1652 1668 1684 1700 1716 1732 1748 1764 1780 1541 1557 1573 1589 1605 1621 1637 1653 1669 1685 1701 1717 1733 1749 1765 1781 1542 1558 1574 1590 1606 1622 1638 1654 1670 1686 1702 1718 1734 1750 1766 1782 1543 1559 1575 1591 1607 1623 1639 1655 1671 1687 1703 1719 1735 1751 1767 1783 1544 1560 1576 1592 1608 1624 1640 1656 1672 1688 1704· 1720 1736 1752 1768 1784 1545 1561 1577 1593 1609 1625 1641 1657 1673 1689 1705 1721 1737 1753 1769 1785 1546 1562 1578 1594 1610 1626 1642 1658 1674 1690 1706 1722 1738 1754 1770 1786 1547 1563 1579 1595 1611 1627 1643 1659 1675 1691 1707 1723 1739 1755 1771 1787 1548 1564 1580 1596 1612 1628 1644 1660 1676 1692 1708 1724 1740 1756 1772 1788 1549 1565 1581 1597 1613 1629 1645 1661 1677 1693 1709 1725 1741 1757 1773 1789 1550 1566 1582 1598 1614 1630 1646 1662 1678 1694 1710 1726 1742 1758 1774 1790 1551 1567 1583 1599 1615 1631 1647 1663 1679 1695 1711 1727 1743 1759 1775 1791 1792 1808 1824 1840 1856 1872 1888 1904 1920 1936 1952 1968 1984 2000 2016 2032 1793 1809 1825 1841 1857 1873 1889 1905 1921 1937 1953 1969 1985 2001 2017 2033 1794 1810 1826 1842 1858 1874 1890 1906 1922 1938 1954 1970 1986 2002 2018 2034 1795 1811 1827 1843 1859 1875 1891 1907 1923 1939 1955 1971 1987 2003 2019 2035 1796 1812 1828 1844 1860 1876 1892 1908 1924 1940 1956 1972 1988 2004 2020 2036 1797 1813 1829 1845 1861 1877 1893 1909 1925 1941 1957 1973 1989 2005 2021 2037 1798 1814 1830 1846 1862 1878 1894 1910 1926 1942 1958 1974 1990 2006 2022 2038 1799 1815 1831 1847 1863 1879 1895 1911 1927 1943 1959 1975 1991 2007 2023 2039 1800 1816 1832 1848 1864 1880 1896 1912 1928 1944 1960 1976 1992 2008 2024 2040 1801 1817 1833 1849 1865 1881 1897 1913 1929 1945 1961 1977 1993 2009 2025 2041 1802 1818 1834 1850 1866 1882 1898 1914 1930 1946 1962 1978 1994 2010 2026 2042 1803 1819 1835 1851 1867 1883 1899 1915 1931 1947 1963 1979 1995 2011 2027 2043 1804 1820 1836 1852 1868 1884 1900 1916 1932 1948 1964 1980 1996 2012 2028 2044 1805 1821 1837 1853 1869 1885 1901 1917 1933 1949 1965 198.1 1997 2013 2029 2045 1806 1822 1838 1854 1870 1886 1902 1918 1934 1950 1966 1982 1998 2014 2030 2046 1807 1823 1839 1855 1871 1887 1903 1919 J935 1951 1967 1983 1999 2015 2031 2047 0 1 2 3 4 5 6 7 8 9 A B C D E F 2048 2064 2080 2096 2112 2128 2144 2160 2176 2192 2208 2224 2240 2256 2272 2288 2049 2065 2081 2097 2113 2129 2145 2161 2177 2193 2209 2225 2241 2257 2273 2289 2050 2066 2082 2098 2114 2130 2146 2162 2178 2194 2210 2226 2242 2258 2274 2290 2051 2067 2083 2099 2115 2131 2147 2163 2179 2195 2211 2227 2243 2259 2275 2291 2052 2068 2084 2100 2116 2132 2148 2164 2180 2196 2212 2228 2244 2260 2276 2292 2053 2069 2085 2101 2117 2133 2149 2165 2181 2197 2213 2229 2245 2261 2277 2293 2054 2070 2086 2102 2118 2134 2150 2166 2182 2198 2214 2230 2246 2262 2278 2294 2055 2071 2087 2103 2119 2135 2151 2167 2183 2199 2215 2231 2247 2263 2279 2295 2056 2072 2088 2104 2120 2136 2152 2168 2184 2200 2216 2232 2248 2264 2280 2296 2057 2073 2089 2105 2121 2137 2153 2169 2185 2201 2217 2233 2249 2265 2281 2297 2058 2074 2090 2106 2122 2138 2154 2170 2186 2202 2218 2234 2250 2266 2282 2298 2059 2075 2091 2107 2123 2139 2155 2171 2187 2203 2219 2235 2251 2267 2283 2299 2060 2076 ·2092 2108 2124 2140 2156 2172 2188 2204 2220 2236 2252 2268 2284 2300 2061 2077 2093 2109 2125 2141 2157 2173 2189 2205 2221 2237 2253 2269 2285 2301 2062 2078 2094 2110 2126 2142 2158 2174 2190 2206 2222 2238 2254 2270 2286 2302 2063 2079 2095 2111 2127 2143 2159 2175 2191 2207 2223 2239 2255 2271 2287 2303 2304 2320 2336 2352 2368 2384 2400 2416 2432 2448 2464 2480 2496 2512 2528 2544 2305 2321 2337 2353 2369 2385 2401 2417 2433 2449 2465 2481 2497 2513 2529 2545 2306 2322 2338 2354 2370 2386 2402 2418 2434 2450 2466 2482 2498 2514 2530 2546 2307 2323 2339 2355 2371 2387 2403 2419 2435 2451 2467 2483 2499 2515 2531 2547 2308 2324 2340 2356 2372 2388 2404 2420', 2436 2452 2468 2484 2500 2516 2532 2548 2309 2325 2341 2357 2373 2389 2405 2421 2437 2453 2469 2485 2501 2517 2533 2549 2310 2326 2342 2358 2374 2390 2406 2422 2438 2454 2470 2486 2502 2518 2534 2550 2311 2327 2343 2359 2375 2391 2407 2423 2439 2455 2471 2487 2503 25·19 2535 2551 2312 2328 2344 2360 2376 2392 2408 2424 2440 2456 2472 2488 2504 2520 2536 2552 2313 2329 2345 2361 2377 2393 2409 2425 2441 2457 2473 2489 2505 2521 2537 2553 2314 2330 2346 2362 2378 2394 2410 2426 2442 2458 2474 2490 2506 2522 2538 2554 2315 2331 2347 2363 2379 2395 2411 2427 2443 2459 2475 2491 2507 2523 2539 2555 2316 2332 2348 2364 2380 2396 2412 2428 2444 2460 2476 2492 2508 2524 2540 2556 2317 2333 2349 2365 2381 2397 2413 2429 2445 2461 2477 2493 2509 2525 2541 2557 2318 2334 2350 2366 2382 2398 2':1:14 2430 2446 2462 2478 2494 2510 2526 2542 2558 2319 2335 2351 2367 2383 2399 2415 2431 2447 2463 2479 2495 2511 2527 2543 2559 Appendix G. Hexadecimal Tables G-3 AO_ AL A2_ A3_ A4_ A5_ A6_ A7_ A8_ A9_ AA_ AB_ AC_ AD_ AE_ AF_ BO_ BL B2_ B3_ B4_ B5_ B6_ B7_ B8_ B9_ BA_ BB_ BC_ BD_ BE_ BF_ CO_ CL C2_ C3_ C4_ C5_ C6_ C7_ C8_ C9_ CA_ CB_ CC_ CD_ CE_ CF_ DO_ DL D2_ D3_ D4_ D5_ D6_ D7_ D8_ D9_ DA_ DB_ DC_ DD_ DE_ DF - G-4 0 1 2 3 4 5 6 7 8 9 A B C D E F 2560 2576 2592 2608 2624 2640 2656 2672 2688 2704 2720 2736 2752 2768 2784 2800 2561 2577 2593 2609 2625 2641 2657 2673 2689 2705 2721 2737 2753 2769 2785 2801 2562 2578 2594 2610 2626. 2642 2658 2674 2690 2706 2722 2738 2754 2770 2786 2802 2563 2579 2595 2611 2627 2643 2659 2675 2691 2707 2723 2739 2755 2771 2787 2803 2564 2580 2596 2612 2628 2644 2660 2676 2692 2708 2724 27.40 2756 2772 2788 28Q4 2565 2581 2597 2613 2629 2645 2661 2677 2693 2709 2725 2741 2757 2773 2789 2805 2566 2582 2598 2614 2630 2646 2662 2678 2694 2710 2726 2742 2758 2774 2790 2806 2567 2583 2599. 2615 2631 2647 2663 2679 2695 2711 2727 2743 2759 2775 2791 2807 2568 2584 2600 2616 2632 2648 2664 2680 2696 2712 2728 2744 2760 2776 2792 2808 2569 2585 2601 2617 2633 2649 2665 2681 2697 2713 2729 2745 2761 2777 2793 2809 2570 2586 2602 2618 2634 2650 2666 2682 2698 2714 2730 2746 2762 2778 2794 2810 2571 2587 2603 2619 2635 2651 2667 2683 2699 2715 2731 2747 2763 2779 2795 2811 2572 2588 2604 2620 2636 2652 2668 2684 2700 2716 2732 2748 2764 2780 2796 2812 2573 2589 2605 2621 2637 2653 2669 2685 2701 2717 2733 2749 2765 2781 2797 2813 2574 2590 2606 2622 2638 2654 2670 2686 2702 2718 2734 2750 2766 2782 2798 2814 2575 2591 2607 2623 2639 2655 2671 2687 2703 2719 2735 2751 2767 2783 2799 2815 2816 2832 2848 2864 2880 2896 2912 2928 2944 2960 2976 2992 3008 3024 3040 3056 2817 2818 2833 2834 2849 2850 2865 2866 2881 2882 2897 2898 2913 2914 2929 2930 2945 . 2946 2961 2962 2977 2978 2993 2994 3009 3010 3025 3026 3041 3042 3057 3058 2819 2835 2851 2867 2883 2899 2915 2931 2947 2963 2979 2995 3011 3027 3043 3059 2820 2836 2852 2868 2884 2900 2916 2932 2948 2964 2980 2996 3012 3028 3044 3060 2821 2837 2853 2869 2885 2901 2917 2933 2949 2965 2981 2997 3013 3029 3045 3061 2822 2838 2854 2870 2886 2902 2918 2934 2950 2966 2982 2998 3014 3030 3046 3062 2823 2839 2855 2871 2887 2903 2919 2935 2951 2967 2983 2999 3015 3031 3047 3063 2824 2840 2856 2872 2888 2904 2920 2936 2952 2968 2984 3000 3016 3032 3048 3064 2825 2841 2857 2873 2889 2905 2921 2937 2953 2969 2985 3001 3017 3033 3049 3065 2826 2842 2858 2874 2890 2906 2922 2938 2954 2970 2986 3002 3018 3034 3050 3066 2827 2843 2859 2875 2891 2907 2923 '2939 2955 2971 2987 3003 3019 3035 3051 3067 2828 ·2829 2830 2844 2845 2846 2860 2861 2862 2876 2877 2878 2892 2893 2894 2908 2909 2910 2924 2925 2926 2940 2941 2942 2956 2957 2958 2972 2973 2974 2988 2989 2990 3004 3005 3006 3020 3021 . 3022 3036 3037 3038 3052 3053 3054 3068 3069 3070 2831 2847 2863 2879 2895 2911 2927 2943 2959 2975 2991 3007 3023 3039 3055 3071 0 1 2 3 4 5 6 7 8 9 A B C D E F 3072 3088 3104 3120 3136 3152 3168 3184 3200 3216 3232 3248 3264 3280 3296 3312 3073 3089 3105 3121 3137 3153 3169 3185 3201 3217 3233 3249 3265 3281 3297 3313 3074 3090 3106 3122 3138 3154 3170 3186 3202 3218 3234 3250 3266 3282 3298 3314 3075 3091 3107 3123 3139 3155 3171 3187 3203 3219 3235 3251 3267 3283 3299 3315 3076 3092 3108 3124 3140 3156 3172 3188 3204 3220 3236 3252 3268 3284 3300 3316 3077 3093 3109 3125 3141 3157 3173 3189 3205 3221 3237 3253 3269 3285 3301 3317 3078 3094 3110 3126 3142 3158 3174 3190 3206 3222 3238 3254 3270 3286 3302 3318 3079 3095 3111 3127 3143 3159 3175 3191 3207 3223 3239 3255 3271 3287 3303 3319 3080 3096 3112 3128 3144 3160 3176 3192 3208 3224 3240 3256 3272 3288 3304 3320 3081 3097 3113 3129 3145 3161 3177 3193 3209 3225 3241 3257 3273 3289 3305 3321 3082 3098 3114 3130 3146 3162 3178 3194 3210 3226 3242 3258 3274 3290 3306 3322 3083 3099 3115 3131 3147 3163 3179 3195 3211 3227 3243 3259 3275 3291 3307 3323 3084 3100 3116 3132 3148 3164 3180 3196 3212 3228 3244 3260 3276 3292 3308 3324 3085 3101 3117 3133 3149 3165 3181 3197 3213 3229 3245 3261 3277 3293 3309 3325 3086 3102 3118 3134 3150 3166 3182 3198 3214 3230 3246 3262 3278 3294 3310 3326 3087 3103 3119 3135 3151 3167 3183 3199 3215 3231 3247 3263 3279 3295 3311 3327 3328 3344 3360 3376 3392 3-408 3424 3440 3456 3472 3488 3504 3520 3536 3552 3568 3329 3345 3361 3377 3393 3409 3425 3441 3457 3473 3489 3505 3521 3537 3553 3569 3330 3346 3362 3378 3394 3410 3426 3442 3458 3474 3490 3506 3522 3538 3554 3570 3331 3347 3363 3379 3395 3411 3427 3443 3459 3475 3491 3507 3523 3539 3555 3571 3332 3348 3364 3380 3396 3412 3428 3444 3460 3476 3492 3508 3524 3540 3556 3572 3333 3349 3365 3381 3397 3413 3429 3445 3461 3477 3493 3509 3525 3541 3557 3573 3334 3335 3350 3351 3366 3367 3382 3383 3398 3399 3414 3415 3430 3431 3446 .3447 3462 3463 3478 3479 3494 3495 3510 3511 3526 3527 3542 3543 3558 3559 3574 3575 3336 3352 3368 3384 3400 3416 3432 3448 3464 3480 3496 3512 3528 3.544 3560 3576 3337 3353 3369 3385 3401 3417 3433 3449 3465 3481 3497 3513 3529 3545 3561 3577 3338 3354 3370 3386 3402 3418 3434 3450 3466 3482 3498 3514 3530 3546 3562 3578 3339 3355 3371 3387 3403 3419 3435 3451 3467 3483 3499 3515 3531 3547 3563 3579 3340 3356 3372 3388 3404 3420 3436 3452 3468 3484 3500 3516 3532 3548 3564 3580 3341 3357 3373 3389 3405 3421 3437 3453 3469 3485 3501 3517 3533 3549 3565 3581 3342 3358 3374 3390 3406 3422 3438 3454 3470 3486 3502 3518 3534 3550 3566 3582 3343 3359 3375 3391 3407 3423 3439 3455 3471 3487 3503 3519 3535 3551 3567 3583 ESAj370 Principles of Operation 0 1 EO_ 3584 3585 El_ 3600 3601 E2_ 3616 3617 E3_ 3632 3633 E4_ 3648 3649 E5_ 3664 3665 E6_ 3680 3681 E7_ 3696 3697 E8_ 3712 3713 E9_ 3728 3729 EA- 3744 3745 EB_ 3760 3761 EC_ 3776 3777 ED_ 3792 3793 EE_ 3808 3809 EF_ 3824 3825 FO_ 3840 3841 Fl_ 3856 3857 F2_ 3872 3873' F3_ 3888 3889 F4_ 3904 3905 F5_ 3920 3921 F6_ 3936 3937 F7_ 3952 3953 F8_ 3968 3969 F9_ 3984 3985 FA_ 4000 4001 FB_ 4016 4017 FC_ 4032 '4033 FD_ 4048 4049 FE_ 4064 4065 FF_ 4080 4081 2 3 4 5 6 7 8 9 A B C D E F 3586 3602 3618 3634 3650 3666 3682 3698 3714 3730 3746 3762 3778 3794 3810 3826 3587 3603 3619 3635 3651 3667 3683 3699 3715 3731 3747 3763 3779 3795 3811 3827. 3588 3604 3620 3636 3652 3668 3684 3700 3716 3732 3748 3764 3780 3796 3812 3828 3589 3605 3621 3637 3653 3669 3685 3701 3717 3733 3749 3765 3781 3797 3813 3829 3590 3606 3622 3638 3654 3670 3686 3702 3718 3734 3750 3766 3782 3798 3814 3830 3591 3607 3623 3639 3655 3671 3687 3703 3719 3735 3751 3767 3783 3799 3815 3831 3592 3608 3624 3640 3594 3610 3626 3658 3674 3690 3706 3722 3738 3754 3770 3786 3802 3818 3834 3595 3611 3627 3643 3659 3675 3691 3707 3723 3739 3755 3771 3787 3803 3819 3835 3596 3612 3628 3644 3672 3688 3704 3720 3736 3752 3768 3784 3800 3816 3832 3593 3609 3625 3641 3657 3673 3689 3705 3721 3737 3753 3769 3785 3801 3817 3833 3676 3692 3708 3724 3740 3756 3772 3788 3804 3820 3836 3597 3613 3629 3645 3661 3677 3693 3709 3725 3741 3757 3773 3789 3805 3821 3837 3598 3614 3630 3646 3662 3678 3694 3710 3726 3742 3758 3774 3790 3806 3822 3838 3599 3615 3631 3647 3663 3679 3695 3711 3727 3743 3759 3775 3791 3807 3823 3839 3842 3858 3874 3890 3906 3922 3938 3954 3970 3986 4002 4018 4034 4050 4066 4082 3843 3859 3875 3891 3907 3923 3939 3955 3971 3987 4003 4019 4035 4051 4067 4083 3844 3860 3876 3892 3908 3924 3940 3956 3972 3988 4004 4020 4036 4052 4068 4084 3845 3861 3877 3893 3909 3925 3941 3957 3973 3989 4005 4021 4037 4053 4069 4085 3846 3862 3878 3894 3910 3926 3942 3958 3974 3990 4006 4022 4038 4054 4070 4086 3847 3863 3879 3895 3911 3927 3943 3959 3975 3991 4007 4023 4039 4055 4071 4087 3848 3864 3880 3896 3912 3928 3944 3960 3976 3992 4008 4024 4040 4056 4072 4088 3849 3865 3881 3897 3913 3929 3945 3961 3977 3993 4009 4025 4041 4057 4073 4089 3850 3866 3882 3898 3914 3930 3946 3962 3978 3994 4010 4026 4042 4058 4074 4090 3851 3867 3883 3899 3915 3931 3947 3963 3979 3995 4011 4027 4043 4059 4075 4091 3852 3868 3884 3900 3916 3932 3948 3964 3980 3996 4012 4028 4044 4060 4076 4092 3853 3869 3885 3901 3917 3933 3949 3965 3981 3997 4013 4029 4045 4061 4077 4093 3854 3870 3886 3902 3918 3934 3950 3966 3982 3998 4014 4030 4046 4062 4078 4094 3855 3871 3887 3903 3919 3935 3951 3967 3983 3999 4015 4031 4047 4063 4079 4095 3656 36~2 3660 Appendix G. Hexadecimal Tables G-5 Conversion Table: Hexadecimal and Decima/Integers HAlfWORD HALFWORD BYTE BYTE BITS: 0123 4567 BYTE 0123 Hex Decimal Hex Decimal Hex Decimal Hex Decimal 0 1 2 3 4 5 6 7 8 9 A B C 0 'E F 0 268,435 456 53";870,912 ROS, 306,368 1,073,741 824 1,342, In ,280 1,610,612,736 1,879,048,192 2,1.47,483,648 2,415,'11'1,104 2,684,354,560 2,952 790,016 3,221 225 472 3,489,660,928 3,758,096,384 4,026,531,840 0 0 16 m,216 33,554,432 50 331 648 67 108 864 83,886,080 100,663,296 117,440,512 134,217,728 150 994,944 167,n2,160 184,549,376 201,326 592 218 103 808 234,881,024 251,658,240 0 1 2 3 4 5 6 7 8 9 A B C 0 E F 0 1 048,576 2,097,152 3 145,728 4 194304 5,242,880 6,291,456 7 340,032 8,388,608 9,437,184 10485,760 11 534 336 12,582 912 13 631 488 14,680,064 15,728,640 0 1 • 2 3 4 5 6 7 8 9 A B C 0 E F 0 65,536 131,072 196,608 262,144 327,680 393,216 458,752 524,288 589,824 655,360 720,896 786 432 851,968 917,504 983,040 j 2 3 4 5 6 7 8 9 A B C 0 E F 6 7 8 1. Hex 0 1 2 3 4 5 6 7 8 9 A B C 0 ·E F 2. Repeat step I for the next (second from the left) position. 3. Repeat step 1 for the units (third from the left) position. 4. Add the numben selected from the table to form the decimal number. Convenion of Hexadecimal Value Decimal Hex 0 4,096 8,192 12,288 16384 20,480 24,576 28,672 32768 36 864 40 960 45 056 49 152 53248 57,344 61,440 0 1 2 3 4 5 6 7 8 9 A B C 0 E F Decimal 0 256 512 768 1 024 1,280 1,536 1,792 2,048 2,304 2,560 2816 3,072 3,328 3,584 3,840 0123 Hex 3 2. Using the remainder from step I (c) repeat all ofstep 1 to develop the second position of the hexadecimal (and a remainder) . 3. Using the remainder from step 2 repeat all ofstep 1 to develop the units position of the hexadecimal. 4. Combine terms to form the hexadecimal number. G-6 0 V6 112 128 144 160 176 192 1 1 2 3 4 5 6 7 8 9 A 2 J 4 5 6 7 8 9 10 11 12 13 14 15 8 C 0 E F 208 224 240 2 034 1 1. 0 3328 2. 3 48 3. 4 4 HEXADECIMAL TO DECIMAL Successive cumulative multiplication from left to right, adding units position. Example: 03416 =338010 4. Decimal 0= 13 ..ill.. 3 3380 Convenion of Decimal Value 1 2 3 4 5 6 7 8 9 10 =A 11 = B 12 =C 13 =0 14 =E 15 =F j ESA/370 Principles of Operation lIT DECIMAL TO HEXADECIMAL 3380 Divide and collect the remainder in reverse order. 1. 0 -3328 ---s2 2. 3 -48 --4 3. 4 -4 4. Hexadecimal = 1000 000016 = (l 07h6 o =+ 3 x16 3376 4= +4 3380 EXAMPLE 1 16 256 4096 65 536 1 048 576 16 m 216 268 435 456 4 294967 296 68 719 476 736 1 099 511 627 n6 17 592 186 044 416 281 474 976 710 656 4 503 599 627 370 496 72 OS7 594 037 927 936 \.1 152 921 504 606 846 976 v Decimal Values Decimal 208 (a) Select from the table the highest decimal number that is equal to or less than the number to be COi"lverted. (b) Record the hexadecimal of the column containing the selected number. (c) Subtract the selected decimal from the number to be converted. POWERS OF 16 TABLE Example: 268,435,456 10 = (2.68435456 x 108 )10 n 16n Hex 0 16 32 48 64 80 5 TO CONVERT DECIMAL TO HEXADECIMAL 1. 0 0 1 2 3 4 6 7 8 9 A B C 0 E F 4567 Decimal To convert integer numben greater than the capacity of table, use the techniques below: EXAMPLE Locate the column of decimal numben corresponding to the left-most digit or letter of the hexadecimal; select from this column and record the number that corresponds to the position of the hexadecimal digit or letter. 4567 4 5 TO CONVERT HEXADECIMAL TO DECIMAL BYTE 0123 4567 034 Conversion Table: Hexadecimal and Decimal Fractions HALFWORD BYTE BYTE 0123 BITS Hex .0 .1 .2 .3 Decimal Hex .0000 .00 .01 .0625 .1250 ;1875 .2500 .3125 .3750 .4375 .5000 .5625 .6250 .6875 .7500 .8125 .8750 .9375 .4 .5 .6 .7 .8 .9 .A .B .C .0 .E .F 4567 0123 Decimal .0000 .0039 .0078 .0117 .0156 .0195 .0234 .0273 .0312 .0351 .0390 .0429 .0468 .0507 .0546 .0585 .02 .03 .04 .05 .06 .07 .08 .09 .OA .OB .OC .00 .Of .OF 0000 0625 1250 1875 2500 3125 3750 4375 5000 5625 6250 6875 7500 8125 8750 9375 Hex .000 .001 .002 .003 .004 .005 .006 .007 .008 .009 :OOA .OOB .OOC .000 .OOE .OOF .0000 .0002 .0004 .0007 .0009 .0012 .0014 .0017 .0019 .0021 .0024 .0026 .0029 .0031 .0034 .0036 0000 4414 8828 3242 7656 2070 ··6484 0898 5312 9726 4140 8554 2968 7382 1796 6210 Find.A in position 1 0000 0625 1250 1875 2500 3125 3750 4375 5000 5625 6250 6875 7500 8125 8750 9375 Decimal Equivalent .0000 .0000 .0001 .0002 .0003 .0004 .0005 .0000 .0000 .0006 .0007 .0008 .0009 .000A .000B .000C .0000 .OOOE .000F .0000 .0000 .0000 .0000 .0001 .0001 .0001 .0001 .0001 .0001 .0001 .0002 .0002 0000 1525 3051 4577 6103 7629 9155 0681 2207 3732 5258 6784 8310 9836 1362 2888 0000 8789 7578 6367 5156 3945 2734 1523 0312 9101 7890 6679 5468 4257 3046 1835 0000 0625 T250 1875 2500 3125 3750 4375 5000 5625 6250 6875 7500 8125 8750 9375 4 To convert fractions beyond the capacity of table, use techniques below: TO CONVERT .ABC HEXADECIMAL TO DECIMAL Find .OB in position 2 Hex 3 2 1 4567 Decimal .6250 HEXADECIMAL FRACTION TO DECIMAL .0429 6875 Find .OOC in position 3 .0029 2968 7500 •ABC Hex is equal to .6708 9843 7500 Convert the hexadecimal fraction to its decimal equivalent using the same technique as for integer numben. Divide the results by 16n (n is the number of fraction positions) • Example: .8A7 = .54077110 8A7 16 163 TO CONVERT .13 DECIMAL TO HEXADECIMAL 1. Find .1250 next lowest to subtract .1300 -.1250 = .2Hex 2. Find .0039 0625 next lowest to .0050 0000 -.0039 0625 = .01 3. Find.OOO9 7656 2500 .00109375 0000 - .0009 7656 2500 = .004 4. Find .0001 0681 1523 4375 .0001 1718 7500 0000 -.0001 0681 1523 4375 = .0007 .0000 1037 5976 5625 = .2147Hex 5 •• 13 Decimal is approximately equal to _ _ _ _ _ _ _ -"'4 = 2215 10 = 4096 .540771 409612215.000000 DECIMAL FRACTION TO HEXADECIMAL Collect integer parts of product in the order of calculation. Example: .540810 = .8A716 .5408 x16 8 ~ (]J.6528 x16 A ~ [Q).4448 1 x16 7 . - 1].1168 Appendix G. Hexadecimal Tables G-7 Hexadecimal Addition and Subtraction Table Example: 6 + 2 = 8, 8 - 2 = 6, and 8 - 6 = 2 1 2 3 4 5 6 7 8 9 A 8 C 0 E F 1 02 03 04 05 06 07 08 09 OA 08 OC 00 OE OF 10 2 03 ,04 05 06 07 08 09 OA 08 OC OD OE OF 10 11 3 04 05 06 07 08 09 OA 08 OC OD OE OF 10 11 12 4 'OS 06 07 08 09 OA 08 OC OD _OE OF 10 11 12 13 5 06 07 08 09 OA 08 OC 00 'OE OF 10 11 12 13 14 6 07 08 09 OA 08 OC OD OE OF 10 11 12 13 14 15 7 08 09 OA 08 OC 00 OE OF 10 11 12 13 14 15 16 8 09 OA 08 OC 00 OE OF 10 11 12 13 14 15 16 17 9 OA 08 OC OD OE OF 10 11 12 13 14 15 16 17 18 A 08 OC 00 OE OF 10 11 12 13 14 15 16 17 18 19 8 OC 00 OE OF 10 11 12 13 14 15 16 17 18 19 lA C OD OE OF 10 11 12 13 14 15 16 17 18 19 lA 18 0 OE OF 10 11 12 13 14 15 16 17 18 19 lA 18 lC E OF 10 11 12 13 14 15 16 17 18 19 lA 18 lC 10 F 10 11 12 13 14 15 16 17 18 19 lA 18 lC 10 1E < Hexadecimal Multiplication Table Example: 2 x 4= 08, F x 2 = IE 1 2 3 4 5 6 7 8 9 A 8 C 0 E F 1 01 02 03 04 05 06 07 08 09 OA 08 OC 00 OE OF 2 02 04 06 08 OA OC OE 10 12 14 16 18 lA lC 1E 3 03 06 09 OC OF 12 15 18 18 IE 21 24 27 2A 20 4 04 08 OC 10 14 18 lC 20 24 28 2C 30 34 38 3C 5 05 OA OF 14 19 IE 23 28 20 32 37 3C 41 46 48 6 06 OC 12 18 1E 24 2A 30 36 3C 42 48 4E 54 SA 7 07 OE 15 lC 23 2A 31 38 3F 46 40 54 58 62 69 8 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 9 09 12 18 24 20 36 3F 48 51 SA 63 6C 75 7E 87 A OA 14 IE 28 32 3C 46 50 SA 64 6E 78 82 8C 96 8 08 16 21 2C 37 42 40 58 63 6E 79 84 8F 9A AS C OC 18 24 30 3C 48 54 60 6C 78 84 90 9C AS B4 0 00 lA 27 34 41 4E 58 68 75 82 8F 9C A9 86 C3 E OE lC 2A 38 46 54 62 70 7E 8C 9A AS 86 C4 02 F OF 1E 20 3C 48 SA 69 78 87 96 AS B4 C3 02 El G;;'S ESA/370 Principles of Operation Appendix H. . EBCDIC Chart Extended Binary-Coded-Decimal Interchange Code (EBCDIC) The 256-position EBCDIC table shows graphiccharacter, control-character, and formattingcharacter representations for EBCDIC. The bitposition numbers, bit patterns, hexadecimal representations, and card-hole patterns for these and other possible EBCDIC characters are also shown. To fmd the card-hole pattern for most characters, partition the table into four blocks, as follows: 1 3 2 4 Block 1: Zone punches at top of table; digit punches at left Block 2: Zone punches at bottom of table; digit punches at left Block 3: Zone punches at top of table; digit punches at right Block 4: Zone punches at bottom of table; digit punches at right Fifteen positions in the table are exceptions to the above arrangement. Each such position is indicated by a circled number in the upper right comer of the box for that position. The card-hole patterns for these positions are shown beneath the table. Bit-position numbers, bit patterns, and hexadecimal representations for these positions are found in the usual manner. The EBCDIC table shows 94 graphic-character positions. Some products have used an 88-character, 63-character, or 62-character subset of these graphic characters. The 94-character set consists of all graphic characters shown in the EBCDIC table. This character set can be used for interchange with other systems; those systems may use codes, other than EBCDIC, which have 94 graphic characters. An 88-character set that has been used consists of the 94-character set with the graphic characters at 6A, 79, AI, CO, DO, and EO hex omitted. This character set has been used for 44- key keyboard applications which require both uppercase and lowercase alphabetic characters. A 63-character set that has been used consists of the 94-character set with the lowercase alphabetic characters omitted and with the graphic characters at 6A, 79, AI, CO, and DO hex omitted. This character set has been used for interchange with other systems; those systems may have used codes, other than EBCDIC, which have 63 graphic characters. A 62-character set that has been used consists of the 63-character set with the graphic character at EO hex omitted. This character set has been used for 44-key keyboard applications which do not require lowercase alphabetic characters. Thirteen positions (4A, 4F, 5A, 5B, 5F, 6A, 79, 7B, 7C, AI, CO, DO; and EO hex) are defmed in the table as Data Processing National Use positions. Each such position contains a shaded triangle in the top left comer of the box for that position. The graphic characters provided in these positions on printing and display devices may differ from one language to another or from one country to another. The characters provided for use in dataprocessing applications by the English (U.S.) version of EBCDIC are shown in the table. Appendix H. EBCDIC Chart 8-1 The other graphic characters shown in the EBCDIC table are provided for data-processing applications in the English (U.S.) version of EBCDIC and in additional versions of EBCDIC in other languages Products which use a Latin-based alphabet. designed for data-processing applications in a language which does not use a Latin-based alphabet support character sets meeting the particular requirements of that language. Character Bit Pattern Type Hex SEl R a Control Character Special Graphic Upper Case lower Case Control Character, function not yet assigned 00000100 01 10 1100 1101 1001 ·10000001 00 II 0000 .. 04 6C 09 81 30 . Bit Positions 01 234567 8-2 ESAj370 Principles of Operation Some examples of the use of the shown in the following figure: Hole Pattern Zone Punches 0/0 Word-processing products·normally support a character set slightly different from the one shown in the table. Additionally, a number of application areas (such as printing and publishing, magnetic-ink character recognition, and some programming languages) also require unique character-set support. IDigit Punches 12 - 9'- 4 0-8-4 11,- 9 12 - 01- 1 12 - 11 - 0 - 9,- 8 - 1 ,I EBCDIC table are ,.... :~ Q ~ ...,' 1 .' ~ ; ~ ~ ii ~ ~ ~ III RSP DC2 FS DC3 WUS IR C RES{ EN BYP/ INP PP D K SYN 12-0-9-8-1 12-11-9-8-1 11-0-9-8-1 U Nl IF TRN N V BS ETB NBS 0 W POC ESC EOT G CAN SA SBS H EM SFE IT UBS SM/SW RFF CUI CSP CU3 IFS MFA DC4 IGS ENQ NAK IRS ACK X Q Y SHY < @ % > CD 12-11-0-9-8-1 CD CD No Punches 0 CD 0' 12 Control Character Representations ACK Acknowledge BEL Bell 8S Backspace BYP/INP Bypass/lnhibit Presentation Cancel CAN Carriage Return CR Control Sequence Prefix CSP CUI Cu~tamer Use 1 Custamer Use 3 CU3 Device Control 1 DCl Device Control 2 DC2 Device Control 3 DC3 Device Control 4 DC4 DEL Delete Data Link Escape OLE OS Digit Select EM End of Medium ENQ Enquiry EO Eight Ones End of Transmission EOT ESC EscaDe End of Transmission Block ETB 4 Z S;ard Hale Patterns '? # @ { } , Comma Percent Underscore Greater-than Sign Question Mark Grave Accent Colon Number Sign At Sign Prime, Apastrophe Equal Sign. Quotation Mark Tilde Opening Brace Closing Brace Reverse Slant Appendix H. EBCDIC Chart H-3 Index A A (AD D) binary instruction 7-8 absolute address 3-4 absolute storage 3-4 access-control bits in storage key 3-7 access exceptions 6-29,6-34 priority of 6-34 recognition of 6-29 access key 3-8 for channel-program execution 3-8,15-21 for channel-subsystem monitoring 3-8 for CPU 3-8 access list 5-39 (See also access-list entry) accessing capability, revocation of 5-33 allocation and invalidation of entries in 5-30 authorizing the use of entries in 5-31 concepts 5-29 designation (ALD) 5-38 length (ALL) 5-38 origin (ALO) 5-38 access-list entry (ALE) 5-39 authorization index (ALEAX) 5-39 number (See ALEN) sequence exception 6-16 as an access exception 6-29 sequence number (ALESN) in ALE 5-39 in ALET 5-36 token (See ALET) access-register mode 3-24 access-register translation (ART) 5-35 as part of LOAD REAL ADDRESS, TEST ACCESS, and TEST PROTECfION 5-41 introduction to 5-29 lookaside buffer (See ALB) process 5-41 sequence of table fetches 5-71 tables 5-37 access registers D-l,2-3 designation of 5-28 functions 5-27 instructions for use of 5-34 save areas for 3-42 validity bit for 11-21 access to storage 5-65 (See also reference) active device 16-15 subchannel 16-15 active allegiance 15-11 active communication 15-11 activity-control field (SCSW) 16-13 following TEST SUBCHANNEL 14-17 AD (ADD NORMALIZED) instruction 9-7 example A-38 ADD (A,AR) binary instructions 7-8 ADD DECIMAL (AP) instruction 8-5 example A-33 ADD HALFWORD (AH) instruction 7-8 example A-8 ADD LOGICAL (AL,ALR) instructions 7-9 ADD NORMALIZED (AD,ADR,AE,AER,AXR) instructions 9-7 example A-38 ADD UNNORMALIZED (AU,AUR,AW,AWR) instructions 9-8 example A-39 address 3-2 absolute 3-4 arithmetic 3-5,5-6 unsigned binary 7-3 backward stack-entry 5-58 base (See base address) branch (See branch address) channel-program (See channel-program address) comparison 12-1 controls for 12-1 effect on CPU state 4-2 CPU (See CPU address) data (I/O) (See data address) effective (See effective address) failing-storage (See failing-storage address) format 3-2 forward-section-header 5-58 generation 5-5 for storage addressing 3-5 I/O 13-5 instruction (See instruction address) invalid 6-14 logical (See logical address) numbering of for byte locations 3-2 PER (See PER address) prefixing (See prefix) primary virtual (See primary virtual address) real 3-4 secondary virtual (See secondary virtual address) size of 3-5 controlled by addressing mode 5-5 storage 3-2 summary information 3-35 translation (See dynamic address translation, prefix) types 3-3 virtual 3-4 wraparound (See wraparound) 24-bit and 31-bit E-l,3-5 in branch-address generation 5-7 in operand-address generation 5-6 31-bit real and absolute E-l address-limit checking (I/O) 17-12 effect of I/O-system reset on 17-8 limit mode (bits in PM CW) 15-2 address-limit-checking control (I/O) 15-22,16-11 used for IPL 17-10 address space 3-13 AR-specified 5-27 changing of 3-13 Index X-I control bits control bit 5-54 in PSW 4-5 use in address translation 3-24 created by DAT 3-23 number (See ASN) address-space-function (ASF) control bit 5-35 use in ASN translation 3-15 use in PC-number translation 5-21 addressing exception 6-14 as an access exception 6-29,6-34 addressing mode 5-5 bit in entry-table entry 5-23 bit in linkage-stack state entry 5-60 bit in PSW 4-6 effect on address size 3-5 effect on operand-address generation 5-6 effect on sequential instruction-address generation 5-6 effect on wraparound 3-5 in branch-address generation 5-7 in examples A-8 in operand-address generation 5-6 set by BRANCH AND SAVE AND SET MODE instruction 7-11 set by BRANCH AND SET MODE instruction 7-12 use of 5-10 ADR (ADD NORMALIZED) instruction 9-7 AE (ADD NORMALIZED) instruction 9-7 example A-38 AER (ADD NORMALIZED) instruction 9-7 AFT (ASN first table) 3-15 AFTE (ASN-first-table entry) 3-15 AFTO (ASN-first-table origin) 3-15 AFX (ASN-first-table index) 3-14 invalid bit 3-15 translation exception 6-16 AH (ADD HALFWORD) instruction 7-8 example A-8 AKM (authorization key mask) 5-23 AL (ADD LOGICAL) instruction 7-9 ALB (ART -lookaside buffer) 5-46 entry clearing of 5-48 effect of translation changes on 5-48 usable state 5-48 ALD (access-list designation) 5-38 ALE (See access-list entry) ALEAX (access-list-entry authorization index) 5-39 ALEN (access-list-entry number) 5-37 invalid bit 5-39 translation exception 6-16 as an access exception 6-29 alert (class of machine-check condition) 11-12 alert interruption condition (I/O) 16-4 alert-status bit (I/O) 16-16 ALESN (access-list-entry sequence number) in ALE 5-39 in ALET 5-36 ALET (access-list-entry token) 5-30,5-36 specification exception 6-16 as an access exception 6-29 x -2 ESA/370 Principles of Operation ALL (access-list length) 5-38 allegiance active 15-11 channel-path 15-10 dedicated 15-11 effect on CLEAR SUBCHANNEL of 15-10 working 15-11 allowed interruptions 6-6 ALO (access-list origin) 5-38 ALR (ADD LOGICAL) instruction 7-9 alter-and-display controls 12-2 alteration general-register (PER event) 4-17 storage (PER event) 4-17 AND (N,NC,NI,NR) instructions 7-9 examples A-8 ·AP (ADD DECIMAL) instruction 8-5 example A-33 AR (ADD) binary instruction 7-8 AR -specified (access-register-specified) address space 3-13,5-27 AR-specified (access-register-specified) virtual address 3-4 effective segment-table designation for 3-28 architectural mode 1-1 indication of 12-2 selection of by IML controls 12-2 selection of by manual controls 12-2 architecture, compatibility 1-3 arithmetic address (See address arithmetic) binary 7-3 examples A -2 decimal 8-2 examples A-5,A-33 floating-point 9-1 examples A-5,A-38 logical (unsigned binary) 7-3 examples A-4 ART (See access-register translation) ART -lookaside buffer (See ALB) ASCII character code, handled by architecture v ASF-control bit (See address-space-function-control bit) ASN (address-space number) 3-13 authorization 3-19 first table (AFT) 3-15 index (AFX) 3-14 origin (AFTO) 3':15 in entry-table entry 5-23 second table (AST) index (ASX) 3-14 origin (ASTO) 3-15 second-table entry (ASTE) address 5-54 address. in ALE 5-39 address, in ETE 5-23 basic (16-byte) 3-16 extended (64-byte) 5-40 primary (PASTE) 5-21 pseudo 3-14 sequence exception 6-17 sequence exception as an access exception 6-29 sequence number (ASTESN) 5-39,5-41 validity exception 6-17 validity exception as an access exception 6-29 trace-control bit 4-9 translation 3-14 exceptions 6-38 specification exception 6-16 specification exception as an access· exception 6-29 translation-control bit 3-15,5-17 assembler language A-7 instruction formats in (See instruction lists and page numbers in Appendix B) assigned storage locations 3-39 comparison of ESA/370 with 370-XA 0-3 comparison of 370-XA with System/370 E-6 AST (See ASN seqond table) AST entry (See ASN-second-table entry) ASTE (See ASN-second-table entry) ASTESN (AST-entry sequence number) in ALE 5-39 in ASTE 5-41 ASTO (ASN-second-table origin) 3-15 ASX (ASN-second-table index) 3-14 invalid bit 3-16 use in ART 5-40 translation exception 6-17 AT (See authority table) ATL (authority-table length) 3-16 use in ART 5-40 ATO (authority-table origin) 3-16 use in ART 5-40 attached ART-table entry 5-47 attached segment-table or page-table entry 3-32 attachment of I/O devices 13-3 attention (device status) 16-23 AU (ADD UNNORMALIZED) instruction 9-8 example A-39 AUR (ADD UNNORMALIZED) instruction 9-8 authority table (AT) 5-17 designation 3-16,5-40 length 3-16,5-40 origin 3-16,5-40 authorization ASN 3-19 index (AX) 3-20,5-17 key mask (AKM) 5-23 mechanisms 5-15 summary of 5-19 testing of 5-52 auxiliary storage 3-1,3-22 availability (characteristic of a system) 1-4 A W (ADD UNNORMALIZED) instruction 9-8 AWR (ADD UNNORMALIZED) instruction 9-8 AX (authorization index) 5-17 AXR (ADD NORMALIZED) instruction 9-7 B B field of instruction 5-6 backed -up bit (machine-check condition) 11-18 backup, processing (synchronous machine-check condition) 11-18 backward stack-entry address 5-58 backward stack-entry validity bit 5-58 BAKR (BRANCH AND STACK) instruction 10-5 examples A-I 0 BAL (BRANCH AND LINK) instruction 7-10 examples A-8 BALR (BRANCH AND LINK) instruction 7-10 examples A-8 BAS (BRANCH AND SAVE) instruction 7-11 example A-8 base address 5-6 register for 2-3 basic AST entry 3-16 basic entry-table entry 5-22 basic I/O functions 15-1 basic operator facilities 12-1 basic PROGRAM CALL 5-50,10-35 basic sense command 15-37 BASR(BRANCH AND SAVE) instruction 7-11 example A-8 BASSM (BRANCH AND SAVE AND SET MODE) instruction 7 -11 example A-8 BC (BRANCH ON CONDITION) instruction 7-12 example A -12 BCR (BRANCH ON CONDITION) instruction 7-12 BCf (BRANCH ON COUNT) instruction 7-13 example A -12 BCfR (D-RANCH ON COUNT) instruction 7-13 example A -12 bimodal addressing E-l,5-5 (See also addressing mode) binary (See also fixed point) arithmetic 7-3 examples A -2 negative zero 7-2 number representation 7-2 examples A -2 overflow 7-3 example A-2 sign bit 7-2 binary-to-decimal conversion 7-24 example A-18 bit 3-2 numbering of within a group of bytes 3-2 block -concurrent storage references 5-74 block of I/O data 15-21 block of storage 3-4 (See also page) testing for usability of 10-69 borrow 7-49 boundary alignment 3-3 for instructions 5-3 branch address 5-7 in linkage-stack state entry 5-60 in trace entry 4-11 BRANCH AND LINK (BAL,BALR) instructions 7-10 examples A-8 BRANCH AND SAVE (BAS,BASR) instructions 7-11 examples A-8 Index X-3 BRANCH AND SAVE AND SET MODE (BASSM) instruction 7-11 examples A-8 BRANCH AND SET MODE (BSM) instruction 7-12 examples A-8 BRANCH AND STACK (BAKR) instruction 10-5 examples A-I 0 BRANCH ON CONDITION (BC,BCR) instructions 7-12 example A -12 BRANCH ON COUNT (BCT,BCTR) instructions 7-13 example A -12 BRANCH ON INDEX HIGH (BXH) instruction 7-14 examples A -13 BRANCH ON INDEX LOW OR EQUAL (BXLE) instruction 7-14 examples A -14 branch state entry 5-59,10-5 branch -trace-control bit 4-9 branching branch-address generation 5-7 in a channel program (See TI C) to perform decision making, loop control, and subroutine linkage 5-7 using the linkage stack 5-51 BSM (BRANCH AND SET MODE) instruction 7-12 example A-8 buffer storage (cache) 3-1 burst mode (channel-path operation) 13-3 bus-out check (bit in I/O sense data) 15-38 busy as device status (I/O) 16-25 control unit 16-24,16-25 in I/O operations 13-7 in SIGNAL PROCESSOR 4-36 BXH (BRANCH ON INDEX HIGH) instruction 7-14 examples A -13 BXLE (BRANCH ON INDEX LOW OR EQUAL) instruction 7-14 examples A -14 bypassing POST and WAIT A-44 byte 3-2 numbering of in storage 3-2 byte index (BX) 3-23 byte-multiplex mode (channel-path operation) 13-3 C C (COMPARE) binary instruction 7-15 cache 3-1 capability list 5-33 carry 7-3 CBC (checking-block code) 11-2 invalid 11-2 in registers 11-10 in storage 11-6 in storage keys 11-7 near-valid 11-2 valid 11-2 CCC (channel-control check) 16-31 CCW (channel-command word) 15-23 address of 15-22,16-18 X-4 ESA/370 Principles of Operation byte count in 15-24 chaining 15-26 check (in subchannellogout) 16-37 command codes (See commands) contents of 15-23 current 15-23 designation of storage area in 15-24,15-25 format control 15-21,16-10 used for IPL 17-10 format-O and format-l 15-23 IDA flag in 15-24 in IPL, assigned storage locations for 3-39 indirect data addressing used in 13-7,15-31 invalid format of 16-30 invalid specification of 16-29 PCI flag in 15-24 prefetch control in 15-21,16-11 used for IPL 17-10 prefetching 15-28 retry of (See command retry) role in I/O operations of 13-6 skip flag in 15-24 suspend flag in 15-24 CD (COMPARE) floating-point instruction 9-9 CDR (COMPARE) floating-point instruction 9-9 examples A-39 CDS (COMPARE DOUBLE AND SWAP) instruction 7-19 examples A -43 CE (COMPARE) floating-point instruction 9-9 central processing unit (See CPU) CER (COMPARE) floating-point instruction 9-9 CFC (COMPARE AND FORM CODEWORD) instruction 7-15 CH (COMPARE HALFWORD) instruction 7-20 example A -15 chaining check (subchannel status) 16-33 chaining of CCWs 15-26 command (See command chaining of CCWs) data (See data chaining of CCWs) chaining of CRWs 17-14,17-15 change bit in storage key 3-7 change recording 3-11 channel-command word (See CCW) channel commands (See commands) channel-control check (sub channel status) 16-31 channel-data check (sub channel status) 16-30 channel end (device status) 16-25 channel path 13-1,13-3 active allegiance for 15-11 available for selection 15-12 dedicated allegiance for 15-11 effect of I/O-system reset on 17-8 masks in SCHIB (See LPM, LPUM, PAM, PIM, PNOM, POM) multipath mode of 15-3,15-20 not operational 16-12 storing of status for 14-14 type of 13-5 working allegiance for 15-11 channel-path identifier (See CHPID) channel-path reset 17-6 effect of I/O-system reset on 17-8 channel-path-reset function 15-43 completion of 15-44 initiation by RESET CHANNEL PATH 14-7 reset signal issued as part of 17-6 signaling for 15-43 channel-path -status word 14-14 channel program 15-23 branching in (See TIC) execution of 13-6,15-19 resumption of 14-9 sequence altered by status modifier 16-23 suspension of 13-8,15-32 serialization 5-77 suspend control for 15-21 channel-program address 15-22,16-18 field-validity flag for in IRB 16-38 used for IPL 17-10 channel report 17-14 generated as a result of RCHP 14-7 channel report pending 11-17,1 7-14 effect of I/O-system reset on 17-8 subclass-mask bit for 11-24 channel-report word (See CRW) channel subsystem 2-6,13-2 addressing used in 13-5 damage 11-17 effect of I/O-system reset on 17-6 effect of power-on reset on 4-32 channel-subsystem monitoring 17-1 effect of I/O-system reset on 17-8 channel-subsystem recovery 11-4,17-13 channel-subsystem timer 17-2 effect of I/O-system reset on 17-9 channel-subsystem timing 17 -1 channel-subsystem timing-facility bit (in PMCW) 15-4 channel-to-channel adapter, publication referenced v characteristic (of floating-point number) 9-1 characters, represented by eight-bit code v check bits 3-2,11-2 check stop 4-2,11-11 as signal-processor status 4-38 during manual operation 12-1 effect on CPU timer 4-26 entering of 11-13 indicator 12-2 malfunction alert for 6-11 system 11-11 checking block 11-2 checking-block code (See CBC) checkpoint 11-2 checkpoint synchronization 11-3 action 11-4 operations 11-3 CHPID (channel-path identifier) 13-5 in PMCW 15-7 used in RESET CHANNEL PATH 14-7 CL (COMPARE LOGICAL) instruction 7-21 CLC (COMPARE LOGICAL) instruction 7-21 example A-IS CLCL (COMPARE LOGICAL LONG) instruction 7-22 example A-I 7 clear function 15-13 bit in SCSW for 16-13 completion of 15-14 initiated by CLEAR SUBCHANNEL 14-4 path management for 15-13 pending 16-15 signaling for 15-14 sub channel modification by 15-13 clear reset 4-31 clear signal 17-5 issued as part of clear function 15-14 CLEAR SUBCHANNEL (CSCH) instruction 14-4 (See also clear function) effect on device status of 15-14 function initiated by 15-13 use of after RESET CHANNEL PATH 14-8 clearing operation by clear-reset function 4-31 by load-clear key 12-3 by system-reset-clear key 12-4 by TEST BLOCK instruction 10-69 CLI (COMPARE LOGICAL) instruction 7-21 example A -16 CLM (COMPARE LOGICAL CHARACTERS UNDER MASK) instruction 7-21 example A -16 clock (See TOD clock) clock comparator 4-25 external interruption 6-10 save areas for 3-42 validity bit for 11-21 clock unit 4-24CLR (COMPARE LOGICAL) instruction 7-21 example A -16 code ASCII, handled by architecture v checking-block (See CBC) command (in CCW) (See command code in CCW) condition (See condition code) decimal digit and sign 8-2 deferred condition (I/O) 16-8 EBCDIC chart for H-l handled by architecture v eight-bit, handled by architecture v error-recovery (I/O) 17-15 exception -extension 6-14 external-damage 11-22 validity bit for 11-21 I/O-interruption subclass 15-2 instruction-length (See ILC) interruption (See interruption code) linkage-stack-entry type 5-57 monitor (See monitor code) operation 5-2 PER (See PER code) reporting-source (I/O) 17-15 storage-access (in subchannellogout) 16-38 version 10-64 codeword (for sorting operations) 7-15 command chaining of CCWs 15-29 effect of status modifier on 15-29 flag in CCW for 15-24 overview of 13-8 Index X-5 \ command code in CCW 15-24 (See also commands) invalid 16-29 command reject (bit in I/O sense data) 15-38 command retry 15-41 effect on PCI of 15-31 status modifier used for 16-23 commands (I/O) 15-24,15-34 control 15-36 initial read (for IPL) 15-35 no-operation (control) 15-37 read 15-35 read backward 15-36 sense 15-37 sense ID 15-39 transfer in channel 15-40 write 15-35 common-segment bit 3-26 COMPARE (C,CR) binary instructions 7-15 COMPARE (CD,CDR,CE,CER) floating-point instructions 9-9 examples A-39 COMPARE AND FORM CODEWORD (CFC) instruction 7-15 COMPARE AND SWAP (CS) instruction 7-19 examples A -43 COMPARE DECIMAL (CP) instruction 8-5 example A-33 COMPARE DOUBLE AND SWAP (CDS) instruction 7-19 examples A -43 COMPARE HALFWORD (CH) instruction 7-20 example A -15 COMPARE LOGICAL (CL,CLC,CLI,CLR) instructions 7-21 examples A -15 COMPARE LOGICAL CHARACfERS UNDER MASK (CLM) instruction 7-21 example A -16 COMPARE LOGICAL LONG (CLCL) instruction 7-22 example A-I 7 comparison address (See address comparison) between System/370 and 370-XA E-l between 370-XA and ESA/370 D-l decimal 8-5 example A-33 floating-point 9-9 examples A-39 logical 7-4 examples A -15 signed-binary 7-4 TOD-clock 4-25 compatibility 1-3 among systems implementing different architectures 1-4 among systems implementing same architecture 1-3 between 370-XA and System/370 I/O operations 13-1 control-program 1-4 problem-state 1-4 completion of I/O functions X-6 ESA/370 Principles of Operation by channel-path-reset function 15-44 by clear function 15-14 by halt function 15-15 during data transfer 15-42 during initiation 15-41 for immediate commands 15-42 completion of instruction execution 5-12 completion of unit of operation 5-13 conceptual sequence 5-65 as related to storage-operand accesses 5-75 conclusion of I/O operations 13-8,16-1 during data transfer 15-42 during initiation 15-41 for immediate commands 15-42 conclusion of instruction execution 5-12 concurrency of access for storage references 5-74 condition code 4-5 deferred 16-8 in PSW 4-5 summary C-l tested by BRANCH ON CONDITION instruction 7-12 used for decision making 5-7 validity bit for 11-21 conditional-swapping instructions (See COMPARE AND SWAP instruction, COMPARE DOUBLE AND SWAP instruction) conditions for interruption (See interruption conditions) configuration 2-1 of storage 3-4 configuration-alert facility (I/O) 17-13 connective (See logical connective) . consistency (storage operand) 5-74 examples A -46,A -48 console device 12-1 control 4-1 as an I/O command 15-36 instructions 10-1 manual (See manual operation) control-program compatibility 1-4 control register 2-3,4-6 comparison, ESA/370 with 370-XA D-3 comparison, 370-XA with System/370 E-6 save areas 3-43 validity bit 11-21 control-register assignment 4-7 (CRx.y indicates control register x, bit position y) CRO.l: SSM-suppression-control bit 6-25,10-61 CRO.2: TOD-clock-sync-control bit 4-22,4-25 CRO.3: low-address-protection-control bit 3-10 CRO.4: extraction-authority-control bit 5-16 CRO.S: secondary-space-control bit 3-24,5-17 CRO.6: fetch-protection-override-control bit 3-9 CRO.8-12: translation format 3-24 CRO.14: vector-control bit 4-9 CRO.l5: I address-space-function-control bit 5-35 CRO.16: malfunction-alert subclass-mask bit 6-11 CRO.17: emergency-signal subclass-mask bit 6-11 CRO.18: external-call subclass-mask bit 6-11 CRO.19: TO D-clock sync-check subclass-mask bit 6-12 CRO.20: clock-comparator subclass-mask bit 6-10 CRO.21: CPU -timer subclass-mask bit 6-11 CRO.22: service-signal subclass-mask bit 6-12 CRO.25: interrupt-key subclass-mask bit 6-11 CRl.0: primary space-switch-control bit 6-24 primary space-switch-event-control bit 3-24 CR1.1-19: primary segment-table origin (PSTO) 3-25 CR1.23: primary private-space-control bit 3-25 CRl.25-31: primary segment-table length (PSTL) 3-25 CR2.1-25: dispatchable-unit-control-table origin (D U erO) 5-36 CR3.0-15: PSW -key mask (PKM) 5-16 CR3.16-31: secondary ASN (SASN) 3-13 CR4.0-15: authorization index (AX) 3-20,5-17 CR4.16-31: primary ASN (PASN) 3-13 CR5.0: subsystem-linkage-control bit 5-17,5-21 CR5.1-24: linkage-table origin (LTO) 5-21 CR5.l-25: primary-AST-entry origin (PASTEO) 5-21,5-36 CR5.25-31: linkage-table length (LTL) 5-21 CR6.0-7: I/O-interruption subclass mask 6-13 CR7.1-19: secondary segment-table origin (SSTO) 3-25 CR7.23: secondary private-space-control bit 3-25 CR7.25-31: secondary segment-table length (SSTL) 3-25 CR8.0-15: extended authorization index (EAX) 5-36 CR8.16-31: monitor-mask bits 6-20 CR9.0: PER successful-branching-event- mask bit 4-13 CR9.l: PER instruction-fetching-event- mask bit 4-13 CR9.2: PER storage-alteration-event-mask bit 4-13 CR9.3: PER general-register-alteration- event-mask bit 4-13 CR9.4:, PER store-using-real-address- event-mask bit 4-13 CR9.16-31: PER general-register-mask bits 4-13 CRI0.l-31: PER starting address 4-13 CRl1.1-31: PER ending address 4-13 CRI2.0: branch -trace-control bit 4-9 CRI2.1-29: trace-entry address 4-9 CRI2.30: ASN -trace-control bit 4-9 CRI2.31: explicit-trace-control bit 4-10 CR13.0: home space-switch-event-control bit 3-25,6-24 CRI3.1-19: home segment-table origin (HSTO) 3-25 CRI3.23: home private-space-control bit 3-25 CRI3.25-31: home segment-table length (HSTL) 3-25 CRI4.3: channel-report-pending subclass-mask bit 11-24 CR14.4: recovery subclass-mask bit 11-24 CRI4.5: degradation subclass-mask bit 11-24 CRI4.6: external-damage subclass-mask bit 11-24 CRI4.7: . warning subclass-mask bit 11-24 CR14.l2: ASN-translation-control bit 3-15,5-17 CRI4.13-31 : ASN-first-table origin (AFTO) 3-15 CRI5.1-28: linkage-stack-entryaddress 5-56 control unit 2-6,13-4 effect of I/O-system reset on 17-7 model number of (from sense-ID command) 15-39 sharing of 13-4 type number of (from sense-ID command) 15-39 type of 15-12 control unit busy 16-24,16-25 control-unit end (device status) 16-24 conversion binary-to-decimal 7-24 example A -18 decimal-to-binary 7-24 example A -18 decimal to hexadecimal G-I floating-point -number basic example A-7 examples with instructions A -41 Index X-7 hexadecimal-to-decimal G-l of hexadecimal and decimal fractions 'G-7 of hexadecimal and decimal integers G-6 CONVERT TO BINARY (CVB) instruction 7-23 example A -18 CONVERT TO DECIMAL (CVD) instruction 7-24 example A -18 COpy ACCESS (CPYA) instruction 7-24 count field " in CCW 15-24 invalid 16-29 in sesw 16-33 counter updating (example) A -44 counting operations 7-13 CP (COMPARE DECIMAL) instruction 8-5 example A -33 CPA (See channel-program address) CPU (central processing unit) 2-2 address 4-34 assigned storage locations for 3-39 when stored during external interruptions 6-9 checkpoint 11-2 effect of power-on reset on 4-32 hangup due to string of interruptions 4-3 identification (ID) 10-64 model number 10-64 registers 2-2 save areas for 3-42 reset 4-30 signal-processor order 4-35 retry 11-2 serialization 5-76 signaling 4-34 state 4-1 check-stop 4-2 load 4-2 no effect on TOD clock 4-22 operating 4-2 stopped 4-2 version code 10-64 CPU timer 4-26 external interruption 6-10 save areas for 3-42 validity bit for 11-21 CPYA (COpy ACCESS) instruction 7-24 CR (See control register) CR (COMPARE) binary instruction 7-15 CRW (channel-report word) 17-15 chaining of 17-14,17-15 error-recovery code (ERC) in 17-15 overflow in 17-15 reporting-source code (RSC) in 17-15 reporting-source ID (RSID) in 17-16 solicited 17-15 storing of 14-14 es (COMPARE AND SWAP) instruction 7-19 examples A -43 esCH (See CLEAR SUBCHANNEL instruction) current CCW 15-23 (See also CCW) current PSW 4-3,5-7 (See also PSW) stored during interruption 6-2 X-8 ESA/370 Principles of Operation CVB (CONVERT TO BINARY) instruction 7-23 example A -18 CVD (CONVERT TO DECIMAL) instruction 7-24 example A -18 D D (DIVIDE) binary instruction 7-25 example A-19 D field of instruction 5-6 damage channel-subsystem 11-17 code" (external) 11-22 validity bit for 11-21 external 11-16 subclass-mask bit for 11-24 instruction -processing 11-16 processing 11-19 service-processor 11-17 system 11-15 timing-facility 11-16 DAT (See dynamic address translation) DAT mode (bit in PSW) 4-5 use in address translation 3-24 data blocking of (I/O) 15-21 format for decimal instructions 8-1 floating-point instructions 9-2 general instructions 7-2 indirect addressing of (I/O) 13-7,15-31 measurement (I/O) (See measurement data) prefetching of for I/O operation 15-26 data address (I/O) 15-25 invalid 16-29 invalid specification of 16-29 data chaining of CCWs 15-28 flag in CCW for 15-24 overview of 13-8 data check bit in I/O sense data 15-38 measurement-block 16-37 data exception "6-17 data streaming (I/O) 13-4 effect of CCW count on 15-29 DCTI (device-connect-time interval) in ESW 16-41 in measurement block 17-3 DD (DIVIDE) floating-point instruction 9-9 DDR (DIVIDE) floating-point instruction 9-9 DE (DIVIDE) floating-point instruction 9-9 decimal arithmetic 8-2 comparison 8-5 digit codes 8-2 divide exception 6-18 instructions 8-1 examples A-33 number representation 8-1 examples A-5 operand overlap 8-3 overflow exception 6-18 mask in PSW 4-6 sign codes 8-2 tables for conversion to hexadecimal G~ 1 decimal-to-binary conversion 7-24 example A -18 dedicated allegiance 15-11 deferred condition code 16-8 degradation (machine-check condition) 11-17 subclass-mask bit for 11-24 degradation, storage (machine-check condition) 11-19 delay in storing 5-72 delayed access exception (machine-check condition) 11-18 deletion of malfunctioning unit 11-4 DER (DIVIDE) floating-point instruction 9-9 examples A-40 designation access-list·5-37 authority-table 3-16 effective segment-table 3-28 entry-table 5-22 home segment-table 3-25 linkage-table 5-21 in AST entry 3-17 of storage area for data (I/O) 15-25 page-table 3-26 primary segment-table 3-24 secondary segment-table 3-25 segment-table 3-24 in AST entry 3-16 destructive overlap 5-75,7-35 device 2-6,13-4 console 12-1 effect of I/O-system reset on 17-7 device-active bit 16-15 device address 13-5 device busy 16-25 device-connect-time interval (See Dcrl) device-connect-time measurement 17-5 effect of suspension on 15-34 enable 15-3 device-dis connect-time interval (in measurement block) 17-4 device end (device status) 16-26 device identifier 13-5 device model/type (from sense-ID command) 15-39 device-not-ready indication 15-38 device number 13-5 assignment of 13-6 in PMCW 15-4 device-number valid (bit in PMCW) 15-4 device-ready indication with attention 16-23 with device end 16-26 with unit exception 16-28 device status 16-23 field-validity flag for (in sub channel logout) 16-32,16-38 with inappropriate bit combination 16-38 device status check 16-38 DIAGNOSE instruction 10-7 digit codes (decimal) 8-2 digit selector (in EDIT) 8-7 direct-access storage 3-1 disabling for interruptions 6-6 disallowed interruptions 6-6 dispatchable unit (DU) 5-30 access-list designation (DUAL D) 5-37 control table (DUCT) 5-37 origin (DUcrO) 5-36 displacement (in relative addressing) 5-6 display (manual controls) 12-2 DIVIDE (D,DR) binary instructions 7-25 example A -19 DIVIDE (DD,DDR,DE,DER,DXR) floating-point instructions 9-9 examples A -40 DIVIDE DECIMAL (DP) instruction 8-6 example A-34 divide exception decimal 6-18 fixed-point 6-19 floating-point 6-20 divisible instruction execution 5-66 doubleword 3-3 doubleword-concurrent storage references 5-74 DP (DIVIDE DECIMAL) instruction 8-6 example A-34 DR (DIVIDE) binary instruction 7-25 DU (dispatchable unit) 5-30 DUALD (dispatchable-unit access-list designation) 5-37 DUCT (dispatchable-unit control table) 5-37 DUcrO (dispatchable-unit-control-table origin) 5-36 dump (standalone) 12-4 DXR (DIVIDE) floating-point instruction 9-9 dynamic address translation (OAT) 3-22 by LOAD REAL ADDRESS instruction 10-25 control of 3-24 explicit and implicit 3-27 mode bit in PSW 4-5 use in address translation 3-24 sequence of table fetches 5-71 dynamic-reconnection feature 13-3 E E instruction format 5-4 EAR (EXTRAcr ACCESS) instruction 7-27 early exception recognition 6-8 EAX (See extended authorization index) EBCDIC (Extended Binary-Coded-Decimal Interchange Code) architecture designed for v character code, chart for H-l ECC (error checking and correction) 11-2 ECW (extended-control word) 16-43 indication in SCSW 16-11 ED (EDIT) instruction 8-6 examples A-34 EDIT (ED) instruction 8-6 examples A -34 EDIT AND MARK (EDMK) instruction 8-10 example A-35 editing instructions 8-3 Index X-9 (See also ED instruction, EDMK instruction) EDMK (EDIT AND .MARK) instruction 8-10 example A-35 effective access-list designation 5-37 effective address 3-5 controlled by addressing mode 5-5 generation 5-5 used for storageitlterlocks 5-67 effective segment-table designation 3-28 effective space designation 5-67 EKM (entry key mask) 5-23 use by stacking PROGRAM CALL 5-53 emergency signal (external interruption) 6-11 signal-processor order 4-34 enabled (bit in PMCW) 15-2 enabling for interruptions 6-6 subchannel 16-5 enabling of sub channel 15-2,16-5 ending of instruction execution 5-12 entry addressing-mode bit 5-53 extended authorization index 5-54 instruction address 5-53 key 5-54 key mask (EKM) 5-23 use by stacking PROGRAM CALL 5-53 parameter 5-53 problem-state bit 5-53 entry (for tracing) 4-10 entry descriptor 5-56 entry index (EX) 5-21 entry table (ET) designation 5-22 length 5-22 origin 5-22 entry-table entry (ETE) basic (16-byte) 5-22 extended (32 byte) 5-52 entry-type code 5-57 EPAR (EXTRACf PRIMARY ASN) instruction 10-7 epoch (for TOD clock) 4-23 equipment check bit in I/O sense data 15-38 in signal-processor status 4-38 ERC (error-recovery code) 17-15 (See also CRW) EREG (EXTRACf STACKED REGISTERS) instruction 10-8 error checking and correction 11-2 from DIAGNOSE instruction 10-7 I/O-error alert 16-39 indirect storage 11-20 intermittent 11-5 PSW -format 6-8 secondary (I/O) 16-38 solid 11-5 state of TO D clock 4-22 storage 11-19 storage-key 11-19 error-recovery code (ERC) 17-15 (See also CRW) ERW (extended-report word) 16-36,16-40 X -10 ESA/370 Principles of Operation as result of channel-control check 16-31 as result of channel-data check 16-31 ESA/370 (Enterprise Systems Architecture/370) architectural-mode controls 12-2 comparison of facilities with 370-XA D-l highlights of 1-1 ESAR (EXTRACf SECONDARY ASN) instruction 10-8 ESTA (EXTRACf STACKED STATE) instruction 10-9 ESW (extended-status word) 16-36 (See also extended status) ESW format bit (in SCSW) 16-8 ET (See entry table) ETE (See entry-table entry) ETL (entry-table length) 5-22 ETO (entry-table origin) 5-22 event 6-13 monitor 7-32 PER 4-12 space-switch 6-24 EX (entry index) 5-21 translation exception 6-19 EX (EXECUTE) (See EXECUTE instruction) exception access identification 3-41 exception-extension code 6-14 exceptions 6-13 access (collective program-interruption name) 6-29,6-34 addressing 6-14 AFX -translation 6-16 ALE-sequence 6-16 ALEN-translation 6-16 ALET -specification 6-16 ASN -translation (collective program-interruption name) 6-38 ASN -transhition -specification 6-16 associated with ART 5-46 stacking process 5-62 unstacking process 5-65 ASTE-sequence 6-17 ASTE-validity 6-17 ASX -translation 6-17 comparison of ESA/370 with 370-XA D-3 data (decimal) 6-17 decimal-divide 6-18 decimal-overflow 6-18 delayed access (machine-check condition) 11-18 during translation 3-31 EX -translation 6-19 execute 6-18 exponent-overflow 6-18 exponent-underflow 6-19 extended-authority 6-19 fixed-point-divide 6-19 fixed-point-overflow 6-19 floating-point-divide 6-20 LX-translation 6-20 operand (of I/O instruction) 6-21 operation 6-21 page-translation 6-21 PC-translation-specification 6-22 primary-authority 6-22 privileged-operation 6-22 protection 6-23 PSW -related 6-8 recognition oft early and late 6-8 secondary-authority 6-24 segment-translation 6-24 significance 6-24 special-operation 6-25 specification 6-26 stack-empty 6-27 stack-full 6-27 stack-operation 6-27 stack -specification 6-27 stack-type 6-27 trace (collective program-interruption name) 6-38 trace-table 6-28 translation-specification 6-28 unnormalized-operand 6-28 vector-operation 6-28 EXCLUSIVE OR (X){C){I){R) instructions 7-25 examples A -19 EXECUTE (EX) instruction 7-26 effect of address comparison on 12-1 example A-21 exceptions while fetching target 6-7 PER event for target of 4-17 execute exception 6-18 exigent machine-check conditions II-II explicit address translation 3-27 explicit-trace-control bit 4-10 exponent 9-1 (See also floating point) overflow 9-1 exception 6-18 underflow 9-1 exception 6-19 mask in PSW 4-6 extended AST entry 5-40 extended-authority exception 6-19 as an access exception 6-29 extended authorization index (EAX) 5-36 control bit 5-53 in entry-table entry 5-54 in linkage-stack state entry 5-60 extended control (bit in SCSW) 16-11 extended-control word (See ECW) extended entry-table entry 5-52 extended floating-point number 9-2 extended-report word (See ERW) extended status (See also ESW) flags in subchannel logout for 16-36 format-O 16-36 format-l 16-40 format-2 16-41 format-3 16-42 extended-status word 16-36 (See also extended status) extended-status-word-format bit 16-8 external call external interruption 6-11 pending (signal-processor status) 4-38 signal-processor order 4-34 external damage 11-16 subclass-mask bit for 11-24 external-damage code 11-22 assigned storage locations for 3-42 validity bit for 11-21 external interruption 6-9 clock -comparator 4-25 t6-1 0 CPU-timer 4-26 t6-10 direct conditions 6-10 emergency-signal 6-11 external-call 6-11 interrupt-key 6-11 malfunction-alert 6-11 mask in PSW 4-5 parameter 6-9 assigned storage locations for 3-39 pending conditions 6-10 priority of conditions 6-10 service-signal 6-12 TOD-clock-sync-check 6-12 externally initiated functions 4-27 I/O 17-10 EXTRACf ACCESS (EAR) instruction 7-27 EXTRACf PRIMARY ASN (EPAR) instruction 10-7 EXTRACf SECONDARY ASN (ESAR) instruction 10-8 EXTRACr STACKED REGISTERS (EREG) instruction 10-8 EXTRACf STACKED STATE (ESTA) instruction 10-9 extraction-authority-control bit 5-16 F facilities of ESA/370 (compared with 370-XA) 0-1 facilities of 370-XA (compared with System/370) E-l I/O 13-1 failing-storage address 11-22 assigned storage locations for 3-42 in ESW 16-36tI6-40 as result of channel-control check 16-31 as result of channel-data check 16-31 validity bit for 11-21 validity flag for (in ERW) 16-40 failure t vector-facility 11-17 fetch protection 3-8 bit in storage key 3-7 override-control bit 3-9 fetch reference 5-72 access exceptions for 6-32 fetching handling of invalid CBC in storage keys during 11-8 of ART-table and OAT-table entries 5-71 of instructions 5-69 of PSWs during interruptions 5-76 of storage operands 5-72 field 3-2 field separator (in ED IT) 8-7 field-validity flags (in subchannellogout) 16-38 relation to channel-control check of 16-32 Index X-ll FIFO (first in first out) queuing, example for lock and unlock A-46 fill byte (in EDIT) 8-7 fixed-length field 3-2 fixed logout· assigned storage locations for 3-42 machine-check 11-24 fixed point (See also binary) divide exception 6-19 overflow exception 6-19 mask in PSW 4-6 floating interruption conditions 6-6,11-23 clearing of 4-31 floating point (See also exponent) comparison 9-9 conversion basic example A-7 examples with instructions A -41 data format 9-2 divide exception 6-20 instructions 9-1 examples A-38 numbers 9-1 examples A-5 registers 2-3 save areas for 3-42 validity bit for 11-21 shifting (See normalization) format address 3-2 CCW (See CCW format control) decimal data 8-1 floating-point data 9-2 general data 7-2 information 3-2 instruction 5-3 PSW 4-5 format-O access-list designation 5-38 format-O and format-l CCWs 15-23 format-l access-list designation 5-38 forward-section-header address 5-58 forward-section validity bit 5-58 fraction 9-1 conversion of between hexadecimal and decimal G-7 free-pool manipulation, programming example A -4 7 fullword (See word) function control (I/O) 16-12 function-pending time 17-2 in measurement block 17-4 G G (giga) iv general instructions 7-2 examples A-8 general registers 2-3 alteration-event-mask bit 4-13 alteration of (PER event) 4-17 PER-mask bits 4-13 X-12 ESA/370 Principles of Operation save areas for 3-42 validity bit for 11-21 glue module 5-11 guard digit 9-3 H halfword 3-3 halfword -concurrent storage references 5-74 halt function 15-14 bit in SCSW for 16-12 completion of 15-15 initiated by HALT SUBCHANNEL 14-4 path management for 15-14 pending 16-14 signaling for 15-15 halt signal 17-5 issued as part of halt function 15-15 HALT SUBCHANNEL '(HSCH) instruction 14-4 (See also halt function) effect on SCSW count field 15-17 function initiated by 15-14 use of after RESET CHANNEL PATH 14-8 HALVE (HDR,HER) instructions 9-11 example A -40 HD R (HALVE) instruction 9-11 example A -40 header entry 5-58 HER (HALVE) instruction 9-11 hexadecimal (hex) representation 5-4 tables G-l high-speed data transfer (I/O) 13-4 home address space 0-1,3-13,5-26 facilities 5-26 home segment table designation (HSTO) 3-25 length (HSTL) 3-25 origin (HSTO) 3-25 home-space mode 3-24 home space-switch event, control bit, in control register 13 3-25 home virtual address 3-4 effective segment-table designation for 3-28 HSCH (See HALT SUBCHANNEL instruction) HSTD (home segment-table designation) 3-25 HSTL (home segment-table length) 3-25 HSTO (home segment-table origin) 3-25 I field of instruction 5-5 I/O (input/output) 2-4 basic functions of 15-1 blocking of data for 15-21 comparison of 370-XA with System/370 E-4,13-1 effect on CPU timer 4-26 sense data (See sense data) support functions of 17-1 I/O addressing 13-5 I/O commands (See commands) I/O device (See device) I/O-error alert (in subchannel logout) 16-39 I/O instructions 14-1,14-2 deferred condition code for 16-8 operand access by 14-1 role of in I/O operations 13-6 I/O interface, OEMI publication referenced v I/O interruption 6-12,16-1 (See also interruption) action for 16-5 masking of 13-9 priority of 16-5 program-controlled interruption (See PCI) I/O-interruption code 6-12,14-16 stored by TPI 16-6 I/O-interruption condition 13-9,16-2 alert 16-4 intermediate 16-4 primary 13-8,16-4 secondary 13-8,16-4 solicited 16-3 unsolicited 16-3 I/O-interruption parameter assigned storage locations for 3-42 in I/O-interruption code 16-6 in ORB 15-21 itt PMCW 15-2 used for IPL 17-10 I/O-interruption request c)earing of 13-9 ft'om sub channels 16-5 I/O-i~terruption subclass 13-9 I/O-interruption subclass code (lSC) 15-2 I/O-irherruption subclass mask 6-13,16-5 relation to priority 16-5 I/O mask in PSW 4-5 I/O operations 13-6 conclusion of (See conclusion of I/O operations) execution of 15-19 immediate 15-42 initiated indication for 16-11· t~rmination of (See conclusion of I/O operations) I/O-system reset 17-6 a~ part of subsystem reset 4-31 lAC (INSERT ADDRESS SPACE CONTROL) instruction 10-12 IC (INSERT CHARACTER) instruction 7-27 IC (instruction counter) (See instruction address) ICM (INSERT CHARACTERS UNDER MASK) instruction 7-27 examples A-21 ID (See CPU identification, sense ID) IDA On direct-data address) 15-31 fbig in CCW 15-24 IDAW (indirect-data-address word) 15-31 check (in subchannellogout) 16-37 contents of 15-32 invalid address of 16-29 invalid address specification in 16.,29 invalid address specification of 16-29 idle state for subchannel 16-13 IFCC (interface-control check) 16-32 fLC (instruction-length code) 6-7 assigned storage locations for 3-40 for program interruptions 6-13 for supervisor-call interruption 6-39 IML (initial microprogram loading) controls 12-2 immediate operand 5-5 immediate operation (I/O) 15-42 implicit address translation 3-27 incorrect length (subchannel status) 16-28 for immediate operations 15-37 when writing undefined blocks 15-35 incorrect-length-indication mode 15-22 incorrect-Iength-indication-suppression facility E-2,17-13 incorrect-length-suppression mode 15-22 incorrect state (signal-processor status) 4-38 index for address generation 5-6 instructions for branching on 7-14 into access list 5-37 into ASN first and second tables 3-14 into authority table 5-17 into entry and linkage tables 5-21 register for 2-3 indicator check-stop 12-2 load 12-3 manual 12-3 mode 12-2 test 12-5 wait 12-5 indirect-data address (See IDA) indirect-data-address word (See IDAW) indirect storage error 11-20 information format 3-2 inhibition of unit of operation 5-13 initial CPU reset 4-31 signal-processor order 4-35 initial-microprogram-Ioading (IML) controls 12-2 initial program loading (See IPL) initial-status-interruption control 15-21,16-11 relation to Z bit 16-11 used for IPL 17-10 inoperative (signal-processor status) 4-38 input/output (See I/O) INSERT ADDRESS SPACE CONTROL (lAC) instruction 10-12 INSERT CHARACTER (IC) instruction 7-27 INSERT CHARACTERS UNDER MASK (ICM) instruction 7-27 examples A -21 INSERT PROGRAM MASK (lPM) instruction 7-28 INSERT PSW KEY (IPK) instruction 10-12 INSERT STORAGE KEY EXTENDED (lSKE) instruction 10-13 INSERT VIRTUAL STORAGE KEY (IVSK) instruction 10-13 installation 2-1 instruction address as a type of address 3-5 handling by DAT 3-24 in entry-table entry 5-23 in PSW 4-6 validity bit for 11-21 instruction-length code (See ILC) instruction -processing damage 11-16 Index X-13 resulting in processing backup 11-18 resulting in processing damage 11-19 instructions (See also instruction lists and page numbers in Appendix B) backing up of 11-18 classes of 2-2 comparison of ESA/370 with 370-XA D-2 comparison of 370-XA with System/370 E-3 control 10-1 damage to 11-16,11-19 decimal 8-1 examples A-33 divisible execution of 5-66 ending of 5-12 examples of use A-7 execution of 5-7 fetching of 5-69 access exception for 6-31 PER event for 4-17 PER-event mask for 4-13 floating-point 9-1 examples A-38 format of 5-3 general 7-2 examples A-8 interruptible (See interruptible instructions) length of 5-4 list of B-1 modification by EXECUTE instruction 7-26 prefetching of 5-70 privileged 4-5 for control 10-1 semiprivileged 4-5,10-1 sequence of execution 5-2 stepping of (rate control) 12-3 effect on CPU state 4-2 effect on CPU timer 4·26 unprivileged 4-5,7-2 vector 2-4 integer binary 7-2 address as 5-6 examples A -2 conversion of between hexadecimal and decimal G-6 decimal 8-2 integral boundary 3-3 interface, I/O, OEM I publication referenced v interface-control check (subchannel status) 16-32 interlocked -update storage reference 5-73 interlocks for virtual storage references 5-66 intermediate interruption condition (I/O) 16-4 intermediate-status bit (I/O) 16·17 intermittent errors 11-5 internal storage 2-2 interpretive execution, publication referenced v interrupt key 12-3 external interruption 6-11 interruptible instructions 5-12 COMPARE AND FORM CODEWORD 7-15 COMPARE LOGICAL LONG 7-23 MOVE LONG 7-35 X -14 ESA/370 Principles of Operation PER event affecting the ending of 4-15 stopping of 4-2 TEST BLOCK 10-70 UPDATE TREE 7-53 vector instructions 5-12 interruption 6-2 (See also masks) action 6-2 I/O 16-5 machine-check 11-12 classes of 6-5 effect on instruction sequence 5-12 external (See external interruption) I/O (See I/O interruption) machine-check (See machine-check interruption) masking of 6-6 pending 6-6 external 6-10 machine-check 11-13 relation to CPU state 4-2 priority of (See priority) program (See program interruption) program-controlled (I/O) (See PCI) restart 6-38 string (See string of interruptions) supervisor-call 6-38 interruption code 6-5 external 6-9 I/O (See I/O-interruption code) machine-check (MCIC) 3-42,11-14 program 6-13 summary of 6-2 supervisor-call 6-39 interruption conditions 6-2 clearing of 4-30 floating 6-6,11-23 I/O (See I/O-interruption condition) interruption parameter external (assigned storage locations) 3-39 I/O (See I/O-interruption parameter) interruption-response block (See IRB) interruption subclass (See I/O-interruption subclass) intervention required (bit in I/O sense data) 15-38 invalid address 6-14 bit in access-list entry 5-39 bit in ASN -first-table entry 3-15 bit in ASN -second-table entry 3-16 bit in linkage-table entry 5-22 bit in page-table entry 3-27 bit in segment-table entry 3-26 CBC 11-2 in registers 11-10 in storage 11-6 in storage keys 11-7 operation code 6-21 order (signal-processor status) 4-38 parameter (signal-processor status) 4-38 translation address 3-31 translation format 3-24 exception recognition 3-31 invalid address specification in channel-program address 16-29 in IDAW 16-29 of data in CCW 16-29 of IDAW 16-29 of TIC CCW 16-29 invalid CCW field command code 16-29 count 16-29 data address 16-29 suspend flag 16-30 invalid format ofCCW 16-30 of ORB 16-30 invalid sequence of CCWs 16-30 INVALIDATE PAGE TABLE ENTRY (I PTE) instruction 10-14 effect of when CPU is stopped 4-2 inverse move (See MOVE INVERSE instruction, move;' inverse facility) IPK (INSERT PSW KEY) instruction 10-12 IPL (initial program loading) 4-32,17~10 assigned storage locations for 3-39 effect on CPU state 4-2 IPM (INSERT PROGRAM MASK) instruction 7-28 IPTE (INVALIDATE PAGE TABLE ENTRY) instruction 10-14 IRB (interruption-response block) 16-6 (See also ECW, ERW, ESW, SCSW) storage requirements for 16-11 ISC (I/O-interruption subclass code) 15-2 ISKE (INSERT STORAGE KEY EXTENDED) instruction 10-13 IVSK (INSERT VIRTUAL STORAGE KEY) instruction 10-13 K K (kilo) iv key access (See access key) manual (See manual operation) PSW (See PSW key) storage (See storage key) subchannel (See subchannel key) key check (in subchannellogout) 16-36 key-controlled protection 3-8 exception for 6-23 key mask authorization 5-23 entry 5-23 PSW (PKM) 5-16 L L (LOAD) binary instruction 7-28 example A-22 L fields of instruction 5-5 LA (LOAD ADDRESS) instruction 7-29 examples A -22 LAE (LOAD ADDRESS EXTENDED) instruction 7-29 LAM (LOAD ACCESS MULTIPLE) instruction 7-28 LASP (LOAD ADDRESS SPACE PARAMETERS) instruction 10-16 last-path-used mask (See LPUM) late exception recognition 6-9 LCDR (LOAD COMPLEMENT) floating-point instruction 9-12 LCER (LOAD COMPLEMENT) floating-point instruction 9-12 LCR (LOAD COMPLEMENT) binary instruction 7-30 LCTL (LOAD CONTROL) instruction 10-23 LD (LOAD) floating-point instruction 9-12 LOR (LOAD) floating-point instruction 9-12 LE (LOAD) floating-point instruction 9-12 left-to-right addressing 3-2 length field 3-2 instruction 5-4 register-operand 5-5 second operand same as first 5-5 variable (storage operand) 5-5 LER (LOAD) floating-point instruction 9-12 LH (LOAD HALFWORD) instruction 7-30 examples A-23 LIFO (last in first out) queuing, example for lock and unlock A-45 light (See indicator) limit mode (I/O) 15-2 link information for BRANCH AND LINK instruction 7-10 for BRANCH AND SAVE AND SET MODE instruction 7-11 for BRANCH AND SAVE instruction 7-11 linkage for subroutines 5-8 linkage index (LX) 5-21 linkage stack 0-1,5-48,5-56 associated PER events 5-52 associated trace entries 5-52 branch state entry 10-5 entry address 5-56 entry descriptor 5-56 entry-type code 5-57 functions 5-49 handling ofinformation in 5-51 header entry 5-58 instructions 5-49 .introduction 5-54 next-entry size 5-57 operations 5-54 control 5-56 program-call state entry 10-36 remaining free space 5-57 section 5-54 identification 5-57 state entry 5-59 trailer entry 5-58 linkage table (LT) 5-22 designation (LTD) 5-21 in AST entry 3-17 length (LTL) 5-21 in primary AST entry 5~21 origin (LTO) 5-21 in primary AST entry 5-21 Index X-IS LM (LOAD MULTIPLE) instruction 7-31 LNDR (LOAD NEGATIVE) floating-point instruction 9-13 LNER (LOAD NEGATIVE) floating-point instruction 9-13 LNR (LOAD NEGATIVE) binary instruction 7-31 LOAD (L,LR) binary instructions 7-28 example A -22 LOAD (LD,LDR,LE,LER) floating-point instructions 9-12 LOAD ACCESS MULTIPLE (LAM) instruction 7-28 LOAD ADDRESS (LA) instruction 7-29 examples A -22 LOAD ADDRESS EXTENDED (LA E) instruction 7-29 LOAD ADDRESS SPACE PARAMETERS (LASP) instruction 10-16 load and store using real address D-2 LOAD AND TEST (LTDR,LTER) floating-point instructions 9-12 LOAD AND TEST (LTR) binary instruction 7-30 load-clear key 12-3 LOAD COMPLEMENT (LCDR,LCER) floating-point instructions 9-12 LOAD COMPLEMENT (LCR) binary instruction 7-30 LOAD CONTROL (LCTL) instruction 10-23 LOAD HALFWORD (LH) instruction 7-30 examples A -23 load indicator 12-3 LOAD MULTIPLE (LM) instruction 7-31 LOAD NEGATIVE (LNDR,LNER) floating-point instructions 9-13 LOAD NEGATIVE (LNR) binary instruction 7-31 load-normal key 12-3 LOAD POSITIVE (LPDR,LPER) floating-point instructions 9-13 LOAD POSITIVE (LPR) binary instruction 7-31 LOAD PSW (LPSW) instruction 10-24 LOAD REAL ADDRESS (LRA) instruction 10-25 LOAD ROUNDED (LRDR,LRER) instructions 9-14 load state 4-1,4-2 during IPL 4-32 load-unit-address controls 12-3 LOAD USING REAL ADDRESS (LURA) instruction 10-27 loading, initial (See IML, IPL) location 3-2 (See also address) not available in configuration 6-14 lock A-45 example with FIFO queuing A-47 example with LIFO queuing A-46 logical arithmetic (unsigned binary) 7-3 comparison 7-4 connective AND 7-9 EXCLUSIVE OR 7-25 OR 7-40 data 7-2 logical address 3-4 handling by DAT 3-24 X-16 ESA/370 Principles of Operation logical-path mask (See LPM) logout fixed assigned storage locations for 3-42 machine-check 11-24 sub channel (I/O) 16-36 long floating-point number 9-2 long I/O block 16-28 loop control 5-8 loop of interruptions (See string of interruptions) low-address protection 3-10 control bit 3-10 exception for 6-23 LPDR (LOAD POSITIVE) floating-point instruction 9-13 LPER (LOAD POSITIVE) floating-point instruction 9-13 LPM (logical-path mask) 15-4,15-22 effect on system performance of 15-10 used for IPL 17-10 LPR (LOAD POSITIVE) binary instruction 7-31 LPSW (LOAD PSW) instruction 10-24 LPUM (last-path-used mask) 15-5 field-validity flag for (in sub channel logout) 16-38 in ESW 16-37 LR (LOAD) binary instruction 7-28 LRA (LOAD REAL ADDRESS) instruction 10-25 LRDR (LOAD ROUNDED) instruction 9-14 LRER (LOAD ROUNDED) instruction 9-14 LT (linkage table) 5-22 LTD (linkage-table designation) 5-21 LTDR (LOAD AND TEST) floating-point instruction 9-12 LTER (LOAD AND TEST) floating-point instruction 9-12 LTL (linkage-table length) 5-21 in primary AST entry 5-21 LTO (linkage-table origin) 5-21 in primary AST entry 5-21 LTR (LOAD AND TEST) binary instruction 7-30 LURA (LOAD USING REAL ADDRESS) instruction 10-27 LX (linkage index) 5-21 invalid bit 5-22 translation exception 6-20 M M (mega) iv M (MULTIPLY) binary instruction 7-38 example A-27 machine check 11-1 (See also malfunction) comparison of 370-XA with System/370 E-7 handling of malfunction detected as part of I/O 11-5 interruption 6-13,11-11 action 11-12 code (MCIC) 3-42,11-14 floating conditions 11-23 mask in PSW 4-5 subclass masks in control register 11 '123 logout 11-24 mask, in PSW 4-5 main storage 3-1 (See also storage) effect of power-on reset on 4-32 shared (in multiprocessing) 4-34 malfunction 11-1 at channel subsystem 16-31 at I/O device 16-32 correction of 11-2 effect on manual operation 12-1 from DIAGNOSE instruction 10-7 indication of 11-4 machine-check handling for when detected as part of I/O 11-5 malfunction alert (external interruption) 6-11 when entering check -stop state 11-11 manual indicator 12-3 (See also stopped state) manual operation 12-1 controls address-compare 12-1 alter-and -display 12-2 IML 12-2 load-unit-address 12-3 power 12-3 rate 12-3 TOO-clock 12-5 effect on CPU signaling 4-37 keys interrupt 12-3 load-clear 12-3 load-normal 12-3 restart 12-4 start 12-4 stop 12-4 store-status 12-4 system-reset-clear 12-4 system-reset-normal 12-5 masks 6-6 (See also I/O interruption, interruption) in BRANCH ON CONDITION instruction 7-12 in COMPARE LOGICAL CHARACTERS UNDER MASK instruction 7-21 in INSERT CHARACTERS UNDER MASK instruction 7-27 in PSW 4-5 in STORE CHARACTERS UNDER MASK instruction 7-46 monitor 6-20 path-management 15-2,15-22 PER-event 4-13 PER general-register 4-13 program-interruption 6-13 subclass external-interruption 6-10 I/O-interruption (See I/O-interruption subclass mask) machine-check-interruption 11-23 mathematical assists, publication referenced v maximum negative number 7-2 MC (MONITOR CALL) instruction 7-32 MCIC (machine-check-interruption code) 3-42,11-14 MD (MULTIPLY) floating-point instruction 9-14 MDR (MULTIPLY) floating-point instruction 9-14 example A -40 ME (MULTIPLY) floating-point instruction 9-14 measurement device-connect-time 17-5 measurement-block update (I/O) 17-2 measurement block (I/O) 17-2 data check 16-37 index 15-6 key, used as access key 3-8 multiple use of 15-10 program check 16-37 protection check 16-37 update enable 15-3 measurement data (I/O) accumulated 17-2 effect of CSCH on 14-4 effect of HSCH on 14-5 measurement-mode control (I/O) 15-3 MER (MULTIPLY) floating-point instruction 9-14 message byte (in EDIT) 8-7 MH (MULTIPLY HALFWORD) instruction 7-39 example A-27 microprogram (initial loading of) 12-2 mode access-register 3-24 addressing (See addressing mode) architectural (See architectural mode) burst (channel-path operation) 13-3 byte-multiplex (channel-path operation) 13-3 home-space 3-24 incorrect-length -indication 15-22 incorrect-length-suppression 15-22 indicator, architectural 12-2 multipath (See multipath mode) primary-space 3-24 real 3-24 requirements for semiprivileged instructions 5-16 secondary-space 3-24 single-path 15-3,15-20 translation 3-24 model number (in CPU ID) 10-64 modifiable area (in linkage-stack state entry) 5-60 MODIFY STACKED STATE (MSTA) instruction 10-27 MODIFY SUBCHANNEL (MSCH) instruction 14-6 MONITOR CALL (MC) instruction 7-32 monitor-class number 6-20 assigned storage locations for 3-41 monitor code 6-20 assigned storage locations for 3-41 monitor event 6-20 monitor masks 6-20 monitoring (See also measurement) channel-subsystem 17-1 for PER events (See PER) with MONITOR CALL 6-20,7-32 MOVE (MVC,MVI) in~tructions 7-32 examples A-21,A723 MOVE INVERSE (MV~IN) instruction 7-33 example A-24 - Index X,-J7 move-inverse facility 7-33 MOVE LONG (MVCL) instruction 7-33 examples A -25 MOVE NUMERICS (MVN) instruction 7-37 example A -25 MOVE TO PRIMARY (MVCP) instruction 10-29 MOVE TO SECONDARY (MVCS) instruction 10-29 MOVE WITH DESTINATION KEY (MVCDK) instruction 10-30 MOVE WITH KEY (MVCK) instruction 10-31 MOVE WITH OFFSET (MVO) instruction 7-37 example A-26 MOVE WITH SOURCE KEY (MVCSK) instruction 10-32 move-with -source-or-destination -key facility 0- 2 MOVE ZONES (MVZ) instruction 7-38 example A -26 MP (MULTIPLY DECIMAL) instruction 8-10 example A-36 MR (MULTIPLY) binary instruction 7-38 example A-27 MSCH (MODIFY SUBCHANNEL) instruction 14-6 MSTA (MODIFY STACKED STATE) instruction 10-27 multipath mode 15-3 entering 15-20 multiple-access storage references 5-74 MULTIPLY (M,MR) binary instructions 7-38 examples A-27 MULTIPLY (MD,MDR,ME,MER,MXD,MXDR,MXR) floatingpoint instructions 9 -14 example A -40 MULTIPLY DECIMAL (MP) instruction 8-10 example A-36 MULTIPLY HALFWORD (MH) instruction 7-39 example A-27 multiprocessing 4-33 manual operations for 12-5 programming considerations for A-42,8-3 programming examples A-42 timing-facility interruptions for 4-24 TOO clock for 4-21 multiprogramming examples A-42 MVC (MOVE) instruction 7-32 examples A-21,A-23 MVCDK (MOVE WITH DESTINATION KEY) instruction 10-30 MVCIN (MOVE INVERSE) instruction 7-33 example A-24 MVCK (MOVE WITH KEY) instruction 10-31 MVCL (MOVE LONG) instruction 7-33 examples A -25 MVCP (MOVE TO PRIMARY) instruction 10-29 MVCS (MOVE TO SECONDARY) instruction 10-29 MVCSK (MOVE WITH SOURCE KEY) instruction 10-32 MVI (MOVE) instruction 7-32 example A -24 MVN (MOVE NUMERICS) instruction 7-37 example A-25 X-1S ESA/370 P~inciples of Operation MVO (MOVE WITH OFFSET) instruction 7-37 example A -26 MVZ (MOVE ZONES) instruction 7-38 example A -26 MXD (MULTIPLY) floating-point instruction 9-14 MXDR (MULTIPLY) floating-point instruction 9-14 MXR (MULTIPLY) floating-point instruction 9-14 N N (AND) instruction 7-9 N condition (I/O) 16-12 NC (AND) instruction 7-9 near-valid CBC 11-2 in storage 11-5 negative zero binary 7-2 decimal 8-3 example A-5 new PSW 4-3 assigned storage locations for 3-39 fetched during interruption 6-2 next-entry size (in linkage stack) 5-57 NI (AND) instruction 7-9 example A-8 no-operation as an I/O command (control) 15-37 instruction (BRANCH ON CONDITION) 7-13 node (of tree structure) 7-52 noninterlocked-update storage reference 5-73 nonvolatile storage 3-2 normalization 9-2 not operational as channel-path state 16-12 (See also path-not-operational bit in SCSW, PNOM) as CPU state 4-36 as TOO-clock state 4-22 not set (fOD-clock state) 4-22 NR (AND) instruction 7-9 nullification exceptions to 5-14 for exigent machine-check conditions 11-11 ofinstruction execution 5-12 of unit of operation 5-13 numbering of addresses (byte locations) 3-2 of bits 3-2 numbers binary 7-2 examples A-2 CPU-model 10-64 decimal 8-1 examples A-5 device 13-5 . floating-point 9-1 examples A-5 hexadecimal G-l,5-4 Jlumeric bits 8-1 moving of 7-37 o o (OR) instruction 7-40 OC (OR) instruction 7-40 OEM I (original equipment manufacturers' information) for I/O interface, publication referenced v 01 (0 R) instruction 7-40 example A -28 example of problem with A -42 old PSW 6-2 assigned storage locations for 3-39 one's complement binary notation 7-2 used for SUBTRACT LOGICAL instruction 7-49 op code (See operation code) operand 5-2 access of 5-72 for I/O instructions 14-1 address generation for 5-6 exception 6-21 immediate 5-5 length of 5-2 overlap for decimal instructions 8-3 for general instructions 7-2 register for 5-4 sequence of references for 5-72 storage 5-5 types of (fetch, store, update) 5-72 used for result 5-3 operating state 4-1,4-2 operation I/O (See I/O operations) unit of 5-12 operation code (op code) 5-2 invalid 6-21 operation exception 6-21 operation-request block (See ORB) operator facilities 2-6,12-1 basic 12-1 operator intervening (signal-processor status) 4-38 OR (O,OC,OI,OR) instructions 7-40 example of problem with OR immediate A-42 examples A-28 ORB (operation-request block) 15-21 channel-program address in 15-22 interruption parameter in 15-21 invalid 16-30 logical-path mask (LPM) in 15-22 orders (I/O) 13-6,15-25 orders (signal-processor) 4-34 conditions precluding response to 4-36 CPU reset 4-35 emergency signal 4-34 external call 4-34 initial CPU reset 4-35 restart 4-35 sense 4-34 set prefix 4-35 start 4-35 stop 4-35 stop and store status 4-35 store status at address 4-36 overflow binary 7-3 example A-2 decimal 6-18 exponent (See exponent overflow) fixed-point 6-19,7-3 in CRW 17-15 overlap destructive 7-35 operand for decimal instructions 8-3 for general instructions 7-2 operation 5-66 overrun (bit in I/O sense data) 15-38 P PACK (PACK) instruction 7-40 example A-28 packed decimal numbers 8-1 conversion of to zoned format 7-52 conversion to from zoned format 7-40 examples A-5 padding byte for COMPARE LOGICAL LONG instruction 7-22 for MOVE LONG instruction 7-33 page 3-23 page-frame real address (PFRA) 3-27 page index (PX) 3-23 page-invalid bit (in page-table entry) 3-27 page protection E-l,3-9 bit for 3-27 exception for 6-23 page swapping 3-23 page table 3-27 designation 3-26 length (PTL) 3-26 lookup 3-30 origin (PTO) 3-26 page-translation exception 6-21 as an access exception 6-29,6-34 PALB (PURGE ALB) instruction 10-52 PAM (path -available mask) 15-7 effect of reconfiguration on 15-10 effect of resetting on 15-10 effect on allegiance of 15-10 parameter external -interruption 6-9 assigned storage locations for 3-39 I/O-interruption (See I/O-interruption parameter) register for SIGNAL PROCESSOR 4-35,10-62 translation 3-24 parity bit 11-2 partial completion of instruction execution 5-13 PASN (primary address-space number) 3-13 in trace entry 4-11 PASTE (primary AST entry) 5-21 PASTEO (primary-AST-entryorigin) 5-21,5-36 path (See channel path) path available for selection 15-12 path management 13-7 for clear function 15-13 for halt function 15-14 Index X-19 for start function and resume function 15-17 path-management-control word (See PMCW) path-management masks last-path-used mask (See LPUM) logical-path mask (See LPM) path-available mask (See PAM) path -installed mask (See PIM) path-not-operational mask (See PNOM) path-operational mask (See POM) path-not-operational bit (N) in SCSW 16-12 path-not-operational condition 15-4 pattern (in EDIT) 8-6 PC (PROGRAM CALL) instruction 10-34 PC-cp (PROGRAM CALL instruction, to current primary) 10-36 PC number 10-34 in linkage-stack state entry 5-60 in trace entry 4-11 translation 5-21 PC-ss (PROG RAM CALL instruction, with space switching) 10-36 PC-translation -specification exception 6-22 PC-type bit 5-53 PCI (program-controlled interruption) 15-30 as flag in CCW 15-24 intermediate interruption condition for 16-17 sub channel status for 16-28 pending channel reports (effect of I/O-system reset on) 17-8 pending interruption (See interruption pending) PER (program-event recording) 4-12 access identification 3-41,4-14 address 4-14 assigned storage locations for 3-41 code 4-14 assigned storage locations for 3-41 events 4-12 general-register-alteration event 4-17 mask bits 4-13 instruction-fetching event 4-17 masks bit in PSW 4-5 general-register 4-13 PER-event 4-13 priority of indication 4-15 program-interruption condition 6-22 storage-alteration event 4-17 storage-area designation 4-16 ending address 4-13 starting address 4-13 wraparound 4-16 store-using-real-address event 4-18 successful-branching event 4-16 PFRA (page-frame real address) 3-27 piecemeal steps of instruction execution 5-66 PIM (path-installed mask) 15-6 PKM (PSW -key mask) 5-16 PMCW (path-management-control word) 15-2 channel-path identifiers (CHPID) in 15-7 PNOM (path-not-operational mask) 15-4 effect on POM of 15-10 indicated in SCSW 16-12 point of damage 11-14 X-20 ESA/370 Principles of Operation point of interruption 5-12 for machine check 11-14 POM (path-operational mask) 15-6 effect on PNOM of 15-10 POST (SVC), example of routine to bypass A-44 postnormalization 9-2 power controls 12-3 power-on reset 4-32 powers of 2, table of F-l PR (PROGRAM RETURN) instruction 10-44 PR-cp (PROGRAM RETURN instruction, to current primary) 10-44 PR-ss (PROGRAM RETURN instruction, with space switching) 10-44 precision (floating-point) 9-1 preferred sign codes 8-2 prefetching (See also CCW prefetch control) access exceptions not recognized for 6-31 channel-control check during 16-31 channel-data check during 16-31 handling of invalid CBC in storage keys during 11-8 of ART-table and OAT-table entries 5-71 of data for I/O 15-26 of instructions 5-70 prefix 3-11 set by signal-processor order 4-35 store-status save area for 3-42 prenormalization 9-2 primary address space 3-13 primary ASN (PASN) 3-13 in linkage-stack state entry 5-60 primary AST entry (PASTE), origin (PASTEO) 5-21,5-36 primary authority 3-20 exception 6-22 primary interruption condition (I/O) 16-4 primary-list bit 5-36 primary segment table designation (PSTD) 3-24 length (PSTL) 3-25 origin (PSTO) 3-25 primary-space access-list designation (PSALD) 5-38 primary-space mode 3-24 primary space-switch event, control bit, in control register 1 3-24 primary-status bit (I/O) 16-17 primary virtual address 3-4 effective segment-table designation for 3-28 priority of access exceptions 6-34 of ASN-translation exceptions 6-38 of external-interruption conditions 6-10 of I/O interruptions 16-5 of interruptions (CPU) 6-39 of PER events 4-15 of program-interruption conditions 6-32 of trace exceptions 6-38 private bit 5-39 private-space-control bit 3-25 effect on fetch-protection override 3-9 low-address protection 3-10 use of common segments 3-26 home 3-25 primary 3-25 secondary 3-25 private-space facility D-2 privileged instructions 4-5 control 10-1 I/O 14-1 privileged-operation exception 6-22 problem state 4-5 bit in entry-table entry 5-23 bit in PSW 4-5 compatibility 1-4 processing backup (synchronous machine-check condition) 11-18 processing damage (synchronous machine-check condition) 11-19 processor (See CPU) program 5-30 channel (See channel program) exceptions 6-13 execution of 5-2 fields of SCHIB modifiable by 15-7 initial loading of 4-32,17-10 interruption 6-13 priority of 6-32 mask (in PSW) 4-6 PROGRAM CALL (PC) instruction 10-34 trace entry for 4-11 type of 5-53 program-call state entry 5-59,10-36 program check as subchanne! status 16-29 measurement-block 16-37 program-controlled interruption (I/O) (See PCI) program-event recording (See PER) program events (See PER events) program mask, validity bit for 11-21 PROGRAM RETURN (PR) instruction 10-44 program -status word (See PSW) PROGRAM TRANSFER (PT) instruction 10-47 trace entry for 4-11 protection (storage) 3-8 during tracing 4-12 fetch (See fetch protection) key-controlled (See key-controlled protection) low-address (See low-address protection) page (See page protection) protection check as subchannel status 16-30 measurement-block 16-37 protection exception 6-23 as an access exception 6-29,6-34 PSALD (primary-space access-list designation) 5-38 pseudo AST entry 3-14 PSTD (primary segment-table designation) 3-24 PSTL (primary segment-table length) 3-25 PSTO (primary segment-table origin) 3-25 PSW (program-status word) 2-2,4-3 assigned storage locations for 3-39 comparison of ESA/370 with 370-XA D-3 comparison of 370-XA with System/370 E-5 current 4-3,5-7 stored during interruption 6-2 exceptions associated with 6-8 format error 6-8 in linkage-stack state entry 5-60 in program execution 5-7 store-status save area for 3-42 validity bits for 11-20 PSW key 4-5 control bit 5-53 in entry-table entry 5-54 in trace entry 4-11 used as access key 3-8 validity bit for 11-20 PSW -key mask (PKM) 5-16 control bit 5-53 in linkage-stack state entry 5-59 PT (PROGRAM TRANSFER) instruction 10-47 PT-cp (PROGRAM TRANSFER instruction, to current primary) 10-48 PT-ss (PROGRAM TRANSFER instruction, with space switching) 10-48 PTL (page-table length) 3-26 PTLB (PURGE TLB) instruction 10-53 PTO (page-table origin) 3-26 publications, other related documents v PURGE ALB (PALB) instruction 10-52 PURGE TLB (PTLB) instruction 10-53 PX (page index) 3-23 Q queuing FIFO, example for lock and unlock A-46 LIFO, example for lock and unlock A-45 R R field of instruction 5-4 range (of floating-point numbers) 9-1 rate control 12-3 I RCHP (See RESET CHANNEL PATH instruction) read (I/O command) 15-35 read backward (I/O command) 15-36 real address 3-4 real mode 3-24 real storage 3-4 receiver check (signal-processor status) 4-39 reconfiguration of I/O system 17-12 recovery as class of machine-check condition 11-12 channel-subsystem 17-13 system 11-16 subclass-mask bit for 11-24 redundancy 11-2 reference bit in storage key 3-7 multiple-access 5-74 recording 3-10 sequence for storage 5-65 (See also sequence) Index X-21 single-access 5-74 register access 2-3 base-address 2-3 control 2-3 designation of 5-4 floating-point 2-3 general 2-3 index 2-3 prefix 3-11 save areas 3-42,11-22 validation of 11-10 validity bits for 11-21 vector-facility 2-4 remaining free space (in linkage stack) 5-57 remote operating stations 12-1 reporting-source code (RSC) 17-15 reporting-source ID (RSID) 17-16 repressible machine-check conditions 11-12 reset 4-27,17-6 channel-path 17-6 clear 4-31 CPU 4-30 effect on CPU state 4-2 effect on TOD clock 4-22 I/O-system 17-6 as part of subsystem reset 4-31 initial CPU 4-31 power on 4-32 subsystem 4-31 summary of functions 4-29 summary of functions performed by manual initiation of 4-28 system-reset-clear key 12-4 system-reset-normal key 12-5 RESET CHANNEL PATH (RCHP) instruction 14-7 (See also channel-path-reset function) function initiated by 15-43 RESET REFERENCE BIT EXTENDED (RRBE) instruction 10-53 reset signal (I/O) 17-6 in channel-path reset 17-6 in I/O-system reset 17-7,17-8 issued as part of RCHP 15-43 resolution . of clock comparator 4-25 of CPU timer 4-26 ofTOD clock 4-21 restart interruption 6-38 key 12-4 signal-processor order 4-35 result operand 5-3 resume function 13-8,15-17 (See also start function) initiated by RESUME SUBCHANNEL 14-8 path management for 15-18 pending 16-13 RESUME SUBCHANNEL (RSCH) instruction 14-8 (See also resume function) channel-program requirements for 14-9 count of in measurement block 17-3 function initiated by 15-17 X-22 ESA/370 Principles of Operation retry CPU 11-2 I/O command (See command retry) rounding (decimal) 8-11 example A-37 RR instruction format 5-4 RRBE (RESET REFERENCE BIT EXTENDED) instruction 10-53 RRE instruction format 5-4 RS instruction format 5-4 RSC (reporting-source code) 17-15 RSCH (See RESUME SUBCHANNEL instruction) RSID (reporting-source ID) 17-16 running (state ofTOD clock) 4-22 RX instruction format 5-4 S S (SUBTRACT) binary instruction 7-48 S instruction format 5-4 SAC (SET ADDRESS SPACE CONTROL) instruction 10-54 SAL (SET ADDRESS LIMIT) instruction 14-10 sample count (in ESW) 17-3 SAR (SET ACCESS) instruction 7-41 SASN (secondary address-space number) 3-13 in trace entry 4-11 save areas for registers 3-42,11-22 SCHIB (subchannel-information block) 15-1 as operand of MODIFY SUBCHANNEL 14-6 STORE SUBCHANNEL 14-15 model-dependent area in 15-7 path-management-control word (PMCW) in 15-2 subchannel-status word (SCSW) in 15-7 summary of modifiable fields in 15-7 SCHM (See SET CHANNEL MONITOR instruction) SCK (SET CLOCK) instruction 10-55 SCKC (SET CLOCK COMPARATOR) instruction 10-56 SCSW (subchannel-status word) 16-6 activity-control field in 16-13 CCW address in 16-18 count in 16-33 device-status field in 16-23 function -control field in 16-12 in IRB 16-6 in SCHIB 15-7 status-control field in 16-16 sub channel-control field in 16-11 sub channel-status field in 16-28 SD (SUBTRACT NORMALIZED) instruction 9-16 SDR (SUBTRACT NORMALIZED) instruction 9-16 SE (SUBTRACT NORMALIZED) instruction 9-16 secondary address space 3-13 secondary ASN (SASN) 3-13 control bit 5-54 in linkage-stack state entry 5-59 secondary authority 3-20 exception 6-24 secondary error (in subchannellogout) 16-38 secondary interruption condition (I/O) 16-4 secondary segment table designation (SSTD) 3-25 length (SSTL) 3-25 origin (SSTO) 3-25 secondary-space-control bit 3-24,5-17 secondary-space mode 3-24 secondary-status bit (I/O) 16-18 secondary virtual address 3-4 effective segment-table designation for 3-28 segment 3-23 segment index (SX) 3-23 segment-invalid bit (in segment-table entry) 3-26 segment table 3-26 lookup 3-30 segment-table designation (STD) 3-24 effective 3-28 home 3-25 obtaining of in access-register translation 5-29 primary 3-24 secondary 3-25 use after ART 5-40 segment-translation exception 6-24 as an access exception 6-29,6-34 self-describing block of I/O data 15-29 semiprivileged instructions 4-5 descriptions of 10-1 program authorization 5-15 summary of 5-19 programs 4-5,5-15 sense as I/O command 15-37 as signal-processor order 4-34 sense data 15-37 bus-out check 15-38 command reject 15-38 data check 15-38 equipment check 15-38 indication of 16-26 intervention required 15-38 overrun 15-38 sense ID (I/O command) 15-39 sequence conceptual 5-65 instruction -execution 5-2 of CCWs which is invalid 16-30 of storage references 5-65 ART-table and DAT-table entries 5-71 instructions 5-69 operands 5-72 storage keys 5-71 sequence code (in sub channel logout) 16-39 field-validity flag for 16-38 SER (SUBTRACT NORMALIZED) instruction 9-16 serialization 5-76 caused by I/O instructions 14-1 channel-program 5-77 CPU 5-76 in completion of store operations 5-72 service-processor damage 11-17 service processor inoperative (signal-processor status) 4-38 service-signal external interruption 6-12 subclass-mask bit for 6-12 SET ACCESS (SAR) instruction 7-41 SET ADDRESS LIMIT (SAL) instruction 14-10 SET ADDRESS SPACE CONTROL (SAC) instruction 10-54 SET CHANNEL MONITOR (SCHM) instruction 14-10 effect on measurement modes of 17-1 SET CLOCK (SCK) instruction 10-55 SET CLOCK COMPARATOR (SCKC) instruction 10-56 SET CPU TIMER (SPT) instruction 10-56 set prefix (signal-processor order) 4-35 SET PREFIX (SPX) instruction 10-56 SET PROGRAM MASK (SPM) instruction 7-41 SET PSW KEY FROM ADDRESS (SPKA) instruction 10-57 SET SECONDARY ASN (SSAR) instruction 10-58 use with access registers 5-33 set state (ofTOD clock) 4-22 SET STORAGE KEY EXTENDED (SSKE) instruction 10-61 SET SYSTEM MASK (SSM) instruction 10-61 SH (SUBTRACT HALFWORD) instruction 7-48 shared storage (See storage sharing) shared TOD clock 4-21 SHIFT AND ROUND DECIMAL (SRP) instruction 8-11 examples A-36 SHIFT LEFT DOUBLE (SLDA) instruction 7-42 example A-28 SHIFT LEFT DOUBLE LOGICAL (SLDL) instruction 7-42 SHIFT LEFT SINGLE (SLA) instruction 7-43 example A-29 SHIFT LEFT SINGLE LOGICAL (SLL) instruction 7-43 SHIFT RIGHT DOUBLE (SRDA) instruction 7-43 SHIFT RIGHT DOUBLE LOGICAL (SRDL) instruction 7-44 SHIFT RIGHT SINGLE (SRA) instruction 7-44 SHIFT RIGHT SINGLE LOGICAL (SRL) instruction 7-45 shifting, floating-point (See normalization) short floating-point number 9-2 short I/O block 16-28 SI instruction format 5-4 SID (subsystem -identification word) 14-1 assigned storage locations for 3-41 sign bit binary 7-2 floating-point 9-1 sign codes (decimal) 8-2 signal (I/O) 17-5 clear (See clear signal) halt (See halt signal) reset (See reset signal) SIGNAL PROCESSOR (SIGP) instruction 10-61 comparison of 370-XA with System/370 E-7 orders 4-34 status 4-37 signed binary arithmetic 7-3 Index X-23 comparison 7-4 integer 7-2 examples A -2 significance exception 6-24 loss 9-2 in floating-point addition 9-8 mask (in PSW) 4-6 starter (m EDIT) 8-7 SIGP (See SIGNAL PROCESSOR instruction) single-access reference 5-74 singie-path mode 15-3J5-20 size notation iv size of address 3-5 controlled by addressing mode 5-5 in CCW 15-24 skip flag in CCW 15-24 effect on data transfer of 15-30 SL (SUBTRACf LOGICAL) instruction 7-48 SLA (SHIFT LEFT SINGLE) instruction 7-43 example A -29 SLDA (SHIFT LEFT DOUBLE) instruction 7-42 example A -28 SLDL (SHIFT LEFT DOUBLE LOGICAL) instruction 7-42 . SLI (suppress-length-indication) flag in CCW 15-34 for immediate operations 15-37 SLL (SHIFT LEFT SINGLE LOGICAL) instruction 7-43 SLR (SUBTRACf LOGICAL) instruction 7-48 solicited interruption condition (I/O) 16-3 solid errors 11-5 sorting instructions (See COMPARE AND FORM CODEWORD instruction, UPDATE TREE instruction) source, vector-facility (machine-check condition) 11-18 source of interruption, identified by interruption code 6-5 SP (SUBTRACf DECIMAL) instruction 8-12 space-switch event 6-24 control bit home, in control register 13 3-25 in ASTE 3-16 primary, in control register 1 3-24 special-operation exception 6-25 specification exception 6-26 SPKA (SET PSW KEY FROM ADDRESS) instruction 10-57 SPM (SET PROGRAM MASK) instruction 7-41 SPT (SET CPU TIMER) instruction 10-56 SPX (SET PREFIX) instruction 10-56 SR (SUBTRACf) binary instruction 7-48 SRA (SHIFT RIGHT SINGLE) instruction 7-44 SRDA (SHIFT RIGHT DOUBLE) instruction 7-43 SRDL (SHIFT RIGHT DOUBLE LOGICAL) instruction 7-44 SRL (SHIFT RIGHT SINGLE LOGICAL) instruction 7-45 SRP (SHIFT AND ROUND DECIMAL) instruction 8-11 examples A-36 SS instruction format 5-4 SSAR (SET SECONDARY ASN) instruction 10-58 X-24 ESA/370 Principles of Operation use with access registers 5-33 SSAR-cp (SET SECONDARY ASN instruction, to current primary) 10-58 SSAR-ss (SET SECONDARY ASN instruction, with space switching) 10-58 SSCH (See START SUBCHANNEL instruction) SSE instruction format 5-4 SSKE (SET STORAGE KEY EXTENDED) instruction 10-61 SSM (SET SYSTEM MASK) instruction 10-61 SSM-suppression-control bit 6-25,10-61 SSTD (secondary segment-table designation) 3-25 SSTL (secondary segment-table length) 3-25 SSTO (secondary segment-table origin) 3-25 ST (STO RE) binary instruction 7-45 stack-empty exception 6-27 stack-full exception 6-27 stack-operation exception 6-27 stack-specification exception 6-27 stack-type exception 6-27 stacking process 5-60 stacking PROGRAM CALL 5-50 STAM (STORE ACCESS MULTIPLE) instruction 7-45 standalone dump 12-4 standard epoch (for TOD clock) 4-23 STAP (STORE CPU ADDRESS) instruction 10-63 start (CPU) function 4-2 key 12-4 signal-processor order 4-35 start function (I/O) 13-6,15-17 bit in SCSW for 16-12 initiated by START SUBCHANNEL 14-12 path management for 15-18 pending 16-14 START SUBCHANNEL (SSCH) instruction 14-12 (See also start function for I/O) count of in measurement block 17-3 deferred condition code for (in SCSW) 16-8 function initiated by 15-1 7 operation-request block (ORB) used by 15-21 state CPU (See CPU state) TO D-clock 4-22 state entry 5-59 status alert 16-16 device 16-23 effect of clear function on 15-14 field-validity flag for (in subchannellogout) 16-38 with inappropriate bit combination 16-38 device-status check 16-38 for SIGNAL PROCESSOR 4-34,10-62 initial, interruption (See initial-status-interruption control) intermediate 16-17 primary 16-17 program (See PSW) resulting from signal-processor orders 4-37 secondary 16-18 storing of 4-33 manual key for 12-4 sub channel 16-28 status-control field (in SCSW) 16-16 status modifier (device status) 16-23 effect of in command chaining 15-29 status-pending 16-18 status-verification facility E-2,17 -12 status while disabled 14-7 STC (STORE CHARACTER) instruction 7-45 STCK (STORE CLOCK) instruction 7-46 STCKC (STORE CLOCK COMPARATOR) instruction 10-63 STCM (STORE CHARACTERS UNDER MASK) instruction 7-46 examples A -29 STCPS (STORE CHANNEL PATH STATUS) instruction 14-14 STCRW (See STORE CHANNEL REPORT WORD instruction) STCTL (STORE CONTROL) instruction 10-63 STD (See segment-table designation) STD (STORE) floating-point instruction 9-16 STE (STORE) floating-point instruction 9-16 STH (STORE HALFWORD) instruction 7-47 STIDP (STORE CPU ID) instruction 10-64 STL (segment-table length) 3-24 STM (STORE MULTIPLE) instruction 7-47 example A-30 STNSM (STORE THEN AND SYSTEM MASK) instruction 10-65 STO (segment-table origin) 3-24 stop function 4-2 key 12-4 signal-processor order 4-35 stop and store status (signal-processor order) 4-35 stopped (signal-processor status) 4-38 stopped state of CPU 4-1 effect on completion of store operations 5-72 ofTOD clock 4-22 storage 3-1 absolute 3-4 address wraparound (See wraparound) addressing 3-2 (See also address) alteration manual controls 12-2 alteration PER event 4-17 mask for 4-13 assigned locations in 3-39 comparison of ESA/370 with 370-XA D-3 comparison of 370-XA with System/370 E-6 auxiliary 3-1,3-22 block 3-4 testing for usability of 10-69 buffer (cache) 3-1 clearing of (See clearing operation) concurrency of access for references to 5-74 configuration of 3-4 direct-access 3-1 display 12-2 error 11-19 indirect 11-20 failing address in (See failing-storage address) interlocked update 5-73 interlocks for virtual references 5-66 internal 2-2 main 3-1 noninterlocked update 5-73 nonvolatile 3-2 operand 5-5 reference to (fetch, store, update) 5-72 update reference 5-72 operand consistency 5-74 examples A -46,A -48 prefixing for 3-11 real 3-4 sequence of references to 5-65 size, notation for iv validation of 11-6 virtual 3-23 volatile 3-2 effect of power-on reset on 4-32 storage-access code (in· sub channel logout) 16-38 storage-area designation for I/O operations 15-25 for PER events 4-16 storage' degradation (machine-check condition) 11-19 storage key 3-7 error in 11-19 sequence of references to 5-71 testing for usability of 10-69 validation of 11-7 storage-logical-validity bit 11-21 storage protection 3-8 during tracing 4-12 storage sharing by address spaces 3-23 by CPUs and the channel subsystem 3-4 examples A -42 in multiprocessing 4-34 STO RE (ST) binary instruction 7-45 STORE (STD,STE) floating-point instructions 9-16 STORE ACCESS MULTIPLE (STAM) instruction 7-45 STORE CI-JANNEL PATH STATUS (STCPS) instruction 14-14 STORE CHANNEL REPORT WORD (STCRW) instruction 14-14 channel~report word (CRW) stored by 17-15 STORE CHARACTER (STC) instruction 7-45 STORE CHARACTERS UNDER MASK (STCM) instruction 7 -46 examples A-29· STORE CLOCK (STCK) instruction 7-46 STORE CLOCK COMPARATOR (STCKC) in'struction 10-63 STORE CONTROL (STCTL) instruction 10-63 STORE CPU ADDRESS (STAP) instruction 10-63 STORE CPU ID (STIDP) instruction 10-64 STORE CPU TIMER (STPT) instruction 10-64 STORE HALFWORD (STH) instruction 7-47 STORE MULTIPLE (STM) instruction 7-47 example A-30 STORE PREFIX (STPX) instruction 10-65 store reference 5-72 Index X-25 access exceptions for 6-32 store status 4-33 key 12-4 signal-processor order for 4-35 store status at address (signal-processor order) 4-36 STORE SUBCHANNEL (STSCH) instruction 14-15 STORE THEN AND SYSTEM MASK (STNSM) instruction 10-65 STORE THEN OR SYSTEM MASK (STOSM) instruction 10-65 STORE USING REAL ADDRESS (STURA) instruction 10-66 store-using-real-address PER event 4-18 mask for 4-13 STOSM (STORE THEN OR SYSTEM MASK) instruction 10-65 STPT (STORE CPU TIMER) instruction 10-64 STPX (STORE PREFIX) instruction 10-65 string of interruptions 4-3,6-39 caused by clock comparator 4-25 caused by CPU timer 4-26 STSCH (STORE SUBCHANNEL) instruction 14-15 STURA (STORE USING REAL ADDRESS) instruction 10-66 SU (SUBTRACT UNNORMALIZED) instruction 9-17 sub channel 13-2 active allegiance for 15-11 dedicated allegiance for 15-11 effect of I/O-system reset on 17-8 idle 16-13 working allegiance for 15-11 subchannel-active bit 16-15 subchannel addressing 13-5 sub channel control information in SCSW 16-11 sub channel enabled bit in PMCW 15-2 subchannel-information block (See SCHIB) subchannel key 15-21,16-8 used as access key 3-8 used for IPL 17-10 sub channel key check (in subchannel logout) 16-36 subchannel logout 16-36 subchannel number 13-5 sub channel status 16-28 generated while subchannel is disabled 14-7 subchannel-status word (See SCSW) subclass-mask bits 6-6 external-interruption 6-10 I/O-interruption (See I/O-interruption subclass mask) machine-check 11-23 subroutine linkage 5-8 subsystem-identification word (See SID) subsystem -linkage-control bit 5-17,5-21 in primary AST entry 5-21 subsystem reset 4-31 SUBTRACT (S,SR) binary instructions 7-48 SUBTRACT DECIMAL (SP) instruction 8-12 SUBTRACT HALFWORD (SH) instruction 7-48 SUBTRACT LOGICAL (SL,SLR) instructions 7-48 X-26 ESA/370 Principles of Operation SUBTRACT NORMALIZED (SD,SDR,SE,SER,SXR) instructions 9-16 SUBTRACT UNNORMALIZED (SU,SUR,SW,SWR) instructions 9-17 successful-branching PER event 4-16 mask for 4-13 SUPERVISOR CALL (SVC) instruction 7-49 supervisor-call interruption 6-38 supervisor state 4-5 support functions (I/O) 17-1 suppress-length-indication flag in CCW (See SLI) suppress-suspended-interruption control (I/O) 15-22,16-11 used for IPL 17-10 suppression exceptions to 5-14 of instruction execution 5-12 of unit of operation 5-13 SUR (SUBTRACr UNNORMALIZED) instruction 9-17 suspend-control bit 15-21,16-8 used for IPL 17-10 suspend flag in CCW 15-24 invalid 16-30 suspend function 13-8 suspended bit (in SCSW) 16-16 suspension of channel-program execution 15-32 effect on DCTI of 15-34 intermediate interruption condition for 16-17 SVC (SUPERVISOR CALL) instruction 7-49 SW (SUBTRACT UNNORMALIZED) instruction 9-17 swapping by COMPARE (DOUBLE) AND SWAP instructions 7-19 by EXCLUSIVE OR instruction 7-26 SWR (SUBTRACT UNNORMALIZED) instruction 9-17 SX (segment index) 3-23 SXR (SUBTRACT NORMALIZED) instruction 9-16 synchronization checkpoint 11-3 of CPU timer with TOO clock 4-26 of TOO clocks 4-22,4-24 synchronous machine-check -interruption conditions 11-18 system manual control of 12-1 organization of 2-1 system check stop 11-11 system damage .11-15 system mask (in PSW) 4-3 validity bit for 11-20 system recovery 11-16 system reset (See reset) I/O (See I/O-system reset) system-reset-clear key 12-4 system-reset-normal key 12-5 System/370 comparison with 370-XA E-l compatibility with ESA/370 1-4 T T (tera) iv table of powers of 2 F -1 tables ASN (See ASN first table, ASN second table) authority (See authority table) DAT (See page table, segment table) entry (See entry table) hexadecimal G-l linkage (See linkage table) page (See page table) segment (See segment table) trace 4-9 translation 3-26 TAR (fEST ACCESS) instruction 10-66 target instruction 7-26 TB (fEST BLOCK) instruction 10-69 termination of I/O operations (See conclusion of I/O operations) of instruction execution 5-12 for exigent machine-check conditions 11-11 of unit of operation 5-14 for exigent machine-check conditions 11-11 termination code (in subchannellogout) 16-38 field-validity flag for 16-38 TEST ACCESS (fAR) instruction 10-66 TEST AND SET (TS) instruction 7-49 TEST BLOCK (TB) instruction 10-69 test indicator 12-5 TEST PENDING INTERRUPTION (fPI) instruction 14-16 interruption code stored by 16-6 TEST PROTECTION (TPROT) instruction 10-71 TEST SUBCHANNEL (fSCH) instruction 14-17 interruption-response block (IRB)used by 16-6 TEST UNDER MASK (fM) instruction 7-50 examples A-30 testing for storage-block and storage-key usability 10-69 TI C (transfer in channel) 15-40 invalid sequence of 16-30 time-of-day clock (See TOO clock) timer (See CPU timer) timing, channel-subsystem 17-1 timing facilities 4-21 timing-facility bit (in PMCW) 15-4 timing-facility damage 11-16 for TOO clock 4-22 TLB (translation-Iookaside buffer) 3..31 entries 3-32 attachment of 3-32 clearing of 3-34 effect of translation changes on 3-33 usable state 3-32 summary 3-32 TM (TEST UNDER MASK) instruction 7-50 examples A-30 TOO clock 4-21 effect of power-on reset on 4-32 effect on clock-comparator interruption 6-10 effect on CPU-timer decrementing 4-26 effect on CPU-timer interruption 6-10 manual control of 4-22,12-5 unique values of 4-23 validation of 11-10 value in trace entry 4-12 TOO-clock sync check (external interruption) 6-12 TO D-clock -sync-control bit 4-22,4-25 TOD-clock-synchronization facility 4-24 TPI (See TEST PENDING INTERRUPTION instruction) TPROT (TEST PROTECTION) instruction 10-71 TR (fRANSLATE) instruction 7-50 example A-30 trace E-2,4-9 entries 4-10 entry address 4-9 exceptions 6-38 table exception 6-28 TRACE (fRACE) instruction 10-73 trace entry for 4-11 trailer entry 5-58 transfer in channel (See TI C) transferring program control 5-49 TRANSLATE (TR) instruction 7-50 example A -30 TRANSLATE AND TEST (TRT) instruction 7-51 example A-31 translation access-register (See access-register translation) address 3-22 (See also dynamic address translation) ASN (See ASN translation) exception identification 3-40 format 3-24 lookaside buffer (See TLB) modes 3-24 parameters 3-24 PC-number 5-21 specification exception 6-28 tables for 3-26 tree structure for sorting 7-52 trial execution for editing instructions and TRANSLATE instruction 5-15 for PER 4-14 TRT (T'RANSLATE AND TEST) instruction 7-51 example A -31 true zero (floating-point number) 9-1 TS (fEST AND SET) instruction 7-49 TSCH (See TEST SUBCHANNEL instruction) two's complement binary notation 7-2 examples A -2 type of PROGRAM CALL 5-53 U underflow (See exponent underflow) unit check (device status) 16-26 in establishing dedicated allegiance 15-11 unit exception (device status) 16-27 unit of operation 5-12 unlock A-45 example with FIFO queuing A-47 example with LIFO queuing A-46 Index X-27 unnormalized floating-point number 9-2 unnormalized-operand exception 6-28 UNPACK (UNPK) instruction 7-52 example A-33 UNPK (UNPACK) instruction 7-52 example A-33 unprivileged instructions 4-5,7-2 unsigned binary arithmetic 7-3 integer 7-2 examples A-4 in address generation 5-6 unsolicited interruption condition (I/O) 16-3 unstack-suppression bit 5-56 unstacking process 5-63 update reference 5-72 UPDATE TREE (UPT) instruction 7-52 UPT (UPDATE TREE) instruction 7-52 usable ALB entry 5-48 usable TLB entry 3-32 V valid ART-table entry 5-47 valid CBC 11-2 valid segment-table or page-table entry 3-32 validation 11-5 of registers 11-10 of storage 11-6 of storage key 11-7 ofTOD clock 11-10 validity bit for backward stack-entry address 5-58 validity bit for forward-section-header address 5-58 validity bits in machine-check -interruption code 11-20 in subchannellogout 16-38 variable-length field 3-2 vector facility 2-4 effect of power-on reset on 4-32 vector-facility failure (machine-check condition) 11-17 vector-facility source ,(machine-check condition) 11-18 vector-operation exception 6-28 vector operations, publication referenced v version code 10-64 virtual address 3-4 virtual storage 3-23 volatile storage 3-2 effect of power-on reset on 4-32 W WAIT (SVC), example of routine to bypass A-45 wait indicator 12-5 wait-state bit, in PSW 4-5 warning (machine-check condition) 11-17 subclass-mask bit for 11-24 word 3-3 X-28 ESA/370 Principles of Operation word-concurrent storage references 5-74 working allegiance (I/O) 15-11 wraparound of instruction addresses 5-5 of PER addresses 4-16 of register numbers for LOAD MULTIPLE instruction 7-31 for STORE MULTIPLE instruction 7-47 of storage addresses 3-5 comparison of 370-XA with System/370 for E-8 controlled by addressing mode 3-5 for MOVE INVERSE instruction 7-33 for MOVE LONG instruction 7-35 ofTOD clock 4-22 write (I/O command) 15-35 x X (EXCLUSIVE OR) instruction 7-25 X field of instruction 5-6 XA (extended architecture) (See 370-XA mode) XC (EXCLUSIVE OR) instruction 7-25 examples A -19 XI (EXCLUSIVE OR) instruction 7-25 example A -20 XR (EXCLUSIVE OR) instruction 7-25 Z Z bit (zero condition-code bit) 16-11 as cause of intermediate interruption condition 16-17 ZAP (ZERO AND ADD) instruction 8-12 example A-38 zero instruction-length code 6-7 negative (See negative zero) normal meaning for byte value v true (floating-point number) 9-1 ZERO AND ADD (ZAP) instruction 8-12 example A-38 zero condition code (Z bit in SCSW) 16-11 zone bits 8-1 moving of 7-38 zoned decimal numbers 8-1 examples A-5 3 370-XA comparison of facilities with System/370 E-l comparison with ESA/370 D-l 370-XA architecture 1-2 comparison of facilities with System/370, I/O 13-1 IBM Enterprise Systems Architecture/370 Principles of Operation READER'S COMMENT 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