SCHEM,MLB,KEPLER,2PHASE,D2 051 9851 A1398 820 3332 A

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK

APPD

2 1

1245678

B

D

6 5 4 3

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

D

SIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

SCHEM,MLB,KEPLER,2PHASE,D2

Schematic / PCB #’s

FSB, 5/9/2012

1 OF 99

2012-05-09

1 OF 132

4.18.0

051-9589

53

03/05/2012

D2_SEAN

Voltage & Load Side Current Sensing

45

52

01/13/2012

D2_KEPLER

SMBus Connections

44

51

01/13/2012

D2_KEPLER

LPC+SPI Debug Connector

43

50

01/13/2012

D2_KEPLER

SMC Support

42

49

01/13/2012

D2_KEPLER

SMC41

46

01/13/2012

D2_KEPLER

USB 3.0 CONNECTORS

40

45

01/13/2012

D2_KEPLER

SSD CONNECTOR

39

44

01/13/2012

D2_KEPLER

RIO CONNECTOR

38

01/13/2012

D2_KEPLER

Thunderbolt Power Support

37

01/13/2012

D2_KEPLER

Thunderbolt Host (2 of 2)

36

01/13/2012

D2_KEPLER

Thunderbolt Host (1 of 2)

35

01/13/2012

D2_KEPLER

X29/ALS/CAMERA CONNECTOR

34

01/13/2012

D2_KEPLER

DDR3/FRAMEBUF VREF MARGINING

33

01/13/2012

D2_KEPLER

DDR3 Termination

32

01/13/2012

D2_KEPLER

DDR3 SDRAM Bank B (2 OF 2)

31

01/13/2012

D2_KEPLER

DDR3 SDRAM Bank B (1 OF 2)

30

01/13/2012

D2_KEPLER

DDR3 SDRAM Bank A (2 OF 2)

29

01/13/2012

D2_KEPLER

DDR3 SDRAM Bank A (1 OF 2)

28

01/13/2012

D2_KEPLER

CPU Memory S3 Support

27

01/13/2012

D2_KEPLER

USB HUB & MUX

26

01/13/2012

D2_KEPLER

Chipset Support

25

01/13/2012

D2_KEPLER

CPU & PCH XDP

24

03/19/2012

D2_CLEAN

PCH DECOUPLING

23

01/13/2012

D2_KEPLER

PCH GROUNDS

22

03/19/2012

D2_CLEAN

PCH POWER

21

01/13/2012

D2_KEPLER

PCH GPIO/MISC/NCTF

20

01/13/2012

D2_KEPLER

PCH PCI/USB/TP/RSVD

19

01/13/2012

D2_KEPLER

PCH DMI/FDI/PM/Graphics

18

01/13/2012

D2_KEPLER

PCH SATA/PCIe/CLK/LPC/SPI

17

03/05/2012

D2_SEAN

CPU DECOUPLING-II

16

03/05/2012

D2_SEAN

CPU DECOUPLING-I

15

14

01/13/2012

D2_KEPLER

CPU POWER AND GND

14

13

01/13/2012

D2_KEPLER

CPU POWER

13

12

01/13/2012

D2_KEPLER

CPU DDR3 INTERFACES

12

11

01/13/2012

D2_KEPLER

CPU CLOCK/MISC/JTAG

11

10

01/13/2012

D2_KEPLER

CPU DMI/PEG/FDI/RSVD

10

9

01/13/2012

D2_KEPLER

Signal Aliases

9

8

01/13/2012

D2_KEPLER

Power Aliases

8

7

01/13/2012

D2_KEPLER

Functional / ICT Test

7

6

01/13/2012

D2_KEPLER

BOM Variants

6

5

01/13/2012

D2_KEPLER

BOM Configuration

5

4

01/13/2012

D2_KEPLER

Revision History

4

3

01/13/2012

D2_KEPLER

Power Block Diagram

3

2

01/13/2012

D2_KEPLER

System Block Diagram

2

Memory Constraints

D2_KEPLER

01/13/2012

101

90

CPU Constraints

D2_KEPLER

01/13/2012

100

89

Power Sequencing EG/PCH S0

D2_KEPLER

01/13/2012

99

88

PCH VCCIO (1.05V) POWER SUPPLY

D2_KEPLER

01/13/2012

98

87

LCD Backlight Driver (LP8545)

D2_KEPLER

01/13/2012

97

86

Thunderbolt Connector B

D2_KEPLER

01/13/2012

96

85

Thunderbolt Connector A

D2_KEPLER

01/13/2012

94

84

eDP Muxed Graphics Support

D2_SEAN

03/05/2012

92

83

eDP Mux

D2_SEAN

03/05/2012

91

82

eDP Display Connector

D2_KEPLER

01/13/2012

90

81

GFX IMVP VCore Regulator

D2_SEAN

03/05/2012

89

80

KEPLER PEX PWR/GNDS

D2_SEAN

03/05/2012

88

79

KEPLER GPIOS,CLK & STRAPS

D2_SEAN

03/05/2012

87

78

KEPLER EDP/DP/GPIO

D2_SEAN

03/05/2012

86

77

GDDR5 Frame Buffer B

D2_SEAN

03/05/2012

85

76

GDDR5 Frame Buffer A

D2_SEAN

03/05/2012

84

75

1V05 GPU / 1V35 FB POWER SUPPLY

D2_SEAN

03/05/2012

83

74

KEPLER FRAME BUFFER I/F

D2_SEAN

03/05/2012

82

73

KEPLER CORE/FB POWER

D2_SEAN

03/05/2012

81

72

KEPLER PCI-E

D2_KEPLER

01/13/2012

80

71

Power Control 1/ENABLE

D2_KEPLER

01/13/2012

79

70

Power FETs

D2_KEPLER

01/13/2012

78

69

Misc Power Supplies

D2_KEPLER

01/13/2012

77

68

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

D2_KEPLER

01/13/2012

76

67

CPU IMVP7 & AXG VCore Output

D2_SEAN

03/05/2012

75

66

CPU IMVP7 & AXG VCore Regulator

D2_SEAN

03/05/2012

74

65

1V5R1V35V DDR3 SUPPLY

D2_KEPLER

01/13/2012

73

64

5V / 3.3V Power Supply

D2_KEPLER

01/13/2012

72

63

System Agent Supply

D2_KEPLER

01/13/2012

71

62

PBus Supply & Battery Charger

D2_KEPLER

01/13/2012

70

61

DC-In & Battery Connectors

D2_KEPLER

01/13/2012

69

60

AUDIO: JACK TRANSLATORS

D2_CARA

03/16/2012

68

59

AUDIO: JACK

D2_CARA

03/16/2012

67

58

AUDIO: SPEAKER AMP

D2_CARA

03/16/2012

66

57

AUDIO: IV SENSE FILTER

D2_CARA

03/16/2012

65

56

AUDIO: IV SENSE

D2_CARA

03/16/2012

64

55

AUDIO: HEADPHONE FILTER

D2_CARA

03/16/2012

63

54

AUDIO: CODEC/REGULATOR

D2_CARA

03/16/2012

62

53

SPI ROM

D2_KEPLER

01/13/2012

61

52

DIGITAL ACCELEROMETER & GYRO

D2_KEPLER

01/13/2012

59

51

KEYBOARD/TRACKPAD (2 OF 2)

D2_KEPLER

01/13/2012

58

50

KEYBOARD/TRACKPAD (1 OF 2)

D2_KEPLER

01/13/2012

57

49

Fan Connectors

D2_KEPLER

01/13/2012

56

48

Thermal Sensors

D2_SEAN

03/05/2012

55

47

D2_KEPLER

01/13/2012

99

SMC12 SENSORS EXTENDED

132

D2_SEAN

03/05/2012

98

DEBUG SENSORS AND ADC

130

D2_KEPLER

01/13/2012

97

PCB Rule Definitions

109

D2_CLEAN

03/15/2012

96

Project Specific Constraints

108

D2_KEPLER

01/13/2012

95

GPU (Kepler) CONSTRAINTS

107

D2_KEPLER

01/13/2012

94

SMC Constraints

106

D2_KEPLER

01/13/2012

93

Thunderbolt Constraints

105

D2_KEPLER

01/13/2012

92

PCH Constraints 2

103

SCHEM,MLB,KEPLER_2PHASE,D2

CRITICAL

SCH1

051-9589

High Side and CPU/AXG Current Sensing

D2_SEAN

03/05/2012

54

46

SyncPage

Date

Contents

(.csa)

D2_KEPLER

01/13/2012

91

PCH Constraints 1

102

Date

(.csa)

Contents

SyncPage

1

01/13/2012

D2_KEPLER

Table of Contents

1

ABBREV=ABBREV

TITLE=MLB

LAST_MODIFIED=Wed May 9 13:50:52 2012

Contents

(.csa)

Date

SyncPage

PCBF,MLB,KEPLER_2PHASE,D2

CRITICAL

1

820-3332

PCB

SCHEM,MLB,KEPLER,2PHASE,D2

苹果笔记本维修交流群群号：３２５７４２６３４

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

POWER SUPPLY

PG 63

DC/BATT

TEMP SENSOR

J6950

U4900

PG 23

SPI

Boot ROM

U6100

XDP CONN

J2500,J2550

J2900

DIMM

PG 26,28

J3100

PG 16

DDR3-1067/1333MHZ

2 DIMMS

RTC

DMI

PG 17

PG 44

PG 51

PG 44

POWER SENSE

FAN CONN AND CONTROL

J5650,5660

Fan

CONNECTION

SMBUS

PG 47

PG 63

SPEATKER

TRACKPAD/KEYBOARD

U6610,6620,6630

SPEATKER

Ser ADC

PG 44

SMC

BSBB,0

J3402

U4900

Prt

PG 55

PG 46

U3600

CAMERA

PG 33

PG 41

PG 31

EXTERNAL B

EXTERNAL C

J4501

J4610

PG 34

PG 31

PG 53

BLUETOOTH

EXTERNAL A

J5713

J3401

J4600

USB

HUB 2

PG 33

HUB 1

USB

PG 34

U3700

LPC + SPI CONN

Port80,serial

J5100

PG 19

Misc

SPI

PG 16

LPC

PG 16

PWR

10 11 1312

98654 73210

CTRL

PG 17

(UP TO 14 DEVICES)

PG 18

USB

AUDIO

PG 56

DIMM

PG 26,28

U6201

AMP

PG 59

PG 60

FILTER

PG 58

AUDIO

CONN

PG 57

J6700,J6750

LINE TIN

FILTER

PG 16

SMB

HDA

J3500

PG 37

CONN

(UP TO 16 LINES)

SDCARD READER

U1800

2.X GHZ

INTEL CPU

INTEL

MOBILE

PG 9

PG 17

FDI

PG 19

GPIO

GRAPHICS

AMD WHISTLER

U8000

PG 73

U2700

CLOCK

SATA3.0/6(GB/S)

SATA2.0/3(GB/S)

BUFFER

PG 16

4 5

SATA

2 3

PG 16

10

DP OUT

RGB OUT

HDMI OUT

LVDS OUT

DVI OUT

PG 18

TMDS OUT

PCI

PG 18

PG 24

PG 41

CK5G05

CONN

SATA

J4501

ODD

PG 41

SATA

CONN

J4500

HDD

PG 83

DP MUX

XP25-5G

PG 84

JTAG

PCI-E

PG 16

PEG

PG 16

BCM57765

GB

PG 36

E-NET

CONN

PG 37

E-NET

J4000

U3900

PG 38

PG 40

CONN

FIREWIRE

FW643

PG 83

DDC MUX

PG 86

GMUX

U4100

J4310PG 31

AirPort

J3401

MINI DP PORT

LCD PANEL

U9600

U9320

U9370

J9400

IR

(RESERVATION)

CODEC

HEADPHONE

CLK

PANTHER-POINT

IVY BRIDGE

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

System Block Diagram

051-9589

4.18.0

2 OF 132

2 OF 99

苹果笔记本维修交流群群号：３２５７４２６３４

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

D2 POWER SYSTEM ARCHITECTURE

CPUVTTS0_PGOOD

VOUT

REF3333

(PAGE 45)

SMC AVREF SUPPLY

VOUT

PGOOD

1.05V

ISL95870

VIN

SMC_RESET_L

(PAGE 70)

U7600

SMC PWRGD

NCP303LSN

VIN

EN

PP5V_S0_CPUVTTS0

(PAGE 45)

U5000

CPUVTTS0_EN

SMC_GPU_VSENSE

PPVCORE_GPU

PP3V42_G3H

V

GPUVCORE_PGOOD

A

U5410

SMC_GPU_ISENSE

(PAGE 62)

PM6640

ENABLE

3.425V G3HOT

U6990

VOUT

PGOOD

U8900

VIN

ISL6263C

GPU VCORE

Q5315

V

VDD

VR_ON

SMC_PBUS_VSENSE

GPUVCORE_EN

PP5V_S3_GFXIMVP6_VDD

PPBUS_G3H

PM_PCH_PWRGD

U2850

PP4V5_AUDIO_ANALOG

SMC_CPU_VSENSE

PPVCORE_S0_CPU

SMC_CPU_DDR_VSENSE

V

U5440

V

VOUT

U7980

PM_ALL_GPU_PGOOD

MAX8840

4.5V

PP1V5_S3

EN

PP3V3_S0

ALL_SYS_PWRGD

Q7880

RSMRST_PWRGD

SMC_ONOFF_L

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_S4_L

PP3V3_S0_PWRCTL

ISL88042IRTJJZ

S0PGOOD_PWROK

VCC

PP3V3_S0

PP1V8_GPUIFPX

PP3V3_S0

V2MON

RST*

U7971

(PAGE 72)

TRST = 200mS

V3MON

V4MON

PP1V5_S0

PP1V05_S0

SMC_CPU_ISENSE

A

SMC_DDR_ISENSE

R7350

CPUIMVP7_AXG_PGOOD

PP3V3_ENET

Q7850

P1V8GPUIFPXFET_GATE

PP1V2_S0

P1V2S0_EN

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

PP1V8_S0

VOUT

PGOOD

ISL95831

U7400

(PAGE 67)

CPU VCORE

VIN

VR_ON

A

P5VS0_EN

PP5V_S0

PPDDR_S3_REG

PPVTT_S0_DDR_LDO

Q7860

VOUT2

VLDOIN

VOUT1

PGOOD

PP1V5_S3RS0

PP5V_S3_DDRREG

VIN

A

R5388/U5388

CPUIMVP7_VR_ON

0.75V

1.5V

TPS51116

Q7801

P1V5S0FET_GATE

U7300

(PAGE 66)

SMC_CPU_HI_ISENSE

S5

S3

PP3V3_S5

PP1V5_S3

G

U7801

VIN

PP3V3_S5

PP5V_S3

DDRREG_EN

DDRVTT_EN

SLG5AP020

ON

VOUT2

VOUT1

VREG5

P1V5CPU_EN

(L/H)

(R/H)

3.3V

5V

VIN

G

U7880

SLG5AP020

VIN

Q7922

ON

FW_PWR_EN

P1V8FB_EN

PP3V3_FW_FWPHY

U4201

TPS22924

(PAGE 39)

EN

PP1V8_S0

P1V8S0_PGOOD

P1V2ENET_PGOOD

PP1V2_ENET

PGOOD

VOUT

(PAGE 70)

U7720

ISL8014A

VIN

ISL8014A

VOUT

PGOOD

(PAGE 70)

U7760

EN

PP3V3_S0GPU

P1V2ENET_EN

P3V3S3_EN

EN

P3V3S0_EN

PP3V3_S0_FET

PP3V3_S3

Q7810

Q7870

Q7830

U7201

P1V8_S0_EN

D6990

PPBUS_G3H

PGOOD

(PAGE 65)

PP1V0_S0GPU_REG

PPVOUT_S0_LCDBKLT

P5V3V3_PGOOD

P1V0GPU_PGOOD

P1V5FB_PGOOD

TPS51125

PP1V5_GPU_REG

SMC_GPU_1V8_ISENSE

F7040

8A FUSE

A

R7050

PPVBAT_G3H

SMC_BATT_ISENSE

VOUT

R6990

ISL6259HRTZ

U7000

PBUS SUPPLY/

BATTERY CHARGER

PP18V5_DCIN_CONN

R7020

VIN

A

SMC_RESET_L

SMC_DCIN_ISENSE

F6905

6A FUSE

DCIN(16.5V)

J6900

IN

(PAGE 64)

R5413

A

VOUT1

POK1

VOUT2

EN1

EN2

POK2

1.003V(L/H)

P3V3S5_EN

(PAGE 85)

1.503V(R/H)

P5VS3_EN

VIN

EN1

ISL6236

EN2

Q9806

U9500

P1V0GPU_EN

PPVBAT_G3H_CHGR_R

P1V5FB_EN

Q7055

GPUVCORE_EN

P3V3GPU_EN

P1V1GPU_EN

P3V3S5_EN

VOUT

VIN

LP8550

PFWBOOST

U9701

(PAGE 87)

ENA

BKLT_EN

Q4260

LCD_BKLT_NO

BKLT_PLT_RST_L

SMC_ADAPTER_EN&&PM_SLP_S3_L

&&

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

PM_SLP_S3_L_R

P5VS3_EN

DDRREG_EN

P3V3S3_EN

PM_ALL_GPU_PGOOD

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

PPVBATT_G3H_CONN

EG_RAIL1_EN

EG_RAIL3_EN

EG_RAIL2_EN

J6950

(9 TO 12.6V)

PB16B

PB17B

PB17A

U9600

GMUX

PB18A

EG_RAIL4_EN

XP25-5

DELAY

RC

SLP_S5#(E4)

SMC_PM_G2_EN

PL32A

U4900

(PAGE 86)

SMC

P60

(PAGE 44)

MOBILE

RC

DELAY

SLP_S4#(H7)

SLP_S3#(P12)

(PAGE 16~21)

U1800

R7978

P1V2S0_EN

P1V8S0_EN

P1V5CPU_EN

CPUVTTS0_EN

RC

DELAY

RC

DELAY

RC

DELAY

PP1V0_FW_FWPHY

PP3V3_S5_SMC

U5001

(PAGE 39)

TPS22924

U4202

FW_PWR_EN

EN

PM_PWRBTN_L

PM_MEM_PWRGD

CPU_PWRGD

PLT_RERST_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PM_SYSRST_L

CPUIMVP_VR_ON

PM_RSMRST_L

SMC_RESET_L

RSMRST_OUT(P15)

SMC_CPU_FSB_ISENSE

PPCPUVTT_S0

(PAGE 16~21)

SYS_RERST#

PWRBTN#

SM_DRAMPWROK

RESET*

(P64)

PP3V3_S5_AVREF_SMC

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

RES*

PLTRST#

SMC_ONOFF_L

SMC_TPAD_RST_L

DRAMPWROK

PROCPWRGD

A

R7640

CPUVTTS0_PGOOD

VOUT

REF3333

(PAGE 45)

SMC AVREF SUPPLY

VOUT

PGOOD

1.05V

ISL95870

SMC_RESET_L

(PAGE 70)

U1800

PS_PWRGD

PM_PCH_PWRGD

U2850

U1000

CPU

SMC

(PAGE 9~14)

PP4V5_AUDIO_ANALOG

ALL_SYS_PWRGD

PWR_BUTTON(P90)

RSMRST_IN(P13)

PWRGD(P12)

H8S2117

SLP_S5_L(P95)

U4900

SLP_S3_L(P93)

SLP_S4_L(P94)

(PAGE 45)

RSMRST_PWRGD

SMC_ONOFF_L

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_S4_L

U6200

VIN

CHGR_BGATE

ADAPTER

AC

P5V3V3_PGOOD

P1V8S0_PGOOD

PP3V3_S0_PWRCTL

(PAGE 82)

DDRREG_PGOOD

P3V3GPU_EN

ACPRESENT

RSMRST#

VCCCPUPWRGD

3S2P

PANTHER-POINT

PANTHER_POINT

Power Block Diagram

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

051-9589

4.18.0

3 OF 132

3 OF 99

www.qdzbwx.com

苹果笔记本维修交流群群号：３２５７４２６３４

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Revision History

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

051-9589

4.18.0

4 OF 132

4 OF 99

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PD Parts

Alternate Parts

BOM Variants (continued on CSA 6)

Module Parts

Bar Code Labels / EEEE #’s (continued on CSA 6)

DRAM SPD Straps

Programmables

DRAM VREF Configs

DEVELOPMENT/BASE BOM

SMC

EFI ROM

BOM Groups

085-4776

D2_DEVEL:FSB

085-3726

D2_DEVEL:ENG

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

BOM Configuration

128S0264

ALL

128S0257

353S3527

Pericom eDP MUX

353S3528

ALL

TI eDP MUX

ALL

353S3526 353S3528

Diodes alt to Toshiba

376S0613

ALL

376S0855

376S0855 376S0613

Diodes alt to Toshiba

ALL

VREFDQ:M1_M3

ALL

376S0796376S0903

Fairchild alt to Siliconix

ALL

Diodes alt to On Semi

376S1076

376S0977

ALL

376S0859

Diodes alt to Toshiba

376S1053

ALL

376S0604

Diodes alt to Fairchild

128S0311

ALL

NEC alt to Sanyo

138S0739 138S0706

ALL

Samsung alt to Murata

197S0435 197S0343

ALL

NDK Alt to TXC

197S0434 197S0343

ALL

Epson Alt to TXC

ALL

197S0431

NDK Alt to Epson

Epson Alt to TXC

ALL

197S0181197S0452

NDK Alt to TXC

ALL

197S0453 197S0181

D2,MLB,KEPLER,FSB DEV

D2,MLB,KEPLER,DEV

D2,MLB,KEPLER_2PHASE,COMMON

607-9546

639-3379

PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W

639-3378

639-3380

639-3384

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600

639-3381

639-3385

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600

639-2821

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600

639-3386

PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600

639-3387

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600

639-2825

639-2817

639-2815

639-2979

639-2981

PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F

639-2980

639-2982

639-3618

639-3561

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600

639-3619

639-3620

639-3628

639-3562

639-3627

639-3629

D2_COMMON2

D2_COMMON1

D2_COMMON

D2_PVB

D2_DEVEL:ENG

D2_PROGPARTS

D2_DEVEL:FSB

IVB_PPT_XDP

CPU_IVY:2_3GHZ

1

CRITICAL

U1000

337S4266

1

337S4268

1

U1000

337S4267

1

U1800

337S4269

IC,GPU,NV GK107-GTX-PS-A2

1

U8000

U3600

1

338S1113

333S0622

32

2G_HYNIX_1600

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

32

333S0623

333S0628

32

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

333S0624

32

CRITICAL

333S0630

4

CRITICAL

IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX

333S0629 CRITICAL

32

PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2

685-0016

685-0017

PBUS_CAP:KEMET

IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG

IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM

IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP

IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA

IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT

PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4

PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44

PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D

PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C

PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43

PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40

PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y

PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V

CRITICAL

U1000

341S3564

ALL

341S3565

Avnet eDP MUX alt to Renesas

107S0232

Cyntec alt to TFT

ALL

107S0129

Epson alt to NDK

197S0466 197S0464

ALL

Panasonic alt to TDK

155S0583155S0667

152S0461

Cyntec alt to Vishay

ALL

152S1645

ALL

376S1080 376S0820

Diodes alt to On Semi

ALL

377S0066

DDS alt to ST

ALL

371S0713

ALL

NXP alt to infineon

371S0652

377S0126 377S0066

ALL

New Semtech package

ALL

376S0975

Toshiba alt to diodes

376S1081

371S0709

Sanyo POSCAP/Mylar alt to Kemet

685-0016685-0017

ALL

CRITICAL

1

725-1648

PBUS_CAP:KEMET

CRITICAL

725-1568

1

725-1569 CRITICAL

1

725-1621 CRITICAL

806-2897

CAN,COVER,2,J5

2

CRITICAL

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

CRITICAL

IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG

CRITICAL

4

333S0631

PBUS_CAP:SANYO

CRITICAL

PBUS_CAP:KEMET

128S0257

CRITICAL

TBTRTR:PRQ

2G_SAMSUNG_1600

PBUS_CAP:SANYO

FB_2G_HYNIX_A_DIE

4G_ELPIDA_1600

4G_SAMSUNG_1600

4G_HYNIX_1600

2G_ELPIDA_1600

CRITICAL

XDP_CONN,XDP_PCH

ALTERNATE,IVB_PPT_XDP

SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG

VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N

CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO

ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB

PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM

PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600

PBUS_CAP:SANYO

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600

ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV

CPU_IVY:2_6GHZ

CPU_IVY:2_7GHZ

FB_2G_SAMSUNG

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600

D2_COMMON,POSCAP_MYLAR_PAIR

[EEEE:DY3V]

CRITICAL825-7563

1

EEEE:DY3V

LABEL,MLB/LIO,MBA

[EEEE:DY3W]

825-7563 CRITICAL

EEEE:DY3W

1

LABEL,MLB/LIO,MBA

[EEEE:DY40]

LABEL,MLB/LIO,MBA

CRITICAL

EEEE:DY40

825-7563

1

825-7563

EEEE:DY3Y

1

[EEEE:DY3Y]

CRITICAL

[EEEE:DY43]

EEEE:DY43

1

825-7563 CRITICAL

LABEL,MLB/LIO,MBA

825-7563

1

CRITICAL

[EEEE:DY45]

LABEL,MLB/LIO,MBA

EEEE:DY44

[EEEE:DY44]

CRITICAL

1

825-7563

1

[EEEE:DY4C]

CRITICAL

LABEL,MLB/LIO,MBA

1

[EEEE:DRF1]

CRITICAL825-7563

LABEL,MLB/LIO,MBA

[EEEE:DRF4]

CRITICAL

1

825-7563

LABEL,MLB/LIO,MBA

EEEE:DRDN

CRITICAL

1

825-7563

[EEEE:DRDN]

LABEL,MLB/LIO,MBA

1

[EEEE:DRDW]

CRITICAL825-7563

LABEL,MLB/LIO,MBA

825-7563

1

EEEE:DT9D

[EEEE:DT9D]

CRITICAL

LABEL,MLB/LIO,MBA

825-7563

1

[EEEE:DT9F]

CRITICAL

1

825-7563

[EEEE:DT9H]

CRITICAL

825-7563

LABEL,MLB/LIO,MBA

1

CRITICAL

[EEEE:DT9G]

LABEL,MLB/LIO,MBA

825-7563

EEEE:F0HR

[EEEE:F0HR]

CRITICAL

1

LABEL,MLB/LIO,MBA

825-7563

EEEE:F0HN

[EEEE:F0HN]

1

CRITICAL

LABEL,MLB/LIO,MBA

825-7563

[EEEE:DYW4]

CRITICAL

1

EEEE:DYW4

825-7563

LABEL,MLB/LIO,MBA

EEEE:F0HV

[EEEE:F0HV]

1

CRITICAL

LABEL,MLB/LIO,MBA

825-7563

EEEE:F0HM

[EEEE:F0HM]

CRITICAL

1

[EEEE:DYW5]

CRITICAL

LABEL,MLB/LIO,MBA

825-7563

1

EEEE:DYW5

LABEL,MLB/LIO,MBA

825-7563

EEEE:F0HT

[EEEE:F0HT]

CRITICAL

1

EEEE:F0HY

LABEL,MLB/LIO,MBA

[EEEE:F0HY]

CRITICAL

1

IC,TRKPD/KYBD CNTRLR,DVB,D2

1

341S3584 CRITICAL

U5701

TPAD_PSOC:PROG

U5701

IC,TP PSOC,QFN,BLANK

337S2983

TPAD_PSOC:BLANK

1

CRITICAL

1

CRITICAL

U3690

TBTROM:PROG

EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

335S0865

U3690

TBTROM:BLANK

CRITICAL

1

IC,GPU ROM,D2,BLANK

335S0852

U8701

1

GPUROM:BLANK

CRITICAL

IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2

341S3565

1

U9100

CRITICAL

DPMUXMCU:PROG

CRITICAL

DPMUXMCU:BLANK

1

U9100

VREFDQ:M1_M3,VREFCA:LDO

VREFDQ:M1_M3,VREFCA:LDO_DAC

VREF:ENG_M3

VREFDQ:M1_DAC,VREFCA:LDO_DAC

VREF:ENG_LDO

RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM_1G_SAMSUNG_1600

RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_4G_SAMSUNG_1600_S

RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_1G_HYNIX_1600

RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1600_S

2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_2G_SAMSUNG_1600

2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_2G_HYNIX_1600

RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_2G_SAMSUNG_1333

4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_SAMSUNG_1600

RAM_2G_ELPIDA_1600

2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_2G_ELPIDA_1600_S

4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM_4G_HYNIX_1600

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1600

RAM_2G_HYNIX_1600_S

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_2G_SAMSUNG_1600_S

CRITICAL

1

685-0016

PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

POSCAP_MYLAR

POSCAP_MYLAR_PAIR

D2 MLB KEPLER 2PHASE BASE BOM

BASE CRITICAL607-9546 BASE_BOM

1

CRITICAL085-4776

DEVEL_FSB_BOM

DEVEL_FSB

D2 MLB KEPLER FSB DEVEL BOM

D2 MLB KEPLER DEVEL BOM

DEVEL

DEVEL_BOM

CRITICAL

1

085-3726

LABEL,MLB/LIO,MBA

128S0329

IC,MCU,H8S/2113,9X9MM,TLP-145V

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600

PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW

PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600

LABEL,MLB/LIO,MBA

Kemet alt to Sanyo

376S0634

EEEE:DRF4

371S0558

197S0432

EEEE:DY45

EEEE:DY4C

EEEE:DRF1

EEEE:DRDW

EEEE:DT9H

EEEE:DT9F

EEEE:DT9G

On Semi alt to Semtech

377S0147

PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1

PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN

PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H

PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G

PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN

PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR

PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5

PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY

EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5

825-7563

337S4313

VREF:PROD

RAM_4G_HYNIX_1600_S

341S3597

IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2

U4900

CRITICAL

1

IC,SMC,DEVELOPMENT-FSB,A3,D2

341S3308

SMC_PROG:FSB

1

CRITICAL

U4900

341S3595

1

BOOTROM_PROG:FSB

CRITICAL

U6100

IC,EFI,ROM,FSB, D2

341S3309

IC,SMC,PVB,A3,2.2F36,D2

SMC_PROG:PVB

IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA

337S4256

1

CRITICAL

946-3819

CRITICAL

1

CRITICAL825-7697

TEXT,LABEL,MLB,D2

LBL,PART CONFIG,BOARDS,D2

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

CONFIG_LABEL

EDGE_BOND

TEXT_LABEL

CAN_COVER1,CAN_COVER2

PCH_INSULATOR

GPU_INSULATOR

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

725-1614

128S0264

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

INSULATOR,GPU,D2

INSULATOR,PCH,D2

825-7841

333S0625

1

INSULATOR,SHORT,REAR,MLB,D2

INSULATOR,TALL,REAR,MLB,D2

INSULATOR,CPU,D2

U8400,U8450,U8500,U8550

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

REAR_INSULATOR

CRITICAL

U8400,U8450,U8500,U8550

REAR_INSULATOR

CPU_INSULATOR

30

C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821

051-9589

4.18.0

5 OF 132

5 OF 99

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Keeping for PRQ

Elipda DQ’d

BOM Variants (continued from CSA 5)

Bar Code Labels / EEEE #’s (continued from CSA 5)

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

BOM Variants

639-3383

PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600

639-3382

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600

PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600

639-3445

PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600

639-3446

PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6

LABEL,MLB/LIO,MBA

[EEEE:DY41]

825-7563

1

EEEE:DY41

CRITICAL

[EEEE:DYJ6]

LABEL,MLB/LIO,MBA

EEEE:DYJ6

CRITICAL

1

825-7563

LABEL,MLB/LIO,MBA

825-7563 CRITICAL

[EEEE:DY42]

1

EEEE:DY42

[EEEE:DYJ5]

LABEL,MLB/LIO,MBA

EEEE:DYJ5

CRITICAL825-7563

1

CRITICAL

EEEE:DRF0

1

825-7563

[EEEE:DRF0]

LABEL,MLB/LIO,MBA

1

EEEE:DRDP

CRITICAL825-7563

[EEEE:DRDP]

LABEL,MLB/LIO,MBA

1

EEEE:DRDT

CRITICAL

[EEEE:DRDT]

825-7563

LABEL,MLB/LIO,MBA

CRITICAL

1

[EEEE:DRDQ]

EEEE:DRDQ

825-7563

LABEL,MLB/LIO,MBA

1

CRITICAL

[EEEE:F0J4]

EEEE:F0J4

825-7563

LABEL,MLB/LIO,MBA

CRITICAL

1

[EEEE:F0JD]

EEEE:F0JD

825-7563

LABEL,MLB/LIO,MBA

1

CRITICAL

[EEEE:F0J3]

EEEE:F0J3

825-7563

LABEL,MLB/LIO,MBA

CRITICAL

1

[EEEE:F0JC]

EEEE:F0JC

825-7563

LABEL,MLB/LIO,MBA

639-2818

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600

PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0

639-2820

PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600

639-2823

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600

PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT

639-2819

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600

PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ

639-3633

PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3

639-3632

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600

PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600

PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600

PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC

639-3630

639-3631

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600

051-9589

4.18.0

6 OF 132

6 OF 99

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEABLE BEAD-PROBES FOR TBT

2X GND

J5050 - hall effect

J4410 - rio flex

10X GND

J3502 - ALS camera

3X P3V3_S3

4X GND

FUNC_TEST

NC NO_TESTs

NO_TEST

CPU NO_TESTs

NO_TEST

ICT Test Points

GPU NO_TESTs

NO_TEST

Thunderbolt NO_TESTs

NO_TEST

NC NO_TESTs

NO_TEST=TRUE

FUNC_TEST

19X GND

5X P5V_S4

5X GND

3X P5V_S0

2X

FUNC_TEST

2X GND

4X GND

4X

FUNC_TEST

4X

3X

16X GND

2X GND

8X

2X GND

2X

POWER RAILS

8X GND

FUNC_TEST

J9000 - eDP

J6701 - audio flex

J6802 - L speaker

J6803 - R speaker

J6900 - DC PWR

J3501 - airport

J5100 - lpc + spi

J4400 - rio coax

J5713 - keyboard

J5650 - left fan

Functional Test Points

J5700 - ipd flex

2X GND

J6801 - 3-mic

PCH ALIASES

J6950 - battery

J5660 - right fan

5X GND

J5815 - kbd backlight

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

I1596

I1597

I1599

I1600

I1601

I1602

I1603

I1604

I1605

I1606

I1607

I1608

I1609

I1610

I1611

I1612

I1613

I1614

I1615

I1616

I1617

I1618

I1619

I1620

I1621

I1622

I1623

I1624

I1625

I1626

I1627

I1628

I1629

I1630

I1631

I1632

I1633

I1634

I1635

I1636

I1637

I1638

I1639

I1640

I1641

I1642

I1643

I1644

I1645

I1646

I1647

I1648

I1649

I1650

I1651

I1652

I1653

I1654

I1655

I1656

I1657

I1658

I1659

I1660

I1661

I1662

I1663

I1664

I1665

I1666

I1667

I1668

I1669

I1670

I1671

I1672

I1673

I1674

I1675

I1676

I1677

I1678

I1679

I1680

I1681

I1682

I1683

I1684

I1685

I1686

I1687

I1688

I1689

I1690

I1691

I1692

I1693

I1694

I1695

I1696

I1697

I1698

I1699

I1700

I1701

I1702

I1703

I1704

I1705

I1706

I1707

I1708

I1709

I1710

I1711

I1712

I1713

I1714

I1715

I1716

I1717

I1718

I1719

I1720

I1721

I1722

I1723

I1728

I1729

I1730

I1731

I1733

I1734

I1735

I1736

I1737

I1738

I1739

I1740

I1741

I1742

I1743

I1744

I1745

I1746

I1747

I1748

I1749

I1750

I1751

I1752

I1753

I1754

I1755

I1756

I1757

I1758

I1759

I1760

I1761

I1762

I1763

I1764

I1765

I1766

I1767

I1768

I1769

I1770

I1771

I1772

I1773

I1774

I1775

I1776

I1777

I1778

I1779

I1780

I1781

I1782

I1785

I1793

I1795

I1797

I1798

I1799

I1800

I1802

I1803

I1817

I1818

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

SYNC_DATE=01/13/2012

Functional / ICT Test

SYNC_MASTER=D2_KEPLER

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TP_LVDS_EG_BKL_PWM

LVDS_IG_B_CLK_N

TP_GPU_MIOA_DE

TP_GPU_MIOA_D<9..0>

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE

USB_EXTB_P

TRUE

SD_PWR_EN

TRUE

USB_EXTB_OC_L

TRUE

WS_KBD21

TRUE

I2C_DPMUX_A_SCL

PM_SLP_S3_L

TRUE

WS_KBD4

TRUE

WS_KBD_ONOFF_L

TRUE

PP5V_S4

DP_TBTSNK0_ML_C_N<3..0>

TRUE

WS_KBD12

TRUE

WS_KBD11

TRUE

ENET_RESET_L

TRUE

USB3_EXTB_TX_C_P

TRUE

USB3_EXTB_RX_N

TRUE

WS_KBD1

TRUE

SMC_LID_R

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

USB_BT_CONN_N

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

WIFI_EVENT_L

TRUE

USB_BT_CONN_P

TRUE

WS_KBD14

TRUE

WS_KBD13

TRUE

HDMI_EG_DATA_C_N<0>

HDMI_EG_DATA_C_P<2>

TRUE

PCIE_CLK100M_ENET_N

TRUE

PCIE_ENET_R2D_C_P

TRUE

PM_SLP_S4_L

USB_CAMERA_CONN_P

TRUE

USB_CAMERA_CONN_N

TRUE

SPI_ALT_MISO

SMC_KBDLED_PRESENT_L

TRUE

PP1V05_S0

TRUE

PP1V8_S0

TRUE

PP3V3_S0

TRUE

PP3V3_S0GPU

PP3V3_S5_AVREF_SMC

TRUE

PP5V_S3

TRUE

CH_HS_GND

MAKE_BASE=TRUE

TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3

LED_RETURN_1

TRUE

CON_DMIC_SDA2

TRUE

CON_DMIC_SDA1

TRUE

PP3V3_S3RS4_BT_F

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_5_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_5_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_5_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_8_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_5_D2RN

NC_LVDS_IG_CTRL_CLK

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_DDC_DATA

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<43..32>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27..26>

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<24..15>

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<2..1>

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD_NCTF<8..5>

TRUE

NC_PCIE_PE8_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE8_D2RN

TRUE

NC_PCIE_PE8_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE7_R2D_CN

TRUE

NC_PCIE_PE7_R2D_CP

MAKE_BASE=TRUE

NC_PCIE_PE6_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE7_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE7_D2RN

TRUE

NC_PCIE_PE6_R2D_CN

MAKE_BASE=TRUE

NC_PCIE_PE6_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE5_D2RP

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE5_D2RN

TRUE

PCH_VSS_NCTF<29>

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<15>

TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<5>

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<7>

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<1>

TRUE

NC_HDA_SDIN1

MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

TRUE

NC_LVDS_IG_CTRL_DATA

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_LPC_DREQ0_L

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

MAKE_BASE=TRUE

TRUE

NC_PCI_AD<31..0>

TRUE

MAKE_BASE=TRUE

NC_PCI_GNT3_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT1_L

NC_PCI_CLK33M_OUT3

TRUE

MAKE_BASE=TRUE

NC_PCH_NV_RCOMP

MAKE_BASE=TRUE

TRUE

NC_NV_DQ<15..0>

MAKE_BASE=TRUE

TRUE

NC_NV_DQS<1..0>

TRUE

MAKE_BASE=TRUE

NC_NV_ALE

MAKE_BASE=TRUE

TRUE

NC_NV_CLE

MAKE_BASE=TRUE

TRUE

NC_NV_WR_RE_L<1..0>

MAKE_BASE=TRUE

TRUE

NC_NV_WE_CK_L<1..0>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7P

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

TRUE

MAKE_BASE=TRUE

NC_SATA_B_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_TBT_PCIE_RESET0_L

TRUE

MAKE_BASE=TRUE

NC_TBT_PCIE_RESET2_L

TRUE

MAKE_BASE=TRUE

NC_TBT_PCIE_RESET1_L

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET3_L

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

NC_SMC_P41

TRUE

MAKE_BASE=TRUE

TRUE

NC_DVPDATA<21..4>

MAKE_BASE=TRUE

TRUE

NC_DVPCNTL_M<1..0>

TRUE

MAKE_BASE=TRUE

NC_DVPDATA<2..0>

TRUE

NC_DVPDATA<2..0>

MAKE_BASE=TRUE

TRUE

PCH_VSS_NCTF<9>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<3..0>

TRUE

NC_CLINK_DATA

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_AUXCH_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_TBT_XTAL25OUT

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_R2D_CP

TRUE

NC_PCIE_6_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4N

TRUE

NC_HDA_SDIN2

MAKE_BASE=TRUE

NC_PCI_GNT2_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCI_PME_L

MAKE_BASE=TRUE

NC_PCI_RESET_L

TRUE

NC_PCI_PAR

MAKE_BASE=TRUE

TRUE

NC_NV_RB_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_L

TRUE

TBT_B_D2R_P<1..0>

TRUE

TBT_B_D2R_C_N<1..0>

TBT_B_D2R_C_P<1..0>

TRUE

TBT_A_R2D_N<1..0>

TRUE

TBT_A_R2D_C_N<1..0>

TRUE

TBT_A_D2R_N<1..0>

DP_TBTSNK1_ML_C_N<3..0>

TRUE

DP_TBTSNK1_ML_N<3..0>

TRUE

DP_TBTSNK1_ML_P<3..0>

TRUE

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK1_AUXCH_C_N

TRUE

DP_TBTSNK1_AUXCH_P

TRUE

DP_TBTSNK0_AUXCH_P

TRUE

DP_TBTSNK0_AUXCH_N

TRUE

DP_TBTSNK0_AUXCH_C_N

TRUE

DP_TBTSNK0_AUXCH_C_P

TRUE

DP_TBTSNK0_ML_P<3..0>

TRUE

DP_TBTSNK0_ML_N<3..0>

TRUE

DP_TBTSNK0_ML_C_P<3..0>

TRUE

TBT_B_R2D_P<1..0>

TRUE

TBT_B_R2D_N<1..0>

TBT_B_R2D_C_P<1..0>

TRUE

TBT_B_R2D_C_N<1..0>

DP_TBTSNK1_AUXCH_N

TRUE

TBT_B_D2R_N<1..0>

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

NC_CRT_IG_RED

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_HPD

NC_DP_IG_C_CTRL_DATA

TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

TRUE

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_MLN<3..0>

TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_HPD

TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_CLK

TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_DATA

TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3..0>

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_MLN<3..0>

TRUE

NC_DP_IG_D_AUXP

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXN

MAKE_BASE=TRUE

NC_SDVO_STALLN

TRUE

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

NC_SDVO_INTN

TRUE

NC_SDVO_STALLP

TRUE

MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE

MAKE_BASE=TRUE

NC_GPU_BUFRST_L

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_GPU_MIOA_D<9..0>

NC_GPU_MIOA_DE

TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWM

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TRUE

NC_SMC_BS_ALRT_L

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_R2D_CP

TRUE

NC_PCIE_PE5_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_D2RN

MAKE_BASE=TRUE

TRUE

TBT_A_D2R_C_N<1..0>

TRUE

MAKE_BASE=TRUE

NC_NV_CE_L<3..0>

TRUE

TBT_A_R2D_C_P<1..0>

DP_TBTSNK1_ML_C_P<3..0>

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_D2RP

TRUE

TBT_A_R2D_P<1..0>

TRUE

TBT_A_D2R_C_P<1..0>

TRUE

TBT_A_D2R_P<1..0>

TRUE

PCIE_AP_D2R_PI_P

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_WAKE_L

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PP3V3_WLAN

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

PCIE_CLK100M_ENET_P

TRUE

USB3_EXTB_TX_C_N

PP3V3_S4

TRUE

SDCONN_STATE_CHANGE_RIO

TRUE

FAN_LT_PWM

TRUE

PP5V_S0

TRUE

FAN_LT_TACH

TRUE

KBDLED_ANODE2

TRUE

KBDLED_ANODE1

LPC_AD<1>

TRUE

LPC_AD<0>

TRUE

LPC_AD<3>

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SMC_TDI

TRUE

SMC_TMS

TRUE

SMC_TDO

TRUE

SMC_TX_L

TRUE

SPI_ALT_CLK

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_MOSI

TRUE

PP3V3_S4

TRUE

WS_CONTROL_KBD

TRUE

PP3V42_G3H

TRUE

WS_KBD10

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD18

TRUE

WS_KBD17

TRUE

WS_KBD19

TRUE

WS_KBD2

TRUE

WS_KBD20

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD3

TRUE

WS_KBD5

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

AUD_HP_PORT_R

TRUE

AUD_HP_PORT_L

TRUE

AUD_SPDIF_OUT_JACK

TRUE

AUD_TYPEDET

AUD_TIPDET_INV

TRUE

CH_HS_MIC

TRUE

PP3V3_S0

TRUE

US_HS_GND

TRUE

CON_DMIC_PWR

TRUE

CON_DMIC_CLK

TRUE

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_SL_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_ID

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

SPKRCONN_SR_OUT_P

TRUE

DP_INT_AUX_P

TRUE

DP_INT_AUX_N

TRUE

DP_INT_ML_N<0>

TRUE

DP_INT_ML_N<2>

TRUE

DP_INT_ML_N<1>

LCD_HPD_CONN

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

LED_RETURN_6

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PP5VR3V3_SW_LCD

TRUE

SYS_DETECT_L

TRUE

SMC_TCK

TRUE

PCIE_AP_R2D_P

TRUE

SMC_RX_L

TRUE

SMC_ROMBOOT

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

AP_CLKREQ_Q_L

TRUE

LPC_AD<2>

TRUE

LPCPLUS_RESET_L

TRUE

LPCPLUS_GPIO

PP0V75_S0_DDRVTT

TRUE

PM_SLP_S3_L

TRUE

PP3V3_S5

TRUE

PP3V3_S3

PP5V_S0

TRUE

PP3V42_G3H

TRUE

PPBUS_G3H

TRUE

PP5V_S5

TRUE

PPVCORE_GPU

PPDCIN_G3H

TRUE

PPVCORE_S0_CPU

TRUE

PPVTTDDR_S3

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

PPVBAT_G3H_CONN

TRUE

LCD_FSS

TRUE

DP_INT_ML_P<2>

TRUE

DP_INT_ML_P<1>

TRUE

DP_INT_ML_P<0>

TRUE

DP_INT_ML_N<3>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<65..62>

TRUE

WS_KBD6

TRUE

TP_SMC_MD1

TP_SMC_TRST_L

TRUE

US_HS_MIC

TRUE

DP_INT_ML_P<3>

TRUE

LPC_FRAME_L

TRUE

PCIE_AP_D2R_PI_N

TRUE

AP_RESET_CONN_L

TRUE

PP1V5_S0_RIO

PP3V3_S3

TRUE

GND

PP3V42_G3H

TRUE

HDMI_HPD_L

TRUE

USB_EXTB_N

TRUE

ENET_CLKREQ_L

TRUE

HDMI_EG_DDC_CLK

TRUE

HDMI_EG_DDC_DATA

I2C_DPMUX_A_SDA

TRUE

PCIE_ENET_D2R_P

TRUE

PCIE_ENET_R2D_C_N

TRUE

USB3_EXTB_RX_P

TRUE

PCIE_ENET_D2R_N

HDMI_EG_DATA_C_N<2>

TRUE

HDMI_EG_DATA_C_N<1>

TRUE

HDMI_EG_CLK_C_N

HDMI_EG_CLK_C_P

TRUE

HDMI_EG_DATA_C_P<0>

TRUE

HDMI_EG_DATA_C_P<1>

TRUE

TDM_ONEWIRE_MPM

TRUE

PP18V5_DCIN_FUSE

TRUE

ADAPTER_SENSE

TRUE

SMC_RESET_L

TRUE

PP5V_S0

TRUE

PM_CLKRUN_L

TRUE

Z2_DEBUG3

Z2_CS_L

TRUE

Z2_MISO

TRUE

Z2_MOSI

TRUE

Z2_SCLK

TRUE

Z2_HOST_INTN

TRUE

Z2_CLKIN

TRUE

Z2_KEY_ACT_L

TRUE

PP3V3_S4

TRUE

PICKB_L

TRUE

Z2_RESET

TRUE

PSOC_F_CS_L

TRUE

PP5V_S5

TRUE

PSOC_MOSI

TRUE

PSOC_MISO

TRUE

PSOC_SCLK

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

WS_KBD9

TRUE

NC_CLINK_RESET_L

MAKE_BASE=TRUE

TRUE

NC_CLINK_CLK

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_AUXCH_CP

MAKE_BASE=TRUE

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

PP5V_S0

TBT_A_R2D_C_P<1>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TP_PCI_C_BE_L<3..0>

TP_NV_DQS<1..0>

TP_PCIE_CLK100M_PEBN

TP_CLINK_DATA

TP_CLINK_CLK

TP_LPC_DREQ0_L

TP_CRT_IG_DDC_CLK

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<2..1>

TP_CRT_IG_GREEN

TP_CRT_IG_RED

TP_PCIE_5_R2D_CP

TP_PCIE_5_D2RP

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_NV_DQ<15..0>

TP_PCH_NV_RCOMP

TP_PCI_PME_L

LVDS_IG_BKL_PWM

SMC_BS_ALRT_L

LVDS_IG_B_CLK_P

TP_GPU_GSTATE<0>

TP_GPU_GSTATE<1>

TP_GPU_BUFRST_L

TP_SDVO_INTP

TP_SDVO_STALLP

TP_SDVO_INTN

TP_SDVO_TVCLKINP

TP_SDVO_STALLN

TP_DP_IG_D_AUXN

TP_SDVO_TVCLKINN

TP_DP_IG_D_AUXP

TP_DP_IG_D_MLN<3..0>

TP_DP_IG_D_MLP<3..0>

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_HPD

TP_DP_IG_C_AUXN

TP_DP_IG_C_AUXP

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

TP_DP_IG_C_CTRL_CLK

TP_DP_IG_C_CTRL_DATA

TP_PCI_AD<31..0>

TP_PCIE_CLK100M_PE5P

TP_PSOC_P1_3

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE7P

TP_SATA_B_R2D_CN

TP_PCI_GNT2_L

TP_NV_CE_L<3..0>

TP_PCI_PAR

TP_PCI_RESET_L

TP_PCI_CLK33M_OUT3

TP_HDA_SDIN2

TP_SATA_B_D2RN

TP_PCIE_6_D2RN

TP_PCIE_6_D2RP

TP_TBT_XTAL25OUT

TP_TBT_PCIE_RESET0_L

TP_TBT_PCIE_RESET1_L

TP_TBT_PCIE_RESET3_L

TP_DP_TBTSRC_ML_CN<3..0>

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_ML_CP<3..0>

TP_SATA_E_D2RP

TP_TBT_PCIE_RESET2_L

TP_CLINK_RESET_L

TP_DVPCNTL_M<1..0>

TP_DVPCNTL<2..0>

TP_DVPDATA<21..4>

TP_SMC_P41

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RP

TP_SATA_F_D2RN

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_B_R2D_CP

TP_SATA_B_D2RP

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE4N

TP_NV_WE_CK_L<1..0>

TP_PCI_GNT3_L

TP_CRT_IG_BLUE

TP_CRT_IG_VSYNC

TP_LVDS_IG_CTRL_CLK

TP_CRT_IG_HSYNC

TP_LVDS_IG_CTRL_DATA

TP_HDA_SDIN1

TP_HDA_SDIN3

TP_PCIE_CLK100M_PEBP

TP_PCIE_PE5_D2RN

TP_PCIE_PE5_R2D_CP

TP_PCIE_PE6_D2RN

TP_PCIE_PE5_D2RP

TP_PCIE_PE5_R2D_CN

TP_PCIE_PE6_R2D_CP

TP_PCIE_PE6_R2D_CN

TP_PCIE_PE7_D2RN

TP_PCIE_PE7_D2RP

TP_PCIE_PE6_D2RP

TP_PCIE_PE7_R2D_CN

TP_PCIE_PE8_D2RP

TP_PCIE_PE8_D2RN

TP_PCIE_PE8_R2D_CN

TP_PCIE_PE8_R2D_CP

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<58..45>

TP_CPU_RSVD<65..62>

TP_CRT_IG_DDC_DATA

TP_PCIE_8_R2D_CP

TP_PCIE_8_R2D_CN

TP_PCIE_8_D2RP

TP_PCIE_8_D2RN

TP_PCIE_7_R2D_CP

TP_PCIE_7_R2D_CN

TP_PCIE_7_D2RN

TP_PCIE_7_D2RP

TP_PCIE_6_R2D_CP

TP_PCIE_6_R2D_CN

TP_PCIE_5_R2D_CN

TP_PCIE_5_D2RN

TP_PCH_LVDS_VBG

TP_CPU_RSVD_NCTF<8..5>

TP_NV_WR_RE_L<1..0>

TP_NV_CLE

TP_NV_ALE

TP_DP_TBTSRC_AUXCH_CP

TP_PCIE_PE7_R2D_CP

TP_DVPCNTL<2..0>

TP_NV_RB_L

TBT_A_D2R_P<1>

TBT_A_D2R_N<1>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>

TP_DP_IG_C_HPD

TP_HDMI_CEC

TRUE

MAKE_BASE=TRUE

NC_HDMI_CEC

TRUE

NC_ISNS_P1V5R1V35_CPUDDRN

TRUE

NC_ISNS_LCDBKLTP

TRUE

NC_ISNS_LCD_PANELP

TRUE

NC_ISNS_LCD_PANELN

TRUE

NC_ISNS_AIRPORTN

TRUE

NC_ISNS_AIRPORTP

TRUE

NC_ISNS_P1V5R1V35_CPUDDRP

TRUE

NC_ISNS_LCDBKLTN

TRUE

NC_USB_HUB_OCS3

TRUE

NC_SMC_XOSC1

TRUE

NC_SMC_ODD_DETECT

TRUE

NC_SMC_HIB_L

NC_SMBUS_SMC_4_ASF_SDA

TRUE

NC_SMC_T25_ISENSE

TRUE

NC_SMC_T25_EN_L

TRUE

NC_SMBUS_SMC_4_ASF_SCL

TRUE

NC_USB_HUB_OCS4

NC_SMC_FAN_2_CTL

TRUE

NC_SMC_FAN_2_TACH

TRUE

NC_USB_HUB_OCS2

TRUE

NC_USB_HUB_PRTPWR4

TRUE

NC_SMC_SYS_LED

TRUE

NC_USB_HUB_PRTPWR2

TRUE

NC_USB_HUB_PRTPWR3

TRUE

NC_FW2_TPAN

TRUE

NC_FW2_TPAP

TRUE

NC_FW0_TPBP

TRUE

NC_ESTARLDO_EN

TRUE

NC_FW0_TPAP

TRUE

NC_FW0_TPBN

TRUE

NC_SMC_FAN_3_CTL

TRUE

NC_SMC_FAN_3_TACH

TRUE

NC_FW2_TPBN

NC_FW2_TPBP

TRUE

NC_FW2_TPBIAS

TRUE

NC_ALS_GAIN

BP0732

1

BP0731

1

BP0735

1

BP0733

1

BP0734

1

051-9589

4.18.0

7 OF 132

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42

34

34 91

34 96

34 41 42

34 91

49

38 77 95

17 38 92

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34 91

43

50

8

7 8

96

8

41 42

8

58

81 86

59

34

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25 38

48

7

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48

50

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92

17 41 43 82

92

17 41 43 82

92

25 43 92

41 42 43

43

20 43 52

43

7 8

49

7 8

49

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53 58

58 59

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58

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96

58

59

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57 59 96

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81

81 86

81 86 99

81

60

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34 92

41 42 43

42 43

17 41 43

18 25 41 43

34

17 41 43 82

92

25 43

20 43

8

7

18 27 38 41 70

8

96

7 8

8

7 8

8

41 44

60 61

81 82

81 95

49

43

58

81 95

17 41 43 82

92

34 92

34

8

7

8

7 8

38 42 82

26 38 91

17 38

38 77

44

17 38 92

19 38 91

17 38 92

38 77 95

60

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7 8

18 41 43

49

7 8

49

7 8

49

7

41 44 94

7

41 44 94

49

48

7

35 84 93

7

35 85 93

7

35 85 93

17

18

17

19

18

49

19

17

35

17

35

17

7

17

18

17

18

17

18

35

7

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7

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26

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

5V Rails

For PCH RTC Power

3.3V Rails

G3H Rails

1.8V/1.5V/1.2V/1.05V Rails

Chipset "VCore" Rails

TBT RAILS

"GPU" Rails

4A max supply

Backlight Rails

Defined here since TBT page does not know PBUS voltage

I1679

Power Aliases

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

=PP3V42_G3H_TDM

=PP3V42_G3H_AUDIO

MIN_NECK_WIDTH=0.1 MM

PP5V_S5

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

=PP5V_S5_TPAD

=PP5V_S5_P5VSUSFET

=PP5V_S4_AUDIO

=PP5V_S4_TPAD

=PP5V_S4_ISNS

=PP5V_S4_RIO

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5V_S4

MIN_NECK_WIDTH=0.2 mm

=PP5V_SUS_PCH

=PPVRTC_G3_OUT

MIN_LINE_WIDTH=0.3 MM

PP3V42_G3H

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP5V_S3

VOLTAGE=5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H_ISOL

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=18.5V

PPDCIN_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 MM

VOLTAGE=12.8V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPVIN_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V0_S0GPU_ISNS

MAKE_BASE=TRUE

PP1V5R1V35_S0GPU

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_GPU

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.17 mm

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP15V_TBT

VOLTAGE=15V

MIN_LINE_WIDTH=0.4 MM

PPVCORE_S0_AXG

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPVRTC_G3H

VOLTAGE=3.42V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.17 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5R1V35_MEM

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V8_S0_CPU_VCCPLL_R

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.5 MM

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PPVCCSA_S0_REG

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0_CPUDDR

MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU

VOLTAGE=1.25V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.075 mm

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP1V05_S0_P1V05TBTFET

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

VOLTAGE=12.8V

PPVIN_SW_TBTBST

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_TBTLC

VOLTAGE=3.3V

PP3V3_TBTLC

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_TBTCIO

VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

MAKE_BASE=TRUE

PP3V3_S0GPU_MISC

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V05_PCHVCCIO_S0

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MAKE_BASE=TRUE

TP_GPU_PGOOD2

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=2 mm

PP0V75_S0_DDRVTT

MAKE_BASE=TRUE

VOLTAGE=0.75V

MAKE_BASE=TRUE

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0_RIO

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0

MAKE_BASE=TRUE

PP3V3_S3

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP5V_S0

MAKE_BASE=TRUE

VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_SUS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_SW_BKL

MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

VOLTAGE=12.6V

NC_SMC_T25_EN_L

MAKE_BASE=TRUE

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP3V3_SUS

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.10MM

PP3V3_S0GPU

=PP3V3_S0GPU_FET

=PP3V3_S0GPU_MISC_FET

=PP3V3_S3_DPMUX_UC

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_GPIO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_SMC

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_FET

=PP3V3_S4_RIO

=PP3V3_SUS_ROM

SMC_T25_EN_L

=PPBUS_SW_BKL

=PP5V_S4_REG

=PP5V_S4_P5VS3FET

=PP5V_S0_LCD

=PP5V_S3_LTUSB

=PP5V_S3_FET

=PP5V_S3_ISNS

=PP5V_S3_ALSCAMERA

=PP5V_S3_DEBUG_ADC_AVDD

=PP5V_S3_DDRREG

=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_MEMRESET

=PP5V_S0_AUDIO_XW

=PP5V_S0_CPUIMVP

=PP5V_S0_CPUVCCIOS0

=PP5V_S0_FAN_LT

=PP5V_S0GPU_P1V0P1V35_GPU

=PP5V_S0_P1V5_LDO

=PPVIN_S0_CPUAXG

=PP3V3_S3_SMBUS_SMC_2_S3

=PP3V3_S5_XDP

=PP3V3_S5_PCH_GPIO

=PP1V8_S0_P1V5_LDO

=PPVDDIO_S0_SBCLK

=PP5V_S0_FAN_RT

=PP5V_S0_BKL

=PP5V_S0_VCCSAS0

=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

=PP1V5_S0_RIO

=PPVTT_S0_DDR_LDO

=PP0V75_S0_MEM_VTT_A

=PP1V5_S3RS0_VMON

=PPVIN_S3_MEM_ISNS_R

=PPVIN_S0_DDRREG_LDO

=PP1V8_S0_GPUFET

=PP1V8_S0_PCH_VCCTX_LVDS

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S4_DPBPWRSW

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_AUDIO

=PP3V3_SUS_P1V05SUSLDO

=PPDCIN_S5_VSENSE

=PP18V5_DCIN_ISOL

=P1V8GPU_EN

TP_P1V8GPU_EN

=PPDDR_S3_MEMVREF

=PP1V5_S0_AUDIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V8_GPU_FET

=PP1V05_S0_RMC

=PP1V05_S0_VMON

=PPVCCIO_S0_SMC

=PPVCCIO_S0_CPUIMVP

=PP1V05_S0_CPU_VCCIO

=PP3V3_GPU_MISC_P3V3GPUMISCFET

=PP3V3_GPU_MISC

=PP3V3_S0_GFX3V3BIAS

=PP3V3_GPU_VDD33

=PP3V3_GPU_IFPX_PLLVDD

=PP1V8_S0_CPU_VCCPLL

=PP3V3_GPU_P3V3GPUFET

=PP3V3_S4_TBTBPWRSW

=PP3V3_S4_TBTAPWRSW

=PP3V3_S5_VMON

=PP3V3_S5_SYSCLK

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PWRCTL

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH

=PP3V3_S5_P3V3SUSFET

=PP3V3_S5_P1V2P1V8

=PP3V3_S5_P1V5S0

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S4_P3V3S4FET

=PP3V3_S3_P3V3S3FET

=PP3V3_S4_DPAPWRSW

=PP3V3_S0_P3V3S0FET

=PP3V3_S3_SDBUF

=PP3V3_S3_SMS

=PP3V3_S3_GYRO

=PP3V3_S3_WLAN

=PP3V3_S3_VREFMRGN

=PP3V3_S3_USB_RESET

=PP3V3_S3_USB_HUB

=PP3V3_S3_TPAD

=PP3V3_S3_USBMUX

=PP3V3_S3_SMBUS_SMC_3

=PP3V3_S3_RIO

=PP3V3_S3_PCH_GPIO

=PP3V3_S3_MEMRESET

=PP3V3_S3_ISNS

=PP3V3_S3_BT

=PP3V3_S3_FET

=PP3V3_S5_REG

=PPHV_SW_TBTBPWRSW

=PP1V05_TBTLC_FET

=PP3V3_TBTLC_RTR

=PP3V3_TBT_PCH_GPIO

=PP1V05_TBTLC_RTR

=PP3V3_S0_TBTPWRCTL

=PP3V3_S0_TPAD

=PP3V3_S0_VMON

=PP3V3_S0_XDP

=PP3V3_S0_SPKRTHMSNS

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP1V05_S0_P1V05TBTFET

=PP1V05_TBTCIO_RTR

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S4_TPAD

=PP3V3_S0_X29THMSNS

=PP3V3_TBTLC_FET

=PP3V3_S0_TBTI2C

=PP3V3_S0_SYSCLK

=PP3V3_S0_SSD

=PP3V3_S0_SMBUS_SMC_1_S0

=PP3V3_S0_SATAMUX

=PP3V3_S0_RSTBUF

=PP3V3_S0_PWRCTL

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH

=PP3V3_S0_P3V3TBTFET

=PP3V3_S0_P1V8GPUFET

=PP3V3_S0_ISNS

=PP3V3_S0_LCD

=PP3V3_S0_IMVPISNS

=PP3V3_S0_HS_ISNS

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_FAN_LT

=PP3V3_S0_FAN_RT

=PP3V3_S0_DPMUX_UC

=PP3V3_S0_DPMUXI2C

=PP3V3_S0_CPU_VCCIO_SEL

=PP3V3_S0_DPMUX

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_AUDIO_DIG

=PP3V3_S0_AUDIO

=LVDS_VCCA

=PPVCORE_S0_CPU_REG

=PPVCORE_GPU_REG

=PP1V05_S0_CPU_VCCPQE

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PPVCCIO_S0_XDP

=PPVCCSA_S0_REG

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V5_S3_CPU_VCCDDR

=PP1V5R1V35_S3_MEM_B

=PP1V5R1V35_S3_MEM_A

=PPVRTC_G3_PCH

=PPVIN_S5_SMCVREF

=PP3V42_G3H_TPAD

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCCIO_PCIE

=PP3V3_S5_SMC

=PPVBAT_G3_SYSCLK

=PP3V3_S4_TBT_R

=PP3V3_S4_FET

=PP5V_S0_FET

=PP5V_S0_PCHVCCIOS0

=PP5V_S0_PCH

=PP3V42_G3H_PWRCTL

=PP3V3_SUS_CNTRL

=PP3V3_SUS_PCH_VCC_SPI

=PP5V_S0_RMC

=PP5V_S0_VMON

=PPVIN_S3_P1V5S3RS0_FET

=PP1V05_SUS_LDO

=PP1V8_S0_REG

=PP1V05_GPU_IFPCD_IOVDD

=PP1V05_SUS_PCH_JTAG

=PPVCCSA_S0_CPU

=PPBUS_G3H

=PP5V_S5_LDO

=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_P1V05TBTFET_R

=PP1V05_GPU_PEX_IOVDD

=PP1V5_S3_CPU_VCCDQ

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU

=PP1V05_TBTCIO_FET

=PP3V3_S0_DDR3THMSNS

=PPHV_SW_TBTAPWRSW

=PP15V_TBT_REG

=PP1V5_S3_MEMRESET

=PP1V35_GPU_S0_FB

=PP1V0_GPU_DPLL

=PP1V0_GPU_DP_AB

=PPVCORE_S0_GFX_REG

=PPVCORE_GPU

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_IFPEF_IOVDD

=PP1V0_GPU_DP_CD

=PP1V5R1V35_GPU_REG

=PP1V05_S0GPU_REG

=PP1V35_GPU_FBVDDQ

=PP3V42_G3H_SMBUS_SMC_5

=PP3V42_G3H_SMCUSBMUX

=PP3V42_S3_HALL

=PP3V42_G3H_REG

=PPBUS_S0_LCDBKLT

=PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_GPU_ISNS_R

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPBUS_S0_VSENSE

=PPVIN_SW_TBTBST

=PPBUS_G3H_T25_R

=PPVIN_S0_CPUIMVP

=PPVIN_S3_DDRREG

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S0_CPUVCCIOS0

=PPVIN_S0_VCCSAS0

=PPVIN_S0_PCHVCCIOS0

=PPVIN_S0_GFXIMVP

=PPVIN_S0GPU_P1V5P1V0

=PPVIN_S5_P5VP3V3

=PPVIN_S5_HS_OTHER_ISNS

=PPDCIN_S5_CHGR

=PP18V5_DCIN_CONN

=PP3V3_S5_LPCPLUS

=PP5V_S0_LPCPLUS

=PP5V_S0_KBDLED

=PP5V_S0_GFXIMVP

=PP3V3_S4_SMC

=PP3V3_S4_BT

=PPVIN_S5_HS_GPU_ISNS

=PP3V42_G3H_CHGR

=PPVDDIO_TBT_CLK

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_SB_PM

=PP3V3_S0_SMBUS_SMC_0_S0

=PPPCHVCCIO_S0_REG

=PPCPUVCCIO_S0_REG

=PPVTT_S3_DDR_BUF

=PP1V5_S0_RIO_LDO

=PP1V5_S0_REG

=PP1V5_S3RS0_FET_ISNS

=PPVIN_S3_MEM_ISNS

=PP1V8_S0_CPU_VCCPLL_R

=PPDDR_S3_REG

PPBUS_S0_LCDBKLT_PWR

=PP5V_SUS_FET

=PPDCIN_S5_CHGR_ISOL

=PP5V_S5_P1V5S3RS0FET

=PP5V_S4_P5VS0FET

=PP5V_S3_DEBUG_ISNS

=PP3V3_S0_FET

=PP3V42_G3H_ONEWIREPROT

GND

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.085MM

VOLTAGE=0V

MAKE_BASE=TRUE

051-9589

4.18.0

8 OF 132

8 OF 99

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69

82

21 23

17 18 19 20

21 23

42

21 23

69

38

52

41

99

63

69

81

40

69

99

34

98

64

98

27

9

65 66

67

48

74

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27

38

64

32

70

45

64

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20 21 23

21

68

45

60

88

33

53

21 23 25

88

98

70

42

65

10 11 13 14 15

69

77

80

71 77 78 79

77

15

69

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84

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42

70

21 23

70

18

69

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27

69

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51

34

33

26

44

38

19 25

27

99

34

69

63

85

37

35 36 37

20

36

37

50

70

24

21 23

21

37 99

36

21

21 23

49

47

37

25

39

44

39

25

70 88

23

21 23

23

17 18 19 20 25 37

17 23

37

45 98 99

81

46

47

48

35 78 82

44

13

82 83

47

86

53 58

59

21

66

45

13 15

21 23

17 23

21

24

62 99

21

11 14 16 27

30 31

28 29

17 18 21

42

49

21 23

8

21 23

23

18

41 42 78

25

36

69

87

23 25

70

21 23

98

70

69

68

77

24

13 16

60 61

63

13 14 16

17 21 23

21 23

8

21 23

17 21 23

99

73 79

13 16

45 66

13 15 45 98

37

84

9

37

27

73

80

72 79

77 79

77

74

72 75 76

44

40

42

60

86

46

45

9

37

65 66

64

46

67

62

87

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63

46

61

60

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50

80

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60

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

T29 / GMUX JTAG Signals

Frame Holes

Digital Ground

SMT GND TEST PONTS

USB SIGNALS

UNUSED USB SIGNALS

UNUSED FDI SIGNALS

SSD PCIE SIGNALS

DPMUX TX & RX

UNUSED TBT PORTS

GPU signals

GMUX ALIASES

Unused PEG signals

T29 Signals Through PEG

CPU signals

APN 806-2247

THERMAL MODULE STANDOFFS

POGO PINS

SM

STDOFF-4.5OD2.15H-SM

805

5%

1/8W

MF-LF

0

TBTBST:N

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD2.15H-SMSTDOFF-4.5OD2.15H-SM

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.9H-SM

2.8R2.3

1K

5%

201

MF

1/20W

RAMCFG0:L

1/20W

RAMCFG1:L

201

1K

MF

5%

RAMCFG3:L

1/20W

MF

5%

201

1K

201

MF

1/20W

RAMCFG2:L

1K

5%

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.8H-SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

I1187

I1188

I1189

I1190

I1191

I1192

SL-1.1X0.45-1.4x0.75

TH-NSP

SM

SHLD-J5-USB

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-2.3X3.9-2.9X4.5

TH-NSP

2.8OD1.2ID-1.35H-SM

SMT-PAD-NSP

2.1SM2.0MM-CIR 2.1SM2.0MM-CIR

SMT-PAD-NSP SMT-PAD-NSP

2.1SM2.0MM-CIR

SMT-PAD-NSP

2.1SM2.0MM-CIR

MLB-MTG-BRKT-J5

TH

SM

SHLD-J5-CAN-FENCE-MDP-1

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

STDOFF-4.5OD2.15H-SM-1

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

2.8OD1.2ID-1.35H-SM

Signal Aliases

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

MAKE_BASE=TRUE

GND

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCH_GPIO65_CLKOUTFLEX1

GND_CHASSIS_MLBCAN6

GND_CHASSIS_MLBCAN5

GND_CHASSIS_MLBCAN4

GND_CHASSIS_FAN

GND_CHASSIS_MLBCAN3

GND_CHASSIS_MLBCAN2

GND_CHASSIS_MLBCAN1

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

TP_FW_PWR_EN

MAKE_BASE=TRUE

SD_PWR_EN

MAKE_BASE=TRUE

SD_PWR_EN_PCH

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_IG

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_IG

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_N

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_P

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_N

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE

MAKE_BASE=TRUE

DPLL_REF_CLKP

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE

MAKE_BASE=TRUE

DPLL_REF_CLKN

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_N

MAKE_BASE=TRUE

USB_TPAD_N

MAKE_BASE=TRUE

USB_TPAD_P

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

USB_BT_P

MAKE_BASE=TRUE

NC_CPU_FDI_DATA_P<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

PU_USBHUB_DN4N

MAKE_BASE=TRUE

PU_USBHUB_DN4P

MAKE_BASE=TRUE

NC_PCH_FDI_DATA_P<7..0>

NO_TEST=TRUE

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S0_AUDIO_AMP_L

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

MAKE_BASE=TRUE

NC_PCH_FDI_DATA_N<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_DATA_N<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<1..0>

MAKE_BASE=TRUE

USB_SMC_N

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S0_AUDIO_AMP_R

MAKE_BASE=TRUE

NC_CPU_FDI_LSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_LSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_SMC_P

MAKE_BASE=TRUE

NC_PCH_FDI_FSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<1..0>

MAKE_BASE=TRUE

PEG_D2R_P<7..0>

MAKE_BASE=TRUE

PEG_D2R_N<7..0>

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<1..0>

MAKE_BASE=TRUE

NC_USB_EXTC_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXTC_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTD_RX_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTD_RX_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCI_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCI_N

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_P

NO_TEST=TRUE

NC_USB3_EXTD_TX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_TX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_TX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_RX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_RX_N

DPMUX_UC_RX

MAKE_BASE=TRUE

NC_TBT_D2RN<3..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_D2RP<3..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

DPMUX_UC_TX

MAKE_BASE=TRUE

NC_TBT_R2D_CN<3..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_TBT_R2D_CP<3..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2R_P

MAKE_BASE=TRUE

NC_SATA_ODD_D2R_N

MAKE_BASE=TRUE

NC_DP_IG_MLP<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_MLN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_C_P

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_C_N

NC_LVDS_IG_B_DATA_N<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_N<2..0>

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_DDC_DATA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_DDC_CLK

NO_TEST=TRUE

PEX_CLKREQ_L

MAKE_BASE=TRUE

PEG_CLKREQ_L

MAKE_BASE=TRUE

EG_RESET_L

MAKE_BASE=TRUE

NO_TEST=TRUE

TBT_LSEO_LSOE2

NO_TEST=TRUE

MAKE_BASE=TRUE

TBT_LSEO_LSOE3

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

MAKE_BASE=TRUE

NC_PEG_D2R_P<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

CPU_VID<0..6>

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

NC_PEG_D2R_N<15..14>

NO_TEST=TRUE

NC_LVDS_IG_A_CLK_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

=PP15V_TBT_REG

PCIE_FW_D2R_P

USB3_EXTC_RX_P

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_B_DATA_N<2..0>

PCIE_FW_D2R_N

PCIE_FW_R2D_C_P

USB3_EXTC_TX_N

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

LVDS_IG_DDC_DATA

USB3_EXTD_TX_N

USB_EXTC_P

USB_EXTC_N

USB_EXTD_EHCI_P

USB_EXTD_EHCI_N

USB3_EXTC_RX_N

PCIE_FW_R2D_C_N

SATA_ODD_D2R_N

TP_DP_IG_B_MLN<3..0>

LVDS_IG_DDC_CLK

TP_DP_IG_B_MLP<3..0>

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

LVDS_IG_A_DATA_P<3>

CPU_VTTSELECT

USB3_EXTC_TX_P

USB3_EXTD_RX_N

USB3_EXTD_RX_P

USB3_EXTD_TX_P

=PEG_R2D_C_N<15..14>

=PEG_R2D_C_P<15..14>

=PEG_R2D_C_P<11..8>

=PEG_R2D_C_N<11..8>

=PEG_D2R_P<15..14>

=PEG_D2R_P<11..8>

=PEG_D2R_N<15..14>

=PEG_D2R_N<11..8>

=DDRVTT_EN

CPUIMVP_VID<0..6>

TBT_LSEO<3>

TBT_LSEO<2>

GPU_RESET_L

IG_LCD_PWR_EN

IG_BKLT_EN

EG_CLKREQ_OUT_L

EG_CLKREQ_IN_L

=PPVIN_SW_TBTBST

=PEG_R2D_C_P<13..12>

=PEG_R2D_C_N<13..12>

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P

=PEG_D2R_N<7..0>

=PEG_R2D_C_P<7..0>

=PEG_D2R_P<7..0>

=PEG_R2D_C_N<7..0>

=FDI_DATA_N<7..0>

=FDI_DATA_P<7..0>

=PEG_D2R_P<13..12>

=PEG_D2R_N<13..12>

FDI_LSYNC<1..0>

USBHUB_DN3_P

FDI_DATA_P<7..0>

FDI_FSYNC<1..0>

=FDI_FSYNC<1..0>

=FDI_LSYNC<1..0>

USBHUB_DN1_P

USBHUB_DN2_N

USBHUB_DN1_N

USBHUB_DN2_P

FDI_DATA_N<7..0>

USBHUB_DN4_N

USBHUB_DN4_P

USBHUB_DN3_N

DPMUX_UC_BOOT_RX

TBT_D2R_N<3..2>

TBT_R2D_C_P<3..2>

TBT_D2R_P<3..2>

DPMUX_UC_BOOT_TX

TBT_R2D_C_N<3..2>

ENET_LOW_PWR

ENET_LOW_PWR_PCH

FW_PWR_EN

DPA_IG_HPD

DPB_IG_HPD

=PP5V_S0_AUDIO_XW

MLB_RAMCFG3

MLB_RAMCFG2

MLB_RAMCFG1

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

PCIE_EXCARD_R2D_C_P

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TBT_LSOE<3>

PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_P

PCIE_EXCARD_R2D_C_N

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_CLKOUT_DPP

TBT_LSOE<2>

MLB_RAMCFG0

GND_BATT_CHGND

TP_PCH_CLKOUT_DPN

STDOFF-4.9OD2.38H-SM-2

SHLD-J5-CAN-FENCE-MDP-2

XW0902

1 2

XW0903

1 2

SH0922

1

R0950

1 2

SH0925

1

SH0926

1

SH0927

1

SH0928

1

SH0929

1

SH0930

1

SH0924

1

ZT0915

1

R0910

1

2

R0911

1

2

R0913

1

2

R0912

1

2

SH0920

1

SH0923

1

SH0931

1

ZT0970

1

SH0950

1

SH0932

1

SH0933

1

SH0935

1

SH0936

1

SH0934

1

ZT0971

1

ZT0972

1

ZT0974

1

ZT0975

1

ZT0973

1

ZT0950

1

SH0940

1

SH0942

1

SH0941

1

SH0943

1

SH0944

1

ZT0990

1

ZT0991

1

ZT0992

1

ZT0993

1

BR0901

1

SH0952

1

SH0951

1

SH0937

1

SH0921

1

SH0946

1

SH0945

1

SH0960

1

SH0961

1

051-9589

4.18.0

9 OF 132

9 OF 99

17

18

7

38

82

11 89

49 91

34 91

57

71 89

39 92

41 91

57

41 91

71 89

39 92

71 88 89

39 92

82

17

82

35 92

27

8

37

17

19 91

18 91

17

19 91

17 91

18

19

19 91

19

19 91

17

17 91

18

18 91

18

18 91

19 91

19

10

27 64

71 78

82

78 82

8

37

10

17 92

10

18

10

10 89

26

10 89

18

26

10 89

26

82

25

20 24 25

25

18 82

8

20

17 92

17

20

17

IN

OUT

IN

OUT

IN

NC

OUT

BI

IN

DMI

(1 OF 11)

PCI EXPRESS BASED INTERFACE SIGNALS

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

FDI0_FSYNC

FDI1_FSYNC

FDI0_LSYNC

EDP_TX0*

EDP_TX2*

PEG_TX8

EDP_TX3*

FDI1_TX3

FDI_INT

FDI1_LSYNC

EDP_TX1*

EDP_TX0

EDP_TX1

EDP_TX2

EDP_TX3

FDI1_TX3*

FDI1_TX2*

PEG_RX7*

PEG_RX6*

PEG_RX8*

PEG_RX10*

DMI_TX1*

DMI_TX0*

DMI_RX3

DMI_TX3*

PEG_RX0

DMI_TX2

DMI_TX1

DMI_TX0

FDI0_TX2

FDI1_TX0

FDI1_TX2

PEG_TX10

PEG_TX9

PEG_TX7

PEG_TX6

PEG_TX14*

PEG_TX15*

PEG_TX13

PEG_TX12

EDP_AUX*

DMI_RX1

DMI_RX2

DMI_TX3

FDI0_TX0*

FDI0_TX1*

FDI1_TX1*

FDI0_TX0

FDI0_TX1

FDI0_TX3

FDI1_TX1

EDP_AUX

EDP_ICOMPO

EDP_COMPIO

EDP_HPD*

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX0*

PEG_RX1*

PEG_RX2*

PEG_RX5*

PEG_RX9*

PEG_RX15*

PEG_RX1

PEG_RX2

PEG_RX3

PEG_RX4

PEG_RX5

PEG_RX6

PEG_RX7

PEG_RX8

PEG_RX9

PEG_RX10

PEG_RX11

PEG_RX12

PEG_RX13

PEG_RX14

PEG_RX15

PEG_TX0*

PEG_TX1*

PEG_TX2*

PEG_TX3*

PEG_TX4*

PEG_TX5*

PEG_TX6*

PEG_TX7*

PEG_TX8*

PEG_TX9*

PEG_TX10*

PEG_TX11*

PEG_TX12*

PEG_TX13*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX11

PEG_TX14

PEG_TX15

DMI_RX0

DMI_RX3*

DMI_RX1*

DMI_RX0*

DMI_RX2*

DMI_TX2*

FDI0_TX2*

FDI0_TX3*

FDI1_TX0*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX3*

PEG_RX4*

RSVD

CFG

(5 OF 11)

RESERVED

NC

S

D

G

NC

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Intel is investigating processor driven VREF_DQ generation.

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(THERMDC)

(THERMDA)

These can be Placed close to J2500 and Only for debug access

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(DDR_VREF1)

(DDR_VREF0)

NOTE:

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

CPU_CFG<4> should be pulled down to enable EDP

This connection is to support the same.

18 89

9

24.9

1/16W

402

MF-LF

1%

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

18 89

9

89

9

89

1%

1/16W

MF-LF

PLACE_NEAR=U1000.AB1:12.7mm

402

24.9

1/16W

MF-LF

5%

402

1K

NOSTUFF

1/16W

5%

402

MF-LF

1K

402

1K

MF-LF

5%

1/16W

EDP:YES

MF-LF

1K

5%

1/16W

402

NOSTUFF

402

5%

MF-LF

1/16W

1K

1/16W

MF-LF

5%

402

NOSTUFF

1K

1/16W

MF-LF

5%

402

1K

NOSTUFF

1/16W

MF-LF

5%

402

1K

NOSTUFF

1/16W

402

1K

NOSTUFF

MF-LF

5%

82 89

402

MF-LF

1K

5%

1/16W

OMIT_TABLE

82

OMIT_TABLE

IVY-BRIDGE

BGA

OMIT_TABLE

IVY-BRIDGE

BGA

2N7002TXG

EDP:YES

SOT-523-3

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

116S0090

1

R1031

EDP:NO

RES,MTL FILM,1/16W,10K,0402,SMD,LF

R1031

EDP:YES

1

RES,MTL FILM,1/16W,1K,0402,SMD,LF

116S0066

CPU DMI/PEG/FDI/RSVD

=PEG_R2D_C_P<14>

=PEG_D2R_N<0>

=PEG_D2R_N<2>

=PEG_D2R_N<3>

=PEG_D2R_N<6>

=PEG_D2R_P<5>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<1>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<4>

=PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<7>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

=PEG_D2R_P<7>

=PEG_D2R_P<0>

=PEG_D2R_P<1>

=PEG_D2R_N<4>

=PEG_D2R_N<7>

=PEG_R2D_C_N<8>

DMI_N2S_N<3>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<15>

DMI_N2S_P<2>

=PEG_D2R_P<3>

=PEG_D2R_P<2>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

DMI_N2S_N<2>

=PEG_R2D_C_N<9>

DMI_S2N_N<1>

=PEG_R2D_C_N<14>

CPU_CFG<7>

CPU_CFG<4>

CPU_CFG<6>

DP_INT_IG_HPD_L

CPU_EDP_COMP

DP_INT_IG_ML_N<0>

FDI_INT

CPU_CFG<3>

CPU_CFG<16>

CPU_CFG<0>

CPU_CFG<5>

FDI_DATA_P<1>

FDI_DATA_P<2>

FDI_DATA_P<3>

FDI_DATA_P<4>

FDI_DATA_P<7>

FDI_LSYNC<0>

FDI_DATA_P<6>

FDI_DATA_N<6>

FDI_DATA_N<5>

DP_INT_IG_HPD

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<12>

=PP1V05_S0_CPU_VCCIO

=PEG_R2D_C_P<9>

DP_INT_IG_AUX_P

DP_INT_IG_ML_P<2>

DP_INT_IG_ML_N<3>

=PP1V05_S0_CPU_VCCIO

FDI_FSYNC<0>

FDI_FSYNC<1>

FDI_DATA_N<7>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_N2S_P<1>

FDI_DATA_N<0>

FDI_DATA_N<1>

FDI_DATA_P<0>

FDI_DATA_P<5>

DMI_S2N_P<0>

DMI_S2N_N<0>

FDI_DATA_N<2>

FDI_DATA_N<3>

DMI_S2N_N<3>

DMI_S2N_P<2>

=PEG_D2R_N<11>

=PEG_D2R_N<13>

=PEG_D2R_N<14>

=PEG_D2R_P<8>

=PEG_D2R_P<10>

=PEG_R2D_C_N<11>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<13>

DP_INT_IG_ML_P<1>

DP_INT_IG_ML_P<0>

DP_INT_IG_ML_P<3>

DP_INT_IG_AUX_N

CPU_CFG<2>

CPU_CFG<5>

CPU_CFG<7>

CPU_CFG<1>

CPU_CFG<10>

CPU_CFG<4>

CPU_CFG<0>

CPU_CFG<11>

CPU_CFG<3>

CPU_CFG<13>

CPU_CFG<9>

CPU_CFG<12>

CPU_CFG<8>

CPU_CFG<6>

CPU_CFG<2>

DMI_N2S_P<3>

FDI_DATA_N<4>

=PEG_R2D_C_P<11>

CPU_CFG<1>

DMI_S2N_P<1>

=PEG_R2D_C_N<10>

DP_INT_IG_ML_N<2>

DP_INT_IG_ML_N<1>

FDI_LSYNC<1>

CPU_CFG<15>

CPU_CFG<14>

DMI_S2N_N<2>

=PEG_D2R_N<15>

CPU_CFG<17>

CPU_CFG<16>

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

PPCPU_MEM_VREFDQ_A

MIN_NECK_WIDTH=0.2 mm

PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=0.75V

=PEG_D2R_N<5>

=PEG_D2R_N<1>

=PEG_D2R_N<12>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<6>

=PEG_D2R_P<13>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<9>

DMI_N2S_P<0>

=PEG_D2R_N<10>

CPU_PEG_COMP

R1010

1

2

R1030

1

2

R1047

1

2

R1046

1

2

R1045

1

2

R1044

1

2

R1042

1

2

R1040

1

2

R1041

1

2

R1043

1

2

R1049

1

2

R1031

1

2

U1000

N8

N10

T9

R10

R6

R8

U8

U10

N2

N4

R2

R4

P3

P1

T5

U6

AE4

AE2

AC2

AE8

AB1

AG4

AG2

AF3

AF1

AF7

AE6

AG8

AG6

AC8

AB7

W6

V7

W10

W8

Y9

AA8

AA10

AC10

AA2

AB3

U2

U4

W4

W2

V3

V1

AA6

Y5

AD9

G2

H1

F3

G22

F23

K23

H23

F11

H11

K11

J12

F9

E8

H9

G10

H7

J8

G6

F7

K21

H21

F19

H19

K19

J20

H17

G18

K15

K17

G14

F15

J16

H15

K13

H13

C22

A22

D23

B23

B13

D13

C10

A10

D11

B11

B9

D9

D7

B7

F13

E12

A18

C18

B21

D21

D19

B19

F21

E20

C14

A14

B17

D17

D15

B15

F17

E16

U1000

B57

D57

F55

K55

F57

E58

H57

H55

D53

K57

B55

A54

A58

D55

C56

E54

J54

G56

G64

BJ42

BG62

BG34

BG26

BG22

BG4

BF63

BF43

BF41

BF35

BF25

BJ34

BF23

BF21

BF19

BF3

BE32

BE16

BE6

BD33

BD29

BD19

BJ22

BD15

BD13

BC42

BC30

BC14

BB57

BB43

BB25

BB17

BB15

BH43

BB13

BA48

BA16

AY45

AY41

AY17

AY15

AY13

AW50

AW46

BH35

AW42

AW14

AJ10

AJ6

AH5

AD5

AC6

AC4

AA4

P7

BH25

N6

M9

M5

L10

L6

L4

L2

K49

K47

K9

BH23

K7

K5

J50

J4

J2

H49

H47

H5

G52

G48

BH21

G4

F5

D49

D25

D3

C52

C24

C4

B53

B25

BH19

Q1031

3

1

2

BP1004

1

BP1011

1

BP1012

1

051-9589

4.18.0

10 OF 132

10 OF 99

10 24 89

89

10 24 89

8

10 11 13 14 15

8

10 11 13 14 15

10 24 89

24 89

10 24 89

24 89

10 24 89

24 89

10 24 89

24 89

10 24 89

33 89

89

BI

IN

OUT

IN

OUT

BI

NC

OUT

BI

(2 OF 11)

CLOCKS

PWR MGMT

JTAG & BPM

DDR3 MISC

THERMAL

PECI

PROCHOT*

THERMTRIP*

RESET*

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

SM_DRAMRST*

SM_VREF

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

BCLK_ITP*

BCLK

BCLK*

PRDY*

PREQ*

TCK

TMS

TRST*

TDI

TDO

DBR*

BPM0*

BPM1*

BPM2*

BPM3*

BPM4*

BPM5*

BPM6*

BPM7*

CATERR*

PROC_SELECT*

PROC_DETECT*

IN

OUT

IN

OUT

IN

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R1120 and R1121 are Intel recommended values

(IPU)

(IPD)

(IPU)

24 89

PLACE_NEAR=U1800.AY11:157mm

MF-LF

1/16W

5%

10K

402

18 27 89

20 24 89

27

17 89

20 89

20 42 89

1/16W

MF-LF

1%

75

402

MF-LF

PLACE_NEAR=U1000.BF45:12.7mm

1%

200

1/16W

402

PLACE_NEAR=U1000.BG46:12.7mm

25.5

1%

1/16W

MF-LF

402

PLACE_NEAR=U1000.BJ46:12.7mm

1%

140

MF-LF

1/16W

402

41 89

68

MF-LF

5%

1/16W

402

PLACE_NEAR=U1000.BJ44:2.54mm

X7R-CERM

0402

16V

0.1UF

10%

MF-LF

1/16W

5%

56

402

41 42 65 89

OMIT_TABLE

BGA

IVY-BRIDGE

9

89

9

89

MF-LF

1/16W

1%

1K

402

PLACE_NEAR=U1000.BJ44:2.54mm

MF-LF

1/16W

1%

1K

402

NOSTUFF

1K

5%

1/20W

MF

201

24 89

200

1%

MF-LF

1/16W

PLACE_NEAR=R1121.2:1mm

402

130

1%

MF-LF

1/16W

PLACE_NEAR=U1000.AY25:51.562mm

402

17 89

18 89

51

MF-LF

NOSTUFF

1/16W

5%

402

43.2

1/16W

1%

MF-LF

402

24 25

NOSTUFF

5%

1K

MF

201

1/20W

24 25 89

24 89

CPU CLOCK/MISC/JTAG

DMI_CLK100M_CPU_P

XDP_CPU_TMS

XDP_CPU_TRST_L

XDP_CPU_TCK

XDP_CPU_PREQ_L

DPLL_REF_CLKP

=PP1V05_S0_CPU_VCCIO

DPLL_REF_CLKN

ITPCPU_CLK100M_P

ITPCPU_CLK100M_N

XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<6>

XDP_CPU_TDI

XDP_BPM_L<0>

XDP_BPM_L<3>

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<2>

XDP_BPM_L<1>

=PP1V05_S0_CPU_VCCIO

CPU_PROCHOT_L

=PP1V5_S3_CPU_VCCDDR

CPU_SM_RCOMP<2>

PM_SYNC

CPU_PWRGD

=MEM_RESET_L

CPU_SM_RCOMP<1>

PM_MEM_PWRGD_R

CPU_RESET_L

PLT_RESET_LS1V1_L

XDP_CPU_PRDY_L

DMI_CLK100M_CPU_N

CPU_SM_RCOMP<0>

PM_THRMTRIP_L

CPU_PROCHOT_R_L

CPU_PECI

CPU_PROC_SEL_L

PM_MEM_PWRGD

=PP1V05_S0_CPU_VCCIO

CPU_CATERR_L

=PP1V5_S3_CPU_VCCDDR

CPU_DDR_VREF

R1100

1

2

R1120

1

2

R1121

12

R1104

1

2

R1125

12

R1102

1

2

R1111

1

2

R1126

1

2

R1114

1

2

R1113

1

2

R1112

1

2

R1101

1

2

C1130

1

2

R1103

12

U1000

D5

C6

K63

K65

C62

D61

E62

F63

D59

F61

F59

G60

H53

H61

AJ4

AJ2

F53

K53

J62

H65

B59

AH9

H51

K51

AY25

BE24

BJ46

BG46

BF45

BJ44

J58

K61

K59

F51

H59

H63

C60

R1131

1

2

R1130

1

2

051-9589

4.18.0

11 OF 132

11 OF 99

8

10 11 13 14 15

8

10 11 13 14 15

8

11 14 16 27

89

8

10 11 13 14 15

8

11 14 16 27

BI

OUT

BI

OUT

BI

OUT

BI

OUT

SA_CLK0

SA_CLK1*

SA_DQ30

SA_DQ0

SA_DQ1

SA_DQ2

SA_DQ9

SA_DQ11

SA_DQ12

SA_DQ13

SA_DQ14

SA_DQ15

SA_DQ16

SA_DQ17

SA_DQ18

SA_DQ19

SA_DQ20

SA_DQ21

SA_DQ22

SA_DQ23

SA_DQ24

SA_DQ25

SA_DQ26

SA_DQ27

SA_DQ28

SA_DQ29

SA_DQ31

SA_DQ32

SA_DQ33

SA_DQ34

SA_DQ35

SA_DQ36

SA_DQ37

SA_DQ38

SA_DQ39

SA_DQ40

SA_DQ41

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ48

SA_DQ49

SA_DQ50

SA_DQ51

SA_DQ52

SA_DQ53

SA_DQ54

SA_DQ55

SA_DQ56

SA_DQ57

SA_DQ58

SA_DQ59

SA_DQ60

SA_DQ61

SA_DQ62

SA_DQ63

SA_BS0

SA_BS1

SA_BS2

SA_RAS*

SA_WE*

SA_CS0*

SA_CS1*

SA_ODT0

SA_ODT1

SA_DQS0*

SA_DQS1*

SA_DQS2*

SA_DQS3*

SA_DQS4*

SA_DQS5*

SA_DQS6*

SA_DQS7*

SA_DQS0

SA_DQS1

SA_DQS2

SA_DQS3

SA_DQS4

SA_DQS5

SA_DQS6

SA_DQS7

SA_MA0

SA_MA1

SA_MA2

SA_MA3

SA_MA4

SA_MA5

SA_MA6

SA_MA7

SA_MA8

SA_MA9

SA_MA10

SA_MA11

SA_MA12

SA_MA13

SA_MA14

SA_MA15

SA_DQ4

SA_DQ3

SA_DQ10

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ6

SA_CAS*

SA_DQ47

SA_DQ46

SA_DQ45

SA_CKE1

SA_CLK0*

SA_CKE0

SA_CLK1

(3 OF 11)

MEMORY CHANNEL A

SB_MA15

SB_MA14

SB_BS0

SB_DQ51

SB_DQ52

SB_DQ53

SB_DQ54

SB_DQ55

SB_DQ56

SB_DQ57

SB_DQ18

SB_DQ19

SB_DQ20

SB_DQ21

SB_DQ22

SB_DQ23

SB_DQ24

SB_DQ14

SB_DQ2

SB_DQ5

SB_DQ7

SB_DQ8

SB_DQ6

SB_DQ10

SB_DQ9

SB_DQS0

SB_DQS4

SB_DQS5

SB_DQS6

SB_DQS7

SB_MA1

SB_MA2

SB_DQ0

SB_DQ12

SB_DQ11

SB_DQ13

SB_DQ15

SB_DQ16

SB_DQ17

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA9

SB_MA8

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA0

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS4*

SB_DQS2*

SB_DQS1*

SB_DQS0*

SB_ODT1

SB_ODT0

SB_CS1*

SB_CS0*

SB_WE*

SB_RAS*

SB_CAS*

SB_BS2

SB_BS1

SB_DQ63

SB_DQ62

SB_DQ61

SB_DQ60

SB_DQ59

SB_DQ58

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ46

SB_DQ45

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ35

SB_DQ34

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ29

SB_DQ28

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQS3*

SB_CLK1*

SB_DQ3

SB_CKE1

SB_CKE0

SB_CLK0

SB_CLK0*

SB_DQ1

SB_DQ4

SB_CLK1

(4 OF 11)

MEMORY CHANNEL B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

28 29 90

28 29 32 90

30 31 90

30 31 32 90

28 32 90

29 32 90

28 32 90

29 32 90

28 32 90

29 32 90

28 29 90

28 29 32 90

30 32 90

31 32 90

30 32 90

31 32 90

30 32 90

31 32 90

30 31 90

30 31 32 90

BGA

IVY-BRIDGE

OMIT_TABLE

BGA

IVY-BRIDGE

OMIT_TABLE

CPU DDR3 INTERFACES

SYNC_DATE=01/13/2012

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<3>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CLK_N<0>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_N<0>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<4>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_DQ<34>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_ODT<1>

MEM_A_DQ<10>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_A<2>

MEM_A_DQ<35>

MEM_A_DQ<27>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<14>

MEM_B_DQ<2>

MEM_B_DQ<5>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<6>

MEM_B_DQ<10>

MEM_B_DQ<0>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_A_DQ<31>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_DQ<11>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<1>

MEM_B_DQ<9>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQS_P<0>

MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_P<3>

MEM_B_DQS_P<4>

MEM_B_DQS_P<5>

MEM_B_DQS_P<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>

MEM_B_DQS_N<2>

MEM_B_DQS_N<3>

MEM_B_DQS_N<4>

MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_A_BA<2>

MEM_A_DQ<20>

MEM_A_DQS_N<5>

MEM_A_CLK_P<1>

U1000

BA36

BC38

BB19

BE44

BC18

BD17

BB31

BA32

AW34

AY33

BD41

BD45

AL6

AL8

AV7

AY5

AT5

AR6

AW6

AT9

BA6

BA8

BG6

AY9

AP7

AW8

BB7

BC8

BE4

AW12

AV11

BB11

BA12

BE8

BA10

AM5

BD11

BE12

BB49

AY49

BE52

BD51

BD49

BE48

BA52

AY51

AK7

BC54

AY53

AW54

AY55

BD53

BB53

BE56

BA56

BD57

BF61

AL10

BA60

BB61

BE60

BD63

BB59

BC58

AW58

AY59

AL60

AP61

AN10

AW60

AY57

AN60

AR60

AM9

AR10

AR8

AN6

AN8

AU8

AU6

BD5

BC6

BC10

BD9

BB51

BC50

BD55

BB55

BD61

BD59

AV61

AU60

BD27

BA28

AW38

AW22

BA20

BB45

BE20

AW18

BB27

AW26

BB23

BA24

AY21

BD21

BC22

BB21

BB41

BC46

BE36

BA44

U1000

BJ38

BD37

AY29

BH39

BD25

BJ26

BF33

BH33

BF37

BH37

BE40

BH41

AL4

AK3

BA4

BB1

AV1

AU2

BA2

BB3

BC2

BF7

BF11

BJ10

AP3

BC4

BH7

BH11

BG10

BJ14

BG14

BF17

BJ18

BF13

BH13

AR2

BH17

BG18

BH49

BF47

BH53

BG50

BF49

BH47

BF53

BJ50

AL2

BF55

BH55

BJ58

BH59

BJ54

BG54

BG58

BF59

BA64

BC62

AK1

AU62

AW64

BA62

BC64

AU64

AW62

AR64

AT65

AL64

AM65

AP1

AR62

AT63

AL62

AM63

AR4

AV3

AU4

AN2

AN4

AW4

AW2

BF9

BH9

BH15

BF15

BH51

BF51

BF57

BH57

AY65

AY63

AN64

AN62

BF31

BH31

AY37

BJ30

AW30

BA40

BB29

BE28

BB37

BC34

BF27

BB33

BH27

BG30

BH29

BF29

BG42

BH45

BG38

BF39

051-9589

4.18.0

12 OF 132

12 OF 99

OUT

BI

OUT

IN

OUT

VCC VCC

(6 OF 11)

CORE POWER

VIDALERT*

VIDSCLK

VCCSA

VIDSOUT

VCCSA_VID0

VCCSA_VID1

VCC_SENSE

VSS_SENSE

VAXG_SENSE

VSSAXG_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCC_DIE_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

VAXG_VAL_SENSE

VSSAXG_VAL_SENSE

VCCIO_SEL

VCCDQ

VCCPLL

VCCPQE

VSS_NCTF

DC_TEST_A4

DC_TEST_A62

DC_TEST_A64

DC_TEST_B3

DC_TEST_B63

DC_TEST_B65

DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1

DC_TEST_BH3

DC_TEST_BH63

DC_TEST_BH65

DC_TEST_BJ2

DC_TEST_BJ4

DC_TEST_BJ62

DC_TEST_BJ64

DC_TEST_C2

DC_TEST_C64

DC_TEST_D1

DC_TEST_D65

(9 OF 11)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

HR_PPDG sections 6.2.1 and 6.3.1.

For Future Compatibility

NOTE: Intel validation sense lines per doc 439028 rev1.0

65 89

67 89

62 89

5%

1/16W

10K

402

MF-LF

MF-LF5%

0

1/16W402

65 89

1%

402

1/16W

PLACE_NEAR=U1000.A50:2.54mm

MF-LF

130

5%402 1/16W MF-LF

0

65 89

PLACE_NEAR=U1000.B51:38mm

5% MF-LF

43

402 1/16W

65 89

402

1%

MF-LF

1/16W

75

PLACE_NEAR=R1310.1:2.54mm

1/16W

MF-LF

10K

402

5%

MF-LF

PLACE_SIDE=BOTTOM

NOSTUFF

1/16W

402

PLACE_NEAR=U1000.AU10:50.8mm

100

1%

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AW10:50.8mm

402

NOSTUFF

MF-LF

1/16W

1%

100

49.9

1/20W

PLACE_SIDE=BOTTOM

MF

1%

201

NOSTUFF

201

1/20W

MF

1%

NOSTUFF

49.9

PLACE_SIDE=BOTTOM

NOSTUFF

MF

1%

49.9

201

1/20W

MF

201

1/20W

1%

49.9

NOSTUFF

PLACE_SIDE=BOTTOM

100

MF-LF

402

5%

PLACE_SIDE=BOTTOM

1/16W

PLACE_NEAR=U1000.B47:50.8mm

1/16W

100

MF-LF

PLACE_SIDE=BOTTOM

402

PLACE_NEAR=U1000.A46:50.8mm

5%

MF-LF

1/16W

10K

402

5%

PLACE_SIDE=BOTTOM

402

100

1%

1/16W

NOSTUFF

MF-LF

PLACE_NEAR=U1000.F49:50.8mm

PLACE_NEAR=U1000.E50:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

100

402

MF-LF

1%

1/16W

100

1/16W

1%

MF-LF

402

62 89

BGA

IVY-BRIDGE

OMIT_TABLE

BGA

OMIT_TABLE

IVY-BRIDGE

SYNC_DATE=01/13/2012

CPU POWER

SYNC_MASTER=D2_KEPLER

=PPVCCSA_S0_CPU

CPU_VCC_VALSENSE_P

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

TP_CPU_VDDQSENSEN

TP_CPU_VDDQSENSEP

CPU_VCCSASENSE

=PP1V05_S0_CPU_VCCPQE

TP_CPU_DIE_SENSE

CPU_VCC_VALSENSE_N

DC_TEST_B65_C64

DC_TEST_BJ64_BH63

CPU_AXG_SENSE_P

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

CPU_VIDALERT_L

CPU_VIDSOUT

=PP3V3_S0_CPU_VCCIO_SEL

=PPVCCSA_S0_CPU

=PPVCORE_S0_CPU_VCCAXG=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

CPU_VIDSCLK

=PPVCORE_S0_CPU

TP_DC_TEST_D65

TP_DC_TEST_D1

TP_DC_TEST_BJ62

TP_DC_TEST_BJ4

DC_TEST_BH3_BJ2

DC_TEST_BG64_BH65

DC_TEST_BH1_BG2

TP_DC_TEST_BF65

TP_DC_TEST_BF1

DC_TEST_B3_C2

DC_TEST_B63_A64

TP_DC_TEST_A62

TP_DC_TEST_A4

=PP1V8_S0_CPU_VCCPLL_R

=PP1V5_S3_CPU_VCCDQ

CPU_VCCIO_SEL

CPU_AXG_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_SENSE_N

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VCCSA_VID<1>

CPU_VCCSA_VID<0>

CPU_VIDALERT_L_R

CPU_VIDSCLK_R

CPU_VIDSOUT_R

R1320

1

2

R1312

1 2

R1302

1

2

R1311

1 2

R1310

1 2

R1300

1

2

R1313

1

2

R1363

1

2

R1362

1

2

R1370

1

2

R1371

1

2

R1364

1

2

R1365

1

2

R1360

1

2

R1361

1

2

R1314

1

2

R1366

1

2

R1367

1

2

R1368

1

2

U1000

R46

R42

N43

B29

A44

A40

A38

A34

A32

A28

A26

N39

N37

N33

N30

N26

N24

N20

M46

M42

R40

M40

M36

M34

M29

M27

M23

M21

L44

L40

L38

R36

L34

L32

L28

L26

L22

K45

K43

K41

K37

K35

R34

K31

K29

K25

J44

J40

J38

J34

J32

J28

J26

R29

H45

H43

H41

H37

H35

H31

H29

H25

G44

G40

R27 G38

G34

G32

G28

G26

F45

F43

F41

F37

F35

R23

F31

F29

F25

E44

E40

E38

E34

E32

E28

E26

R21

D45

D43

D41

D37

D35

D31

D29

C44

C40

C38

N45

C34

C32

C28

C26

B45

B43

B41

B37

B35

B31

U1000

A4

A62

A64

B3

B63

B65

BF1

BF65

BG2

BG64

BH1

BH3

BH63

BH65

BJ2

BJ4

BJ62

BJ64

C2

C64

D1

D65

F49

B49

F47

B47

D47

AV23

AT23

AP23

AL23

AJ8

AW10

AK65

AK63

AK61

AV21

AT21

AP21

AL21

W17

W15

N16

N14

M17

M15

M12

M11

L18

L14

W12

U17

U15

U12

T16

T14

T11

N18

K3

AE10

AG10

AY19

B51

D51

A50

BJ60

BJ6

E64

E2

B61

B5

A60

A6

BH61

BH5

BE64

BE2

BD65

BD1

F65

F1

A46

AU10

AW20

C48

E50

A48

051-9589

4.18.0

13 OF 132

13 OF 99

8

13 16

8

15

8

13 15 45 98

8

13 15 45 98

8

10 11 13 14 15

8

10 11 13 14 15

8

13

16

8

13 14 16

8

13 14

16

8

10 11 13 14 15

8

13 15 45 98

8

13 15 45 98

8

15

8

16

VCCIOVCCIO

(7 OF11)

IO POWER

VDDQ

VAXG

(8 OF 11)

IO POWER DDR3

GRAPHIC CORE POWER

VSSVSS

(11 OF 11)

VSSVSS

(10 OF 11)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OMIT_TABLE

IVY-BRIDGE

BGA

OMIT_TABLE

BGA

IVY-BRIDGE

OMIT_TABLE

IVY-BRIDGE

BGA

OMIT_TABLE

BGA

IVY-BRIDGE

CPU POWER AND GND

=PPVCORE_S0_CPU_VCCAXG

=PP1V5_S3_CPU_VCCDDR

=PP1V05_S0_CPU_VCCIO =PP1V05_S0_CPU_VCCIO

U1000

AV55

AV53

AU20

AU18

AT55

AT53

AT48

AT17

AT15

AT12

AR58

AR56

AV48

AR52

AR49

AR20

AR18

AR16

AR14

AP55

AP53

AP48

AN58

AV17

AN56

AN52

AN49

AN20

AN18

AN16

AN14

AM11

AL55

AL53

AV15

AL48

AL17

AL15

AL12

AK58

AK56

AJ17

AJ15

AJ12

AH16

AV12

AH14

AH11

AF16

AF14

AE17

AE15

AE12

AD11

AC17

AC15

AU58

AC12

AB16

AB14

Y16

Y14

Y11

AU56

AU52

AU49

U1000

AH65

AH63

AE64

AE62

AE60

AD65

AD63

AD61

AD58

AD56

AB65

AB63

AH61

AB61

AB58

AB56

AA64

AA62

AA60

Y58

Y56

W64

W62

AH58

W60

V65

V63

V61

V58

V56

T65

T63

T61

T58

AH56

T56

R64

R62

R60

R55

R53

R48

N64

N62

N60

AG64

N58

N56

N52

N49

M65

M63

M61

M59

M55

M53

AG62

M48

L56

L52

L48

AG60

AF58

AF56

BJ36

BJ28

AY47

AY43

AY39

AY35

AY31

AY27

AY23

AV46

AV42

AV40

BG40

AV36

AV34

AV29

AV27

AU45

AU43

AU39

AU37

AU33

AU30

BG32

AU26

AU24

AT46

AT42

AT40

AT36

AT34

AT29

AT27

AR45

BD47

AR43

AR39

AR37

AR33

AR30

AR26

AR24

AP46

AP42

AP40

BD43

AP36

AP34

AP29

AP27

AN45

AN43

AN39

AN37

AN33

AN30

BD39

AN26

AN24

AL46

AL42

AL40

AL36

AL34

AL29

AL27

BD31

BD23

BB35

U1000

AG12

AF65

AF63

AF61

AF11

AF9

AF5

AE57

AD16

AD14

AD7

AD3

AD1

AC64

AC62

AC60

AC57

AB11

AB9

AB5

AA57

AA17

AA15

AA12

Y65

Y63

Y61

Y7

Y3

Y1

W57

V16

V14

V11

V9

V5

U64

U62

U60

U57

T7

T3

T1

R57

R50

R44

R38

R31

R25

R19

R17

R15

R12

P65

P63

P61

P11

P9

P5

N54

N47

N41

N35

N28

N22

M57

M50

M44

M38

M31

M25

M19

M7

M3

M1

L64

L62

L60

L58

L54

L50

L46

L42

L36

L30

L24

L20

L16

L12

L8

K39

K33

K27

K1

J64

J60

J56

J52

J48

J46

J42

J36

J30

J24

J22

J18

J14

J10

J6

H39

H33

H27

H3

G62

G58

G54

G50

G46

G42

G36

G30

G24

G20

G16

G12

G8

F39

F33

F27

E60

E56

E52

E48

E46

E42

E36

E30

E24

E22

E18

E14

E10

E6

E4

D63

D39

D33

D27

C58

C54

C50

C46

C42

C36

C30

C20

C16

C12

C8

B39

B33

B27

A56

A52

A42

A36

A30

A24

A20

A16

A12

A8

U1000

BJ56

BJ52

BG60

AU47

AU41

AU35

AU28

AU22

AU16

AU14

AT61

AT57

AT50

BG56

AT44

AT38

AT31

AT25

AT19

AT11

AT7

AT3

AT1

AR54

BG52

AR47

AR41

AR35

AR28

AR22

AP65

AP63

AP57

AP50

AP44

BG48

AP38

AP31

AP25

AP19

AP17

AP15

AP12

AP11

AP9

AP5

BG44

AN54

AN47

AN41

AN35

AN28

AN22

AM61

AM7

AM3

AM1

BG36

AL57

AL50

AL44

AL38

AL31

AL25

AL19

AK16

AK14

AK11

BG28

AK9

AK5

AJ64

AJ62

AJ60

AJ57

AH7

AH3

AH1

AG57

BG24

AG17

AG15

BG20

BG16

BJ48

BG12

BG8

BF5

BE62

BE58

BE54

BE50

BE46

BE42

BE38

BJ40

BE34

BE30

BE26

BE22

BE18

BE14

BE10

BD35

BD7

BD3

BJ32

BC60

BC56

BC52

BC48

BC44

BC40

BC36

BC32

BC28

BC26

BJ24

BC24

BC20

BC16

BC12

BB65

BB63

BB47

BB39

BB9

BB5

BJ20

BA58

BA54

BA50

BA46

BA42

BA38

BA34

BA30

BA26

BA22

BJ16

BA18

BA14

AY61

AY11

AY7

AY3

AY1

AW56

AW52

AW48

BJ12

AW44

AW40

AW36

AW32

AW28

AW24

AW16

AV65

AV63

AV59

BJ8

AV57

AV50

AV44

AV38

AV31

AV25

AV19

AV9

AV5

AU54

051-9589

4.18.0

14 OF 132

14 OF 99

8

13 16

8

11 16 27

8

10 11 13 14 15

8

10 11 13 14 15

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU VCCPLL DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1600-C16C7):

PLACEMENT_NOTE (C1620-C1623):

CPU VCCIO/VCCPQ DECOUPLING

Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

PLACEMENT_NOTE (C1646-C1671):

CPU VCORE DECOUPLING

(Z = 1.2mm, place on short side behind CPU)

PLACEMENT_NOTE (C1672-C1681):

PLACEMENT_NOTE (C1624-C16D5):

PLACEMENT_NOTE (C1640-C1645):

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

Apple Implementation: 8x 270uF 6mOhm, 0x 470uF 4mOhm , 16x 22uF 0402, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0402 (NOSTUFF)

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

10V

X6S-CERM

0402

1UF

10%

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U100.

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

X6S

Place near U1000 on bottom side

10UF

4V

0402

20%

X6S

Place near U1000 on bottom side

10UF

4V

0402

20%

X6S

Place near U1000 on bottom side

10UF

4V

0402

20%

X6S

Place near U1000 on bottom side

10UF

4V

0402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

10V

X6S-CERM

0402

1UF

10%

MF-LF

1/16W

5%

0

402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U100.

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10% 10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

0603

20%

Place near U1000 on bottom side

X6S-CERM

10UF

4V

0603

20%

X6S-CERM

10UF

Place near U1000 on bottom side

4V

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

0603

20%

Place near U1000 on bottom side

X6S-CERM

10UF

4V

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

20%

Place near U1000 on bottom side

X6S-CERM

0603

10UF

4V

0603

0.010

1%

1/4W

MF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

0201

CERM-X6S

4V

NOSTUFF

1UF

20%

CRITICAL

B16

220UF

2.5V

TANT

PLACE_NEAR=U1000.AK61:5MM

20%

270UF

TANT

2V

CRITICAL

CASE-B2-SM

20%

CRITICAL

270UF

2V

TANT

CASE-B2-SM

20%

270UF

CASE-B2-SM

TANT

2V

CRITICAL

20%

270UF

CASE-B2-SM

TANT

2V

CRITICAL

20%

270UF

CASE-B2-SM

TANT

2V

CRITICAL

20%

270UF

CASE-B2-SM

TANT

2V

CRITICAL

20%

270UF

CASE-B2-SM

TANT

2V

CRITICAL

20%

270UF

CASE-B2-SM

TANT

2V

CRITICAL

POLY-TANT

2.0V

20%

330UF-6MOHM

CRITICAL

D15T-ECGLT-COMBO D15T-ECGLT-COMBO

CRITICAL

330UF-6MOHM

20%

2.0V

POLY-TANT

CPU DECOUPLING-I

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

=PP1V8_S0_CPU_VCCPLL_R

=PP1V8_S0_CPU_VCCPLL

=PP1V05_S0_CPU_VCCPQE

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

X6T-CERM

CRITICAL

Place near inductors on bottom side.

2V

0402

20UF

20%

NOSTUFF

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

CRITICAL

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

CRITICAL

2V

X6T-CERM

0402

20UF

20%

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

20%

Place near inductors on bottom side.

2V

X6T-CERM

CRITICAL

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

CRITICAL

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

CRITICAL

NOSTUFF

Place near inductors on bottom side.

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

20%

Place near inductors on bottom side.

CRITICAL

2V

X6T-CERM

0402

20UF

C1612

1

2

C1611

1

2

C1610

1

2

C16A4

1

2

C16A3

1

2

C1609

1

2

C16A2

1

2

C1608

1

2

C1607

1

2

C16A1

1

2

C16A0

1

2

C1631

1

2

C1606

1

2

C1619

1

2

C1605

1

2

C1618

1

2

C1604

1

2

C1617

1

2

C1603

1

2

C1602

1

2

C1616

1

2

C1615

1

2

C1601

1

2

C1614

1

2

C1600

1

2

C1613

1

2

C1630

1

2

C1629

1

2

C1627

1

2

C1626

1

2

C16A6

1

2

C16A5

1

2

C1620

1

2

C1621

1

2

C1622

1

2

C1623

1

2

C1625

1

2

C1624

1

2

C1628

1

2

C1632

1

2

C1633

1

2

C1639

1

2

C1638

1

2

C1637

1

2

C1636

1

2

C1635

1

2

C1634

1

2

C1686

1

2

R1600

1 2

C1685

1

2

C1684

1

2

C1658

1

2

C1657

1

2

C1656

1

2

C1655

1

2

C1654

1

2

C1653

1

2

C1652

1

2

C1651

1

2

C1650

1

2

C1649

1

2

C1648

1

2

C1647

1

2

C1646

1

2

C1664

1

2

C1663

1

2

C1662

1

2

C1661

1

2

C1660

1

2

C1659

1

2

C1671

1

2

C1670

1

2

C1669

1

2

C1668

1

2

C1667

1

2

C1666

1

2

C1665

1

2

C1675

1

2

C1674

1

2

C1673

1

2

C1672

1

2

C1679

1

2

C1678

1

2

C1677

1

2

C1676

1

2

C1681

1

2

C1680

1

2

R1601

1 2

C16A7

1

2

C16A8

1

2

C16A9

1

2

C16B0

1

2

C16B1

1

2

C16B2

1

2

C16B3

1

2

C16B4

1

2

C16B5

1

2

C16B6

1

2

C16B7

1

2

C16B8

1

2

C16B9

1

2

C16C0

1

2

C16C7

1

2

C16C6

1

2

C16C5

1

2

C16C4

1

2

C16C3

1

2

C16C1

1

2

C16C2

1

2

C16D3

1

2

C16D2

1

2

C16D1

1

2

C16D0

1

2

C16D4

1

2

C16D5

1

2

C1687

1

2

C1640

1

2

C1641

1

2

C1642

1

2

C1643

1

2

C1689

1

2

C1644

1

2

C1645

1

2

C1688

1

2

C1699

1

2

C1698

1

2

C1696

1

2

C1695

1

2

C1694

1

2

C1693

1

2

C1691

1

2

C1690

1

2

C1682

1

23

C1683

1

23

051-9589

4.18.0

16 OF 132

15 OF 99

8

10 11 13 14

8

13 45 98

8

13

8

13

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE (C1726-C1731):

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

PLACEMENT_NOTE (C1734-C1735):

INTEL RECOMMENDATION: 2X 470UF 4MOHM, 2X 470UF 4MOHM (NOSTUFF), 6X 22UF 0805, 2X 22UF 0805 (NOSTUFF), 6X 10UF 0603, 2X 10UF 0603 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)

APPLE IMPLEMENTATION: 0X 470UF 4MOHM, 3X 330UF 9MOHM , 6X 22UF 0603, 2X 22UF 0603 (NOSTUFF), 6X 10UF 0402, 2X 10UF 0402 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)

Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

CPU VCCSA DECOUPLING

VAXG DECOUPLING

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1718-C1723):

PLACEMENT_NOTE (C1700-C1708):

PLACEMENT_NOTE (C1758-C1762):

Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

CPU VDDQ/VCCDQ DECOUPLING

Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1738-C1747):

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

NOSTUFF

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

Place close to U1000 on bottom side

NOSTUFF

4V

X6S

10UF

20%

0402

Place close to U1000 on bottom side

NOSTUFF

4V

X6S

10UF

20%

0402

NOSTUFF

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

Place near inductors on bottom side.

NOSTUFF

4V

X6S

0603

22UF

20%

10V

X6S-CERM

0402

1UF

10%

Place close to U1000 on bottom side

4V

X6S

10UF

20%

0402

10V

X6S-CERM

0402

1UF

10%

Place close to U1000 on bottom side

4V

X6S

10UF

20%

0402

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place close to U1000 on bottom side

4V

X6S

10UF

20%

0402

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U100.

10V

X6S-CERM

0402

1UF

10%

Place close to U1000 on bottom side

4V

X6S

10UF

20%

0402

Place close to U1000 on bottom side

4V

X6S

10UF

20%

0402

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place close to U1000 on bottom side

4V

X6S

10UF

20%

0402

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

Place near inductors on bottom side.

4V

X6S

0603

22UF

20%

10V

X6S-CERM

0402

1UF

10%

X6S-CERM

0402

10V

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

0402

1UF

10%

X6S-CERM

10V

Place on bottom side of U100.

X6S-CERM

0402

1UF

10%

0402

Place on bottom side of U1000

10V

X6S-CERM

1UF

10%

Place close to U1000 on bottom side

4V

X6S-CERM

10UF

0603

20%

Place close to U1000 on bottom side

4V

X6S-CERM

10UF

0603

20%

Place close to U1000 on bottom side

4V

X6S-CERM

10UF

0603

20%

Place close to U1000 on bottom side

4V

X6S-CERM

10UF

0603

20%

Place close to U1000 on bottom side

4V

X6S-CERM

10UF

0603

20%

Place close to U1000 on bottom side

4V

X6S-CERM

10UF

0603

20%

Place close to U1000 on bottom side

X6S-CERM

10UF

0603

20%

4V

10UF

Place close to U1000 on bottom side

4V

X6S-CERM

0603

20%

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

4V

X6S-CERM

10UF

0603

20%

4V

X6S-CERM

10UF

0603

20%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

Place on bottom side of U100.

10V

X6S-CERM

0402

1UF

10%

4V

X6S-CERM

10UF

0603

20%

4V

X6S-CERM

10UF

0603

20%

Place on bottom side of U1000

10V

X6S-CERM

0402

1UF

10%

4V

X6S-CERM

10UF

0603

20%

MF

1/4W

1%

0.010

0603

330UF-0.006OHM

POLY

2V

CASE-D2-SM

Place near inductors on bottom side

20%

330UF-6MOHM

2.0V

CRITICAL

POLY-TANT

D15T

20%

330UF-6MOHM

2.0V

POLY-TANT

D15T

CRITICAL

20%

330UF-6MOHM

2.0V

POLY-TANT

CRITICAL

D15T

20%

CRITICAL

D15T-ECGLT-COMBO

330UF-6MOHM

20%

2.0V

POLY-TANT

SYNC_MASTER=D2_SEAN

CPU DECOUPLING-II

SYNC_DATE=03/05/2012

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

=PP1V5_S3_CPU_VCCDQ

C1717

1

2

C1716

1

2

C1715

1

2

C1714

1

2

C1713

1

2

C1712

1

2

C1711

1

2

C1710

1

2

C1709

1

2

C1708

1

2

C1707

1

2

C1706

1

2

C1725

1

2

C1724

1

2

C1733

1

2

C1732

1

2

C1705

1

2

C1723

1

2

C1704

1

2

C1722

1

2

C1703

1

2

C1721

1

2

C1731

1

2

C1730

1

2

C1729

1

2

C1702

1

2

C1701

1

2

C1720

1

2

C1719

1

2

C1700

1

2

C1718

1

2

C1728

1

2

C1727

1

2

C1726

1

2

C1757

1

2

C1747

1

2

C1746

1

2

C1745

1

2

C1744

1

2

C1743

1

2

C1742

1

2

C1741

1

2

C1740

1

2

C1739

1

2

C1738

1

2

C1755

1

2

C1754

1

2

C1753

1

2

C1752

1

2

C1751

1

2

C1750

1

2

C1749

1

2

C1748

1

2

C1762

1

2

C1761

1

2

C1767

1

2

C1766

1

2

C1760

1

2

C1759

1

2

C1765

1

2

C1764

1

2

C1758

1

2

C1763

1

2

R1700

1 2

C1756

1

2

C1735

1

23

C1737

1

23

C1734

1

23

C1768

1

23

051-9589

4.18.0

17 OF 132

16 OF 99

8

13

8

11 14 27

8

13 14

8

13

IN

OUT

IN

BI

IN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

SATA3COMPI

SATA3RCOMPO

SATA0GP/GPIO21

SATA1GP/GPIO19

SATALED*

SATA3RBIAS

SATAICOMPO

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN

SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0

HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33

HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1

RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1

FWH2/LAD2

FWH3/LAD3

FWH4/LFRAME*

SATA1RXP

SATA1TXN

SATA2TXN

SATA2TXP

SATA3RXN

SATA3RXP

SATA3TXN

SATA3TXP

SATA4RXN

SATA4RXP

SATA4TXN

SATA4TXP

SATA5RXN

SATA5TXN

SATA5TXP

SATAICOMPI

JTAG

SPI

SATA

LPC

IHDA

RTC

(1 OF 10)

PEG_B_CLKRQ*/GPIO56

CLKOUT_PEG_B_N

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ1*/GPIO18

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE2N

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N

CLKOUT_PCIE1P

CLKOUT_PCIE0N

CLKOUT_PCIE0P

PERN3

PETP2

PETN2

PERP1

PETN1

PERN1

SMBCLK

SMBALERT*/GPIO11

PETP8

PERP8

PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6

PETP6

PERP6

PERN6

PETP5

PETN5

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP3

PERN2

PERP2

PETP1

SMBDATA

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PEG_B_P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

CLKOUT_PEG_A_N

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_P

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1*

C-LINK

PCI-E*

CLOCKS

FLEX

SMBUS

(2 OF 10)

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

OUT

NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

VSel strap not functional (VCCVRM = 1.8V)

Unused clock terminations for FCIM Mode

1.8V -> 1.1V

(IPD-PWROK)

If HDA = S0, must also ensure that signal cannot be high in S3.

(IPD-BOOT)

(IPD)

(IPU)

(IPD-PLTRST#)

(IPD-PWROK)

(IPU-RSMRST#)

(IPD)

(IPU-RSMRST#)

(IPU)

(IPD-PWROK)

(IPU)

(IPD-BOOT)

(IPU)

Controlled by PCIECLKRQ5#

(IPD)

(IPD-BOOT)

(IPU/IPD)

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

(IPU/IPD)

33MHz clocks must be matched within 5"

(IPD-PWROK)

25 91

53 92

43 92

7

41 43

39 91

7

38 92

7

38 92

34 92

9

7

38 92

7

38 92

34 92

9

44 92

9

1/20W

5%

201

MF

330K

1M

1/20W

5%

201

MF

1/20W

5%

201

MF

20K

1/20W

5%

201

MF

20K

10V

10%

X5R

1UF

402

10V

10%

402

X5R

1UF

1/20W

1%

201

MF

37.4

PLACE_NEAR=U1800.Y11:2.54mm

1/20W

5%

201

MF

10K

PLACE_NEAR=U1800.Y47:2.54mm

90.9

1/20W

1%

201

MF

44 92

20

MOBILE

OMIT_TABLE

FCBGA

PANTHERPOINT

FCBGA

MOBILE

PANTHERPOINT

OMIT_TABLE

17

24

NO STUFF

1/20W

5%

201

MF

0

NO STUFF

1/20W

5%

201

MF

0

MF-LF

1/16W

1%

402

604

1/20W

1%

201

MF

1K

25 91

25

1/20W

1%

201

MF

750

PLACE_NEAR=U1800.AH1:2.54mm

1%

201

49.9

PLACE_NEAR=U1800.AB12:2.54mm

MF

1/20W

24

34 92

9

92

17 34

9

92

17 39

17

44 92

11 89

9

17 92

25 92

9

17

9

91

9

91

9

91

9

91

7

17 38

71 92

35 92

17 37

4.7K

1/20W

5% MF

201

1/20W

5%

201

MF

4.7K

201

MF

10K

5%

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

201

1/20W

5% MF

10K

1/20W

5%

201

MF

10K

MF

1/20W

5%

10K

201

10K

1/20W

5%

201

MF

1/20W

5%

201

MF

10K

201

MF

1/20W

5%

10K

1/20W

5%

201

MF

GPU:1P

10K

1/20W

MF

201

5%

17 26

17

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

PLACE_NEAR=U1800.K34:1.27mm

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.A36:1.27mm

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.N34:1.27mm

1/20W

5%

201

MF

33

PLACE_NEAR=U1800.L34:1.27mm

1/20W

5%

201

MF

33

53 92

7

41 43 82 92

7

41 43 82 92

7

41 43 82 92

7

41 43 82 92

1/20W

5%

33

201

MF

1/20W

5%

201

MF

33

1/20W

5%

201

MF

33

1/20W

5%

201

MF

33

7

41 43 82 92

201

MF

33

1/20W

5%

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

MF

1/20W

5%

201

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

7

38 92

7

38 92

39 92

GPU:2P

10K

5%

201

MF

1/20W

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

PCIE_CLK100M_PCH_N

TP_PCIE_CLK100M_PEBN

TP_PCH_GPIO64_CLKOUTFLEX0

SYSCLK_CLK25M_SB_R

PCIE_ENET_D2R_N

SPI_MISO

SPI_MOSI_R

TP_SPI_CS1_L

SPI_CLK_R

SPI_CS0_R_L

PEGCLKRQB_L_GPIO56PEGCLKRQB_L_GPIO56

ENET_CLKREQ_L

HDA_BIT_CLK

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

RTC_RESET_L

HDA_SYNC_R

SMBUS_PCH_ALERT_L

LPC_FRAME_R_L

TP_LPC_DREQ0_L

PCIE_AP_R2D_C_N

FW_CLKREQ_L

SSD_CLKREQ_L

PCIE_CLK100M_SSD_P

PCH_SATA3RBIAS

PCH_SATA3COMP

SMBUS_PCH_ALERT_L

SMBUS_PCH_CLK

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCIE_7_R2D_CN

TP_PCIE_6_R2D_CP

TBT_PWR_EN_PCH

PCH_SATALED_L

PCH_INTRUDER_L

TP_PCIE_8_D2RN

TP_PCIE_5_R2D_CN

TP_PCIE_5_R2D_CP

TP_PCIE_6_D2RN

TP_PCIE_6_D2RP

TP_PCIE_6_R2D_CN

TP_PCIE_7_D2RN

TP_PCIE_7_D2RP

TP_PCIE_8_D2RP

TP_PCIE_8_R2D_CP

TP_PCIE_7_R2D_CP

TP_PCIE_8_R2D_CN

TP_PCIE_5_D2RN

TP_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

PCIE_FW_R2D_C_N

PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N

PCIE_AP_D2R_P

LPC_SERIRQ

SATA_HDD_D2R_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_E_D2RN

TP_SATA_E_D2RP

TP_SATA_F_R2D_CN

LPC_AD_R<0>

LPC_AD<1>

TP_PCIE_CLK100M_PEBP

PCH_CLK14P3M_REFCLK

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

PCH_CLKIN_GNDN1

USB_EXTB_SEL_XHCI

=PP1V05_S0_PCH_VCCIO_SATA

ENET_CLKREQ_L

PCIE_FW_D2R_N

PCIE_FW_D2R_P

LPC_AD_R<1>

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_F_D2RN

PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

PCH_CLKIN_GNDP1

PCH_CLKIN_GNDN1

JTAG_DPMUXUC_TRST_L

ENET_MEDIA_SENSE_RDIV

USB_EXTD_SEL_XHCI

USB_EXTB_SEL_XHCI

PEG_CLKREQ_L

EXCARD_CLKREQ_L

DP_AUXCH_ISOL

PCH_SPKR

HDA_SDOUT_R

=PP1V05_S0_PCH_VCCDIFFCLK

SML_PCH_1_CLK

SML_PCH_1_DATA

ITPCPU_CLK100M_P

ENET_MEDIA_SENSE_RDIV

XDP_PCH_TMS

TP_SATA_C_D2RP

LPC_AD_R<3>

LPC_AD_R<1>

TP_SATA_C_D2RN

TP_HDA_SDIN2

TP_HDA_SDIN3

JTAG_ISP_TMS

PCIE_CLK100M_AP_N

PCH_SPKR

HDA_SDIN0

TP_HDA_SDIN1

XDP_PCH_TDO

=PPVRTC_G3_PCH

=PP3V3_S0_PCH

PEGCLKRQB_L_GPIO56

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO67_CLKOUTFLEX3

PCH_CLKIN_GNDP1

TP_PCIE_CLK100M_PEGAN

PEGCLKRQA_L_GPIO47

TP_PCIE_CLK100M_PEGAP

TP_CLINK_CLK

TP_CLINK_DATA

TP_CLINK_RESET_L

SMBUS_PCH_DATA

SML_PCH_0_CLK

SML_PCH_0_DATA

USB_EXTD_SEL_XHCI

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_P

PCH_CLK33M_PCIIN

PCIE_ENET_D2R_P

PCIE_AP_R2D_C_P

PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_P

PCIE_EXCARD_R2D_C_N

AP_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PEG_CLK100M_N

LPC_AD<0>

LPC_AD_R<3>

LPC_FRAME_R_L

LPC_FRAME_L

HDA_BIT_CLK_R

HDA_RST_R_L

LPC_AD_R<0>

TP_SATA_D_D2RN

SATA_HDD_R2D_C_P

PCH_INTRUDER_L

PCH_INTVRMEN_L

SYSCLK_CLK25M_SB

PCIE_CLK100M_AP_P

XDP_PCH_TDI

HDA_SDOUT_R

LPC_AD_R<2>

PCIE_ENET_R2D_C_N

PCH_CLK100M_SATA_N

TP_PCIE_CLK100M_PE4P

PCH_XCLK_RCOMP

EXCARD_CLKREQ_L

TP_SATA_F_D2RP

TP_SATA_F_R2D_CP

PCIE_CLK100M_PCH_N

HDA_SYNC_R

LPC_AD_R<2>

HDA_BIT_CLK_R

HDA_RST_R_L

XDP_PCH_TCK

SYSCLK_CLK32K_RTC

TBT_CLKREQ_L

LPC_AD<2>

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

PEGCLKRQA_L_GPIO47

FW_CLKREQ_L

SATARDRVR_EN

AP_CLKREQ_L

JTAG_DPMUXUC_TRST_L

PCH_SATALED_L

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SYSCLK_CLK25M_SB_R

PCH_CLK96M_DOT_P

PCIE_CLK100M_TBT_P

LPC_AD<3>

HDA_SYNC

HDA_RST_L

PCH_INTVRMEN_L

PCH_SRTCRST_L

RTC_RESET_L

HDA_SDOUT

ITPCPU_CLK100M_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

TBT_CLKREQ_L

PCIE_CLK100M_TBT_N

PEG_CLKREQ_L

PEG_CLK100M_P

PCH_SATAICOMP

=PP1V05_S0_PCH

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCH_SRTCRST_L

PCIE_CLK100M_SSD_N

TP_PCIE_CLK100M_PE4N

PCIE_CLK100M_EXCARD_N

SSD_CLKREQ_L

=PP3V3_SUS_PCH_GPIO

=PP3V3_S0_PCH_GPIO

R1800

1

2

R1801

1

2

R1802

1

2

R1803

1

2

C1803

1

2

C1802

1

2

R1830

1

2

R1820

1

2

R1890

1

2

U1800

C38

A38

B37

C37

D36

N34

C36

N32

K34

E34

G34

C34

A34

A36

L34

K22

C17

J3

K5

H1

H7

E36

K36

D20

A20

C20

V14

AM3

AM1

AP7

AP5

P1

AM10

AM8

AP11

AP10

AD7

AD5

AH5

AH4

AB13

AH1

AB12

AB8

AB10

AF3

AF1

Y7

Y5

AD3

AD1

Y3

Y1

AB3

AB1

Y10

Y11

P3

V5

T3

Y14

T1

U3

V4

T10

G22

U1800

M7

T11

P10

BF18

BE18

G24

E24

BJ30

BG30

H45

AK7

AK5

AV22

AU22

AM12

AM13

AK14

AK13

Y40

Y39

AB49

AB47

AA48

AA47

Y37

Y36

Y43

Y45

V45

V46

V40

V42

V38

V37

AB37

AB38

AB42

AB40

K43

F47

H47

K49

J2

M1

V10

A8

L12

L14

T13

K12

M10

E6

BG34

BE34

BG36

BF36

BG37

BJ38

BG40

BE38

BJ34

BF34

BJ36

BE36

BH37

BG38

BJ40

BC38

AV32

BB32

AV34

AY34

AY36

AU36

AY40

AW38

AU32

AY32

AU34

BB34

BB36

AV36

BB40

AY38

K45

E12

H14

C9

A12

C8

G12

C13

E14

M16

Y47

V47

V49

R1840

1 2

R1841

1 2

R1872

1 2

R1873

1

2

R1832

1

2

R1831

1

2

R1877

1 2

R1878

1 2

R1834

1 2

R1842

1 2

R1869

1 2

R1844

1 2

R1845

1 2

R1847

1 2

R1814

2 1

R1815

1 2

R1843

1 2

R1833

1 2

R1879

1 2

R1846

1 2

R1853

1 2

R1848

1 2

R1854

1 2

R1855

1 2

R1812

1 2

R1813

1 2

R1810

1 2

R1811

1 2

R1861

1 2

R1862

1 2

R1863

1 2

R1864

1 2

R1860

1 2

R1891

1 2

R1892

1 2

R1893

1 2

R1894

1 2

R1895

1 2

R1896

1 2

R1897

1 2

R1870

1 2

R1871

1 2

R1880

1 2

051-9589

4.18.0

18 OF 132

17 OF 99

7

9

17 91

17 17

7

17 38

17

17 92

17

7

17

91

17

9

7

17

7

17

7

17

8

21 23

17

7

17 92

17

17 26

9

17

24 25

17

17 25 92

8

21 23

11 89

17

7

17

7

8

18 21

8

23

17

9

17

7

17

17 92

17

7

17

17 25 92

17

7

17 92

17

17 92

17 37

17

24

17 34

17

17 91

17 92

17

11 89

17 92

24 89

91

8

23

9

92

9

92

17

7

17 39

8

18 19 20

8

18 19 20 25 37

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

DMI1TXP

SUSACK*

DMI_ZCOMP

DMI0TXN

FDI_RXN6

FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1

FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

DMI2TXN

DMI1TXN

DMI3TXN

DMI3TXP

FDI_RXN0

FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4

FDI_RXN5

DMI0RXN

FDI_RXP6

DMI1RXN

DMI0TXP

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

DMI3RXN

DMI2RXN

DMI2TXP

DMI2RBIAS

DMI_IRCOMP

SUS_STAT*/GPIO61

SLP_S4*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SLP_SUS*

SLP_A*

SLP_S3*

PMSYNCH

SLP_LAN*/GPIO29

SYS_RESET*

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30

PWRBTN*

ACPRESENT/GPIO31

BATLOW*/GPIO72

RI*

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SYSTEM POWER

MANAGEMENT

FDI

DMI

(3 OF 10)

LVD_VBG

DDPD_3P

DDPD_2P

DDPD_3N

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0P

DDPD_0N

DDPD_HPD

DDPD_AUXN

DDPD_AUXP

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3P

DDPC_3N

DDPC_2P

DDPC_2N

DDPC_0P

DDPC_1P

DDPC_1N

DDPC_0N

DDPC_HPD

DDPC_AUXN

DDPC_AUXP

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3P

DDPB_3N

DDPB_1P

DDPB_2P

DDPB_2N

DDPB_1N

DDPB_0P

DDPB_HPD

DDPB_0N

DDPB_AUXN

DDPB_AUXP

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTP

SDVO_INTN

SDVO_STALLP

SDVO_STALLN

SDVO_TVCLKINP

SDVO_TVCLKINN

L_CTRL_CLK

DAC_IREF

CRT_IRTN

CRT_VSYNC

CRT_HSYNC

CRT_DDC_DATA

CRT_DDC_CLK

CRT_RED

CRT_GREEN

CRT_BLUE

L_VDD_EN

L_DDC_DATA

L_CTRL_DATA

LVD_IBG

LVD_VREFH

LVD_VREFL

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA0*

LVDSA_DATA1*

LVDSA_DATA2*

LVDSA_DATA3*

LVDSA_DATA0

LVDSA_DATA1

LVDSA_DATA2

LVDSA_DATA3

LVDSB_CLK*

LVDSB_CLK

LVDSB_DATA0*

LVDSB_DATA1*

LVDSB_DATA2*

LVDSB_DATA0

LVDSB_DATA3*

LVDSB_DATA3

LVDSB_DATA1

LVDSB_DATA2

L_DDC_CLK

L_BKLTCTL

L_BKLTEN

LVDS

(4 OF 10)

DIGITAL DISPLAY INTERFACE

CRT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-DeepS4/S5)

(IPU)

(IPD-PLTRST#)

(IPD)

10 89

9

49.9

1%

MF

201

PLACE_NEAR=U1800.BJ24:12.7mm

1/20W

10 89

PLACE_NEAR=U1800.T43:2.54mm

201

MF

1/20W

5%

1K

PLACE_NEAR=U1800.BH21:2.54mm

1%

1/20W

MF

201

750

OMIT_TABLE

PANTHERPOINT

FCBGA

MOBILE

PANTHERPOINT

FCBGA

MOBILE

OMIT_TABLE

390K

5%

1/20W

MF

201

MF

5%

10K

1/20W

5%

1/20W

201

MF

0

18 70

100K

5%

MF

201

1/20W

25 41

24 41 70

11 27 89

25 70

70

18 24 41

41 42 70

42

7

18 34

7

18 41 43

7

25 41 43

42

18 41 70

7

18 27 34 38 40 41 70

7

18 27 38 41 70

11 89

41

9

PLACE_NEAR=U1800.AF37:2.54mm

2.37K

1%

1/20W

MF

201

9

18

9

18

7

9

91

7

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

7

9

100K

201

MF

1/20W

5%

1K

1/20W

201

MF

201

1/20W

5%

8.2K

5%

1K

1/20W

MF

201

100K

201

MF5%

1/20W

100K

201

MF5%

5%

201

MF

1/20W

100K

201

MF

1/20W

5%

10K

35 42

10K

5%

1/20W

201

MF

18 64

100K

201

MF5%

1/20W

5% MF

201

100K

NOSTUFF

5%

1/20W

201

MF

0

SYNC_MASTER=D2_KEPLER

PCH DMI/FDI/PM/Graphics

SYNC_DATE=01/13/2012

PCIE_WAKE_L

MAKE_BASE=TRUE

PCH_DMI_COMP

DMI_S2N_P<3>

=FDI_DATA_P<6>

=FDI_DATA_P<5>

=FDI_DATA_P<3>

=FDI_DATA_P<2>

=PP3V3_SUS_PCH_GPIO

PCH_DSWVRMEN

PM_DSW_PWRGD

PM_SLP_S3_L

=FDI_FSYNC<0>

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCIO_PCIE

PCH_SUSACK_L

PM_PCH_APWROK

PM_MEM_PWRGD

PM_RSMRST_L

PCH_SUSWARN_L

PM_PWRBTN_L

=FDI_LSYNC<1>

PM_SYNC

=FDI_DATA_P<1>

=FDI_DATA_P<4>

=FDI_DATA_P<0>

=FDI_DATA_P<7>

=FDI_DATA_N<7>

=FDI_DATA_N<6>

=FDI_DATA_N<5>

=FDI_DATA_N<0>

=FDI_DATA_N<4>

=FDI_DATA_N<3>

=FDI_DATA_N<2>

=FDI_DATA_N<1>

PM_CLKRUN_L

=FDI_FSYNC<1>

PCH_SUSACK_L

LPC_PWRDWN_L

TP_PM_SLP_A_L

PM_SLP_S4_L

PCIE_WAKE_L

PM_SLP_S5_L

DMI_N2S_N<0>

DMI_N2S_N<1>

DMI_N2S_N<2>

DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<3>

DMI_N2S_P<1>

DMI_N2S_P<2>

DMI_S2N_N<0>

DMI_S2N_N<1>

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_P<1>

DMI_S2N_P<2>

PCH_LVDS_IBG

TP_PCH_LVDS_VBG

TP_DP_IG_D_MLP<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_HPD

TP_DP_IG_D_AUXN

TP_DP_IG_D_AUXP

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLN<0>

DPB_IG_HPD

DPB_IG_AUX_CH_N

DPB_IG_AUX_CH_P

DPB_IG_DDC_DATA

DPB_IG_DDC_CLK

TP_DP_IG_B_MLP<3>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLP<0>

DPA_IG_HPD

TP_DP_IG_B_MLN<0>

DPA_IG_AUX_CH_N

DPA_IG_AUX_CH_P

DPA_IG_DDC_CLK

DPA_IG_DDC_DATA

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_LVDS_IG_CTRL_CLK

PCH_DAC_IREF

TP_CRT_IG_VSYNC

TP_CRT_IG_HSYNC

TP_CRT_IG_DDC_DATA

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_GREEN

TP_CRT_IG_BLUE

LVDS_IG_PANEL_PWR

LVDS_IG_DDC_DATA

TP_LVDS_IG_CTRL_DATA

LVDS_IG_DDC_CLK

LVDS_IG_BKL_PWM

LVDS_IG_BKL_ON

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<3>

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_CLK_P

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_P<3>

PCH_DMI2RBIAS

PM_PCH_PWROK

PM_PCH_SYS_PWROK

PM_SLP_SUS_L

MEM_VDD_SEL_1V5_L

PCH_SUSWARN_L

PM_SYSRST_L

PM_BATLOW_L

SMC_ADAPTER_EN

=FDI_LSYNC<0>

=PP3V3_S5_PCH

PM_PWRBTN_L

MEM_VDD_SEL_1V5_L

PM_CLKRUN_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_SUS_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

PCH_RI_L

FDI_INT

=PP3V3_SUS_PCH_GPIO

=TBT_WAKE_L

R1900

1

2

R1951

1

2

R1920

1

2

U1800

H20

L10

E10

N3

BC24

BE24

AW24

AY24

BE20

BC20

AW20

AY20

BH21

BG18

BJ18

BB18

AY18

BG20

BJ20

AV18

AU18

BG25

BJ24

E22

B13

A18

AV12

BC10

AW16

AV14

BB10

BJ14

AY14

BE14

BH13

BC12

BJ12

BG10

BG9

BG14

BB14

BF14

BG13

BE12

BG12

BJ10

BH9

AP14

E20

L22

A10

C21

G10

K14

F4

H4

D10

G16

G8

C12

N14

K16

P12

K3 B9

U1800

N48

T39

M40

P49

M47

T42

T49

M49

T43

AV42

AV40

AV45

AV46

AU48

AU47

AV47

AV49

AT49

AT47

AT40

AY47

AY49

AY43

AY45

BA47

BA48

BB47

BB49

AP47

AP49

P46

P42

AT38

BB43

BB45

BF44

BE44

BF42

BE42

BJ42

BG42

AT45

AT43

M43

M36

BH41

P45

J47

T45

P39

T40

K47

M45

AF37

AF36

AE48

AE47

AK40

AK39

AN47

AN48

AM49

AM47

AK49

AK47

AJ47

AJ48

AF39

AF40

AH43

AH45

AH49

AH47

AF47

AF49

AF43

AF45

P38

M39

AP39

AP40

AM42

AM40

AP43

AP45

R1915

1

2

R1905

1

2

R1986

12

R1909

1

2

R1950

1

2

R1923

2 1

R1925

1 2

R1991

1 2

R1985

1 2

R1922

2 1

R1921

2 1

R1924

2 1

R1983

1

2

R1982

1 2

R1984

2 1

R1981

2 1

R1999

12

051-9589

4.18.0

19 OF 132

18 OF 99

7

18 34

8

17 18 19 20

8

17 21

8

18

7

9

82

83 95

83

9

82

9

83 95

83

7

18

8

18 24 41

18 64

7

18 41 43

7

18 27 38 41 70

7

18 27 34 38 40 41 70

18 70

18 41 70

9

18

9

18

8

17 19 20 25 37

8

17 18 19 20

8

17 18 19 20

USB3RP4

USB3RP3

USB3RP2

USB3RP1

USB3RN1

RSVD8

RSVD9

RSVD10

RSVD12

USBP0N

USBP0P

USBP1N

USBP2N

USBP1P

USBP2P

USBP3N

USBP4N

USBP3P

USBP4P

USBP5N

USBP5P

USBP6P

USBP6N

USBP7N

USBP7P

USBP8P

USBP8N

USBP9N

USBP9P

USBP10P

USBP10N

USBP11N

USBP11P

USBP12P

USBP12N

USBP13N

USBP13P

OC0*/GPIO59

USBRBIAS*

USBRBIAS

OC1*/GPIO40

OC2*/GPIO41

OC3*/GPIO42

OC4*/GPIO43

OC5*/GPIO9

OC6*/GPIO10

OC7*/GPIO14

PIRQA*

PIRQB*

PIRQC*

REQ1*/GPIO50

PIRQD*

REQ3*/GPIO54

REQ2*/GPIO52

GNT1*/GPIO51

GNT2*/GPIO53

GNT3*/GPIO55

PIRQE*/GPIO2

PIRQF*/GPIO3

PIRQG*/GPIO4

PME*

PIRQH*/GPIO5

PLTRST*

CLKOUT_PCI0

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI4

CLKOUT_PCI3

RSVD1

TP1

TP2

RSVD2

RSVD3

TP3

TP4

RSVD4

RSVD5

TP5

TP6

RSVD6

RSVD7

TP7

TP8

TP9

TP10

RSVD11

TP11

RSVD13

TP14

RSVD14

RSVD15

TP15

TP16

RSVD16

RSVD17

TP17

TP18

RSVD18

RSVD19

TP19

TP20

RSVD20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

RSVD27

RSVD26

RSVD28

RSVD29

TP13

TP12

TP23

TP22

TP21

USB3RN4

USB3RN3

USB3RN2

USB3TN2

USB3TN1

USB3TN3

USB3TN4

USB3TP1

USB3TP2

USB3TP3

USB3TP4

TP24

PCI USB

(5 OF 10)

NC

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

BI

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD)

Redundant to pull-up on audio page

Unused

USB Hub (All LS/FS Devices)

Ext C (XHCI/EHCI)

Camera

RSVD: SD

Ext D (EHCI)

RSVD: WiFi

Unused

(IPU)

(IPD)

Ext B (XHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

Ext B (EHCI)

Ext A (XHCI/EHCI)

(IPU-PCIERST#)

RSVD: BT (HS)

Redundant to pull-up on audio page

Unused

OMIT_TABLE

PANTHERPOINT

MOBILE

FCBGA

26 91

9

26 91

9

91

9

91

26 91

40 91

7

38 91

7

38 91

9

91

9

91

9

91

9

91

9

1/20W

10K

MF

201

5%

1/20W

201

MF

10K

201

1/20W

5% MF

10K

MF

1/20W

5%

201

10K

NO STUFF

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

MF

10K

201

5%

1/20W

201

10K

MF5%

1/20W

NO STUFF

10K

MF

201

5%

1/20W

5%

10K

MF

201

1/20W

19

19 59

19 35

19 58

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

10K

NO STUFF

MF

201

5%

1/20W

10K

1/20W

5%

201

MF

19 24

24

19 24

40 91

19 24

MF

1/20W

5%

201

1K

201

1K

MF5%

1/20W

40 91

34 91

1%

1/20W

MF

201

PLACE_NEAR=U1800.B33:2.54mm

22.6

25 27

25

25 92

25

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

PCH PCI/USB/TP/RSVD

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

TP_PCH_STRP_ESI_L

PCH_STRP_TOPBLK_SWP_L

AUD_IP_PERIPHERAL_DET

TP_PCH_STRP_BBS1

PCH_CLK33M_PCIOUT

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

TP_PCH_TP23

=PP3V3_S3_PCH_GPIO

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

AUD_IP_PERIPHERAL_DET

USB3_EXTD_RX_P

TP_PCI_PME_L

TP_USB_BT_HSP

AUD_I2C_INT_L

LPC_CLK33M_LPCPLUS_R

USB3_EXTA_TX_N

USB_EXTC_N

USB3_EXTA_TX_P

USB3_EXTD_TX_N

USB3_EXTB_RX_P

USB3_EXTC_RX_P

USB3_EXTA_RX_N

PCI_INTD_L

PCI_INTC_L

PCI_INTB_L

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

JTAG_GMUX_TMS

USB3_EXTC_TX_P

USB3_EXTD_TX_P

USB3_EXTC_TX_N

USB3_EXTB_TX_N

USB3_EXTD_RX_N

USB3_EXTC_RX_N

USB3_EXTB_RX_N

USB_CAMERA_N

USB_HUB_UP_P

TP_USB_WLANP

TP_USB_4P

TP_USB_4N

USB_EXTB_XHCI_P

USB_EXTA_N

PLT_RESET_L

TBT_PWR_REQ_L

BLC_GPIO

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

USB_EXTA_P

USB_EXTB_XHCI_N

USB_EXTD_XHCI_P

USB_EXTD_XHCI_N

USB_EXTC_P

USB3_EXTB_TX_P

TP_USB_12P

USB_EXTB_EHCI_N

USB_EXTB_EHCI_P

USB_EXTD_EHCI_N

TP_USB_BT_HSN

USB_CAMERA_P

USB_HUB_UP_N

TP_USB_WLANN

TP_USB_SDP

TP_USB_SDN

PCH_USB_RBIAS

AUD_I2C_INT_L

AP_PWR_EN

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

TP_USB_12N

USB3_EXTA_RX_P

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

TP_USB_13P

PCI_INTA_L

TP_PCI_CLK33M_OUT2

=PP3V3_S0_PCH_GPIO

TP_PCI_CLK33M_OUT3

JTAG_GMUX_TMS

LPC_CLK33M_SMC_R

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

TBT_PWR_REQ_L

BLC_GPIO

USB_EXTD_EHCI_P

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

TP_USB_13N

R2070

1

2

U1800

H49

H43

J48

K42

H40

D47

E42

F46

A14

K20

B17

C16

L16

A16

D14

C14

K40

K38

H38

G38

G42

G40

C42

D44

C6

K10

C46

C44

E40

AY7

AT1

AY3

AT5

AV3

AV1

BB1

BA3

BB5

BB3

BB7

AV7

BE8

BD4

BF6

AV5

AV10

AT8

AY5

BA2

AT12

BF3

AU3

BG4

AT10

BC8

AU2

AT4

AT3

BG26

C18

N30

H3

AH12

AM4

AM5

Y13

K24

L24

AB46

BJ26

AB45

B21

M20

AY16

BG46

BH25

BJ16

BG16

AH38

AH37

AK43

AK45

BE28

BC30

BE32

BJ32

BC28

BE30

BF32

BG32

AV26

BB26

AU28

AY30

AU26

AY26

AV28

AW30

C24

A24

C30

A30

L32

K32

G32

E32

C32

A32

C25

B25

C26

A26

K28

H28

E28

D28

C28

A28

C29

B29

N28

M28

L30

K30

G30

E30

B33

C33

R2067

2 1

R2068

1 2

R2061

1 2

R2062

1 2

R2033

1 2

R2060

1 2

R2030

1 2

R2018

1 2

R2016

1 2

R2017

1 2

R2014

1 2

R2031

1 2

R2010

1 2

R2011

1 2

R2012

1 2

R2013

1 2

R2054

2 1

R2069

1 2

R2020

1 2

R2021

1 2

051-9589

4.18.0

20 OF 132

19 OF 99

19 24 19 24

8

25

19 24

19 59

7

19 35

19

91

19 58

24 34 70

8

17 18 19 20 25 37

8

17 18 20 25

8

17 18 19 20 25 37

7

19

OUT

BI

IN

NC

IN

OUT

IN

BI

ININ

OUT

IN

OUT

SATA2GP/GPIO36

SATA3GP/GPIO37

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_29

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_24

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_19

VSS_NCTF_21

VSS_NCTF_20

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_14

NC_1

TS_VSS4

TS_VSS3

TS_VSS1

TS_VSS2

DF_TVS

INIT3_3V*

THRMTRIP*

PROCPWRGD

RCIN*

PECI

A20GATE

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

TACH4/GPIO68

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_9

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_4

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_0

VSS_NCTF_1

SATA5GP/GPIO49/TEMP_ALERT*

SLOAD/GPIO38

GPIO27

GPIO24

GPIO57

SDATAOUT1/GPIO48

BMBUSY*/GPIO0

TACH1/GPIO1

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

TACH2/GPIO6

SDATAOUT0/GPIO39

GPIO35

SCLOCK/GPIO22

TACH0/GPIO17

GPIO8

TACH3/GPIO7

GPIO28

STP_PCI*/GPIO34

GPIO

CPU/MISC

(6 OF 10)

NCTF

OUT

BI

IN

OUT

IN

OUT

IN

D

GS

D

S G

D

S G

IN

OUT

08

Y1

Y2

GND

B2

VCC

A1

B1

A2

OUT

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-PLTRST#)

(IPD-PLTRST#?)

(IPU-DeepS4/S5)

(IPU-RSMRST#)

(IPU)

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPU)

(IPD)

Set to Vcc when High

Set to Vss when Low

DF_TVS:DMI & FDI Term Voltage

(IPU-RSMRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

Must stuff R2197 when R2180 NO STUFFed.

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOS

NOTE: TMS/TDI from PCH is Open Drain

NOTE: TDO from CR is Push-Pull CMOS

(TBT_CIO_PLUG_EVENT_ISOL)

Stuff R2160 or R2574, not both

TBT_PWR_EN goes high for JTAG Programming

(IPD-PLTRST#)

current limiting 1K resistor R2574

Connects to PCH through

11 24 89

24

7

20 43

20 82

1/20W

5%

201

MF

1K

NO STUFF

20

24

20

24

20

7

20 43 52

11 42 89

1/20W

5%

201

MF

10K

RAMCFG3:H

1/20W

5%

201

MF

10K

RAMCFG2:H RAMCFG1:H

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

RAMCFG0:H

20 41

24

20

20 41

20 25

FCBGA

MOBILE

PANTHERPOINT

OMIT_TABLE

1/20W

5%

201

MF

1K

1/20W

5%

201

MF

2.2K

201

1/20W

5% MF

20K

1/20W

5%

201

MF

100K

MF

1/20W

5%

201

10K

201

MF

1/20W

5%

10K

201

1/20W

100K

MF5%

201

MF

1/20W

5%

10K

201

5%

1/20W

MF

NO STUFF

5%

1/20W

201

MF

10K

100K

MF

1/20W

201

5%

10K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

NO STUFF

1/20W

10K

MF5%

201

1/20W

5%

201

MF

10K

24

1/20W

5%

201

MF

0

37

20 24

1/20W

5%

201

MF

10K

5%

1/20W

201

MF

10K

1/20W

MF5%

201

10K

201

5% MF

1/20W

5%

201

MF

43

NO STUFF

1/20W

5%

201

MF

0

1/20W

5%

201

MF

390

11 42 89

24

20

20 24

20

17

1/20W

5%

201

MF

10K

SSM3K15FV

SOD-VESM-HF

CRITICAL

MF

1/20W

5%

201

10K

CRITICAL

SSM6N15AFE

SOT563

201

1/20W

10K

5%

MF

CRITICAL

SSM6N15AFE

SOT563

5%

201

MF

10K

1/20W

5%

201

MF

10K

35

10K

5%

1/20W

MF

201

35

SOT833

74LVC2G08GT

CRITICAL

0201

0.1UF

10%

16V

X5R-CERM

35

201

1/20W

5%

MF

10K

24 35

MF

201

5%

1/20W

10K

25 35

24

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

PCH GPIO/MISC/NCTF

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAMCFG_SLOT

TBT_CIO_PLUG_EVENT_ISOL

JTAG_TBT_TDI

=PP3V3_S0_PCH_GPIO

SPIROM_USE_MLB

TBT_GO2SX_BIDIR

SMC_WAKE_SCI_L

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_SUS_PCH_GPIO

=PP3V3_S5_PCH_GPIO

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

ODD_PWR_EN_L

=PP3V3_S0_PCH_GPIO

JTAG_ISP_TDI

TBT_SW_RESET_R_L

FW_PWR_EN_PCH

SPIROM_USE_MLB

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

ODD_PWR_EN_L

TP_PCH_GPIO8

FW_PME_L

XDP_FC1_PCH_GPIO0

DPMUX_UC_IRQ

LPCPLUS_GPIO

JTAG_ISP_TDO

TBT_PWR_EN

JTAG_TBT_TCK

JTAG_ISP_TCK

TBT_CIO_PLUG_EVENT

=PP3V3_S0_PCH_GPIO

WOL_EN

PCH_A20GATE

FW_PWR_EN_PCH

SMC_RUNTIME_SCI_L

XDP_FC1_PCH_GPIO0

FW_PME_L

TBT_SW_RESET_R_L

PCH_RCIN_L

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_FC0_PCH_GPIO15

LPCPLUS_GPIO

JTAG_ISP_TMS

=PP3V3_S0_PCH_GPIO

JTAG_ISP_TDI

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDOJTAG_ISP_TDO

=PP3V3_S0_PCH_GPIO

ENET_LOW_PWR_PCH

TBT_SW_RESET_L

MLB_RAMCFG1

DPMUX_UC_IRQ

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

TBT_GO2SX_BIDIR

WOL_EN

SMC_RUNTIME_SCI_L

PCH_PECI

PCH_PROCPWRGD

CPU_PECI

MLB_RAMCFG2

=PP3V3_S0_PCH_GPIO

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

MLB_RAMCFG0

MLB_RAMCFG3

PM_THRMTRIP_L

CPU_PWRGD

PCH_INIT3V3_L

PM_THRMTRIP_L_R

PCH_A20GATE

XDP_DC1_PCH_GPIO35_MXM_GOOD

PCH_RCIN_L

PCH_DF_TVS

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

SMC_WAKE_SCI_L

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

R2130

1

2

R2172

1

2

R2173

1

2

R2174

1

2

R2175

1

2

U1800

P4

T7

AY1

G2

E8

E16

P8

K4

D6

C10

T14

C4

P37

AU16

AY11

P5

V8

M5

U2

V3

T5

M3

V13

N2

K1

D40

A42

H36

E38

C40

B41

C41

A40

AY10

AH8

AK11

AH10

AK10

A4

BD49

BE1

BE49

BF1

BF49

BG2

BG48

BH3

BH47

BJ4

A44

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

A45

E49

F1

F49

A46

A5

A6

B3

B47

BD1

R2178

12

R2179

1

2

R2111

2 1

R2195

2 1

R2191

1 2

R2192

1 2

R2193

1 2

R2194

1 2

R2184

1 2

R2197

1 2

R2190

1 2

R2196

1 2

R2185

1 2

R2160

1 2

R2112

2 1

R2180

1 2

R2198

2 1

R2116

2 1

R2150

1 2

R2155

1 2

R2170

1 2

R2140

1 2

R2156

1 2

R2186

1

2

Q2162

3

1

2

R2199

1

2

Q2160

3

5

4

R2188

1

2

Q2160

6

2

1

R2162

1

2

R2161

1

2

R2163

1

2

U2100

1

5

2

6

4

8

7

3

C2113

1

2

R2113

1

2

R2166

1

2

051-9589

4.18.0

21 OF 132

20 OF 99

8

17 18 19 20 25 37

7

20 43 52

20 35

20 41

24 25

8

17 18 19

8

20 24

20

8

17 18 19 20 25 37

20

8

17 18 19 20 25 37

20

20 25

20 41

20 24

20

7

20 43

8

17 18 19 20 25 37

8

20

8

20

8

20

8

17 18 19 20 25 37

9

24 25

9

20 82

20 35

9

8

17 18 19 20 25 37

8

21 23

11 89

9

42

20

NC

VCCTX_LVDS

VSSALVDS

VCCALVDS

VCC3_3_7_HVCMOS

VCC3_3_6_HVCMOS

VCCCORE

VSSADAC

VCCADAC

VCCDMI_2_FDI

VCCIO_27_PLLFDI

VCCAFDIPLL

VCCVRM_2_FDI

VCCIO_26_DP

VCC3_3_3_PCIE

VCCIO_24_PCIE

VCCIO_25_DP

VCCIO_21_PCIE

VCCIO_22_PCIE

VCCIO_23_PCIE

VCCIO_19_PCIE

VCCIO_20_PCIE

VCCIO_18_PCIE

VCCIO_17_PCIE

VCCIO_16_FDI

VCCIO_15_FDI

VCCAPLLEXP

VCCIO_28_PLLPCIE

VCCSPI

VCCDFTERM

VCCCORE

VCCVRM_3_DMI

VCCDMI_1_DMI

VCCCLKDMI

DMI CRT

VCCIO

FDI

DFT/SPI

VCC CORE

(7 OF 10)

HVCMOS

LVDS

NC

VCCIO_34_PLLUSB

VCCRTC

V_PROC_IO

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA

VCCADPLLB

DCPSST

DCPSUS_2_CLK

DCPSUS_1_CLK

VCCDIFFCLKN

VCCDSW3_3

VCCIO_7_CLK

VCC3_3_5_CLK

VCCASW_2_CLK

VCCASW_3_CLK

VCCASW_4_CLK

VCCASW_5_CLK

VCCASW_6_CLK

VCCAPLLDMI2

VCCASW_18_CLK

VCCASW_8_CLK

VCCASW_9_CLK

VCCASW_10_CLK

VCCASW_11_CLK

VCCASW_12_CLK

VCCASW_13_CLK

VCCASW_14_CLK

VCCASW_15_CLK

VCCASW_16_CLK

VCCASW_17_CLK

VCCASW_7_CLK

VCCVRM_4_CLK

VCCASW_20_CLK

VCCASW_19_CLK

VCCSSC

VCCASW_1_CLK

DCPSUS_3_CLK

VCCIO_14_PLLCLK

VCCIO_30_USB

VCCIO_29_USB

VCCIO_31_USB

VCCIO_32_USB

VCCIO_33_USB

VCCSUS3_3_7_USB

VCCSUS3_3_8_USB

VCCSUS3_3_6_USB

VCCSUS3_3_10_USB

VCCSUS3_3_9_USB

DCPSUS_4_USB

V5REF_SUS

VCCSUS3_3_1_USB

VCC3_3_2_SATA

VCCIO_5_PLLSATA

VCCIO_13_SATA3

VCCIO_12_SATA3

VCCAPLLSATA

VCCIO_6_PLLSATA3

VCCIO_2_SATA

VCCVRM_1_SATA

VCCIO_4_SATA

VCCIO_3_SATA

VCCASW_22_MISC

VCCASW_23_MISC

VCCASW_21_MISC

V5REF

VCCSUS3_3_2_GPIO

VCCSUS3_3_4_GPIO

VCCSUS3_3_3_GPIO

VCCSUS3_3_5_GPIO

VCC3_3_1_GPIO

VCC3_3_8_GPIO

VCC3_3_4_GPIO

VCCSUSHDA

USB

SATAMISC

HDA

PCI/GPIO/

LPC

CPURTC

CLK/MISC

(8 OF 10)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VCCAPLLDMI2 pin left as NC per DG

1.44 A Max, 474mA Idle

PCH output, for decoupling only

10 mA Max, 1mA Idle

NC-ed per DG

AL24 left as NC per DG

VCCACLK pin left as NC per DG

55mA Max, 5mA Idle

NC-ed per DG

VCCAPLLSATA pin left as NC per DG

VCCAFDIPLL pin left as NC per DG

PLACE_NEAR=U1800.A22:2.54mm

0.1UF

402

CERM

10V

20%

PLACE_NEAR=U1800.A22:2.54mm

1UF

402

CERM

6.3V

10%

PLACE_NEAR=U1800.V16:2.54mm

20%

10V

CERM

402

0.1UF

PLACE_NEAR=U1800.N16:2.54mm

20%

10V

CERM

402

0.1UF

PLACE_NEAR=U1800.A22:2.54mm

0.1UF

402

CERM

10V

20%

CKPLUS_WAIVE=PwrTerm2Gnd

PANTHERPOINT

FCBGA

MOBILE

OMIT_TABLE

PANTHERPOINT

FCBGA

MOBILE

OMIT_TABLE

SYNC_DATE=03/19/2012SYNC_MASTER=D2_CLEAN

PCH POWER

=LVDS_VCCA

PP3V3_S0_PCH_VCCA_DAC_F

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP5V_S0_PCH_V5REF

=PP1V05_S0_PCH_VCCASW

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_SUS_PCH_VCCSUS

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCSSC

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_CLK

=PP3V3_S5_PCH_VCCDSW

=PP1V05_S0_PCH_VCCDIFFCLK

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F

TP_PPVOUT_PCH_DCPSUSBYP

=PP1V05_S0_PCH_V_PROC_IO

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCIO_PLLUSB

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_VCC_DMI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH_VCCIO_PLLPCIE

TP_1V05_S0_PCH_VCCAPLLEXP

=PP3V3_S0_PCH_VCC3_3_PCI

=PP1V05_S0_PCH_VCCIO

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_S0_PCH_VCC3_3_HVCMOS

PP1V8_S0_PCH_VCCTX_LVDS_F

PP3V3_S0_PCH_VCC3_3_CLK_F

PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

MIN_NECK_WIDTH=0.2 mm

C2232

1

2

C2231

1

2

C2222

1

2

C2210

1

2

C2233

1

2

U1800

BH29

V33

V34

U48

BG6

AK36

BJ22

AB36

AA23

AG26

AG27

AG29

AJ23

AJ26

AJ27

AJ29

AJ31

AC23

AD21

AD23

AF21

AF23

AG21

AG23

AG24

AG16

AG17

AJ16

AJ17

AT20

AU20

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

AP17

AN19

V1

AM37

AM38

AP36

AP37

AP16

AT16

U47

AK37

U1800

N16

V16

T17

V19

AL24

AN23

V12

P34

M26

BJ8

AA16

AJ2

T34

T38

W16

AD49

BD47

BF47

BH23

AK1

AA19

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

AA21

W33

T19

T21

V21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AF33

AF34

AG34

T16

AH13

AH14

AL29

AC16

N26

AC17

P26

P28

T27

T29

T26

AD17

AF13

AF14

AF17

A22

AG33

AN24

V24

N20

N22

P20

P22

P24

T23

T24

V23

P32

AF11

Y49

051-9589

4.18.0

22 OF 132

21 OF 99

8

23

8

23

8

23

8

23 25

8

23

8

21 23

8

21

8

17 21 23

8

17 21 23

8

23

8

23

8

23

8

23

8

21 23

8

23

8

21

8

21 23

8

21 23

8

23

8

17 23

23

8

23

8

17 18

8

23

8

23

8

21

8

20 23

8

23

8

23

8

21

8

23

8

23

VSS

(9 OF 10)

VSS

(10 OF 10)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PANTHERPOINT

FCBGA

MOBILE

OMIT_TABLE

PANTHERPOINT

FCBGA

MOBILE

OMIT_TABLE

PCH GROUNDS

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

U1800

H5

AA17

AB43

AM39

AM43

AM45

AM46

AM7

AN2

AN29

AN3

AN31

AP12

AB5

AP19

AP28

AP30

AP32

AP38

AP4

AP42

AP46

AP8

AR2

AB7

AR48

AT11

AT13

AT18

AT22

AT26

AT28

AT30

AT32

AT34

AC19

AT39

AT42

AT46

AT7

AU24

AU30

AV16

AV20

AV24

AV30

AC2

AV38

AV4

AV43

AV8

AW14

AW18

AW2

AW22

AW26

AW28

AC21

AW32

AW34

AW36

AW40

AW48

AV11

AY12

AY22

AY28

AC24

AC33

AC34

AC48

AA2

AD10

AD11

AD12

AD13

AD19

AD24

AD26

AD27

AD33

AD34

AA3

AD36

AD37

AD38

AD39

AD4

AD40

AD42

AD43

AD45

AD46

AA33

AD8

AE2

AE3

AF10

AF12

AD14

AD16

AF16

AF19

AF24

AA34

AF26

AF27

AF29

AF31

AF38

AF4

AF42

AF46

AF5

AF7

AB11

AF8

AG19

AG2

AG31

AG48

AH11

AH3

AH36

AH39

AH40

AB14

AH42

AH46

AH7

AJ19

AJ21

AJ24

AJ33

AJ34

AK12

AK3

AB39

AK38

AK4

AK42

AK46

AK8

AL16

AL17

AL19

AL2

AL21

AB4

AL23

AL26

AL27

AL31

AL33

AL34

AL48

AM11

AM14

AM36

U1800

AY4

AY42

AY46

AY8

B11

B15

B19

B23

B27

B31

B35

B39

B7

F45

BB12

BB16

BB20

BB22

BB24

BB28

BB30

BB38

BB4

BB46

BC14

BC18

BC2

BC22

BC26

BC32

BC34

BC36

BC40

BC42

BC48

BD46

BD5

BE22

BE26

BE40

BF10

BF12

BF16

BF20

BF22

BF24

BF26

BF28

BD3

BF30

BF38

BF40

BF8

BG17

BG21

BG33

BG44

BG8

BH11

BH15

BH17

BH19

H10

BH27

BH31

BH33

BH35

BH39

BH43

BH7

D3

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D42

D8

E18

E26

G18

G20

G26

G28

G36

G48

H12

H18

H22

H24

H26

H30

H32

H34

F3

H46

K18

K26

K39

K46

K7

L18

L2

L20

L26

L28

L36

L48

M12

P16

M18

M22

M24

M30

M32

M34

M38

M4

M42

M46

M8

N18

P30

N47

P11

P18

T33

P40

P43

P47

P7

R2

R48

T12

T31

T37

T4

W34

T46

T47

T8

V11

V17

V26

V27

V29

V31

V36

V39

V43

V7

W17

W19

W2

W27

W48

Y12

Y38

Y4

Y42

Y46

Y8

BG29

N24

AJ3

AD47

B43

BE10

BG41

G14

H16

T36

BG22

BG24

C22

AP13

M14

AP3

AP1

BE16

BC16

BG28

BJ28

051-9589

4.18.0

23 OF 132

22 OF 99

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

69 mA

PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)

PCH VCCADPLLB Filter

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

(PCH PCI 3.3V PWR)

PCH VCC3_3 BYPASS

(PCH USB 1.05V PWR)

PCH VCCIO BYPASS

(PCH 1.05V CORE PWR)

PCH VCCCORE BYPASS

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1 mA

<1 mA

68 mA

(PCH DPLLA PWR)

PCH V5REF_SUS Filter & Follower

<1 mA S0-S5

1 mA S0-S5

(PCH DPLLB PWR)

PCH VCCSUSHDA BYPASS

PCH VCCIO BYPASS

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

(PCH Reference for 5V Tolerance on USB)

PCH VCCADPLLA Filter

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

10%

X5R

402

10V

1UF

PLACE_NEAR=U1800.P34:2.54mm

402

100

5%

1/16W

MF-LF

0.1UF

402

20%

10V

PLACE_NEAR=U1800.M26:2.54mm

CERM

SOT-363

BAT54DW-X-G

402

MF-LF

1/16W

5%

10

SOT-363

BAT54DW-X-G

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.AJ2:2.54mm

0.1UF

402

20%

10V

PLACE_NEAR=U1800.AJ16:2.54mm

CERM

0.1UF

402

20%

PLACE_NEAR=U1800.P32:2.54mm

10V

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AT20:2.54mm

CERM

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.BH29:2.54mm

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.V24:2.54mm

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.BJ8:2.54mm

X5R

402

PLACE_NEAR=U1800.BJ8:2.54mm

20%

6.3V

4.7UF

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.P24:2.54mm

10%

0.1UF

X5R

402

25V

PLACE_NEAR=U1800.AA16:2.54mm

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AN27:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AG33:2.54mm

CERM

10%

402

6.3V

PLACE_NEAR=U1800.AF34:2.54mm

1UF

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AF17:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AN27:2.54mm

CERM

X5R

20%

603

6.3V

PLACE_NEAR=U1800.AN27:2.54mm

10UF

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AC17:2.54mm

CERM

0.1UF

402

20%

PLACE_NEAR=U1800.T16:2.54mm

10V

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.V1:2.54mm

CERM

10%

0.1UF

X5R

402

25V

PLACE_NEAR=U1800.T34:2.54mm

10%

402

6.3V

PLACE_NEAR=U1800.AH13:2.54mm

1UF

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.P28:2.54mm

CERM

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.V33:2.54mm

X5R

20%

603

6.3V

10UF

PLACE_NEAR=U1800.AG26:2.54mm

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AG24:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AD21:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AJ27:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AN27:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AN27:2.54mm

CERM

20%

22UF

603

X5R-CERM-1

6.3V

PLACE_NEAR=U1800.AC27:2.54mm

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AC27:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AC27:2.54mm

CERM

10%

402

6.3V

1UF

PLACE_NEAR=U1800.AC27:2.54mm

CERM

X5R

20%

603

6.3V

10UF

PLACE_NEAR=U1800.AB36:2.54mm

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.BJ8:2.54mm

20%

22UF

603

X5R-CERM-1

6.3V

PLACE_NEAR=U1800.AC27:2.54mm

10%

16V

NOSTUFF

PLACE_NEAR=U1800.AM37:2.54mm

X7R-CERM

0402

0.01UF

20%

603

PLACE_NEAR=U1800.AM37:2.54mm

X5R-CERM-1

6.3V

22UF

NO STUFF

10%

16V

NO STUFF

PLACE_NEAR=U1800.AM37:2.54mm

X7R-CERM

0402

0.01UF

NO STUFF

0.1UH

0805

1/20W

0

5%

201

MF

10%

16V

PLACE_NEAR=U1800.U48:2.54mm

X7R-CERM

0402

0.01UF

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U1800.U48:2.54mm

X5R

PLACE_NEAR=U1800.U48:2.54mm

20%

603

6.3V

10UF

402

1

1/16W

MF-LF

5%

X5R

20%

603

6.3V

10UF

PLACE_NEAR=U1800.T38:2.54mm

10%

X5R

402

10V

1UF

PLACE_NEAR=U1800.T38:2.54mm

0603

10UH-0.12A-0.36OHM

CRITICAL

10%

402

6.3V

1UF

PLACE_NEAR=U1800.P22:2.54mm

CERM

PLACE_NEAR=U1800.BD47:2.54MM

20%

CRITICAL

B16

TANT

2.5V

220UF

10%

402

6.3V

1UF

PLACE_NEAR=U1800.BD47:2.54MM

NO STUFF

CERM

10%

402

1UF

NO STUFF

6.3V

PLACE_NEAR=U1800.BF47:2.54MM

CERM

20%

B16

2.5V

220UF

CRITICAL

TANT

PLACE_NEAR=U1800.BF47:2.54MM

10UH-0.12A-0.36OHM

0603

CRITICAL

10UH-0.12A-0.36OHM

0603

CRITICAL

402

0

1/16W

MF-LF

5%

402

5%

MF-LF

1/16W

0

10UH-0.58A-0.35OHM

CRITICAL

1098AS-SM

1/20W

PLACE_NEAR=U1800.AM37:2.54MM

0

5%

201

MF

402

MF-LF

1/16W

5%

0

SYNC_DATE=03/19/2012

PCH DECOUPLING

SYNC_MASTER=D2_CLEAN

=PP3V3_SUS_PCH_VCCSUS

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_V_PROC_IO

=PP5V_SUS_PCH_V5REFSUS

=PP5V_SUS_PCH =PP3V3_S0_PCH

=PP5V_S0_PCH

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH

=PP1V05_S0_PCH_VCCIO

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_VCCSUS_USB

=PP5V_S0_PCH_V5REF

=PP1V8_S0_PCH_VCCTX_LVDS

=PP1V05_S0_PCH_VCCASW

=PP3V3_S0_PCH_VCCADAC

PP1V05_S0_PCH_VCCADPLLA_F

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCADPLLB_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.075 MM

VOLTAGE=3.3V

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLA_R

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

MIN_NECK_WIDTH=0.25 MM

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=5V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.075 MM

VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

PP3V3_S0_PCH_VCCA_DAC_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PP1V05_S0_PCH_VCCCLKDMI_R

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0_PCH_VCCTX_LVDS_F

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB_R

VOLTAGE=1.05V

C2439

1

2

R2405

2

1

C2438

1

2

D2400

1

6

R2404

2

1

D2400

4

3

C2423

1

2

C2440

1

2

C2441

1

2

C2419

1

2

C2421

1

2

C2413

1

2

C2417

1

2

C2416

1

2

C2484

1

2

C2485

1

2

C2463

1

2

C2475

1

2

C2434

1

2

C2469

1

2

C2414

1

2

C2401

1

2

C2452

1

2

C2499

1

2

C2442

1

2

C2486

1

2

C2444

1

2

C2446

1

2

C2424

1

2

C2460

1

2

C2482

1

2

C2481

1

2

C2483

1

2

C2407

1

2

C2429

1

2

C2420

1

2

C2496

1

2

C2456

1

2

C2426

1

2

C2411

1

2

C2430

1

2

C2428

1

2

C2406

1

2

C2400

1

2

C2408

1

2

L2407

1 2

R2450

1 2

C2455

1

2

C2451

1

2

C2450

1

2

R2451

1 2

C2453

1

2

C2454

1

2

L2451

1 2

C2476

1

2

C2491

1

2

C2492

1

2

C2494

1

2

C2493

1

2

L2490

1 2

L2491

1 2

R2490

1 2

R2491

1 2

L2406

1 2

R2401

1

2

R2415

1 2

051-9589

4.18.0

24 OF 132

23 OF 99

52

8

21

8

21

8

21

8

17

8

25

8

17

8

21

8

21

8

21

8

21

8

21

8

17 21

8

21

8

17 21

8

21

8

21 25

8

20 21

8

21

8

21

8

21

8

21

8

21

8

21

8

21

8

21

IN

OUT

IN

OUT

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

IN

OUT

OUTOUT

IN

OUT

BI

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

DBR#/HOOK7

VCC_OBS_CD

OBSDATA_D3

OBSDATA_D2

PWRGD/HOOK0

OBSFN_A1

OBSDATA_A0

OBSDATA_A2

OBSDATA_A3

OBSFN_A0

SDA

needs to split between route from PCH to J2550

and path to non-XDP signal destination.

(R2564-R2567)

- ’Output’ non-XDP signals require pulls.

OBSDATA_B2

OBSDATA_D1

OBSDATA_D0

ITPCLK/HOOK4

PCH SIGNALS

RESET#/HOOK6

OBSFN_B0

VCC_OBS_AB

HOOK2

OBSDATA_B2

OBSFN_B1

998-2516

VCC_OBS_CD

OBSDATA_B3

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

OBSDATA_B0

doc id 404081.

- For isolated GPIOs:

VCC_OBS_AB

HOOK2

HOOK3

SCL

TCK1

OBSFN_C0

OBSDATA_C0

OBSDATA_B1

OBSFN_C1

OBSFN_B1

OBSDATA_B0

support chipset debug.

TRSTn

TDI

TDO

OBSFN_B0

OBSDATA_A1

OBSFN_D0

OBSFN_D1

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

998-2516

OBSDATA_C2

OBSFN_D0

ITPCLK/HOOK4

HOOK3

TCK0

SDA

HOOK1

TDI

TMS

TDO

TRSTn

DBR#/HOOK7

ITPCLK#/HOOK5

OBSFN_D1

OBSFN_C1

OBSDATA_C3

OBSDATA_C0

OBSDATA_D0

OBSDATA_D1

1K series R on PCH Support Page

XDP_PRESENT#

TMS

TCK0

OBSDATA_D3

TCK1

SCL

PWRGD/HOOK0

OBSDATA_B3

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

CPU Micro2-XDP

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_C1

OBSFN_C0

OBSDATA_A0

OBSFN_A0

XDP SIGNALS

PCH/XDP Signal Isolation Notes:

it is functional in that state, else add BOM options.

(R2520-R2537)

(R2560-R2563)

RESET#/HOOK6

NOTE: This is not the standard XDP pinout.

Non-XDP Signals

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path

Initially, stuffing both 33 and 0 ohms and validate whether

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

Use with 921-0133 Adapter Flex to

support chipset debug.

OBSDATA_A3

OBSDATA_A2

PCH Micro2-XDP

PCH SIGNALS

XDP_PRESENT#

ITPCLK#/HOOK5

HOOK1

10 89

11 25

11 89

10 24 89

10 89

25

17 24

10 89

17 24

10 89

24 44

11 24 25 89

10%

0.1UF

16V

0402

X7R-CERM

XDP

10%

0.1UF

16V

0402

X7R-CERM

XDP

18 24 41

18 41 70

11 24 89

11 24 25 89

10 89

11 24 89

17 89

11 24 89

402

1/16W

5%

MF-LF

1K

NO STUFF

1/20W

5%

201

MF

0

XDP

PLACE_NEAR=R1841.1:2.54mm

1/20W

5%

201

MF

0

XDP

PLACE_NEAR=R1840.1:2.54mm

5%

PLACE_NEAR=U1000.G3:2.54mm

1/20W

201

MF

1K

XDP

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=J2550.52:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1800.K5:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1800.H7:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1800.J3:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=J2500.52:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1000.K61:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1000.H59:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1000.J58:2.54mm

1/20W

5%

201

MF

51

XDP

PLACE_NEAR=U1000.H63:2.54mm

1/20W

5%

201

MF

330

XDP

1/20W

5%

201

MF

1K

XDP

PLACE_NEAR=U1000.B57:2.54mm

1/20W

5%

201

MF

0

XDP

PLACE_NEAR=U4900.P17:2.54mm

1/20W

5%

201

MF

1K

XDP

PLACE_NEAR=U1000.C60:2.54mm

1/20W

5%

201

MF

0

XDP_CPU:BPM

11 89

1/20W

5%

201

MF

0

XDP_CPU:BPM

1/20W

5%

201

MF

0

XDP_CPU:BPM

1/20W

5%

201

MF

0

XDP_CPU:BPM

1/20W

5%

201

MF

0

XDP_CPU:CFG

1/20W

5%

201

MF

0

XDP_CPU:CFG

1/20W

5%

201

MF

0

XDP_CPU:CFG

1/20W

5%

201

MF

0

XDP_CPU:CFG

10 89

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

201

1/20W

5% MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

1/20W

5%

201

MF

33

XDP

20 24

20

10 24 89

17 24

20

20 24

19 24

19

19 24

1/20W

5%

201

MF

1K

XDP

PLACE_NEAR=J2550.39:2.54mm

1/20W

5%

201

MF

0

XDP

PLACE_NEAR=U4900.P17:2.54mm

41 70

18 24 41

24

M-ST-SM

DF40RC-60DP-0.4V

CRITICAL

XDP_CONN

DF40RC-60DP-0.4V

M-ST-SM

CRITICAL

1/20W

5%

201

MF

33

XDP

25

27

17 25

20 25

MF

1/20W

5%

201

0

1/20W

5% MF

0

201

0

MF5%

1/20W

201

1/20W

5%

201

MF

0

1/20W

5%

201

MF

0

9

20 25

1/20W

5%

201

MF

0

19 24

20 24

10%

0.1UF

16V

0402

X7R-CERM

XDP

20 24

201

1/20W

5% MF

33

XDP

1/20W

5%

33

XDP

201

MF

1/20W

5%

201

MF

33

XDP

1/20W

5%

XDP

MF

201

33

MF

33

XDP

201

1/20W

5%

1/20W

5%

201

MF

XDP

33

20

20 24

19

1/20W

5%

201

MF

0

MF

1/20W

5%

201

0

10 89

17 24

17

201

1/20W

5% MF

0

201

5%

0

1/20W

MF

19 24

7

38

40

19 34 70

19 24

20 20 24

201MF5%

1/20W

1K

10%

0.1UF

16V

0402

X7R-CERM

XDP

11 89

10 89

24 44

11 24 89

10 89

11 20 89

10 89

11 89

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

CPU & PCH XDP

DP_AUXCH_ISOL

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

ISOLATE_CPU_MEM_L

=PPVCCIO_S0_XDP

XDP_CPURST_L

XDP_DBRESET_L

XDP_CPU_CLK100M_N

XDP_CPU_CFG<0>

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

USB_EXTA_OC_L

USB_EXTB_OC_L

AP_PWR_EN

=PP3V3_S5_XDP

TP_XDP_PCH_OBSFN_A<0>

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DB2_PCH_GPIO10_AP_PWR_EN

CPU_CFG<7>

SATARDRVR_EN

XDP_CPU_TDO

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DB2_AP_PWR_EN

XDP_FC0

XDP_FC1

XDP_FC1_PCH_GPIO0

CPU_CFG<4>

XDP_FC0

XDP_FC1

XDP_DC1_MXM_GOOD

XDP_DC2_DP_AUXCH_ISOL

XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0>

TP_XDP_PCH_OBSFN_D<1>

XDP_CPU_TCK

XDP_DA1_USB_EXTB_OC_L

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DA2_USB_EXTC_OC_L

XDP_DA1_USB_EXTB_OC_L

XDP_DA0_USB_EXTA_OC_L

TP_XDP_PCH_OBSFN_A<1>

XDP_DA0_USB_EXTA_OC_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DD1_JTAG_ISP_TCK

XDPPCH_PLTRST_L

XDP_DBRESET_L

XDP_PCH_TDO

TP_XDP_PCH_TRST_L

XDP_PCH_TMS

XDP_CPU_PWRBTN_L

=SMBUS_XDP_SDA

=SMBUS_XDP_SCL

=PP3V3_S0_XDP

CPU_CFG<0>

TP_XDP_PCH_HOOK5

PM_PWRBTN_L

XDP_DC0_ISOLATE_CPU_MEM_L

CPU_CFG<6>

XDP_PCH_TCK

XDP_PCH_TDI

XDP_PCH_TMS

XDP_PCH_TDO

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPU_TDO

PM_PWRBTN_L

=PPVCCIO_S0_XDP

XDP_DB2_AP_PWR_EN

XDP_PCH_TCK

=SMBUS_XDP_SCL

TP_XDPPCH_HOOK2

TP_XDPPCH_HOOK3

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_PCH_TDI

TP_XDP_PCH_HOOK4

XDP_DD2_AUD_IPHS_SWITCH_EN

CPU_CFG<16>

CPU_CFG<17>

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

CPU_RESET_L

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

XDP_BPM_L<3>

CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<14>

CPU_CFG<2>

CPU_CFG<0>

CPU_CFG<8>

CPU_CFG<3>

CPU_CFG<1>

=PP1V05_SUS_PCH_JTAG

XDP_BPM_L<4>

XDP_BPM_L<6>

XDP_BPM_L<7>

CPU_CFG<13>

XDP_BPM_L<1>

XDP_BPM_L<2>

PM_PCH_SYS_PWROK

XDP_DD3_ENET_LOW_PWR

=SMBUS_XDP_SDA

XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN

XDP_DD3_ENET_LOW_PWR

ENET_LOW_PWR_PCH

TP_XDP_PCH_OBSFN_B<0>

XDP_DA2_USB_EXTC_OC_L

TP_XDP_PCH_OBSFN_B<1>

XDP_DA3_USB_EXTD_OC_L

XDP_PCH_PWRBTN_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

CPU_CFG<9>

CPU_PWRGD

CPU_CFG<15>

XDP_OBSDATA_B<3>

XDP_CPU_PWRGD

XDP_OBSDATA_B<0>

CPU_CFG<12>

XDP_OBSDATA_B<1>

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DA3_USB_EXTD_OC_L

XDP_DC3_SATARDRVR_EN

XDP_DD0_DP_GPU_TBT_SEL

ALL_SYS_PWRGD

XDP_BPM_L<5>

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_FC0_PCH_GPIO15

XDP_BPM_L<0>

SDCONN_STATE_CHANGE

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DC2_DP_AUXCH_ISOL

XDP_DC1_MXM_GOOD

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DB3_SDCONN_STATE_CHANGE

XDP_PCH_S5_PWRGD

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DD0_DP_GPU_TBT_SEL

XDP_VR_READY

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_OBSDATA_B<2>

CPU_CFG<5>

XDP_CPU_CLK100M_P

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TCK

TBT_CIO_PLUG_EVENT_ISOL

XDP_FC1_PCH_GPIO0

C2501

1

2

C2500

1

2

C2580

1

2

C2581

1

2

R2540

1

2

R2515

1 2

R2516

1 2

R2505

1 2

R2550

2 1

R2551

2 1

R2552

2 1

R2556

2 1

R2510

2 1

R2511

2 1

R2512

2 1

R2513

2 1

R2514

2 1

R2504

1 2

R2501

1 2

R2502

1 2

R2500

1 2

R2560

1 2

R2561

1 2

R2562

1 2

R2563

1 2

R2566

1 2

R2565

1 2

R2564

1 2

R2567

1 2

R2524

1 2

R2525

1 2

R2526

1 2

R2527

1 2

R2530

1 2

R2532

1 2

R2533

1 2

R2534

1 2

R2535

1 2

R2536

1 2

R2537

1 2

R2584

1 2

R2585

1 2

J2500

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

J2550

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

R2521

1 2

R2597

1 2

R2596

1 2

R2572

1 2

R2570

1 2

R2576

1 2

R2577

1 2

R2528

1 2

R2529

1 2

R2520

1 2

R2522

1 2

R2523

1 2

R2531

1 2

R2575

1 2

R2573

1 2

R2591

1 2

R2590

1 2

R2574

1 2

051-9589

4.18.0

25 OF 132

24 OF 99

8

24

89

8

24

8

24

17 24

11 24 89

8

24

8

24

89

24

89

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

NC

08

Y1

Y2

GND

B2

VCC

A1

B1

A2

OUT

IN

D

SG

D

S G

OUT

08

Y1

Y2

GND

B2

VCC

A1

B1

A2

IN

OUT

Y

B

A

D

G S

IN

OUT

D

S G

D

S G

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ethernet XTAL Power (Unused on 15" MBP)

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

VDDIO_25M_B: Ethernet power rail for XTAL circuit.

GreenClk 25MHz Power

SB XTAL Power

TBT XTAL Power

LPC 33MHz Clock Series Termination

NOTE: 30 PPM crystal required

Coin-Cell & No G3Hot: 3.3V S5

No Coin-Cell: 3.42V G3Hot (no RC)

System RTC Power Source & 32kHz / 25MHz Clock Generator

VTT pullup on CPU page

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

GPIO Glitch Prevention

DP_AUXIO_EN INVERSION

PCH Reset Button

SDCONN_STATE_CHANGE ISOLATION

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.3V S5

VDDIO_25M_A: SB power rail for XTAL circuit.

No bypass necessary

internally ORed to

SMC controls strap enable to allow in-field control of strap setting.

Platform Reset Connections

Series R on Pg38, R3803

Buffered

IPD = 9-50k

Unbuffered

Coin-Cell: VBAT (300-ohm & 10uF RC)

Buffered CPU reset

create VDD_RTC_OUT.

VBAT and +V3.3A are

For SB RTC Power

+V3.3A should be first

available ~3.3V power

to reduce VBAT draw.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

11 24 89

5%

402

MF-LF

0

XDP

1/16W

5%

402

MF-LF

1/16W

33

5%

402

33

1/16W

MF-LF

7

43

41

34

19 27

5%

201

MF

1/20W

22

PLACE_NEAR=U1800.P53

PLACE_NEAR=U1800.N52

MF

201

1/20W

22

5%

19 92

33

5%

402

MF-LF

0

1/16W

7

43 92

41 92

19

82

5%

PLACE_NEAR=U1800.P46

1/20W

MF

201

22

24

5%

402

MF-LF

1K

XDP

1/16W

402

CERM

0.1UF

20%

10V

SC70-HF

MC74VHC1G08

CRITICAL

5%

402

100K

1/16W

MF-LF

17 92

5%

PLACE_NEAR=U1800.P48

201

MF

1/20W

22

19

82

5%

402

MF-LF

1/16W

0

5%

402

MF-LF

1/16W

0

OMIT

SILK_PART=SYS RESET

92

86

5%

402

1/16W

MF-LF

4.7K

18 41

17 91

35 91

402

CERM

10%

6.3V

1UF

X5R

10%

10V

402-1

1UF

402

CERM

0.1UF

20%

10V

NO STUFF

402

CERM

20%

10V

0.1UF

5%

402

NO STUFF

1/16W

MF-LF

1M

402

CERM

0.1UF

10V

20%

5%

402

0

1/16W

MF-LF

5%

12PF

0402

C0G-CERM

50V

5%

12PF

0402

C0G-CERM

50V

11 24

5%

402

MF-LF

1/16W

100K

SC70

CRITICAL

74LVC1G07

402

CERM

10V

20%

0.1UF

5%

402

0

1/16W

MF-LF

5%

402

0

MF-LF

1/16W

37

SLG3NB148A

TQFN

CRITICAL

CKPLUS_WAIVE=PwrTerm2Gnd

CRITICAL

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM

5%

402

0

1/16W

MF-LF

NO STUFF

5%

402

0

1/16W

MF-LF

74LVC2G08GT

CRITICAL

SOT833

402

CERM

20%

10V

0.1UF

9

9 9

20 24

18 25 70

20

5%

402

MF-LF

1/16W

0

41 42

5%

1K

201

1/20W

MF

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

SOT563

5%

MF

1/20W

201

100K

17 92

38

58

20 35

402

CERM

0.1UF

10V

20%

74LVC2G08GT

CRITICAL

SOT833

17

18 25 70

20 24 39

5%

402

1/16W

MF-LF

0

SOT665

TC7SZ08AFEAPE

CRITICAL

201

X5R

10%

6.3V

0.1UF

SOD-VESM-HF

SSM3K15FV

16V

0.1UF

X5R-CERM

0201

10%

5%

MF

10K

201

1/20W

5%

NO STUFF

1/20W

201

10K

MF

17 24

84 85

SOT563

SSM6N15FEAPE

SOT563

7

38

42

24

5%

201

470K

1/20W

MF

5%

MF

1/20W

470K

201

7

18 41 43

SYNC_MASTER=D2_KEPLER

Chipset Support

SYNC_DATE=01/13/2012

=PP3V3_S0_RSTBUF

=PP3V3_S3_SDBUF

=PP3V3_S0_PCH_GPIO

=PPVDDIO_TBT_CLK

SYSCLK_CLK25M_TBT

=PPVRTC_G3_OUT

SSD_RESET_L

BKLT_PLT_RST_L

SYSCLK_CLK25M_SB

=PP5V_S0_PCH

SYSCLK_CLK25M_X2

TP_SYSCLK_CLK25M_ENET

=PP3V3_S0_SB_PM

DPMUX_LRESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

SMC_LRESET_L

=PP3V3R1V5_S0_PCH_VCCSUSHDA

SPI_DESCRIPTOR_OVERRIDE_LS5V

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S0_RSTBUF

AP_RESET_L

=TBT_RESET_L

LPC_RESET_L

=ENET_RESET_L

SYSCLK_CLK25M_X2_R

=PP3V3_S0_SYSCLK

CPU_RESET_L

=PPVDDIO_S0_SBCLK

PM_SYSRST_L

DP_AUXIO_EN

DP_AUXCH_ISOL

=PP3V3_S4_SMC

PM_PCH_PWROK

=PP3V3_S3_PCH_GPIO

ENET_LOW_PWR_PCH

FW_PWR_EN_PCH

ENET_LOW_PWR

FW_PWR_EN

=PP3V3_S3_PCH_GPIO

TBT_PWR_EN

AUD_IPHS_SWITCH_EN_PCH

PCH_CLK33M_PCIIN

TP_PCI_CLK33M_OUT2

PCH_CLK33M_PCIOUT

=PP3V3_S4_SMC

SDCONN_STATE_CHANGE_INV

SDCONN_STATE_CHANGE_RIO

AUD_IPHS_SWITCH_EN

SDCONN_STATE_CHANGE

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

LPC_CLK33M_DPMUX_UC

LPC_CLK33M_LPCPLUS_R

TBT_PWR_EN_PCH

PM_PCH_PWROK

LPC_PWRDWN_L

SYSCLK_CLK32K_RTC

XDP_DBRESET_L

LPC_CLK33M_DPMUX_UC_R

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

SYSCLK_25M_B_GND

MAKE_BASE=TRUE

PLT_RST_BUF_L

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RESET_L

MAKE_BASE=TRUE

ENET_RESET_L

MAKE_BASE=TRUE

PLT_RST_CPU_BUF_L

LPC_CLK33M_SMC_R

SDCONN_STATE_CHANGE_SMC

=PPVBAT_G3_SYSCLK

=PP3V3_S5_SYSCLK

SYSCLK_CLK25M_X1

R2696

1 2

R2683

1 2

R2681

1 2

R2656

1 2

R2655

1 2

R2671

1 2

R2657

1 2

R2689

1 2

C2680

1

2

U2680

3

2

1

4

5

R2680

1

2

R2659

1 2

R2687

1 2

R2697

1

2

R2695

1

2

C2610

1

2

C2602

1

2

C2620

1

2

C2622

1

2

R2606

1

2

C2624

1

2

R2605

1 2

C2605

12

C2606

1 2

R2690

1

2

U2690

2

3

5

4

C2690

1

2

R2688

1 2

R2693

1 2

U2600

9

8

15

12

7

10

16

13

2

17

5

1

11

6

14

4

3

Y2605

24

13

R2607

1 2

R2608

1

2

U2650

1

5

2

6

4

8

7

3

C2650

1

2

R2686

1 2

R2621

1

2

Q2620

6

21

Q2620

3

5

4

R2620

1

2

C2652

1

2

U2652

1

5

2

6

4

8

7

3

R2685

1 2

U2630

2

1

3

5

4

C2630

1

2

Q2630

3

12

C2639

1

2

R2630

1 2

R2631

1

2

Q2640

6

2

1

Q2640

3

5

4

R2641

1

2

R2640

1

2

051-9589

4.18.0

26 OF 132

25 OF 99

1

8

25

8

17 18 19 20 37

8

23

8

70

8

21 23

8

25

8

25 42

8

19 25

8

19 25

8

25 42

7

8

BI

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN

XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1*

OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1*

PRTPWR2/BC_EN2*

SYM VER 1

BI

IN

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

BI

NC

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH PORT 7 (EHCI1)

IPU

PCH PORT 1 (XHCI)

IPU

TO TP/KB

TO CONNECTOR

USB XHCI/EHCI2 PORT MUX FOR EXT B

SEL=0 CHOOSE USB EHCI2 PORT

SEL=1 CHOOSE USB XHCI PORT

PCH GPIO60

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

BOM TABLE

PCH PORT 9 (EHCI2)

TO CONNECT TP/KB TO PCH XHCI

TO PCH XHCI

NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB MUX FOR LS/FS INTERNAL DEVICES

1 : 1 PORT 1&2&3 ARE NON REMOVABLE

1 : 0 PORT 1&2 ARE NON REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLE

0 : 0 ALL PORTS ARE REMOVABLE

NON_REM 1 : NON_REM 0 STRAP PIN CFG

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

SMC DEBUG PORT FOR 15" MBP, IR for MBP OG

TRACKPAD/KEYBOARD FOR 15" MBP & MBP OG

BLUETOOTH FOR 15" MBP & MBP OG

NC FOR 15" MBP, SMC DEBUG PORT FOR MBP OG

15" MBP ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B

MBP OG ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

15" MBP USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION

MBP OG USES 197S0284 FOR Y2700 TO SAVE COST

5%

402

1/16W

MF-LF

10K

5%

402

CRITICAL

1/16W

MF-LF

1M

402

1UF

X5R

16V

10%

0402

16V

X7R-CERM

0.1UF

10%

402

X5R

1UF

16V

10%

16V

X7R-CERM

0402

0.1UF

10%

BYPASS=U2700.15::2MM

16V

X7R-CERM

0402

0.1UF

10%

5%

402

10K

MF-LF

1/16W

402

1/16W

1%

12K

MF

CRITICAL

19 91

BYPASS=U2700.10::2MM

16V

X7R-CERM

0402

0.1UF

10%

BYPASS=U2650.23::2MM

16V

X7R-CERM

0402

0.1UF

10%

BYPASS=U2700.5::2MM

16V

X7R-CERM

0402

0.1UF

10%

5%

402

100

MF-LF

1/16W

5%

18PF

0402

C0G-CERM

50V

CRITICAL

5%

18PF

0402

C0G-CERM

50V

CRITICAL

5%

402

10K

MF-LF

1/16W

5%

402

1/16W

MF-LF

10K

5%

402

MF-LF

1/16W

HUB_NONREM0_1

10K

5%

402

MF-LF

1/16W

10K

HUB_NONREM1_1

5%

402

MF-LF

1/16W

10K

HUB_NONREM0_0

5%

402

10K

1/16W

MF-LF

HUB_NONREM1_0

9

CRITICAL

24.000MHZ-16PF

SM-2

OMIT

QFN

USB2513B

CKPLUS_WAIVE=NdifPr_badTerm

BYPASS=U2700.29::2MM

16V

X7R-CERM

0402

0.1UF

10%

BYPASS=U2700.36::2MM

16V

X7R-CERM

0402

0.1UF

10%

603

X5R

20%

6.3V

4.7UF

BYPASS=U27000.5::5MM

BYPASS=U2700.23::5MM

603

20%

X5R

6.3V

4.7UF

9

26

9

26

BYPASS=U2700.26::2MM

16V

X7R-CERM

0402

0.1UF

10%

9

26

9

26

5%

402

NOSTUFF

1/16W

10K

MF-LF

5%

402

MF-LF

10K

1/16W

NOSTUFF

5%

402

1/16W

10K

MF-LF

NOSTUFF

5%

402

1/16W

10K

MF-LF

NOSTUFF

7

38 91

7

38 91

17

402

CERM

10V

20%

0.1UF

PI3USB102ZLE

CRITICAL

TQFN

19 91

19

91

19

91

19 91

49 96

5%

402

NOSTUFF

27

1/16W

MF-LF

5%

402

1/16W

MF-LF

27

NOSTUFF

19 91

5%

402

NOSTUFF

1/16W

MF-LF

10K

5%

402

NOSTUFF

10K

MF-LF

1/16W

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

USB HUB & MUX

HUB_ALLREM

HUB_NONREM1_0,HUB_NONREM0_0

HUB_NONREM1_0,HUB_NONREM0_1

HUB_1NONREM

HUB_NONREM1_1,HUB_NONREM0_0

HUB_2NONREM

HUB_NONREM1_1,HUB_NONREM0_1

HUB_3NONREM

USB HUB 2513B

338S0923

1

U2700

CRITICAL

USBHUB2513B

USB HUB 2512B

338S0983

CRITICAL

1

U2700

USBHUB2512B

1

U2700

CRITICAL

338S0824

USB HUB 2514B

USBHUB2514B

NC_USB_HUB_PRTPWR3

NC_USB_HUB_PRTPWR2

TP_USB_HUB_PRTPWR1

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8

=PP3V3_S3_USB_HUB

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

USB_HUB_XTAL2

USBHUB_DN4_N

USBHUB_DN2_N

USBHUB_DN2_P

USB_EXTD_XHCI_P

USB_TPAD_R_P

=PP3V3_S3_USB_HUB

USBHUB_DN4_P

USBHUB_DN3_P

USBHUB_DN3_N

USB_EXTB_SEL_XHCI

USB_EXTB_XHCI_N

=PP3V3_S3_USB_HUB

=PP3V3_S3_USBMUX

USB_EXTB_P

USB_HUB_RESET_L

=PP3V3_S3_USB_RESET

USB_EXTB_XHCI_P

USB_EXTB_EHCI_N

USB_EXTB_EHCI_P

USB_EXTB_N

USB_EXTD_XHCI_N

USB_TPAD_R_N

USBHUB_DN1_N

USBHUB_DN1_P

USBHUB_DN2_N

USBHUB_DN2_P

USBHUB_DN3_N

USBHUB_DN3_P

USBHUB_DN4_P

NC_USB_HUB_OCS4

USB_HUB_VBUS_DET

USB_HUB_RBIAS

USB_HUB_UP_N

NC_USB_HUB_PRTPWR4

USB_HUB_UP_P

USB_HUB_RESET_L

USB_HUB_TEST

USB_HUB_XTAL1

USB_HUB_CFG_SEL1

USB_HUB_CFG_SEL0

USB_HUB_NONREM1

USB_HUB_NONREM0

USBHUB_DN4_N

NC_USB_HUB_OCS3

NC_USB_HUB_OCS2

TP_USB_HUB_OCS1

R2712

1

2

R2700

1 2

C2714

1

2

C2713

1

2

C2712

1

2

C2711

1

2

C2708

1

2

R2708

1

2

R2709

1

2

C2701

1

2

C2706

1

2

C2705

1

2

R2701

1 2

C2710

1

2

C2709

1

2

R2707

1

2

R2706

1

2

R2703

1

2

R2702

1

2

R2705

1

2

R2704

1

2

Y2700

2 4

1 3

U2700

14

25

8

9

20

21

13

17

19

34

12

16

18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

5

10

15

23

29

36

33

32

C2702

1

2

C2703

1

2

C2700

1

2

C2704

1

2

C2715

1

2

R2716

1

2

R2717

1

2

R2718

1

2

R2719

1

2

C2760

1

2

U2760

6

7

3

4

5

810

9

2

1

R2720

1 2

R2721

1 2

R2722

1

2

R2723

1

2

051-9589

4.18.0

27 OF 132

26 OF 99

7

8

26

9

26

9

26

9

26

8

26

9

26

9

26

9

26

8

26

8

26

8

9

26

9

26

7

26

7

IN IN

IN

OUT

D

SG

D

S G

D

SG

D

S G

D

SG

D

S G

D

S G

D

SG

OUT

IN

D

SG

D

SG

IN

G

D

S

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

Ensures CKE signals are held low in S3

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

MEMVTT Clamp

60mW max power

S0

to

S3

to

S0

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

2 0 0 1 1 1 1 0 1

3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1

5 0 1 1 1 0 (*) 1 1 1

6 0 1 1 1 1 1 1 1

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

75mA max load @ 0.75V

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

1V5 S0 "PGOOD" for CPU

24

7

18 38 41 70

19 25

1/16W

5%

MF-LF

CPUMEM_S0

100K

402

9

10K

1/16W

5%

MF-LF

CPUMEM_S0

402

100K

5%

1/16W

MF-LF

CPUMEM_S0

402

28 29 30 31

SOT563

SSM6N15FEAPE

CRITICAL

CPUMEM_S0

CRITICAL

SOT563

SSM6N15FEAPE

CPUMEM_S0

SOT563

CPUMEM_S0

CRITICAL

SSM6N15FEAPE

SOT563

SSM6N15FEAPE

CPUMEM_S0

CRITICAL

SOT563

SSM6N15FEAPE

CPUMEM_S0

CRITICAL

CPUMEM_S0

SOT563

SSM6N15FEAPE

CRITICAL

CPUMEM_S0

SSM6N15FEAPE

SOT563

CRITICAL

SSM6N15FEAPE

CPUMEM_S0

SOT563

CRITICAL

69

10K

1/16W

5%

MF-LF

CPUMEM_S0

402

7

18 34 38 40 41 70

100K

5%

MF-LF

CPUMEM_S0

1/16W

402

9

64

SOT563

CPUMEM_S0

SSM6N15FEAPE

CRITICAL

CPUMEM_S0

100K

5%

1/16W

MF-LF

402

NO STUFF

50V

0.001UF

20%

CERM

402

SOT563

CRITICAL

CPUMEM_S0

SSM6N15FEAPE

CPUMEM_S0

10

5%

MF-LF

603

1/10W

MF-LF

1/16W

5%

0

CPUMEM_S3

402

11

OMIT_TABLE

MF-LF

1%

1/16W

402

33.2K

27.4K

1%

1/16W

MF-LF

402

DMB53D0UV

SOT-563

CRITICAL

5%

10K

MF-LF

1/16W

402

CRITICAL

DMB53D0UV

SOT-563

11 18 89

CPUMEM_S0

X7R-CERM

0402

16V

0.1UF

10%

NOSTUFF

201

0.047UF

6.3V

X5R

10%

MF-LF

1/16W

5%

1K

402

CPUMEM_S0

402

4700PF

10%

100V

CERM

CPU Memory S3 Support

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

114S0365

RES,MTL FILM,1/16W,33.2K,1,0402,SMD,LF

1

PPDDR:1V5

R2821

114S0376

RES,MTL FILM,1/16W,43.2K,1,0402,SMD,LF

R2821

1

PPDDR:1V35

PM_MEM_PWRGD

=PP3V3_S5_CPU_VCCDDR

PM_SLP_S4_L

MEMVTT_EN_L

=PP5V_S3_MEMRESET

=PPVTT_S0_VTTCLAMP

P1V5CPU_EN

PM_SLP_S3_L

MEMVTT_EN

P1V5CPU_EN_L

=PP3V3_S3_MEMRESET

PLT_RESET_L

=DDRVTT_EN

VTTCLAMP_EN

VTTCLAMP_L

=MEM_RESET_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

MEMRESET_ISOL_LS5V_L

ISOLATE_CPU_MEM_L

=PP5V_S3_MEMRESET

PM_MEM_PWRGD_L

=PP1V5_S3_CPU_VCCDDR

MEM_RESET_L

=PP1V5_S3_MEMRESET

P1V5_S0_DIV

R2802

1

2

R2810

1

2

R2815

1

2

Q2800

3

54

Q2805

3

5

4

Q2810

6

21

Q2810

3

5

4

Q2800

6

21

Q2815

6

2

1

Q2815

3

5

4

Q2805

6

21

R2805

1

2

R2801

1

2

Q2850

3

54

R2851

1

2

C2851

1

2

Q2850

6

21

R2850

1

2

R2817

1 2

R2821

1

2

R2820

1

2

Q2820

5

3

4

R2822

1

2

Q2820

6

2

1

C2816

1

2

C2817

1

2

R2816

1

2

C2820

1

2

051-9589

4.18.0

28 OF 132

27 OF 99

8

27

8

33

8

27

8

11 14 16

8

NC

NC NC

NC

NC NC

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM 6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

10%

0.1UF

X5R

201

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

MF

1/20W

1%

240

201

MF

240

1%

201

1/20W

MF

1/20W

1%

240

201

1%

201

240

1/20W

MF

201

CERM-X5R-1

4V

20%

0.47UF 0.47UF

201

4V

20%

CERM-X5R-1

4V

20%

201

CERM-X5R-1

0.47UF 0.47UF

20%

4V

CERM-X5R-1

201201

4V

CERM-X5R-1

20%

0.47UF

20%

4V

201

CERM-X5R-1

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

CERM-X5R-1

20%

4V

201

0.47UF 0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

CERM-X5R-1

0.47UF

20%

4V

201

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

MF

1/20W

1%

240

201

240

201

1%

1/20W

MF

0.47UF

201

CERM-X5R-1

4V

20%

4V

201

0.47UF

CERM-X5R-1

20%20%

CERM-X5R-1

4V

201

0.47UF

CERM-X5R-1

4V

20%

0.47UF

201

MF

1/20W

1%

240

201

MF

1%

201

240

1/20W

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

201

6.3V

X5R

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

201

10%

X5R

0.1UF

20%

10V

402

2.2UF

X5R-CERM

402

10V

20%

2.2UF

X5R-CERM X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

402

10V

20%

2.2UF

20%

10V

402

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

402

10V

20%

2.2UF

X5R-CERM

402

10V

20%

X5R-CERM

2.2UF

20%

10V

402

20%

X5R-CERM

2.2UF

402

10V

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

20%

10V

402

2.2UF

X5R-CERM

402

10V

20%

2.2UF

10V

20%

402

X5R-CERM

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE OMIT_TABLE

FBGA

DDR3-1333

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE OMIT_TABLE

DDR3-1333

FBGA

DDR3 SDRAM Bank A (1 OF 2)

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

=PP1V5R1V35_S3_MEM_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<0>

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_DQ<2>

MEM_A_CS_L<0>

MEM_A_DQ<4>

MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<0>

MEM_A_A<2>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_DQS_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<0>

=PP1V5R1V35_S3_MEM_A

MEM_A_A<7>

MEM_A_A<2>

MEM_A_DQ<10>

MEM_A_DQ<15>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQS_P<1>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_N<1>

MEM_A_DQ<8>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<1>

MEM_A_RAS_L

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<7>

MEM_A_A<0>

MEM_A_DQ<9>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_DQ<14>

=PP1V5R1V35_S3_MEM_A

MEM_A_A<7>

MEM_A_A<11>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<23>

MEM_A_DQ<19>

MEM_A_DQS_P<2>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_N<2>

MEM_A_DQ<20>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<2>

MEM_A_RAS_L

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<4>

MEM_A_A<2>

=PP1V5R1V35_S3_MEM_A

MEM_A_A<3>

MEM_A_A<2>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<30>

MEM_A_DQ<25>

MEM_A_DQ<29>

MEM_A_DQS_P<3>

MEM_A_CS_L<0>

MEM_A_DQS_N<3>

MEM_A_DQ<26>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<3>

MEM_A_RAS_L

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_A<2>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<39>

MEM_A_DQS_P<4>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_N<4>

MEM_A_DQ<38>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<4>

MEM_A_RAS_L

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<37>

MEM_A_CAS_L

MEM_A_DQ<32>

MEM_A_A<2>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<47>

MEM_A_DQS_P<5>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_N<5>

MEM_A_DQ<46>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<5>

MEM_A_RAS_L

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5R1V35_S3_MEM_A

MEM_A_A<2>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<55>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_N<6>

MEM_A_DQ<54>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<6>

MEM_A_RAS_L

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_DQS_P<6>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQS_P<7>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_DQS_N<7>

MEM_A_DQ<62>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<7>

MEM_A_RAS_L

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<51>

=PP1V5R1V35_S3_MEM_A

MEM_A_DQ<50>

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

C2940

1

2

C2941

1

2

C2943

1

2

C2944

1

2

C2945

1

2

C2953

1

2

C2954

1

2

C2955

1

2

C2963

1

2

C2964

1

2

C2965

1

2

C2973

1

2

C2974

1

2

C2975

1

2

R2900

2

1

R2910

2

1

R2920

2

1

R2930

2

1

C2907

1

2

C2909

1

2

C2908

1

2

C2919

1

2

C2918

1

2

C2917

1

2

C2929

1

2

C2928

1

2

C2927

1

2

C2939

1

2

C2938

1

2

C2937

1

2

C2979

1

2

C2978

1

2

C2977

1

2

C2969

1

2

C2968

1

2

C2967

1

2

C2959

1

2

C2958

1

2

R2970

2

1

R2960

2

1

C2957

1

2

C2949

1

2

C2948

1

2

C2947

1

2

R2950

2

1

R2940

2

1

C2935

1

2

C2934

1

2

C2933

1

2

C2925

1

2

C2924

1

2

C2923

1

2

C2915

1

2

C2914

1

2

C2913

1

2

C2905

1

2

C2904

1

2

C2903

1

2

C2901

1

2

C2900

1

2

C2911

1

2

C2951

1

2

C2910

1

2

C2950

1

2

C2921

1

2

C2961

1

2

C2920

1

2

C2960

1

2

C2931

1

2

C2930

1

2

C2971

1

2

C2970

1

2

U2900

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2910

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2920

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2930

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2940

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2950

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2960

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U2970

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

051-9589

4.18.0

29 OF 132

28 OF 99

8

28 29

12 28

32 90

12 28 32 90

12 28 29 32

90

12 28 29 32

90

12 28 32 90

12 28 29 32

90

12 28 29 32 90

27 28 29

30 31

12 28 29 32

90

12 28

29

32 90

12 28 29 32

90

12 28

29

32 90

12 28 29 32

90

12 28

29

32 90

12 28 29 32

90

12 28 29 32 90

12 28

29

32 90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

12 29

90

12 28

32 90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

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29

32 90

12 28

29

32

90

12 29

90

12 28

32 90

12 29

90

8

28 29

12 28 29 32 90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 28

32 90

12 28

32 90

12 29

90

12 29

90

12 28 29 32 90

12

28 29 32 90

28 29 33 89

12 28 29 32 90

27 28 29

30 31

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28

32 90

28 29 33 89

12 28 29 32 90

12 29

90

12 28 29 32

90

12 28 32 90

12 29

90

8

28 29

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 28

32 90

12 28

32 90

12 29

90

12 29

90

12 28 29 32 90

12

28 29 32 90

12 28 29 32 90

28 29 33 89

12 28 29 32

90 27 28 29

30 31

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

12 28

32 90

28 29 33 89

12 28 29 32 90

8

28 29

12 28 29 32 90

12 29 90

12 29

90

12 28 32 90

12 29

90

12 29 90

12 28 29 32 90

12

28 29 32 90

12 28 29 32 90

8

28 29

28 29 33 89

12 28 29 32

90 27 28 29 30 31

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

28 29 33 89

12 28 32 90

12 28 29 32

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 28

32 90

12 28

32 90

12 29

90

12 29

90

12 28 29 32

90

12 28

29

32 90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

12 28 29 32

90

12 28 29 32 90

12 28

29

32 90

12 28 29 32

90

28 29 33 89

12 28 29 32

90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

27 28 29

30 31

12 28

29

32 90

12 28 29 32 90

12 28 32 90

12 28 29 32

90

12 28 29 32

90

12 28 32 90

12 28

32 90

28 29 33 89

12 29

90

12 29

90

12 28 29 32 90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 28

32 90

12 28

32 90

12 29

90

12 29

90

12 28 29 32 90

12

28 29 32 90

12 28 29 32 90

8

28 29

28 29 33 89

12 28 29 32

90 27 28 29

30 31

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

12 28

32 90

28 29 33 89

8

28 29

12 28 29 32 90

12 29

90

12 29

90

12 29

90

12 29

90

12 29

90

12 28

32 90

12 28

32 90

12 29

90

12 29

90

12 28 29 32 90

12

28 29 32 90

12 28 29 32

90 27 28 29

30 31

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

12 28

32 90

12 29

90

12 28 29 32 90

12 29 90

12 29

90

12 28 32 90

12 29

90

12 29 90

12 28 29 32 90

12

28 29 32 90

12 28 29 32 90

8

28 29

28 29 33 89

12 28 29 32

90

12 28 29 32 90

27 28 29 30 31

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

28 29 33 89

8

28 29

28 29 33 89

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

NC NC

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

FBGA

OMIT_TABLE

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

201

240

1%

MF

1/20W

MF

1/20W

1%

240

201 201

1%

MF

240

1/20W

MF

1/20W

1%

240

201

CERM-X5R-1

4V

20%

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

201

4V

CERM-X5R-1

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20% 20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20% 20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

CERM-X5R-1

201

0.47UF

20%

4V

0.47UF

201

4V

20%

CERM-X5R-1

201

4V

CERM-X5R-1

0.47UF

20%

201

240

1%

1/20W

MFMF

1/20W

1%

240

201

20%

4V

201

0.47UF

CERM-X5R-1

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

20%

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

201

240

1%

1/20W

MFMF

1/20W

1%

240

201

20%

402

2.2UF

X5R-CERM

10V

402

10V

20%

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

20%

10V

402

X5R-CERM

402

10V

20%

2.2UF

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

20%

10V

402

X5R-CERM

2.2UF

402

10V

20%

2.2UF

X5R-CERM

402

10V

20%

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

20%

10V

402

X5R-CERM

2.2UF

402

10V

20%

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

X5R

201

10%

0.1UF 0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

DDR3-1333

FBGA

OMIT_TABLE

DDR3-1333

FBGA

OMIT_TABLE OMIT_TABLE

FBGA

DDR3-1333

FBGA

DDR3-1333

OMIT_TABLE

DDR3 SDRAM Bank A (2 OF 2)

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

=PP1V5R1V35_S3_MEM_A

MEM_A_ZQ<13>

MEM_A_WE_L

MEM_A_BA<0>

MEM_A_DQ<46>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<1>

MEM_A_A<4>

MEM_A_DQ<41>

PP0V75_S3_MEM_VREFDQ_APP0V75_S3_MEM_VREFDQ_A

MEM_A_A<2>

MEM_A_DQ<6>

MEM_A_DQ<0>

MEM_A_DQ<5>

MEM_A_DQ<7>

MEM_A_DQ<4>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQS_P<0>

MEM_A_CKE<1>

MEM_A_DQ<1>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_ZQ<8>

MEM_A_RAS_L

MEM_A_CLK_P<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<13>

MEM_A_A<15>

=PP1V5R1V35_S3_MEM_A

MEM_A_A<2>

MEM_A_DQ<9>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<12>

MEM_A_DQ<8>

MEM_A_DQ<11>

MEM_A_DQS_P<1>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_DQS_N<1>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<9>

MEM_A_RAS_L

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_DQS_N<0>

MEM_A_A<15>

MEM_A_CLK_N<1>

MEM_A_CS_L<1>

=PP1V5R1V35_S3_MEM_A

MEM_A_DQ<13>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<10>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<10>

MEM_A_WE_L

MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<8>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_DQ<23>

MEM_A_DQS_N<2>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<2>

MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_A<6>

MEM_A_A<2> MEM_A_A<2>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<26>

MEM_A_DQ<30>

MEM_A_DQS_P<3>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_DQS_N<3>

MEM_A_DQ<25>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<11>

MEM_A_RAS_L

MEM_A_CLK_P<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<1>

MEM_A_A<0>

MEM_A_WE_L

MEM_A_A<2>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<39>

MEM_A_DQ<36>

MEM_A_DQS_P<4>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<12>

MEM_A_RAS_L

MEM_A_CLK_P<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<2>

MEM_A_DQ<40>

MEM_A_DQ<42>

MEM_A_DQ<47>

MEM_A_DQ<44>

MEM_A_DQS_P<5>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_DQ<45>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_ODT<1>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQS_N<4>

MEM_A_CLK_N<1>

MEM_A_A<2>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<52>

MEM_A_DQS_P<6>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_DQS_N<6>

MEM_A_DQ<53>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<13>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<6>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<14>

MEM_A_RAS_L

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_DQS_N<5>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_DQ<43>

MEM_A_A<2>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_DQS_P<7>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_DQS_N<7>

MEM_A_DQ<61>

MEM_A_A<15>

MEM_A_BA<2>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<6>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<15>

MEM_A_RAS_L

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<5>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<14>

MEM_A_A<10>

R3000

2

1

R3010

2

1

R3020

2

1

R3030

2

1

C3007

1

2

C3009

1

2

C3008

1

2

C3019

1

2

C3018

1

2

C3017

1

2

C3029

1

2

C3028

1

2

C3027

1

2

C3039

1

2

C3038

1

2

C3037

1

2

C3079

1

2

C3078

1

2

C3077

1

2

C3069

1

2

C3068

1

2

C3067

1

2

C3059

1

2

C3058

1

2

R3070

2

1

R3060

2

1

C3057

1

2

C3049

1

2

C3048

1

2

C3047

1

2

R3050

2

1

R3040

2

1

C3040

1

2

C3000

1

2

C3041

1

2

C3001

1

2

C3050

1

2

C3010

1

2

C3051

1

2

C3011

1

2

C3060

1

2

C3061

1

2

C3020

1

2

C3021

1

2

C3070

1

2

C3071

1

2

C3030

1

2

C3031

1

2

C3043

1

2

C3044

1

2

C3003

1

2

C3004

1

2

C3045

1

2

C3053

1

2

C3005

1

2

C3013

1

2

C3054

1

2

C3014

1

2

C3055

1

2

C3063

1

2

C3015

1

2

C3023

1

2

C3064

1

2

C3065

1

2

C3024

1

2

C3025

1

2

C3073

1

2

C3033

1

2

C3074

1

2

C3034

1

2

C3075

1

2

C3035

1

2

U3000

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3010

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3020

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3030

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3040

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3050

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3060

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3070

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

051-9589

4.18.0

30 OF 132

29 OF 99

8

28 29

8

28 29

12 28 29 32 90

12 28

90

12 28 29 32 90

12 28 29 32 90 12 28

90

28 29 33 89 28 29 33 89

12 28 29 32

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 29

32 90

12 28

90

12 28 29 32

90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

12 28 29 32

90

12 28 29 32

90

12 28 29 32

90

28 29 33 89

12 28 29 32

90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

27 28 29

30 31

12 28

29

32 90

12 28 29 32 90

12 28 29 32

90

12 29 32 90

12 28

29

32 90

12 29 32 90

28 29 33 89

12 28 29 32

90

8

28 29

12 28 29 32 90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 29

32 90

12 29

32 90

12 28

90

12 28 29 32 90

12 28 29 32

90 27 28 29

30 31

12 28 29 32 90

12 29 32 90

12 28 29 32 90

12 29 32 90

12 29

32 90

12 28

90

12 28 29 32 90

8

28 29

12 28

90

28 29 33 89

12 28

90

28 29 33 89

12 29

32 90

12 29 32 90

12 28 29 32 90

12 29 32 90

12 28 29 32 90

27 28 29

30 31

12 28 29 32

90

28 29 33 89

8

28 29

12

28 29 32 90

12 28 29 32 90

12 28

90

12 28

90

12 29

32 90

12 29

32 90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28 29 32 90 12 28 29 32 90

12 28 90

12 28

90

12 29 32 90

12 28

90

12 28 90

12 28 29 32 90

12

28 29 32 90

12 28 29 32 90

8

28 29

28 29 33 89

12 28 29 32

90 27 28 29 30 31

12 28 29 32 90

12 29 32 90

12 28 29 32 90

12 29 32 90

28 29 33 89

12 29 32 90

12 28 29 32 90

12 28 29 32

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 29

32 90

12 28 29 32

90

12 28

29

32 90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

12 28 29 32

90

12 28 29 32 90

12 28

29

32 90

12 28 29 32

90

8

28 29

28 29 33 89

12 28 29 32

90

12 28 29 32

90

12 28 29 32 90

12 28 29 32

90

27 28 29

30 31

12 28

29

32 90

12 28 29 32 90

12 28 29 32

90

12 29 32 90

12 28 29 32 90

12 28

29

32 90

12 29 32 90

28 29 33 89

12 28 29 32 90

12 28

90

12 28

90

12 28

90

12 28

90

12 29

32 90

12 29

32 90

12 28

90

12 28 29 32 90

12 28 29 32

90

12 28 29 32 90

27

28 29 30

31

12 28 29 32 90

12 29 32 90

12 29

32 90

12 29 32 90

12 28

90

12 28 29 32 90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 28

90

12 29

32 90

12 29

32 90

12 28

90

12 28

90

12 28 29 32 90

8

28 29

28 29 33 89

12 28 29 32 90

27 28 29

30 31

12 28 29 32 90

12 29 32 90

12 28 29 32 90

12 29 32 90

12 29

32 90

12 28

90

12 28 29 32 90

12 28 90

12 28

90

12 29 32 90

12 28

90

12 28 90

12 28 29 32 90

12

28 29 32 90

12 28 29 32 90

8

28 29

28 29 33 89

12 28 29 32

90 27 28 29 30 31

12 28 29 32 90

12 29 32 90

12 28 29 32 90

12 29 32 90

28 29 33 89

12 28 29 32 90

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

NC NC

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

OMIT_TABLE

DDR3-1333

FBGA

DDR3-1333

FBGA

OMIT_TABLE

DDR3-1333

FBGA

OMIT_TABLE

MF

1/20W

1%

240

201 201

240

1%

1/20W

MF MF

1/20W

240

201

1%

MF

240

201

1%

1/20W

CERM-X5R-1

20%

4V

201

0.47UF 0.47UF

CERM-X5R-1

201

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

0.47UF

201

CERM-X5R-1

4V

20%

CERM-X5R-1

0.47UF

201

4V

20%

4V

201

CERM-X5R-1

0.47UF 0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

4V

CERM-X5R-1

20%

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

201

CERM-X5R-1

4V

20%

CERM-X5R-1

0.47UF

201

4V

20%

4V

CERM-X5R-1

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

201

240

1%

1/20W

MF

201

MF

240

1/20W

1%

CERM-X5R-1

20%

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V

CERM-X5R-1

20%

CERM-X5R-1

0.47UF

4V

20%

201

240

1%

1/20W

MFMF

1/20W

1%

240

201

X5R-CERM

2.2UF

402

10V

20%

2.2UF

X5R-CERM

20%

10V

402

X5R-CERM

2.2UF

402

10V

20% 20%

10V

402

2.2UF

X5R-CERM

2.2UF

402

10V

20%

402

10V

20%

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

402

10V

20%

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

X5R-CERM

2.2UF

402

20%

X5R-CERM

10V

2.2UF

20%

10V

402

2.2UF

X5R-CERM

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

10%

201

X5R

6.3V 6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF 0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

DDR3-1333

FBGA

OMIT_TABLE

DDR3-1333

FBGA

OMIT_TABLE

DDR3-1333

FBGA

OMIT_TABLE

DDR3-1333

FBGA

OMIT_TABLE

DDR3-1333

FBGA

OMIT_TABLE

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

DDR3 SDRAM Bank B (1 OF 2)

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_ZQ<6>

MEM_B_ZQ<2>

MEM_B_A<2>

MEM_B_A<6>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<7>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<54>

MEM_B_DQS_N<6>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<5>

MEM_B_DQ<32>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<5>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<4>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<38>

MEM_B_DQS_N<4>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<4>

MEM_B_DQ<39>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_A<2>

MEM_B_WE_L MEM_B_WE_L

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_ODT<0>

MEM_B_WE_L

MEM_B_DQ<19>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<3>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<31>

MEM_B_DQS_N<3>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<3>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_A<2>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_DQ<20>

MEM_B_DQ<17>

MEM_B_A<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<22>

MEM_B_DQS_N<2>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<2>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_A<2>

MEM_B_DQ<11>

MEM_B_DQ<3>

MEM_B_A<12>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<1>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<1>

MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_A<2>

=PP1V5R1V35_S3_MEM_B

MEM_B_DQ<2>

MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_DQ<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<7>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<0>

MEM_B_DQ<1>

MEM_B_DQ<6>

MEM_B_A<2>

=PP1V5R1V35_S3_MEM_B

R3100

2

1

R3110

2

1

R3120

2

1

R3130

2

1

C3107

1

2

C3109

1

2

C3108

1

2

C3119

1

2

C3118

1

2

C3117

1

2

C3129

1

2

C3128

1

2

C3127

1

2

C3139

1

2

C3138

1

2

C3137

1

2

C3179

1

2

C3178

1

2

C3177

1

2

C3169

1

2

C3168

1

2

C3167

1

2

C3159

1

2

C3158

1

2

R3170

2

1

R3160

2

1

C3157

1

2

C3149

1

2

C3148

1

2

C3147

1

2

R3150

2

1

R3140

2

1

C3140

1

2

C3100

1

2

C3141

1

2

C3150

1

2

C3101

1

2

C3110

1

2

C3151

1

2

C3111

1

2

C3160

1

2

C3161

1

2

C3120

1

2

C3121

1

2

C3170

1

2

C3171

1

2

C3130

1

2

C3131

1

2

C3143

1

2

C3144

1

2

C3103

1

2

C3104

1

2

C3145

1

2

C3153

1

2

C3105

1

2

C3113

1

2

C3154

1

2

C3114

1

2

C3155

1

2

C3163

1

2

C3115

1

2

C3123

1

2

C3164

1

2

C3165

1

2

C3124

1

2

C3125

1

2

C3173

1

2

C3133

1

2

C3134

1

2

C3174

1

2

C3175

1

2

C3135

1

2

U3100

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3110

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3120

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3130

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3140

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3150

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3160

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3170

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

051-9589

4.18.0

31 OF 132

30 OF 99

12 30 31 32 90

30 31 33 89

12 30 32 90

12 30 31 32 90

12 30 32 90

12 30 31 32 90

27 28 29 30 31

12 30 31 32 90

30 31 33 89

8

30 31

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31 32 90

12 30 31 32 90

12 31 90

12 31

90

12 30 32 90

12 31

90

12 31 90

12 30 31 32 90

30 31 33 89

12 30 32 90

12 30 31 32 90

12 30 32 90

12 30 31 32 90

30 31 33 89

8

30 31

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31 32 90

12 30 31 32 90

30 31 33 89

12 30 31 32 90

12 31

90

30 31 33 89

12 30 32 90

12 30 31 32 90

12 30 32 90

12 30 31 32 90

30 31 33 89

8

30 31

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31 32 90

12 30 31 32 90

30 31 33 89

12 30 32 90

12 30 31 32

90

12 30 31 32

90

12 30 32 90

12 30 31 32

90

12 30 31 32 90

12 30 31 32

90

12 30

31

32 90

12 30 31 32

90

12 30

31

32 90

12 30 31 32

90

8

30 31

12 30

31

32 90

12 30 31 32

90

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31

32 90

12 30 31 32

90

12 30 31 32

90

12 30 31 32 90

12 30 31 32

90 12 30 31 32 90

12 30

32 90

12 30 32 90

12 30 31 32 90

12 31

90

30 31 33 89

12 30 32 90

12 30 31 32 90

27 28 29 30 31

12 30 31 32 90

30 31 33 89

8

30 31

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31 32 90

12 30 31 32 90

12 31 90

12 31

90

12 30 32 90

12 31

90

12 31 90

12 30 31 32 90

30 31 33 89

12 30 31 32 90

12 30 32 90

12 30 31 32 90

30 31 33 89

8

30 31

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31 32 90

12 30 31 32 90

12 31

90

12 30 31 32

90

30 31 33 89

12 30 32 90

12 30 31 32 90

12 30 32 90

12 30 31 32 90

30 31 33 89

8

30 31

12 30 31 32 90

12 30

31

32 90

12 30 31 32 90

8

30 31

30 31 33 89

12 30 32 90

12 30 31 32

90

12 30 32 90

12 30 31 32

90

12 30 31 32 90

12 30 31 32

90

12 30

31

32 90

12 30 31 32

90

12 30

31

32 90

12 30 31 32

90

30 31 33 89

12 30

31

32 90

12 30 31 32

90

12 30 31 32 90

12 30 31 32

90

12 30 31 32 90

12 30

31

32 90

12 30 31 32

90

12 30 31 32

90

12 30 31 32 90

8

30 31

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

NC NC

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

DDR3-1333

FBGA

201

1/20W

240

1%

MF MF

1/20W

1%

240

201 201

240

1%

1/20W

MF MF

1/20W

1%

201

240

0.47UF

4V

201

20%

CERM-X5R-1

20%

CERM-X5R-1

4V

0.47UF

201

20%

4V

201

CERM-X5R-1

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

4V

20%

201

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

4V

CERM-X5R-1

201

0.47UF

CERM-X5R-1

20%

4V

201

0.47UF

201

CERM-X5R-1

4V

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

4V

CERM-X5R-1

201

20%

0.47UF

20%

4V

201

CERM-X5R-1

0.47UF

20%

4V

0.47UF

CERM-X5R-1

201

MF

1/20W

1%

240

201201

240

1%

1/20W

MF

0.47UF

201

CERM-X5R-1

4V

20%

4V

201

0.47UF

CERM-X5R-1

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

MF

1/20W

1%

201

240

201

240

1%

1/20W

MF

X5R-CERM

2.2UF

402

10V

20%

402

X5R-CERM

2.2UF

20%

10V

X5R-CERM

2.2UF

402

10V

20% 20%

10V

402

2.2UF

X5R-CERM

2.2UF

402

10V

20%

402

10V

20%

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

402

10V

20%

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

20%

10V

402

2.2UF

X5R-CERM

402

20%

X5R-CERM

10V

2.2UF

20%

10V

402

2.2UF

X5R-CERM

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

10%

201

X5R

6.3V 6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

0.1UF 0.1UF

6.3V

X5R

201

10%

0.1UF

6.3V

X5R

201

10%

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

DDR3 SDRAM Bank B (2 OF 2)

=PP1V5R1V35_S3_MEM_B

MEM_B_A<2>

MEM_B_DQ<1>

MEM_B_DQ<5>

MEM_B_DQ<0>

MEM_B_DQ<7>

MEM_B_DQS_P<0>

MEM_B_CKE<1>

MEM_B_DQS_N<0>

MEM_B_DQ<4>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<0>

=PP1V5R1V35_S3_MEM_B

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_ZQ<8>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CS_L<1>

MEM_B_A<11>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<11>

MEM_B_DQ<8>

MEM_B_DQ<15>

MEM_B_DQ<10>

MEM_B_DQS_P<1>

MEM_B_CS_L<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<9>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CKE<1>

MEM_B_DQ<3>

MEM_B_DQ<6>

MEM_B_DQ<9>

MEM_B_DQ<12>

MEM_B_DQS_N<1>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2> MEM_B_A<2>

MEM_B_DQ<20>

MEM_B_DQ<18>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQS_P<2>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_DQS_N<2>

MEM_B_DQ<21>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<10>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

=PP1V5R1V35_S3_MEM_B

MEM_B_DQ<19>

MEM_B_A<8>

MEM_B_A<1> MEM_B_A<2>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<24>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQS_P<3>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<11>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_WE_L

MEM_B_A<2>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<36>

MEM_B_DQS_P<4>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_DQS_N<4>

MEM_B_DQ<37>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<1>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<9>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<12>

MEM_B_RAS_L

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_P<1>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<2>

MEM_B_DQ<40>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<46>

MEM_B_DQ<44>

MEM_B_DQS_P<5>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_DQS_N<5>

MEM_B_DQ<45>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<13>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

=PP1V5R1V35_S3_MEM_B

MEM_B_DQ<41>

MEM_B_A<5>

MEM_RESET_L

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<50>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<53>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<14>

MEM_B_RAS_L

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CS_L<1>

MEM_B_DQ<47>

MEM_B_A<2> MEM_B_A<2>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<60>

MEM_B_DQS_P<7>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_DQS_N<7>

MEM_B_DQ<61>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<15>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CKE<1>

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<3>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_BA<2>

MEM_B_DQ<51>

=PP1V5R1V35_S3_MEM_B

MEM_B_DQ<2>

PP0V75_S3_MEM_VREFCA_B

R3200

2

1

R3210

2

1

R3220

2

1

R3230

2

1

C3207

1

2

C3209

1

2

C3208

1

2

C3219

1

2

C3218

1

2

C3217

1

2

C3229

1

2

C3228

1

2

C3227

1

2

C3239

1

2

C3238

1

2

C3237

1

2

C3279

1

2

C3278

1

2

C3277

1

2

C3269

1

2

C3268

1

2

C3267

1

2

C3259

1

2

C3258

1

2

R3270

2

1

R3260

2

1

C3257

1

2

C3249

1

2

C3248

1

2

C3247

1

2

R3250

2

1

R3240

2

1

C3240

1

2

C3200

1

2

C3241

1

2

C3250

1

2

C3201

1

2

C3210

1

2

C3251

1

2

C3211

1

2

C3260

1

2

C3261

1

2

C3220

1

2

C3221

1

2

C3270

1

2

C3271

1

2

C3230

1

2

C3231

1

2

C3243

1

2

C3244

1

2

C3203

1

2

C3204

1

2

C3245

1

2

C3253

1

2

C3205

1

2

C3213

1

2

C3254

1

2

C3214

1

2

C3255

1

2

C3263

1

2

C3215

1

2

C3223

1

2

C3264

1

2

C3265

1

2

C3224

1

2

C3225

1

2

C3273

1

2

C3233

1

2

C3234

1

2

C3274

1

2

C3275

1

2

C3235

1

2

U3200

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3210

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3220

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3230

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3240

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3250

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3260

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

U3270

K4

L8

H8

M8

K8

N4

N8

J8

L4

K3

L9

L3

M9

M3

N9

M4

J3

K9

J4

G4

F8

G8

G10

H3

B8

B4

C8

C3

C9

C4

D4

A1

A4

A11

F2

F10

H2

H10

N1

N11

E4

E9

D3

E8

A8

G2

F4

N3

A3

A10

D8

G9

G3

K2

K10

M2

M10

B10

C2

E3

E10

J9

E2

A2

B2

L10

N10

J2

L2

N2

F3

A9

D9

F9

J10

B3

D2

B9

C10

D10

H4

H9

051-9589

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IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

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DRAWING NUMBER

REVISION

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM Clock Termination

Place RC end termination after last DRAM

Place Source Cterm at neckdown at first DRAM

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

12 30 31 90

1/32W

4X0201

5%

36

4X0201

1/32W

36

5%

1/32W

4X0201

5%

36

4X0201

5%

36

1/32W

36

5%

1/32W

4X0201

1/32W

36

5%

4X0201

1/32W

36

5%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

4V

CERM-X5R-1

201

0.47UF

5% 4X0201

1/32W

36

20%

4V

201

0.47UF

CERM-X5R-1

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

0.47UF

201

4V

CERM-X5R-1

0.47UF

201

20%

0.47UF

201

CERM-X5R-1

4V

20%

PLACE_NEAR=U3270.F7:3.2mm

3.3PF

201

CERM

25V

5%

30

1/20W

MF

5%

201

PLACE_NEAR=U3000.F7:3.2mm

3.3PF

201

CERM

25V

5%

1/32W

36

4X0201

5%

30

1/20W

MF

5%

201

5%

MF

1/20W

30

1/20W

MF

5%

201

10%

6.3V

X5R

201

0.1UF

10%

6.3V

X5R

201

0.1UF

10%

6.3V

X5R

201

0.1UF

10%

6.3V

X5R

201

0.1UF

30

1/20W

MF

5%

201

5%

1/32W

4X0201

36

201

5%

MF

1/20W

30

PLACE_NEAR=U2900.F7:3.2mm

201

3.3PF

CERM

25V

5%

30

201

5%

MF

1/20W

30

1/20W

MF

5%

201

PLACE_NEAR=U3170.F7:3.2mm

3.3PF

CERM

201

25V

5%

12 28 90

12 30 90

12 29 90

20%

4V

CERM-X5R-1

201

0.47UF

12 29 90

12 31 90

36

5%

1/32W

4X0201

12 29 90

1/32W

36

5% 4X0201

12 28 29 90

36

4X0201

1/32W

5%

12 30 31 90

36

4X0201

5%

1/32W

0.47UF

201

CERM-X5R-1

4V

20%

12 30 31 90

36

4X0201

1/32W

5%

12 30 31 90

36

5%

1/32W

4X0201

12 28 29 90

4X0201

1/32W

5%

36

12 28 29 90

1/32W

5%

36

4X0201

12 30 31 90

20%

4V

CERM-X5R-1

201

0.47UF

5%

1/32W

4X0201

36

12 31 90

12 30 31 90

12 30 90

12 30 31 90

12 31 90

12 30 31 90

12 30 90

12 30 31 90

12 28 29 90

12 28 90

12 29 90

12 28 29 90

12 30 31 90

12 28 29 90

1/32W

4X0201

5%

36

4X0201

5%

36

1/32W

5% 4X0201

36

1/32W

5%

36

1/32W

4X0201

5% 4X0201

1/32W

36

12 30 31 90

4X0201

1/32W

36

5%

4X0201

1/32W

36

5%

36

1/32W

4X0201

1/32W

36

5%

4X0201

1/32W

5%

36

5%

36

4X0201

1/32W

4X0201

5%

36

5%

36

1/32W

4X0201

1/32W

5%

36

4X0201

5%

1/32W

36

12 30 31 90

5%

36

4X0201

1/32W

5%

1/32W

4X0201

36

20%

4V

201

0.47UF

CERM-X5R-1

0.47UF

201

4V

20%

CERM-X5R-1

201

4V

20%

0.47UF

CERM-X5R-1

5%

1/32W

4X0201

36

1/32W

4X0201

5%

36

5%

1/32W

4X0201

1/32W

5%

36

4X0201

1/32W

5% 4X0201

36

12 30 31 90

4X0201

1/32W

5%

36

1/32W

4X0201

5%

36

1/32W

4X0201

5%

36

1/32W

4X0201

36

5%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

36

1/32W

4X0201

5%

12 28 29 90

1/32W

4X0201

5%

36

12 28 29 90

12 29 90

12 28 29 90

12 28 90

12 28 29 90

4X0201

1/32W

36

5%

12 28 90

12 28 29 90

36

1/32W

5% 4X0201

5%

1/32W

36

4X0201

36

1/32W

5% 4X0201

1/32W

5%

36

4X0201

36

5% 4X0201

1/32W

36

4X0201

5%

1/32W

36

4X0201

5%

1/32W

36

4X0201

1/32W

5%

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

DDR3 Termination

MEM_B_CAS_L

MEM_B_A<14>

MEM_B_A<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_A<4>

MEM_B_CS_L<0>

MEM_B_A<1>

MEM_B_A<11>

MEM_B_A<15>

=PP0V75_S0_MEM_VTT_B

MEM_B_A<2>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_ODT<1>

MEM_B_CKE<1>

MEM_B_WE_L

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_A<10>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_A_A<14>

MEM_A_A<8>

MEM_A_ODT<1>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_ODT<0>

MEM_A_A<15>

MEM_A_CS_L<0>

MEM_B_A<3>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_CS_L<1>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CLK1_TERM_R

MEM_B_CLK_P<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_B_CLK0_TERM_R

MEM_A_CLK1_TERM_R

MEM_A_CLK0_TERM_R

MEM_B_A<13>

MEM_A_BA<1>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_CKE<1>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_WE_L

MEM_A_A<4>

MEM_A_RAS_L

MEM_A_A<2>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_CS_L<1>

=PP0V75_S0_MEM_VTT_A

MEM_A_CKE<0>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_B_CLK_N<0>

MEM_A_CLK_N<1>

RP3330

3 6

RP3326

1 8

RP3330

1 8

RP3328

2 7

RP3330

2 7

RP3324

2 7

C3330

1

2

C3328

1

2

C3326

1

2

RP3320

1 8

RP3324

4 5

RP3330

4 5

RP3320

3 6

RP3320

2 7

RP3322

2 7

RP3322

4 5

RP3326

3 6

RP3328

3 6

RP3328

4 5

RP3326

2 7

RP3324

3 6

RP3322

3 6

RP3320

4 5

RP3328

1 8

RP3324

1 8

RP3322

1 8

RP3326

4 5

C3324

1

2

C3322

1

2

C3320

1

2

RP3306

3 6

RP3301

1 8

RP3301

3 6

RP3304

4 5

RP3304

2 7

RP3307

4 5

RP3302

4 5

RP3303

3 6

RP3307

1 8

C3310

1

2

C3308

1

2

C3306

1

2

RP3307

2 7

RP3303

4 5

RP3304

1 8

RP3306

4 5

RP3302

3 6

RP3304

3 6

RP3303

2 7

RP3307

3 6

RP3306

1 8

RP3303

1 8

RP3302

1 8

RP3301

2 7

RP3301

4 5

RP3302

2 7

RP3306

2 7

C3304

1

2

C3302

1

2

C3300

1

2

C3323

1

2

C3327

1

2

C3325

1

2

C3307

1

2

C3303

1

2

C3305

1

2

C3365

1

2

R3366

1 2

C3355

1

2

R3365

1 2

R3356

1 2

R3355

1 2

C3366

1 2

C3356

1 2

C3351

1 2

C3361

1 2

R3350

1 2

R3351

1 2

C3350

1

2

R3360

1 2

R3361

1 2

C3360

1

2

RP3305

1 8

RP3305

2 7

RP3325

2 7

RP3325

3 6

RP3325

1 8

RP3305

3 6

RP3305

4 5

RP3325

4 5

051-9589

4.18.0

33 OF 132

32 OF 99

8

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

D

S G

D

S G

NC

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable

Addr=0x30(WR)/0x31(RD)

- =PPDDR_S3_MEMVREF

8.59mV / step @ output

MEM B VREF CA

watchdog will disable margining.

3

C

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

1.267V (DAC: 0x8B)

0.000V - 3.300V (0x00 - 0xFF)

GPU Frame Buffer (1.8V, 70% VRef)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

MEM A VREF CA

4

(OD)

PCA9557D Pin:

Nominal value

DAC Channel:

A

2

B

0.300V - 1.200V (+/- 450mV)

C

0.000V - 1.501V (0x00 - 0x74)

5

D

MEM VREG

+61uA - -61uA (- = sourced)

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74)

6

D

10mA max load

DDRVREF_DAC - Stuffs Apple margining circuit.

VREFDQ:LDO - LDO outputs sent to DQ inputs.

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

VREFCA:LDO - LDO outputs sent to CA inputs.

BOM options provided by this page:

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =I2C_VREFDACS_SCL

- =PP3V3_S3_VREFMRGN

Required zero ohm resistors when no VREF margining circuit stuffed

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

DAC range:

1

DDR3L (1.35V) 6.99mV per step

both at the same time!

Addr=0x98(WR)/0x99(RD)

MEM A VREF DQ MEM B VREF DQ

Margined target:

VRef current:

DAC step size:

7.69mV / step @ output

+3.4mA - -3.4mA (- = sourced)

0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)

DDR3 (1.5V) 7.70mV per step

NOTE: CPU DAC output step sizes:

soft-resets and sleep/wake cycles.

NOTE: Margining will be disabled across all

RST* on ’platform reset’ so that system

VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

Power aliases required by this page:

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

Page Notes

64

0.1UF

402

CERM

10V

20%

DDRVREF_DAC

402

MF-LF

PLACE_NEAR=R7320.2:1mm

DDRVREF_DAC

1/16W

1%

33.2K

402

100K

MF-LF

5%

1/16W

DDRVREF_DAC

402

100K

MF-LF

5%

1/16W

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

UCSP

MAX4253

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

DDRVREF_DAC

CRITICAL

MAX4253

UCSP

DDRVREF_DAC

CRITICAL

MAX4253

UCSP

DDRVREF_DAC

MAX4253

CRITICAL

UCSP

DDRVREF_DAC

402

1%

1/16W

MF-LF

PLACE_NEAR=J2900.126:2.54mm

VREFCA:LDO_DAC

200

402

1/16W

200

1%

MF-LF

PLACE_NEAR=J3100.126:2.54mm

VREFCA:LDO_DAC

402

OMIT

NONE

SHORT

402

OMIT

NONE

SHORT

25

402

PLACE_NEAR=J2900.1:2.54mm

1%

200

1/16W

MF-LF

VREFDQ:LDO_DAC

402

PLACE_NEAR=R3403.2:1mm

MF-LF

1%

1/16W

133

VREFDQ:LDO_DAC

402

VREFDQ:LDO_DAC

200

PLACE_NEAR=J3100.1:2.54mm

MF-LF

1%

1/16W

402

1%

133

1/16W

MF-LF

PLACE_NEAR=R3405.2:1mm

VREFDQ:LDO_DAC

402

1/16W

5%

MF-LF

0

DDRVREF_DAC

402

DDRVREF_DAC

0

MF-LF

5%

1/16W

10%

0.1UF

16V

0402

X7R-CERM

VREFDQ:M1_M3

PLACE_NEAR=Q3420.3:2mm

VREFDQ:M1_M3

SSM6N15FEAPE

SOT563

CRITICAL

10%

0.1UF

16V

0402

X7R-CERM

VREFDQ:M1_M3

PLACE_NEAR=Q3420.6:2mm

VREFDQ:M1_M3

CRITICAL

SOT563

SSM6N15FEAPE

402

PLACE_NEAR=R3421.2:1mm

MF-LF

1/16W

1%

1K

VREFDQ:M1_M3

402

PLACE_NEAR=R3441.2:1mm

1%

1/16W

1K

VREFDQ:M1_M3

MF-LF

402

1K

1/16W

MF-LF

VREFDQ:M1_M3

1%

PLACE_NEAR=Q3420.6:1mm

402

1/16W

1%

1K

VREFDQ:M1_M3

PLACE_NEAR=Q3420.3:1mm

MF-LF

402

100K

MF-LF

5%

1/16W

DDRVREF_DAC

402

100K

5%

1/16W

MF-LF

DDRVREF_DAC

402

MF-LF

1%

PLACE_NEAR=R3409.2:1mm

133

1/16W

VREFCA:LDO_DAC

402

MF-LF

5%

100K

1/16W

DDRVREF_DAC

QFN

CRITICAL

PCA9557

DDRVREF_DAC

0.1UF

402

20%

10V

CERM

DDRVREF_DAC

402

1/16W

MF-LF

1%

133

PLACE_NEAR=R3411.2:1mm

VREFCA:LDO_DAC

402

100K

1/16W

MF-LF

5%

DDRVREF_DAC

44

MSOP

DAC5574

DDRVREF_DAC

CRITICAL

44

0.1UF

402

CERM

20%

10V

DDRVREF_DAC

6.3V

20%

2.2UF

CERM

402-LF

DDRVREF_DAC

0.1UF

402

DDRVREF_DAC

20%

CERM

10V

0.1UF

402

20%

CERM

10V

DDRVREF_DAC

VREFDQ:M1_DAC

R3404,R3406

2

RES,MTL FILM,332,1%,0402,SM,LF

114S0171

RES,MTL FILM,1K,1%,0402,SM,LF

114S0218

VREFDQ:M1_DAC

R3421,R3422,R3441,R3442

4

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

VREFCA:LDO

R3409,R3411

2

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

VREFDQ:LDO

2

R3403,R3405

SYNC_DATE=01/13/2012

DDR3/FRAMEBUF VREF MARGINING

SYNC_MASTER=D2_KEPLER

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_B

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

VREFMRGN_CA_SODIMMA_EN

PP0V75_S3_MEM_VREFDQ_B

=PPDDR_S3_MEMVREF

VREFMRGN_CA_SODIMMA_BUF

PPCPU_MEM_VREFDQ_A

=PPDDR_S3_MEMVREF

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

VREFMRGN_MEMVREG_FBVREF_R

VREFMRGN_FRAMEBUF_BUF_R

MEMRESET_ISOL_LS5V_L

PPCPU_MEM_VREFDQ_B

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SCL

PCA9557D_RESET_L

MEMRESET_ISOL_LS5V_L

PP0V75_S3_MEM_VREFDQ_A

DDRREG_FB

VREFMRGN_SODIMMS_CA

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_SODIMMB_DQ

VREFMRGN_SODIMMA_DQ

=PPVTT_S3_DDR_BUF

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_BUF

=PP3V3_S3_VREFMRGN

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_FRAMEBUF_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_FRAMEBUF_BUF

U3401

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C3403

1

2

C3402

1

2

R3402

1

2

R3401

1

2

R3410

1 2

R3407

1

2

C3404

1

2

R3412

1 2

R3408

1

2

U3400

9

10

3

6

7

8

1

2

4

5

C3401

1

2

C3400

1

2

C3405

1

2

R3414

1 2

R3413

1

2

R3415

1

2

U3402

C3

C2

C1

C4

B1

B4

U3403

A3

A2

A1

A4

B1

B4

U3402

A3

A2

A1

A4

B1

B4

U3403

C3

C2

C1

C4

B1

B4

U3404

A3

A2

A1

A4

B1

B4

U3404

C3

C2

C1

C4

B1

B4

R3409

1 2

R3411

1 2

R3418

1 2

R3419

1 2

R3403

1 2

R3404

1 2

R3405

1 2

R3406

1 2

R3417

1

2

R3416

1

2

C3440

1

2

Q3420

3

5

4

C3420

1

2

Q3420

6

2

1

R3422

1

2

R3442

1

2

R3421

1

2

R3441

1

2

051-9589

4.18.0

34 OF 132

33 OF 99

30 31 33 89

28 29 33 89

30 31 89

28 29 89

30 31 33 89

8

33

10 89

8

33

27 33

10 89

27 33

28 29 33 89

8

64

8

BI

IN

BI

SYM_VER-1

IN

SYM_VER-1

OUT

IN

OUT

IN

OUT

IN

OUT

G

S

D

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

IN

D

G S

OUT

BI

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SEL OUTPUT

H USB_BT

L USB_BT_WAKE

AIRPORT

155S0367

CURRENT SENSE

BLUETOOTH

CAMERA

ALS

206 mA nominal max

275 mA peak

1A PEAK

14 mOhm Typ

DMP2018LFK

20 mOhm Max

1 A (EDP)

P-TYPE

3V S3 WLAN FET

RDS(ON) @ 2.5V

MOSFET

LOADING

CHANNEL

Supervisor & CLKFREG # Isolation

Delay = 130 ms +/- 20%

PLACE_NEAR=J3502.6:2.54MM

FERR-120-OHM-1.5A

0402-LF

0.1uF

20%

10V

CERM

402

19 91

44

PLACE_NEAR=J3502.3:2.54MM

DLP0NS

CRITICAL

90-OHM

70

10K

MF-LF

1/16W

5%

402

MF-LF

1/16W

5%

33K

402

10%

X5R

16V

0.033UF

402

10%

0.1UF

0402

X7R-CERM

16V

FERR-120-OHM-3A

0603

0.1uF

20%

10V

PLACE_NEAR=J3501.29:2.54MM

CERM

402

0.1uF

PLACE_NEAR=J3501.29:2.54MM

10V

CERM

402

20%

17 92

10%

0.1UF

0402X7R-CERM

16V

PLACE_NEAR=J3501.15:2.54MM

10%

0.1UF

0402X7R-CERM

16V

PLACE_NEAR=J3501.17:2.54MM

PLACE_NEAR=J3501.11:2.54MM

90-OHM-100MA

DLP11S

CRITICAL

PLACE_NEAR=J3501.27:2.54MM

FERR-120-OHM-1.5A

0402-LF

BTPWR:S3

7

18

10%

16V

X7R-CERM

0402

0.01UF

CRITICAL

CCR20-6K710S

F-RT-SM

OMIT

25

19 24 70

17

0.1uF

10V

20%

CERM

402

232K

1%

MF-LF

1/16W

402

100K

1%

1/16W

MF-LF

402

100K

1/16W

MF-LF

1%

7

41 42

10%

0.1UF

16V

NOSTUFF

X5R-CERM

0201

0.6NH+/-0.1NH-0.85A

OMIT_TABLE

0201

10%

0.1UF

16V

0201

X5R-CERM

NOSTUFF

10%

0.1UF

16V

NOSTUFF

0201

X5R-CERM

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

0201

10%

0.1UF

16V

X5R-CERM

NOSTUFF

0201

10%

0.1UF

16V

X5R-CERM

NOSTUFF

0201

OMIT_TABLE

0201

0.6NH+/-0.1NH-0.85A

10%

0.1UF

16V

0201

X5R-CERM

NOSTUFF

10%

0.1UF

16V

NOSTUFF

X5R-CERM

0201

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

0201

10%

0.1UF

16V

NOSTUFF

0201

X5R-CERM

17 92

514S0335

SSD-K99

F-RT-SM1

CRITICAL

34 99

CRITICAL

DMP2018LFK

DFN2563-6

TQFN

CRITICAL

PI3USB102ZLE

10%

16V

NOSTUFF

X7R-CERM

0402

0.01UF

10%

X5R

6.3V

201

0.1UF

MF

1/20W

5%

0

201

BTPWR:S4

1/20W

MF

15K

1%

201

BTPWR:S4

1/20W

1%

MF

201

15K

NOSTUFF

201

MF

1%

15K

1/20W

NOSTUFF

SOD-VESM-HF

BTPWR:S4

SSM3K15FV

SIGNAL_MODEL=EMPTY

42

9

91

9

91

PLACE_NEAR=J3501.27:2.54MM

0402-LF

FERR-120-OHM-1.5A

BTPWR:S4

NOSTUFF

201

MF

1%

1/20W

15K

1%

MF

201

15K

1/20W

NOSTUFFNOSTUFF

201

1%

15K

1/20W

MF

201

MF

1/20W

5%

0

BTPWR:S3

CRITICAL

TDFN

SLG4AP041V

X29/ALS/CAMERA CONNECTOR

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

RES, 0OHM, 0201

4

117S0002

L3570,L3571,L3573,L3574

1

J3502

CONN,HDR,TWIN-AX,P=0.4MM,6P,HF

CRITICAL518S0767

AP_CLKREQ_L

AP_PWR_EN

AP_RESET_L

AP_CLKREQ_Q_L

=PP3V3_S3_WLAN

P3V3WLAN_VMON

AP_RESET_CONN_L

PP3V3_WLAN_F

PP3V3_S3RS4_BT_F

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

PP3V3_WLAN_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

PP5V_S3_ALSCAMERA_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

=BT_WAKE_L

PM_SLP_S4_L

PCIE_CLK100M_AP_N

PCIE_AP_D2R_P

PCIE_WAKE_L

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP_CONN_P

PCIE_AP_D2R_PI_P

PCIE_AP_D2R_PI_N

=I2C_ALS_SCL

USB_CAMERA_CONN_N

WIFI_EVENT_L

=I2C_ALS_SDA

=PP5V_S3_ALSCAMERA

PCIE_AP_R2D_C_P

PCIE_AP_R2D_PI_N

PCIE_AP_R2D_C_N

USB_CAMERA_N

USB_CAMERA_P

PCIE_AP_R2D_PI_P

P3V3WLAN_SS

USB_BT_P

USB_BT_N

PCIE_CLK100M_AP_P

USB_CAMERA_CONN_P

PCIE_AP_D2R_N

PM_WLAN_EN_L

=PP3V3_S3_WLAN

=PP3V3_S3_BT

=PP3V3_S4_BT

USB_BT_WAKE_P

PCIE_AP_R2D_N

PCIE_AP_R2D_P

USB_BT_CONN_P

USB_BT_CONN_N

BTMUX_SEL

PP3V3_WLAN

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

USB_BT_WAKE_N

L3508

12

C3552

1

2

L3507

4 3

21

R3551

1

2

R3550

1 2

C3551

1

2

C3550

1 2

L3504

1 2

C3521

1

2

C3522

1

2

C3531

1 2

C3530

1 2

L3501

4 3

21

L3506

12

C3532

1

2

J3502

7

8

1

2

3

4

5

6

C3540

1

2

R3554

1

2

R3555

1

2

R3553

1

2

C3570

1

2

L3570

1 2

C3571

1

2

C3573

1

2

L3571

1 2

C3572

1

2

C3575

1

2

L3573

1 2

C3574

1

2

C3577

1

2

L3574

1 2

C3576

1

2

J3501

19

20

21

1

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

Q3550

4

3

1

2

U3510

6

7

3

4

5

8

10

9

2

1

C3511

1

2

C3510

1

2

R3511

1 2

R3512

1

2

R3514

1

2

R3513

1

2

Q3510

3

12

L3505

12

R3517

1

2

R3516

1

2

R3515

1

2

R3518

1

2

U3540

6

5

7

3

8

4

2

9

1

051-9589

4.18.0

35 OF 132

34 OF 99

7

8

34

7

34 99

7

34

7

96

7

96

7

92

7

92

7

91

8

92

7

91

8

34

8

91

7

92

7

92

7

91

7

91

7

42

91

OUT

BI

IN

BI

IN

OUT

PETN_3

PETN_2

PETP_2

PETP_1

PETN_1

PETP_0

PETN_0

MONOBS_N

MONDC0

MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0

PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P

PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI

EE_DO

EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P

REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS

TCK

TEST_EN

TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N

PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OE

GND

VCC

A Y

OE

GND

VCC

A Y

OUT

D

C

Q

S*

W*

HOLD*

PAD

VSS THM

VCC

IN

OUT

IN

BI

OUT

IN

OUT

BI

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

Not used in host mode.

(TBT_EN_CIO_PWR_L)

DEBUG: For monitoring clock

CR HPD INPUTS (S4) FORWARDED TO GMUX (S0)

SNK0 AC Coupling

Divides 3.3V to 1.8V

DEBUG: For monitoring current/voltage

(TBT_SPI_MOSI)

SNK1 AC Coupling

(TBT_SPI_CS_L)

(TBT_SPI_CLK)

Use AA8 GND ball for THERM_DN

(TBT_SPI_MISO)

(FORCE_PWR)

201

1/20W

MF

3.3K

5%

82

201

1/20W

MF

0

5%

1/20W

5%

100K

MF

201

1/20W

100K

5%

MF

201

MF

5%

201

1/20W

100K

201

1/20W

MF

0

5%

MF

201

3.3K

1/20W

0.1UF

10%

X5R-CERM

16V

0201

7

83 95

7

83 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

0.1UF

16V10%

X5R-CERM

0201

0.1UF

16V10%

X5R-CERM

0201

0.1UF

16V10%

X5R-CERM

0201

0.1UF

16V10%

X5R-CERM

0201

0.1UF

16V

X5R-CERM

10%

0201

X5R-CERM

0.1UF

16V10%

0201

0.1UF

16V

X5R-CERM

10%

0201

1/20W

MF

1%

1K

201

0.1UF

X5R-CERM

0201

10% 16V

X5R-CERM

0.1UF

0201

X5R-CERM

10%

0.1UF

16V

0201

10%

0.1UF

16V

X5R-CERM

0201

X5R-CERM

0201

0.1UF

16V10%

0.1UF

16V

X5R-CERM

10%

0201

10%

X5R-CERM

0.1UF

16V

0201

X5R-CERM

0201

16V

0.1UF

10%

0.1UF

16V

X5R-CERM

10%

0201

0.1UF

16V

X5R-CERM

10%

0201

0.1UF

16V

X5R-CERM

10%

X5R-CERM

0.1UF

16V10%

0201

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

7

77 95

10%

402

CERM

6.3V

1UF

7

83 95

7

83 95

37

20

CRITICAL

OMIT_TABLE

FCBGA

CACTUSRIDGE4C

37

25 91

10K

5%

MF

1/20W

201

1/20W

806

1%

MF

201

MF

201

1K

5%

1/20W

201

10K

5%

1/20W

MF

NO STUFF

17 92

35 84

84

35 37 84

35 84

84 93

84

7

84 93

7

84 93

7

84 93

7

84 93

84

82 84

7

84 93

7

84 93

7

84 93

7

84 93

35 85

85

35 37 85

35 85

85 93

85

7

85 93

7

85 93

7

85 93

7

85 93

85

82 85

7

85 93

7

85 93

7

85 93

7

85 93

35 84

5%

1K

201

MF

1/20W

NOSTUFF

5%

MF

201

1K

1/20W

NOSTUFF

35 85

SOT833

74LVC2G126GT/S500

NOSTUFF

SOT833

74LVC2G126GT/S500

NOSTUFF

100K

5%

1/20W

MF

201

82

100K

5%

201

1/20W

MF

82

OMIT_TABLE

M95256-RMC6XG

MLP

CRITICAL

37

NO STUFF

0201

X5R-CERM

16V

10%

0.1UF

201

47K

5%

1/20W

MF

0201

NONE

NOSTUFF

OMIT

35 82

37

44

18 42

20 25

MF

1/20W

5%

10K

201

0201

16V

X5R-CERM

0.1UF

10%

201

MF

1/20W

5%

10K

201

MF

1/20W

5%

10K

201

MF

1/20W

5%

10K

MF

201

10K

5%

1/20W

10K

201

5%

MF

1/20W

201

10K

5%

1/20W

MF

NO STUFF

201

100K

5%

1/20W

MF

20

X5R-CERM

0201

16V10%

0.1UF

20

MF

1/20W

5%

0

201

16V

0201

0.1UF

10%

X5R-CERM

0201

16V

X5R-CERM

0.1UF

10%

3.3K

1/20W

201

MF

5%

0201

16V

X5R-CERM

0.1UF

10%

0201

16V

X5R-CERM

0.1UF

10%

0.1UF

X5R-CERM

0201

16V

0201

16V

X5R-CERM

10%

0.1UF

16V

0201

X5R-CERM

10%

0.1UF

X5R-CERM

0201

16V10%

0.1UF

0201

16V

X5R-CERM

10%

201

MF

5%

3.3K

1/20W

0.1UF

0201

16V

X5R-CERM

10%

0.1UF

10% 16V

0201

X5R-CERM

10%

0201

16V

0.1UF

0201

16V

X5R-CERM

10%

0.1UF

X5R-CERM

0201

10% 16V

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

9

92

SYNC_DATE=01/13/2012

Thunderbolt Host (1 of 2)

SYNC_MASTER=D2_KEPLER

TBT_CIO_PLUG_EVENT

TBT_DDC_XBAR_EN_L

JTAG_TBT_TDO

TBT_SPI_MISO

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

TBT_B_R2D_C_N<0>

TBT_B_D2R_P<0>

=PP3V3_S0_DPMUX_UC

TBT_B_D2R_N<0>

TBT_B_R2D_C_P<0>

=I2C_TBTRTR_SDA

=I2C_TBTRTR_SCL

TBT_TEST_EN

TBT_SPI_CLK

JTAG_TBT_TCK

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<0>

NO_TEST=TRUE

PCIE_TBT_R2D_P<1>

NO_TEST=TRUE

PCIE_TBT_R2D_N<1>

NO_TEST=TRUE

PCIE_TBT_R2D_P<3>

NO_TEST=TRUE

PCIE_TBT_R2D_N<3>

NO_TEST=TRUE

PCIE_TBT_R2D_P<0>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<1>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<1>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<3>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<2>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<2>

PCIE_TBT_R2D_P<2>

NO_TEST=TRUE

PCIE_TBT_R2D_N<2>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<0>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<0>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<3>

TBT_A_R2D_C_N<0>

TP_DP_TBTSRC_ML_CP<1>

=PP3V3_S0_DPMUX_UC

DP_TBTSNK0_ML_C_P<0>

TBT_B_D2R_N<1>

TBT_B_D2R_P<1>

TBT_GPIO_9

=PP3V3_TBTLC_RTR

TBT_A_HV_EN

TBT_B_HV_EN

=PP3V3_S4_TBT

TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2>

TBT_SPI_MOSI

=PP3V3_TBTLC_RTR

SYSCLK_CLK25M_TBT

TP_DP_TBTSRC_ML_CN<3>

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBTROM_WP_L

TBTROM_HOLD_L

TBT_TEST_PWR_GOOD

TP_TBT_THERM_DP

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_HPD

TP_DP_TBTSRC_ML_CP<2>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<0>

TBT_PCIE_RESET_L

TP_TBT_MONDC0

TP_TBT_MONDC1

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_N<1>

TP_TBT_PCIE_RESET1_L

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<0>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_P<1>

=TBT_CLKREQ_L

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

TP_TBT_PCIE_RESET2_L

TP_TBT_PCIE_RESET0_L

TBT_RSENSE

DP_TBTPA_ML_C_N<1>

TBT_A_CONFIG1_BUF

TBT_A_CONFIG2_RC

TBT_A_LSTX

TBT_A_LSRX

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_AUXCH_C_N

DP_TBTPA_HPD

TBT_A_HV_EN

TBT_A_CIO_SEL

TBT_B_LSRX

TBT_B_LSTX

TBT_B_DP_PWRDN

TBT_B_CONFIG1_BUF

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_P<2>

TBT_B_HV_EN

=PP3V3_S4_TBT

TBT_MONOBSP

TBT_MONOBSN

DP_TBTPA_HPD_BUF

DP_TBTPA_HPD_BUF_EN

DP_TBTPA_HPD

=PP3V3_S0_DPMUX_UC

DP_TBTPB_HPD_BUF

DP_TBTPB_HPD_BUF_EN

DP_TBTPB_HPD

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<3>

TBT_A_R2D_C_P<0>

TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<1>

TBT_A_D2R_P<1>

TBT_A_D2R_N<1>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_N<1>

TP_DP_TBTSRC_ML_CP<3>

TBT_SPI_CS_L

=PP3V3_TBTLC_RTR

TP_TBT_XTAL25OUT

TBT_GPIO_14

JTAG_TBT_TMS

JTAG_TBT_TDI

SYSCLK_CLK25M_TBT_R

DP_TBTSNK0_ML_P<3>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_ML_CN<2>

DP_TBTSRC_HPD

TBT_TMU_CLK_OUT

TBT_TMU_CLK_IN

TBT_RBIAS

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<3>

DP_TBTPB_HPD

DP_TBTPB_AUXCH_C_P

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_P<3>

DP_TBTPB_AUXCH_C_N

TBT_GPIO_14

DP_TBTSNK0_HPD

=TBT_WAKE_L

TBT_A_DP_PWRDN

DP_TBTSNK0_ML_P<1>

DP_TBTSNK1_ML_P<1>

TBT_GO2SX_BIDIR

TBT_GPIO_9

TBT_PWR_REQ_L

TBT_PWR_EN

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CP<0>

TBT_B_CONFIG2_RC

TBT_EN_LC_PWR

TP_TBT_PCIE_RESET3_L

DP_TBTSNK1_ML_P<3>

TBT_B_CIO_SEL

=PP3V3_S0_DPMUX_UC

TBT_DDC_XBAR_EN_L

R3690

1

2

C3690

1

2

R3692

1

2

R3691

1

2

R3655

1

2

C3601

1 2

C3600

1 2

C3602

1 2

C3603

1 2

C3604

1 2

C3605

1 2

C3606

1 2

C3607

1 2

C3640

1 2

C3641

1 2

C3642

1 2

C3643

1 2

C3645

1 2

C3644

1 2

C3646

1 2

C3647

1 2

R3625

1

2

R3632

1

2

R3630

1

2

R3631

1

2

R3629

1

2

R3693

1

2

C3629

1 2

C3628

1 2

C3627

1 2

C3626

1 2

C3625

1 2

C3624

1 2

C3623

1 2

C3622

1 2

C3621

1 2

C3620

1 2

C3630

1 2

C3631

1 2

C3632

1 2

C3633

1 2

C3634

1 2

C3635

1 2

C3636

1 2

C3637

1 2

C3638

1 2

C3639

1 2

U3600

D19

E20

D17

E18

D15

E16

D13

E14

B5

A6

U6

D11

E12

D9

E10

D7

E8

D5

E6

B3

A4

T5

B9

A8

B11

A10

B13

A12

B15

A14

D3

C2

V3

W4

AD3

R4

P5

K5

G2

M3 L2

H3 L4

T3

V5

M1

Y1

W2

J4

AA2

AB1

AC2

P3

M5

AD23

AC24

W16

W18

F1

F3

E22

G22

E24

G24

J22

L22

J24

L24

K1

G4

B17

A16

B19

A18

H1

J6

N2

E2

D1

N22

R22

N24

R24

U22

W22

U24

W24

P1

H5

B21

A20

B23

A22

K3

G6

L6

W6

N6

T1

Y5

U2

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

R6

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

J2

W20

AD21

AB21

U20

AA6

V1

R2

N4

AB5

Y7

AB3

Y3

AA4

AA24

AB23

R3698

1

2

R3695

1 2

R3696

1

2

R3699

1

2

R3643

1 2

R3642

1 2

U3610

2

4

1

8

6

U3610

5

4

7

8

3

R3645

1

2

R3644

1

2

U3690

6

5

7

2

1

9

8

4

3

C3610

1

2

R3610

1

2

R3615

1

2

R3685

1

2

R3686

1

2

R3687

1

2

R3688

1

2

R3680

1

2

R3683

1

2

R3682

1

2

R3697

1

2

R3681

1

2

051-9589

4.18.0

36 OF 132

35 OF 99

U4

93

8

35 78 82

93

92

7

8

35 78 82

35

8

35 36 37

35 37 84

35 37 85

35 36 37

35 85

35 84

7

35 95

7

35 95

93

8

35 36 37

7

47

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

35 36 37

8

35 78 82

7

93

8

35 36 37

7

35

91

7

35 95

7

35

7

35 95

7

35 95

35

19

7

35 95

8

35 78 82

35 82

VSSPE

VSS

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE

VCC1P0

VCC3P3_DP

VCC3P3_CIO

VCC3P3

VCC1P0

VCC1P0_ON

VCC3P3

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCCGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP: 1600 mA

EDP: 1100 mA

EDP: 240 mA

???? mW (Single Port)

???? mW (Single-Port)

EDP: 10 mA

??? mW (Single-Port)

250 mW (Dual-Port)

2700 mW (Dual-Port)

250 mW (Dual Port)

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10UF

CERM-X5R

0402-1

6.3V

20%

10V

X5R-CERM

0201-1

1.0UF

20% 20%

10V

X5R-CERM

0201-1

1.0UF

0

402

MF-LF

1/16W

5%

10V

X5R-CERM

0201-1

1.0UF

20%

10UF

0402-1

CERM-X5R

6.3V

20%

10UF

CERM-X5R

0402-1

6.3V

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20% 10V

X5R-CERM

0201-1

1.0UF

20%

CACTUSRIDGE4C

CRITICAL

OMIT_TABLE

FCBGA

CERM-X5R

0402-1

10UF

6.3V

20%

0201-1

X5R-CERM

10V

1.0UF

20%

1.0UF

X5R-CERM

0201-1

10V

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20% 10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

10V

X5R-CERM

0201-1

1.0UF

20%

0201-1

10V

X5R-CERM

1.0UF

20%

Thunderbolt Host (2 of 2)

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

=PP3V3_S4_TBT

=PP3V3_S4_TBT_R

=PP1V05_TBTLC_RTR

=PP3V3_TBTLC_RTR

=PP1V05_TBTCIO_RTR

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S4_TBT

C3714

1

2

C3715

1

2

C3716

1

2

C3710

1

2

C3711

1

2

C3712

1

2

C3717

1

2

C3713

1

2

C3700

1

2

C3701

1

2

U3600

K11

K15

R10

R14

T11

U10

V11

W10

L10

L14

M11

M15

N10

N14

P11

P15

G8

H9

J10

J12

J14

J16

J8

K17

T15

U14

V7

W8

G10

G12

V15

V19

W12

W14

G14

G16

G18

H19

K19

M19

P19

T19

M7

P7

T7

L18

N18

R18

H11

H13

H15

H17

H7

K7

AD1

K13

N16

N8

P13

P17

P9

R12

R16

R8

T13

T17

K9

T9

U12

U16

U8

V9

L12

L16

L8

M13

M17

M9

N12

A2

A24

AC12

AC14

AC16

AC18

AC20

AC22

AC4

AC6

AC8

B1

AA14

B7

C10

C12

C14

C16

C18

C20

C22

C24

C4

AA20

C6

C8

D21

D23

E4

F11

F13

F15

F17

F19

AA22

F21

F23

F5

F7

F9

G20

H21

H23

J18

J20

AA8

K21

K23

L20

M21

M23

N20

P21

P23

R20

T21

AB11

T23

U18

V13

V17

V21

V23

Y11

Y13

Y15

Y17

AB17

Y19

Y21

Y23

Y9

AB7

AC10

C3760

1

2

C3772

1

2

C3771

1

2

C3770

1

2

C3790

1

2

C3744

1

2

C3743

1

2

C3742

1

2

C3741

1

2

C3740

1

2

C3745

1

2

C3705

1

2

C3773

1

2

C3774

1

2

R3790

1 2

051-9589

4.18.0

37 OF 132

36 OF 99

35 37

8

35 37

8

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

D

S G

D

S G

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

NC

IN

S

G

D

SG

D

SG

GND

VOUT

ON

VIN

VOUT

GND

ON

VIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

OUT

D

S G

D

SG

IN

D

GS

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

@ 2.5V

18.3 mOhm Typ

U3810

Max Current = 2A (85C)

R(on)

Type

TPS22924C

Part

R(on)

20.3 mOhm Typ

Load Switch

3.3V TBT "LC" Switch

U3815

Part

SGND shorted to

no XW necessary.

Intel investigating whether RC is sufficient.

Pull-ups provided by SB page.

<R1>

UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO(falling) = 1.22 * (R1 + R2) / R2

Delay = 27.3ms

Vt = 2.33V +/- 2%

1.05V TBT "CIO" Switch

TBT "POC" Power-up Reset

Pull-up: R3610

BOM options provided by this page:

- =PP1V05_TBTLC_FET (1.05V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

TBTBST:Y - Stuffs 15V boost circuitry.

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

Max Current = 2A?

Vout = 15.47V

- =PP3V3_TBTLC_FET (3.3V FET Output)

Vds(max): -30V

TPS22920

11.5 mOhm Max

Load Switch

Part

Type

28.6 mOhm Max

TPS22924C

@ 1.0V

Type

8-13V Input

<R2>

Vgs(max): +/-12V

SI8409DB:

Id(max): 3.7A @ 70C

Supervisor & CLKREQ# Isolation

Vout = 1.6V * (1 + Ra / Rb)

Freq = 300KHz

Voltage not specified here,

add property on another page.

Changes required

for 2S.

GND inside package,

<Ra>

<Rb>

Vgs(th): -1.4V

- =TBT_RESET_L

- =TBT_CLKREQ_L

Signal aliases required by this page:

Max Current = 2A (85C)

DLY = 60 ms +/- 20%

R(on)

@ 1.05V

TPS3808G25

U3820

Max Current = 4A (85C)

8 mOhm Typ

C3816 must be 10%

RC guarantees minimum 5ms to reach 0.5V

UVLO = 4.55V (falling), 4.95 (rising)

- =PP15V_TBT_REG (15V Boost Output)

Rds(on): 46mOhm @ 4.5V Vgs

Thunderbolt 15V Boost Regulator

Platform (PCIe) Reset

Max Vgs: 10V

1.05V TBT "LC" Switch

24 mOhm Max

Load Switch

TPS22924

CRITICAL

CSP

35

17

X5R-CERM

10%

0.1UF

16V

0201

25

35

1UF

6.3V

20%

0201

X5R

20%

0201

X5R

1UF

6.3V

SLG4AP016V

TDFN

CRITICAL

5%

MF

100K

1/20W

201

35 84

35 85

402

MF-LF

1%

1/16W

73.2K

TBTBST:Y

5%

402

TBTBST:Y

MF-LF

1/16W

330K

5%

402

TBTBST:Y

470K

MF-LF

1/16W

402

10V

2.2UF

TBTBST:Y

20%

X5R-CERM

10V

402

20%

TBTBST:Y

2.2UF

X5R-CERM

5%

68PF

0402

COG-CERM

50V

TBTBST:Y

402

2.2UF

TBTBST:Y

X5R-CERM

10V

20%

402

TBTBST:Y

X5R

0.1UF

25V

10%

SOT563

SSM6N37FEAPE

TBTBST:Y

5%

402

1/16W

330K

MF-LF

TBTBST:Y

SOT563

SSM6N37FEAPE

TBTBST:Y

5%

402

1/16W

MF-LF

330K

TBTBST:Y

402

28.7K

1%

1/16W

TBTBST:Y

MF-LF

49.9K

402

1/16W

MF-LF

1%

TBTBST:Y

402

TBTBST:Y

MF-LF

200K

1%

1/16W

CRITICAL

TBTBST:Y

QFN

LT3957

TBTBST:Y

X5R-CERM

0603

10UF

20%

25V

TBTBST:Y

10UF

20%

X5R-CERM

0603

25V

41 42 70

5%

CERM

50V

402

NO STUFF

100PF

5%

50V

10PF

0402

C0G-CERM

TBTBST:Y

402

1/16W

TBTBST:Y

15.8K

1%

MF-LF

402

TBTBST:Y

137K

MF-LF

1/16W

1%

PLACE_NEAR=C3895.1:2 mm

SM

5%

TBTBST:Y

1/20W

MF

0

201

PDS540XF

TBTBST:Y

PWRDI5

CRITICAL

TBTBST:Y

33UF-0.06OHM

POLY-TANT

CASE-D3L

20%

25V

TBTBST:Y

10UF

X5R

1206-2

25V

10%

805

NO STUFF

10UF

X5R

25V

10%

50V

TBTBST:Y

X7R-CERM

0402

0.001UF

10%

402

TBTBST:Y

CERM-X5R

6.3V

0.33UF

10%

TBTBST:Y

CRITICAL

SI8409DB

BGA

SSM6N37FEAPE

SOT563

TBTBST:YTBTBST:Y

SOT563

SSM6N37FEAPE

CSP

TPS22924

CRITICAL

CERM

25V

0402

0.0047UF

10%

402

0.1UF

X5R

25V

10%

TPS22920

CRITICAL

CSP

QFN

TPS3808

CRITICAL

35

6.3V

0201

X5R

1UF

20%

50V

X7R-CERM

0402

0.0033UF

10%

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

5%

100K

MF

1/20W

201

5%

1/20W

MF

100K

201

20

35

10%

1UF

6.3V

402

CERM

NOSTUFF

SOD-VESM-HF

SSM3K15FV

35

5%

1/20W

MF

10K

201

3.3UH-6.5A

CRITICAL

TBTBST:Y

PIMB063T-SM

16V

X7R-CERM

0201

330PF

10%

1UF

6.3V

CERM

402

201

MF

1/20W

5%

0

36.5K

1/20W

MF

1%

201

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

Thunderbolt Power Support

=PP1V05_S0_P1V05TBTFET

MAKE_BASE=TRUE

TBT_CLKREQ_ISOL_L

TBTBST_SHDN_DIV

TBT_EN_LC_PWR

=TBT_RESET_L

TBT_PCIE_RESET_L

=PP3V3_TBTLC_RTR

TBTPOCRST_CT

=PP1V05_S0_P1V05TBTFET

=PP3V3_S4_TBT

=PP1V05_TBTCIO_FET

=TBT_CLKREQ_L

TBTBST_SNS2

TBTBST_FBX

TBTBST_VSNS

TBT_A_HV_EN

TBT_B_HV_EN

PP1V05_TBTLC

TBTBST_SNS1

=PPVIN_SW_TBTBST

TBTBST_PWREN_L

TBT_PWR_ON_POC_RST_L

=PP15V_TBT_REG

TBT_CLKREQ_L

TBTBST_VC_RC

TBT_SW_RESET_L

TBT_EN_CIO_PWR

=PP3V3_TBTLC_RTR

TBT_EN_CIO_PWR_L

SMC_DELAYED_PWRGD

=PP3V3_S0_PCH_GPIO

TBTPOCRST_MR_L

TBTBST_PWREN_DIV_L

TBTBST_RT

TBTBST_SS

GND_TBTBST_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVIN_SW_TBTBST

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

TBTBST_BOOST

DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm

=PP3V3_S0_P3V3TBTFET

TBTBST_VC

TBTBST_INTVCC

TBTBST_EN_UVLO

=PP3V3_S0_TBTPWRCTL

TBT_EN_LC_3V3

TBT_EN_LC_1V05

TBT_EN_LC_ISOL

=PP1V05_TBTLC_FET

=PP3V3_TBTLC_FET

U3810

C1

C2

A2

B2

A1

B1

C3800

1

2

C3810

1

2

C3815

1

2

U3800

6

5

7

3

8

4

2

9

1

R3807

1

2

R3892

1

2

R3881

1

2

R3880

1

2

C3890

1

2

C3891

1

2

C3887

1

2

C3892

1

2

C3880

1

2

Q3888

6

2

1

R3887

1

2

Q3888

3

5

4

R3888

1

2

R3894

1

2

R3893

1

2

R3891

1

2

U3890

25

31

12

13

14

15

16

17

28

1

2

10

35

36

33

6

3

4

23

24

37

32

8

9

20

21

38

34

30

27

C3860

1

2

C3861

1

2

C3889

1

2

C3888

1

2

R3896

1

2

R3895

1

2

XW3895

12

R3889

1

2

D3895

1 2

3

C3896

1

2

C3895

1

2

C3897

1

2

C3899

1

2

C3894

1

2

Q3880

2 3

1

4

Q3805

3

54

Q3805

6

21

U3815

C1

C2

A2

B2

A1

B1

C3831

1

2

C3830

1

2

U3820

D1

D2

A2

B2

C2

A1

B1

C1

U3830

3

5

4

62

7

1

C3820

1

2

C3893

1

2

Q3825

3

5

4

Q3825

6

21

R3830

1

2

R3820

1

2

C3816

1

2

Q3840

3

1

2

R3840

1

2

L3895

1 2

C3825

1

2

C3811

1

2

R3816

1

2

R3811

1 2

051-9589

4.18.0

38 OF 132

37 OF 99

8

37 99

8

35 36 37

8

37 99

35 36

8

8 9

8

35 36 37

8

17 18 19 20 25

8

IN

BI

IN

OUT

IN

OUT

IN

TP

OUT

IN

OUT

IN

OUT

BI

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0829

516S0853

USB3_EXTB_RX_P

USB3_EXTB_TX_N

USB3_EXTB_RX_N

SD_PWR_EN

USB3_EXTB_RX_RC_P

HDMI_EG_DDC_CLK

HDMI_HPD_L

HDMI_EG_DDC_DATA

PM_SLP_S4_L

PM_SLP_S3_L

=PP5V_S4_RIO

SDCONN_STATE_CHANGE_RIO

ENET_CLKREQ_L

=ENET_RESET_L

USB_EXTB_OC_L

=PP1V5_S0_RIO

=PP3V3_S3_RIO

=I2C_HDMIRDRV_SDA

=PP3V3_S4_RIO

=I2C_HDMIRDRV_SCL

HDMI_EG_CLK_C_N

HDMI_EG_DATA_C_N<2>

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

PCIE_CLK100M_ENET_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_CLK100M_ENET_P

HDMI_EG_DATA_C_P<2>

HDMI_EG_DATA_C_P<0>

HDMI_EG_DATA_C_P<1>

HDMI_EG_DATA_C_N<1>

HDMI_EG_DATA_C_N<0>

USB3_EXTB_TX_C_N

USB_EXTB_P

USB_EXTB_N

USB3_EXTB_TX_C_P

USB3_EXTB_TX_P

USB3_EXTB_RX_RC_N

HDMI_EG_CLK_C_P

RIO CONNECTOR

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

NP0-CERM 02015%

15PF

25V

GND_VOID=TRUE

201

GND_VOID=TRUE

1%

12

1/20W

MF

0201NP0-CERM5%

15PF

25V

GND_VOID=TRUE

201

GND_VOID=TRUE

1%

12

1/20W

MF

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

77

7

82 42

7

70 41 27 18

7

70 41 40 34 27 18

7

77

7

F-ST-SM

AXK732327G

25

17

7

9 7

25

7

24

7

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

SM

SIGNAL_MODEL=EMPTY

BEAD-PROBE

95 77

7

95 77

7

92 17

7

92 17

7

92 17

7

92 17

7

92 17

7

92 17

7

95 77

7

95 77

7

95 77

7

95 77

7

GND_VOID=TRUE

20525-130E-01

GND_VOID=TRUE

F-RT-SM

GND_VOID=TRUE

10%

0201

X5R-CERM

GND_VOID=TRUE

16V

0.1UF

91 19

7

91 19

7

91 19

10%

GND_VOID=TRUE

0.1UF

16V

0201

X5R-CERM

91 26

7

91 26

7

95 77

7

95 77

7

C4401

1 2

C4402

1 2

J4400

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

5

6

7

8

9

BP4401

1

BP4402

1

BP4405

1

BP4406

1

J4410

33

34

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

4

5 6

7 8

9

BP4403

1

BP4404

1

R4403

1 2

C4403

1 2

R4404

1 2

C4404

1 2

051-9589

4.18.0

44 OF 132

38 OF 99

97

8

44

8

44

97

7

97

7

97

OUT

IN

A1_P

A1_N

SEL

XSD

B0_P

B1_P

B0_N

B1_N

C0_P

C1_P

C0_N

C1_N

VDD

VSS

THRM

A0_P

A0_N

PAD

OUT

IN

OUT

IN

TP

IN

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Per PCIe spec, only TX side should have AC cap

353S3361

PCIE/SATA GUMSTICK2 CONNECTOR

514S0393

97 99

0.1UF

10V

CERM

402

20%

0.1UF

10V

CERM

402

20%

0612

0.005

MF

1W

CRITICAL

1%

9

92

9

92

9

92

9

92

10V

PLACE_NEAR=U4510.10:2 mm

CERM

402

20%

0.1UF

PLACE_NEAR=U4510.6:2 mm

16V

X7R-CERM

0402

0.01UF

20%

VQFN

CBTL02043ABQ

CRITICAL

17 91

1/20W

201

10K

MF

5%

10%

X5R-CERM

0.1UF

GND_VOID=TRUE

0201

16V

9

92

9

92

9

92

9

92

0.1UF

X5R-CERM

0201

10%

GND_VOID=TRUE

16V

5%

1/20W

MF

0

201

GND_VOID=TRUE

0

MF

1/20W

5%

201

GND_VOID=TRUE

10%

X5R-CERM

0.1UF

0201

GND_VOID=TRUE

16V

10%

0201

X5R-CERM

GND_VOID=TRUE

0.1UF

16V

X7R25V

GND_VOID=TRUE

10% 402

0.01UF

10% X7R25V

GND_VOID=TRUE

402

0.01UF

10% 25V X7R

GND_VOID=TRUE

402

0.01UF

10% 25V X7R

GND_VOID=TRUE

402

0.01UF

0.1UF

10V

CERM

402

20%

GND_VOID=TRUE

SSD-J5

CRITICAL

F-RT-SM

GND_VOID=TRUE

5%

1/20W

MF

0

GND_VOID=TRUE

201

0

MF

1/20W

5%

GND_VOID=TRUE

201

25

17

17 92

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

MF

1/20W

5%

0

201

69 70

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

5%

100K

402

SYNC_DATE=01/13/2012

SSD CONNECTOR

SYNC_MASTER=D2_KEPLER

=PP3V3_S0_SATAMUX

SATA_PCIE_SEL

SATA_SSD_D2R_P

SATA_SSD_D2R_N

SATA_HDD_D2R_P

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_P<0>

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_SSD_R2D_N

PCIE_CLK100M_SSD_N

PCIE_CLK100M_SSD_P

PCIE_SSD_R2D_N<1>

SATA_SSD_R2D_P

PCIE_SSD_R2D_P<1>

SSD_CLKREQ_L

PCIE_SSD_R2D_MUX_IN_P

SATAMUX_EN_L

=PP3V3_S0_SSD

PCIE_SSD_R2D_MUX_IN_N

SATA_SSD_D2R_MUX_OUT_P

SSD_RESET_L

SMC_OOB1_RX_L

SSD_P3V3S0_EN

=P3V3S0_EN

ISNS_SSD_N

ISNS_SSD_P

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_C_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_C_N<1>

PCIE_SSD_D2R_MUX_OUT_P

SATA_SSD_D2R_MUX_OUT_N

SATA_SSD_R2D_MUX_IN_P

PCIE_SSD_D2R_MUX_OUT_N

SMC_OOB1_TX_L

PCIE_SSD_D2R_P<0>

SATA_HDD_D2R_N

SATA_SSD_R2D_MUX_IN_N

PCIE_SSD_D2R_N<0>

MIN_LINE_WIDTH=0.6mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6mm

MIN_NECK_WIDTH=0.25mm

PP3V3_S0_SSD_FLT

PLACE_NEAR=J4501.9:3mm

CRITICAL

0603

FERR-26-OHM-6A

MIN_NECK_WIDTH=0.25mm

PP3V3_S0_SSD_R

MF-LF

1/16W

C4502

1

2

C4501

1

2

R4599

2 1

4 3

C4514

1

2

C4519

1

2

U4510

4

3

8

7

18

19

16

17

14

15

12

13

9

21

1

6

10

5

11

20

2

R4510

1

2

C4521

1 2

C4520

1 2

R4518

1 2

R4517

1 2

C4513

1 2

C4512

1 2

C4516

1 2

C4515

1 2

C4511

1 2

C4510

1 2

C4505

1

2

J4501

27

28

29

30

31

32

33

34

35

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

3

4

5

6

7

8

9

R4526

1 2

R4525

1 2

BP4501

1

BP4502

1

R4520

1 2

L4500

BP4503

1

R4505

1

2

051-9589

4.18.0

45 OF 132

39 OF 99

8

91

92

91

92

8

92

91

92

92 92

91

92

91

OUT

IN

SHLD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

STDA_SSRX-

GND_DRAIN

SHLD

GND

VBUS

D-

D+

SYM_VER-1

BI

IN

OUT

IN

OUT

IO

NC

GND

VBUS

NC

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GND

THRM

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

USB Port Power Switch

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

USB/SMC Debug Mux

SEL=1 Choose USB

SEL=0 Choose SMC

Place L4605 and L4615 at connector pin

We can add protection to 5V if we want, but leaving NC for now

514-0804

Left USB Port A

19 91

0603

CRITICAL

FERR-120-OHM-3A

16V

0201

X5R-CERM

0.1UF

10%

16V

GND_VOID=TRUE

0.1UF

0201

X5R-CERM

10%

USB3.0-J5

F-RT-TH

CRITICAL

BEAD-PROBE

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

ESD0P2RF-02LS

TSSLP-2-1

CRITICALCRITICAL

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

CRITICALCRITICAL

TSSLP-2-1

ESD0P2RF-02LS

25V

15PF

5% 0201NP0-CERM

GND_VOID=TRUE

12

1/20W

MF

201

1%

GND_VOID=TRUE

25V

15PF

NP0-CERM 02015%

GND_VOID=TRUE

12

1/20W

MF

201

1%

201

SMC_DEBUG_NO

0

5%

1/20W

MF

1/20W

5%

0

SMC_DEBUG_NO

201

20%

CRITICAL

6.3V

220UF-35MOHM

CASE-B2-SM1

POLY-TANT

402

22.1K

1%

1/16W

MF-LF

201

22.1K

1%

1/20W

MF

20%

603

10UF

6.3V

X5R

20%

CERM

0.1UF

10V

402

19 91

20%

CERM

0.1UF

SMC_DEBUG_YES

10V

402

SMC_DEBUG_YES

10K

1/16W

MF-LF

5%

402

41 42

41

20%

0.01UF

0402

16V

24

RCLAMP0502N

SLP1210N6

CRITICAL

X5R

603

20%

6.3V

10UF

5%

MF-LF

1/16W

5.1K

402

10V

X5R

0402

0.47UF

10%

CRITICAL

PI3USB102ZLE

SMC_DEBUG_YES

TQFN

SON

CRITICAL

TPS2557DRB

SYNC_DATE=01/13/2012

USB 3.0 CONNECTORS

SYNC_MASTER=D2_KEPLER

USB_EXTA_MUXED_N

USB_EXTA_MUXED_P

PM_SLP_S4_L

SMC_DEBUGPRT_RX_L

SMC_DEBUGPRT_EN_L

SMC_DEBUGPRT_TX_L

=PP3V42_G3H_SMCUSBMUX

USB_EXTA_N

USB_EXTA_P

NO_TEST=TRUE

USB3_EXTA_RX_P

NO_TEST=TRUE

USB3_EXTA_RX_N

USB3_EXTA_RX_RC_N

NO_TEST=TRUE

USB3_EXTA_TX_C_P

NO_TEST=TRUE

USB3_EXTA_TX_C_N

NO_TEST=TRUE

PP5V_S3_LTUSB_A_ILIM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

NO_TEST=TRUE

USB3_EXTA_TX_P

NO_TEST=TRUE

USB3_EXTA_TX_N

VOLTAGE=5V

PP5V_S3_LTUSB_A_F

MIN_NECK_WIDTH=0.25 mm

USB3_EXTA_RX_RC_P

NO_TEST=TRUE

USB_EXTA_OC_L

USB_ILIM_R

USB_ILIM

=PP5V_S3_LTUSB

USB_PWR_EN

GND_VOID=TRUE

USB_LT1_P

USB_LT1_N

X7R-CERM

MIN_LINE_WIDTH=0.5 mm

TCM0605-1

90-OHM-50MA

CRITICAL

SIGNAL_MODEL=EMPTY

L4605

1 2

C4696

1

2

C4695

1

2

C4691

1

2

C4650

1

2

R4650

1

2

C4605

1

2

D4600

1

5 4

6

C4690

1

2

R4690

1

2

C4692

1

2

U4650

6

7

3

4

5

8

10

9

2

1

U4600

4

8

1

5

2

3

6

7

9

C4611

1 2

C4610

1 2

J4600

2

3

4

7

14

15

16

17

18

10

11

12

13

5

6

8

9

1

L4600

1

2 3

4

BP4605

1

BP4602

1

BP4607

1

BP4604

1

BP4606

1

BP4608

1

D4611

1

2

D4610

1

2

D4613

1

2

D4612

1

2

C4612

1 2

R4612

1 2

C4613

1 2

R4613

1 2

R4651

1 2

R4652

1 2

R4600

1

2

R4601

1

2

051-9589

4.18.0

46 OF 132

40 OF 99

2 3

91

7

18 27 34 38 41 70

91

8

97

8

LPC0AD3

LPC0CLK

LPC0FRAME*

LPC0AD1

LPC0AD2

AIN08

AIN07

LPC0CLKRUN*

LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX

PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119

PP4/IRQ120

C0-

WT2CCP0/PH0

WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2

SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127

PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4

PF5

T1CCP0/PJ0

T2CCP0/PJ2

T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK

SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI

IN

BI

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

OUT

NC

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

IN

NC

OUT

IN

OUT

BI

IN

BI

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(OD)

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

(OD)

If SMS interrupt is not used, pull up to SMC rail.

(OD)

pins designed as outputs can be left floating,

LM4FSXAH5BB

BGA

OMIT_TABLE

BGA

LM4FSXAH5BB

OMIT_TABLE

PLACE_NEAR=U4900.A1:4MM

SM

7

42 43 61

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

42

201

MF

5%

1/20W

1M

20%

402

10V

CERM

0.1UF

402

CERM

0.1UF

10V

20%

402

10V

0.1UF

CERM

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

20%

402

10V

CERM

0.1UF

7

17 43 82 92

7

17 43 82 92

7

17 43 82 92

7

17 43 82 92

25 92

7

17 43 82 92

25

7

17 43

7

18 43

7

18 25 43

20

44 94

7

44 94

7

44 94

42

7

44

7

44

42

42 70

18

37 42 70

42

40 42

42

40

42 78

24 70

42

18 24

18 25

20%

402

10V

CERM

0.1UF

20

42

7

42 43

7

42 43

9

91

9

91

48

50

48

42

42 49

42 51

42 60

42

7

18 27 38 70

7

18 27 34 38 40 70

18 70

42 49

42

42 70

7

34 42

42

70

25 42

30-OHM-1.7A

0402

11 42 65 89

39

42

39 42

10%

1UF

402

X5R

25V

10%

1UF

402

X5R

25V

NO STUFF

10%

1UF

402

X5R

25V

60

18 24 70

42

11 89

42

8

18 42 70

42

60

78

10%

0.01UF

0201

X5R-CERM

10V

402

10%

1UF

CERM

6.3V

20%

10V

X5R-CERM

1UF

0603-1

SMC

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.25 MM

PP1V2_S5_SMC_VDDC

SMBUS_SMC_0_S0_SCL

SMC_PROCHOT

SMC_ADC23

SMC_ADC22

SMC_ADC14

SMC_ADC15

SMC_ADC16

SMC_ADC17

SPI_SMC_MISO

SMC_WAKE_SCI_L

SMC_RUNTIME_SCI_L

SMBUS_SMC_0_S0_SDA

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

SMC_FAN_0_CTL

SMC_XTAL

SMC_TCK

SMC_GFX_THROTTLE_L

CPU_PROCHOT_L

SMC_VCCIO_CPU_DIV2

SMC_S5_PWRGD_VIN

SMC_DELAYED_PWRGD

SMC_DEBUGPRT_RX_L

SMC_PM_G2_EN

CPU_THRMTRIP_3V3

SPI_SMC_MOSI

SPI_DESCRIPTOR_OVERRIDE_L

CPU_CATERR_L

SMC_SYS_LED

S5_PWRGD

SMC_OOB1_TX_L

CPU_PECI_R

SMC_ODD_DETECT

SMC_PME_S4_WAKE_L

SMC_DP_HPD_L

SMC_BIL_BUTTON_L

SMC_PECI_L

SMC_PME_S4_DARK_L

SMC_S4_WAKESRC_EN

SMC_LID

PM_SLP_S3_L

SMC_TX_L

SMC_RX_L

SMC_ONOFF_L

PM_SLP_S5_L

PM_SLP_S4_L

SYS_ONEWIRE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_3_SCL

TP_SMC_MPM5_LED_PWR

TP_SMC_MPM5_LED_CHG

SMC_FAN_1_TACH

SMC_FAN_1_CTL

SMC_ADC13

SMC_ADC8

SYS_TDM_ONEWIRE

SMC_SYS_KBDLED

SMC_T25_EN_L

SMS_INT_L

USB_SMC_P

SMC_THRMTRIP

SMC_ADC7

SMC_ADC9

SMC_ADC11

SMC_ADC6

SMC_ADC10

SMC_ADC12

PM_CLKRUN_L

SMC_ADC1

SMC_ADC0

SMC_ADC3

SMC_ADC5

SMC_ADC2

SMC_ADC4

SMC_BC_ACOK

SMC_ADC18

SMC_ADC20

SMC_ADC19

SMC_ADC21

LPC_PWRDWN_L

HISIDE_ISENSE_OC

PM_PWRBTN_L

ENET_ASF_GPIO

SMBUS_SMC_3_SDA

USB_SMC_N

SMBUS_SMC_4_ASF_SDA

G3_POWERON_L

SMBUS_SMC_5_G3_SCL

IR_RX_OUT_RC

SMC_TMS

SMC_TDO

SMC_TDI

SMC_RESET_L

WIFI_EVENT_L

NC_SMC_HIB_L

SMC_EXTAL

SMC_WAKE_L

NC_SMC_XOSC1

SMC_DEBUGPRT_TX_L

PM_DSW_PWRGD

SMC_GFX_OVERTEMP

ALL_SYS_PWRGD

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.25 MM

PP3V3_S5_SMC_VDDA

SMC_CLK32K

=PP3V3_S5_SMC

SMC_LRESET_L

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_S3_SDA

SMC_FAN_0_TACH

SPI_SMC_CLK

SMC_DEBUGPRT_EN_L

PM_PCH_SYS_PWROK

SPI_SMC_CS_L

SMC_ADAPTER_EN

MEM_EVENT_L

PM_SYSRST_L

SMC_OOB1_RX_L

BDV_BKL_PWM

SMC_BATLOW_L

LPC_SERIRQ

LPC_CLK33M_SMC

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

LPC_FRAME_L

U4900

E2

E1

F2

F1

B3

A3

B4

A4

B5

A5

B6

A6

C1

C2

B1

B2

G2

G1

H1

H2

B7

A7

B8

A8

K2

K1

L2

E10

D13

M4

N2

N8

M8

L8

K8

N7

M7

N4

N3

B13

A13

C12

D11

H12

G11

D12

F13

C13

F12

H13

L1

C4

C6

L9

K9

J4

J2

B12

C11

A12

H11

L13

G3

D10

L11

N12

N11

M11

M13

L12

M5

J12

J13

L5

D8

K6

D4

E4

F5

N5

N6

K5

M6

L6

M2

M3

L4

N1

L10

K10

M9

N9

F4

F3

C9

B9

A9

C8

D5

C5

L3

M1

F11

E11

E13

E12

K7

L7

K3

K4

J3

H4

H3

G4

H10

U4900

A1

C7

K11

D9

E5

F9

H5

H9

J5

J8

J11

C3

E3

M12

G12

G13

B11

G10 C10

A10

A11

B10

K12

D7

E6

E8

E9

F10

J7

J9

J10

D3

J1

J6

K13

D6

D1

D2

N13

M10

N10

XW4900

12

C4914

1

2

C4915

1

2

C4916

1

2

C4917

1

2

C4913

1

2

R4902

1

2

C4906

1

2

C4905

1

2

C4909

1

2

C4908

1

2

C4904

1

2

C4903

1

2

C4907

1

2

C4901

1

2

L4901

1 2

C4911

1

2

C4910

1

2

C4912

1

2

C4920

1

2

C4921

1

2

C4902

1

2

051-9589

4.18.0

49 OF 132

41 OF 99

A2

42

42 45 46 99

7

42 42

7

42 43

42

7

42 43

7

42 43

7

42 43

7

42

7

8

42 78

D

S G

IN

OUT

BI

IN

D

S G

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

IN

OUT

IN

OUT

IN

D

GS

OUT

NCNC

NC NC

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

BI

D

S G

OUT

IN

D

G S

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC12 SPI SUPPORT

APN: 998-3029

Hall Effect pads

SMC Crystal Circuit

To SMC

From SMC

ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD

Internal 20K pull-up on PM_BATLOW_L in PCH.

SMC12 PECI SUPPORT

From/To CPU/PCH

ENG PACKAGE REQUIRES 1.2V ON SMC_ADC23 PIN

HDMI HPD ESD PROTECTION

Inversion now taking place on RIO

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

BATLOW# ISOLATION

1K for ESD protection

(IPU)

MR1* and MR2* must both be low to cause manual reset.

NOTE: Internal pull-ups are to VIN, not V+.

Mac Mini: 5V

SMC Reset "Button", Supervisor & AVREF Supply

Used on mobiles to support SMC reset via keyboard.

Debug Power "Buttons"

Mobiles: 3.42V

SSM6N15FEAPE

SOT563

10K

1/20W

201

MF5%

1/20W

201

100K

MF5%

201

1/20W

MF

10K

5%

201

MF

1/20W

100K

5%

1/20W

201

10K

MF5%

MF

201

1/20W

10K

5%

10K

1/20W

MF

201

5%

10K

1/20W

MF

201

5%

10K

MF

1/20W

201

5%

41 42

20

SILK_PART=PWR_BTN

MF-LF

603

0

1/10W

OMIT

5%

PLACE_SIDE=BOTTOM

11 41 65 89

41

SSM6N15FEAPE

SOT563

10K

MF

201

1/20W

5%

10K

1/20W

MF

201

5%

201

1/20W

MF

470K

5%

201

1/20W

MF

10K

5%

10K

MF

201

1/20W

5%

0

603

OMIT

MF-LF

1/10W

5%

PLACE_SIDE=TOP

SILK_PART=PWR_BTN

1/10W

OMIT

0

SILK_PART=SMC_RST

603

MF-LF

5%

PLACEMENT_NOTE=Place R5001 on BOTTOM side

41 42 49

49

X7R-CERM

16V

0402

0.01UF

10%

VREF-3.3V-VDET-3.0V

CRITICAL

DFN

20%

X5R

603

10uF

6.3V

16V

X7R-CERM

0402

0.01UF

10%

7

41 43 61

18

1/20W

PLACE_NEAR=U1800.N14:5.1mm

22

201

MF

5%

41

MF

201

1/20W

100K

5%

49 41

MF

100K

1/20W

201

5%

41 70

SSM3K15FV

SOD-VESM-HF

18

201

MF

100K

1/20W

5%

0

1/16W

MF-LF

402

5%

NOSTUFF

41

OMIT_TABLE

HALL-SENSOR-MLB-PADS-K99

SM

10%

0.001UF

0402

X7R-CERM

50V

MF-LF

0

1/16W

402

5%

MF-LF

0

1/16W

SMC_PACKAGE:ENG

402

5%

201

MF

10K

1/20W

5%

201

100K

1/20W

MF5%

MF

10K

201

1/20W

5%

201

1K

5%

1/20W

MF

201

MF

1/20W

100K

5%

330

1/16W

MF-LF

402

5%

OMIT

NOSTUFF

NONE

402

5%

1/16W

MF-LF

0

41

1/20W

MF

100K

201

NO STUFF

5%

SMC_PACKAGE:PROD

1/16W

MF-LF

0

402

5%

99

43 52 41

100K

201

MF

1/20W

1%

1/20W

MF

201

100K

1/20W

MF

100K

201

5%

7

38 82

41 42

11 20 89

MF

1/20W

100K

201

5%

10K

MF

1/20W

201

NOSTUFF

5%

MMBT3904LP-7

DFN1006-3

CRITICAL

MF-LF

1/16W

43

402

5%

41 11 20 89

SSM6N15FEAPE

SOT563

41 42 49

41 78

201

3.3K

1/20W

MF

5%

MF

100K

1/20W

201

5%

201

MF

1/20W

1K

5%

34

100K

1/20W

201

MF5%

100K

1/20W

201

MF5%

VESM

CRITICAL

SSM3K15AMFVAPE

50V

0402

12PF

5%

C0G-CERM

50V

C0G-CERM

0402

12PF

5%

1%

2.49K

201

MF

1/20W

MF-LF

402

1/16W

33

PLACE_NEAR=U6100.5:1MM

5%

MF-LF

1/16W

33

PLACE_NEAR=U6100.6:1MM

402

5%

MF-LF

1/16W

33

PLACE_NEAR=U6100.1:1MM

402

5%

402

12

5%

1/16W

MF-LF

12.000MHZ-30PPM-10PF

CRITICAL

3.2X2.5MM-SM-1

NP0-C0G

25V

5%

1000PF

NOSTUFF

402

201

1/20W

5%

0

MF

CERM-X5R

402

0.47UF

10%

6.3V

402

4.7UF

20%

6.3V

X5R

402

5%

100K

1/16W

MF-LF

402

47

5%

1/16W

MF-LF

SYNC_DATE=01/13/2012

SMC Support

SYNC_MASTER=D2_KEPLER

SUBASSY,PCBA HALL EFFECT,K99

CRITICAL1 J5050607-6811

=PP3V3_S5_SMC

PP3V42_G3H_SMC_SPVSR

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.1 mm

VOLTAGE=3.42V

GND_SMC_AVSS

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0V

=PPVIN_S5_SMCVREF

SMC_RESET_L

SMC_ADC16

SMC_ADC18

SMC_ADC19

SMC_ADC12

SMC_GPU_CORE_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_RST_L

SMC_ONOFF_L

SMC_MANUAL_RST_L

SMC_ADC3

SMC_ADC0

MAKE_BASE=TRUE

SMC_PCH_CORE_ISENSE

SMC_PECI_L

SPI_MLB_MISOSPI_SMC_MISO

PM_THRMTRIP_L_R

CPU_PROCHOT_L

SMC_EXTAL

SMC_XTAL_R

MAKE_BASE=TRUE

SMC_GPU_CORE_VSENSE

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_CHGR_BMON_ISENSE

NC_SMC_ODD_DETECT

MAKE_BASE=TRUE

NC_ENET_ASF_GPIO

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

NC_IR_RX_OUT_RC

NC_MEM_EVENT_L

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

SMC_GFX_VSENSE

MAKE_BASE=TRUE

SMC_CPU_SA_ISENSE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_CPU_GFX_ISENSE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

SMC_LCDBKLT_VSENSE

SMC_TBT_ISENSE_R

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_P1V5MEM_ISENSE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

SMC_GPU_P1V35_ISENSE

MAKE_BASE=TRUE

SMC_CPU_SA_VSENSE

SMC_X29_ISENSE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_BDV_BKL_PWM

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_DEBUGPRT_TX_L

SPI_SMC_CS_L SPI_MLB_CS_L

SPI_SMC_CLK SPI_MLB_CLK

SPI_SMC_MOSI SPI_MLB_MOSI

SMC_PME_S4_DARK_L

SMC_OOB1_TX_L

SMC_TMS

SMC_TDO

SPI_DESCRIPTOR_OVERRIDE_L

PM_THRMTRIP_L

=TBT_WAKE_L

=PSOC_WAKE_L

SMC_CLK32K

SMC_ONOFF_L

SMC_PECI_L_R

CPU_PECI_R

=PPVCCIO_S0_SMC

CPU_PECI

SMC_ADC1

SMC_ADC5

SMC_ADC6

SMC_ADC7

SMC_ADC10

SMC_ADC11

SMC_LID

SMC_LID_R

SMC_ADC21

SMC_ADC23

SMC_ADC22

SMC_ADC23

SMC_ADC8

SMC_ADC9

SDCONN_STATE_CHANGE_SMC

BDV_BKL_PWM

SMC_GFX_OVERTEMP

SMC_BIL_BUTTON_L

SMC_BC_ACOK

PM_THRMTRIP_B_L

SMBUS_SMC_4_ASF_SCL

CPU_THRMTRIP_3V3

=PPVCCIO_S0_SMC

=PP3V3_S4_SMC

MEM_EVENT_L

SMC_ADC15

SMC_TX_L

SMC_RX_L

CPU_THRMTRIP_3V3

SMS_INT_L

SMC_S5_PWRGD_VIN

SMC_TCK

SMC_TDI

SMC_LID

SMC_ONOFF_L

=CHGR_ACOK

SMC_ADC14

SMC_ADC20

IR_RX_OUT_RC

SMC_ODD_DETECT

SMC_ADC13

SMC_ADC17

=PP3V3_S5_SMCBATLOW

HISIDE_ISENSE_OC

SMC_ADC4

ENET_ASF_GPIO

SMC_SYS_LED

SMC_BATLOW_L

PP1V2_S5_SMC_VDDC

SMC_ADC2

SMC_PROCHOT

SMC_TBT_ISENSE

G3_POWERON_L

SMC_DEBUGPRT_RX_L

=PP3V3_S4_SMC

PM_CLK32K_SUSCLK_R

=BT_WAKE_L

=PP3V3_S4_SMC

HDMI_HPD_L

SMC_DP_HPD_L

=PP3V42_S3_HALL

=PP3V3_SUS_SMC

PP3V3_WLAN

WIFI_EVENT_L

SMC_ADAPTER_EN

SMC_ROMBOOT

SMC_PM_G2_EN

SMC_S4_WAKESRC_EN

SMC_DELAYED_PWRGD

PM_BATLOW_L

SMBUS_SMC_4_ASF_SDA

SMC_VCCIO_CPU_DIV2

SMC_XTAL

SMC_THRMTRIP

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

SMC_RESET_R_L

Q5059

3

5

4

R5070

1 2

R5071

1 2

R5073

1 2

R5074

1 2

R5077

1 2

R5078

1 2

R5079

1 2

R5080

1 2

R5085

1 2

R5015

1

2

Q5059

6

2

1

R5089

1 2

R5081

1 2

R5087

1 2

R5093

1 2

R5072

1 2

R5016

1

2

R5001

1

2

C5001

1

2

U5010

4

2

6

7

8

5

9

1

3

C5025

1

2

C5026

1

2

R5012

1 2

R5090

1 2

R5082

1

2

Q5040

3

1

2

R5040

1

2

R5041

1 2

J5050

1

2

3

4 5

6

7

8

C5050

1

2

R5050

1 2

R5099

1

2

R5075

1 2

R5076

1 2

R5086

1 2

R5088

1

2

R5069

1 2

R5031

1

2

R5033

1

2

R5032

1 2

R5068

1 2

R5013

1 2

R5097

1

2

R5096

1

2

R5092

1 2

R5094

1 2

R5095

1 2

Q5058

1

3

2

R5034

1 2

Q5057

3

5

4

R5058

1 2

R5059

1

2

R5057

1 2

R5098

1 2

R5091

1 2

Q5030

3

12

C5011

1

2

C5010

1

2

R5010

1 2

R5022

1 2

R5023

1 2

R5024

1 2

R5021

1 2

Y5010

2 4

1 3

C5028

1

2

R5028

1 2

C5020

1

2

C5027

1

2

R5000

1

2

R5027

1 2

051-9589

4.18.0

50 OF 132

42 OF 99

8

41 42 78

41 45 46 99

8

41

45

41

99

41

45

41 42

46

7

99

45

46

45

41 42 60

99

46

7

99

46

45

7

99

7

46

45

8

41 42 78

40 41

41 42

39 41

7

41 43

7

41 43

25 41

18 35

8

42

41

41 42 49

7

41

41 42

41

41 42

41

25

41

41 42 60

41

8

42

8

25 42

41

7

41 43

7

41 43

41 42

41 51

41

7

41 43

7

41 43

41 42 49

45 61

41

8

41

40 41

8

25 42

8

25 42

8

7

34

7

34 41

18 41 70

7

43

41 70

37 41 70

41

41 42

7

41

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

BI

IN

BI

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SPI Bus Series Termination

LPC+SPI Connector

516S0573

42 52

PLACE_NEAR=U1800.AY1:5mm

15

402

MF-LF

5%

1/16W

17 92

7

41 42

7

41 42

CRITICAL

M-ST-SM

LPCPLUS_CONN:YES

55909-0374

7

20

7

41 42

7

42

7

41 42 61

7

41 42

7

41 42

7

25

7

43

7

17 41 82 92

7

18 41

7

43

7

17 41 82 92

7

17 41 82 92

7

41 42

7

18 25 41

7

17 41

7

43

7

43

7

20 52

7

17 41 82 92

7

17 41 82 92

7

25 92

PLACE_NEAR=J5100.12:5mm

LPCPLUS_R:YES

33

5%

1/16W

MF-LF

402

PLACE_NEAR=R5126.2:5mm

5%

MF-LF

1/16W

33

402

LPCPLUS_R:YES

33

5%

1/16W

MF-LF

PLACE_NEAR=J5100.14:5mm

402

5%

MF-LF

1/16W

33

PLACE_NEAR=R5125.2:5mm

402

MF-LF

1/16W

5%

12

LPCPLUS_R:YES

402

PLACE_NEAR=J5100.11:5mm

MF-LF

1/16W

1%

60.4

PLACE_NEAR=U6100.2:5mm

402

LPCPLUS_R:YES

33

5%

1/16W

MF-LF

402

PLACE_NEAR=J5100.9:5mm

5%

MF-LF

1/16W

33

PLACE_NEAR=R5127.2:5mm

402

42 52

5%

1/16W

MF-LF

15

402

PLACE_NEAR=U1800.AV3:5mm

17 92

42 52

15

402

MF-LF

5%

1/16W

PLACE_NEAR=U1800.BA2:5mm

17 92

42 52 17 92

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

LPC+SPI Debug Connector

SPI_MOSI SPI_MLB_MOSI

SPI_MISO SPI_MLB_MISO

SPI_ALT_MISO

SPI_CS0_L

SPI_MLB_CS_L

SPI_CLK

SPI_MLB_CLK

=PP5V_S0_LPCPLUS

SMC_TX_L

LPC_SERIRQ

SMC_TDI

SMC_TCK

LPC_AD<1>

SPI_ALT_MOSI

LPCPLUS_RESET_L

SMC_TMS

LPC_FRAME_L

SPI_ALT_MISO

LPC_AD<0>

LPC_AD<3>

LPC_AD<2>

LPC_CLK33M_LPCPLUS

SPI_CLK_R

SPI_CS0_R_L

SPI_MOSI_R

SPI_ALT_CLK

SPI_ALT_CS_L

PM_CLKRUN_L

TP_SMC_TRST_L

SMC_RESET_L

=PP3V3_S5_LPCPLUS

SMC_RX_L

SMC_ROMBOOT

SPI_ALT_CS_L

SPI_ALT_CLK

SPI_ALT_MOSI

TP_SMC_MD1

SMC_TDO

LPC_PWRDWN_L

LPCPLUS_GPIO

SPIROM_USE_MLB

R5110

1 2

R5111

1 2

R5112

1 2

J5100

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

4

56

78

9

R5126

1

2

R5121

1 2

R5125

1

2

R5120

1 2

R5128

1

2

R5123

1 2

R5127

1

2

R5122

1 2

051-9589

4.18.0

51 OF 132

43 OF 99

92

7

43

92

8

7

8

7

43

7

43

7

43

7

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Write: 0x9E Read: 0x9F)

VBIOS may overwrite as 0x82/0x83

GK107: U8000

(Write: 0x98 Read: 0x99)

EMC1414-A: U5550

GPU Temp (Ext)

(MASTER)

Panther Point

XDP Connectors

(Write: 0x30 Read: 0x31)

Margin Control

Panther Point

(WRITE: 0x58 READ: 0x59)

LED BACKLIGHT SMBUS CONNECTION

(WRITE: 0XD0 READ: 0XD1)

J6950

(Write: 0x16 Read: 0x17)

(WRITE: 0xCC READ: 0xCD)

J4410 -> U9700

(Write: 0x10 Read: 0x11)

SMC "2" SMBUS CONNECTIONS

SMC "1" SMBUS CONNECTIONS

PCH "SMLink 0" Connections

access PCH & CPU via PECI.

(MASTER)

DEBUG SENSOR ADC A

(MASTER)

X29 TEMP

TMP105: U5523

(WRITE: 0X92 READ: 0X93)

(MASTER)

U4900

The bus formerly known as "Battery B"

GYRO

U5940

U5920

SMC

ALS

U4900

SMC

SMLink 1 is slave port to

U1800

(Write: 0x88 Read: 0x89)

U1800

(MASTER)

U1800

U3300

SMC

(MASTER)

U4900

(Write: 0x12 Read: 0x13)

ISL6258 - U7000

Battery

Battery Charger

SMC

(MASTER)

SMC "5" SMBUS CONNECTIONS

UD100

U3301

SMC

J3502

(Write: 0x90 Read: 0x91)

SMS

(WRITE: 0X30/31 READ: 0X32/33)

U4900

Trackpad

CPU/DDR3/PCH/AIRFLOW TEMP

EMC1414-A: U5570

GPU Temp (Int)

J5800

(Write: 0x72 Read: 0x73)

U9100

(MASTER)

LED BACKLIGHT

U9700

DPMUX IC

HDMI REDRIVER SMBUS CONNECTION

U9100

(MASTER)

HDMI Redriver (on RIO)

(Write: 0x98 Read: 0x99)

VRef DACs

U4900

PCH "SMLink 1" Connections

PCH SMBus "0" Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "3" SMBUS CONNECTIONS

DPMUX IC

(Write: 0x98 Read: 0x99)

SMC "0" SMBus Connections

U3600

TBT

(WRITE: 0xFE READ: 0xFF)

J2500 & J2550

(MASTER)

Audio

Mikey (WRITE: 0X72 READ: 0X73)

U6751 & U6750

China HS (WRITE: 0X76 READ: 0X77)

MF-LF

1/16W

402

5%

4.7K

402

MF-LF

1/16W

5%

4.7K

402

2.0K

MF-LF

1/16W

5%

402

MF-LF

5%

2.0K

1/16W

402

1K

MF-LF

1/16W

5% 5%

1K

402

MF-LF

1/16W

5%

4.7K

MF-LF

1/16W

402

4.7K

1/16W

5%

402

MF-LF

8.2K

5%

402

MF-LF

1/16W

5%

MF-LF

1/16W

8.2K

402

NO STUFF

402

8.2K

5%

1/16W

MF-LF

NO STUFF

8.2K

5%

402

MF-LF

1/16W

MF-LF

5%

0

402

1/16W

402

MF-LF

0

5%

1/16W

402

5%

1/16W

MF-LF

1K

402

MF-LF

1/16W

5%

1K

4.7K

5%

MF-LF

402

1/16W1/16W

402

4.7K

MF-LF

5%

1K

5%

1/16W

MF-LF

402

5%

1K

MF-LF

402

1/16W

201

4.7K

5%

1/20W

MF

201

4.7K

5%

1/20W

MF

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

SMBus Connections

=I2C_MIKEY_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

=I2C_TBTRTR_SCL

=SMBUS_GPUTHMSNS_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

SML_PCH_1_CLK

MAKE_BASE=TRUE

SML_PCH_0_DATA

SML_PCH_0_CLK

MAKE_BASE=TRUE

SML_PCH_1_DATA

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

I2C_DPMUX_UC_SCL

MAKE_BASE=TRUE

I2C_DPMUX_UC_SDA

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

I2C_DPMUX_A_SCL

MAKE_BASE=TRUE

I2C_DPMUX_A_SDA

MAKE_BASE=TRUE

=PP3V3_S0_DPMUXI2C

=I2C_DPMUX_A_SDA

=I2C_DPMUX_A_SCL

=I2C_SMC_SMS_SDA

=PP3V3_S0_SMBUS_SMC_1_S0

=I2C_TBTRTR_SDA

SMB_0_S0_DATA

=I2C_HDMIRDRV_SDA

=I2C_HDMIRDRV_SCL

=I2C_DPMUX_UC_SCL

=PP3V3_S0_DPMUXI2C

=I2C_DPMUX_UC_SDA

=I2C_CPUTHMSNS_SDA

=I2C_BKL_1_SCL

=I2C_BKL_1_SDA

=I2C_ALS_SDA

SMB_3_DATA

SMB_3_CLK

=I2C_SMC_GYRO_SDA

=PP3V42_G3H_SMBUS_SMC_5

=I2C_SMC_ADCS_SDA

GPU_SMB_CLK_R

=I2C_TPAD_SDASMB_2_S3_DATA

SMB_2_S3_CLK

SMB_0_S0_CLK

=I2C_TPAD_SCL

GPU_SMB_DAT_R

=I2C_PCA9557D_SDA

SMB_5_CLK

SMB_5_DATA

=SMBUS_CHGR_SDA

=SMBUS_CHGR_SCL

=SMBUS_XDP_SCL

=I2C_SMC_SMS_SCL

=I2C_ALS_SCL

SMB_1_S0_DATA

SMB_1_S0_CLK

=I2C_X29THMSNS_SCL

=I2C_CPUTHMSNS_SCL

=I2C_X29THMSNS_SDA

=I2C_SMC_ADCS_SCL

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

=PP3V3_S0_SMBUS_PCH

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=PP3V3_S0_SMBUS_PCH

=PP3V3_S3_SMBUS_SMC_2_S3

=SMBUS_GPUTHMSNS_SCL

=PP3V3_S3_SMBUS_SMC_3

=SMBUS_XDP_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

=I2C_SMC_GYRO_SCL

=PP3V3_S0_SMBUS_PCH

=I2C_PCA9557D_SCL

=I2C_MIKEY_SDA

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_0_S0

R5291

1

2

R5290

1

2

R5280

1

2

R5281

1

2

R5270

1

2

R5271

1

2

R5251

1

2

R5250

1

2

R5210

1

2

R5211

1

2

R5221

1

2

R5220

1

2

R5223

1 2

R5222

1 2

R5201

1

2

R5200

1

2

R5235

1

2

R5234

1

2

R5261

1

2

R5260

1

2

R5236

1

2

R5237

1

2

051-9589

4.18.0

52 OF 132

44 OF 99

58

17 92

35

47

17 92

41

94

41

94

7

8

44

82

51

8

35

38

82

8

44

82

47

86

34

51

8

98

78

49

78

33

61

24

51

34

47

98

60

8

44

33

8

44

8

47

8

24

41

94

41

94

51

8

44

33

58

17 92

41

94

41

94

8

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

V+

V-

THRM

OUT

IN

V+

V-

THRM

OUT

V+

V-

THRM

IN

OUT

V+

V-

THRM

IN

OUT

NC

NC NC

NC

NC NC

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Divider set for Vin max of 22.32V

RTHEVENIN = 4567 Ohms

CPU Vcore Voltage Sense / Filter

Vimon=3x50A*(0.2/R8915)*R8912=1V

Vi=Voltage across R7640=0.02139V

EDP:21.329A

EDP:50A

Gain: 154x

SMC Key IC1C

SMC_ADC14

SMC KEY VG0C

GPU Vcore Voltage Sense / Filter

DDR3 1.5V DRAM ONLY CURRENT SENSE / FILTER

SMC Key VC0C

GFX Vcore Voltage Sense / Filter

EDP CURRENT:8A

SMC_ADC12

SMC Key VN0C

SMC_ADC0

SMC KEY VD0R

SMC_ADC3

PBUS Voltage Sense Enable & Filter

SMC_ADC11

SMC Key IC2C

SMC_ADC5

SMC Key VP0R

EDP:6A

Enables PBUS VSense

GAIN:549X

Gain: 182x

GAIN:136.6X

SMC Key IG0C

SMC_ADC13

SMC_ADC15

GPU VCore Load Side Current Sense / Filter

Vi=Voltage across R7140=0.006V

DC-In Voltage Sense Enable & Filter

divider when AC present.

Enables DC-In VSense

divider when SUS present.

divider when in S0.

SMC_ADC10

SMC KEY IM0C

Gain: 3.004x

CPU 1.05V VCCIO Current Sense / Filter

RTHEVENIN = 4573 Ohms

CPU SA Current Sense / Filter

42

20%

PLACE_NEAR=U4900.N12:5MM

6.3V

X5R

402

0.22UF

PLACE_NEAR=U4900.N12:5MM

1%

1/16W

402

4.53K

MF-LF

70

MF-LF

402

1/16W

100K

1%

100K

1%

1/16W

MF-LF

402

42

0.22UF

6.3V

20%

X5R

402

PLACE_NEAR=U4900.L8:5MM

27.4K

PLACE_NEAR=U4900.L8:5MM

1/16W

402

MF-LF

1%

1/16W

PLACE_NEAR=U4900.L8:5MM

402

5.49K

1%

MF-LF

SOT-963

NTUD3169CZ

CRITICAL

42

1/16W

1%

MF-LF

402

100K

CRITICAL

SOT-963

NTUD3169CZ

PLACE_NEAR=U4900.N9:5MM

0.22UF

20%

X5R

6.3V

402

MF-LF

1/16W

1%

100K

402

42

PLACE_NEAR=U4900.L10:5MM

0.22UF

20%

6.3V

X5R

402

4.53K

1%

PLACE_NEAR=U4900.L10:5MM

402

MF-LF

1/16W

PLACE_NEAR=R8940.1:5 MM

SM

SIGNAL_MODEL=EMPTY

MF-LF

402

1/16W

1%

1M

OPA2333

DFN

CRITICAL

MF

4.53K

201

1/20W

1%

PLACE_NEAR=U4900.N11:5mm

42

0.22UF

6.3V

20%

X5R

PLACE_NEAR=U4900.N11:5mm

0201

67 96

1/16W

1%

MF-LF

402

6.49K

1M

MF-LF

1%

402

1/16W

402

MF-LF

1%

1M

SIGNAL_MODEL=EMPTY

1%

402

MF-LF

6.49K

1/16W

CRITICAL

OPA2333

DFN

PLACE_NEAR=U4900.L12:5mm

1/16W

4.53K

1%

402

MF-LF

6.3V

0.22UF

20%

PLACE_NEAR=U4900.L12:5mm

X5R

402

42

CRITICAL

CERM

0.1UF

402

20%

10V

42

402

MF-LF

1%

4.53K

1/16W

0.22UF

6.3V

PLACE_NEAR=U4900.M10:5mm

402

X5R

20%

1/16W

MF-LF

402

1%

1.82K

DFN

CRITICAL

OPA2333

1M

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

402

MF-LF

1/16W

1M

1%

1/16W

1.82K

402

MF-LF

62 96

42

MF-LF

1%

1/16W

402

4.53K

PLACE_NEAR=U4900.N13:5mm

0.22UF

402

X5R

20%

6.3V

PLACE_NEAR=U4900.N13:5mm

7.32K

402

1/16W

MF-LF

1%

DFN

OPA2333

1%

MF-LF

1M

402

1/16W

SIGNAL_MODEL=EMPTY

402

1/16W

MF-LF

1%

1M

1%

402

1/16W

MF-LF

7.32K

10V

20%

0.1UF

X7R-CERM

0402

0612

0.003

CRITICAL

MF

1W

1%

8

NOSTUFF

1%

PLACE_NEAR=U4900.N11:5mm

4.53K

MF

1/20W

201

80

201

5%

1/20W

MF

NOSTUFF

0

5%

1/20W

MF

201

42 61

70

499K

1%

1/16W

MF-LF

402

MF-LF

PLACE_NEAR=U4900.N9:5MM

402

30.9K

1%

1/16W

PLACE_NEAR=U4900.N9:5MM

MF-LF

5.36K

402

1%

1/16W

PLACE_NEAR=R7550.2:5 MM

SM

42

4.53K

PLACE_NEAR=U4900.N10:5MM

1/16W

1%

402

MF-LF

PLACE_NEAR=U4900.N10:5MM

20%

6.3V

0.22UF

402

X5R

PLACE_NEAR=R7510.2:5 MM

SM

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

Voltage & Load Side Current Sensing

CPUVCCIOISNS_R_P

GPUVCORE_IOUT

VCCSAS0_CS_P

VCCSAISNS_R_P

SMC_P1V5MEM_ISENSE

GPUVCORE_INV

SMC_GPU_CORE_ISENSE

=PPBUS_S0_VSENSE

PM_SUS_EN

=CHGR_ACOK

DCINVSENS_EN

VCCSAS0_CS_N

PBUS_S0_VSENSE

PBUSVSENS_EN_L

GND_SMC_AVSS

CPUVCCIOS0_CS_P

ISNS_1V5_MEM_R_N

ISNS_1V5_MEM_P

ISNS_1V5_MEM_N

DCINVSENS_EN_L

GND_SMC_AVSS

CPUVCCIOS0_CS_N

=PPDCIN_S5_VSENSE

GND_SMC_AVSS

GFXVSENSE_IN

=PPVCORE_S0_AXG_REG

=PPVCORE_GPU_REG

GPUVSENSE_IN

SMC_GPU_CORE_VSENSE

GND_SMC_AVSS

SMC_CPU_SA_ISENSE

=PPVIN_S3_MEM_ISNS_R

SMC_PBUS_VSENSE

ISENSE_SA_IOUT

GND_SMC_AVSS

ISNS_1V5_MEM_R_P

=PP3V3_S0_ISNS

ISENSE_P1V5MEM_IOUT

SMC_GFX_VSENSE

=PPVCORE_S0_CPU

PBUSVSENS_EN_L_DIV

=PP3V3_S0_ISNS

GND_SMC_AVSS

CPUVCCIOISNS_R_N

ISENSE_CPUVCCIO_IOUT

VCCSAISNS_R_N

=PPVIN_S3_MEM_ISNS

GND_SMC_AVSS

SMC_CPU_VSENSE

CPUVSENSE_IN

SMC_CPUVCCIO_ISENSE

GFXIMVP6_IMON

PDCINVSENS_EN_L_DIV

DCIN_S5_VSENSE

GND_SMC_AVSS

SMC_DCIN_VSENSE

=PBUSVSENS_EN

CRITICAL

PLACE_NEAR=U4900.M10:5mm

116S0114

SENSOR_NONPROD:N

RES,MTL FILM,100K,5,1/16W,0402,SMD,LF

1

C5327

1

SENSOR_NONPROD:N

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

C5308

SENSOR_NONPROD:Y

SENSOR_NONPROD:Y SENSOR_NONPROD:Y

SENSOR_NONPROD:Y

C5330

1

2

R5330

1 2

XW5330

1 2

R5320

1 2

C5320

1

2

XW5320

1 2

R5302

1

2

R5301

1

2

C5304

1

2

R5303

1

2

R5304

1

2

Q5300

6

3

2

5

1

4

R5312

1

2

Q5310

6

3

2

5

1

4

C5314

1

2

R5311

1

2

C5335

1

2

R5335

1 2

XW5335

1 2

R5307

1 2

U5310

3

2

1

9

4

8

R5308

1 2

C5308

1

2

R5324

1 2

R5325

1

2

R5326

1 2

R5323

1 2

U5310

5

6

7

9

4

8

R5327

1 2

C5327

1

2

C5310

1

2

R5367

1 2

C5367

1

2

R5363

1 2

U5360

3

2

1

9

4

8

R5366

1 2

R5365

1

2

R5364

1 2

R5377

1 2

C5377

1

2

R5373

1 2

U5360

5

6

7

9

4

8

R5376

1 2

R5375

1

2

R5374

1 2

C5360

1

2

R5360

1

2

3

4

R5310

1 2

R5315

1

2

R5316

1

2

R5309

1

2

R5313

1

2

R5314

1

2

051-9589

4.18.0

53 OF 132

45 OF 99

96

8

96

41 42 45 46 99

8

41 42 45 46 99

8

66

8

41 42 45 46 99

96

8

45 98 99

8

13 15 98

8

45 98 99

41 42 45 46 99

96

41 42 45 46 99

IN

OUT

IN

OUT

V+

REFIN+

IN- OUT

GND

IN

OUT

V+

REFIN+

IN- OUT

GND

IN

OUT

V+

REFIN+

IN- OUT

GND

IN

OUT

V-

V+

+

-

IN

V-

V+

+

-

IN

OUT

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU VCore Load Side Current Sense / Filter

CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER

IPBR

SMC_ADC1

SMC Key IC0R

SMC Key IO0R

SMC Key IN0C

SMC_ADC4

DC-IN (AMON) Current Sense Filter

SMC Key ID0R

Gain:200x

OTHER High Side Current Sense / Filter

EDP Current:12.546A

SMC_ADC18

SMC_ADC9

SMC_ADC8

Gain:50x

SMC Key IC0C

Scale: 28.55A / V

EDP Current:20.1A

Gain:50x

EDP Current:4.9A

From charger

EDP Current:4.6A

Gain:90.31x

EDP: 33A TDP: 21.5A

SMC Key IG0R

Max VOut: 3.3V at 94.2A

GRAPHICS High Side Current Sense / Filter

Power Drop across R5400 at EDP becomes 1.21W

COMPUTING High Side Current Sense / Filter

SMC_ADC2

SMC_ADC7

SENSE R IS R7550, R7560, 0.75MOHM

Gain:140x

GFX/IG VCore Load Side Current Sense / Filter

EDP: 94A TDP :45A

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)

Individual Sense R is 0.75mOhm

Sense R is R7510, R7520 & R7530

61

42 61

402

0.22UF

20%

6.3V

X5R

PLACE_NEAR=U4900.N8:5MM

402

MF-LF

1%

1/16W

4.53K

PLACE_NEAR=U4900.N8:5MM

42

402

1%

MF-LF

1/16W

4.53K

PLACE_NEAR=U4900.L7:5MM

402

X5R

0.22UF

20%

6.3V

PLACE_NEAR=U4900.L7:5MM

42

SC70

INA213

CRITICAL

8

8 402

10V

20%

CERM

0.1UF

402

0.1UF

20%

CERM

10V

8

CRITICAL

SC70

INA213

8

42

402

0.22UF

6.3V

20%

X5R

PLACE_NEAR=U4900.K9:5MM

402

1%

4.53K

PLACE_NEAR=U4900.K9:5MM

MF-LF

1/16W

20%

402

10V

0.1UF

CERM

INA210

CRITICAL

SC70

8

CRITICAL

1W

1%

MF

0612

0.003

0612

MF

1W

1%

CRITICAL

0.003

MF

1W

CRITICAL

0612

0.005

1%

42

6.3V

402

20%

0.22UF

X5R

PLACE_NEAR=U4900.M11:5MM

SENSOR_NONPROD:Y

402

MF-LF

PLACE_NEAR=U4900.M11:5MM

4.53K

1%

1/16W

SENSOR_NONPROD:Y

1/16W

SENSOR_NONPROD:Y

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

732K

SENSOR_NONPROD:Y

SC70-5

OPA333DCKG4

CRITICAL

3.48K

SENSOR_NONPROD:Y

402

MF-LF

1%

1/16W

SENSOR_NONPROD:Y

402

MF-LF

3.48K

1%

1/16W

SENSOR_NONPROD:Y

PLACE_NEAR=R7520.3:5MM

402

1/16W

MF

0.5%

SIGNAL_MODEL=EMPTY

5.23K

SENSOR_NONPROD:Y

1/16W

MF

402

5.23K

PLACE_NEAR=R7530.3:5MM

SIGNAL_MODEL=EMPTY

0.5%

65 66 97

66 97

402

0.22UF

6.3V

20%

X5R

PLACE_NEAR=U4900.M13:5MM

SENSOR_NONPROD:Y

402

1/16W

4.53K

1%

MF-LF

PLACE_NEAR=U4900.M13:5MM

0402

X7R-CERM

PLACE_NEAR=U5460.5:3MM

0.1UF

20%

10V

SENSOR_NONPROD:Y

402

1/16W

732K

1%

MF-LF

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

SC70-5

CRITICAL

OPA333DCKG4

402

1%

1/16W

MF-LF

SIGNAL_MODEL=EMPTY

732K

SENSOR_NONPROD:Y

402

5.49K

1/16W

MF-LF

1%

SENSOR_NONPROD:Y

402

5.49K

MF-LF

1/16W

SENSOR_NONPROD:Y

1%

1/16W

SENSOR_NONPROD:Y

1%

402

732K

MF-LF

SIGNAL_MODEL=EMPTY

66 96

SENSOR_NONPROD:Y

SIGNAL_MODEL=EMPTY

0.5%

402

PLACE_NEAR=R7510.3:5MM

MF

1/16W

5.23K

65 66 97

66 97

SENSOR_NONPROD:Y

402

PLACE_NEAR=R7530.4:5MM

SIGNAL_MODEL=EMPTY

MF

5.23K

0.5%

1/16W

SENSOR_NONPROD:Y

402

MF

SIGNAL_MODEL=EMPTY

0.5%

5.23K

PLACE_NEAR=R7520.4:5MM

1/16W

PLACE_NEAR=R7510.4:5MM

402

5.23K

0.5%

MF

1/16W

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

402

PLACE_NEAR=R7550.4:5MM

1/16W

5.23K

0.5%

MF

SIGNAL_MODEL=EMPTY

402

SIGNAL_MODEL=EMPTY

5.23K

0.5%

1/16W

MF

SENSOR_NONPROD:Y

PLACE_NEAR=R7550.3:5MM

42

10%

0.022UF

0402

X5R-X7R-CERM

16V

1%

MF-LF

1/16W

45.3K

402 402

0

MF-LF

1/16W

5%

66 97

SENSOR_NONPROD:Y

402

1/16W

5.23K

0.5%

PLACE_NEAR=R7560.3:5MM

SIGNAL_MODEL=EMPTY

MF

SENSOR_NONPROD:Y

402

5.23K

MF

1/16W

0.5%

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7560.4:5MM

X7R-CERM

10V

20%

0.1UF

0402

SENSOR_NONPROD:Y

PLACE_NEAR=U5450.5:3MM

402

PLACE_NEAR=U4900.K10:5MM

45.3K

1%

1/16W

MF-LF

PLACE_NEAR=U4900.K10:5MM

402

0.0022UF

10%

50V

CERM

High Side and CPU/AXG Current Sensing

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

SENSOR_NONPROD:N

2

116S0114

RES,MTL FILM,100K,5,1/16W,0402,SMD,LF

C5451,C5461

GND_SMC_AVSS

SMC_DCIN_ISENSE

CHGR_AMON

CHGR_BMON

=PPVIN_S5_HS_GPU_ISNS_R

=PP3V3_S0_IMVPISNS

CPUIMVP_ISUMG_R_N

SMC_CHGR_BMON_ISENSE

CPUIMVP_ISUMG_IOUT

CPUIMVP_ISNS2G_N

SMC_GPU_HI_ISENSE

=PP3V3_S0_HS_ISNS

SMC_CPU_HI_ISENSE

CPUIMVP_ISUM_IOUT

CPUIMVP_ISUM_R_N

CPUIMVP_ISUM_R_P

GND_SMC_AVSS

=PPVIN_S5_HS_GPU_ISNS

HS_GPU_IOUT

SMC_CHGR_BMON_INSENSE_R

GND_SMC_AVSS

SMC_CPU_ISENSE

SMC_CPU_GFX_ISENSE

GND_SMC_AVSS

SMC_OTHER_HI_ISENSE

CPUIMVP_ISNS1G_R_P

CPUIMVP_ISNS2G_P

ISNS_HS_GPU_N

CPUIMVP_ISNS1_P

CPUIMVP_ISNS1G_R_N

GND_SMC_AVSS

=PPVIN_S5_HS_COMPUTING_ISNS_R

CPUIMVP_ISNS1G_P

=PPVIN_S5_HS_COMPUTING_ISNS

CPUIMVP_ISNS2_N

HS_COMPUTING_IOUT

GND_SMC_AVSS

CPUIMVP_ISNS2_P

ISNS_HS_OTHER_P

HS_OTHER_IOUT

GND_SMC_AVSS

CPUIMVP_ISNS3_P

CPUIMVP_ISNS1G_N

=PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_OTHER_ISNS

ISNS_HS_OTHER_N

ISNS_HS_GPU_P

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

=PP3V3_S0_HS_ISNS

CPUIMVP_ISNS3_N

CPUIMVP_ISNS_N

CPUIMVP_ISNS1_N

CPUIMVP_ISUMG_R_P

CPUIMVP_ISNS_P

=PP3V3_S0_IMVPISNS

C5403

1

2

R5403

1 2

R5433

1 2

C5433

1

2

U5400

2

5

4

6

1

3

C5401

1

2

C5431

1

2

U5430

2

5

4

6

1

3

C5413

1

2

R5413

1 2

C5411

1

2

U5410

2

5

4

6

1

3

R5400

1

2

3

4

R5410

1

2

3

4

R5430

1

2

3

4

C5451

1

2

R5451

1 2

R5455

1 2

U5450

1

3

4

2

5

R5452

1 2

R5453

1 2

R5457

1 2

R5458

1 2

C5461

1

2

R5461

1 2

C5460

1

2

R5454

1

2

U5460

1

3

4

2

5

R5465

1 2

R5462

1 2

R5463

1 2

R5464

1

2

R5456

1 2

R5472

1 2

R5471

1 2

R5470

1 2

R5467

1 2

R5466

1 2

C5421

1

2

R5423

1 2

R5420

1 2

R5468

1 2

R5469

1 2

C5450

1

2

R5441

1 2

C5441

1

2

051-9589

4.18.0

54 OF 132

46 OF 99

41 42 45 46 99

8

46

8

46

8

46

97

41 42 45 46 99

96

41 42 45 46 99

96

41 42 45 46 99

96

8

46

97

96

8

46

BI

NC

V+

GNDS

SDA

SCL

A0

ALERT

BI

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK

TW0P

X29 PROXIMITY

PLACE Q5504 ON TOP SIDE UNDER PCH

Placement note:

PLACE U5523 ON BOTTOM NEAR X29 CONN

Placement note:

TC0P

Placement note:

Read Address: 0x99

PLACE Q5503 ON TOP SIDE NEAR DDR3

Write Address: 0x98

THSP

CPU PROXIMITY TEMPERATURE

TP0P

PCH PROXIMITY TEMPERATURE

Ta0P

AIRFLOW PROXIMITY TEMPERATURE

TM0P

DDR3 PROXIMITY TEMPERATURE

TG0D

Placement note:

Th1H

PLACE Q5503 ON BOTTOM SIDE NEAR RIGHT FIN STACK

TG0P

Placement note:

Use GND pin B1 on U3600 for N leg

RIGHT FIN STACK TEMPERATURE

Th2H

LEFT FIN STACK TEMPERATURE

Placement note:

WRITE ADDRESS: 0X92

READ ADDRESS: 0X93

CLOSE TO BOARD EDGE

PLACE Q5501 ON TOP SIDE

CLOSE TO THE LEFT FIN STACK

TBT DIE

Placement note:

PLACE Q5502 ON TOP SIDE

GPU PROXIMITY TEMPERATURE

Placement note:

Write Address: 0x98

PLACE U5570 ON TOP SIDE UNDER CPU

Detect GPU Die Temperature

PLACE U5550 ON TOP SIDE UNDER GPU

Read Address: 0x99

DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

10K

5%

1/16W

402

MF-LF

5%

MF-LF

10K

1/16W

402

SOT732-3

BC846BMXXH

CRITICAL

44

MF-LF

1/16W

10K

5%

402

MF-LF

10K

1/16W

402

5%

0402

0.1UF

X7R-CERM

20%

10V

402

MF-LF

1/16W

5%

47

PLACE_NEAR=U5550.2:5mm

10%

50V

402

CERM

0.0022uF

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5550.3:5mm

SIGNAL_MODEL=EMPTY

50V

10%

PLACE_NEAR=U5550.5:5mm

PLACE_NEAR=U5550.4:5mm

CERM

0.0022uF

402

77 96

CRITICAL

BC846BMXXH

SOT732-3

CRITICAL

SOT732-3

BC846BMXXH

SOT732-3

CRITICAL

CERM

PLACE_NEAR=U5570.3:5mm

PLACE_NEAR=U5570.2:5mm

0.0022uF

50V

SIGNAL_MODEL=EMPTY

402

10%

35

SM

PLACE_NEAR=U3600.B1:2mm

PLACE_SIDE=BOTTOM

1/16W

402

NOSTUFF

5%

MF-LF

10K

0.1uF

20%

10V

CERM

402

WCSP-6

CRITICAL

TMP105

PLACE_SIDE=BOTTOM

PLACE_NEAR=J3501

44

10K

402

1/16W

5%

MF-LF

BC846BMXXH

SOT732-3

CRITICAL

EMC1414-A-AIA

DFN

EMC1414-A-AIA

44

0402

0.1UF

X7R-CERM

10V

20%

MF-LF

1/16W

47

402

5%

10%

PLACE_NEAR=U5570.5:5mm

PLACE_NEAR=U5570.4:5mm

50V

CERM

402

SIGNAL_MODEL=EMPTY

0.0022uF

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

Thermal Sensors

TBT_THERMD_N

=PP3V3_S0_GPUTHMSNS

X29THMSNS_A0

=I2C_X29THMSNS_SDA

=I2C_X29THMSNS_SCL

TP_TBT_THERM_DP

=PP3V3_S0_X29THMSNS

=PP3V3_S0_CPUTHMSNS

TBT_THERMD_P

MAKE_BASE=TRUE

GPUTHMSNS_D_N

GPUTHMSNS_D_P

GPUTHMSNS_ALERT_L

=SMBUS_GPUTHMSNS_SCL

=SMBUS_GPUTHMSNS_SDA

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

GPU_TDIODE_N

GPUTHMSNS_THM_L

GPU_TDIODE_P

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

DDR3THMSNS_D1_N

CPUTHMSNS_THM_L

DDR3THMSNS_D1_P

C5570

1

2

R5570

1 2

C5590

1

2

R5572

1

2

R5571

1

2

Q5504

1

3

2

R5551

1

2

R5552

1

2

C5550

1

2

R5550

1 2

C5551

1

2

C5552

1

2

Q5503

1

3

2

Q5501

1

3

2

Q5502

1

3

2

C5571

1

2

XW5520

1 2

R5520

1

2

C5523

1

2

U5523

C2

B2

A2

B1

A1

C1

R5522

1

2

Q5506

1

3

2

U5550

83

5

2

4

6

10

9

7

11

1

U5570

83

5

2

4

6

10

9

7

11

1

051-9589

4.18.0

55 OF 132

47 OF 99

97

8

97

96

G

S D

G

S D

IN

OUT OUT

IN

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Right Fan

Left Fan

518S0769 518S0769

1/16W

5%

47K

MF-LF

402

5%

1/16W

47K

MF-LF

402

5%

47K

1/16W

5%

1/16W

47K

MF-LF

402

100K

MF-LF

402

5%

1/16W

2N7002DW-X-G

SOT-363

MF-LF

402

5%

1/16W

100K

SOT-363

2N7002DW-X-G

41

41 41

41

CRITICAL

F-RT-SM

FF14A-5C-R11DL-B-3H

CRITICAL

F-RT-SM

FF14A-5C-R11DL-B-3H

Fan Connectors

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

=PP3V3_S0_FAN_RT

FAN_RT_PWM

FAN_RT_TACH

=PP5V_S0_FAN_RT

SMC_FAN_1_TACH

FAN_LT_PWM

FAN_LT_TACH

=PP5V_S0_FAN_LT

=PP3V3_S0_FAN_LT

SMC_FAN_0_TACH

SMC_FAN_1_CTLSMC_FAN_0_CTL

R5650

1

2

R5655

1 2

R5660

1

2

R5665

1 2

R5651

1

2

Q5660

3

5

4

R5661

1

2

Q5660

6

2

1

J5650

7

6

1

2

3

4

5

J5660

7

6

1

2

3

4

5

051-9589

4.18.0

56 OF 132

48 OF 99

8

7

8

7

8

IN

OUT

D

SG

IN_2

IN_3

IN_1

OUT_2

OUT_3

OUT_ALL#

OE

THRM

GND

OUT_1

VDD

PAD

(IPD)

OUT

G

D

S

V+

GND

D

S

G

IN

NC

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3

P2_1

P4_7

P4_5

P4_3

P4_1

P3_7

P3_5

P3_3

P3_1

P5_7

P5_5

P5_3

P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSS

D+

D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

OUT NC

NC

NC NC

NC

D

G S

IN

D

G S

D

S

G

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

337S2983

Keys ANDed with PSoC power to isolate when PSoC is not powered.

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

75.2E-6 W

4.7 OHM

ISSP SDATA/I2C SDA

RDS(ON)

CHANNEL

MOSFET SiA413

29 mOhm @4.5V

P-TYPE 12V

16 mA (EDP)

IPD Flex Connector

PSOC

3V3 LDO

TMP102

IC

VDD

VIN

VOUT

VDD

V+

PIN NAME

4MA (MAX)

CURRENT

80UA

10UA

60MA (MAX)

10 OHM

1.5 OHM

0.2 OHM

2.55 KOHM

R_SNS

0.012 V

0.021 V

0.0188 V

0.6 V

0.0255 V

0.204 V

V_SNS POWER

0.255E-6 W

16.32E-6 W

36E-3 W

0.72E-3 W

96E-6 W

294E-6 W

516S0689

(PP3V3_S3_PSOC)

- USB INTERFACES TO MLB

518S0752

Keyboard Connector

Pull-up in U5010.

- KEYBOARD SCANNER

- SPI HOST TO Z2

5V TPAD FET

No IPD on OE input pin PP3V3_S4 (symbol error).

14MA (MAX)

8MA (TYP)

60MA (MAX)

SMC Manual Reset & Isolation

18V BOOSTER

- TRACKPAD PICK BUTTONS

PSOC USB CONTROLLER

ISSP SCLK/I2C SCL

LOADING

LED Current

none

sink

source

Q5738

off

on

Q5736

off

on

off

CAP_COMP_L

1

0

CAP_COMP_H

1

0

1

Z

0

1

WS_KBD15_C

TPAD_5V:SW_S4 Original implementation off PP5V_S4

TPAD_5V:LDO_S5 PP5V_S5 LDO power

BOM Options available to CSA 5

TPAD_5V:LDO_S4 PP5V_S5 LDO power in S4 only

Caps Lock LED Drive

LID CLOSE => SMC_LID_LC < 0.50V

LID OPEN => SMC_LID_LC ~ 3.42V

WHEN THE LID IS CLOSED

THE TPAD BUTTONS WILL BE DISABLE

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

PLACE THESE COMPONENTS CLOSE TO J5800

TPAD Buttons Disable

5V TRACKPAD S4 FET

All RC values are TBD

41 42

10V

20%

PLACEMENT_NOTE=NEAR J5713

CERM

402

0.1UF

MF-LF

1K

1/16W

5%

402

1%

MF-LF

1/16W

10K

402

41 42

SSM6N15FEAPE

SOT563

SLG4AP021

TQFN

42

16V

X7R-CERM

0402

0.1UF

10%

M-ST-SM

55560-0228

CRITICAL

F-RT-SM

FF14A-30C-R11DL-B-3H

DFN1006H4-3

DMN3730UFB4

CAPS:EXT

MF

10K

1/20W

201

5%

CAPS:EXT

20K

MF

1/20W

201

5%

MF

1/20W

1%

113

CAPS:EXT

201

LM393ADGKR

MSOP

CAPS:EXT

MF

1/20W

201

5%

10K

20K

1/20W

MF

CAPS:EXT

201

5%

CAPS:EXT

MF

10K

1/20W

201

5%

CAPS:EXT

1/20W

MF

10K

201

5%

MF

1/20W

10K

CAPS:EXT

201

5%

CAPS:EXT

10K

MF

1/20W

201

5%

CAPS:EXT

MF

1/20W

113

1%

201

NTZD3152P

CAPS:EXT

SOT-563-HF

1/20W

24

MF

5%

201

1/20W

MF

24

201

5%

70

NP0-CERM

0201

25V

5%

BYPASS=U5701.22:19:5 mm

100PF

6.3V

10%

X5R

201

0.1UF

BYPASS=U5701.22:19:8 mm

BYPASS=U5701.22:19:11 mm

6.3V

20%

X5R

4.7UF

402

CRITICAL

OMIT

MLF

CY8C24794

42

PLACE_SIDE=BOTTOM

1.5

MF-LF

1/16W

5%

402

1/20W

MF

220K

201

5%

BYPASS=U5701.49:50:5 mm

NP0-CERM

0201

25V

100PF

5%

X5R

6.3V

BYPASS=U5701.49:50:8 mm

201

0.1UF

10%

6.3V

20%

X5R

4.7UF

BYPASS=U5701.49:50:11 mm

402

TPAD_5V_SW_S4

10%

0.1UF

PLACE_NEAR=J5800.18:3MM

X5R-CERM

0201

10V

TPAD_5V_SW_S4

PLACE_NEAR=J5800.18:3MM

FERR-120-OHM-1.5A

0402-LF

VESM

SSM3K15AMFVAPE

CRITICAL

CAPS:EXT

1/20W

CAPS:EXT

MF

10K

201

5%

MF-LF

1/16W

1%

56.2

CAPS:INT

402

70

TPAD_5V_FET

SOD-VESM-HF

SSM3K15FV

TPAD_5V_FET

10%

402

16V

0.033UF

X5R

TPAD_5V_FET

CRITICAL

SIA413DJ

SC70-6L

TPAD_5V_NO_FET

402

0

1/16W

MF-LF

5%

TPAD_5V_LDO

FERR-120-OHM-1.5A

0402-LF

PLACE_NEAR=J5800.18:3MM

TPAD_5V_LDO

X5R-CERM

0.1UF

PLACE_NEAR=J5800.18:3MM

10%

10V

0201

TPAD_5V_FET

MF

1/20W

5%

220K

201

TPAD_5V_FET

MF

1/20W

5%

3.3K

201

TPAD_5V_FET

10%

10V

X5R

0.01UF

201

0

5%

1/20W

MF

NOSTUFF

201

0.1UF

10%

6.3V

X5R

201

220K

5%

1/20W

MF

KEYBOARD/TRACKPAD (1 OF 2)

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

TPAD_5V_NO_FET,TPAD_5V_LDO

TPAD_5V:LDO_S5

TPAD_5V_FET,TPAD_5V_LDO

TPAD_5V:LDO_S4

TPAD_5V_SW_S4TPAD_5V:SW_S4

=PP3V3_S4_TPAD

=P5VS4_TPAD_EN

TP_PSOC_SDA

TP_PSOC_SCL

TP_P7_7

Z2_HOST_INTN

WS_LEFT_OPTION_KBD

TP_ISSP_SDATA_P1_0

WS_KBD5

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50MM

PP3V3_S3_PSOC

MIN_NECK_WIDTH=0.20MM

USB_TPAD_P

BUTTON_DISABLE

=PP3V42_G3H_TPAD

Z2_SCLK

Z2_MISO

=PP3V3_S4_TPAD

WS_KBD15_C

WS_KBD15_CAP

WS_KBD7

WS_KBD8

WS_KBD11

WS_KBD12

WS_KBD13

WS_CONTROL_KBD

WS_LEFT_SHIFT_KBD

CAP_SINK

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MM

WS_KBD15_CAP

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MM

CAP_SOURCE

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MM

CAP_COMP_L

WS_KBD15_C

CAP_VREF_H

USB_TPAD_R_N

CAP_COMP_H

CAP_COMP_L_INV

CAP_VREF_L

WS_KBD6

=PP3V42_G3H_TPAD

WS_KBD9

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KEY

WS_KBD2

PSOC_MISO

BUTTON_DISABLE

PICKB_L

=PP3V3_S4_TPAD

WS_KBD19

WS_KBD21

WS_KBD20

WS_KBD23

=PSOC_WAKE_L

WS_KBD15_C

WS_KBD17

WS_KBD16N

WS_KBD14

WS_KBD13

WS_KBD10

WS_KBD1

WS_KBD8

WS_KBD12

WS_KBD11

WS_KBD9

WS_KBD18

TP_ISSP_SCLK_P1_1

TP_PSOC_P1_3

PSOC_F_CS_L

Z2_SCLK

Z2_KEY_ACT_L

WS_CONTROL_KEY

PSOC_SCLK

Z2_MOSI

Z2_CS_L

PSOC_MOSI

USB_TPAD_N

WS_KBD_ONOFF_L

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

WS_CONTROL_KEY

WS_KBD19

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

WS_KBD23

WS_KBD22

WS_KBD20

WS_KBD21

WS_KBD10

WS_KBD14

WS_KBD17

WS_KBD18

WS_KBD5

WS_KBD3

SMC_LID

=PP3V3_S4_TPAD

WS_KBD4

WS_KBD1

SMC_TPAD_RST_L

WS_KBD16_NUM

WS_KBD16N

WS_KBD2

SMC_ONOFF_L

WS_KBD22

Z2_HOST_INTN

Z2_CS_L

=I2C_TPAD_SCL

=I2C_TPAD_SDA

PSOC_SCLK

PSOC_MOSI

PSOC_MISO

PP5V_S5RS4_CUMULUS

Z2_KEY_ACT_L

USB_TPAD_R_P

WS_KBD4

WS_KBD7

TPAD_VBUS_EN

WS_KBD3

WS_KBD6

Z2_CLKIN

P5VCUMULUS_EN_L

=PP5V_S5_TPAD

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

PP5V_S5RS4_CUMULUS

MIN_LINE_WIDTH=0.50MM

Z2_MOSI

Z2_MISO

P5VCUMULUS_SS

=PP3V3_S4_TPAD

=PP5V_S4_TPAD

PSOC_F_CS_L

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_TPAD_CONN

PICKB_L

MIN_NECK_WIDTH=0.20MM

VOLTAGE=5V

PP5V_S4_CUMULUS

MIN_LINE_WIDTH=0.50MM

Z2_CLKIN

C5710

1

2

R5710

1 2

R5715

1 2

Q5701

6

21

U5750

5

1

2

3

4

9

8

7

6

11

10

C5750

1

2

J5700

1

10

1112

1314

1516

1718

19

2

20

2122

34

56

78

9

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

Q5738

3

1

2

R5735

1

2

R5734

1

2

R5737

1

2

U5730

4

6

2

5

3

7

1

8

R5732

1

2

R5733

1

2

R5730

1

2

R5731

1

2

R5738

1

2

R5736

1

2

R5739

1

2

Q5736

6

2

1

R5702

1 2

R5701

1 2

C5702

1

2

C5703

1

2

C5701

1

2

U5701

20

21

45

54

46

53

47

52

48

51

25

18

26

17

27

16

28

15

412

421

43

56

44

55

3310

349

358

367

376

385

394

403

2914

3013

3112

3211

24

23

57

22 49

19

50

R5704

2 1

R5703

1

2

C5704

1

2

C5705

1

2

C5706

1

2

C5700

1

2

L5700

1 2

Q5734

3

12

R5740

1

2

R5714

1 2

Q5721

3

12

C5722

1

2

Q5720

1

3

4 7

R5720

1 2

L5707

1 2

C5707

1

2

R5721

1

2

R5722

1 2

C5723

1 2

R5708

1 2

C5708

1

2

R5700

1

2

49 OF 99

051-9589

4.18.0

57 OF 132

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49

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7

49

7

49

7

49

7

49

7

49

7

49

7

49

7

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7

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26

96

7

49

8

49

7

49

7

49

7

49

7

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8

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7

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7

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7

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7

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7

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7

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91

7

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49

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49

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44

7

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7

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26

96

7

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49

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49

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49

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7

49

7

49

7

49

OUT

NC

IN

SW

LED

CAP

SW

VIN

GND

CTRL

PAD

SW

LED

CAP

SW

VIN

GND

CTRL

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Keyboard Backlight Connector

Keyboard Backlight Driver & Detection

353S3472

ON KEYBOARD BACKLIGHT FLEX

J5815 PIN 4 IS GROUNDED

To detect Keyboard backlight, SMC will

tristate and read SMC_SYS_KBDLED:

R5853 always stuffed, R5854 only

If LOW, keyboard backlight present

grounded when KB BL flex connected.

If HIGH, keyboard backlight not present

516S0899

402

470K

1/16W

MF-LF

5%

4.7K

1/16W

MF-LF

5%

402

41 50

AA07A-S010-VA1

F-ST-SM

CRITICAL

10V

X5R

0603

10UF

20%

NOSTUFF

41 50

10K

5%

1/16W

MF-LF

402

NOSTUFF

100K

5%

1/16W

MF-LF

402

NOSTUFF

1UF

X5R

10V

10%

402-1

1/16W

120K

5%

MF-LF

402

NOSTUFF

1UF

X5R

10V

10%

402-1

VLF403212MT-SM

CRITICAL

15UH-20%-740MA-0.42OHM

5%

NOSTUFF

0

402

1/16W

MF-LF

VLF403212MT-SM

CRITICAL

15UH-20%-740MA-0.42OHM

5%

402

MF-LF

0

1/16W

DFN

LT3591

OMIT_TABLE

1/16W

MF-LF

10

402

1%

OMIT_TABLE

LT3591

DFN

402

10

1/16W

MF-LF

1%

10%

1.0UF

0603

X5R

50V

CRITICAL

KBD_BL:SANDWICH

10%

1.0UF

0603

X5R

50V

CRITICAL

KBD_BL:SANDWICH

KBD_BL:TBONE

10%

1.0UF

0805

X7R

50V

CRITICAL

10%

1.0UF

0603

X5R

50V

CRITICAL

KBD_BL:SANDWICH

10%

1.0UF

0603

X5R

50V

CRITICAL

KBD_BL:SANDWICH

10%

1.0UF

0805

X7R

50V

CRITICAL

KBD_BL:TBONE

CRITICAL

50V

X7R

0805

1.0UF

10%

CRITICAL

KBD_BL:TBONE

50V

X7R

0805

1.0UF

10%

2

U5850,U5860

CRITICAL

IC,DC/DC CVTR,BOOST,WHITE LED,1MHZ,DFN8

353S1612

SYNC_MASTER=D2_KEPLER

KEYBOARD/TRACKPAD (2 OF 2)

SYNC_DATE=01/13/2012

KBDLED_ANODE2

SMC_SYS_KBDLED

=PP3V3_S0_TPAD

KBDLED_ANODE1

SMC_KBDLED_PRESENT_L

SMC_SYS_KBDLED_FILTER

=PP5V_S0_KBDLED

SMC_SYS_KBDLED_ANALOG

SMC_SYS_KBDLED_R

SMC_SYS_KBDLED

KBDLED_CAP1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

KBDLED_SW2

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=35V

MIN_LINE_WIDTH=0.25 MM

KBDLED_ANODE2

MIN_NECK_WIDTH=0.2 MM

KBDLED_ANODE1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=35V

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

KBDLED_SW1

MIN_LINE_WIDTH=0.25 MM

KBDLED_CAP2

MIN_NECK_WIDTH=0.2 MM

R5853

1

2

R5854

1

2

J5815

11

12

13

14

1

10

2

34

56

78

9

C5859

1

2

R5857

1

2

R5859

1

2

C5860

1

2

R5858

1

2

C5850

1

2

L5860

1 2

R5866

1 2

L5850

1 2

R5856

1 2

U5860

5

6

8

2

7

3

4

9

1

R5865

1 2

U5850

5

6

8

2

7

3

4

9

1

R5855

1 2

C5865

1

2

C5866

1

2

C5867

1

2

C5855

1

2

C5856

1

2

C5857

1

2

C5868

1

2

C5858

1

2

051-9589

4.18.0

58 OF 132

50 OF 99

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50

8

7

50

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50

INT2

VDD

VDD_IO

SDO

GND

NC

RESERVED

INT1

CS

SDA/SDI/SDO

SCL/SPC

NC

OUT

BI

IN

RES/VDD

VDD

RES0

RES1

RES2

RES3

DRDY/

VDD_IO

SCL_SPC

SDA_SDI_SDO

SDO_SA0

CS

GND

INT1

PLLFILT

DEN

INT2

BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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PAGE TITLE

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Circle indicates pin 1 location when placed

INT ARE PUSH-PULL

CS PU = I2C

338S0927 = 8KHZ

(WRITE: 0XD0 READ: 0XD1)

GYRO

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

in correct orientation

+X

Desired orientation when

+Y

+Z (dn)

Front of system

338S0687

placed on board bottom-side (view thru top):

SMS

CRITICAL

PLACEMENT_NOTE=See schematic for orientation.

LIS331DLH

LGA

SMS

0.1UF

6.3V

BYPASS=U5920.14:13:8 mm

X5R

201

10%

SMS

20%

10UF

6.3V

603

BYPASS=U5920.14:13:8 mm

X5R

SMS

MF

5%

1/20W

10K

201

SMS

MF

1/20W

5%

10K

201

SMS

1/20W

5%

0

MF

201

SMS

1/20W

0

MF

5%

201

SMS

MF

1/20W

5%

10K

201

41 42

44

NOSTUFF

10K

1/20W

5%

MF

201

GYRO

1/20W

MF

5%

10K

201

GYRO

402

CERM-X5R

6.3V

0.47UF

10%

GYRO

10V

X5R-CERM

0201

0.01UF

10%

GYRO

10K

5%

1/20W

MF

201

GYRO

CRITICAL

AP3GDL8B

LGA

GYRO

0.1UF

6.3V

X5R

201

10%

GYRO

0.1UF

6.3V

X5R

201

10%

GYRO

6.3V

CERM-X5R

20%

0402-1

10UF

GYRO

5%

MF

0

1/20W

201

GYRO

1/20W

MF

0

5%

201

44

DIGITAL ACCELEROMETER & GYRO

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

=I2C_SMC_GYRO_SCL

=I2C_SMC_GYRO_SDA

TP_GYRO_SYNC

=PP3V3_S3_SMS

SMS_ADDR_SELECT

SMS_I2C_SEL

SMS_INT_L

TP_SMS_INT2

PLLFILT_GYRO

PLLFILT_GYRO1

I2C_SMC_SMS_SCL_R

=I2C_SMC_SMS_SCL

I2C_SMC_GYRO_SDA_R

I2C_SMC_GYRO_SCL_R

=I2C_SMC_SMS_SDA

GYRO_CS

TP_IRQ_GYRO_INT2_L

I2C_SMC_SMS_SDA_R

TP_IRQ_GYRO_INT1_L

=PP3V3_S3_GYRO

U5920

8

5

12

13

16

11

9

2

3

10

15

4

6

7

14

1

C5922

1

2

C5926

1

2

R5920

1

2

R5921

1

2

R5922

1 2

R5923

1 2

R5924

1

2

R5925

1

2

R5945

1

2

C5942

1

2

C5945

1

2

R5944

1

2

U5940

5

8

6

13

7

14

9

10

11

12

15

2

3

4

16

1

C5940

1

2

C5941

1

2

C5943

1

2

R5946

1 2

R5947

1 2

051-9589

4.18.0

59 OF 132

51 OF 99

8

OUT

IN

IN IN

IN

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ROM will ignore SPI cycles.

NOTE: If HOLD* is asserted

10V

0.1UF

CERM

20%

402

1/16W

MF-LF

5%

3.3K

402

42 43

42 43 42 43

7

20 43

OMIT

CRITICAL

SST25VF064C

64MBIT

SOIC

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

SPI ROM

SPIROM_USE_MLB

=PP3V3_SUS_ROM

SPI_MLB_MOSI

SPI_MLB_CS_L

SPI_WP_L

SPI_MLB_MISO

SPI_MLB_CLK

C6100

1

2

R6101

1

2

U6100

1

7

65

2

8

4

3

051-9589

4.18.0

61 OF 132

52 OF 99

8

IN

OUT

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

OUT

IN

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC

FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+

MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI

SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL

AUDIO CODEC

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

APPLE P/N 353S2355

NC

RT. SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

LFT SUBWOOFER AMP. SIG. SOURCE

NOTES ON CODEC I/O

NC

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

DAC2/3 FSOUTPUTSE= 1.34VRMS

SE FSINPUT= 1.22VRMS

DAC1 FSOUTPUT= 1.34VRMS

DIFF FSINPUT= 2.45VRMS

RT. SUBWOOFER AMP. SIG. SOURCE

APPLE P/N 353S2456

4.5V POWER SUPPLY FOR CODEC

EXT MIC CODEC INPUT

GPIO3 = SPKR AMP SHDN CONTROL

15" MBP: PLACE XW6201 NEAR 5V SOURCE

20%

TANT

1UF

0603-SM

16V

4V

20%

X5R-1

4.7UF

402

17 92

59

57

7

54 58

7

54 58

57 96

58 96

10V

1UF

402

X5R

10%

FERR-22-OHM-1A-0.065-OHM

0201

MF

2.2K

5%

1/20W

201

10V

1UF

402

X5R

10%

6.3V

201

X5R

0.1UF

10%

2.67K

1%

1/20W

MF

201

MF

5%

201

22

1/20W

X7R-CERM

0402

16V

0.1UF

10%

TANT-POLY

2012-LLP

10UF

20%

16V

2012-LLP

TANT-POLY

10UF

20%

16V

10UF

20%

2012-LLP

TANT-POLY

16V

8

53 58

53 58 59

8

53 58 59

58

53 58 59

SON

TPS71745

CRITICAL

57 96

0201

FERR-22-OHM-1A-0.065-OHM

201

6.3V

X5R

0.1UF

10%

8

53 58

QFN

CS4206B

CRITICAL

SM

0201

FERR-22-OHM-1A-0.065-OHM

SM

8

59

0201

X5R-CERM

CRITICAL

16V

0.1UF

10% 20%

1.0UF

10V

X5R-CERM

CRITICAL

0201-1

0201

X5R-CERM

CRITICAL

16V

0.1UF

10%

0402-1

10UF

X5R-CERM

10V

CRITICAL

20%

57 96

MF-LF

5%

1/16W

33

402

7

58

59

10V

1UF

X5R

402-1

10%

59

MF-LF

1/16W

5%

0

402

X5R

20%

15UF

CRITICAL

0402

4V

0402

X5R

4V

20%

15UF

CRITICAL

0402

15UF

20%

4V

X5R

0402

15UF

20%

4V

X5R

AUDIO: CODEC/REGULATOR

SYNC_MASTER=D2_CARA

SYNC_DATE=03/16/2012

HDA_SYNC

HDA_SDOUT

HDA_BIT_CLK

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 mm

PP1V5_S0_AUDIO_DIG

VOLTAGE=1.5V

PP5V_AUDIO_HPAMP

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.3MM

AUD_HP_PORT_L

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.15MM

VOLTAGE=0V

GND_AUDIO_CODEC

NC_AUD_LI_P_L

NO_TEST=TRUE

PP5V_S4_AUDIO_XW

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.60MM

VOLTAGE=5V

AUD_HP_PORT_R

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.3MM

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.20MM

VOLTAGE=4.5V

MIN_NECK_WIDTH=0.15MM

PP5V_AUDIO_HPAMP

MIN_LINE_WIDTH=0.20MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.15MM

CS4206_VCOM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

VBIAS_DAC

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

CS4206_VREF_ADC

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

TP_AUD_CODEC_MICBIAS

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

AUD_HP_PORT_REF

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

NC_AUD_LI_P_R

NO_TEST=TRUE

NC_AUD_LI_REF

NO_TEST=TRUE

AUD_SDI_R

PP4V5_AUDIO_ANALOG

AUD_LO2_L_N

AUD_LO2_R_P

AUD_MIC_INL_P

AUD_SPDIF_OUT_JACK

4V5_REG_EN

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO_DIG

=PP5V_S4_AUDIO

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

4V5_NR

=PP1V5_S0_AUDIO

TP_AUD_MIC_INN_R

AUD_LO2_L_P

AUD_LO1_R_N

HDA_SDIN0

AUD_LO2_R_N

AUD_LO1_L_P

AUD_LO1_L_N

AUD_LO1_R_P

AUD_DMIC_CLK

AUD_SENSE_A

=PP3V3_S0_AUDIO_DIG

AUD_SPDIF_OUT

TP_AUD_SPDIF_IN

AUD_DMIC_CLK_R

AUD_MIC_INL_N

TP_AUD_MIC_INP_R

HDA_RST_L

4V5_REG_IN

MIN_LINE_WIDTH=0.20MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.15MM

AUD_DMIC_SDA1

AUD_DMIC_SDA2

GND_AUDIO_CODEC

CS4206_FLYP

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

CS4206_FLYC

CS4206_FLYN

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

CS4206_FP

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

CS4206_FN

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

AUD_GPIO_3

TP_XCVR_ADC_RSTN

C6224

1

2

C6210

1

2

C6201

1

2

L6200

1 2

R6200

1 2

C6200

1

2

C6211

1

2

R6210

1

2

R6211

1 2

C6218

1

2

C6225

1

2

C6217

1

2

C6219

1

2

U6200

4

2

6

3

1

L6201

1 2

C6226

1

2

U6201

26

6

7

4

43

42

45

2

12

14

15

38

40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

11

8

5

13

47

48

10

49

25

46

24

29

28

9

41

44

3

1

27

XW6200

1 2

L6202

1 2

XW6201

1 2

C6202

1

2

C6203

1

2

C6214

1

2

C6213

1

2

R6220

1 2

C6216

1

2

R6241

1 2

C6220

1

2

C6221

1

2

C6222

1

2

C6223

1

2

051-9589

4.18.0

62 OF 132

53 OF 99

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53

53 54 58 59

53

92

53 54 58 59

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

7

53 58

10K

1%

1/20W

MF

201

7

53 58

10K

1%

1/20W

MF

201

0.1UF

X5R

10%

6.3V

CRITICAL

39

MF

201

1/20W

5%

39

5%

1/20W

MF

201

0.1UF

201

X5R

6.3V

10%

CRITICAL

7

53 58

53 58 59

7

53 58

AUDIO: HEADPHONE FILTER

SYNC_DATE=03/16/2012

SYNC_MASTER=D2_CARA

AUD_HP_ZOBEL_L

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

AUD_HP_ZOBEL_R

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

GND_AUDIO_CODEC

AUD_HP_PORT_R

AUD_HP_PORT_L

R6302

1

2

R6312

1

2

C6300

1

2

R6300

1

2

R6310

1

2

C6310

1

2

051-9589

4.18.0

63 OF 132

54 OF 99

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_DATE=03/16/2012

SYNC_MASTER=D2_CARA

AUDIO: IV SENSE

051-9589

4.18.0

64 OF 132

55 OF 99

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_DATE=03/16/2012

SYNC_MASTER=D2_CARA

AUDIO: IV SENSE FILTER

051-9589

4.18.0

65 OF 132

56 OF 99

VDD

EDGE

GND

GAIN

SD*

OUT+

OUT-

IN-

IN+

OUT

VDD

EDGE

GND

GAIN

SD*

OUT+

OUT-

IN-

IN+

OUT

IN

OUT

IN

OUT

IN

OUT

IN-

IN+

OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

IN-

IN+

OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

GAIN = +3 DB

1ST ORDER FC (SUB) = NOM 9 HZ

1ST ORDER FC (L&R) = NOM 569 HZ

0402

FERR-1000-OHM

CRITICAL

16V

0.22UF

CRITICAL

CERM

402

10%

16V

CERM

402

10%

0.22UF

CRITICAL

10%

402

CERM

CRITICAL

0.22UF

16V

10%

402

CERM

CRITICAL

0.22UF

16V

2012-LLP

20%

POLY-TANT

6.3V

47UF

CRITICAL

47UF

2012-LLP

20%

POLY-TANT

6.3V

CRITICAL

SSM2375

WLCSP

7

59 96

7

59 96

PLACE_NEAR=U6630.C2

X5R-CERM

0201

0.1UF

16V

10%

6.3V

47UF

20%

CRITICAL

2012-LLP

POLY-TANT

SSM2375

CRITICAL

WLCSP

6.3V

20%

47UF

2012-LLP

POLY-TANT

CRITICAL

7

59 96

7

59 96

PLACE_NEAR=U6640.C2

16V

X7R-CERM

0402

0.1UF

10%

MF-LF

1/16W

5%

402

100K

0402

CRITICAL

FERR-1000-OHM

53 96

53

CRITICAL

0402

FERR-1000-OHM

7

59 96

PLACE_NEAR=U6610.A1

10%

0.1UF

0402

16V

X7R-CERM

CRITICAL

20%

6.3V

POLY-TANT

2012-LLP

47UF

PLACE_NEAR=U6620.A1

X5R-CERM

16V

10%

0.1UF

0201

FERR-1000-OHM

0402

CRITICAL

53 96

7

59 96

20%

TANT-POLY

CASE-A4

6.3V

47UF

CRITICAL

0402

CRITICAL

FERR-1000-OHM

53 96

CRITICAL

0402

FERR-1000-OHM

53 96

CRITICAL

10%

0402

X7R-CERM

50V

0.01UF

10%

X7R-CERM

50V

CRITICAL

0.01UF

0402

50V

CRITICAL

0.01UF

X7R-CERM

0402

10%

0.01UF

50V

0402

CRITICAL

X7R-CERM

5%

100K

1/20W

MF

201

NOSTUFF

7

59 96

7

59 96

CRITICAL

MAX98300

WLP

1/16W

402

MF-LF

5%

100K

CRITICAL

WLP

MAX98300

100K

1/16W

5%

402

MF-LF

53 96

CRITICAL

FERR-1000-OHM

0402

CRITICAL

FERR-1000-OHM

0402

53 96

FERR-1000-OHM

0402

CRITICAL

53 96

SYNC_DATE=03/16/2012

SYNC_MASTER=D2_CARA

AUDIO: SPEAKER AMP

PP5V_S0_AUDIO_AMP_L

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_P

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_R_OUT_N

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_L_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_L_OUT_P

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRAMP_LIN_P

NO_TEST=TRUE

PP5V_S0_AUDIO_AMP_R

SPKRAMP_RIN_P

NO_TEST=TRUE

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SL_OUT_P

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_SL_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_R_OUT_P

MIN_NECK_WIDTH=0.10 MM

AUD_SPKRAMP_SHUTDOWN_L

AUD_GPIO_3

AUD_LO2_L_N

AUD_LO2_R_P

AUD_SPKRAMP_RIN_N

NO_TEST=TRUE

AUD_SPKRAMP_RIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

NO_TEST=TRUE

SPKRAMP_RIN_N

SPKR_L_GAIN

SPKR_R_GAIN

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_LO2_L_P

PP5V_S0_AUDIO_AMP_L

AUD_LO2_R_N

SPKRAMP_LIN_N

NO_TEST=TRUE

AUD_SPKRAMP_SHUTDOWN_L

AUD_SPKRAMP_RSUBIN_P

NO_TEST=TRUE

AUD_LO1_R_P

NO_TEST=TRUE

AUD_SPKRAMP_RSUBIN_N

AUD_LO1_R_N

AUD_SPKRAMP_SHUTDOWN_L TP_SWR_GAIN

RSUBIN_P

NO_TEST=TRUE

TP_SWL_GAIN

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_P

AUD_SPKRAMP_LSUBIN_N

NO_TEST=TRUE

AUD_LO1_L_P

AUD_LO1_L_N

NO_TEST=TRUE

RSUBIN_N

LSUBIN_N

NO_TEST=TRUE

LSUBIN_P

AUD_SPKRAMP_SHUTDOWN_L

PP5V_S0_AUDIO_AMP_R

R6600

1

2

L6601

1 2

L6611

1 2

C6611

1

2

C6622

1

2

C6621

1

2

L6621

1 2

C6612

1

2

L6610

1 2

L6620

1 2

C6623

1 2

C6624

1 2

C6614

1 2

C6613

1 2

R6601

1

2

U6610

C3

B3

A3

C1

B1

A2 A1

C2

R6610

1

2

U6620

C3

B3

A3

C1

B1

A2 A1

C2

R6620

1

2

L6641

1 2

L6640

1 2

L6631

1 2

L6630

1 2

C6643

1 2

C6644

1 2

C6634

1 2

C6633

1 2

C6635

1

2

C6632

1

2

U6630

B2

A3

C1

A1

B1

B3

C3

A2

C2

C6631

1

2

C6645

1

2

U6640

B2

A3

C1

A1

B1

B3

C3

A2

C2

C6642

1

2

C6641

1

2

051-9589

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B2

9

57

96

9

57

96

57

96

9

57

96

57

96

57

96

96 57

9

57

ADDR

SDA

SCL

REF

MIC

CLAMPO

CLAMPI

RAMPO

RAMPI

GND2

MIC2

GND

MIC1

VDD

GND1

OUT

CS

HDET

AGND

DGND

ENABLE

AVDD

SDA

BYPASS

DETECT

MICBIAS

INT*

SCL

IN

BI

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOISE ISSUE SEEN ON EARLY HEADSETS

R/C6750 FILTER TO ADDRESS OUT-OF-BAND

(SEE RADAR # 6210118)

MIKEY U6751 WRITE 0111 0010 0X72

CHS U6750 READ 0111 0111 0X77

CHS U6750 WRITE 0111 0110 0X76

I2C ADDRESSES

MIKEY U6751 READ 0111 0011 0X73

PORT B LEFT(HEADSET MIC)

APN:353S2640

HP=80HZ, LP=10.63KHZ

AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS

I2C PULLUPS ON SOUTHBRIDGE PAGE

APN:510S0009

MIKEY 1A

MIKEY ADDRESS: WRITE=72H, READ=73H

TS3A8235YFP

CRITICAL

WCSP

53 96

X5R

0.1UF

MIKEY

CRITICAL

6.3V

201

10%

X5R

MIKEY

0.1UF

6.3V

CRITICAL

201

10%

5%

MF

1/20W

100K

MIKEY

201

5%

100K

1/20W

MF

201

WCSP

CD3282A1

CRITICAL

MIKEY

10V

X5R-X7R-CERM

0201

6800PF

10%

5%

MIKEY

1/20W

2.2K

MF

201

0.01UF

0201

X5R-CERM

10V

10%

5%

27PF

0201

25V

CRITICAL

MIKEY

NP0-C0G

5%

1K

MF

1/20W

MIKEY

201

0201-1

X5R-CERM

1.0UF

20%

10V

MF

2.2K

1%

1/20W

201

2.2K

1/20W

MF

1%

201

5%

MF

1K

1/20W

201

PLACE_NEAR=U6750.D1

SM

X5R-CERM

10UF

0402-1

20%

10V

58

44

19

25

59

5%

1/20W

MF

47K

NOSTUFF

201

5%

1/20W

33

MF

201

5%

1/20W

MF

33

201

5%

10K

MF

1/20W

201

0201

FERR-22-OHM-1A-0.065-OHM

X5R-CERM

1.0UF

20%

0201-1

10V

16V

PLACE_NEAR=U6750.A1

X5R-CERM

0.1UF

0201

10%

X5R-CERM

0402-1

20%

10UF

10V

7

59

7

53 54

FERR-470-OHM

CRITICAL

0201

120-OHM-25%-1.3A

0402

CRITICAL

7

53

59

7

53 54

CRITICAL

0201

FERR-33-OHM-0.8A-0.09-OHM

7

58

0402

CRITICAL

120-OHM-25%-1.3A

0402

CRITICAL

7

58

FERR-33-OHM-0.8A-0.09-OHM

CRITICAL

0201

0402

CRITICAL

120-OHM-25%-1.3A

CRITICAL

F-ST-SM

51138-0274

20%

X5R-CERM

1.0UF

0201-1

10V

1.0UF

X5R-CERM

20%

0201-1

10V

1.0UF

20%

X5R-CERM

0201-1

10V

20%

1.0UF

0201-1

X5R-CERM

10V

5%

0

1/20W

MF

MIKEY

201

5%

MF

1/20W

47K

NOSTUFF

201

SYNC_MASTER=D2_CARA

SYNC_DATE=03/16/2012

AUDIO: JACK

HS_MIC_LO

NO_TEST=TRUE

CHS_CLAMPI

HS_MIC_HI_RC

NO_TEST=TRUE

HS_HDET

NO_TEST=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

PP3V42_GH3_AUDIO_LC

CHS_CLAMPO

NO_TEST=TRUE

AUD_HP_PORT_R

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.06MM

CH_HS_GND

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.1MM

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.3MM

US_HS_GND

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.4MM

AUD_CONN_SLEEVE_XW

MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.3MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

AUD_CONN_MIC_XW

NO_TEST=TRUE

HS_MIC_BIAS

HS_MIC_HI

NO_TEST=TRUE

GND_AUDIO_CODEC

HS_RX_BP

=PP3V3_S0_AUDIO_DIG

HS_SW_DET

=PP3V42_G3H_AUDIO

AUD_CONN_TIPDET_INV

=PP3V3_S0_AUDIO_DIG

AUD_SPDIF_OUT_JACK

AUD_CONN_SLEEVE

CH_HS_MIC

AUD_CONN_TYPEDET

AUD_CONN_MIC

AUD_TYPEDET

US_HS_GND

AUDIO_SCL

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

GND_AUDIO_CODEC

AUDIO_SDA

AUD_PORTA_DET_L

US_HS_MIC

AUDIO_SDA

GND_AUDIO_CODEC

CH_HS_GND

AUD_IPHS_SWITCH_EN

AUD_I2C_INT_L

AUDIO_SCL

PP4V5_AUDIO_ANALOG

AUD_MIC_INL_N

GND_AUDIO_CODEC

HS_MIC_LO_RC

AUD_MIC_INL_P

AUD_HP_PORT_REF

U6750

A2

C4

B4

C2

B2

B3

C3

D2 B1

C1

D4

D3

D1

A3

A4

A1

C6753

1 2

C6752

1 2

R6756

1

2

R6755

1

2

U6751

D2

A2

D1

B2

B1

C2

A3

A1

D3

C1

C3

B3

C6750

1

2

R6750

1 2

C6756

1

2

C6758

1

2

R6754

1

2

C6755

1

2

R6753

1 2

R6752

1 2

R6751

12

XW6751

1 2

C6751

1

2

R6761

1 2

R6758

1 2

R6757

1 2

R6762

1

2

L6754

1 2

C6790

1

2

C6754

1

2

C6791

1

2

L6706

1 2

L6705

1 2

L6703

1 2

L6704

1 2

L6702

1 2

L6701

1 2

L6700

1 2

J6701

1

10

11 12

13 14

15 16

17 18

19

2

20

21

22

23

24

3 4

5 6

7 8

9

C6792

1

2

C6793

1

2

C6794

1

2

C6795

1

2

R6759

1 2

R6760

1

2

051-9589

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58 OF 99

53 54 58 59

8

53 58

8

53 58

7

53 54 58 59

7

58

53 54 58 59

58

53 59

53 54 58 59

53

OUT

D

SG

D

SG

IN

OUT

IN IN

IN

OUT

D

SG

OUT

NC

IN

D

SG

D

SG

OUT

G

D

S

P-CHN

D

S

G

N-CHN

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

PORT A DETECT (HEADPHONES)

FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3)

NOM R6892-C6860 FC = 106Hz

APN:376S0613

SSM6N15FE Vth = 0.8V to 1.5V

SSM6N15FE IGSS = +/-1uA

FUNCTION

NOTHING SPDIF HEADPHONE

AUDIO CONNECTOR DETECT STATES

AUD_J1_TYPEDET_R 1 1 0

0X09 (9,A)

0X0B (11)

0X10 (16)

PIRQ H

MIKEY INTERRUPT

3V3

0X0F (15) N/A

0X04 (4)

PIN COMPLEX

GPIO 3

GPIO 5

NC

N/A

0X03 (3)

FUNCTION

PIN COMPLEX

0X04 (4)

INT

VREF

N/AGPIO_3

SPDIF OUT

MUTE CONTROL

HP=80HZ

APN: 518S0627

NC

3-MIC CONNECTOR

DET ASSIGNMENT

SPEAKER CONNECTOR

CONVERTER

PORT C DETECT(SPEAKER MISMATCH)

VOLUME

CODEC OUTPUT SIGNAL PATHS

0X02 (2) 0X02 (2)

N/A

GPIO_30X0A (10)0X03 (03)

0X08 (8)

N/A

0X0C (A)

0X05 (5)

0X09 (B)

0X12 (12,C)

0X07 (7)

N/A3V3

0X06 (6)

DMIC 1

SPDIF IN

0X06 (6)

0X0D (13,V22,B,LEFT)

MIKEY MIKEY

HEADSET MIC

HP/LINE OUT

MIKEY ENABLE

SUB

0X0E (D,E)

GPIO

SATA4GP/GPIO 16

PERIPHERAL DETECT

TWEETERS

AUD_J1_TIPDET_R 0 1 1

0X0C (12,C)

N/A

Alternate Parts

AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

PIRQ F

CODEC INPUT SIGNAL PATHS

FUNCTION

SYSTEM INT AND GPIO LINES

CONVERTER

DMIC2

EXTRACTION NOTIFICATION

AUD_OUTJACK_INSERT_L 1 0 0

PORT B DETECT(SPDIF DELEGATE)

AUD_TYPEDET_OD

PP4V5_AUDIO_ANALOG

AUD_TYPEDET

AUD_TYPEDET_OD

GND_AUDIO_CODEC

AUD_SENSE_A

AUD_TYPEDET_OD_INV

AUD_OUTJACK_INSERT_L

SPKRCONN_SL_OUT_N

AUD_PORTB_DET_L

=PP5V_S4_AUDIO

MCP6514_POS

AUD_IP_PERIPHERAL_DET

AUD_OUTJACK_INSERT_L

=PP5V_S4_AUDIO

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

SPKR_MATCH_DRV_R

AUD_TIPDET_FET1

=PP5V_S4_AUDIO

=PP3V3_S0_AUDIO

CON_DMIC_CLK

CON_DMIC_SDA2

AUD_DMIC_SDA1 CON_DMIC_SDA1

SPKRCONN_L_OUT_N

SPKRCONN_SL_OUT_P

GND_AUDIO_CODEC

SPKR_MATCH_DRV

SPKRCONN_L_ID

SPKRCONN_SR_OUT_N

SPKRCONN_R_OUT_N

SPKRCONN_L_OUT_P

AUD_SENSE_A

AUD_PORTC_DET_L

SPKRCONN_R_OUT_P

SPKRCONN_R_ID

CON_DMIC_PWR

AUD_DMIC_SDA2

AUD_DMIC_CLK

SPKRCONN_L_ID

SPKRCONN_SR_OUT_P

MCP6514_OUT

AUD_TIPDET_INV

=PP3V3_S0_AUDIO

AUD_CONN_TIPDET_INV

MCP6514_NEG

SPKRCONN_R_ID

AUD_PORTA_DET_L

AUD_TIPDET_FET2

GND_AUDIO_CODEC

353S3452 353S1286

MAXIM ALT TO MICROCHIP

U6800

SYNC_MASTER=D2_CARA

SYNC_DATE=03/16/2012

AUDIO: JACK TRANSLATORS

DMC2400UV

SOT563

DMC2400UV

59

19

402

MF-LF

1/16W

5%

0

SOT563

SSM6N15FEAPE

10%

1UF

402X5R 25V

FERR-33-OHM-0.8A-0.09-OHM

0201

CRITICAL

47K

201

MF

5%

1/20W

475K

201

MF

1%

SOT563

SSM6N15FEAPE

10%

1UF

402X5R 25V

402

MF-LF

1%

1.5K

1/16W

58

150K

1/20W

MF

201

1%

402

0

5%

1/16W

MF-LF

402

MF-LF

5%

0

1/16W

402

MF-LF

1/16W

0

5%

59

402

33

5%

1/16W

MF-LF

SPEAKERID

96 57

7

96 57

7

96 57

7

96 57

7

59

7

96 57

7

59

7

96 57

7

96 57

7

96 57

7

53

FERR-1000-OHM

SPEAKERID

0402

59 53

402

MF-LF

1/16W

10K

1%

SPEAKERID

SSM6N15FEAPE

SOT563

SPEAKERID

100K

5%

1/20W

MF

201

59

58

7

402

1/16W

MF-LF

1%

SPEAKERID

100K

402

100K

MF-LF

1%

1/16W

SPEAKERID

402

SPEAKERID

MF-LF

1%

1/16W

100K

402

SPEAKERID

1%

MF-LF

1/16W

274K

402

45.3K

SPEAKERID

1%

MF-LF

1/16W

20%

10V

X5R-CERM

0402

4.7UF

SPEAKERID

CRITICAL

59

7

59

7

X5R

0.1UF

6.3V

10%

201

SPEAKERID

402

MF-LF

SPEAKERID

1/16W

1%

90.9K

402

1%

100K

MF-LF

1/16W

SPEAKERID

402

100K

1%

MF-LF

1/16W

SPEAKERID

MCP6541T

SC70-5

SPEAKERID

CRITICAL

M-RT-SM

CRITICAL

78171-6006

CRITICAL

78171-6006

M-RT-SM

53

402

MF-LF

1/16W

0

5%

F-RT-SM

FF14A-5C-R11DL-B-3H

CRITICAL

1/20W

5%

MF

201

100K

X5R

PLACE_NEAR=Q6800.4

0.1UF

10%

201

6.3V

59

SOT563

SSM6N15FEAPESSM6N15FEAPE

SOT563

402

1%

MF-LF

1/16W

39.2K

59 53

402

1%

1/16W

MF-LF

20.0K

R6896

1

2

R6895

1

2

Q6897

6

21

Q6896

3

54

C6800

1

2

R6802

12

J6801

7

6

1

2

3

4

5

R6885

1 2

J6802

7

8

1

2

3

4

5

6

J6803

7

8

1

2

3

4

5

6

U6800

3

4

1

5

2

R6810

1

2

R6811

1

2

R6815

1

2

C6810

1

2

C6811

1

2

R6817

1 2

R6814

1

2

R6812

1

2

R6813

1

2

R6816

1 2

R6803

12

Q6896

6

21

R6894

1

2

L6802

1 2

R6820

1 2

R6884

1 2

R6883

1 2

R6886

1 2

R6801

1

2

R6892

1 2

C6860

1

2

Q6803

6

21

R6866

1

2

R6865

1

2

L6801

1 2

C6891

1

2

Q6897

3

54

R6867

1 2

Q6800

3

5

4

Q6800

6

2

1

051-9589

4.18.0

68 OF 132

59 OF 99

59 58 53

59 58 54 53

59 53

8

59 53

8

59 58 53

59 58 54 53

59 53

8

59

8

7

59 58 54 53

7

59

8

58

59 58 54 53

VCC

EXT INT

NC GND

NC

NEG

SCL

POS

SDA

SYS_DETECT

NEG

POS

NC

GND

THRM

IN_A

IN_B1

IN_B2

OUT_C

OUT_D1

OUT_D2

VDD

PAD

BI

NC

G

D

S

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

IN

Y

B

A

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OF 1 OZ CU FOR THERMAL

Q0220 NEEDS 10 SQ CM

for 15" MBP design only

sparkitecture requirements

Input impedance of 22.1K meets

connected.

The chassis ground will otherwise float and can

send transients onto ADAPTER_SENSE when AC is

1-Wire OverVoltage Protection

TDM LEVEL SHIFT

518-0376

518S0508

LAYOUT NOTE:

BATTERY CONNECTOR

100MA MAX OUTPUT

(Switcher limit)

Vout = 3.425V

<Ra>

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

MagSafe DC Power Jack

When input voltage is at 16V+, FET will

When input voltage is 2V the FET will be off

6.8V Zener

3.425V "G3Hot" Supply

conduct and power charger and 3.42V reg

properly detected.

blocking the leakage path and 22.1K can be

Supply needs to guarantee 3.31V delivered to SMC VRef generator

20%

0603

CERM

50V

0.01UF

MAX9940

SC70-5

CRITICAL

10%

25V

X5R

0.1UF

402

10%

25V

X5R

1UF

603-1

RCLAMP2402B

SC-75

CRITICAL

MF-LF

5%

10K

402

1/16W

50V

5%

22PF

0201

NP0-C0G-CERM

201

1/20W

1%

MF

200K

20%

603

X5R-CERM-1

6.3V

22UF

201

MF

348K

1%

1/20W

5%

MF-LF

805

1/8W

10

MF

1/3W

47

1%

805

BAT30CWFILM

SOT-323

CRITICAL

DP418C-SM

33UH-20%-0.39A-0.435OHM

CRITICAL

0.22UF

CERM

10V

10%

402

BAT-J5

F-ST-TH

CRITICAL

WTB-PWR-M82

M-RT-SM

5%

201

TDM:MLB

22

MF

1/20W

CRITICAL

SLG4AP030

TDM:MLB

TDFN

201

TDM:MLB

2.21K

MF

1/20W

201

6.34K

MF

1%

TDM:MLB

1/20W

201

MF

1/20W

TDM:MLB

1%

54.9

201

MF

1/20W

1%

24.9K

TDM:MLB

SOD523

DDZ9694T

CRITICAL

TDM:MLB

SOT723

MMBT2222AM3T5G

CRITICAL

TDM:MLB

12.1

805

1/8W

MF-LF

1%

TDM:MLB

12.1

1%

1/8W

MF-LF

805

TDM:MLB

CRITICAL

ZXTN619MA

DFN

TDM:MLB

41

5%

TDM:MPM

MF

22

1/20W

201

402

5%

MF-LF

2.0K

1/16W

POWERPAK

SI5419DU

1/20W

MF

201

5%

100K

201

MF

1/20W

1%

22.1K

GDZ-0201

GDZT2R6.8

0603

X5R-CERM

10%

35V

4.7UF4.7UF

0603

10%

35V

X5R-CERM

NOSTUFF

0603

4.7UF

35V

10%

X5R-CERM

10%

35V

X5R-CERM

4.7UF

0603

4.7UF

NOSTUFF

0603

35V

10%

X5R-CERM

4.7UF

10%

35V

X5R-CERM

0603

NOSTUFF

0402

X5R

25V

10%

0.047UF

201

10K

5%

1/20W

MF

DFN

CRITICAL

LT3470AED

0.1UF

CERM

402

20%

10V

41 42

CRITICAL

TC7SZ08FEAPE

SOT665

10V

20%

402

CERM

0.1UF

DC-In & Battery Connectors

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

SMC_BC_ACOK_VCC

TDM_RX

MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P3V42G3H_SW

P3V42G3H_BOOST

DIDT=TRUE

=PP3V42_G3H_REG

P3V42G3H_FB

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PP18V5_DCIN_CONN_R

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=18.5V

PPBUS_G3H_R

MIN_NECK_WIDTH=0.25 mm

=PP18V5_DCIN_ISOL

SYS_DETECT_L

=PPBUS_G3H

TDM_ONEWIRE_MLB

=SMBUS_BATT_SCL

TDM_PD_BASE_R

TDM_PD_DS

=PP3V42_G3H_TDM

TDM_RX_D

=SMBUS_BATT_SDA

PPVBAT_G3H_CONN

DCIN_ISOL_GATE

DCIN_ISOL_GATE_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20MM

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=1MM

TDM_PD_BASE

PPVIN_G3H_P3V42G3H

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

ADAPTER_SENSE

SMC_BC_ACOK

SYS_ONEWIRE

TDM_ONEWIRE_MPM

SYS_TDM_ONEWIRE

1%

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

=PP3V42_G3H_ONEWIREPROT

6AMP-32V-0.0095OHM

0603

CRITICAL

=PP18V5_DCIN_CONN

C6905

1

2

U6900

5

2

4

1

C6950

1

2

C6960

1

2

D6950

3

1

2

R6950

1

2

C6995

1

2

R6996

1

2

C6999

1

2

R6995

1

2

R6905

1 2

R6920

1 2

D6905

1

2

3

L6995

1 2

C6994

1

2

J6950

1021

1122

112

213

314

415

516

617

718

819

920

J6900

1

2

3

4

5

6

R6976

1 2

U6970

5

2

4

7

6

3

8

9

1

R6975

1

2

R6974

1

2

R6972

1

2

R6973

1

2

D6970

A

K

Q6971

1

3

2

R6971

1

2

R6970

1

2

Q6970

1

2

3

R6977

1

2

R6929

1

2

Q6910

1

4

5

5A

R6910

1

2

R6912

1

2

D6910

A

K

C6991

1

2

C6990

1

2

C6992

1

2

C6993

1

2

C6996

1

2

C6997

1

2

C6912

1

2

R6911

1 2

U6990

2

3

1

5

8 4

9

6

C6908

1

2

U6901

2

1

3

5

4

C6900

1

2

F6905

1 2

051-9589

4.18.0

69 OF 132

60 OF 99

3

7

8

7

8

61

44

8

44

7

61

7

8

7

8

苹果笔记本维修交流群群号：３２５７４２６３４

OUT

IN

BI

OUT

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

G

D

S

IN

NC

G

S

D

S

D

NC NC

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

20V/V

Sparkitecture impedance is set by R6912 in 15" MBP

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V

(CHGR_DCIN)

(CHGR_SGATE)

Reverse-Current Protection

For EMC

Inrush Limiter

(CHGR_CSO_N)

30mA max load

FROM ADAPTER

<Ra>

<Rb>

100MA MAX OUTPUT

(Switcher limit)

152S1466

Max Current = 8A

f = 400 kHz

(L7030 limit)

(OD)

353S2392

(PPVBAT_G3H_CHGR_R)

(CHGR_AGATE)

(CHGR_BGATE)

(AGND)

36V/V

TO/FROM BATTERY

Vout = 1.25V * (1 + Ra / Rb)

Vout = 5.50V

(GND)

(PPVBAT_G3H_CHGR_R)

(CHGR_CSO_P)

(P5V1_BIAS)

TO SYSTEM

For Erp Lot6 spec

10%

10V

X5R-CERM

0402

0.068UF

10%

470PF

0402

CERM

50V

402

MF-LF

3.01K

1/16W

1%

10%

50V

220PF

X7R-CERM

0402

402

330K

MF-LF

1/16W

5%

10%

X5R

402

1UF

10V

10%

402-1

X5R

1UF

10V

402

4.7

MF-LF

1/16W

5%

10%

16V

0402

0.01UF

X7R-CERM

10%

0.1UF

0402

X7R-CERM

16V

SM

PLACE_NEAR=U7000.22:1mm

PLACE_NEAR=U7000.29:1mm

10%

X5R

402

1UF

10V

402

10%

0.1UF

X5R

25V

10%

0.1UF

X5R

402

25V

10%

X5R-CERM

0402

10V

0.047UF

10%

402

CERM

PLACE_NEAR=U7000.25:2mm

0.22UF

10V

CRITICAL

LFPAK-HF

RJK0305DPB

402

10

1/16W

5%

MF-LF

402

MF-LF

10

5%

1/16W

402

2.2

1/16W MF-LF

5%

402

0

1/16W MF-LF

5%

46

44

10%

16V

0402

0.01UF

X7R-CERM

10%

X5R

16V

402

1UF

10%

50V

0402

X7R-CERM

42 45

0.5%

0612

0.020

1W

MF-LF

CRITICAL

10%

50V

0402

0.001UF

X7R-CERM

10%

50V

0.001UF

ISL6259

CRITICAL

TQFN

402

NO STUFF

MF-LF

100K

5%

70

SI7137DP

SO-8

CRITICAL

SOT-323

BAT30CWFILM

CRITICAL

402

1K

MF-LF

1/16W

1%

LFPAK-SM

CRITICAL

RJK0332DPB-01

16V

68UF

CASE-D2E-SM

POLY-TANT

20%

402

20

MF-LF

1/16W

5%

10%

X5R

35V

CRITICAL

1UF

603

10%

X5R

1UF

35V

603

CRITICAL

10%

X5R

25V

1UF

603-1

402

MF-LF

1/16W

5%

0

10%

0.1UF

X5R

402

25V

MF-LF

402

1/16W

1%

470K

402

332K

402

1/16W

MF-LF

5%

62K

402

100K

5%

MF-LF

1/16W

DIRECTFET-MC

IRF9395TRPBF

CRITICAL

0.005

MF

CRITICAL

1%

1W

0612

NO STUFF

MF

1W

1%

0.001

CRITICAL

0612

PIME173T-SM

4.7UH-20%-14.5A-9MOHM

CRITICAL

CASE-D2-SM

TANT-POLY

10UF

20%

35V

CRITICAL

CASE-D2-SM

20%

35V

TANT-POLY

CRITICAL

10UF

CRITICAL

20%

CASE-D2-SM

35V

TANT-POLY

10UF

20%

35V

TANT-POLY

10UF

CRITICAL

CASE-D2-SM

10UF

20%

35V

TANT-POLY

CRITICAL

CASE-D2-SM

402

0

5%

MF-LF

1/16W

681K

1%

1/20W

MF

201

X5R

10UF

CRITICAL

20%

0603

10V

1/20W

1%

MF

200K

201

10%

402

CERM

0.22UF

10V

DP418C-SM

CRITICAL

33UH-20%-0.39A-0.435OHM

50V

0201

22PF

5%

NP0-C0G-CERM

10%

X5R-CERM

0805

35V

4.7UF

CRITICAL

DFN

LT3470A

402

NOSTUFF

0

MF-LF 1/16W

5%

402

CHGR_5V:LDO

0

1/16W

MF-LF

5%

X5R

10UF

20%

CRITICAL

0603

10V

402

CHGR_5V:LDO

0

1/16W

MF-LF

5%

10%

50V

0.22UF

X5R-CERM

0603-1

402

MF-LF

1/16W

1%

130K

402

MF-LF

1/16W

1%

40.2K

NO STUFF

0603

X5R-CERM

25V

10%

4.7UF

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

PBus Supply & Battery Charger

=PPDCIN_S5_CHGR_ISOL

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

VOLTAGE=5.1V

PPVBAT_G3H_CHGR_R

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.6V

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_CHGR

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

P5V1_SW

DIDT=TRUE

P5V1_BOOST

DIDT=TRUE

VOLTAGE=5.1V

PP5V1_CHGR_VDDP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

DIDT=TRUE

CHGR_BOOT

DIDT=TRUE

CHGR_UGATE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

CHGR_LGATE

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

PPVBAT_G3H_CONN

MIN_NECK_WIDTH=0.25 mm

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

CHGR_DCIN_D_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

P5V1_BIAS

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

CHGR_CSO_P

CHGR_CSO_N

=CHGR_ACOK

CHGR_BMON

CHGR_BGATE

CHGR_VCOMP_R

CHGR_ICOMP

PP5V1_CHGR_VDDP

CHGR_DCIN

CHGR_DCIN_D_R

SMC_RESET_L

CHGR_CSO_R_N

CHGR_CSO_R_P

CHGR_AMON

CHGR_VCOMP

=SMBUS_CHGR_SCL

GND_CHGR_AGND

CHGR_VFRQ

CHGR_RST_L

CHGR_VNEG

CHGR_ICOMP_RC

=SMBUS_CHGR_SDA

CHGR_CSI_R_N

P5V1_FB

CHGR_CSI_R_P

CHGR_SGATE

CHGR_AGATE

CHGR_VNEG_R

CHGR_CELL

CHGR_ACIN

=PPDCIN_S5_CHGR

CHGR_AGATE_DIV

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=18.5V

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm

CHGR_CSI_N

CHGR_DCIN

CHGR_CSI_P

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE

=PP3V42_G3H_CHGR

1/16W

X7R-CERM

=PPBUS_G3H

CRITICAL

0603

8AMP-32V-0.006OHM

CRITICAL

8AMP-32V-0.006OHM

0603

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.25 mm

1%

1/16W

MF-LF

0.001UF

MIN_LINE_WIDTH=0.6 mm

0402

CRITICAL

OMIT_TABLE

C7042

1

2

C7016

1

2

R7016

1

2

C7015

1

2

R7015

1

2

C7002

1

2

C7000

1

2

R7001

1 2

C7057

1

2

C7056

1

2

XW7000

1 2

C7001

1

2

C7021

1

2

C7022

1

2

C7020

1

2

C7025

1

2

Q7035

5

4

1 2 3

R7022

1 2

R7021

1 2

R7051

1 2

R7052

1 2

C7011

1

2

C7050

1

2

C7026

1

2

R7020

2

1

4

3

C7037

1

2

C7045

1

2

U7000

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11

10

26

13

29

24

7

19

20

4

12

8

R7002

1

2

Q7055

5

4

1 2 3

D7005

1

2

3

R7012

1

2

Q7030

5

4

1 2 3

C7040

1

2

R7005

1 2

C7035

1

2

C7036

1

2

C7055

1

2

R7000

1 2

C7085

1

2

R7085

1

2

R7086

1

2

R7081

1

2

R7080

1

2

Q7080

8

7

9

10

6

3

4

1

5

2

R7050

2 1

4 3

R7055

2 1

4 3

L7030

1 2

C7030

1

2

C7031

1

2

C7032

1

2

C7033

1

2

C7034

1

2

R7042

1

2

R7095

1

2

C7098

1

2

R7096

1

2

C7094

1

2

L7095

1 2

C7095

1

2

C7090

1

2

U7090

2

3

1

5

8 4

9

6

R7090

1 2

R7091

1 2

C7099

1

2

R7092

1 2

C7005

1

2

R7010

1

2

R7011

1

2

C7080

1

2

F7041

1 2

F7040

1 2

051-9589

4.18.0

70 OF 132

61 OF 99

7

8

61

7

60

61

94

61

96

61

96

8

94

61

94

8

70

60

8

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

152S1302

(ENDIAN SWAP)

INTEL TABLE:

0 0 0.9V

0 1 0.725V

1 1 0.675V

1 0 0.8V

f = 300 kHz

OCP = 8.5A

OCP = R7141 x 8.5uA / R7140

(VCCSAS0_VO)

6A Max Output

(VCCSAS0_OCSET)

376S0944

VID1 VID0 Voltage

Vout<0,0> = Vref x (1+ (R7147 / (R7148 + R7149 // R7150 )) x fb

Vout<1,0> = Vref x (1+ (R7147 + R7148) / R7149 )) x fb

Vout<0,1> = Vref x (1+R7147 / (R7148 + R7149 )) x fb

fb = (R7151+R7152)/R7152 = 1.349 and Vref = 0.5;

VID1=0, VID0=0

VID1=1, VID0=0

VID1=0, VID0=1:

Vout<1,1> = Vref x fb;

VID1=1, VIC0=1:

CPU_VCCSASENSE_DIV

VCCSAS0_AGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

VCCSAS0_OCSET

VCCSAS0_RTN_DIV

CPU_VCCSA_VID<0>

VCCSAS0_CS_P

VCCSAS0_CS_N

VCCSAS0_VO

PVCCSA_PGOOD

=PVCCSA_EN

=PPVCCSA_S0_REG

=PP5V_S0_VCCSAS0

=PPVIN_S0_VCCSAS0

CPU_VCCSASENSE

VCCSAS0_SET0

VCCSAS0_SET1

CPU_VCCSA_VID<1>

VCCSAS0_SET_R

VCCSAS0_FSEL

VCCSAS0_SREF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VCCSAS0_VBST

DIDT=TRUE

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

DIDT=TRUE

VCCSAS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_DRVL

VCCSAS0_DRVH

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

VCCSAS0_RTN

PP5V_S0_VCCSAS0_VCC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_LL

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

System Agent Supply

10%

16V

603

X5R

2.2UF

402

MF-LF

1/16W

1%

1.5K

402

MF-LF

1/16W

1%

1.5K

5%

10PF

0402

C0G-CERM

50V

402

1%

1/16W

MF-LF

499K

402

52.3K

MF-LF

1/16W

1%

5%

402

MF-LF

1/16W

0

402

41.2K

MF-LF

1/16W

1%

402

1%

1/16W

MF-LF

82.5K

402

1.62K

MF-LF

1/16W

1%

402

1.62K

1/16W

1%

MF-LF

4.64K

402

1%

MF-LF

1/16W

402

4.64K

1%

1/16W

MF-LF

RJK0222DNS

HWSON

CRITICAL

89 13

SM

X5R-X7R-CERM

10%

16V

0.022UF

0402

CRITICAL

25V

X5R-CERM

0603

10UF

20%

89 13

CRITICAL

UTQFN

ISL95870AH

C0G-CERM

5%

10PF

0402

50V

10%

0.1UF

0402

X7R-CERM

16V

CRITICAL

25V

X5R-CERM

0603

10UF

20%

1.0UH-7A

CRITICAL

PIMB053T-SM

MF-1

0.001

CRITICAL

1%

1W

0612

5%

402

PLACE_NEAR=Q7100.2:1.5mm

NP0-C0G

1000PF

25V

5%

402

1000PF

NP0-C0G

25V

402

CERM

10%

0.22UF

10V

5%

603

0

1/10W

MF-LF

10V

20%

X5R

603

10UF

5%

402

MF-LF

2.2

1/16W

SM

PLACE_NEAR=U7100.3:1mm

70

C7105

1

2

C7103

1

2

R7103

1

2

C7102

1

2

XW7100

1 2

R7101

1

2

C7101

1

2

R7130

1

2

C7130

1

2

C7140

12

C7122

1

2

R7140

2 1

4 3

L7100

1 2

C7120

1

2

C7121

1

2

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

C7119

1

2

XW7101

1

2

Q7100

2

1

6

7

3 4 5

R7154

1

2

R7152

1

2

R7153

1 2

R7151

1 2

R7150

1 2

R7147

1

2

R7148

1

2

R7149

1

2

C7106

1

2

R7142

1

2

R7141

1

2

051-9589

4.18.0

71 OF 132

62 OF 99

96 45

99

8

OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

100MA MAX OUTPUT

F = 400 KHZ

(P5VP3V3_VREF2)

152S0688

VOUT = 5.0V

11A MAX OUTPUT

VOUT = 5V

VOUT = 3.3V

F = 400 KHZ

10A MAX OUTPUT

152S0754

(P5VP3V3_VREF2)

CRITICAL CRITICAL CRITICAL CRITICAL

OMIT_TABLEOMIT_TABLEOMIT_TABLE OMIT_TABLE

68UF

POLY-TANT

1/16W

P5VP3V3_VREF2

P3V3S5_COMP2_R

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0V

P3V3S5_VFB2

P3V3S5_CSN2

P3V3S5_CSP2_R

P3V3S5_COMP2

DIDT=TRUE

P3V3S5_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=P3V3S5_EN

P5VS4_COMP1_R

P5VS4_VFB1

P5VS4_CSN1

=P5VS4_EN

=PP5V_S4_REG

=PP3V3_S5_REG

=PP5V_S4_REG

P5VS4_VFB1_R

P3V3S5_VFB2_R

=P5VS5_EN

P3V3S5_CSP2

P3V3S5_PGOOD

=PP5V_S5_LDO

P5VP3V3_VREG3

P5VP3V3_SKIPSEL

P5VS4_PGOOD

P5VS4_CSP1_R

P3V3S5_RF

P5VS4_CSP1

=PPVIN_S5_P5VP3V3

P5VS4_COMP1

MIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P5VS4_DRVH

P3V3S5_LL

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

SWITCH_NODE=TRUE

P3V3S5_VBST

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS4_VBST

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P3V3S5_TG

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P3V3S5_SNUBR

DIDT=TRUE

P5VS4_TG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

DIDT=TRUE

P5VS4_LL

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P3V3S5_DRVH

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P5VS4_VSW

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS4_DRVL

DIDT=TRUE

5V / 3.3V Power Supply

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

CERM

100V

10%

4700PF

402

CERM

100V

10%

4700PF

402

PCMB103T-1R0MS

CRITICAL

1.0UH-21A-0.006OHM

20%

150UF

CASE-B2-SM

POLY-TANT

6.3V

CRITICAL

150UF

20%

6.3V

CASE-B2-SM

6.3V

CASE-B2-SM

POLY-TANT

20%

150UF

CRITICAL

NOSTUFF

SKIP_5V3V3:INAUDIBLE

5%

MF

0

1/20W

201

5%

SKIP_5V3V3:AUDIBLE

MF

1/20W

0

201

CRITICAL

SON5X6

CSD58872Q5D

PLACE_NEAR=U7200.28:1MM

SM

50V

NO STUFF

X7R-CERM

0402

0.001UF

10%

70

603-1

25V

1UF

X5R

10%

402

5%

1

1/16W

MF-LF

402

5%

0

1/16W

MF-LF

402

3.83K

1/16W

MF-LF

1%

402

1.43K

1%

1/16W

MF-LF

CRITICAL

RJK0214DPA

WPAK2

70

20%

68UF

POLY-TANT

CASE-D2E-SM

16V

20%

CASE-D2E-SM

68UF

POLY-TANT

16V

CRITICAL

TPS51980

QFN

50V

X7R-CERM

0402

0.001UF

10%

50V

X7R-CERM

0402

0.001UF

10% 50V

X7R-CERM

0402

0.001UF

10%

50V

X7R-CERM

0402

0.001UF

10%

5%

NO STUFF

1/10W

10

603

MF-LF

5%

MF-LF

NO STUFF

1/10W

1

603

50V

NO STUFF

X7R-CERM

0402

0.0033UF

10%

70

402

12.1K

MF-LF

1%

1/16W

402

CERM

50V

47PF

5%

402

1/16W

MF-LF

10K

1%

20%

6.3V

CASE-D3L-SM

POLY-TANT

CRITICAL

330UF

SM

PLACE_NEAR=L7220.1:3MM

SM

PLACE_NEAR=L7260.2:3MM

5%

150PF

0402

C0G-CERM

50V

402

10K

1/16W

1%

MF-LF

402

1/16W

MF-LF

1%

12.1K

PLACE_NEAR=L7220.2:3MM

SM

PLACE_NEAR=L7220.1:3MM

SM

402

3.92K

1/16W

1%

MF-LF

402

3.24K

1/16W

MF-LF

1%

16V

X7R-CERM

0402

0.1UF

10%

PLACE_NEAR=L7260.1:3MM

SM

16V

X7R-CERM

0402

0.1UF

10%

20%

POLY-TANT

CASE-D2E-SM

16V 20%

68UF

POLY-TANT

CASE-D2E-SM

16V

402

MF-LF

10K

1%

402

40.2K

1/16W

MF-LF

1%

402

MF-LF

1%

1/16W

10K

402

1/16W

1%

MF-LF

23.2K

402

CERM

0.22UF

10V

10%

PLACE_NEAR=L7260.2:3MM

SM

70

402

1%

249K

1/16W

MF-LF

603

6.3V

10UF

20%

X5R

402

20%

10V

X5R-CERM

2.2UF

1UF

603-1

25V

X5R

10%

20%

805

10V

CRITICAL

10UF

X5R

20%

6.3V

CASE-D3L-SM

330UF

POLY-TANT

CRITICAL

50V

603-1

X7R

0.1UF

10%

20%

6.3V

10UF

603

X5R

50V

X7R

603-1

0.1UF

10%

CRITICAL

1.0UH-22A

PCMC063T-SM

25V

1UF

603-1

X5R

10%

C7200

1

2

L7260

12

C7264

1

2

C7290

1

2

C7224

1

2

C7252

1

2

C7250

1

2

C7281

1

2

C7203

1

2

C7205

1

2

R7206

1

2

XW7261

1

2

C7201

1

2

R7260

1

2

R7261

1

2

R7220

1

2

R7221

1

2

C7280

1

2

C7240

1

2

C7288

1 2

XW7260

1

2

C7218

1 2

R7247

1 2

R7256

1

2

XW7220

1

2

XW7221

1

2

R7236

1

2

R7237

1

2

C7237

1

2

XW7262

1

2

XW7222

1

2

C7292

1

2

R7239

1

2

C7239

1

2

R7238

1

2

C7299

1

2

R7299

1

2

R7298

1

2

C7272

1

2

C7283

1

2

C7270

1

2

C7271

1

2

U7201

10 15

8

17

7

18

1

24

30 27

12

4

21

28

11

14

5

20

3

6

19

32 25

33

2

31 26

9

16

23

13

22

29

C7242

1

2

C7282

1

2

Q7260

2

1

6

7

345

R7246

1 2

R7216

1

2

R7263

1 2

R7244

1

2

C7241

1

2

C7298

1

2

XW7200

1

2

Q7220

5

9

3

4

1

6

7

8

R7200

1

2

R7201

1

2

C7253

1

2

C7254

1

2

C7293

1

2

L7220

1

2

C7236

1

2

C7238

1

2

72 OF 132

4.18.0

051-9589

63 OF 99

63

8 8

63

8

IN

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

VSW

PGND

TGR

TG

BG

VIN

D

G S

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Q7335 limit)

18A max output

DDR3 (1V5R1V35 S3) REGULATOR

Vout = 1.5V

f = 400 kHz

(DDRREG_LL)

(DDRREG_DRVL)

10mA max load

(DDRREG_DRVH)

(DDRREG_VDDQSNS)

(VTT Enable)

(VDDQ/VTTREF Enable)

152S0905

C7360, C7361 close to memory

10V

10UF

20%

603

X5R

POLY-TANT

CASE-D2E-SM

CRITICAL

68UF

16V

5%

1

1/16W

MF-LF

402

POLY-TANT

20%

CASE-D2E-SM

CRITICAL

16V

1UF

603-1

25V

X5R

10%

50V

603-1

X7R

0.1UF

10%

0.001UF

0402

50V

X7R-CERM

10%

20%

TANT

2V

CASE-B4-SM

270UF

CRITICAL

PCMB103T

0.68UH-18A-3.3MOHM

2V

TANT

270UF

20%

CRITICAL

CASE-B4-SM

6.3V

20%

603

10UF

X5R

0.001UF

0402

50V

X7R-CERM

10%

SM

PLACE_NEAR=C7340.1:1MM

70

QFN

TPS51916

CRITICAL

88

SM

PLACE_NEAR=C7361.1:3mm

PLACE_NEAR=U7300.7:1mm

SM

10V

CERM

0.22UF

402

10%

PLACE_NEAR=C3101.1:1mm

6.3V

603

20%

10UF

X5R

9

27

X7R-CERM

0402

16V

0.1UF

10%

603

20%

PLACE_NEAR=C3101.1:3mm

10UF

6.3V

X5R

1/16W

MF-LF

1%

200K

402

OMIT_TABLE

1/16W

MF-LF

20.0K

1%

402

OMIT_TABLE

100K

MF-LF

1/16W

1%

402

0.01UF

0402

X7R-CERM

16V

10%

10V

10UF

20%

603

X5R

603-1

25V

1UF

X5R

10%

SON5X6

CSD58872Q5D

CRITICAL

NOSTUFF

SSM3K15FV

SOD-VESM-HF

150K

NOSTUFF

MF-LF

1/16W

1%

402

18

MF-LF

1/16W

1%

61.9K

402

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

1V5R1V35V DDR3 SUPPLY

PPDDR:1V35

R7315

1

RES,MTL FILM,1/16W,19.6K,1,0402,SMD,LF

114S0342

PPDDR:1V5

R7315

RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF

1

114S0343

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

114S0411

R7316

1

PPDDR:1V5

RES,MTL FILM,1/16W,57.6K,1,0402,SMD,LF

114S0389

R7316

1

PPDDR:1V35

=PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.17 mm

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND_DDRREG_SGND

DDRREG_TRIP

DDRREG_MODE

=PPVIN_S0_DDRREG_LDO

=DDRREG_EN

DDRREG_1V8_VREF

DDRREG_VTTSNS

=PPDDR_S3_REG

DDRREG_PGOOD

=PPVTT_S0_DDR_LDO

MEM_VDD_SEL_1V5_L

DDRREG_P1V35_L

=PPVIN_S3_DDRREG

=DDRVTT_EN

DDRREG_FB

=PP5V_S3_DDRREG

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_LL

DIDT=TRUE

SWITCH_NODE=TRUE

DDRREG_VSW

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH_R

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVH

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVL

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VDDQSNS

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

68UF

20%

OMIT_TABLEOMIT_TABLE

C7300

1

2

C7330

1

2

R7330

1 2

C7331

1

2

C7332

1

2

C7325

1 2

C7333

1

2

C7340

1

2

L7330

1 2

C7341

1

2

C7345

1

2

C7346

1

2

XW7301

1

2

U7300

14

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

XW7360

1 2

XW7300

1

2

C7350

1

2

C7360

1

2

C7315

1

2

C7361

1

2

R7317

1

2

R7315

1

2

R7316

1

2

C7316

1

2

C7301

1

2

C7334

1

2

Q7330

5

9

3

4

1

6

7

8

Q7319

3

12

R7319

1

2

R7318

1

2

051-9589

4.18.0

73 OF 132

64 OF 99

8

33

8

33

8

BI

IN

OUT

IN

OUT

IN

OUT

IN

CSPA3

DRVPWMA

POKB

POKA

CLK

VRHOT*

THRM

GNDSB

SR

THERMB

THERMA

DRVPWMB

VDIO

EN

ALERT*

AGND

GNDSA

CSPBAVE

IMAXB

IMAXA

TONB

TONA

LXA1

DHA1

BSTA1

CSPA1

DLA1

CSPAAVE

CSNA

FBA

CSPA2

LXA2

BSTA2

DHA2

DLA2

BSTB

DHB

LXB

DLB

PGNDA

PGNDB

FBB

CSPB1

CSPB2

CSNB

VDDB

VCC

VDDA

PAD

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPUIMVP_AXG_PWM2

CPUIMVP_UGATE1

CPUIMVP_TONA

CPUIMVP_FBA_R

CPUIMVP_ISUM1P

CPUIMVP_ISUMG_AVEP

CPUIMVP_PHASE1

CPUIMVP_UGATE1G

CPUIMVP_BOOT1G

CPUIMVP_FBB_R

CPUIMVP_FBA

CPUIMVP_ISNS3_P

CPUIMVP_ISUM3P

CPUIMVP_PWM3

CPU_PROCHOT_L

CPUIMVP_IMAXB

CPU_AXG_SENSE_R

=PP5V_S0_CPUIMVP

=PPVIN_S0_CPUIMVP

CPUIMVP_PGOOD

CPUIMVP_FBB

CPUIMVP_TONB

CPUIMVP_ISNS1_P

CPUIMVP_ISNS2_P

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

CPU_VCCSENSE_NCPU_VCCSENSE_R

CPUIMVP_FBB

CPUIMVP_AXG_PGOOD

CPUIMVP_LGATE1G

CPU_AXG_SENSE_N

CPUIMVP_LGATE1

CPUIMVP_PHASE1G

CPUIMVP_FBA

CPUIMVP_ISUM2P

CPUIMVP_PHASE2

CPUIMVP_UGATE2

CPUIMVP_BOOT2

CPUIMVP_LGATE2

CPUIMVP_NTC

CPUIMVP_BOOT1

CPUIMVP_ISUMGN

CPUIMVP_ISUM

CPUIMVP_ISUMG2P

CPUIMVP_ISUMG1P

CPUIMVP_ISUM_R

CPUIMVP_ISUMN

=PPVCCIO_S0_CPUIMVP

CPUIMVP_VR_ON

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP5V_S0_CPUIMVP_VCC

GND_CPUIMVP_SGND

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

CPUIMVP_NTCG

CPUIMVP_SLEW

CPUIMVP_IMAXA

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

CPU IMVP7 & AXG VCore Regulator

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

0201

NO STUFF

470PF

X5R-X7R-CERM

16V

10%

5%

100PF

0201

NP0-CERM

25V

NO STUFF

NP0-CERM

0201

25V

100PF

5%

66

1/20W

MF

182K

1%

201

66

66 65

QFN

MAX15119GTM

CRITICAL

1%

MF

1/20W

200K

201

200K

1%

MF

1/20W

NO STUFF

201

100KOHM

CRITICAL

0402

PLACE_NEAR=Q7550.1:6mm

0402

CRITICAL

100KOHM

PLACE_NEAR=Q7510.1:7mm

1/20W

MF

1%

300

SIGNAL_MODEL=EMPTY

201

SIGNAL_MODEL=EMPTY

MF

1/20W

1%

300

201

130

1%

1/20W

MF

201

PLACE_NEAR=U7400.16:2mm

1%

54.9

MF

1/20W

201

PLACE_NEAR=U7400.18:2mm

NO STUFF

SIGNAL_MODEL=EMPTY

16V

X7R-CERM

0201

1000PF

10%

SIGNAL_MODEL=EMPTY

NO STUFF

16V

X7R-CERM

0201

1000PF

10%

66

NO STUFF

NP0-CERM

0201

25V

100PF

5%

NO STUFF

NP0-CERM

0201

25V

100PF

5%

97 66 46

1/20W

MF

1%

16.2K

201

1/20W

1%

10

MF

201

SIGNAL_MODEL=EMPTY

16V

X7R-CERM

0201

1000PF

10%

89 13

MF

10

1%

1/20W

201

SIGNAL_MODEL=EMPTY

16V

X7R-CERM

0201

1000PF

10%

1/20W

MF

1%

12.1K

201

1000PF

SIGNAL_MODEL=EMPTY

16V

X7R-CERM

0201

10%

SIGNAL_MODEL=EMPTY

16V

X7R-CERM

0201

1000PF

10%

89 13

1%

10

MF

1/20W

201

1%

10

MF

1/20W

201

NO STUFF

NP0-CERM

0201

25V

100PF

5%

66

NO STUFF

NP0-CERM

0201

25V

100PF

5%

NO STUFF

NP0-CERM

0201

25V

100PF

5%

1%

137K

MF

1/20W

201

1/20W

137K

1%

MF

201

301K

1/20W

MF

1%

201

301K

1/20W

MF

1%

201

20%

2.2UF

0402

X6S-CERM

10V

PLACE_NEAR=U7400.15:2mm

1%

5.76K

1/20W

MF

201

1%

5.76K

1/20W

MF

201

1/20W

MF

182K

1%

201

SM

66

89 42 41 11

70

88

70

SIGNAL_MODEL=EMPTY

1%

40.2K

NO STUFF

MF

1/20W

201

0201

X7R-CERM

150PF

SIGNAL_MODEL=EMPTY

25V

10%

1

MF

1/20W

5%

201

SIGNAL_MODEL=EMPTY

1/20W

MF

1%

300

201

NP0-CERM

0201

25V

100PF

5%

NO STUFF

89 13

20%

2.2UF

0402

X6S-CERM

10V

PLACE_NEAR=U7400.24:2mm

20%

2.2UF

0402

X6S-CERM

10V

402

1/16W

MF-LF

10

5%

R7401

1 2

C7401

1

2

C7402

1

2

C7414

1

2

R7406

1 2

R7410

1 2

C7408

1 2

R7409

1 2

XW7400

12

R7402

1 2

R7468

1

2

R7466

1

2

C7403

1

2

R7462

1

2

R7460

1

2

R7463

1

2

R7461

1

2

C7415

1

2

C7416

1

2

C7417

1

2

R7440

1 2

R7441

1 2

C7440

1

2

C7441

1

2

R7412

1 2

C7412

1

2

R7413

1 2

C7422

1

2

R7423

1 2

R7422

1 2

C7419

1

2

C7418

1

2

C7442

1

2

C7443

1

2

R7479

1

2

R7480

1

2

R7407

1 2

R7408

1 2

R7469

1

2

R7467

1

2

R7464

1

2

R7465

1

2

U7400

5

20

22

25

34

14

23

43

10

42

44

45

41

9

11

8

27

32

16

28

31

18

37

13

47

3

6

2

7

35

36

26

33

15

30

17

24

12

38

39

40

49

48

1

46

29

19

21

4

R7403

1 2

C7410

1

2

C7473

1 2

C7409

1 2

051-9589

4.18.0

74 OF 132

65 OF 99

65

66 65

66

8

66

8

65

66

8

IN

SKIP*

PWN

THRM

DL

LX

VDD

BST

DH

PAD

GND

SKIP*

PWN

THRM

DL

LX

VDD

BST

DH

PAD

GND

IN

S

D

G

D

S

GD

S

G

D

S

G

D

S

G

D

S

G

S

D

G

S

D

G

S

D

G

S

G

D

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

152S1538

PHASE 3

376S1011

AXG PHASE 2

376S1011

THESE TWO CAPS ARE FOR EMC

PHASE 2

376S1010

(D SIZE)

152S1538

376S1014

AXG PHASE 1

376S1010

152S1538

THESE TWO CAPS ARE FOR EMC

(B SIZE)

THESE TWO CAPS ARE FOR EMC

152S1538

PHASE 1

376S1011

THESE TWO CAPS ARE FOR EMC

376S1010

376S1011

376S1010

THESE TWO CAPS ARE FOR EMC

Additonal Input Bulk Caps

OMIT_TABLEOMIT_TABLE

CPUIMVP_ISUM2P

68UF

POLY-TANT

OMIT_TABLE

0.36UH-20%-36A-0.00108OHM

MIN_NECK_WIDTH=0.25 MM

PIMS103T-SM

OMIT_TABLE

OMIT_TABLEOMIT_TABLE

OMIT_TABLEOMIT_TABLEOMIT_TABLE

OMIT_TABLEOMIT_TABLE

OMIT_TABLE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_LGATE2G

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

CPUIMVP_BOOT2G_RC

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_AXG1_L

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1G

SWITCH_NODE=TRUE

DIDT=TRUE

CPUIMVP_PHASE3_L

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU_PH3

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE2

CPUIMVP_PH2_SNUB

DIDT=TRUE

CPUIMVP_PH3_SNUB

DIDT=TRUE

CPUIMVP_AXG1_SNUB

DIDT=TRUE

PPVCORE_S0_AXG2_L

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU_PH2

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.25 MM

CPUIMVP_BOOT2_RC

DIDT=TRUE

CPUIMVP_AXG2_SNUB

CPUIMVP_BOOT1

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT2G

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_UGATE1

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1G

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_UGATE1G

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1G_R

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PH1_SNUB

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_LGATE1

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_BOOT2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT3

DIDT=TRUE

CPUIMVP_PHASE3

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_ISUMG1P

=PPVCORE_S0_CPU_REG

CPUIMVP_ISUM1P

CPUIMVP_ISUMN

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU_REG

CPUIMVP_ISUMN

CPUIMVP_ISUMG2P

CPUIMVP_ISUMGN

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS2G_N

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS2_P CPUIMVP_ISNS2_N

CPUIMVP_ISUMG_AVEP

CPUIMVP_ISUMG_AVE_RP

CPUIMVP_ISUMGN

CPUIMVP_ISNS1G_NCPUIMVP_ISNS1G_P

CPUIMVP_ISNS1_N

CPUIMVP_ISNS1_P

CPUIMVP_PWM3

CPUIMVP_SKIP

CPUIMVP_AXG_PWM2

CPUIMVP_SKIP

CPUIMVP_ISNS3_P

CPUIMVP_ISUMN

CPUIMVP_ISNS3_N

CPUIMVP_ISUM3P

=PP5V_S0_CPUIMVP

CPUIMVP_ISUMGN

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS1G_P

=PP5V_S0_CPUIMVP

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_LGATE1G

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE2G

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_BOOT3_RC

CPUIMVP_UGATE3

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

CPUIMVP_LGATE2

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2G

=PPVIN_S0_CPUAXG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_LGATE3

GATE_NODE=TRUE

DIDT=TRUE

=PPVIN_S0_CPUIMVP

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU_PH1

VOLTAGE=1.25V

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

CPU IMVP7 & AXG VCore Output

NOSTUFF

MF-LF

603

5%

1/10W

2.2

402

3.3

MF-LF

1/16W

5%

20%

16V

POLY-TANT

CASE-D2E-SM

CRITICAL

1/20W

46.4

1%

MF

201

0.36UH-20%-36A-0.00108OHM

PIMS103T-SM

CRITICAL

PIMS103T-SM

CRITICAL

0.36UH-20%-36A-0.00108OHM

CRITICAL

PIMS103T-SM

0.36UH-20%-36A-0.00108OHM

CRITICALCRITICAL

20%

16V

TANT

SM

15UF

CRITICAL

20%

16V

TANT

SM

15UF

CRITICAL

10%

NOSTUFF

X7R-CERM

0402

50V

0.001UF

NOSTUFF

MF-LF

603

1/10W

5%

2.2

10%

16V

NOSTUFF

X7R-CERM

0201

330PF

20%

16V

15UF

CRITICAL

SM

TANT

20%

16V

CRITICAL

15UF

SM

TANT

CRITICAL

649136PBF

S1

CRITICAL

DIRECTFET-SA

IRF6802SDTRPBF

CRITICAL

IRF6802SDTRPBF

DIRECTFET-SA

IRF6802SDTRPBF

CRITICAL

DIRECTFET-SA

CRITICAL

DIRECTFET_S3C

649135PBF

CRITICAL

DIRECTFET_S3C

649135PBF

CRITICAL

649135PBF

DIRECTFET_S3C

CRITICAL

649135PBF

DIRECTFET_S3C

649135PBF

CRITICAL

IRF6802SDTRPBF

DIRECTFET-SA

CRITICAL

10%

16V

X7R-CERM

0201

1000PF

0

MF

1/20W

5%

201

MF

1/20W

1%

200

201

NOSTUFF

MF

0

5%

1/20W

201

1%

200

MF

1/20W

201

10%

16V

X7R-CERM

0201

330PF

1%

MF

1/20W

46.4

201

10

1/20W

1%

MF

201

65

402

1/16W

MF-LF

5%

10K

TQFN

CRITICAL

MAX17491

10%

1UF

0402

X6S-CERM

16V

10%

402

16V

CERM

0.22UF

20%

16V

68UF

CASE-D2E-SM

CRITICAL

20%

16V

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20%

10UF

0603

X6S-CERM

16V

CRITICAL

NOSTUFF

CRITICAL

1%

0.00075

1W

MF

0612

20%

10UF

0603

X6S-CERM

16V

CRITICAL

NOSTUFF

10%

1UF

0402

X6S-CERM

16V 10%

50V

0402

X7R-CERM

0.001UF

10%

50V

X7R-CERM

0.001UF

0402

402

0

5%

MF-LF

1/16W

1/20W

10

1%

MF

201

1/20W

MF

1%

10

201

10

1/20W

MF

1%

201

46.4

MF

1%

1/20W

201

46.4

MF

1%

1/20W

201

MF

1%

46.4

1/20W

201

CRITICAL

TQFN

MAX17491

10%

16V

X7R-CERM

0201

330PF

10%

16V

X7R-CERM

0201

330PF

10%

16V

X7R-CERM

0201

330PF

10%

16V

X7R-CERM

0201

330PF

20%

10UF

0603

X6S-CERM

16V

CRITICAL

NOSTUFF

CRITICAL

0612

1%

MF

1W

0.00075

1%

1W

MF

0612

CRITICAL

1/20W

1%

MF

10

201

46.4

MF

1%

201

1/20W

20%

16V

CASE-D2E-SM

68UF

CRITICAL

POLY-TANT

20%

16V

POLY-TANT

68UF

CASE-D2E-SM

CRITICAL

20%

16V

POLY-TANT

CASE-D2E-SM

68UF

CRITICAL

65

10%

402

16V

CERM

0.22UF

10%

X7R-CERM

0402

50V

0.001UF

NOSTUFF

MF-LF

1/10W

5%

2.2

NOSTUFF

603

20%

16V

CRITICAL

68UF

POLY-TANT

CASE-D2E-SM

20%

10UF

0603

X6S-CERM

16V

CRITICAL

10%

1UF

0402

X6S-CERM

16V 10%

50V

0402

0.001UF

X7R-CERM

10%

50V

0402

0.001UF

X7R-CERM

402

1/16W

MF-LF

5%

10K

10%

402

16V

CERM

0.22UF

402

5%

1/16W

MF-LF

0

402

0

5%

MF-LF

1/16W

10%

402

16V

CERM

0.22UF

65

10%

1UF

0402

X6S-CERM

16V

402

3.3

MF-LF

5%

1/16W

10%

402

16V

CERM

0.22UF

10%

NOSTUFF

X7R-CERM

0402

50V

0.001UF

1/10W

2.2

5%

603

MF-LF

NOSTUFF

20%

16V

68UF

POLY-TANT

CASE-D2E-SM

CRITICAL

MF

1W

1%

0612

0.00075

CRITICAL

20%

16V

CASE-D2E-SM

68UF

POLY-TANT

CRITICAL

20%

10UF

0603

X6S-CERM

16V

CRITICAL

20%

10UF

0603

X6S-CERM

16V

CRITICAL

10%

1UF

0402

X6S-CERM

16V 10%

50V

0402

X7R-CERM

0.001UF

10%

50V

X7R-CERM

0402

0.001UF

10%

50V

X7R-CERM

0402

0.001UF

10%

50V

X7R-CERM

0402

0.001UF

10%

1UF

0402

X6S-CERM

16V

MF

1%

CRITICAL

1W

0612

0.00075

20%

10UF

0603

X6S-CERM

16V

CRITICAL

20%

10UF

0603

X6S-CERM

16V

CRITICAL

NOSTUFF

20%

16V

CRITICAL

POLY-TANT

CASE-D2E-SM

68UF

CASE-D2E-SM

20%

POLY-TANT

16V

68UF

CRITICAL

NOSTUFF

2.2

5%

MF-LF

603

1/10W

10%

50V

0.001UF

0402

X7R-CERM

NOSTUFF

65

20%

16V

CRITICAL

68UF

POLY-TANT

CASE-D2E-SM

65

10%

0.001UF

50V

X7R-CERM

0402

10%

X7R-CERM

50V

0402

0.001UF

10%

1UF

0402

X6S-CERM

16V

20%

10UF

0603

X6S-CERM

16V

NOSTUFF

CRITICAL

20%

16V

CRITICAL

20%

10UF

0603

X6S-CERM

16V

NOSTUFF

10%

NOSTUFF

X7R-CERM

0402

50V

0.001UF

R7512

1

2

C7512

1

2

C7515

1

2

C7513

1

2

C7516

1

2

C7517

1

2

C7518

1

2

C7519

1

2

C7514

1

2

C7522

1

2

R7522

1

2

C7523

1

2

C7524

1

2

C7525

1

2

C7526

1

2

R7520

1 2

3 4

C7527

1

2

C7528

1

2

C7529

1

2

C7539

1

2

C7538

1

2

C7537

1

2

C7536

1

2

C7535

1

2

C7534

1

2

R7530

1 2

3 4

C7533

1

2

R7532

1

2

C7532

1

2

C7531

1

2

R7531

1

2

C7541

1

2

C7521

1

2

R7521

1

2

R7511

1

2

C7511

1

2

R7547

1

2

C7559

1

2

C7558

1

2

C7557

1

2

C7556

1

2

C7554

1

2

R7552

1

2

C7552

1

2

C7551

1

2

C7572

1

2

C7571

1

2

C7570

1

2

R7513

1

2

R7514

1

2

R7510

1 2

3 4

R7550

2 1

4 3

C7555

1

2

C7581

1

2

C7582

1

2

C7583

1

2

C7584

1

2

U7541

1

8

4

3

7

2

6

9

5

R7523

1

2

R7533

1

2

R7553

1

2

R7524

1

2

R7534

1

2

R7554

1

2

R7556

1 2

C7566

1

2

C7565

1

2

C7564

1

2

C7563

1

2

R7560

1 2

3 4

C7562

1

2

C7561

1

2

C7560

1

2

C7530

1

2

C7540

1

2

U7542

1

8

4

3

7

2

6

9

5

R7540

1

2

R7562

1

2

R7561

1

2

C7567

1

2

R7563

1

2

R7565

1

2

R7564

1

2

R7566

1

2

C7568

1

2

Q7510

7

8

2

3

Q7551

1

2

8

7

4

3

5

6

Q7561

1

2

8

7

4

3

5

6

Q7525

1

2

8

7

4

3

5

6

Q7515

1

2

8

7

4

3

5

6

Q7535

1

2

8

7

4

3

5

6

Q7510

5

6

1

4

Q7550

7

8

2

3

Q7550

5

6

1

4

Q7530

1

2

5

64

3

C7573

1

2

C7576

1

2

C7569

1

2

R7587

1

2

C7587

1

2

C7574

1

2

C7578

1

2

L7510

1 2

L7520

1 2

L7530

1 2

L7550

1 2

L7560

1 2

R7582

1

2

C7575

1

2

R7535

1

2

051-9589

4.18.0

75 OF 132

66 OF 99

65

66

8

65

66 65

66 45

8

66

8

66 65

65

66 65

66 45

8

97 46

66

8

97 65 46

97 46

65

66 65

96 46 96 66 46

97 46

97 65 46

66

97 65 46

66 65

97 46

65

66 65

8

66 65

97 46

96 66 46

66 65

8

65

8

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

152S1238

CPU VCCIO (1V0R1V05 S0) REGULATOR

Vout = 0.5V * (1 + Ra / Rb)

(CPUVCCIOS0_OCSET)

OCP = R7641 x 8.5uA / R7640

376S0959

(CPUVCCIOS0_VO)

f = 300 kHz

OCP = 10.3A

9A MAX OUTPUT

VOUT = 1.05V

402

3.01K

1%

1/16W

MF-LF

70

10%

16V

2.2UF

X5R

603

5%

402

MF-LF

1/16W

0

PLACE_NEAR=U7600.1:1mm

SM

CRITICAL

UTQFN

ISL95870

5%

402

1/16W

MF-LF

2.2

10UF

603

X5R

10V

20%

402

10%

16V

1UF

X5R

5%

402

1000PF

25V

NP0-C0G

5%

402

25V

PLACE_NEAR=L7630.2:1.5mm

1000PF

NP0-C0G

16V

CRITICAL

CASE-D2E-SM

68UF

20%

POLY-TANT

16V

CRITICAL

68UF

20%

POLY-TANT

CASE-D2E-SM

5%

402

NP0-C0G

1000PF

25V

PLACE_NEAR=Q7630.1:1.5mm

CASE-B4-SM

TANT

CRITICAL

270UF

20%

2V

CRITICAL

MF-1

1%

0.001

1W

0612

2V

TANT

20%

CASE-B4-SM

270UF

CRITICAL

5%

MF-LF

0

1/10W

603

5%

10PF

0402

C0G-CERM

50V

CRITICAL

0.82UH-20%-13A-0.0067OHM

IHLP2525CZ-SM

CRITICAL

POWERPAK-6X3.7

SIZ710DT

402

10%

25V

X5R

1UF

5%

10PF

0402

C0G-CERM

50V

402

1.87K

1%

1/16W

MF-LF

402

MF-LF

1/16W

1%

1.87K

10%

0.047UF

0402

X7R-CERM

16V

402

OMIT_TABLE

1%

MF-LF

1/16W

2.74K

402

MF-LF

1%

1/16W

2.74K

OMIT_TABLE

402

MF-LF

1/16W

1%

3.01K

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

PPCPUVCCIO:IVB

RES,MTL FILM,1/16W,3.01K,1,0402,SMD,LF

R7605,R7645

2

114S0264

PPCPUVCCIO:SNB

RES,MTL FILM,1/16W,2.74K,1,0402,SMD,LF

2

R7605,R7645

114S0260

=PP5V_S0_CPUVCCIOS0

CPU_VCCIOSENSE_N

CPUVCCIOS0_PGOOD

CPUVCCIOS0_FSEL

CPU_VCCIOSENSE_P

CPUVCCIOS0_RTN

=PPCPUVCCIO_S0_REG

=PPVIN_S0_CPUVCCIOS0

CPUVCCIOS0_FB

CPUVCCIOS0_SREF

=CPUVCCIOS0_EN

CPUVCCIOS0_VO

CPUVCCIOS0_CS_N

CPUVCCIOS0_OCSET

CPUVCCIOS0_CS_P

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

CPUVCCIOS0_LL

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0_CPUVCCIOS0_VCC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_AGND

MIN_LINE_WIDTH=0.3 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_DRVL

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPCPUVCCIO_S0_REG_R

CPUVCCIOS0_VBST

CPUVCCIOS0_BOOT_RC

OMIT_TABLE OMIT_TABLE

C7604

1

2

C7605

1

2

C7603

1

2

R7645

1

2

R7605

1

2

R7604

1

2

R7644

1

2

C7602

1

2

R7603

1

2

XW7600

1 2

U7600

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

R7601

1

2

C7601

1

2

C7630

1

2

C7640

12

C7623

1

2

C7620

1

2

C7621

1

2

C7622

1

2

C7648

1

2

R7640

1 2

3 4

C7649

1

2

R7630

1

2

L7630

1 2

Q7630

1

6

4 5

237

8

C7625

1

2

R7642

1

2

R7641

1

2

051-9589

4.18.0

76 OF 132

67 OF 99

8

13 89

8

45 96

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

OUT

IN

NC

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

OUT

SS

IN0

IN1

THRML_PAD

EN FB

BIAS

OUT0

OUT1

GND

PG

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Panther Point-M requires JTAG pull-ups to be powered at 1.05V in Sus.

Freq = 1 MHz

1.8V S0 Regulator

Vout = 0.8V * (1 + Ra / Rb)

Over 1.5V to compensate for flex loss

Vout = 1.563V

Vout = 0.8V * (1 + Ra / Rb)

1.5V S0 LDO (RIO)

Max Current = 0.5A

<Rb>

<Ra>

1.5V S0 Regulator

Max Current = 1.5A

152S0691

152S1302

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.

1.05V SUS LDO

353S2535

<Ra>

Vout = 1.05V

Max Current = 0.35A

Max Current = 4A

Vout = 1.794V

<Rb>

Freq = 1.6MHZ

Vout = 1.508V

<Ra>

70mA is required to support pull-ups. Alternative is strong voltage

Vout = 0.8V * (1 + Ra / Rb)

CRITICAL

PIMB053T-SM

1.0UH-7A

10%

X5R

2.2UF

6.3V

XDP_PCH

402

TPS720105

XDP_PCH

CRITICAL

SON

10%

XDP_PCH

6.3V

CERM

402

1UF

90.9K

402

1%

1/16W

MF-LF

70

MF-LF

113K

1%

1/16W

402

47PF

402

50V

CERM

5%

25V

402

5%

1000PF

NP0-C0G

QFN

CRITICAL

OMIT_TABLE

ISL8014A

70

ISL8009B

DFN

CRITICAL

6.3V

805

22UF

20%

CERM

CRITICAL

2.2UH-3A

PCMB042T-IHLP1616BZ

MF-LF

1%

1/16W

402

113K

5%

50V

47PF

402

CERM

1/16W

402

1%

MF-LF

100K

6.3V

20%

22UF

CRITICAL

CERM

805

70

402

5%

MF-LF

1/16W

0

P1V5S0:LDO

SON

TPS74701

P1V5S0:LDO

CRITICAL

MF-LF

1/16W

5%

0

P1V5S0:LDO

402

5%

MF-LF

1/16W

0

P1V5S0:REG

X5R

P1V5S0:LDO

1.0UF

20%

6.3V

0201-MUR

X5R

20%

P1V5S0:LDO

1.0UF

6.3V

0201-MUR

10%

2.2NF

0201

X5R-CERM

10V

P1V5S0:LDO

201

MF

1/20W

5%

100

P1V5S0:LDO

201

P1V5S0:LDO

MF

1/20W

1%

4.42K

201

P1V5S0:LDO

MF

1/20W

5%

100K

201

MF

1/20W

1%

4.22K

P1V5S0:LDO

X5R-1

4V

20%

4.7UF

402

P1V5S0:LDO

0805

CRITICAL

20%

6.3V

X6S-CERM

22UF

20%

6.3V

X6S-CERM

22UF

CRITICAL

0805

20%

6.3V

X6S-CERM

22UF

CRITICAL

0805

SYNC_MASTER=D2_KEPLER

Misc Power Supplies

SYNC_DATE=01/13/2012

U7720

IC,ISL8014A,SYNC BUCK REG,4A 1MHZ,QFN16

1

353S3739

=PP3V3_S5_P1V2P1V8

=PP1V8_S0_REG

P1V5S0_LDO_PGOOD

=PP1V5_S0_REG

P1V5S0_PGOOD

=P1V5S0_EN

P1V8S0_PGOOD

=PP1V05_SUS_LDO

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_S5_P1V5S0

P1V8S0_FB

1V5_S0_FB

=PP1V8_S0_P1V5_LDO

P1V5S0_LDO_SS

=PP1V5_S0_RIO_LDO

=PP5V_S0_P1V5_LDO

P1V5S0_LDO_FB

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_S0_P1V5_LDO

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

1V5_S0_SW

DIDT=TRUE

SWITCH_NODE=TRUE

P1V8S0_SW

MIN_NECK_WIDTH=0.15 mm

PP1V5_S0_LDO

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

PP5V_S0_P1V5_LDO_BIAS

VOLTAGE=5V

=P1V8S0_EN

L7720

1 2

C7741

1

2

U7740

4

3

5

61

7

C7740

1

2

R7721

1

2

R7720

1

2

C7723

1

2

C7724

1

2

U7720

5

14

15

6

16

13

7

11

12

9

10

4

17

3

8

1

2

U7710

2

7

8

3

54

9

6

1

C7750

1

2

L7770

1 2

R7781

1

2

C7776

1

2

R7780

1

2

C7771

1

2

R7730

1

2

U7730

4

5 8

6

1

2

9

10

37

11

R7734

1 2

R7735

1 2

C7731

1

2

C7730

1

2

C7733

1

2

R7733

1

2

R7737

1

2

R7738

1

2

R7736

1

2

C7732

1

2

C7720

1

2

C7721

1

2

C7722

1

2

051-9589

4.18.0

77 OF 132

68 OF 99

2

8

8 8

8

IN

D

SG

S

D

G

D

G S

D

S

G

D

S

G

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

D

SG

D

S

G

D

S

G

D

SG

IN

D

S

G

IN

D

G S

IN

D

SG

S

G

D

IN

D

G S

S

G

D

OUT

D

SG

D

S

G

IN

D

S

G

D

G S

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APN 376S0651

LOADING

3.3V S0 GPU MISC FET

0.5A (EDP)

3.3V S0 MISC GPU FET

RDS(ON)

CHANNEL

MOSFET

26 mOhm @1.8V

SiA427

P-TYPE 8V/5V

SiA427

0.11A (EDP)

26 mOhm @1.8V

3.3V S0 GPU FET

MOSFET

CHANNEL

RDS(ON)

LOADING

3.3V S0 GPU FET

5V S3 FET

26 mOhm @1.8V

3 A (EDP)

P-TYPE 8V/5V

SiA427

RDS(ON)

LOADING

CHANNEL

MOSFET

1.5V S3/S0 FET

3.3V S3 FET

SiA427

P-TYPE 8V/5V

MOSFET

CHANNEL

3 A (EDP)

26 mOhm @1.8V

LOADING

3.3V S3 FET

LOADING

RDS(ON)

MOSFET

N-TYPE

SI7108DN

1.5V S3/S0 FET

6 mOhm @4.5V

5 A (EDP)

3.3V S0 FET

P-TYPE 20V/12V

5.5 mOhm @4.5V

5.6 A (EDP)

SI7615DN

CHANNEL

RDS(ON)

LOADING

26 mOhm @1.8V

P-TYPE 8V/5V

100? mA (EDP)

RDS(ON)

LOADING

5.0V S0 FET

SiA427

CHANNEL

MOSFET

3.3V SUS FET

5.5 MOHM @4.5V

P-TYPE 20V/12V

SI7615DN

LOADING

RDS(ON)

CHANNEL

MOSFET

376S0945

0.7? A (EDP)

26 mOhm @1.8V

P-TYPE 8V/5V

SiA427

CHANNEL

LOADING

2 mA (EDP)

MOSFET

RDS(ON)

CHANNEL

5V SUS FET

SiA413

P-TYPE 12V

29 mOhm @4.5V

5 A (EDP)

3.3V SUS FET

5V SUS FET

3.3V S0 FET

5.0V S0 FET

3.3V S4 FET

5V_SUS FET INPUT FILTER

CHANNEL

MOSFET

RDS(ON)

10%

0.01UF

0402

X7R-CERM

16V

402

1K

MF-LF

5%

1/16W

402

5%

51K

MF-LF

1/16W

88

27

10%

0.01UF

0402

X7R-CERM

16V

10%

402

16V

0.033UF

X5R

402

MF-LF

1/16W

5%

47K

402

MF-LF

5%

1/16W

100K

70

SSM6N15FEAPE

SOT563

CRITICAL

SI7108DN

PWRPK-1212-8-HF

SSM3K15FV

SOD-VESM-HF

SIA427DJ

CRITICAL

SC70-6L

CRITICAL

SC70-6L

SIA427DJ

CRITICAL

TDFN

SLG5AP020

402

CERM

20%

10V

0.1UF

402

5%

0

1/16W

MF-LF

88

70

SOT563

SSM6N15FEAPE

402

220K

5%

1/16W

MF-LF

402

47K

1/16W

5%

MF-LF

10%

402

16V

X5R

0.033UF

SIA427DJ

SC70-6L

CRITICAL

10%

0.01UF

0402

X7R-CERM

16V

10%

402

16V

0.033UF

X5R

CRITICAL

SC70-6L

SIA427DJ

10%

0.01UF

0402

X7R-CERM

16V

402

100K

1/16W

5%

MF-LF

SOT563

SSM6N15FEAPE

402

12K

5%

MF-LF

1/16W

70

10%

402

16V

0.033UF

X5R

SIA413DJ

SC70-6L

CRITICAL

10%

0.01UF

0402

X7R-CERM

16V

402

220K

5%

MF-LF

1/16W

402

5%

MF-LF

1/16W

3.3K

70

SSM3K15FV

SOD-VESM-HF

39 70

SSM6N15FEAPE

SOT563

402

MF-LF

1/16W

5%

47K

402

MF-LF

1/16W

5%

33K

10%

402

16V

X5R

0.033UF

10%

0.01UF

0402

X7R-CERM

16V

PWRPK-1212-8

SI7615DN

CRITICAL

70

SOD-VESM-HF

SSM3K15FV

402

220K

5%

1/16W

MF-LF

402

10K

5%

1/16W

MF-LF

10%

402

16V

0.033UF

X5R

10%

0.01UF

0402

X7R-CERM

16V

CRITICAL

PWRPK-1212-8

SI7615DN

10%

402

NO STUFF

10V

1UF

X5R

402

20%

2.2UF

X5R-CERM

10V

NO STUFF

402

0

MF-LF

1/16W

5%

PLACE_NEAR=Q7840.4:5mm

402

NOSTUFF

5%

1/16W

MF-LF

0

7

98

7

98

SOT563

SSM6N15FEAPE

CRITICAL

SC70-6L

SIA427DJ

10%

402

16V

X5R

0.033UF

402

47K

1/16W

MF-LF

5%

402

1/16W

5%

MF-LF

100K

10%

0.01UF

0402

X7R-CERM

16V

70

SC70-6L

SIA427DJ

CRITICAL

10%

0.01UF

0402

X7R-CERM

16V

402

1/16W

5%

MF-LF

1K

402

1/16W

MF-LF

51K

5%

SOD-VESM-HF

SSM3K15FV

88

0402

0.47UF

10%

6.3V

X6S-CERM

0402

0.33UF

10%

6.3V

X6S-CERM

SM

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

Power FETs

P3V3GPU_SS

=PP3V3_GPU_P3V3GPUFET

P3V3S0_EN_L

P3V3GPU_EN_L

P3V3GPU_MISC_SS

=PP3V3_GPU_MISC_P3V3GPUMISCFET

P1V5S3RS0_RAMP_DONE

P3V3S3_EN_L

=PP3V3_S3_P3V3S3FET

=PP3V3_S0GPU_FET

=P3V3S0_EN

=P3V3S4_EN

=P3V3S3_EN

=PP5V_S5_P5VSUSFET

=PP3V3_S4_FET

P5VSUS_SS

P5VSUS_EN_L

=P5VSUS_EN

=P3V3SUS_EN

P3V3SUS_EN_L

=PP3V3_S5_P3V3SUSFET

P3V3S4_EN_L

P3V3S3_S4

P5V0S0_EN_L

=PP5V_S0_FET

P5V0S0_SS

=P5VS0_EN

P3V3SUS_SS

P3V3S0_SS

=PP3V3_SUS_FET

=PP3V3_S0_P3V3S0FET

=PP3V3_S0_FET

=PP5V_SUS_FET

P1V5CPU_EN

P1V5S3RS0FET_GATE

P1V5S3RS0FET_GATE_R

=PP3V3_S3_FET

=PP3V3_S4_P3V3S4FET

=PP5V_S5_P1V5S3RS0FET

P3V3S3_SS

=P5VS3_EN

P5VS3_SS

P5VS3_EN_L

=PP5V_S4_P5VS3FET

=PP5V_S4_P5VS0FET

=PPVIN_S3_P1V5S3RS0_FET

=PP5V_S3_FET

=P3V3GPU_EN

=P3V3GPU_MISC_EN

P3V3GPU_MISC_EN_L

=PP3V3_S0GPU_MISC_FET

PP5V_S5_P5VSUSFET_R

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.1 MM

=PP1V5_S3RS0_FET_ISNS

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0_FET

MIN_NECK_WIDTH=0.2 MM

NC_ISNS_P1V5R1V35_CPUDDRN

NC_ISNS_P1V5R1V35_CPUDDRP

C7870

1 2

R7870

1 2

R7872

1

2

C7810

1 2

C7811

1

2

R7810

1 2

R7812

1

2

Q7812

6

21

Q7801

5

4

1 2 3

Q7872

3

12

Q7810

1

3

4 7

Q7870

1

3

4 7

U7801

5

7

4

2

8

6

3

9

1

C7801

1

2

R7801

1 2

Q7802

6

21

R7802 1

2

R7800

1

2

C7809

1

2

Q7800

1

3

4 7

C7800

1 2

C7821

1

2

Q7820

1

3

4 7

C7820

1 2

R7822

1

2

Q7802

3

54

R7820

1 2

C7841

1

2

Q7840

1

3

4 7

C7840

1 2

R7842

1

2

R7840

1 2

Q7842

3

12

Q7812

3

54

R7832 1

2R7830

1 2

C7831 1

2

C7830

1 2

Q7830

5

4

123

Q7865

3

12

R7862

1

2

R7860

1 2

C7861

1

2

C7860

1

2

Q7860

5

4

1 2 3

C7802

1

2

C7843

1

2

R7843

1 2

R7803

1 2

Q7852

6

21

Q7850

1

3

4 7

C7851

1

2

R7850

1 2

R7852

1

2

C7850

1 2

Q7880

1

3

4 7

C7880

1 2

R7880

1 2

R7882

1

2

Q7882

3

12

C7881

1

2

C7871

1

2

XW7805

1 2

051-9589

4.18.0

78 OF 132

69 OF 99

8

88

8

OUT

IN

OUT

D

G S

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

OUT

IN

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

IN

OUT

NC

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

VCC

A

Y

GND

B

C

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

D

GS

IN

Y

A

B

08

Y

A

B

08

IN

OUT

D

SG

D

SG

OUT

IN

OUT

NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

0 0

0

PM_RSMRST_L goes to U1800.C21

CPUVCORE ENABLE

3.3V S4 ENABLE

PM_SLP_S5_L:100K pull down on PCH page

Mobile System Power State Table

SMC_PM_G2_ENABLE

1

Battery Off (G3Hot)

01

0

toggle 3Hz

Battery Off (G3HotAC)

Sleep (S3)

Sleep (S3AC)

SMC_ADAPTER_EN

X

1

0

1

00

0

1

PM_SUS_EN

0

1

0

PM_SLP_S5_L

0

1

0

1

0

PM_SLP_S4_L

1

PM_SLP_S3_L

3.3V/5.0V Sus ENABLE

PM_SLP_SUS_L:100K pull down on PCH page

SMC_BATLOW_L:100K pull up on SMC page

CHGR VFRQ Generation

S0 Rail PGOOD (BJT Version)

S5 Rail Enables & PGOOD

3.3V SUS Detect

U7930 Sense input

5V, 3.3V, DDR S3 ENABLE

3.3V w/Divider: 2.345V

(ISL Version in development)

V2MON: 2.815V-3.099V

VDD: 2.734V-3.010V

V3MON: 0.572V-0.630V

V4MON: 0.572V-0.630V

SMC-->PM_DSW_PWRGD

Worst-Case Thresholds:

Min delay time

Q4: 0.660V

PP1V5_S3RS0

353S2809

Thresholds:

(IPU)

353S2310

Q3: 0.640V

Q2: 0.XXXV

PCH S0 PWRGD

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

on open-drain AP_PWR_EN signal.

NOTE: S3 term is guaranteed by S3 pull-up

PM_SLP_S4_L:100K pull down in PCH page

S0 ENABLE

PM_SLP_S3_L:100K pull down in PCH page

threhold is 3.07V

S0 Rail PGOOD Circuitry

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

No stuff C7931, 12ms

Run (S0)

State

Deep Sleep (dS4AC)

Deep Sleep (dS4)

Deep Sleep (dS5AC)

Deep Sleep (dS5)

P1V5S0_PGOOD from U7710

0

(PM_SLP_S3_R_L)

SMC_S4_WAKESRC_EN

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

Could stuff to satisfy

PCH power down timing t235

64

69

1/16W

5%

MF-LF

0

PLACE_NEAR=Q7812.2:6mm

402

0.47UF

CERM-X5R

6.3V

NO STUFF

402

10%

65

PLACE_NEAR=U7400.7:5mm

0

5%

MF-LF

1/16W

402

69

39 69

45

67

87

68

62

5.1K

5%

1/16W

MF-LF

PLACE_NEAR=U7300.16:6mm

402

0.47UF

CERM-X5R

6.3V

402

10%

7

18 27 34 38 40 41

MF-LF

1/16W

5%

PLACE_NEAR=U7720.5:6mm

5.1K

402

PLACE_NEAR=U7760.4:6mm

MF-LF

1/16W

20K

5%

402

PLACE_NEAR=U7600.3:6mm

1/16W

5%

MF-LF

20K

402

PLACE_NEAR=U7760.4:6mm

1UF

CERM-X5R

6.3V

402

10%

CERM-X5R

0.47UF

6.3V

PLACE_NEAR=U7600.3:6mm

402

10%

PLACE_NEAR=U7100.15:6mm

6.3V

0.47UF

CERM-X5R

402

10%

402

PLACE_NEAR=U7100.15:6mm

1/16W

33K

5%

MF-LF

1/16W

100K

MF-LF

5%

402

61

SSM3K15FV

SOD-VESM-HF

7

18 27 38 41 70

84

5%

1/16W

MF-LF

10K

402

24 41 70

100

5%

MF-LF

1/16W

402

100

MF-LF

5%

1/16W

402

100

5%

1/16W

MF-LF

402

MF-LF

402

1/16W

5%

100

68

63

100

5%

1/16W

MF-LF

402

S0PGOOD_ISL

330

5%

1/16W

MF-LF

402

87

62

1%

1/16W

150K

MF-LF

402

1K

1/16W

5%

MF-LF

402

15.0K

MF-LF

1/16W

1%

402

7.15K

1%

MF-LF

1/16W

402

ASMCC0179

DFN2015H4-8

CRITICAL

1K

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

1K

402

69

18 41

CRITICAL

TPS3808G33DBVRG4

SOT23-6

NO STUFF

20%

CERM

50V

402

0.001UF

5%

MF-LF

1/16W

100K

402

20%

0.1uF

10V

PLACE_NEAR=U7930.6:2.3mm

CERM

402

5%

100

MF-LF

1/16W

402

68

5%

1/16W

MF-LF

100

402

10K

1/16W

5%

MF-LF

402

68

PLACE_NEAR=U7710.2:6mm

0.47UF

6.3V

CERM-X5R

402

10%

18

63

41 42

NO STUFF

X7R-CERM

0402

0.0033UF

50V

10%

1/16W

PLACE_NEAR=U7201.21:7mm

MF-LF

5%

100

402

63

41

100K

5%

MF-LF

1/16W

PLACE_NEAR=U7201.20:7mm

402

ISL88042IRTEZ

TDFN

CRITICAL

S0PGOOD_ISL

MF-LF

1%

1/16W

6.04K

402

15.0K

1/16W

MF-LF

S0PGOOD_ISL

1%

402

1%

1/16W

10K

S0PGOOD_ISL

MF-LF

402

OMIT_TABLE

10K

1%

1/16W

MF-LF

402

S0PGOOD_ISL

6.04K

1%

1/16W

MF-LF

402

1/16W

MF-LF

S0PGOOD_ISL

15.0K

1%

402

74AUP1G3208

SOT891

0.1uF

20%

10V

PLACE_NEAR=U7940.1:2.3mm

CERM

402

69

18

41 42

1/16W

MF-LF

0

5%

NO STUFF

402

85

5%

1/16W

MF-LF

100

402

67

18 41 42

7

18 27 38 41 70

0

1/16W

NO STUFF

5%

MF-LF

402

34

19 24 34

NO STUFF

6.3V

CERM-X5R

0.47UF

402

10%

PLACE_NEAR=Q7842.2:6MM

5%

0

MF-LF

1/16W

402

69

SOD-VESM-HF

SSM3K15FV

65

PLACE_NEAR=U1800.p12:7mm

74LVC2G08GT

SOT833

5%

1/16W

MF-LF

0

402

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT

SOT833

5%

MF-LF

1/16W

1K

402

24 41 70

1/16W

MF-LF

5%

1K

402

10V

20%

0.1UF

CERM

402

18 25

18 24 41

18

SSM6N15FEAPE

SOT563

SSM6N15FEAPE

SOT563

84 85

0

NOSTUFF

5%

1/16W

MF-LF

402

41 42

63

SOT891

74LVC1G32

PLACE_NEAR=U7940.1:2.3mm

20%

0.1uF

10V

CERM

402

10%

402

NO STUFF

6.3V

CERM-X5R

0.47UF

PLACE_NEAR=U5701.4:6MM

201

1/20W

MF

3.3K

5%

49

0

5%

1/20W

MF

201

NOSTUFF

PLACE_NEAR=U7720.5:6mm

0402

0.47UF

10%

6.3V

X6S-CERM

0402

S0PGOOD_ISL

0.1UF

20%

10V

X7R-CERM

402

0.47UF

CERM-X5R

6.3V

10%

NO STUFF

201

MF

5%

0

1/20W

49

R7971

RES,MTL FILM,1/16W,10K,1,0402,SMD,LF

114S0315

1

PPDDR:1V5

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

Power Control 1/ENABLE

RES,MTL FILM,1/16W,12.4K,1,0402,SMD,LF

114S0323

R7971

1

PPDDR:1V35

SMC_DELAYED_PWRGD

PM_PCH_PWROK

MAKE_BASE=TRUE

=PP3V3_S5_PCHPWRGD

=P5VS4_TPAD_EN

P5V3V3_S4_EN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

PM_SUS_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

PM_SLP_S4_L

PVCCSA_EN

MAKE_BASE=TRUE

=PP3V3_S0_VMON

PVCCSA_PGOOD

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

P1V5S0_EN

=PP1V05_S0_VMON

MAKE_BASE=TRUE

CPUVCCIOS0_EN

MAKE_BASE=TRUE

P5VS3_EN

DDRREG_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

MAKE_BASE=TRUE

S5_PWRGD

MAKE_BASE=TRUE

P3V3S5_EN

MAKE_BASE=TRUE

PCHVCCIOS0_EN

=DDRREG_EN

VMON_Q2_BASE

P1V05_VID_VMON

=TBT_S0_EN

P5VS4_PGOOD

CPUVCCIOS0_PGOOD

ALL_SYS_PWRGD

PM_SLP_S3_L

=PP3V3_S5_PWRCTL

PM_WLAN_EN_L

PM_PCH_APWROK

ALL_SYS_PWRGD

=PP3V3_S0_PWRCTL

S0PGD_C

=PBUSVSENS_EN

=P1V8S0_EN

PM_SLP_S3_L

AC_EN_L

SMC_ADAPTER_EN

PM_PCH_SYS_PWROK

PM_S0_PGOOD

SYS_PWROK_R

=PP3V3_S0_SB_PM

CHGR_VFRQ

P3V3S5_PGOOD

VMON_Q3_BASE

Sus_PGOOD_CT

=PCHVCCIOS0_EN

=P5VS0_EN

=P3V3S0_EN

=PP1V05_S0_VMON

=PP1V5_S3RS0_VMON

=PP3V3_S0_VMON

=PP3V42_G3H_CHGR

=PP5V_S0_VMON

=PP1V5_S3RS0_VMON

ALL_SYS_PWRGD_R

=PP3V3_S5_VMON

=PP3V3_SUS_CNTRL

=CPUVCCIOS0_EN

=P1V5S0_EN

=P5VS5_EN

=PVCCSA_EN

S0PGD_BJT_GND_R

P1V5S0_PGOOD

P1V8S0_PGOOD

AP_PWR_EN

=PP3V42_G3H_PWRCTL

ALL_SYS_PWRGD

PCHVCCIOS0_PGOOD

P1V5_DIV_VMON

P5V_DIV_VMON

VMON_3V3_DIV

=P3V3S3_EN

=P5VS3_EN

TPAD_VBUS_EN

=P3V3S5_EN

ALL_SYS_PWRGD

CPUIMVP_PGOOD

=PP3V3_SUS_CNTRL

SUS_PGOOD_MR_L

PM_SLP_SUS_L

=P3V3SUS_EN

=P5VSUS_EN

SMC_BATLOW_L

=PP3V3_S5_PWRCTL

PM_SLP_S5_L

CPUIMVP_VR_ON

VMON_Q4_BASE

PM_RSMRST_L

=TBTAPWRSW_EN

=P3V3S4_EN

=TBTBPWRSW_EN

P5VS4_EN

MAKE_BASE=TRUE

=P5VS4_EN

PM_SLP_S3_R_L

MAKE_BASE=TRUE

R7912

1

2

C7912

1

2

R7974

1 2

R7911

1

2

C7910

1

2

R7986

1

2

R7985

2

1

R7981

1

2

C7985

1

2

C7981

1

2

C7987

1

2

R7987

1

2

R7931

1 2

Q7931

3

12

R7967

1

2

R7957

1

2

R7966

1 2

R7969

1 2

R7965

1 2

R7963

1 2

R7962

1 2

R7956

1

2

R7953

1 2

R7951

1

2

R7952

1

2

Q7950

5

7

1

6

4

8

2

3

R7954

1 2

R7955

1 2

U7930

4

2

3

15

6

C7931

1

2

R7933

1

2

C7930

1

2

R7968

1 2

R7978

1 2

R7988

1 2

C7988

1

2

C7942

1

2

R7940

1 2

R7941

1

2

U7960

4

1

8

9

3

5

6

2

7

R7972

1

2

R7973

1

2

R7970

1

2

R7971

1

2

R7960

1

2

R7961

1

2

U7940

1

3

6

2

5

4

C7940

1

2

R7917

1 2

R7964

1 2

R7929

1

2

C7913

1

2

R7913

1

2

Q7925

3

1

2

U7950

1

2

4

8

7

R7948

1 2

U7950

5

6

4

8

3

R7949

1 2

R7950

1

2

C7950

1

2

Q7920

6

21

Q7920

3

54

R7915

1 2

U7970

2

1

3

6

4

C7970

1

2

C7914

1

2

R7914

1 2

R7930

1

2

C7986

1

2

C7960

1

2

C7975

1

2

R7975

1 2

051-9589

4.18.0

79 OF 132

70 OF 99

5

37 41 42

8

70

45

8

70

8

70

8

70

24 41 70

8

88

8

25

63

8

70

8

70

8

70

8

61

8

70

8

70

8

24 41 70

8

70

8

70

OUT

NC

IN

OUT

IN

NC

PEX_SVDD_3V3

PEX_TX0*

PEX_TX0PEX_RX0

PEX_RX1

PEX_RX6*

PEX_REFCLK*

PEX_WAKE*

PEX_CLKREQ*

PEX_RST*

PEX_REFCLK

PEX_RX15

PEX_RX15*

PEX_RX14*

PEX_RX14

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7

PEX_RX7*

PEX_RX6

PEX_RX5

PEX_RX5*

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2

PEX_RX2*

PEX_RX1*

PEX_TSTCLK_OUT*

PEX_TERMP

PEX_TX15

PEX_TX15*

PEX_TSTCLK_OUT

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX13

PEX_TX12

PEX_TX12*

PEX_TX11

PEX_TX11*

PEX_TX10

PEX_TX10*

PEX_TX9*

PEX_TX8*

PEX_TX9

PEX_TX8

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2

PEX_TX2*

PEX_TX1*

PEX_TX1

PEX_TX4*

PEX_RX0*

PEX_RX13*

PEX_RX13

PEX_TX7*

(1 OF 10)

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Power aliases required by this page:

BOM options provided by this page:

Page Notes

Signal aliases required by this page:

(NONE)

- =PP3V3_GPU_VDD33

9

88 89

9

88 89

9

89

9

89

9

89

9

89

9

88 89

9

88 89

9

89

9

89

9

89

9

89

9

89

9

89

GND_VOID=TRUE

6.3V

0.22UF

20%

X6S-CERM 0201

9

78

71 78

9

89

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

9

89

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

GND_VOID=TRUE

6.3V X6S-CERM

0.22UF

20%

0201

1/20W

MF

1%

NOSTUFF

200

201

MF

1/20W

2.49K

1%

201

10K

1%

1/20W

MF

201

0

1/20W

5%MF

201

NV-GK107

OMIT_TABLE

BGA

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

17 92

9

88 89

9

88 89

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

KEPLER PCI-E

PEG_R2D_P<2>

PEG_R2D_P<0>

PEG_R2D_C_P<3>

PEG_R2D_N<2>

PEG_R2D_N<3>

PEG_R2D_C_N<3>

PEG_R2D_N<6>

PEG_D2R_C_N<4>

PEG_R2D_P<7>

PEG_R2D_P<5>

PEG_R2D_P<2>

PEG_D2R_C_N<2>

PEG_R2D_C_P<4>

PEG_R2D_P<1>

PEG_R2D_N<1>

PEG_R2D_N<5>

PEG_D2R_N<0>

PEG_R2D_C_P<6>

PEG_D2R_C_P<1>

PEG_D2R_N<1>

PEG_D2R_C_N<4>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_N<5>

PEG_D2R_C_P<7>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_N<7>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_D2R_C_P<4>

PEG_D2R_C_N<3>

PEG_D2R_N<6>

PEG_D2R_N<7>

PEG_D2R_P<7>

PEG_D2R_C_N<1>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

PEG_D2R_P<1>

PEG_D2R_P<0>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<4>

PEG_D2R_N<5>

PEG_D2R_P<5>

PEG_D2R_N<4>

PEG_D2R_N<3>

PEG_R2D_N<4>

PEG_R2D_C_P<0>

PEG_R2D_C_N<7>

PEG_R2D_C_N<5>

PEG_R2D_P<6>

PEG_R2D_C_N<4>

PEG_R2D_C_N<0>

PEX_CLKREQ_L_R

PEG_D2R_P<3>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_P<6>

GPU_RESET_L

PEG_R2D_C_P<1>

PEG_R2D_N<0>

=PP3V3_GPU_VDD33

PEG_R2D_C_N<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_D2R_C_N<7>

PEG_R2D_N<0>

PEG_D2R_C_P<1>

PEG_D2R_C_N<1>

PEG_D2R_C_N<2>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_C_N<3>

PEG_D2R_C_P<4>

PEG_D2R_C_P<5>

PEG_D2R_C_N<5>

PEG_D2R_C_P<6>

PEG_D2R_C_N<6>

PEG_D2R_C_P<7>

PEX_TSTCLK_O_P

GPU_PEX_TERMP

PEX_TSTCLK_O_N

PEG_R2D_N<1>

PEG_R2D_N<2>

PEG_R2D_P<3>

PEG_R2D_N<3>

PEG_R2D_P<4>

PEG_R2D_N<4>

PEG_R2D_N<5>

PEG_R2D_P<5>

PEG_R2D_P<6>

PEG_R2D_N<7>

PEG_R2D_P<7>

PEG_CLK100M_P

GPU_RESET_R_L

PEX_CLKREQ_L_R

PEG_CLK100M_N

PEG_R2D_N<6>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_D2R_C_P<0>

PEG_D2R_C_N<0>

PP3V3_GPU_PEX_PLL_HVDD

C8020

1 2

C8021

1 2

C8022

1 2

C8023

1 2

C8024

1 2

C8025

1 2

C8026

1 2

C8027

1 2

C8028

1 2

C8029

1 2

C8030

1 2

C8031

1 2

C8032

1 2

C8033

1 2

C8034

1 2

C8035

1 2

C8056

1 2

C8057

1 2

C8058

1 2

C8059

1 2

C8060

1 2

C8061

1 2

C8063

1 2

C8064

1 2

C8065

1 2

C8066

1 2

C8068

1 2

C8069

1 2

C8070

1 2

C8062

1 2

C8067

1 2

C8055

1 2

R8002

1 2

R8005

1 2

R8001

1

2

R8000

1 2

U8000

AK12

AL13

AK13

AJ12

AN12

AM12

AN14

AM14

AN23

AM23

AP23

AP24

AN24

AM24

AN26

AM26

AP26

AP27

AN27

AM27

AP14

AP15

AN15

AM15

AN17

AM17

AP17

AP18

AN18

AM18

AN20

AM20

AP20

AP21

AN21

AM21

AG12

AP29

AJ26

AK26

AK14

AJ14

AH14

AG14

AK21

AJ21

AL22

AK22

AK23

AJ23

AH23

AG23

AK24

AJ24

AL25

AK25

AK15

AJ15

AL16

AK16

AK17

AJ17

AH17

AG17

AK18

AJ18

AL19

AK19

AK20

AJ20

AH20

AG20

AJ11

051-9589

4.18.0

80 OF 132

71 OF 99

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 78

71 89

71 88 89

8

77 78 79

71 89

71 88 89

71 89

92 95

92

95

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89

71 89

71 88 89 71 89

71 89

79

NC

XVDD

VDD

(10 OF 10)

FBVDDQFBVDDQ

(7 OF 10)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: ATLEAST 2 GND VIAS & 2 POWER VIAS PER CAP

GPU VCORE DE-COUPLING

GPU FB DE-COUPLING

Power aliases required by this page:

- =PPVCORE_GPU

- =PP1V35_GPU_FBVDDQ

Page Notes

(NONE)

Signal aliases required by this page:

BOM options provided by this page:

EDP = 6500 MA

EDP = 30 A

20%

4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

CRITICAL

4V

CERM-X6S

0201

1UF 20%

CRITICAL

4V

CERM-X6S

0201

1UF 20%

CRITICAL

4V

CERM-X6S

0201

1UF 20%

CRITICAL

4V

CERM-X6S

0201

1UF

20%

CRITICAL

4V

CERM-X6S

0201

1UF

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

1000PF

X7R-CERM

16V

10%

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X7R-CERM

1000PF

16V

10%

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

BGA

NV-GK107

OMIT_TABLE

BGA

NV-GK107

0805

X6S

4V

20%

47UF

NOSTUFF

20%

CRITICAL

NOSTUFF

X6S-CERM

0603

4V

22UF

20%

NOSTUFF

CRITICAL

X6S-CERM

0603

4V

22UF

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

10UF

0402-1

X6S-CERM

4V

20%

4V

CERM-X6S

0201

1UF

KEPLER CORE/FB POWER

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

=PPVCORE_GPU

=PP1V35_GPU_FBVDDQ

=PPVCORE_GPU =PPVCORE_GPU

=PP1V35_GPU_FBVDDQ=PP1V35_GPU_FBVDDQ

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

NOSTUFF

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

NOSTUFF

2V

X6T-CERM

0402

20UF

20%

CRITICAL

NOSTUFF

2V

0402

X6T-CERM

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

2V

X6T-CERM

0402

20UF

20%

CRITICAL

NOSTUFF

2V

X6T-CERM

0402

20UF

20%

CRITICAL

NOSTUFF

2V

X6T-CERM

0402

20UF

20%

2V

X6T-CERM

0402

20UF

20%

2V

X6T-CERM

0402

20UF

20%

2V

X6T-CERM

0402

20UF

20%

2V

X6T-CERM

0402

20UF

C8104

1

2

C8103

1

2

C8102

1

2

C8101

1

2

C8114

1

2

C8113

1

2

C8112

1

2

C8111

1

2

C8110

1

2

C8109

1

2

C8108

1

2

C8107

1

2

C8106

1

2

C8105

1

2

C8125

1

2

C8126

1

2

C8127

1

2

C8128

1

2

C8186

1

2

C8187

1

2

C8188

1

2

C8189

1

2

C8190

1

2

C8191

1

2

C8192

1

2

C8193

1

2

C8194

1

2

C8195

1

2

C8196

1

2

C8119

1

2

C8120

1

2

C8121

1

2

C8122

1

2

C8123

1

2

C8124

1

2

C8197

1

2

C8115

1

2

C8118

1

2

U8000

AA12

AB18

AB20

AB22

AC12

AC14

AC16

AC19

AC21

AC23

M12

AA14

M14

M16

M19

M21

M23

N13

N15

N17

N18

N20

AA16

N22

P12

P14

P16

P19

P21

P23

R13

R15

R17

AA19

R18

R20

R22

T12

T14

T16

T19

T21

T23

U13

AA21

U15

U17

U18

U20

U22

V13

V15

V17

V18

V20

AA23

V22

W12

W14

W16

W19

W21

W23

Y13

Y15

Y17

AB13

Y18

Y20

Y22

AB15

AB17

U1

V2

V3

V4

V5

V6

V7

V8

W2

W3

W4

U2

W5

W7

W8

Y1

Y2

Y3

Y4

Y5

Y6

Y7

U3

Y8

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

U4

U5

U6

U7

U8

V1

U8000

AA27

B13

B16

B19

E13

E16

E19

H10

H11

H12

H13

AA30

H14

H15

H16

H18

H19

H20

H21

H22

H23

H24

AB27

H8

H9

L27

M27

N27

P27

R27

T27

T30

T33

AB33

V27

W27

W30

W33

Y27

AC27

AD27

AE27

AF27

AG27

C8161

1

2

C8162

1

2

C8163

1

2

C8164

1

2

C8165

1

2

C8182

1

2

C8183

1

2

C8198

1

2

C8199

1

2

C8145

1

2

C8151

1

2

C8150

1

2

C8149

1

2

C8148

1

2

C8147

1

2

C8146

1

2

C8166

1

2

C8167

1

2

C8168

1

2

C8169

1

2

C8170

1

2

C8171

1

2

C8172

1

2

C8173

1

2

C8174

1

2

C8175

1

2

C8176

1

2

C8177

1

2

C8178

1

2

C8179

1

2

C8180

1

2

C8181

1

2

C8184

1

2

C8185

1

2

051-9589

4.18.0

81 OF 132

72 OF 99

8

72 79

8

72 75 76

8

72 79

8

72 79

8

72 75 76

8

72 75 76

OUT

BI

IN

BI

IN

NC

OUT

NC

BI

OUT

NC

OUT

NC

OUT

D

GS

IN

OUT

FBA_CMD5

FBA_CMD0

FBA_CLK1*

FBA_CLK1

FBA_CLK0*

FB_GND_SENSE

FBA_WCKB67

FBA_D0

FBA_WCKB67*

FBA_WCKB45*

FBA_WCKB23*

FBA_WCKB45

FBA_WCKB01*

FBA_WCKB23

FBA_WCK67*

FBA_WCKB01

FBA_WCK67

FBA_WCK45*

FBA_WCK23*

FBA_WCK45

FBA_WCK01*

FBA_WCK23

FBA_WCK01

FBA_D63

FBA_D62

FBA_D60

FBA_D61

FBA_D57

FBA_D58

FBA_D59

FBA_D56

FBA_D55

FBA_D54

FBA_D52

FBA_D53

FBA_D50

FBA_D51

FBA_D47

FBA_D49

FBA_D48

FBA_D45

FBA_D46

FBA_D42

FBA_D43

FBA_D44

FBA_D40

FBA_D41

FBA_D39

FBA_D37

FBA_D38

FBA_D34

FBA_D35

FBA_D36

FBA_D32

FBA_D33

FBA_D31

FBA_D30

FBA_D29

FBA_D27

FBA_D28

FBA_D24

FBA_D25

FBA_D26

FBA_D22

FBA_D19

FBA_D20

FBA_D16

FBA_D17

FBA_D18

FBA_D14

FBA_D15

FBA_D11

FBA_D12

FBA_D13

FBA_D9

FBA_D10

FBA_D8

FBA_D7

FBA_D6

FBA_D4

FBA_D5

FBA_D3

FBA_D2

FBA_D1

FB_VDDQ_SENSE

FBA_CMD_RFU

FB_CLAMP

FBA_CMD_RFU

FB_CAL_PU_GND

FB_CAL_TERM_GND

FBA_DEBUG

FB_CAL_PD_VDDQ

FBA_PLL_AVDD

FBA_DEBUG

FBA_DQS_WP7

FB_DLL_AVDD

FBA_DQS_WP4

FBA_DQS_WP5

FBA_DQS_WP6

FBA_DQS_WP3

FBA_DQS_WP2

FBA_DQS_WP1

FBA_DQS_WP0

FBA_DQS_RN7

FBA_DQS_RN6

FBA_DQS_RN5

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN1

FBA_DQS_RN2

FBA_DQS_RN0

FBA_DQM7

FBA_DQM5

FBA_DQM6

FBA_DQM4

FBA_DQM3

FBA_DQM2

FBA_DQM0

FBA_DQM1

FBA_CLK0

FBA_CMD31

FBA_CMD29

FBA_CMD30

FBA_CMD27

FBA_CMD28

FBA_CMD24

FBA_CMD25

FBA_CMD26

FBA_CMD22

FBA_CMD23

FBA_CMD21

FBA_CMD19

FBA_CMD20

FBA_CMD16

FBA_CMD17

FBA_CMD18

FBA_CMD14

FBA_CMD15

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD4

FBA_CMD1

FBA_CMD3

FBA_CMD2

FBA_D23

FBA_D21

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9

FBA_CMD10

(3 OF 10)

MEM INTERFACE A

FBB_CMD31

FBB_CMD10

FBB_CMD14

FBB_CMD24

FBB_CMD25

FBB_CMD_RFU1

FBB_CMD_RFU0

FBB_D12

FBB_D10

FBB_D7

FBB_D1

FBB_D2

FBB_D3

FBB_CMD16

FBB_DQS_RN4

FBB_DQM4

FBB_CLK1

FBB_CMD22

FBB_CLK0

FBB_CLK0*

FBB_CLK1*

FBB_CMD0

FBB_CMD1

FBB_CMD2

FBB_CMD3

FBB_CMD4

FBB_CMD5

FBB_CMD6

FBB_CMD7

FBB_CMD8

FBB_CMD9

FBB_CMD11

FBB_CMD12

FBB_CMD13

FBB_CMD15

FBB_CMD17

FBB_CMD18

FBB_CMD19

FBB_CMD20

FBB_CMD21

FBB_CMD23

FBB_CMD26

FBB_CMD27

FBB_CMD29

FBB_CMD30

FBB_D0

FBB_D4

FBB_D5

FBB_D6

FBB_D8

FBB_D9

FBB_D11

FBB_D13

FBB_D14

FBB_D15

FBB_D16

FBB_D17

FBB_D18

FBB_D19

FBB_D20

FBB_D21

FBB_D22

FBB_D23

FBB_D24

FBB_D25

FBB_D26

FBB_D27

FBB_D28

FBB_D29

FBB_D32

FBB_D33

FBB_D34

FBB_D35

FBB_D36

FBB_D37

FBB_D38

FBB_D39

FBB_D40

FBB_D41

FBB_D42

FBB_D43

FBB_D44

FBB_D45

FBB_D46

FBB_D47

FBB_D48

FBB_D49

FBB_D50

FBB_D51

FBB_D52

FBB_D53

FBB_D54

FBB_D55

FBB_D56

FBB_D57

FBB_D58

FBB_D59

FBB_D60

FBB_D61

FBB_D62

FBB_D63

FBB_DEBUG0

FBB_DEBUG1

FBB_DQM0

FBB_DQM1

FBB_DQM2

FBB_DQM3

FBB_DQM5

FBB_DQM6

FBB_DQM7

FBB_DQS_RN0

FBB_DQS_RN1

FBB_DQS_RN2

FBB_DQS_RN3

FBB_DQS_RN5

FBB_DQS_RN6

FBB_DQS_RN7

FBB_DQS_WP0

FBB_DQS_WP1

FBB_DQS_WP2

FBB_DQS_WP3

FBB_DQS_WP4

FBB_DQS_WP5

FBB_DQS_WP6

FBB_DQS_WP7

FBB_PLL_AVDD

FBB_WCK01

FBB_WCK01*

FBB_WCK23

FBB_WCK23*

FBB_WCK45

FBB_WCK45*

FBB_WCK67

FBB_WCK67*

FBB_WCKB01*

FBB_WCKB23

FBB_WCKB23*

FBB_WCKB45

FBB_WCKB45*

FBB_WCKB67

FBB_WCKB67*

FB_VREF

FBB_WCKB01

FBB_D31

FBB_D30

FBB_CMD28

(4 OF 10)

MEM INTRERFACE B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- =PP1V35_GPU_S0_FB

FB PLL & DLL VDD

(NONE)

BOM options provided by this page:

- =PP1V05_GPU_PEX_IOVDD

Power aliases required by this page:

Signal aliases required by this page:

PLACE CLOSE TO BGA

MEM VREFC & VREFD SWITCH

(NONE)

Page Notes

ESR = 0.05OHM

NOTE:GDDR5 MODE H MAPPING

FB VREF GEN (TEST ONLY)

20UF

2V

X6T-CERM

0402

20%

20UF

2V

X6T-CERM

0402

20%

PP1V05_GPU_FB_PLL_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

PP1V05_GPU_FB_DLL_AVDD

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_GPU_FB_PLL_AVDD

FB_B1_CAS_L

FB_B0_A<0>

FB_B0_CKE_L

FB_B1_ABI_L

FB_B1_A<8>

FB_B0_DQ<12>

FB_B0_DQ<10>

FB_B0_DQ<7>

FB_B0_DQ<1>

FB_B0_DQ<2>

FB_B0_DQ<3>

FB_B1_CS_L

FB_B1_DBI_L<0>

FB_B1_CLK_P

FB_B1_A<7>

FB_B0_CLK_P

FB_B1_CLK_N

FB_B0_CS_L

FB_B0_A<3>

FB_B0_A<2>

FB_B0_A<4>

FB_B0_A<5>

FB_B0_WE_L

FB_B0_A<7>

FB_B0_A<6>

FB_B0_ABI_L

FB_B0_A<8>

FB_B0_A<1>

FB_B0_RAS_L

FB_B0_RESET_L

FB_B0_CAS_L

FB_B1_A<3>

FB_B1_A<2>

FB_B1_A<4>

FB_B1_A<5>

FB_B1_WE_L

FB_B1_A<6>

FB_B1_RESET_L

FB_B1_CKE_L

FB_B0_DQ<0>

FB_B0_DQ<4>

FB_B0_DQ<5>

FB_B0_DQ<6>

FB_B0_DQ<8>

FB_B0_DQ<9>

FB_B0_DQ<11>

FB_B0_DQ<13>

FB_B0_DQ<14>

FB_B0_DQ<15>

FB_B0_DQ<16>

FB_B0_DQ<17>

FB_B0_DQ<18>

FB_B0_DQ<19>

FB_B0_DQ<20>

FB_B0_DQ<21>

FB_B0_DQ<22>

FB_B0_DQ<23>

FB_B0_DQ<24>

FB_B0_DQ<25>

FB_B0_DQ<26>

FB_B0_DQ<27>

FB_B0_DQ<28>

FB_B0_DQ<29>

FB_B1_DQ<0>

FB_B1_DQ<1>

FB_B1_DQ<2>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<8>

FB_B1_DQ<9>

FB_B1_DQ<10>

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_B1_DQ<15>

FB_B1_DQ<16>

FB_B1_DQ<17>

FB_B1_DQ<18>

FB_B1_DQ<19>

FB_B1_DQ<20>

FB_B1_DQ<21>

FB_B1_DQ<22>

FB_B1_DQ<23>

FB_B1_DQ<24>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<28>

FB_B1_DQ<29>

FB_B1_DQ<30>

FB_B1_DQ<31>

GPU_FBB_DEBUG0

GPU_FBB_DEBUG1

FB_B0_DBI_L<0>

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B1_DBI_L<1>

FB_B1_DBI_L<3>

FB_B0_EDC<0>

FB_B0_EDC<2>

FB_B1_EDC<0>

FB_B1_EDC<1>

FB_B1_EDC<2>

FB_B1_EDC<3>

FB_B0_WCLK_P<0>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1>

FB_B0_WCLK_N<1>

FB_B1_WCLK_P<0>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>

FB_B1_WCLK_N<1>

FB_VREF

FB_B0_DQ<31>

FB_B0_DQ<30>

FB_B1_RAS_L

FB_A0_A<4>

FB_A1_CLK_N

FB_A1_CLK_P

FB_A0_CLK_N

GPU_FBGND_SENSE

FB_A0_DQ<0>

FB_A1_WCLK_N<1>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<0>

FB_A0_WCLK_N<1>

FB_A1_WCLK_P<0>

FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1>

FB_A0_WCLK_P<0>

FB_A1_DQ<31>

FB_A1_DQ<30>

FB_A1_DQ<28>

FB_A1_DQ<29>

FB_A1_DQ<25>

FB_A1_DQ<26>

FB_A1_DQ<27>

FB_A1_DQ<24>

FB_A1_DQ<23>

FB_A1_DQ<22>

FB_A1_DQ<20>

FB_A1_DQ<21>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<15>

FB_A1_DQ<17>

FB_A1_DQ<16>

FB_A1_DQ<13>

FB_A1_DQ<14>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<12>

FB_A1_DQ<8>

FB_A1_DQ<9>

FB_A1_DQ<7>

FB_A1_DQ<5>

FB_A1_DQ<6>

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<0>

FB_A1_DQ<1>

FB_A0_DQ<31>

FB_A0_DQ<30>

FB_A0_DQ<29>

FB_A0_DQ<27>

FB_A0_DQ<24>

FB_A0_DQ<25>

FB_A0_DQ<26>

FB_A0_DQ<22>

FB_A0_DQ<19>

FB_A0_DQ<18>

FB_A0_DQ<14>

FB_A0_DQ<15>

FB_A0_DQ<12>

FB_A0_DQ<13>

FB_A0_DQ<8>

FB_A0_DQ<7>

FB_A0_DQ<6>

FB_A0_DQ<4>

FB_A0_DQ<5>

FB_A0_DQ<3>

FB_A0_DQ<2>

GPU_FBVDDQ_SENSE

FB_CLAMP

FB_CAL_PU_GND

FB_CAL_TERM_GND

GPU_FBA_DEBUG1

FB_CAL_PD_VDDQ

PP1V05_GPU_FB_PLL_AVDD

GPU_FBA_DEBUG0

FB_A1_EDC<3>

PP1V05_GPU_FB_DLL_AVDD

FB_A1_EDC<0>

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A0_EDC<3>

FB_A0_EDC<2>

FB_A0_EDC<1>

FB_A0_EDC<0>

FB_A1_DBI_L<3>

FB_A1_DBI_L<1>

FB_A1_DBI_L<2>

FB_A1_DBI_L<0>

FB_A0_DBI_L<3>

FB_A0_DBI_L<2>

FB_A0_DBI_L<0>

FB_A0_DBI_L<1>

FB_A0_CLK_P

FB_A1_CAS_L

FB_A1_RESET_L

FB_A1_CKE_L

FB_A1_RAS_L

FB_A1_A<8>

FB_A1_A<0>

FB_A1_A<6>

FB_A1_A<4>

FB_A1_A<5>

FB_A1_CS_L

FB_A1_A<3>

FB_A1_A<2>

FB_A0_CKE_L

FB_A0_CAS_L

FB_A0_RESET_L

FB_A0_RAS_L

FB_A0_A<1>

FB_A0_A<5>

FB_A0_A<3>

FB_A0_A<2>

FB_A0_DQ<21>

FB_A0_A<7>

FB_A0_A<6>

FB_A0_A<8>

FB_A0_A<0>

FB_A1_RESET_L

FB_A0_CKE_L

=PP1V35_GPU_S0_FB

FB_VREF

FB_CAL_PU_GND

FB_SW_LEG

GPU_ALT_VREF

GPU_FBB_DEBUG0

GPU_FBB_DEBUG1

FB_B1_CKE_L

FB_A0_RESET_L

FB_B1_RESET_L

FB_CAL_PD_VDDQ

FB_B0_RESET_L

FB_A1_CKE_L

FB_B0_CKE_L

=PP1V05_GPU_PEX_IOVDD

FB_A1_DQ<4>

FB_A0_DQ<28>

FB_A0_DQ<23>

FB_A0_DQ<20>

FB_A0_DQ<1>

FB_A0_DQ<11>

FB_A0_DQ<10>

FB_A0_DQ<9>

FB_A0_ABI_L

FB_A0_DQ<17>

FB_A0_DQ<16>

FB_A1_WE_L

FB_A1_A<7>

FB_B1_A<1>

FB_B1_A<0>

FB_A0_WE_L

FB_A0_CS_L

FB_B0_CLK_N

FB_B0_DBI_L<1>

FB_B1_DBI_L<2>

FB_B0_EDC<3>

FB_B0_EDC<1>

FB_B1_DQ<6>

FB_B1_DQ<7>

FB_B1_DQ<5>

FB_A1_A<1>

FB_A1_ABI_L

KEPLER FRAME BUFFER I/F

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

BGA

OMIT_TABLE

NV-GK107

BGA

OMIT_TABLE

NV-GK107

1/20W

100

5%

MF

201

100

5%

1/20W

MF

201

97 74

X6S

0.1UF

10%

6.3V

0201

4V

CERM-X6S

0201

1UF

20%

CRITICAL

FERR-220-OHM-2A

0603

CRITICAL

FERR-220-OHM-2A

0603

76 75

78

SOD-VESM-HF

SSM3K15FV

95 76

95 76 73

95 76

95 76 73

95 76

95 76 73

95 76

95 75

95 75 73

95 75

95 75 73

95 75

1%

1/20W

MF

10K

201

PLACE_NEAR=U8000.H26:8.4MM

NOSTUFF

1.33K

1%

1/20W

MF

201

1/20W

1%

1.33K

NOSTUFF

MF

PLACE_NEAR=U8000.H26:8.4MM

201

1/20W

MF

10K

1%

201

10K

MF

1%

1/20W

201

MF

1%

1/20W

10K

201

1/20W

10K

1%

MF

201

60.4

1%

1/20W

MF

201

MF

1/20W

1%

60.4

201

95 76

4V

CERM-X6S

0201

1UF

20%

X6S

0.1UF

10%

6.3V

0201

95 76

1%

MF

10K

1/20W

201

MF

1/20W

1%

10K

201

MF

1/20W

1%

10K

201

MF

1/20W

1%

10K

201

95 76

4V

CERM-X6S

0201

1UF

20%

X6S

0.1UF

10%

6.3V

0201

1%

60.4

1/20W

MF

201

MF

1%

60.4

1/20W

201

PLACE_NEAR=U8000.J27:8.4MM

1%

1/20W

MF

40.2

201

1/20W

MF

40.2

1%

PLACE_NEAR=U8000.H27:8.4MM

201

60.4

1/20W

1% MF

PLACE_NEAR=U8000.H25:8.4MM

201

95 75

PLACE_NEAR=U8000.H26:8.4MM

X6S

0.1UF

10%

NOSTUFF

6.3V

0201

95 76

95 75

C8260

1

2

R8201

1 2

R8204

1

2

R8205

1

2

R8202

1

2

R8203

1

2

C8201

1

2

C8203

1

2

C8202

1

2

R8250

1

2

R8251

1

2

R8252

1

2

R8253

1

2

C8207

1

2

C8206

1

2

R8207

1

2

R8206

1

2

R8255

1

2

R8257

1

2

R8254

1

2

R8256

1

2

R8258

1

2

R8259

1

2

R8261

1 2

Q8265

3

1

2

L8201

1 2

L8202

1 2

C8208

1

2

C8204

1

2

C8205

1

2

R8270

1

2

R8271

1

2

U8000

J27

H27

H25

E1

K27

F2

F1

R30

R31

AB31

AC31

U30

T31

V30

U34

U31

V34

V33

Y32

AA31

AA29

AA28

AC34

U29

AC33

AA32

AA33

Y28

Y29

W31

Y30

AA34

Y31

Y34

R34

Y33

V31

R33

U32

U33

U28

V28

V29

R32

AC32

L28

M29

J29

H28

G29

E31

E32

F30

C34

D32

B33

C33

L29

F33

F32

H33

H32

P34

P32

P31

P33

L31

L34

M28

L32

L33

AG28

AF29

AG29

AF28

AD30

AD29

AC29

AD28

N31

AJ29

AK29

AJ30

AK28

AM29

AM31

AN29

AM30

AN31

AN32

P29

AP30

AP32

AM33

AL31

AK33

AK32

AD34

AD32

AC30

AD33

R29

AF31

AG34

AG32

AG33

P28

J28

H29

R28

AC28

P30

F31

F34

M32

AD31

AL29

AM32

AF34

M30

H30

E34

M34

AF30

AK31

AM34

AF32

M31

G31

E33

M33

AE31

AK30

AN33

AF33

U27

K31

L30

H34

J34

AG30

AG31

AJ34

AK34

J30

J31

J32

J33

AH31

AJ31

AJ32

AJ33

U8000

H26

D12

E12

E20

F20

D13

E14

D15

A14

D14

A15

B15

C17

D18

E18

F18

A20

F14

B20

C18

B18

G18

G17

F17

D16

A18

D17

A17

A12

B17

E17

B12

C14

B14

G15

F15

E15

C12

C20

G9

E9

E6

F6

F4

G4

E2

F3

C2

D4

D3

C1

G8

B3

C4

B5

C5

A11

C11

D11

B11

D8

A8

F9

C8

B8

F24

G23

E24

G24

D21

E21

G21

F21

F11

G27

D27

G26

E27

E29

F29

E30

D30

A32

C31

G11

C32

B32

D29

A29

C29

B29

B21

C23

A21

C21

F12

B24

C24

B26

C26

G12

G6

F5

G14

G20

E11

E3

A3

C9

F23

F27

C30

A24

D9

E4

B2

A9

D22

D28

A30

B23

D10

D5

C3

B9

E23

E28

B30

A23

H17

F8

E8

A5

A6

D24

D25

B27

C27

D6

D7

C6

B6

F26

E26

A26

A27

051-9589

4.18.0

82 OF 132

73 OF 99

73

82

73

95 75 73

73

8

73

8

73

8

73

8

73

95 76 73

95 75 73

95 76 73

73

95 76 73

95 75 73

95 76 73

79 73

8

79

73

8

BG

TGR

TG

PGND

VIN

VSW

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

OUT

IN

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

13A MAX OUTPUT

GPU 1V05 SUPPLY

Vout = 0.5V * (1 + Ra / Rb)

5.3A MAX OUTPUT

F = 500 KHZ

0 0 1.5V

1 0 1.35V

F = 500 KHZ

<Ra>

<Ra>

GPU FB SUPPLY

376S0959

VOUT = 1.05V

376S1038

GPIO(16) VID1 VID0 FBVDD

VOUT = 1.5V / 1.35V

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

1/16W

402

Q3D

CSD58873Q3D

CRITICAL

P1V05_GPU_LL_FET

IHLP2525CZ-SM1

MIN_LINE_WIDTH=0.6 mm

P1V05_S0GPU_REG_R

CRITICAL

P1V05_GPU_BOOT_RC

MIN_LINE_WIDTH=0.3 mm

GPUFB_GPU_OCSET_R

GPUFB_GPU_VO_R

P1V05_GPU_OCSET_R

P1V05_GPU_OCSET

P1V05_GPU_VO_R

P1V05_GPU_VO

=PP5V_S0GPU_P1V0P1V35_GPU

=P1V35FB_EN

GPUFB_FSEL

=PP1V5R1V35_GPU_REG

GPUFB_CS_P

P1V05_GPU_CS_N

P1V05_GPU_SREF

P1V05_S0GPU_PGOOD

=PP1V05_S0GPU_REG

FBVDD_ALTVO

GPUFB_PGOOD

P1V05_GPU_FSEL

=P1V05_GPU_EN

P1V05_GPU_RTN

P1V05_GPU_FB

GPUFB_CS_N

=PPVIN_S0GPU_P1V5P1V0

P1V05_GPU_CS_P

GPUFB_SREF

GPUFB_SET0

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

PP1V5R1V35_GPU_REG_R

MIN_LINE_WIDTH=0.3 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

GPUFB_BOOT_RC

P1V05_GPU_DRVL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

P1V05_GPU_LL

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05_GPU_DRVH_R

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

P1V05_GPU_PEX_IOVDD_SNS_N

VOLTAGE=0V

DIDT=TRUE

P1V05_GPU_VBST

MIN_NECK_WIDTH=0.2 mm

P1V05_GPU_AGND

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

P1V05_GPU_DRVH

PP5V_S0GPU_P1V05_GPU

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.35V

GPU_FBVDDQ_SENSE

VOLTAGE=0V

GPU_FBGND_SENSE

GPUFB_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0GPU_P1V35_GPU

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

P1V05_GPU_PEX_IOVDD_SNS_P

VOLTAGE=1.05V

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GPUFB_DRVL

GPUFB_LL

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

=PPVIN_S0GPU_P1V5P1V0

GPUFB_RTN_DIV

GPUFB_SET_R

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

GPUFB_AGND

GPUFB_SET1

GPUFB_VO

GPUFB_SENSE_DIV

GPUFB_OCSET

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

GPUFB_DRVH_R

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

GPUFB_VBST

DIDT=TRUE

=PP5V_S0GPU_P1V0P1V35_GPU

SYNC_MASTER=D2_SEAN

1V05 GPU / 1V35 FB POWER SUPPLY

SYNC_DATE=03/05/2012

4.75K

1%

1/20W

MF

201

4.75K

1%

1/20W

MF

201

2.74K

1%

1/20W

MF

201

MF

1/20W

1%

2.74K

201

0.68UH-25A-5.5MOHM

CRITICAL

PCMC063T-SM

COG-CERM

0201-1

50V

10PF

5%

COG-CERM

0201-1

50V

10PF

5%

1/20W

1%

1.62K

MF

201

1.62K

1%

1/20W

MF

201

NOSTUFF

MF

1/20W

1%

4.64K

201

4.64K

MF

1/20W

1%

NOSTUFF

201

SM

10%

16V

X7R-CERM

1000PF

SM

CRITICAL

1W

1%

MF

0612

0.002

UTQFN

CRITICAL

ISL95870AH

97

73

97 73

10%

16V

0402

0.01UF

27K

1/20W

MF

201

1%

0603

X6S-CERM

2.2UF

16V

10%

78

NOSTUFF

0

201

1/20W

MF

5%

PLACE_NEAR=U8350.1:1mm

SM

1/20W

1%

MF

150K

201

301K

1%

MF

1/20W

201

88

402

2.2

MF-LF

5%

1/16W

10UF

10V

20%

X6S-CERM

0603

0

1/20W

MF

5%

201

SM

1W

1%

0.003

0612

MF

10%

16V

X7R-CERM

1000PF

0201

97 79

402

2.74K

1/16W

1%

MF-LF

402

2.74K

1%

1/16W

MF-LF

50V

C0G-CERM

0402

10PF

5%

50V

C0G-CERM

0402

10PF

5%

10%

16V

X7R-CERM

0402

0.047UF

1/20W

MF

NOSTUFF

0

201

5%

10%

X5R

16V

603

2.2UF

402

1/16W

1%

3.01K

MF-LF

402

3.01K

1/16W

MF-LF

1%

88

PLACE_NEAR=U8310.1:1mm

SM

ISL95870

UTQFN

CRITICAL

402

1/16W

2.2

MF-LF

5%

X5R

603

10UF

20%

10V

CRITICAL

CASE-B4-SM

TANT

20%

2V

PLACE_NEAR=L8360.2:3MM

270UF

10%

X5R

1UF

603-1

25V

10%

X5R

1UF

603-1

25V

16V

CASE-D2E-SM

402

PLACE_NEAR=Q8310.1:1.5MM

1000PF

5%

402

PLACE_NEAR=L8310.2:1.5MM

25V

NP0-C0G

1000PF

5%

CRITICAL

CASE-B4-SM

270UF

2V

20%

TANT

PLACE_NEAR=L8310.2:3MM

402

MF-LF

5%

MF-LF

1/16W

1

5%

10%

0.1UF

16V

0402

X7R-CERM

402

1

1/16W

5%

MF-LF

PLACE_NEAR=L8360.2:3MM

2V

20%

TANT

CRITICAL

270UF

CASE-B4-SM

CRITICAL

SIZ710DT

POWERPAK-6X3.7

402

0

1/16W

MF-LF

5%

10%

0.1UF

16V

0402

X7R-CERM

16V

68UF

CRITICAL

CASE-D2E-SM

POLY-TANT

20%

402

25V

PLACE_NEAR=Q8360.1:1.5MM

NP0-C0G

1000PF

5%

402

25V

PLACE_NEAR=L8360.2:1.5MM

NP0-C0G

1000PF

5%

2.2

CRITICAL

2.2UH-14A

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

X7R-CERM

MIN_NECK_WIDTH=0.2 mm

POLY-TANT

20%

68UF

CRITICAL

NP0-C0G

25V

0201

OMIT_TABLE

C8361

1

2

C8358

1

2

C8356

1

2

C8355

1

2

R8359

1

2

Q8360

1

6

4 5

237

8

C8360

1

2

R8389

12

L8310

1 2

C8345

1

2

R8346

12

R8325

1

2

C8310

1

2

C8309

1

2

C8308

1

2

C8307

1

2

Q8310

5

9

3

4

1

6

7

8

C8362

1

2

C8312

1

2

C8363

1

2

C8301

1

2

R8301

1

2

U8310

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

XW8300

1 2

R8305

1

2

R8304

1

2

C8302

1

2

R8303

1

2

C8303

1

2

C8305

1

2

C8304

1

2

R8307

1

2

R8306

1

2

C8320

12

R8345

1 2

3 4

XW8301

1

2

XW8302

1

2

R8350

1 2

C8371

1

2

R8351

1

2

R8367

1

2

R8368

1

2

XW8350

1 2

R8363

1

2

C8372

1

2

R8349

1

2

C8373

1

2

U8350

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

R8380

1 2

3 4

XW8351

1

2

C8370

12

XW8352

1

2

R8352

1

2

R8354

1

2

R8381

1 2

R8353

1 2

C8365

1

2

C8376

1

2

L8360

1 2

R8322

1

2

R8321

1

2

R8372

1

2

R8371

1

2

051-9589

4.18.0

83 OF 132

74 OF 99

74

8

99 96

98 96

8

99 96

74

8

98 96

74

8

74

8

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

IN IN

IN

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

NC

BI

IN

BI

IN

BI

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CK TERMINATION - A0

PLACE CLOSE TO U8400

BOM options provided by this page:

Page Notes

(NONE)

- =PP1V5R1V35_S0_FB_VDD

PLACE CLOSE TO U8450

CK TERMINATION - A1

Power aliases required by this page:

Signal aliases required by this page:

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA

201

40.2

MF

1%

1/20W

PLACE_NEAR=U8400.J12:8.4MM

201

PLACE_NEAR=U8450.J12:8.4MM

1/20W

1%

40.2

MF

0201

10%

0.01UF

X7R-CERM

10V

PLACE_NEAR=U8400.J11:8.4MM

0201

10%

0.01UF

X7R-CERM

10V

PLACE_NEAR=U8450.J11:8.4MM

201

PLACE_NEAR=U8400.J11:8.4MM

40.2

MF

1%

1/20W

201

40.2

MF

1%

1/20W

PLACE_NEAR=U8450.J11:8.4MM

201

931

MF

1%

1/20W

PLACE_NEAR=U8400.J14:8.4MM

201

549

MF

1%

1/20W

PLACE_NEAR=U8400.J14:8.4MM

201

1.33K

MF

1%

1/20W

PLACE_NEAR=U8400.J14:8.4MM

0201

10%

X7R-CERM

25V

PLACE_NEAR=U8400.J14:8.4MM

820PF

73 75 76

201

1.33K

MF

1%

1/20W

PLACE_NEAR=U8450.J14:8.4MM

73 75 76

201

PLACE_NEAR=U8450.J14:8.4MM

931

MF

1%

1/20W

201

549

MF

1%

1/20W

PLACE_NEAR=U8450.J14:8.4MM

0201

10%

X7R-CERM

25V

820PF

PLACE_NEAR=U8450.J14:8.4MM

0201

10%

X7R-CERM

25V

PLACE_NEAR=U8400.U10:8.4MM

820PF

201

549

MF

1%

1/20W

PLACE_NEAR=U8400.U10:8.4MM

73 75

76

201

931

MF

1%

1/20W

PLACE_NEAR=U8400.U10:8.4MM

201

1.33K

MF

1%

1/20W

PLACE_NEAR=U8400.U10:8.4MM

0201

10%

25V

X7R-CERM

820PF

PLACE_NEAR=U8400.A10:8.4MM

201

1.33K

MF

1%

1/20W

PLACE_NEAR=U8450.U10:8.4MM

73 75 76

201

PLACE_NEAR=U8450.U10:8.4MM

931

MF

1%

1/20W

201

PLACE_NEAR=U8450.U10:8.4MM

549

MF

1%

1/20W

0201

10%

X7R-CERM

25V

820PF

PLACE_NEAR=U8450.U10:8.4MM

0201

10%

PLACE_NEAR=U8450.A10:8.4MM

820PF

X7R-CERM

25V

20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V 20%

1UF

0201

CERM-X6S

4V

32MX32-1.25GHZ-MFL

OMIT_TABLE

H5GQ1H24AFR-T2C

BGA

32MX32-1.25GHZ-MFL

BGA

OMIT_TABLE

H5GQ1H24AFR-T2C

73 95

73 75 95

73 95

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

73 95

73 75 95

73 95

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

73 95

SYNC_MASTER=D2_SEAN

GDDR5 Frame Buffer A

SYNC_DATE=03/05/2012

FB_A0_DBI_L<3>

FB_A0_DQ<14>

=PP1V35_GPU_FBVDDQ

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A0_VREFC

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A1_VREFC

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A0_VREFD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A1_VREFD

FB_A0_RAS_L

FB_A0_ZQ

FB_A0_MF

FB_A0_CS_L

FB_A0_SEN

FB_A0_WCLK_P<0>

FB_A0_WCLK_N<0>

=PP1V35_GPU_FBVDDQ

FB_A0_WCLK_P<1>

FB_A1_DQ<31>

FB_A1_DQ<30>

FB_A1_DQ<29>

FB_A1_DQ<28>

FB_A1_DQ<27>

FB_A1_DQ<26>

FB_A1_DQ<25>

FB_A1_DQ<24>

FB_A1_DQ<23>

FB_A1_DQ<22>

FB_A1_DQ<21>

FB_A1_DQ<20>

FB_A1_DQ<19>

FB_A1_DQ<18>

FB_A1_DQ<17>

FB_A1_DQ<15>

FB_A1_DQ<14>

FB_A1_DQ<13>

FB_A1_DQ<12>

FB_A1_DQ<11>

FB_A1_DQ<10>

FB_A1_DQ<9>

FB_A1_DQ<8>

FB_A1_DQ<7>

FB_A1_DQ<6>

FB_A1_DQ<5>

FB_A1_DQ<4>

FB_A1_DQ<3>

FB_A1_DQ<2>

FB_A1_ABI_L

FB_A1_EDC<0>

FB_A1_RESET_L

FB_A1_DQ<16>

FB_A1_SEN

FB_A1_RAS_L

FB_A1_MF

FB_A1_ZQ

FB_A1_DQ<0>

FB_A1_DQ<1>

FB_A1_CAS_L

FB_A1_CLK_N

FB_A1_DBI_L<3>

FB_A1_DBI_L<2>

FB_A1_DBI_L<1>

FB_A0_DQ<20>

FB_A0_A<6>

FB_A0_A<0>

FB_A0_DBI_L<2>

FB_A0_DQ<0>

FB_A0_DQ<1>

FB_A0_DQ<2>

FB_A0_DQ<3>

FB_A0_A<7>

FB_A0_DQ<5>

FB_A0_DQ<27>

FB_A0_DQ<31>

FB_A0_DQ<30>

FB_A0_DQ<28>

FB_A0_DQ<26>

FB_A0_DQ<22>

FB_A0_DQ<25>

FB_A0_DQ<24>

FB_A0_DQ<23>

FB_A0_DQ<21>

FB_A0_DQ<19>

FB_A0_DQ<18>

FB_A0_DQ<17>

FB_A0_RESET_L

FB_A0_DQ<16>

FB_A0_DQ<15>

FB_A0_DQ<12>

FB_A0_DQ<11>

FB_A0_DQ<10>

FB_A0_DQ<7>

FB_A0_DQ<6>

FB_A0_DQ<4>

FBA1_CK_MIDFB_A1_CLK_P

FBA0_CK_MID

FB_A0_CAS_L

FB_SW_LEG

FB_A1_VREFD

FB_A1_VREFC

FB_A0_VREFD

FB_A0_VREFC

FB_A0_A<1>

FB_SW_LEG

FB_A0_A<8>

FB_SW_LEG

FB_A1_WCLK_N<1>

FB_A1_CLK_N

FB_A0_CLK_P FB_A0_CLK_N

FB_A0_A<2>

FB_A0_A<3>

FB_A0_A<5>

FB_A0_DQ<13>

FB_A0_DBI_L<0>

FB_A0_DBI_L<1>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_P<0>

FB_A1_A<6>

FB_A1_A<5>

FB_A1_A<0>

FB_A1_CKE_L

FB_A1_A<2>

FB_A1_A<3>

FB_A1_A<4>

FB_A1_WE_L

FB_A1_A<1>

FB_A1_A<7>

FB_A1_CS_L

FB_A1_DBI_L<0>

FB_A1_A<8>

FB_A0_A<4>

FB_A0_CLK_P

FB_A0_CLK_N

FB_A1_CLK_P

FB_A0_DQ<29>

=PP1V35_GPU_FBVDDQ

FB_A0_CKE_L

FB_A0_WE_L

FB_A0_ABI_L

FB_A0_WCLK_N<1>

FB_A0_EDC<0>

FB_A0_EDC<3>

FB_A0_EDC<2>

FB_A0_EDC<1> FB_A1_EDC<2>

FB_A1_EDC<1>

FB_A1_EDC<3>

FB_A0_DQ<9>

FB_A0_DQ<8>

U8400

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

U8400

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

C8416

1

2

C8417

1

2

C8418

1

2

C8419

1

2

C8420

1

2

C8421

1

2

C8422

1

2

C8423

1

2

C8424

1

2

C8425

1

2

U8450

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

C8467

1

2

C8466

1

2

C8471

1

2

C8475

1

2

C8470

1

2

C8474

1

2

C8469

1

2

C8473

1

2

C8468

1

2

C8472

1

2

C8400

1

2

C8401

1

2

C8402

1

2

C8403

1

2

C8404

1

2

C8405

1

2

C8450

1

2

C8451

1

2

C8452

1

2

C8453

1

2

C8454

1

2

C8455

1

2

R8403

1

2

R8404

1

2

R8400

1

2

R8453

1

2

R8454

1

2

R8450

1

2

U8450

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

R8401

1 2

R8451

1 2

C8490

1

2

C8491

1

2

R8402

1 2

R8452

1 2

R8434

1

2

R8430

1

2

R8431

1

2

C8431

1

2

R8481

1

2

R8484

1

2

R8480

1

2

C8481

1

2

C8433

1

2

R8432

1

2

R8435

1

2

R8433

1

2

C8432

1

2

R8483

1

2

R8485

1

2

R8482

1

2

C8483

1

2

C8482

1

2

C8456

1

2

C8457

1

2

C8458

1

2

C8459

1

2

C8460

1

2

C8461

1

2

C8462

1

2

C8463

1

2

C8464

1

2

C8465

1

2

C8406

1

2

C8407

1

2

C8408

1

2

C8409

1

2

C8410

1

2

C8411

1

2

C8412

1

2

C8413

1

2

C8414

1

2

C8415

1

2

051-9589

4.18.0

84 OF 132

75 OF 99

8

72 75 76

75 75

75

8

72 75 76

8

72 75 76

8

72 75 76

73

75

95

75

73

75

95

73 75 95 73 75 95

8

72 75 76

8

72 75 76

IN

BI

IN

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

NC

BI

IN

BI

IN

BI

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

IN

NC

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7

A9/A1

DBI2*

WE*

BA2/A4

BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

(MF=0)

(1 OF 2)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

(NONE)

Page Notes

(NONE)

CK TERMINATION - B0

CK TERMINATION - B1

Power aliases required by this page:

PLACE CLOSE TO U8500

PLACE CLOSE TO U8550

73 95

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

X6S

0402

4.7UF

6.3V

20%

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

120

MF

1%

1/20W

201

40.2

MF

1%

1/20W

PLACE_NEAR=U8500.J11:8.4MM

201

PLACE_NEAR=U8500.J11:8.4MM

10V

X7R-CERM

0.01UF

10%

0201

PLACE_NEAR=U8500.J12:8.4MM

40.2

MF

1%

1/20W

201

1/20W

40.2

MF

1%

PLACE_NEAR=U8550.J11:8.4MM

201

PLACE_NEAR=U8550.J11:8.4MM

10V

X7R-CERM

0.01UF

10%

0201

40.2

MF

1/20W

1%

PLACE_NEAR=U8550.J12:8.4MM

201

MF

1%

1/20W

1.33K

PLACE_NEAR=U8500.J14:8.4MM

201

73 75 76

PLACE_NEAR=U8500.J14:8.4MM

MF

1%

1/20W

931

201

PLACE_NEAR=U8500.J14:8.4MM

549

MF

1%

1/20W

201

X7R-CERM

25V

PLACE_NEAR=U8500.J14:8.4MM

820PF

10%

0201

PLACE_NEAR=U8500.U10:8.4MM

1.33K

MF

1%

1/20W

201

PLACE_NEAR=U8500.U10:8.4MM

931

MF

1%

1/20W

201

PLACE_NEAR=U8500.U10:8.4MM

549

MF

1%

1/20W

201

73 75 76

820PF

X7R-CERM

25V

PLACE_NEAR=U8500.A10:8.4MM

10%

0201 X7R-CERM

25V

820PF

PLACE_NEAR=U8500.U10:8.4MM

10%

0201

PLACE_NEAR=U8550.J14:8.4MM

549

MF

1%

1/20W

201

73 75 76

PLACE_NEAR=U8550.J14:8.4MM

931

MF

1%

1/20W

201

PLACE_NEAR=U8550.J14:8.4MM

1.33K

MF

1%

1/20W

201

X7R-CERM

25V

820PF

PLACE_NEAR=U8550.J14:8.4MM

10%

0201

X7R-CERM

25V

820PF

PLACE_NEAR=U8550.U10:8.4MM

10%

0201

73 75 76

PLACE_NEAR=U8550.U10:8.4MM

931

MF

1%

1/20W

201

PLACE_NEAR=U8550.U10:8.4MM

549

MF

1%

1/20W

201

1.33K

PLACE_NEAR=U8550.U10:8.4MM

MF

1%

1/20W

201

820PF

X7R-CERM

25V

PLACE_NEAR=U8550.A10:8.4MM

10%

0201

4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20%

4V

CERM-X6S

0201

1UF

20% 4V

CERM-X6S

0201

1UF

20%

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA

H5GQ1H24AFR-T2C

OMIT_TABLE

32MX32-1.25GHZ-MFL

BGA

73 95

73 76 95

73 95

120

MF

1%

1/20W

201

73 95

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

73 95

73 76 95

73 95

32MX32-1.25GHZ-MFL

OMIT_TABLE

H5GQ1H24AFR-T2C

BGA

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

X6S

0.1UF

10%

6.3V

0201

73 95

OMIT_TABLE

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

BGA

SYNC_DATE=03/05/2012

GDDR5 Frame Buffer B

SYNC_MASTER=D2_SEAN

=PP1V35_GPU_FBVDDQ

FB_B0_VREFD

FB_B0_VREFC

=PP1V35_GPU_FBVDDQ

FB_B1_CLK_N

FB_B1_WCLK_N<1>

FB_B1_ZQ

FB_B1_A<6>

FB_B1_A<3>

FB_B1_A<4>

FB_B1_A<2>

FB_B0_DQ<17>

FB_B0_DQ<22>

FB_B0_DQ<31>

FB_B1_CLK_P

FB_B1_CKE_L

FB_B1_CAS_L

FB_B1_RAS_L

FB_B1_SEN

FB_B0_DQ<23>

FB_B0_DQ<24>

FB_B0_DQ<25>

FB_B0_DQ<26>

=PP1V35_GPU_FBVDDQ

FB_B0_DQ<30>

FB_B0_DQ<29>

FB_B0_DQ<27>

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

FB_B0_RAS_L

FB_B1_VREFD

FB_B1_VREFC

FB_SW_LEG

FB_B1_RESET_L

FB_B0_RESET_L

FB_B0_CS_L

FB_B0_WE_L

FB_B0_CAS_L

FB_B0_WCLK_N<1>

FB_B0_WCLK_P<1>

FB_B0_WCLK_N<0>

FB_B0_A<6>

FB_B0_A<0>

FB_B0_A<1>

FB_B1_WCLK_P<1>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<0>

FB_B1_WE_L

FB_B1_A<0>

FB_B1_A<1>

FB_B1_A<7>

FB_B1_A<5>

FB_B1_DBI_L<2>

FB_B1_DBI_L<1>

FB_B1_DBI_L<0>

FB_B0_DBI_L<0>

FB_B0_CKE_L

FB_B1_CS_L

FB_B1_CLK_N

FB_B0_CLK_P

FB_B0_CLK_N

FB_B0_CLK_P

FB_B0_SEN

FB_B0_ABI_L

FBB0_CK_MID

FB_B1_CLK_P

FB_B0_CLK_N

FB_B0_MF

FBB1_CK_MID

FB_B0_DBI_L<1>

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B0_DQ<7>

FB_B0_DQ<8>

FB_B0_DQ<13>

FB_B0_DQ<10>

FB_B0_DQ<15>

FB_B0_DQ<0>

FB_B0_DQ<1>

FB_B0_DQ<2>

FB_B0_DQ<3>

FB_B0_DQ<4>

FB_B0_DQ<5>

FB_B0_DQ<6>

FB_B0_DQ<9>

FB_B0_DQ<11>

FB_B0_DQ<12>

FB_B0_DQ<16>

FB_B0_DQ<18>

FB_B0_DQ<19>

FB_B0_DQ<28>

FB_B0_WCLK_P<0>

FB_B1_DQ<0>

FB_B1_DQ<1>

FB_B1_A<8>

FB_B1_DBI_L<3>

FB_B1_DQ<2>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<5>

FB_B1_DQ<6>

FB_B1_DQ<7>

FB_B1_DQ<8>

FB_B1_DQ<9>

FB_B1_DQ<10>

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_B1_DQ<15>

FB_B1_DQ<16>

FB_B1_DQ<17>

FB_B1_DQ<18>

FB_B1_DQ<19>

FB_B1_DQ<20>

FB_B1_DQ<21>

FB_B1_DQ<22>

FB_B1_DQ<23>

FB_B1_DQ<24>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<28>

FB_B1_DQ<29>

FB_B1_DQ<30>

FB_B1_DQ<31>

FB_B0_DQ<14>

FB_B0_DQ<20>

FB_B0_DQ<21>

FB_B0_A<3>

FB_B0_A<5>

FB_B0_A<4>

FB_B0_A<7>

FB_B1_ABI_L

FB_B1_MF

FB_B1_EDC<2>

FB_B1_EDC<1>

FB_B1_EDC<3>

FB_B1_EDC<0>

FB_B0_EDC<0>

FB_B0_EDC<2>

FB_B0_EDC<3>

FB_B0_EDC<1>

FB_B0_ZQ

FB_SW_LEG

FB_B0_A<8>

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B1_VREFC

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B1_VREFD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B0_VREFD

=PP1V35_GPU_FBVDDQ

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B0_VREFC

FB_B0_A<2>

U8500

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

U8500

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

R8500

1

2

C8516

1

2

C8517

1

2

C8518

1

2

C8519

1

2

C8520

1

2

C8521

1

2

C8522

1

2

C8523

1

2

C8524

1

2

C8525

1

2

U8550

C5

C10

L14

P11

R5

R10

D11

G1

G4

G11

G14

L1

L4

L11

B1

B3

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

B12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

B14

P12

P14

T1

T3

T12

T14

D1

D3

D12

D14

E5

E10

J14

A10

U10

B5

B10

L10

P10

T5

T10

D10

G5

G10

H1

H14

K1

K14

L5

A1

A3

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

A12

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

A14

R12

R14

U1

U3

U12

U14

C1

C3

C4

C11

C12

C14

C8567

1

2

C8566

1

2

C8571

1

2

C8575

1

2

C8570

1

2

C8574

1

2

C8569

1

2

C8573

1

2

C8568

1

2

C8572

1

2

U8550

H4

K5

K4

H5

J4

H11

K10

K11

H10

L3

J12

J11

J3

G12

D2

D13

P13

P2

A4

A2

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

B4

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

B2

M4

M2

E4

E2

F4

F2

A11

A13

C2

C13

R13

R2

J1

A5

J5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

C8500

1

2

C8501

1

2

C8502

1

2

C8505

1

2

C8504

1

2

C8503

1

2

C8550

1

2

C8551

1

2

C8552

1

2

C8553

1

2

C8554

1

2

C8555

1

2

R8504

1

2

R8503

1

2

R8553

1

2

R8554

1

2

R8550

1

2

R8502

1 2

C8590

1

2

R8501

1 2

R8552

1 2

C8591

1

2

R8551

1 2

R8531

1

2

R8534

1

2

R8530

1

2

C8531

1

2

R8533

1

2

R8535

1

2

R8532

1

2

C8532

1

2

C8533

1

2

R8580

1

2

R8584

1

2

R8581

1

2

C8581

1

2

C8583

1

2

R8585

1

2

R8582

1

2

R8583

1

2

C8582

1

2

C8506

1

2

C8507

1

2

C8508

1

2

C8509

1

2

C8510

1

2

C8511

1

2

C8512

1

2

C8513

1

2

C8514

1

2

C8515

1

2

C8556

1

2

C8557

1

2

C8558

1

2

C8559

1

2

C8560

1

2

C8561

1

2

C8562

1

2

C8563

1

2

C8564

1

2

C8565

1

2

051-9589

4.18.0

85 OF 132

76 OF 99

8

72 75 76

76

8

72 75 76

73

76

95

8

72 75 76

8

72 75 76

8

72 75 76

76

73 76 95

73

76

95

73 76 95

76

8

72 75 76

76

BI

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

BI

OUT

BI

OUT

D

S G

D

S G

BI

OUT

BI

IFPEF_PLLVDD

IFPEF_RSET

IFPD_RSET

IFPD_PLLVDD

I2CA_SDA

IFPF_IOVDD

IFPAB_PLLVDD

IFPAB_RSET

IFPC_PLLVDD

IFPC_RSET

IFPC_L1

IFPC_L0*

IFPC_L0

IFPC_AUX_I2CW_SCL

IFPB_TXD7*

IFPA_TXD3*

IFPB_TXC

DACA_VREF

DACA_RSET

IFPE_IOVDD

I2CA_SCL

IFPC_L3*

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

IFPF_AUX_I2CZ_SDA*

IFPF_AUX_I2CZ_SCL

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX_I2CY_SDA*

IFPE_AUX_I2CY_SCL

IFPD_L3*

IFPD_L3

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

IFPD_IOVDD

IFPC_L3

IFPC_L1*

IFPC_IOVDD

IFPC_AUX_I2CW_SDA*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD6

IFPB_TXD5*

IFPB_TXD5

IFPB_TXD4*

IFPB_TXD4

IFPB_TXC*

IFPB_IOVDD

IFPA_TXD3

IFPA_TXD2*

IFPA_TXD2

IFPA_TXD1*

IFPA_TXD1

IFPA_TXD0*

IFPA_TXD0

IFPA_TXC

IFPA_IOVDD

I2CS_SDA

I2CS_SCL

I2CC_SDA

I2CC_SCL

I2CB_SDA

I2CB_SCL

DACA_VSYNC

DACA_VDD DACA_RED

DACA_HSYNC

DACA_GREEN

DACA_BLUE

CEC

IFPA_TXC*

IFPD_L2*

IFPC_L2

IFPC_L2*

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA*

(5 OF 10)

OUT

NC

BI

OUT

NC

THERMDP

THERMDN

JTAG_TRST*

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

STRAP3

STRAP4

STRAP2

STRAP1

STRAP0

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

VID_PLLVDD

PLLVDD

SP_PLLVDD

TESTMODE

MULTI_STRAP_REF0_GND

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS*

VDD33

GPIO20

GPIO16

GPIO0

GPIO1

GPIO2

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO13

GPIO14

GPIO15

GPIO17

GPIO18

GPIO19

GPIO21

GPIO11

GPIO12

GPIO4

GPIO3

(6 OF 10)

IN

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- D2:YES

- =PP1V05_GPU_IFPCD_IOVDD

PD FOR RSET

DDC 3.3V/5V LEVEL TRANSLATOR

Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other

GPU PLL VDD

PLACE BELOW GPU NEAR DISPLAY SECTION

ESR = 0.05OHM

I2CA -> IFPE

I2CC -> SSC CLK GEN

IFP CD IOVDD

DDC MAPPING

I2CB -> IFPF

ESR = 0.05OHM

IFP EF IOVDD

- =PP1V05_GPU_DPLL

- =PP1V05_GPU_IFPEF_IOVDD

- =PP1V8_GPU_DPLL

- =PP1V8_GPU_IFPA_IOVDD

- =PP3V3_GPU_IFPX_PLLVDD

Signal aliases required by this page:

- =PP3V3_GPU_VDD33

BOM options provided by this page:

Page Notes

- J31:YES

(NONE)

ESR = 0.05OHM

GPU 3V3 VDD

---------------------

PD FOR AUX CHANNELS (FOR NVIDIA)

IFPX PLLVDD

- =PP3V3_GPU_IFPB_IOVDD

Power aliases required by this page:

DISABLE PHY A & B FOR 15" MBP

78

47 96

78

78 95

77 95

0201

PLACE_NEAR=U8000.J1:5MM

MF

0.1%

1/20W

40.2K

25V

10%

1UF

X6S-CERM

04020402

X6S-CERM

10%

1UF

25V

X6S-CERM

20%

10UF

0603

10V

20%

6.3V

X6S

0402

4.7UF

20%

6.3V

X6S

0402

4.7UF

1UF

20%

0201

CERM-X6S

4V

78

10K

PLACE_NEAR=U8000.J4:8.4MM

1%

201

1/20W

MF

10K

201

MF

1/20W

1%

PLACE_NEAR=U8000.H1:8.4MM

83

MF

100K

201

1/20W

1%

201

MF

1%

100K

1/20W

1%

MF

201

100K

1/20W

1%

1/20W

MF

201

100K

1%

1/20W

MF

201

100K

MF

1%

1/20W

100K

201

PLACE_NEAR=U8000.AN2:5MM

1%

1/20W

MF

1K

201

1%

1/20W

MF

201

1K

PLACE_NEAR=U8000.AD6:5MM

83

78

CRITICAL

0603

FERR-220-OHM-2A

CRITICAL

0603

FERR-220-OHM-2A

0603

CRITICAL

10%

6.3V

4.7UF

X6S-CERM

0603

20%

6.3V

X6S

0402

4.7UF

1UF

20%

0201

CERM-X6S

4V

1UF

20%

0201

CERM-X6S

4V

4.7K

201

MF

1/20W

1%

201

1/20W

4.7K

MF

1%

PLACE_NEAR=U8000.AF8:5MM

1K

201

1%

1/20W

MF

20%

4V

10UF

0402-1

X6S-CERM

1UF

20%

0201

CERM-X6S

4V

7

38

95

7

38

95

7

38

95

7

38 95

7

38 95

7

38 95

7

38 95

7

38 95

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

SOT563

7

38

MF

1/20W

1%

4.7K

201

1/20W

MF

201

1%

4.7K

NO STUFF

1%

MF

201

100K

1/20W

NO STUFF

1%

MF

201

100K

1/20W

7

38

20%

6.3V

X6S

0402

4.7UF

78

X6S-CERM

16V

20%

0.1UF

0201

X6S-CERM

16V

20%

0.1UF

0201

0.1UF

20%

16V

X6S-CERM

0201 0201

X6S-CERM

16V

20%

0.1UF

0201

0.1UF

20%

16V

X6S-CERM 0201

0.1UF

20%

16V

X6S-CERM

16V

20%

0.1UF

0201 0201

0.1UF

20%

16V

X6S-CERM

0201

0.1UF

20%

16V

X6S-CERM 0201

X6S-CERM

16V

20%

0.1UF

X6S-CERM

16V

20%

0.1UF

0201 0201

0.1UF

20%

16V

X6S-CERM

0201

0.1UF

20%

16V

X6S-CERM

0201

0.1UF

20%

16V

X6S-CERM X6S-CERM

16V

20%

0.1UF

0201

X6S-CERM

16V

20%

0.1UF

0201 0201

0.1UF

20%

16V

X6S-CERM

77 82 95

NV-GK107

CRITICAL

OMIT_TABLE

BGA

82 95

77 83 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

7

35 95

1/20W

201

1%

10K

MF

1%

1/20W

MF

10K

201

1%

1/20W

MF

201

10K

1%

1/20W

MF

201

10K

10%

1UF

0402

X6S-CERM

25V

20%

10UF

0603

X6S-CERM

10V

0603

330-OHM-1.2A

CRITICAL

20%

10UF

0603

X6S-CERM

10V 10%

1UF

0402

X6S-CERM

25V 10%

1UF

0402

X6S-CERM

25V

20%

4V

10UF

0402-1

X6S-CERM

1UF

20%

0201

CERM-X6S

4V

1UF

20%

0201

CERM-X6S

4V

20%

6.3V

X6S

0402

4.7UF

BGA

NV-GK107

OMIT_TABLE

MF

1%

201

1/20W

10K

78

SYNC_DATE=03/05/2012

KEPLER EDP/DP/GPIO

SYNC_MASTER=D2_SEAN

MAKE_BASE=TRUE

PP1V05_GPU_SP_PLLVDD

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

PP1V05_GPU_IFPAB_PLLVDD

MIN_LINE_WIDTH=0.5 MM

PP3V3_GPU_IFPB_IOVDD

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

GPU_MLS_STRAP2

GPU_MLS_STRAP1

HDMI_EG_DATA_C_N<0>

=PP3V3_GPU_MISC

=PP3V3_GPU_VDD33

GPU_ROM_CS_L

PP1V05_GPU_PLLVDD

HDMI_EG_DDC_DATA_Q

=PP3V3_GPU_VDD33

DP_INT_EG_ML_P<0>

DP_INT_EG_ML_N<0>

GPU_OSC_27M_XTAL_BUFFOUT_R

HDMI_EG_DDC_DATA

GPU_ROM_SCLK

GPU_TESTMODE

PP1V05_GPU_VID_PLLVDD

HDMI_EG_DDC_CLK_Q

PP3V3_GPU_IFPB_IOVDD

PP1V8_GPU_IFPA_IOVDD

HDMI_EG_CLK_C_P

HDMI_EG_DATA_C_P<0>

HDMI_EG_DATA_C_N<2>

HDMI_EG_DATA_C_P<2>

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK1_EG_AUXCH_N

GPU_MLS_STRAP3

HDMI_EG_DDC_CLK

=PP1V05_GPU_PEX_PLLVDD

PP3V3_GPU_IFPX_PLLVDD

IFPEF_RSET

IFPD_RSET

PP3V3_GPU_IFPX_PLLVDD

DPA_EG_DDC_DATA

PP1V05_GPU_IFPEF_IOVDD

PP1V05_GPU_IFPAB_PLLVDD

PP3V3_GPU_IFPX_PLLVDD

IFPC_RSET

HDMI_EG_DATA_C_P<1>

PP1V05_GPU_IFPEF_IOVDD

DPA_EG_DDC_CLK

HDMI_EG_CLK_C_N

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK0_EG_AUXCH_P

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_P<2>

DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<1>

PP1V05_GPU_IFPCD_IOVDD

HDMI_EG_DATA_C_N<1>

PP1V05_GPU_IFPCD_IOVDD

GPU_SMB_DAT

GPU_SMB_CLK

GPU_SSC_SMB_DAT

DPB_EG_DDC_DATA

DPB_EG_DDC_CLK

DAC_AVDD

DP_INT_EG_ML_N<2>

DP_INT_EG_AUX_P

DP_INT_EG_AUX_N

GPU_OSC_27M_XTALIN

=PP3V3_GPU_VDD33

IFPD_RSET

IFPEF_RSET

IFPC_RSET

PP1V05_GPU_SP_PLLVDD

=PP1V05_GPU_IFPCD_IOVDD

=PP1V05_GPU_IFPEF_IOVDD

PP1V05_GPU_VID_PLLVDD

GPU_OSC_27M_SSIN

GPU_OSC_27M_XTALOUT

GPU_MLS_STRAP0

GPU_MLS_STRAP4

GPU_JTAG_TRST_L

GPU_JTAG_TCK

GPU_JTAG_TDO

GPU_JTAG_TMS

GPU_TESTMODE

GPU_OSC_27M_XTAL_BUFFOUT_R

GPU_JTAG_TDI

GPU_TDIODE_N

MULTI_STRAP_REF

GPU_TDIODE_P

HDMI_EG_DDC_CLK_Q

=PP3V3_GPU_IFPX_PLLVDD

HDMI_EG_DDC_DATA_Q

GPU_ROM_SI

GPU_ROM_SO

DP_TBTSNK0_EG_AUXCH_P

DP_INT_EG_AUX_N

DP_INT_EG_AUX_P

DP_TBTSNK0_EG_AUXCH_N

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.8V

PP1V8_GPU_IFPA_IOVDD

GPU_GPIO_0

GPU_GPIO_1

GPU_GPIO_2

GPU_GPIO_3

GPU_GPIO_4

GPU_GPIO_5

GPU_GPIO_6

GPU_GPIO_7

GPU_GPIO_8

GPU_GPIO_9

GPU_GPIO_10

GPU_GPIO_11

GPU_GPIO_12

GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_GPIO_16

GPU_GPIO_17

GPU_GPIO_18

GPU_GPIO_19

GPU_GPIO_20

GPU_GPIO_21

GPU_SSC_SMB_CLK

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_P<1>

PP3V3_GPU_IFPX_PLLVDD

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 MM

PP1V05_GPU_IFPEF_IOVDD

=PP3V3_GPU_VDD33

=PP3V3_GPU_MISC

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.41 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_GPU_PLLVDD

PP1V05_GPU_IFPCD_IOVDD

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5 MM

20%

0402

X6T-CERM

2V

20UF

U8000

L3

AL9

AL10

AM9

AK9

AP8

AG10

AP9

AN9

R4

R5

R7

R6

R2

R3

T4

T3

AG8 AM6

AN6

AP3

AN3

AN5

AM5

AL6

AK6

AJ6

AH6

AH8

AJ8

AG9

AJ9

AH9

AP6

AP5

AM7

AL7

AN8

AM8

AK8

AL8

AG3

AG2

AF6

AK1

AJ1

AJ3

AJ2

AH3

AH4

AG5

AG4

AF7

AF8

AK3

AK2

AG6

AM1

AM2

AM3

AM4

AL3

AL4

AK4

AK5

AG7

AN2

AB3

AB4

AC7

AD2

AD3

AD1

AC1

AC2

AC3

AC4

AC5

AB8

AD6

AF3

AF2

AC8

AE3

AE4

AF4

AF5

AD4

AD5

AG1

AF1

R8600

1

2

R8601

1

2

R8602

1

2

R8603

1

2

C8611

1

2

C8610

1

2

L8604

1 2

C8613

1

2

C8615

1

2

C8616

1

2

C8629

1

2

C8636

1

2

C8635

1

2

C8634

1

2

U8000

P6

M3

L1

M5

N3

M4

N4

P2

R8

M6

R1

P3

L6

P4

P1

P5

P7

L7

M7

N8

M1

M2

AM10

AM11

AP12

AP11

AN11

J1

AD8

H6

H4

H5

H7

AE8

J2

J7

J6

J5

J3

AK11

K4

K3

J8

K8

L8

M8

AD7

H3

H2

J4

H1

R8608

1

2

R8609

1 2

C8642

1

2

C8641

1

2

C8640

1

2

C8646

1

2

C8645

1

2

C8652

1

2

R8611

1

2

R8612

1

2

R8613

1

2

R8614

1

2

R8615

1

2

R8616

1

2

R8617

1

2

R8618

1

2

R8606

1

2

R8607

1

2

C8651

1

2

L8606

1 2

L8605

1 2

L8607

1 2

C8619

1

2

C8633

1

2

C8630

1

2

C8626

1

2

R8623

1

2

R8624

1

2

R8621

1

2

C8655

1

2

C8656

1

2

Q8600

3

5

4

Q8600

6

2

1

R8626

1

2

R8625

1

2

R8628

1

2

R8627

1

2

C8625

1

2

C8650

1

2

C8612

1

2

C8617

1

2

C8618

1

2

C8627

1

2

C8628

1

2

C8631

1

2

C8632

1

2

C8637

1

2

C8638

1

2

C8643

1

2

C8644

1

2

C8649

1

2

C8653

1

2

C8654

1

2

C8657

1

2

C8658

1

2

051-9589

4.18.0

86 OF 132

77 OF 99

77 79

77

8

77

8

71 77 78 79

77

8

71 77 78 79

77

77 83 95

8

79

77

8

71 77 78

79

8

71 77 78 79

77 77 77

77 79

77

77 95

77

77 83 95

77 82 95

77 83 95

77

8

71 77 78 79

8

77

OUT

IN

OUT

GND

THRM

VCC

CS*

WP*

SI

SCLK

SO

HOLD*

PAD

NC

IN

D

G S

OUT

NC

08

NC

BI

OUT

BI

D

S G

D

S G

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU internal Temp isolation

Straps for GK107. GF108 support has been removed.

GPU overtemp masking

STRAP NOTES:

GC6 SUPPORT

Unused signals

0x4

CONFIG STRAPS - MLPS

Strap

0x1

0x0

M-DIE

D-DIE

GP

GPIOs

Native Func

GPU XTAL 27 MHZ

GP

GPIOs

GP

Native Func

GP

Die Rev

Note: PU to non GPU_S0 3v3 source

A-DIE

GPU GC6 ROM

STUFF R8705 FOR THIN DIE

STUFF R8704 FOR THICK DIE

CURRENTLY STUFFED FOR GF108a/GK107-GTX

0

MF

1/20W

NO STUFF

201

5%

0

MF

1/20W

201

5%

41 42 78

MF

10K

1/20W

201

5%

10K

MF

1/20W

201

5%

78 82

74 78

77 95

0

MF

201

5%

1/20W

33

MF

GPU_ROM:YES

0201

X6S

6.3V

10%

0.1UF

GPU_ROM:YES

9

82

201

1/20W

1%

MF

5.62K

NOSTUFF

77

1%

MF

201

NOSTUFF

3.24K

1/20W

77

5.62K

1/20W

NOSTUFF

1%

MF

201

77

1/20W

3.24K

1%

MF

201

77 78

3.24K

MF

1/20W

1%

201

NOSTUFF

77 78

201

45.3K

1/20W

1%

MF

25.5K

MF

1%

1/20W

201

OMIT_TABLE

CRITICAL

USON

MX25L1005CMI-12G

1MBIT

OMIT_TABLE

0

MF

1/20W

NO STUFF

201

5%

GPU_ROM:YES

0

1/20W

MF

201

5%

GPU_ROM:YES

33

MF

1/20W

201

5%

GPU_ROM:YES

33

MF

1/20W

201

5%

GPU_ROM:YES

MF

10K

1/20W

201

25V

NP0-C0G-CERM

0201

18PF

5% 5%

25V

NP0-C0G-CERM

0201

18PF

20K

1/20W

1%

MF

201

MF

1/20W

33

201

5%

GPU_ROM:YES

MF

1/20W

10K

201

5%

1/20W

MF

10K

201

5%

10K

1/20W

MF

201

5%

NO STUFF

5%

201

MF

1/20W

10K

1%

MF

201

NOSTUFF

1/20W

10K

MF

1/20W

201

1%

MF

1%

201

15K

1/20W

NOSTUFF

SSM3K15FV

SOD-VESM-HF

41

42

78

MF

1/20W

10K

201

5%

NOSTUFF

5%

201

1/20W

10K

MF

SOT891

74LVC1G08

41

77

10K

MF

201

5%

1/20W

0

5%

NOSTUFF

201

1/20W

MF

SOT563

SSM6N37FEAPE

10K

1/20W

MF

201

5%

SOT563

SSM6N37FEAPE

0

5%

1/20W

MF

201

NOSTUFF

44

MF

1/20W

1%

24.9K

201

MF

1/20W

1%

30K

201

MF

1%

1/20W

45.3K

201

0

5%

1/20W

MF

201

1/20W

MF

201

0

5%

NOSTUFF

10K

1/20W

MF

201

5%

NOSTUFF

201

1%

MF

45.3K

1/20W

201

10K

5%

1/20W

MF

NOSTUFF

MF

1/20W

5%

10K

201

MF

1/20W

1%

34.8K

NOSTUFF

201

R8711

118S0414

1

FB_2G_HYNIX_M_DIE

RES,5.1KOHM, 0201

118S0013

RES, 10KOHM, 0201

FB_2G_SAMSUNG

1

R8711

118S0230

R8711

FB_2G_HYNIX_A_DIE

1

RES,MF,24.9KOHM,1,1/20W,0201

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

KEPLER GPIOS,CLK & STRAPS

SMC_GFX_OVERTEMP_R_L

GPU_RESET_L

GPU_GPIO_9

SMC_GFX_OVERTEMP_R_L

SMC_GFX_OVERTEMP_Q

=PP3V3_GPU_VDD33

EG_LCD_PWR_EN

GPU_ROM_SI

GPU_ROM_SCLK

=PP3V3_GPU_VDD33

GPU_MLS_STRAP2

GPU_ROM_SI

=PP3V3_GPU_VDD33

FB_CLAMP_TOGGLE_REQ_L

TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

GPU_JTAG_TMS

=PP3V3_GPU_VDD33

PEX_CLKREQ_L_R EG_CLKREQ_IN_L

GPU_GPIO_16

GPU_GPIO_15

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_GPU_OVERTEMP

EG_LCD_PWR_EN

MAKE_BASE=TRUE

GFXIMVP_PSI_R_L

MAKE_BASE=TRUE

HDMI_EG_HPD

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

FB_CLAMP_TOGGLE_REQ_L

MAKE_BASE=TRUE

GFXIMVP_VID<2>

MAKE_BASE=TRUE

GFXIMVP_VID<1>

MAKE_BASE=TRUE

GFXIMVP_VID<4>

GFXIMVP_VID<3>

MAKE_BASE=TRUE

DP_INT_EG_HPD

MAKE_BASE=TRUE

DP_EXTB_CA_DET_EG

MAKE_BASE=TRUE

DP_EXTA_CA_DET_EG

MAKE_BASE=TRUE

GFXIMVP_VID<0>

MAKE_BASE=TRUE

GFXIMVP_VID<5>

MAKE_BASE=TRUE

GPU_ALT_VREF

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TCK

MAKE_BASE=TRUE

FBVDD_ALTVO

MAKE_BASE=TRUE

NC_GPU_GPIO_21_RSVD

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_20_RSVD

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_TBTSNK1_HPD_EG

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_EG

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP

FBVDD_ALTVO

EG_BKLT_EN

=PP3V3_GPU_VDD33

=PP3V3_S5_SMC

GPU_GPIO_17

GPU_GPIO_19

GPU_GPIO_20

=PP3V3_GPU_VDD33

GPU_ROM_SO_R

GPU_ROM_SO

GPU_ROM_SCLK_R

GPU_ROM_SCLK

GPU_ROM_CS_L

GPU_ROM_CS_L_R

GPU_ROM_WP_L

GPU_ROM_SI_R

GPU_ROM_SO

GPU_GPIO_21

SMC_GFX_THROTTLE_L

SMC_GFX_OVERTEMP

GPU_GPIO_4

GPU_GPIO_5

GPU_GPIO_6

GPU_MLS_STRAP3

GPU_GPIO_10

GPU_GPIO_14

=PP3V3_GPU_VDD33

GPU_GPIO_11

GPU_JTAG_TDO

=PP3V3_S0_DPMUX_UC

GPU_GPIO_12

GPU_GPIO_8

SMC_GFX_THROTTLE_R_L

=PP3V3_GPU_VDD33

GPU_GPIO_7

GPU_JTAG_TCK

GPU_JTAG_TDI

GPU_GPIO_18

=PP3V3_GPU_VDD33

GPU_GPIO_13

GPU_MLS_STRAP4

GPU_SMB_DAT_R

GPU_SMB_CLK_R

GPU_MLS_STRAP0

GPU_GPIO_0

GPU_GPIO_3

GPU_GPIO_2

GPU_GPIO_1

GPU_MLS_STRAP1

GPU_JTAG_TRST_L

=PP3V3_GPU_VDD33

GPU_SMB_CLK

GPU_SMB_DAT

=PP3V3_GPU_VDD33

GPU_OSC_27M_XTALOUT

GPU_OSC_27M_XTALIN

NOSTUFF

5%

1/20W

201

2.50X2.00MM-SM

CRITICAL

27MHZ-30PPM-18PF-60OHM

R8798

1 2

R8799

1 2

R8797

1

2

R8796

1

2

R8795

1 2

R8723

1 2

C8721

1

2

R8701

1

2

R8702

1

2

R8707

1

2

R8708

1

2

R8710

1

2

R8700

1

2

R8711

1

2

U8701

1

4

7

6

5

2

9

8

3

R8722

1

2

R8721

1

2

R8724

1 2

R8725

1 2

R8720

1

2

C8700

1

2

C8701

1

2

R8706

1

2

R8726

1 2

R8792

1

2

R8793

1

2

R8794

1

2

R8790

1

2

R8713

1

2

R8712

1

2

R8704

1

2

Q8701

3

12

R8752

1

2

R8753

12

U8702

2

1

3

6

4

R8754

1 2

R8781

1 2

Q8702

3

5

4

R8755

1 2

Q8702

6

2

1

R8780

1 2

R8714

1

2

R8705

1

2

R8709

1

2

R8756

1

2

R8757

1

2

R8791

1

2

R8703

1

2

R8751

1

2

R8758

1

2

R8715

1

2

Y8700

2 4

1 3

051-9589

4.18.0

87 OF 132

78 OF 99

5

78

77

78

8

71 77 78 79

8

71 77 78 79

8

71 77 78 79

8

71 77 78 79

77

78

8

71 77 78 79

78 82

77

8

71 77 78 79

71

77

78 82

80

82

78

78 82

80

82

80

73

78 82

74 78

82

8

71 77 78 79

8

41 42

77

8

71 77 78 79

77

78

77 78

77

8

71 77 78 79

77

8

35 82

77

78

8

71 77 78 79

8

71 77 78 79

77

8

71 77 78 79

77

8

71 77 78 79

8

71 77 78 79

NC

OUT

GND

(9 OF 10)

GND

(8 OF 10)

GND_SENSE

NC

PEX_IOVDDQ

PEX_PLLVDD

NC

PEX_IOVDD

NC

PEX_IOVDDQ

NC

PEX_IOVDDQ

BUFRST*

NC

PEX_PLL_HVDD

VDD_SENSE

GND_OPT

PEX_IOVDDQ

(2 OF 10)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU SP PLLVDD

- =PP1V05_GPU_PEX_IOVDD

- =PP1V05_GPU_PEX_PLLVDD

- =PP3V3_GPU_VDD33

Power aliases required by this page:

(NONE)

Page Notes

BOM options provided by this page:

Signal aliases required by this page:

ESR = 0.05OHM

PLACE XW8800 & XW8804 CLOSE TO C8803

PEX IOVDD & PEX IOVDDQ

EDP = 2000 MA

20UF

X6T-CERM

20%

0402

2V

20UF

20%

0402

X6T-CERM

2V

20UF

20%

0402

X6T-CERM

2V

20UF

20%

0402

X6T-CERM

2V

20UF

20%

0402

X6T-CERM

2V

=PP1V05_GPU_PEX_IOVDD

=PPVCORE_GPU

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_PEX_IOVDD

P1V05_GPU_PEX_IOVDD_SNS_P

P1V05_GPU_PEX_IOVDD_SNS_N

=PP3V3_GPU_VDD33

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_PEX_IOVDD

MIN_LINE_WIDTH=0.8 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_GPU_PEX_PLL_HVDD

PP1V05_GPU_PEX_PLLVDD

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

GND_GPU_PEX_PLLVDD

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0V

GND_GPU_PEX_PLL_HVDD

GPUVCORE_SENSE_P

GPUVCORE_SENSE_N

GPU_BUFRSTN

PP1V05_GPU_SP_PLLVDD

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=0V

GND_GPU_SP_PLLVDD

KEPLER PEX PWR/GNDS

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

OMIT_TABLE

BGA

NV-GK107

OMIT_TABLE

BGA

NV-GK107

OMIT_TABLE

NV-GK107

BGA

0201

X6S-CERM

16V

20%

0.1UF

0201

0.1UF

20%

16V

X6S-CERM

0.1UF

20%

16V

X6S-CERM

0201

X6S-CERM

16V

20%

0.1UF

0201

402

MF-LF

1/16W

0

5%

1/10W

603

MF-LF

0

5%

201

100

1/20W

MF

5%

201

100

1/20W

MF

5%

97 74

PLACE_NEAR=C8803.2:2MM

SM

97 74

PLACE_NEAR=C8803.1:2MM

SM

0201

6.3V

10%

0.1UF

X6S

20%

1UF

0201

CERM-X6S

4V

20%

4V

10UF

0402-1

X6S-CERM

20%

4V

10UF

0402-1

X6S-CERM

0201

6.3V

10%

0.1UF

X6S

20%

1UF

0201

CERM-X6S

4V

20%

6.3V

4.7UF

0402

X6S

20%

4V

10UF

0402-1

X6S-CERM

20%

4V

10UF

0402-1

X6S-CERM

20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

0201

6.3V

10%

0.1UF

X6S

20%

1UF

0201

CERM-X6S

4V

20%

6.3V

4.7UF

0402

X6S

0201

NP0-CERM

25V

100PF

5%

0201

NP0-CERM

25V

100PF

5%

0201

NP0-CERM

25V

100PF

5%

0201

NP0-CERM

25V

100PF

5%

FERR-220-OHM-2A

0603

CRITICAL

20%

6.3V

4.7UF

0402

X6S

20%

1UF

0201

CERM-X6S

4V

20%

1UF

0201

CERM-X6S

4V

97 80

201

1%

1/20W

10K

MF

20%

1UF

0201

CERM-X6S

4V

0201

6.3V

10%

0.1UF

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

20%

6.3V

4.7UF

0402

X6S

U8000

C7

D2

D31

D33

E10

E22

E25

E5

E7

F28

F7

G10

G13

G16

G19

G2

G22

G25

G28

G3

G30

G32

G33

G5

G7

K2

K28

K30

K32

K33

K5

K7

M13

M15

M17

M18

M20

M22

N12

N14

N16

N19

N2

N21

N23

N28

N30

N32

N33

N5

N7

P13

P15

P17

P18

P20

P22

R12

R14

R16

R19

R21

R23

T13

T15

T17

T18

T2

T20

T22

T28

T32

T5

T7

U12

U14

U16

U19

U21

U23

V12

V14

V16

V19

V21

V23

W13

W15

W17

W18

W20

W22

W28

Y12

Y14

Y16

Y19

Y21

Y23

AH11

U8000

AG11

AB12

C28

AB14

AB16

AB19

AB2

AB21

AB23

AB28

AB30

AB32

A2

AB5

AB7

AC13

AC15

AC17

AC18

AC20

AC22

AE2

AE28

A33

AE30

AE32

AE33

AE5

AE7

AH10

AH13

AH16

AH19

AH2

AA13

AH22

AH24

AH28

AH29

AH30

AH32

AH33

AH5

AH7

AJ7

AA15

AK10

AK7

AL12

AL14

AL15

AL17

AL18

AL2

AL20

AL21

AA17

AL23

AL24

AL26

AL28

AL30

AL32

AL33

AL5

AM13

AM16

AA18

AM19

AM22

AM25

AN1

AN10

AN13

AN16

AN19

AN22

AN25

AA20

AN30

AN34

AN4

AN7

AP2

AP33

B1

B10

B22

B25

AA22

B28

B31

B34

B4

B7

C10

C13

C19

C22

C25

U8000

L2

C16

W32

L5

P8

D23

D26

H31

T8

V32

AC6

AJ28

AJ4

AJ5

AL11

C15

D19

D20

AG19

AG21

AG22

AG24

AH21

AH25

AG13

AG15

AK27

AL27

AM28

AN28

AG16

AG18

AG25

AH15

AH18

AH26

AH27

AJ27

AH12

AG26

L4

C8801

1

2

C8802

1

2

C8822

1

2

C8827

1

2

C8826

1

2

C8829

1

2

C8828

1

2

R8800

1

2

C8833

1

2

C8832

1

2

C8831

1

2

C8830

1

2

L8804

1 2

C8819

1

2

C8820

1

2

C8821

1

2

C8818

1

2

C8823

1

2

C8824

1

2

C8825

1

2

C8814

1

2

C8808

1

2

C8800

1

2

C8813

1

2

C8807

1

2

C8812

1

2

C8806

1

2

C8804

1

2

C8803

1

2

C8805

1

2

C8816

1

2

C8817

1

2

C8815

1

2

C8809

1

2

C8810

1

2

C8811

1

2

XW8801

1 2

XW8802

1 2

XW8803

1 2

XW8804

1 2

XW8800

1 2

R8810

1

2

R8811

1

2

R8803

1 2

R8802

1 2

C8834

1

2

C8835

1

2

C8836

1

2

C8837

1

2

051-9589

4.18.0

88 OF 132

79 OF 99

79 73

8

72

8

79

77

8

79 73

8

78 77 71

8

79 77

8

79 73

8

71

77

S

D

G

D

S

G

S

D

G

D

S

G

NC

IN

IMON

THRM

ISUM-

ISUM+

ISEN1

VSSP1

LGATE1A

UGATE1

BOOT1

PHASE1

ISEN2

LGATE1B

VSSP2

LGATE2

PHASE2

UGATE2

BOOT2

RTN

VSEN

FB

FB2

COMP

VW

VR_ON

DPRSLPVR

VID6

VID5

VID4

VID1

VID2

VID0

CLK_EN*

VR_TT*

PGOOD

VINVDD

NTC

RBIAS

VCCP

PSI*

VID3

PAD

NCNC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

376S1011

25A max per phase

PSI_L = HIGH & DPSLP_EN = HIGH

353S3679

DEFAULT = 0.9 V

GPU VCORE VID STRAPS

R8982 = DPSLP Control

R8982 = VID6 control (old connection)

(GND_GFXIMVP_AGND)

R8981 = PSI Control

Stuff option for GPIO control

Do not config

Line Width & DIDT

on all DIDT nets

20%

CASE-D2E-SM

68UF

POLY-TANT

CRITICAL

16V 16V

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20%

CRITICAL

TANT

270UF

CASE-B2-SM

2V 20%

CRITICAL

CASE-B2-SM

TANT

2V

270UF

20%

CRITICAL

2V

270UF

CASE-B2-SM

TANT

20%

CASE-B2-SM

TANT

2V

270UF

CRITICAL

201

NOSTUFF

1%

MF

1/20W

10K

201

NOSTUFF

1%

MF

1/20W

10K

201

NOSTUFF

1%

MF

1/20W

10K

201

NOSTUFF

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

NOSTUFF

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

NOSTUFF

MF

1/20W

10K

201

1%

NOSTUFF

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

20%

16V

CRITICAL

68UF

DIRECTFET-SA

IRF6802SDTRPBF

649135PBF

DIRECTFET_S3C

CRITICAL

IRF6802SDTRPBF

DIRECTFET-SA

649135PBF

DIRECTFET_S3C

CRITICAL

SM

PLACE_NEAR=U8900.41:1mm

201

100K

MF

1/20W

5%

201

NOSTUFF

100K

MF

1/20W

5%

88

201

0

MF

1/20W

5%

201

0

MF

1/20W

5%

NOSTUFF

78

ISL62882C

TQFN

CKPLUS_WAIVE=PdifPr_badTerm

PLACE_NEAR=Q8931.3:1mm

SM

603

0

1/10W

MF-LF

5%

10%

402

0.22UF

CERM

16V

603

0

1/10W

MF-LF

5%

10%

402

0.22UF

CERM

16V

SM

PLACE_NEAR=Q8961.3:1mm

201

1%

1.00

MF

1/20W

201

1K

1%

MF

1/20W

201

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

201

1%

MF

1/20W

10K

MF

1/20W

201

1%

1.00

1/20W

201

1%

1K

MF

1/20W

201

1%

MF

10K

201

1%

1.15K

MF

1/20W

NOSTUFF

10%

0201

6.3V

0.1UF

X6S

NOSTUFF

10%

0201

6.3V

0.1UF

X6S

10%

CERM

10V

201

5600PF

20%

0.22UF

0201

X6S-CERM

6.3V

20%

0.22UF

0201

X6S-CERM

6.3V

10%

1UF

0402

X6S-CERM

25V

PLACE_NEAR=Q8900.25:1mm

201

1

MF

1/20W

5%

10%

0201

6.3V

0.1UF

X6S

SIGNAL_MODEL=EMPTY

45

79 97

10%

0201

16V

SIGNAL_MODEL=EMPTY

X7R-CERM

1000PF

10%

0201

SIGNAL_MODEL=EMPTY

16V

X7R-CERM

1000PF

10%

0201

16V

1000PF

X7R-CERM

201

1%

49.9

NOSTUFF

MF

1/20W

10%

CERM

10V

201

NOSTUFF

5600PF

201

1%

301

SIGNAL_MODEL=EMPTY

MF

1/20W

201

1%

49.9

MF

1/20W

10%

0201

330PF

X7R-CERM

16V

0201

NOSTUFF

50V

22PF

5%

NP0-C0G-CERM

78 80

88

201

147K

1%

MF

1/20W

201

499

1%

NOSTUFF

MF

1/20W

201

NOSTUFF

0

1/20W

5%

MF

10%

1UF

0402

X6S-CERM

25V 10%

1UF

0402

X6S-CERM

25V

0612

1W

1%

0.00075

MF

1W

1%

0612

MF

0.00075

10%

10V

201

SIGNAL_MODEL=EMPTY

X7R

3300PF

201

1%

8.06K

MF

1/20W

20%

16V

CRITICAL

SM

15UF

TANT

201

100K

NOSTUFF

MF

1/20W

5%

201

100K

MF

1/20W

5%

201

5.11K

1%

1/20W

MF

201

SIGNAL_MODEL=EMPTY

MF

1/20W

10K

1%

10%

0201

50V

560PF

X7R-CERM

CRITICAL

CASE-D2E-SM

20%

16V

POLY-TANT

68UF

201

MF

1/20W

1%

30.1K

10%

0402

X6S-CERM

25V

PLACE_NEAR=Q8900.16:1mm

10%

25V

0.22UF

X7R

0402

201

MF

1/20W

1%

1.24K

10%

50V

0402

X7R-CERM

10%

0402

X7R-CERM

50V

0.001UF

0.2UH-20%-24A-0.003OHM

CRITICAL

PIMB063T-SM

0.2UH-20%-24A-0.003OHM

CRITICAL

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

GFX IMVP VCore Regulator

GFXIMVP_ISEN2

MIN_LINE_WIDTH=0.6MM

GFXIMVP_VSSP1

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GFXIMVP_ISUMP_C

GFXIMVP_ISUMN_R

=PP5V_S0_GFXIMVP

GFXIMVP_VW

GFXIMVP_ISUMN

GFXIMVP_VID<6>

GFXIMVP_ISUMN

GFXIMVP_ISUMP

GFXIMVP_NTC

GFXIMVP_RBIAS

GPUVCORE_PGOOD

GFXIMVP_VR_TT_L

GFXIMVP_FB2

GFXIMVP_COMP

GFXIMVP6_IMON

GPUVCORE_SENSE_P

GFXIMVP_ISUMP

GFXIMVP_VID<3>

GFXIMVP_VID<4>

=GPUVCORE_EN

=PP3V3_S0_GFX3V3BIAS

GFXIMVP_COMP_R

=PP3V3_S0_GFX3V3BIAS

GFXIMVP_ISNS1_N

GFXIMVP_ISUMP

GFXIMVP_DPSLP_EN

GFXIMVP_PSI_L

GFXIMVP_VID<5>

GFXIMVP_PSI_R_L

GFXIMVP_VID<0>

=PPVIN_S0_GFXIMVP

GFXIMVP_DPSLP_EN

GFXIMVP_VID<0>

GFXIMVP_VID<2>

GFXIMVP_VID<5>

GFXIMVP_VID<6>

GFXIMVP_PSI_L

GFXIMVP_VR_TT_L

GFXIMVP_FB_GND_R

GFXIMVP_ISUMN

GFXIMVP_ISNS2_N

GFXIMVP_ISNS2_NGFXIMVP_ISNS2_P

GFXIMVP_ISNS1_P GFXIMVP_ISNS1_N

GFXIMVP_PSI_L

GFXIMVP_VID<4>

GFXIMVP_VID<2>

GFXIMVP_VID<1>

GFXIMVP_FB_SNS_R

GFXIMVP_BOOT1

GFXIMVP_DPSLP_EN

GFXIMVP_VID<1>

GFXIMVP_VID<6>

GPUVCORE_SENSE_N

GFXIMVP_VID<3>

GFXIMVP_FB

GFXIMVP_ISEN1

=PPVCORE_S0_GFX_REG

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

GFXIMVP_BOOT2

MIN_LINE_WIDTH=0.6MM

GFXIMVP_LGATE1

GATE_NODE=TRUE

GFXIMVP_UGATE1

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

GFXIMVP_VSSP2

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

PP5V_S0_GFXIMVP_VDD

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

GFXIMVP_BOOT1_R

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

GND_GFXIMVP_AGND

MIN_NECK_WIDTH=0.2MM

GFXIMVP_LGATE2

GATE_NODE=TRUE

GFXIMVP_UGATE2

=PPVIN_S0_GFXIMVP

GFXIMVP_PHASE2

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.05V

PPVCORE_S0_GFX_PH2

MIN_NECK_WIDTH=0.2MM

SWITCH_NODE=TRUE

GFXIMVP_PHASE1

PPVCORE_S0_GFX_PH1

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

1UF

PLACE_NEAR=Q8900.17:1mm

MF

1/20W

5%

10

201

VOLTAGE=12.8V

PPVIN_S0_GFXIMVP_R

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP_BOOT2_R

0.001UF

20%

CASE-D2E-SM

POLY-TANT

OMIT_TABLE OMIT_TABLEOMIT_TABLEOMIT_TABLE

C8920

1

2

C8921

1

2

C8962

1

2

C8963

1

2

C8964

1

2

C8961

1

2

R8943

1

2

R8944

1

2

R8946

1

2

R8945

1

2

R8948

1

2

R8949

1

2

R8947

1

2

R8952

1

2

R8953

1

2

R8956

1

2

R8955

1

2

R8954

1

2

R8951

1

2

R8950

1

2

C8922

1

2

Q8930

7

8

2

3

Q8931

1

2

8

7

4

3

5

6

Q8930

5

6

1

4

Q8961

1

2

8

7

4

3

5

6

XW8900

12

R8971

1

2

R8972

1

2

R8981

1 2

R8982

1 2

U8900

19

30

40

7

39

8

9

18

11

10

14

15

23

24

26

5

1

21

28

2

3

13

41

20

29

25

16

31

32

33

34

35

36

37

17

38

4

12

22

27

6

XW8930

12

R8930

1

2

C8930

1

2

R8960

1

2

C8965

1

2

XW8931

12

R8964

1

2

R8963

1

2

R8961

1

2

R8962

1

2

R8931

1

2

R8934

1

2

R8933

1

2

R8932

1

2

R8911

1 2

C8912

1

2

C8911

1

2

C8910

1

2

C8966

1 2

C8931

1 2

C8902

1

2

R8901

1 2

C8913

1

2

C8914

1

2

C8915

1

2

C8919

1

2

R8917

1

2

C8941

1

2

R8915

1

2

R8916

1

2

C8917

1

2

C8918

1

2

R8940

1 2

R8970

1

2

R8983

1 2

C8923

1

2

C8924

1

2

R8999

1 2

3 4

R8998

12

34

C8940

1

2

R8913

1

2

C8925

1

2

R8974

1

2

R8973

1

2

R8914

1

2

R8912

1

2

C8916

1

2

C8926

1

2

R8918

1 2

C8901

1

2

C8900

1

2

R8910

1 2

C8928

1

2

C8927

1

2

L8930

1 2

L8960

1 2

R8900

1

2

051-9589

4.18.0

89 OF 132

80 OF 99

8

80

78 80

8

80

8

80

80 97

80

8

80

78 80

80

80 97

80 97 97

97 80 97

80

78 80

80

78 80

8

80

IN

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

IN

BI

NC

OUT

SYM_VER-2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0829

LCD Panel HPD & AUX strapping

LCD PANEL INTERFACE (eDP)

16V

X7R-CERM

0402

0.1UF

10%

0805

CRITICAL

FERR-220-OHM

10K

402

MF-LF

1/16W

5%

82

0.001UF

0402

X7R-CERM

50V

10%

16V

X7R-CERM

0402

0.1UF

10%

MFET-2X2-8IN

CRITICAL

FPF1009

16V

X7R-CERM

0402

0.1UF

10%

603

20%

10UF

6.3V

X5R

0201

X5R-CERM

16V

0.1UF

10%

X5R-CERM

0201

16V

0.1UF

10%

82 95

0.1UF

X5R-CERM

0201

16V10%

0201

X5R-CERM

16V

0.1UF

10%

82 95

X5R-CERM

0201

16V

0.1UF

10%

X5R-CERM

0201

16V

0.1UF

10%

82 95

0201

X5R-CERM

16V

0.1UF

10%

0201

X5R-CERM

16V

0.1UF

10%

82 95

X5R-CERM

0201

16V

0.1UF

10%

X5R-CERM

0201

16V

0.1UF

10%

82 95

CRITICAL

F-RT-SM

20525-130E-01

X7R

603-1

100V

1000PF

10%

7

82

0

5%

1/20W

MF

201

82

MF

1/20W

5%

1M

201

1M

5%

1/20W

MF

1/20W

5%

1M

201

1/20W

MF

5%

1M

201

1/20W

MF

5%

1/20W

5%

MF

1M

201

1M

1/20W

MF

5%

MF

201

1M

1/20W

5%

MF

1/20W

1M

201

1M

1/20W

MF

5%

1/20W

201

5%

MF

1M

7

98

7

98

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

SM

BEAD-PROBE

SIGNAL_MODEL=EMPTY

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

CRITICAL

DLP0NS

15OHM-100MA-8.5GHZ

DLP0NS

CRITICAL

DLP0NS

15OHM-100MA-8.5GHZ

DLP0NS

CRITICAL

SM

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

eDP Display Connector

NC_ISNS_LCD_PANELP

NC_ISNS_LCD_PANELN

PP5VR3V3_SW_LCD_ISNS

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

DP_INT_ML_C_N<2>

LCD_PWR_EN

=PP5V_S0_LCD

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<3> DP_INT_ML_F_P<3>

DP_INT_ML_P<3>

DP_INT_ML_F_N<3>

DP_INT_ML_N<3>

DP_INT_ML_F_P<1>

DP_INT_ML_P<1>

DP_INT_ML_F_N<1>

DP_INT_ML_N<1>

DP_INT_ML_F_P<2>

DP_INT_ML_P<2>

DP_INT_ML_F_N<2>

DP_INT_ML_N<2>

DP_INT_ML_F_P<0>

DP_INT_ML_P<0>

DP_INT_ML_F_N<0>

DP_INT_ML_N<0>

DP_INT_AUX_N

LCD_HPD_CONN

LCD_FSS

DP_INT_AUX_P

LED_RETURN_2

LED_RETURN_5

LCD_HPD

DP_INT_ML_P<0>

DP_INT_ML_C_N<0>

DP_INT_ML_C_P<0>

DP_INT_AUX_C_N

DP_INT_ML_C_P<1>

DP_INT_AUX_C_P

LED_RETURN_1

LED_RETURN_3

LED_RETURN_4

LED_RETURN_6

PPVOUT_S0_LCDBKLT

DP_INT_ML_C_N<1>

DP_INT_ML_N<0>

DP_INT_ML_P<3>

DP_INT_ML_N<3>

DP_INT_ML_N<2>

DP_INT_ML_N<1>

DP_INT_ML_P<2>

DP_INT_AUX_N

=PP3V3_S0_LCD

DP_INT_AUX_PLCD_HPD_CONN

DP_INT_ML_P<1>

MIN_NECK_WIDTH=0.25 mm

PP5VR3V3_SW_LCD

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

C9001

1

2

L9000

1 2

R9010

1

2

C9002

1

2

C9009

1

2

U9000

6

1

7

2

3

4

5

C9011

1

2

C9012

1

2

C9021

1 2

C9020

1 2

C9023

1 2

C9022

1 2

C9025

1 2

C9024

1 2

C9027

1 2

C9026

1 2

C9029

1 2

C9028

1 2

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

5

6

7

8

9

C9000

1

2

R9000

1 2

R9002

1

2

R9003

1

2

R9001

1

2

R9013

1 2

R9014

1 2

R9015

1 2

R9016

1 2

R9012

1 2

R9017

1 2

R9018

1 2

R9011

1 2

BP9000

1

BP9007

1

BP9006

1

BP9005

1

BP9003

1

BP9002

1

BP9001

1

BP9004

1

FL9000

1 2

34

FL9002

1 2

34

FL9001

1 2

34

FL9003

1 2

34

XW9020

1 2

051-9589

4.18.0

90 OF 132

81 OF 99

8

95

7

81 95

95

7

81 95

95

7

81 95

95

7

81 95

95

7

81 95

95

7

81 95

95

7

81 95

95

7

81 95

7

81 95

7

81

7

81 95

7

86

7

86

7

81 95

7

86

7

86

7

86

7

86

7

86 99

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

7

81 95

8

7

81 95

7

81

7

81 95

7

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

P45/PWMU3B/TCMCKI2/TCMMCI2

P44/TMO1/PWMU2B/TCMCYI2

P43/TMI1/TCMCKI1/TCMMCI1

P41/TMO0/TCMCKI0/TCMMCI0

P52/SCL0

P51/FRXD

P50/FTXD

P47/PWMU5B

P46/PWMU4B

P42/TCMCYI1

P40/TMI0/TCMCYI0

P37/SERIRQ

P36/LCLK

P35/LRESET*

P34/LFRAM*

P33/LAD3

P32/LAD2

P31/LAD1

P30/LAD0

P26

P27

P25

P22

P21

P23

P24

P20

P10/WUE0*

P11/WUE1*

P12/WUE2*

P13/WUE3*

P14/WUE4*

P15/WUE5*

P16/WUE6*

P17/WUE7*

P96/EXCL

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P83/LPCPD*

P82/CLKRUN*

P90/IRQ2*

P91/IRQ1*

P85/IRQ4*/RXD1

P84/IRQ3*/TXD1

P86/IRQ5*/SCK1

P97/SDA0/IRQ15*

P77/AN7

P76/AN6

P75/AN5

P74/AN4

P73/AN3

P72/AN2

P71/AN1

P80/PME*

P81/GA20

P70/AN0

P66/KIN6*

P65/KIN5*

P64/KIN4*

P63/KIN3*

P62/KIN2*

P61/KIN1*

P60/KIN0*

P67/IRQ7*/KIN7*

SYM 1 OF 3

IN

NC

IN

OUT

IN

OUT

IN

OUT

PC2/TIOCC0/TCLKA/WUE10*

PC3/TIOCD0/TCLKB/WUE11*

PC5/TIOCB1/TCLKC/WUE13*

PC7/TIOCB2/TCLKD/WUE15*

PD6/SSCK

PD7/SCS

PD5/SSI

PD4/SSO

PD3/AN11

PD2/AN10

PC4/TIOCA1/WUE12*

PC6/TIOCA2/WUE14*

PD1/AN9

PD0/AN8

PB6/CTS*/FSICK

PB7/RTS*/FSISS

PC0/TIOCA0/WUE8*

PB5/DTR*/FSIDI

PB4/DSR*/FSIDO

PB3/DCD*/PWMU1B

PC1/TIOCB0/WUE9*

PB1/LSCI

PB0/LSMI*

PA5/KIN13*/PS2BD

PA0/KIN8*/SDA1

PA1/KIN9*/SCL1

PA2/KIN10*/PS2AC

PA3/KIN11*/PS2AD

PA4/KIN12*/PS2BC

PA6/KIN14*/PS2CC

PA7/KIN15*/PS2CD

PEVREF

PECI

PH1/EXIRQ7*

PH0/IRQ6*

PG7/EXIRQ15*/SCLD

PG6/EXIRQ14*/SDAD

PG5/EXIRQ13*/SCLC

PG4/EXIRQ12*/SDAC

PF3/IRQ11*/TMOX

PF4/PWMU2A/EXDSR

PF5/PWMU3A/EXDTR

PF6/PWMU4A/EXCTS

PF7/PWMU5A/EXRTS

PG2/EXIRQ10*/SDAB

PG3/EXIRQ11*/SCLB

PF2/IRQ10*/TMOY

PE4/ETMS

PE1/ETCK

PE2/ETDI

PE3/ETDO

PE0/EXEXCL

PE5/ETRST*

PF0/IRQ8*/PWMU0A

PF1/IRQ9*/PWMU1A

PG1/EXIRQ9*/TMIY/SCLA

PG0/EXIRQ8*/TMIX/SDAA

PB2/RI*/PWMU0B

SYM 2 OF 3

IN

D

G S

IN

OUT

IN

D

S G

OUT

D

S G

IN

NC

IN

BI

OUT

IN

NC

IN

NC

A

B

OUT

DIN1_1-

DIN1_1+

VDD

GND

DIN1_0-

DIN1_3-

DOUT_0+

DOUT_1-

DAUX1-

DIN2_0+

DIN2_0-

DAUX2+

DIN2_3-

DIN2_3+

DIN2_2-

DIN2_2+

HPDIN

AUX+

DIN2_1-

DDC_AUX_SEL

DIN2_1+ DOUT_3-

DOUT_3+

DOUT_2-

DOUT_2+

DDC_DAT1

DDC_CLK1

DOUT_1+

DIN1_2+

GPU_SEL

HPD_2

DDC_CLK2

DAUX2-

DDC_DAT2

DIN1_3+

DAUX1+

DIN1_2-

HPD_1

XSD*

DIN1_0+

GND

AUX-

DOUT_0-

OUT

IN

VSS

AVSS

EXTAL

VBAT

AVREF

VCL

AVCC

VCC

RES*

XTAL

VSS

MD2

MD1

NMI

NC

MDCKN

SYM 3 OF 3

BI

NC

BI

IN

OUT

IN

BI

OUT

IN

BI

OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PD on LCD Page

CONNECT I2C TO LCD BKLT IC

CA_DET ISOLATION

PU OFFPAGE

DPMUX UC DEBUG HEADER

HDMI HPD INVERSION & ISOLATION

DPMUX UC PULL-DOWNS

DP 2:1 ANALOG MUX

DPMUX UC PULL-UPS

PU on PCH Page

81 95

1/20W

MF

201

5%

10K

NOSTUFF

81 95

10K

1/20W

5%

201

MF

82 88

81 95

82 88

10K

5%

201

1/20W

MF

10K

MF

1/20W

201

5%

201

MF

10K

1/20W

MF

201

5%

10K

MF5%

1/20W

201

10K

9

82

81 95

9

82

5%

NOSTUFF

1/20W

10K

201

MF

10K

5%

201

1/20W

MF

7

81

81 95

9

82

9

82

83

9

44

20

82 86

R4F2113NLG

OMIT_TABLE

TLP-145V

10K

MF

1/20W

201

5%

MF

1/20W

201

10K

5%

78

9

78

88

25 82

9

NOSTUFF

5% MF

201

1/20W

10K

201

1/20W

MF

10K

5%

10K

MF

201

1/20W

NOSTUFF

MF

1/20W

201

5%

10K

NOSTUFF

5%

201

1/20W

MF

10K

1/20W

MF

201

5%

10K

5%

201

1/20W

MF

10K

1/20W

5%

201

MF

10K

9

81

1909782

M-RT-SM

DPMUX_DEBUG

402

MF-LF

1/16W

5%

0

402

MF-LF

1/16W

5%

0

5% MF

201

10K

1/20W

10K

5%

1/20W

MF

201

5%

1/20W

MF

201

10K

1/20W

5% MF

10K

201

10K

MF

1/20W

201

5%

81 82

82 86

82

78

78 82

10 82

402

NOSTUFF

MF-LF

0

5%

1/16W

78 82

35

83

OMIT_TABLE

TLP-145V

R4F2113NLG

100K

201

MF

1/20W

5%

100K

1/20W

201

MF5%

NOSTUFF

MF

100K

5%

1/20W

201

77 95

DPMUX:HOCO

MF

10K

5%

1/20W

201

25V

15PF

DPMUX:XTAL

NPO

0201

5%

15PF

5%

25V

NPO

0201

DPMUX:XTAL

MF

0

5%

1/20W

201

SSM3K15FV

SOD-VESM-HF

100K

201

MF

1/20W

5%

1/20W

100K

201

MF5%

77 95

201

MF

1/20W

100K

5%

201

MF

1/20W

100K

5%

201

MF

100K

1/20W

100K

201

5%

1/20W

MF

82

78

1/20W

MF

201

100K

1%

82

77 95

35 84

1/20W

201

MF

5%

100K

77 95

SOT563

SSM6N37FEAPE

82

5%

1/20W

MF

201

100K

SOT563

SSM6N37FEAPE

35 85

77 95

7

38 42

88

35

77 95

35

44

35

77 95

74LVC1G00GF

SOT891

9

CRITICAL

TFBGA

CBTL06142EEE

73

2.50X2.00MM-SM

DPMUX:XTAL

20MHZ-30PPM-12PF-50OHM

77 95

R4F2113NLG

OMIT_TABLE

TLP-145V

81 95

77 95

10 89

81 95 10 89

10 89

20%

0.1UF

0402

X7R-CERM

10V

81 95

20%

0.1UF

0402

X7R-CERM

10V

25

25 82

7

17 41 43 92

7

17 41 43 92

7

17 41 43 92

7

17 41 43 92

7

17 41 43 92

81 95

20%

0.1UF

0402

X7R-CERM

10V 20%

0.1UF

0402

X7R-CERM

10V 20%

0.1UF

0402

X7R-CERM

10V 20%

0.1UF

0402

X7R-CERM

10V

10%

0.47UF

6.3V

X6S-CERM

0402

20%

0.1UF

0402

X7R-CERM

10V

eDP Mux

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

DPMUX_UC_NMI

DPMUX_UC_MD2

DPMUX_UC_MD1

DPMUX_UC_RESET_LDP_TBTPA_HPD_BUF

DPMUX_UC_UNUSED

DPMUX_UC_MD1

DPMUX_UC_NMI

LPC_CLK33M_DPMUX_UC

DPMUX_UC_TMS

DPMUX_UC_TRST_L

DPMUX_UC_TDO

DPMUX_UC_TDI

VOLTAGE=3.3V

PP3V3_S0_DPMUX_UC_R

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<1>

=PP3V3_S0_DPMUX

DP_INT_IG_ML_N<0>

DP_INT_IG_ML_N<3>

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<1>

DP_INT_IG_AUX_N

DP_INT_EG_ML_P<0>

DP_INT_EG_ML_N<0>

DP_INT_EG_AUX_P

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<2>

DPMUX_HPD_PD

DP_INT_AUX_C_P

DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<1>

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<2>

DP_INT_ML_C_P<1>

DP_INT_IG_ML_P<2>

LCD_MUX_SEL

DP_INT_EG_AUX_N

DP_INT_IG_ML_P<3>

DP_INT_IG_AUX_P

DP_INT_IG_ML_N<2>

LCD_MUX_EN

DP_INT_IG_ML_P<0>

DP_INT_AUX_C_N

DP_INT_ML_C_N<0>

LCD_FSS

EG_RAIL5_EN

EG_RAIL3_EN

DPMUX_UC_VCL

=PP3V3_S3_DPMUX_UC

DP_TBTSNK1_HPD_IG

DP_TBTSNK0_HPD_IG

TP_DP_EXTB_CA_DET_IG

TP_DPMUX_UC_PC2

TP_DPMUX_UC_PC3

DP_TBTSNK0_HPD_EG

DP_TBTSNK1_HPD_EG

DP_EXTA_CA_DET_EG

LCD_PWR_EN

DPMUX_UC_RESET_L

HDMI_HPD_BUF

=PP3V3_S0_DPMUX_UC

GPU_PGOOD1

GPU_PGOOD2

DPMUX_UC_UNUSED

DP_EXTB_CA_DET_EG

HDMI_EG_HPD

DP_INT_EG_HPD

TP_DPMUX_UC_P12

TP_DPMUX_UC_P15

EG_RAIL2_EN

DPMUX_UC_PEVREF

DP_TBTSNK0_HPD_EG

TP_DP_EXTA_CA_DET_IG

EG_CLKREQ_OUT_L

DPMUX_UC_TMS

DPMUX_UC_TRST_L

TP_DPA_IG_HPD

DPMUX_UC_UNUSED

DP_EXTB_MUX_SEL_EG

IG_BKLT_EN

HDMI_HPD_BUF

=I2C_DPMUX_A_SCL

=I2C_DPMUX_A_SDA

TBT_B_CONFIG1_BUF

DP_B_CA_DET_BUF

=PP3V3_S0_DPMUX_UC

DPMUX_LRESET_L

LCD_HPD

IG_LCD_PWR_EN

TP_HDMI_IG_HPD

TBT_A_CONFIG1_BUF

DP_A_CA_DET_BUF

TP_DPMUX_UC_P40

DPMUX_UC_UNUSED

DPMUX_UC_TDO

DPMUX_UC_MD1

DPMUX_UC_UNUSED

TP_DPMUX_UC_P66

DPMUX_UC_UNUSED

EG_RESET_L

TP_DPMUX_UC_P16

TP_DPMUX_UC_P17

LCD_BKLT_EN

EG_RAIL3_EN

DPMUX_UC_MD1

DPMUX_UC_RX

DP_EXTA_MUX_SEL_EG

DP_EXTB_MUX_EN

TP_DPMUX_UC_P62

TP_DPMUX_UC_P63

TP_DPMUX_UC_P11

DP_EXTA_MUX_EN

PP3V3_S0_DPMUX_UC_R

TP_DPMUX_UC_P14

TP_DPMUX_UC_P10

EG_CLKREQ_OUT_L

TP_DPMUX_UC_P45

EG_RAIL1_EN

DPMUX_UC_TX

DPMUX_UC_RESET_L

TP_DPMUX_UC_P80

DPMUX_UC_UNUSED

EG_RAIL4_EN

LPC_AD<1>

LPC_AD<3>

TP_DPMUX_UC_P13

DP_INT_IG_HPD

TP_DPB_IG_HPD

DP_DDC_MUX_CROSSBAR_L

DPMUX_UC_CLK32K

DPMUX_UC_TCK

DPMUX_UC_MD2

DP_INT_EG_HPD

DP_INT_IG_HPD

DP_TBTSNK1_HPD_EG

DPB_IG_HPD

LPC_AD<0>

EG_RAIL5_EN

=PP3V3_S0_DPMUX_UC

TP_DPB_EG_HPD

DPMUX_UC_UNUSED

EG_LCD_PWR_EN

EG_BKLT_EN

PM_ALL_GPU_PGOOD

EG_CLKREQ_IN_L

GPU_PGOOD4

DPMUX_UC_UNUSED

DPMUX_UC_IRQ

DPMUX_UC_UNUSED

FB_CLAMP_TOGGLE_REQ_L

TP_DPA_EG_HPD

=I2C_DPMUX_UC_SDA

TP_DPMUX_UC_P67

DPMUX_UC_PEVREF

DPMUX_UC_PECI

DPMUX_UC_CLK32K

DPMUX_UC_BOOT_TX

LPC_AD<2>

DPMUX_UC_UNUSED

DP_TBTPB_HPD_BUF

DPMUX_UC_UNUSED

=PP3V3_S0_DPMUX_UC

HDMI_HPD_L

TP_DPMUX_UC_P81

TP_DPMUX_UC_P82

TP_DPMUX_UC_P83

DPMUX_UC_BOOT_RX

TP_LCD_IRQ

TP_DPMUX_UC_P52

DPMUX_UC_RX

DPMUX_UC_TX

TP_DPMUX_UC_P47

TP_DPMUX_UC_P46

LCD_MUX_SEL

TP_DPMUX_UC_P41

LPC_FRAME_L

TP_DPMUX_UC_P37

FB_CLAMP

DPMUX_LRESET_L

TP_DPMUX_UC_P42

EG_RAIL4_EN

DPMUX_UC_UNUSED

GPU_PGOOD3

LCD_MUX_EN

TP_LCD_MUX_REQ

LCD_BKLT_PWM

DPMUX_UC_UNUSED

=I2C_DPMUX_UC_SCL

PP3V3_S3_DPMUX_UC_R

MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3MM

TBT_DDC_XBAR_EN_L

DP_A_CA_DET_BUF

DP_TBTSNK0_HPD

DP_TBTSNK1_HPD

DPMUX_UC_TCK

DPMUX_LRESET_L

DPMUX_UC_TDI

=PP3V3_S0_DPMUX_UC

DPMUX_UC_MD2

DPA_IG_HPD

EG_RESET_L

DPMUX_UC_PECI

DPMUX_UC_MD2

DPMUX_UC_MD1

DPMUX_UC_NMI

LCD_BKLT_PWM

LCD_BKLT_EN

LCD_PWR_EN

EG_RAIL2_EN

EG_RAIL1_EN

DPMUX_UC_RESET_L

DPMUX_UC_XTAL

TP_DPMUX_UC_P96

DP_B_CA_DET_BUF

DPMUX_UC_EXTAL

DPMUX_UC_XTAL_R

U9100

B12

A13

A12

B13

D11

C13

C12

D10

D13

E11

D12

F11

E13

E12

F13

E10

A9

D9

C8

B7

A8

D8

D7

D6

D4

A5

B4

A1

C2

B2

C1

C3

G2

F3

E4

L13

K12

K11

J12

K13

J10

J11

H12

N10

M11

L10

N11

N12

M13

N13

L12

A7

B6

C7

D5

A6

B5

C6

J4

G3

H2

G1

H4

G4

F4

F1

U9100

N3

N1

M3

M2

N2

L1

K3

L2

B8

C9

B9

A10

C10

B10

C11

A11

G11

G13

F12

H13

G10

G12

H11

J13

M10

N9

K10

L8

M9

N8

K9

L7

K1

J3

K2

J1

K4

H3

A4

B3

K5

N5

M6

L5

M5

N4

L4

M4

M8

N7

K8

K7

K6

N6

M7

L6

E2

F2

U9100

M12

L11

L9

A2

D1

H1

C4

E3

D3

J2

B1

M1

H10

E1

D2

L3

F10

C5

B11

A3

C9150

1

2

C9151

1

2

C9100

1

2

C9101

1

2

C9102

1

2

C9103

1

2

C9105

1

2

C9104

1

2

R9120

1 2

R9110

1 2

R9121

1 2

R9122

1 2

R9123

1 2

R9124

1 2

R9125

1 2

R9126

1 2

R9127

1 2

R9128

1 2

R9111

1 2

R9129

1 2

R9112

1 2

R9113

1 2

R9131

1 2

R9130

1 2

R9132

1 2

R9133

1 2

R9114

1 2

J9100

7

8

1

2

3

4

5

6

R9100

1 2

R9101

1 2

R9115

1 2

R9116

1 2

R9117

1 2

R9118

1 2

R9134

1 2

R9102

1 2

R9135

1 2

R9119

1 2

R9140

1 2

R9150

1

2

C9141

1

2

C9140

1

2

R9151

1 2

Q9190

3

12

R9136

1 2

R9137

1 2

R9138

1 2

R9139

1 2

R9145

1 2

R9146

1 2

R9162

1 2

R9160

1 2

Q9110

3

5

4

R9161

1 2

Q9110

6

2

1

U9110

2

1

3

6

4

U9150

H1

H2

J9

H9

J6

H6

C2

H8

H5

J8

J5

A4

B4

A5

B5

A6

B6

A9

A8

B9

B8

D9

D8

E9

E8

F9

F8

B1

B2

D1

D2

E1

E2

F1

F2

B3

C8

G8

H4

H7

G2

A1

J2

H3

J1

A2

J4

B7

Y9100

2 4

1 3

051-9589

4.18.0

91 OF 132

82 OF 99

5

E5

82

8

83

82

82 88

8

82

8

35 78 82

82

78 82

9

82

8

35 78 82

82

9

82

9

82

82 88

82

78 82

10 82

78 82

9

18

8

35 78 82

82

78

82

8

35 78 82

82

25 82

82

8

35 78 82

82

9

18

9

82

82 86

81 82

82 88

82

VCC

OUTA1+

OUTA1-

OUTA0+

OUTA0-

SAO

OUTB1+

OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

ENB

SAI

INB-

INB+

SBI

GND

THRM

PAD

BI

IN

VCC

OUTA1+

OUTA1-

OUTA0+

OUTA0-

SAO

OUTB1+

OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

ENB

SAI

INB-

INB+

SBI

GND

THRM

PAD

BI

IN

BI

IN

BI

IN

BI

IN

OUT

BI

OUT

IN

BI

IN

BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

0 0 1 OUTB1 OUTA0

0 0 0 OUTB0 OUTA0

MUX TRUTH TABLE

SAI/SBI SAO SBO | INA INB

DP A & DP B AUX MUX DP A & DP B DDC MUX

0 1 0 OUTB0 OUTA1

1 1 1 OUTA1 OUTB1

1 1 0 OUTA1 OUTB0

1 0 1 OUTA0 OUTB1

1 0 0 OUTA0 OUTB0

0 1 1 OUTB1 OUTA1

QFN

TS3DS10224

7

35 95

82 83

TS3DS10224

QFN

7

35 95

82 83

18

77

18

77

18

82 83

82

402

10K

MF-LF

1/16W

5%

201

470K

1%

1/20W

MF

201

MF

470K

1%

1/20W1/20W

470K

1%

MF

201

470K

1%

1/20W

MF

201

84

85

201

1/20W

1%

MF

470K

201

1/20W

MF

1%

470K

201

MF

1/20W

1%

470K

1/20W

201

MF

1%

470K

82 83

77 95

18 95

77 95

82 83

20%

0.1UF

0402

X7R-CERM

10V

18 95

7

35 95

7

35 95

82 83

20%

0.1UF

0402

X7R-CERM

10V

SYNC_MASTER=D2_SEAN

SYNC_DATE=03/05/2012

eDP Muxed Graphics Support

=PP3V3_S0_DPMUX

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

DP_EXTB_MUX_EN

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_EXTA_MUX_EN

DP_EXTB_MUX_SEL_EG

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK1_EG_AUXCH_P

DP_EXTA_MUX_SEL_EG

DPA_IG_AUX_CH_N

DPA_IG_AUX_CH_P

DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK0_EG_AUXCH_P

DPB_EG_DDC_CLK

DP_EXTB_MUX_SEL_EG

DPB_EG_DDC_DATA

DP_EXTA_MUX_SEL_EG

DP_DDC_MUX_CROSSBAR_L

DP_EXTB_MUX_EN

DP_TBTPB_DDC_DATA

DPA_EG_DDC_CLK

DP_EXTA_MUX_EN

DPA_IG_DDC_DATA

DPB_IG_DDC_CLK

DPA_EG_DDC_DATA

DPB_IG_DDC_DATA

DPA_IG_DDC_CLK

DP_TBTPA_DDC_CLK

DP_TBTPA_DDC_DATA

DP_TBTPB_DDC_CLK

U9200

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

14 15

12 11

21

13

C9200

1

2

C9210

1

2

U9210

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

14 15

12 11

21

13

R9210

1

2

R9240

1

2

R9250

1

2

R9220

1

2

R9230

1

2

R9253

1

2

R9254

1

2

R9252

1

2

R9251

1

2

051-9589

4.18.0

92 OF 132

83 OF 99

8

82

IN

OUT

IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

DPMLO+

DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIO-

AUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX

LSRX

HPDOUT

HPD

OUT

BI

IN

OUT

IN

BI

IN

Y A

B

C

VCC

GND

OUT

AUX_CHN

AUX_CHP

DP_PWR

GND4

ML_LANE3N

ML_LANE3P

GND2

CONFIG2

CONFIG1

HPD

RETURN

ML_LANE2N

ML_LANE2P

GND3

ML_LANE1N

ML_LANE0P

GND0

ML_LANE0N

GND1

ML_LANE1P

PORT B

SHIELD PINS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TBT Dir

TBT: TX_0

For J9400 TBT SMT pads

(3, 5, 17 & 19):

<RV3P3>

TBT: LSX_R2P/P2R (P/N)

(0-18.9V)

(Both C’s)

18.9V Max

V3P3 must be S4 to support

wake from Thunderbolt devices.

514-0803

(Both C’s)

470k R’s for ESD protection

on AC-coupled signals.

(Both D’s)

TBT: LSX_A_R2P/P2R (P/N)

DP Dir

TBT: RX_1 Bias Sink

Low: 0 - 0.8V

High: 2.0 - 5.0V

Sink HPD range:

greater than or equal

down HPD input with

(0-18.9V)

Nominal Min Max

12V: See

below

For 12V systems:

ILIM = 40000 / RISET

Single R on ISET_V3P3 OK.

ISET_Sx with CD3210.

requires two R’s per HV

Single-fault protection

DP Source must pull

to 100K (DPv1.1a).

TBT: TX_1

TBT: Unused

(Both C’s)

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Nominal Min Max

Y = B

3.3V/HV Power MUX

DP Dir

IV3P3 1100mA 1030mA 1200mA

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

TBT Dir

Thunderbolt Connector A

10%

0.01UF

0402

X7R-CERM

50V

7

35 93

7

35 93

10%

0.01UF

16V

X5R-CERM

0201

MF

201

12

1/20W

5%

10%

0.01UF

0402

X7R-CERM

50V

201

SIGNAL_MODEL=EMPTY

1/20W

MF

GND_VOID=TRUE

1K

5%

201

GND_VOID=TRUE

1/20W

MF

SIGNAL_MODEL=EMPTY

1K

5%

50V

C0G-NP0

0402

30PF

5%

50V

C0G-NP0

0402

30PF

5%

201

1/20W

MF

100K

5%

GND_VOID=TRUE

650NH-5%-0.430MA-0.52OHM

CRITICAL

SIGNAL_MODEL=EMPTY

0603

GND_VOID=TRUE

CRITICAL

0603

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.52OHM

6.3V

CERM-X5R

0402

10UF

20%10%

16V

0.1UF

0201

X5R-CERM

10%

16V

X5R-CERM

0.1UF

0201

X5R-CERM-1

603

6.3V

20%

22UF

CRITICAL

CASE-B2-SM

POLY-TANT

100UF

6.3V

20%

201

1/20W

MF

1M

5%

201

1/20W

MF

1M

5%

10%

330PF

0201

X7R-CERM

16V 10%

330PF

0201

X7R-CERM

16V

201

GND_VOID=TRUE

1/20W

MF

2.2K

5%

201

2.2K

1/20W

MF

GND_VOID=TRUE

5%

CRITICAL

FERR-120-OHM-3A

0603

35

10%

25V

0.1UF

X5R

402

BAR90-02LRH

TSLP-2-7

CRITICAL

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

CRITICAL

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

201

1/20W

MF

470K

GND_VOID=TRUE

5%

201

MF

1/20W

470K

GND_VOID=TRUE

5%

0.22UF

X5R

GND_VOID=TRUE

6.3V

0201

20%

6.3V

0201

GND_VOID=TRUE

X5R

0.22UF

20%

7

35 93

7

35 93

0.22UF

GND_VOID=TRUE

6.3V

X5R

0201

20%

GND_VOID=TRUE

6.3V

X5R

0201

20%

0.22UF

201

GND_VOID=TRUE

MF

1/20W

470K

5%

201

1/20W

MF

470K

GND_VOID=TRUE

5%

CRITICAL

QFN

CD3210A0RGP

35 37

70

70 85

201

1/20W

MF

36.5K

1%

10%

0.1UF

25V

X5R

402

SIGNAL_MODEL=TBT_MUX

HVQFN

CBTL05023

CRITICAL

201

1/20W

MF

100K

5%

201

1/20W

MF

100K

5%

10%

16V

X5R-CERM

0.1UF

0201

10%

16V

0.1UF

0201

X5R-CERM

35

83

25 85

35

201

1/20W

MF

1M

5%

201

10K

MF

1/20W

5%

10%

16V

0201

X5R-CERM

0.1UF

35 82

7

35 93

7

35 93

7

35 93

7

35 93

X5R

6.3V

20%

0.22UF

0201

6.3V

20%

X5R

0201

0.22UF

35 93

10% 16V

0201

X5R-CERM

0.1UF

10% 16V

X5R-CERM

0201

0.1UF

35 93

0.22UF

20%

X5R

6.3V

0201

0.22UF

6.3V

0201

20%

X5R

35 93

201

MF

470K

1/20W

5%

201

470K

MF

1/20W

5%

201

TBTHV:P15V

MF

1/20W

1%

22.6K

201

TBTHV:P15V

1/20W

1%

22.6K

MF

201

MF

1/20W

1%

22.6K

TBTHV:P15V

201

1/20W

1%

22.6K

MF

TBTHV:P15V

201

GND_VOID=TRUE

4V

CERM-X5R-1

20%

0.47UF

201

4V

CERM-X5R-1

20%

0.47UF

201

0.47UF

GND_VOID=TRUE

4V

CERM-X5R-1

20%

201

CERM-X5R-1

20%

0.47UF

4V

10%

X5R-CERM

4.7UF

0603

25V

10%

0.01UF

25V

X5R-CERM

0201

GND_VOID=TRUE

10%

0.01UF

0201

25V

X5R-CERM

GND_VOID=TRUE

74AUP1T97

CRITICAL

SOT891

10%

16V

0.1UF

X5R-CERM

0201

35

MDP-D2

F-RT-TH

2

TBTHV:P12V

R9411,R9414

118S0145

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

2

TBTHV:P12V

R9410,R9413

118S0145

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Thunderbolt Connector A

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_TBTAPWR

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=18.9V

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=3.3V

TBT_A_BIAS

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=3.3V

PP3V3_SW_TBTAPWR

MIN_NECK_WIDTH=0.20 MM

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18V

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

PPHV_SW_TBTAPWR

TBT_A_D2R_C_N<0>

TBTAPWRSW_ISET_V3P3

=PPHV_SW_TBTAPWRSW

DP_TBTPA_ML_P<3>

=PP3V3_S4_TBTAPWRSW

TBT_A_LSRX_UNBUFPP3V3_SW_TBTAPWR

DP_TBTPA_ML_N<1>

DP_TBTPA_ML_P<1>

TBT_A_LSRX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_AUXCH_C_N

TBT_A_HV_EN

=TBT_S0_EN

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3>

TBT_A_D2R_C_N<1>

TBT_A_D2R_C_P<1>

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

TBT_A_D2R_N<0>

TBT_A_BIAS

TBT_A_D2R_P<0>

TBT_A_R2D_C_N<0>

TBTAPWRSW_ISET_S0_R

TBTAPWRSW_ISET_S0

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

=TBTAPWRSW_EN

DP_A_AUXCH_DDC_N

DP_A_AUXCH_DDC_P

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT_A_CONFIG1_RC

TBT_A_HPD

DP_TBTPA_ML_C_P<1>

PP3V3_SW_TBTAPWR

DP_TBTPA_DDC_CLK

TBT_A_CIO_SEL

DP_TBTPA_AUXCH_N

DP_TBTPA_DDC_DATA

DP_TBTPA_HPD

TBT_A_CONFIG1_BUF

TBTAPWRSW_ISET_S3

DP_TBTPA_ML_C_N<1>

DP_TBTPA_AUXCH_P

DP_AUXIO_EN

TBT_A_DP_PWRDN

TBT_A_LSTX

TBT_A_R2D_C_P<0>

DP_A_LSX_ML_P<1>

TBT_A_R2D_N<0>

TBT_A_R2D_P<0>

DP_A_LSX_ML_N<1>

TBT_A_R2D_P<1>

TBT_A_R2D_N<1>

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R1_AUXDDC_N

DP_TBTPA_ML_N<3>

TBT_A_HPD

DP_A_AUXCH_DDC_P

TBT_A_CONFIG1_RC

DP_A_AUXCH_DDC_N

TBT_A_CONFIG2_RC

TBT_A_D2R_C_P<0>

TBTAPWRSW_ISET_S3_R

L9400

1 2

C9400

1

2

C9402

1

2

R9401

1 2

C9401

1

2

R9494

1

2

R9495

1

2

C9498

1

2

C9499

1

2

R9441

1

2

L9498

12

L9499

12

C9486

1

2

C9485

1

2

C9481

1

2

C9480

1

2

C9487

1

2

R9452

1

2

R9451

1

2

C9494

1

2

C9495

1

2

R9498

1

2

R9499

1

2

C9410

1

2

D9499

A K

D9498

A K

R9470

1

2

R9471

1

2

C9471

1 2

C9470

1 2

C9472

1 2

C9473

1 2

R9473

1

2

R9472

1

2

U9410

5

1

2

3

4

13

11 10

9

8

12

14

1516

17

21

19

20

18

6

7

R9412

1

2

C9411

1

2

U9420

7

8

2

23

22

1

24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3

15

R9429

1

2

R9428

1

2

C9420

1

2

C9421

1

2

R9426

1

2

R9427

1

2

C9425

1

2

C9432

1 2

C9433

1 2

C9430

1 2

C9431

1 2

C9478

1 2

C9479

1 2

R9479

1 2

R9478

1 2

R9411

1

2

R9410

1

2

R9414

1

2

R9413

1

2

C9474

1 2

C9475

1 2

C9476

1 2

C9477

1 2

C9415

1

2

C9405

1

2

C9406

1

2

U9460

2

3

1

6

5

4

C9460

1

2

J9400

B18

B16

B4

B6

B20

B1

B7B8

B13B14

B2

B5

B3

B11

B9

B17

B15

B12

B10

B19

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

051-9589

4.18.0

94 OF 132

84 OF 99

84

7

93

8

93

8

84

93

84

84 93

84

93

84 93

7

93

7

93

84 93

7

93

7

93 93

93

84

84 93

84

84 93

7

93

IN

OUT

IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

DPMLO+

DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIO-

AUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX

LSRX

HPDOUT

HPD

OUT

BI

IN

OUT

IN

BI

IN

OUT

Y A

B

C

VCC

GND

ML_LANE1N

ML_LANE2P

ML_LANE0N

GND1

ML_LANE0P

DP_PWR

GND0

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND2

CONFIG2

HPD

GND4 GND3

ML_LANE1P

ML_LANE2N

PORT A

SHIELD PINS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Nominal Min Max

DP Dir

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

Nominal Min Max

For J9600 TBT SMT pads

TBT Dir

<RHVS0>

ILIM = 40000 / RISET

<RHVS3>

Single-fault protection

requires two R’s per HV

ISET_Sx with CD3210.

Single R on ISET_V3P3 OK.

IV3P3 1100mA 1030mA 1200mA

below

(0-18.9V)

TBT: TX_0

TBT Dir

(0-18.9V)

wake from Thunderbolt devices.

514-0803

TBT: RX_1 Bias Sink

TBT: LSX_A_R2P/P2R (P/N)

Low: 0 - 0.8V

High: 2.0 - 5.0V

(Both C’s)

18V Max

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

on AC-coupled signals.

to 100K (DPv1.1a).

Sink HPD range:

greater than or equal

down HPD input with

DP Source must pull

12V: See

<RV3P3>

DP Dir

TBT: Unused

(Both D’s)

(3, 5, 17 & 19):

3.3V/HV Power MUX

V3P3 must be S4 to support

For 12V systems:

Thunderbolt Connector B

Y = B

470k R’s for ESD protection

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

X7R-CERM

0402

0.01UF

10%

50V

7

35 93

7

35 93

X5R-CERM

0201

16V

0.01UF

10%

12

1/20W

MF

201

5%

X7R-CERM

0402

0.01UF

10%

50V

GND_VOID=TRUE

1K

MF

1/20W

SIGNAL_MODEL=EMPTY

201

5%

SIGNAL_MODEL=EMPTY

1K

GND_VOID=TRUE

MF

1/20W

201

5%

50V

C0G-NP0

0402

30PF

5%

50V

C0G-NP0

0402

30PF

5%

100K

MF

1/20W

201

5%

SIGNAL_MODEL=EMPTY

0603

650NH-5%-0.430MA-0.52OHM

CRITICAL

GND_VOID=TRUE

650NH-5%-0.430MA-0.52OHM

CRITICAL

0603

SIGNAL_MODEL=EMPTY

0402

10UF

CERM-X5R

6.3V

20%

X5R-CERM

0.1UF

0201

16V

10%

0.1UF

0201

X5R-CERM

16V

10%

22UF

603

6.3V

20%

X5R-CERM-1

CRITICAL

POLY-TANT

100UF

CASE-B2-SM

6.3V

20%

1M

MF

1/20W

201

5%

1M

MF

1/20W

201

5%

16V

X7R-CERM

0201

330PF

10% 16V

X7R-CERM

0201

330PF

10%

GND_VOID=TRUE

2.2K

MF

1/20W

201

5%

2.2K

GND_VOID=TRUE

MF

1/20W

201

5%

0603

FERR-120-OHM-3A

CRITICAL

35

25V

X5R

0.1UF

10%

402

BAR90-02LRH

TSLP-2-7

CRITICAL

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

SIGNAL_MODEL=TBTPIN

CRITICAL

GND_VOID=TRUE

470K

GND_VOID=TRUE

MF

1/20W

201

5%

GND_VOID=TRUE

MF

1/20W

470K

201

5%

GND_VOID=TRUE

6.3V

X5R

0201

0.22UF

20%

GND_VOID=TRUE

6.3V

X5R

0201

0.22UF

20%

7

35 93

7

35 93

GND_VOID=TRUE

6.3V

X5R

0201

0.22UF

20%

GND_VOID=TRUE

6.3V

X5R

0201

0.22UF

20%

GND_VOID=TRUE

MF

1/20W

470K

201

5%

MF

1/20W

470K

GND_VOID=TRUE

201

5%

QFN

CRITICAL

CD3210A0RGP

35 37

70

70 84

1/20W

MF

36.5K

1%

201

25V

0.1UF

X5R

10%

402

CBTL05023

CRITICAL

HVQFN

SIGNAL_MODEL=TBT_MUX

1/20W

MF

100K

201

5%

1/20W

MF

100K

201

5%

0.1UF

0201

X5R-CERM

16V

10%

0201

0.1UF

X5R-CERM

16V

10%

35

83

25 84

35

1/20W

MF

1M

201

5%

1/20W

MF

10K

201

5%

0.1UF

0201

X5R-CERM

16V

10%

35 82

7

35 93

7

35 93

7

35 93

7

35 93

6.3V

X5R

0201

0.22UF

20%

6.3V

X5R

0201

0.22UF

20%

35 93

0.1UF

0201

X5R-CERM

16V10%

0.1UF

0201

X5R-CERM

16V10%

35 93

X5R

0.22UF

20%

6.3V

0201

6.3V

X5R

0.22UF

20%

0201

35 93

MF

1/20W

470K

201

5%

MF

1/20W

470K

201

5%

TBTHV:P15V

1/20W

1%

22.6K

MF

201

MF

1/20W

1%

22.6K

TBTHV:P15V

201

TBTHV:P15V

22.6K

1%

1/20W

MF

201

1/20W

1%

22.6K

MF

TBTHV:P15V

201

0.47UF

20%

CERM-X5R-1

4V

201

CERM-X5R-1

0.47UF

20%

4V

GND_VOID=TRUE

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

CERM-X5R-1

4V

GND_VOID=TRUE

201

4.7UF

X5R-CERM

25V

0603

10%

GND_VOID=TRUE

0201

25V

X5R-CERM

0.01UF

10%

GND_VOID=TRUE

0201

25V

X5R-CERM

0.01UF

10%

35

0201

0.1UF

X5R-CERM

16V

10%

SOT891

74AUP1T97

CRITICAL

MDP-D2

F-RT-TH

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

118S0145

R9610,R9613

2

TBTHV:P12V

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

118S0145

R9611,R9614

2

TBTHV:P12V

Thunderbolt Connector B

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

PP3V3_SW_TBTBPWR

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=3.3V

TBT_B_BIAS

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18V

MIN_NECK_WIDTH=0.20 MM

TBTBCONN_20_RC

PPHV_SW_TBTBPWR

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=18.9V

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_SW_TBTBPWR

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM

TBTBCONN_7_C

DP_B_LSX_ML_N<1>

TBT_B_R2D_P<1>

TBT_B_R2D_N<0>

TBT_B_R2D_P<0>

TBT_B_D2R1_AUXDDC_P

DP_TBTPB_ML_P<3>

DP_TBTPB_ML_N<3>

TBT_B_D2R_C_P<0>

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R_C_N<0>

TBT_B_HPD

DP_B_LSX_ML_P<1>

TBT_B_R2D_N<1>

TBT_B_LSRX

PP3V3_SW_TBTBPWR TBT_B_LSRX_UNBUF

DP_TBTPB_AUXCH_C_N

=PP3V3_S4_TBTBPWRSW

TBT_B_HV_EN

TBT_B_BIAS

DP_B_LSX_ML_P<1>

DP_B_LSX_ML_N<1>

TBT_B_CONFIG1_RC

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_N<1>

TBT_B_CONFIG1_BUF

TBT_B_R2D_C_N<0>

DP_TBTPB_AUXCH_C_P

TBT_B_R2D_C_P<0>

TBT_B_HPD

DP_B_AUXCH_DDC_N

DP_B_AUXCH_DDC_P

PP3V3_SW_TBTBPWR

DP_TBTPB_ML_P<1>

=TBTBPWRSW_EN

DP_TBTPB_ML_C_N<3>

DP_B_AUXCH_DDC_N

DP_TBTPB_HPD

TBT_B_CIO_SEL

DP_AUXIO_EN

DP_TBTPB_AUXCH_N

DP_TBTPB_AUXCH_P

DP_TBTPB_DDC_DATA

DP_TBTPB_DDC_CLK

DP_B_AUXCH_DDC_P

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_RC

TBTBPWRSW_ISET_S0_R

TBTBPWRSW_ISET_S3_R

TBTBPWRSW_ISET_S0

TBT_B_LSTX

TBT_B_D2R_N<0>

TBT_B_D2R_P<0>

TBT_B_D2R_C_N<1>

TBT_B_D2R_N<1>

TBT_B_D2R_C_P<1>

TBT_B_D2R_P<1>

DP_TBTPB_ML_C_P<3>

=TBT_S0_EN

TBT_B_DP_PWRDN

TBTBPWRSW_ISET_S3

TBTBPWRSW_ISET_V3P3

=PPHV_SW_TBTBPWRSW

L9600

1 2

C9600

1

2

C9602

1

2

R9601

1 2

C9601

1

2

R9694

1

2

R9695

1

2

C9698

1

2

C9699

1

2

R9641

1

2

L9698

12

L9699

12

C9686

1

2

C9685

1

2

C9681

1

2

C9680

1

2

C9687

1

2

R9652

1

2

R9651

1

2

C9694

1

2

C9695

1

2

R9698

1

2

R9699

1

2

C9610

1

2

D9699

A K

D9698

A K

R9670

1

2

R9671

1

2

C9671

1 2

C9670

1 2

C9672

1 2

C9673

1 2

R9673

1

2

R9672

1

2

U9610

5

1

2

3

4

13

11 10

9

8

12

14

1516

17

21

19

20

18

6

7

R9612

1

2

C9611

1

2

U9620

7

8

2

23

22

1

24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3

15

R9629

1

2

R9628

1

2

C9620

1

2

C9621

1

2

R9626

1

2

R9627

1

2

C9625

1

2

C9632

1 2

C9633

1 2

C9630

1 2

C9631

1 2

C9678

1 2

C9679

1 2

R9679

1 2

R9678

1 2

R9613

1

2

R9614

1

2

R9611

1

2

R9610

1

2

C9675

1 2

C9674

1 2

C9677

1 2

C9676

1 2

C9615

1

2

C9605

1

2

C9606

1

2

C9660

1

2

U9660

2

3

1

6

5

4

J9400

A18

A16

A4

A6

A20

A1

A7A8

A13A14

A2

A5

A3

A11

A9

A17

A15

A12

A10

A19

S1

S10

S11

S2

S3

S4

S5

S6

S7

S8

S9

051-9589

4.18.0

96 OF 132

85 OF 99

85

85 93

7

93

7

93

7

93

7

93

7

93

85

85 93

7

93

85

8

85

85 93

85

93

85

85 93

85

93

85 93

93

85 93

85

8

IN

OUT1

FSET

GD

FILTER

ISET

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VIN

VDDIO VLDO

FB

SW

OUT2

OUT4

OUT5

VSYNC

OUT3SCLK

SDA

GND_S

PAD

OUT

IN

D

SG

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PLACE XW9710 AWAY FROM U9701.1 AND U9701.15

*L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.

PPBUS_SW_LCDBKLT_PWR

C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE

I_LED=23.96MA

I_LED=369/Riset

details in spec

(EEPROM should set EN_I_RES=1)

R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS

AND PPBUS_SW_BKL

NEED VALUE CHANGES FOR 55V AND 96 LEDS !!!

C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719

152S1527

(APN: 353S3376)

PWM RES = 9+3

ON THE SENSOR PAGE

FDC638APZ

THERE IS A SENSE RESISTOR BETWEEN

0.715 A (EDP)

CHANNEL

MOSFET

P-TYPE

43 mOhm @4.5V

PPBUS S0 LCDBkLT FET

LOADING

RDS(ON)

FPWM=19.2KHZ

ADD VIAS IN TPAD OF U9701

LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

MIN_LINE_WIDTH=0.5 MM

PPVOUT_S0_LCDBKLT

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=55V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

BKL_FET_CNTL

BKL_ISEN2

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN1

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISET

BKLT_EN

BKL_FB

TP_BKL_FAULT

LCD_BKLT_PWM

=I2C_BKL_1_SCL

LCDBKLT_EN_DIV

BKL_VSYNC_R

=I2C_BKL_1_SDA

BKLT_PLT_RST_L

=PPBUS_S0_LCDBKLT

LCD_BKLT_EN

LCDBKLT_DISABLE

LCDBKLT_EN_L

=PP5V_S0_BKL

=PP3V3_S0_BKL_VDDIO

PPBUS_S0_LCDBKLT_PWR

BKL_FLT

BKL_FSET

BKL_SCL

BKL_SDA

LVDS_BKL_PWM_RC

BKL_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

VOLTAGE=50V

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.6 MM

MIN_LINE_WIDTH=0.5 mm

BKL_SW

MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

BKL_ISEN4

MIN_LINE_WIDTH=0.4 mm

PPBUS_SW_LCDBKLT_PWR

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

PPBUS_S0_LCDBKLT_FUSED

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_PWR

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

D_BKL:PROD

116S0004

6

R9717,R9718,R9719,R9720,R9721,R9722

RES, 0OHM, 0402

SYNC_MASTER=D2_KEPLER

LCD Backlight Driver (LP8545)

SYNC_DATE=01/13/2012

402

5%

0

MF-LF

1/16W

DFLS2100

POWERDI-123

CRITICAL

PLACE_NEAR=L9710.2:3MM

SI7812DN

CRITICAL

PWRPK-1212-8

402

MF-LF

1/16W

1%

15.4K

DEM8030C-SM

CRITICAL

22UH-20%-2.4A-0.105OHM

5%

33PF

0402

C0G-CERM

50V

NO STUFF

SSOT6-HF

CRITICAL

FDC638APZ_SBMS001

10%

0.1UF

16V

0402

X7R-CERM

402

1/16W

301K

1%

MF-LF

3AMP-32V-467

603-HF

BOTTOM

SOT563

SSM6N15FEAPE

SOT563

SSM6N15FEAPE

402

147K

1/16W

1%

MF-LF

82

25

402

10K

5%

1/16W

MF-LF

402

1/16W

MF-LF

1%

59.0K

402

1/16W

MF-LF

63.4K

1%

10%

1000PF

0603

X7R-CERM

100V

PLACE_NEAR=R9708.1:5MM

10%

100V

CRITICAL

2.2UF

PLACE_NEAR=D9701.2:5MM

1210

X7R-CERM

10%

100V

1210

X7R-CERM

2.2UF

CRITICAL

PLACE_NEAR=D9701.2:3MM

10%

100V

2.2UF

PLACE_NEAR=D9701.2:5MM

CRITICAL

X7R-CERM

1210

402

5%

1/16W

0

MF-LF

10%

100V

PLACE_NEAR=D9701.2:3MM

X7R-CERM

2.2UF

1210

CRITICAL

402

5%

0

1/16W MF-LF

81

7

81

7

81

7

81

7

81

7

402

PLACE_NEAR=U9701.12:10MM

D_BKL:DEV

0.1%

1/16W

TF

10.2

402

1%

301K

1/16W

MF-LF

402

PLACE_NEAR=U9701.13:10MM

D_BKL:DEV

0.1%

TF

1/16W

10.2

402

PLACE_NEAR=U9701.14:10MM

D_BKL:DEV

1/16W

0.1%

TF

10.2

402

PLACE_NEAR=U9701.16:10MM

D_BKL:DEV

1/16W

TF

10.2

0.1%

402

PLACE_NEAR=U9701.17:10MM

D_BKL:DEV

1/16W

0.1%

TF

10.2

81

7

402

PLACE_NEAR=U9701.18:10MM

D_BKL:DEV

1/16W

0.1%

TF

10.2

LLP

CRITICAL

LP8545SQX-EXTJ

402

5%

MF-LF

1/16W

10K

PLACE_NEAR=U9701.9:10MM

SM

10%

0.1UF

16V

0402

X7R-CERM

PLACE_NEAR=U9701.8:3MM

10%

X5R

PLACE_NEAR=U9701.22:5MM

1UF

25V

603-1

10%

0.1UF

X5R

402

25V

PLACE_NEAR=L9710.1:3MM

10%

16V

0.01UF

0402

X7R-CERM

PLACE_NEAR=U9701.22:3MM

10%

X5R

CRITICAL

25V

805

10UF

PLACE_NEAR=L9710.1:5MM

402

1/16W

1%

12.7K

MF-LF

402

100K

MF-LF

1/16W

1%

82

R9731

1 2

R9757

1 2

R9753

1 2

C9704

1

2

R9704

1 2

R9715

1 2

R9716

1

2

C9712

1

2

C9714

1

2

C9713

1

2

C9710

1

2

C9711

1

2

XW9710

1 2

R9755

1

2

U9701

4

7

21

20

5

6

15

9

1

3

12

13

14

16

17

18

2

10

11

24

25

8

23

22

19

R9722

1 2

R9721

1 2

R9720

1 2

R9719

1 2

R9718

1 2

R9717

1 2

C9715

1

2

C9716

1

2

C9718

1

2

C9719

1

2

C9717

1

2

R9708

1

2

R9709

1

2

R9765

1

2

R9789

1

2

Q9707

6

21

Q9707

3

54

F9700

1 2

R9788

1

2

C9782

1

2

Q9706

1 2 5 6

3

4

L9710

1 2

R9714

1

2

Q9701

5

4

123

D9701

A K

051-9589

4.18.0

97 OF 132

86 OF 99

99 81

7

44

8

86

8

99

86

8

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PCHVCCIOS0_OCSET)

Vout = 0.5V * (1 + Ra / Rb)

OCP = 14.4A

12A MAX OUTPUT

(PCHVCCIOS0_VO)

OCP = R9841 x 8.5uA / R9840

PCH VCCIO (1.05V S0) REGULATOR

Vout = 1.05V

f = 300 kHz

376S0953

152S1651

3.01K

1%

1/16W

MF-LF

402

70

2.2UF

X5R

603

16V

10%

MF-LF

1/16W

0

402

5%

PLACE_NEAR=U9800.1:1mm

SM

ISL95870

UTQFN

CRITICAL

MF-LF

1/16W

2.2

402

5%

20%

X5R

10V

603

10UF

X5R

1UF

16V

10%

402

25V

NP0-C0G

1000PF

402

5%

PLACE_NEAR=L9830.2:1.5mm

1000PF

25V

NP0-C0G

402

5%

CASE-D2E-SM

POLY-TANT

68UF

20%

CRITICAL

16V

CASE-D2E-SM

CRITICAL

20%

POLY-TANT

68UF

16V

PLACE_NEAR=Q9830.1:1.5mm

1000PF

NP0-C0G

402

5%

2V

20%

TANT

270UF

CASE-B4-SM

CRITICAL

0612

MF-1

1%

0.001

1W

2V

TANT

20%

CASE-B4-SM

270UF

CRITICAL

603

MF-LF

1/10W

0

5%

50V

C0G-CERM

0402

10PF

5%

CRITICAL

WPAK2

RJK0214DPA

PLACE_NEAR=U1800.BJ8:1MM

SM

PLACE_NEAR=U1800.BJ6:1MM

SM

PIMB103T

CRITICAL

0.68UH-20%-23A-0.0034OHM

2.0K

1%

1/16W

MF-LF

402

2.0K

1%

1/16W

MF-LF

402

50V

C0G-CERM

0402

10PF

5%

16V

X7R-CERM

0402

0.047UF

10%

1/16W

MF-LF

1%

2.74K

402

MF-LF

1%

2.74K

1/16W

402

MF-LF

1/16W

3.01K

1%

402

PCH VCCIO (1.05V) POWER SUPPLY

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

MIN_LINE_WIDTH=0.6 mm

PCHVCCIOS0_LL

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PCHVCCIOS0_BOOT_RC

DIDT=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0_PCHVCCIOS0_VCC

MIN_LINE_WIDTH=0.3 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

PCHVCCIOS0_VBST

DIDT=TRUE

PCHVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

PCHVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

PCHVCCIOS0_AGND

PPPCHVCCIO_S0_REG_R

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S0_PCHVCCIOS0

PCHVCCIOS0_RTN

=PPPCHVCCIO_S0_REG

PCH_VCCIOSENSE_N

PCH_VCCIOSENSE_P

PCHVCCIOS0_PGOOD

PCHVCCIOS0_FSEL

=PCHVCCIOS0_EN

PCHVCCIOS0_SREF

PCHVCCIOS0_FB

=PP5V_S0_PCHVCCIOS0

PCHVCCIOS0_OCSET

PCHVCCIOS0_CS_P

PCHVCCIOS0_VO

PCHVCCIOS0_CS_N

25V

OMIT_TABLE OMIT_TABLE

C9804

1

2

C9805

1

2

C9803

1

2

R9845

1

2

R9805

1

2

R9804

1

2

R9844

1

2

C9802

1

2

R9803

1

2

XW9800

1 2

U9800

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

R9801

1

2

C9801

1

2

C9830

1

2

C9840

12

C9823

1

2

C9820

1

2

C9821

1

2

C9822

1

2

C9848

1

2

R9840

2 1

4 3

C9849

1

2

R9830

1

2

Q9830

2

1

6

7

3 4 5

XW9801

1 2

XW9802

1 2

L9830

1 2

R9842

1

2

R9841

1

2

051-9589

4.18.0

98 OF 132

87 OF 99

8

87

8

87

97

8

97 99

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

KEPLER GPU REQUIRES RAILS TO COME

1) GPU_3.3V

2) IFPX IOVDD - 1.8V

4) FBVDDQ/GDDR5 1.35V

EXT GPU PWRGD Pullup

Unused PGOOD signal

3) GPUVCORE

5) PEXVDD/Q

NOTE 2: CHECK IF 1V8 IS READ AS LOGIC HIGH BY GMUX

NOTE: NO PU ON 3V3 AND 1V8 PGOODS SINCE THEY ARE SYNTHETIC.

PLACE R9910 - R9917 CLOSE TO U8000

PLACE R9920 - R9927 CLOSE TO U1000

PCIE TEST STRUCTURES (FOR LAB USE)

OR IFPY IOVDD - 1.05V

up in the following order:

GPU Rail Sequencing

NOTE: 1V8 MAY NOT BE REQUIRED FOR KEPLER IF THERE IS NO LVDS

65

64

69

1/16W

MF-LF

5%

402

NO STUFF

10K

8

69

80

74

8

1/20W

MF

5%

100K

201

MF

1/20W

5%

100K

201

5%

201

1/20W

100K

MF

80

74

8

82

74

69

82

5%

1/20W

MF

201

NOSTUFF NOSTUFF

201

82

5%

1/20W

MF

NOSTUFF

201

82

5%

1/20W

MF

NOSTUFF

82

5%

1/20W

MF

201

NOSTUFF

82

5%

1/20W

MF

201

NOSTUFF

82

5%

1/20W

MF

201

NOSTUFF

82

5%

1/20W

MF

201

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

Power Sequencing EG/PCH S0

P1V8GPU_EN

MAKE_BASE=TRUE

GPUVCORE_EN

MAKE_BASE=TRUE

GPUVCORE_PGOOD

P1V05_S0GPU_EN

MAKE_BASE=TRUE

GPUFB_PGOOD

MAKE_BASE=TRUE

P1V05_S0GPU_PGOOD

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

P1V35GPUFB_EN

MAKE_BASE=TRUE

P3V3GPU_EN

MAKE_BASE=TRUE

PEG_D2R_N<0>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<4>

PEG_D2R_N<4>

=P3V3GPU_MISC_EN

=P1V35FB_EN

=P3V3GPU_EN

GPU_PGOOD4

EG_RAIL4_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL5_EN

=GPUVCORE_EN

=P1V05_GPU_EN

EG_RAIL1_EN

P1V5S3RS0_RAMP_DONE

DDRREG_PGOOD

CPUIMVP_AXG_PGOOD

=PP3V3_S0_PWRCTL

PM_ALL_GPU_PGOOD

PEG_D2R_P<0>

PEG_R2D_N<0>

PEG_R2D_P<0>

PEG_R2D_N<3>

PEG_R2D_P<3>

PEG_R2D_N<5>

PEG_R2D_P<5>

PEG_R2D_N<7>

PEG_R2D_P<7>

GPU_PGOOD3

=PP3V3_S0GPU_FET

GPU_PGOOD1

=PP1V8_GPU_FET

GPU_PGOOD2

=PP3V3_S0_PWRCTL

=P1V8GPU_EN

R9991

1

2

R9901

1

2

R9902

1

2

R9900

1

2

R9920

1

2

R9924

1

2

R9927

1

2

R9913

1

2

R9910

1

2

R9915

1

2

R9917

1

2

051-9589

4.18.0

99 OF 132

88 OF 99

9

71 89

9

71 89

9

71 89

9

71 89

9

71 89

82

8

70 88

9

71 89

8

70 88

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Some signals require 27.4-ohm single-ended impedance.

PCI-Express

SOURCE: IVB PLATFORM DG , Tables 205-207

Most CPU signals with impedance requirements are 50-ohm single-ended.

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

CPU Signal Constraints

PEG

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SPACING

PHYSICAL

NET_TYPE

I115

I120

I121

I122

I123

I125

I126

I127

I128

I129

I130

I131

I132

I133

I134

I135

I136

I137

I138

I139

I140

I141

I144

I145

I146

I147

I148

I149

I150

=50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

CPU_50S

=50_OHM_SE

*

=50_OHM_SE

=27P4_OHM_SE

7 MIL

=27P4_OHM_SE

CPU_27P4S

=27P4_OHM_SE

7 MIL

*

CPU_VREF

12 MIL

* ?

CPU_VCCSENSE

25 MIL

?*

=2:1_SPACING

* ?

CPU_ITP

20 MIL

CPU_COMP

?*

?

CPU_8MIL

8 MIL

*

0.457 MM

?

CPU_VID

*

=2x_DIELECTRIC

TOP,BOTTOM

CPU_AGTL

?

=85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

PCIE_85D

=90_OHM_DIFF

*

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFFCLK_PCIE_90D

=90_OHM_DIFF

PCIE

TOP,BOTTOM

15 MIL

?

CPU_AGTL

?*

=STANDARD

=80_OHM_DIFF

*

=80_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF

PEG_80D

15 MIL

?

PCIE

*

CLK_PCIE

20 MIL

?*

=55_OHM_SE=55_OHM_SE

=STANDARD

=55_OHM_SE

CPU_55S

=55_OHM_SE

=STANDARD

*

SYNC_DATE=01/13/2012

CPU Constraints

SYNC_MASTER=D2_KEPLER

=4X_DIELECTRIC

PEG_RXRX

* ?

PEG_TXTX

=4X_DIELECTRIC

*

?

=10X_DIELECTRIC

PEG_TXRX

?

*

PEG_TXRX

PEG_D2R PEG_R2D

*

PEG_R2DPEG_R2D

PEG_TXTX

*

PEG_RXRX

PEG_D2RPEG_D2R

*

PEG_R2D

PEG_R2D_P<7..0>

PEG_80D

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSE_P

CPU_27P4S

CPU_VID

CPU_VIDSCLK

CPU_50S

CPU_AGTL

CPU_50S

CPU_PWRGD

CPU_AGTL

PM_MEM_PWRGD

CPU_50S

PM_SYNC

CPU_50SPM_SYNC

CPU_AGTL

CPU_VCCSENSECPU_VCCSENSE

CPU_27P4S

CPU_VCC_VALSENSE_N

CPU_VREF

CPU_MEM_VREF

PPCPU_MEM_VREFDQ_A

CPU_VREF

PP0V75_S3_MEM_VREFDQ_A

CPU_MEM_VREF

CPU_VREF

PP0V75_S3_MEM_VREFDQ_B

CPU_MEM_VREF

CPU_VREF

PP0V75_S3_MEM_VREFCA_A

XDP_CPU_CLK100M_N

CLK_PCIE

XDP_CLK_ITP

CLK_PCIE_90D

CPU_VREF

CPU_MEM_VREF

PP0V75_S3_MEM_VREFCA_B

CPU_VREF

CPU_MEM_VREF

PPCPU_MEM_VREFDQ_B

CPU_AGTL

CPU_VCCSASENSE

CPU_50S

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCIOSENSE_N

CPU_27P4S

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

CPU_PROCHOT_L

CPU_ITP

XDP_CPU_TDI

XDP_TDI CPU_50S

DPLL_REF_CLK120M

CLK_PCIE_90D

CLK_PCIE

DPLL_REF_CLKP

XDP_CLK_CPU

CLK_PCIE

CLK_PCIE_90D

ITPCPU_CLK100M_N

CPU_ITPCPU_CFG

CPU_CFG<17..0>

CPU_50S

CPU_COMP

CPU_PEG_COMP

CPU_27P4S

CPU_PEG_COMP

CPU_EDP_COMP

CPU_COMP

CPU_EDP_COMP

CPU_27P4S

DP_INT_AUX

DISPLAYPORT

DP_INT_IG_AUX_N

DP_85D

XDP_CLK_PCH

CLK_PCIE

ITPXDP_CLK100M_N

CLK_PCIE_90D

CPU_ITP

XDP_CPU_TMS

XDP_TMS CPU_50S

CPU_VID CPU_VIDALERT_L

CPU_50S

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCIOSENSE_P

CPU_27P4S

CPU_VCCSENSECPU_VCCSENSE

CPU_27P4S

CPU_AXG_VALSENSE_P

CPU_VCCSENSECPU_VCCSENSE

CPU_27P4S

CPU_AXG_SENSE_N

CPU_VCCSENSECPU_VCCSENSE

CPU_27P4S

CPU_AXG_SENSE_P

CPU_VID

CPU_VIDSOUT

CPU_50S

CPU_VCCSENSECPU_VCCSENSE

CPU_AXG_VALSENSE_N

CPU_27P4S

CPU_VCCSENSECPU_VCCSENSE

CPU_VCCSENSE_N

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP

CPU_SM_RCOMP<2..0>

CPU_27P4S

CPU_VIDCPU_50S

CPU_PECI

XDP_TCK CPU_ITP

XDP_CPU_TCK

CPU_50S

XDP_PREQ_L

CPU_ITP

XDP_CPU_PREQ_L

CPU_50S

XDP_CPU_PWRGD

CPU_ITP

XDP_CPU_PWRGD

CPU_50S

CPU_VID

CPU_VCCSA_VID<1..0>

CPU_55S

CPU_VCCSENSECPU_VCCSENSE

CPU_27P4S

CPU_VCC_VALSENSE_P

PEG_R2D

PEG_R2D_N<7..0>

PEG_80D

PEG_R2DPEG_R2D

PEG_R2D_C_P<7..0>

PEG_80D

PEG_R2D

PEG_R2D_C_N<7..0>

PEG_80D

PEG_D2RPEG_80D

PEG_D2R_C_P<7..0>

PEG_D2RPEG_80D

PEG_D2R_C_N<7..0>

CPU_AGTL

CPU_CATERR_L

CPU_50S

PEG_D2RPEG_80D

PEG_D2R_N<7..0>

XDP_CLK_ITP

XDP_CPU_CLK100M_P

CLK_PCIE_90D

CLK_PCIE

CPU_8MIL

PM_THRMTRIP_L

CPU_50S

PM_THRMTRIP_L

CPU_PROC_SEL_L

CPU_AGTL

CPU_50S

CPU_50S CPU_ITP

XDP_CPU_PRDY_L

XDP_PRDY_L

XDP_BPM_L

CPU_ITP

XDP_BPM_L<7..4>

CPU_50S

XDP_BDRESET_L

CPU_ITP

XDP_DBRESET_L

CPU_50S

CPU_ITP

XDP_CPU_TDO

XDP_TDO CPU_50S

CPU_ITP

XDP_TRST_L

XDP_CPU_TRST_L

CPU_50S

CPU_ITP

XDP_BPM_L<3..0>

XDP_BPM CPU_50S

XDP_CLK_CPU

ITPCPU_CLK100M_P

CLK_PCIE

CLK_PCIE_90D

DP_INT_ML

DP_INT_IG_ML_P<3:0>

DISPLAYPORT

DP_85D

CLK_PCIE

DMI_CLK100M_CPU_P

CLK_PCIE_90D

DMI_CLK100M

DMI_S2N_P<3:0>

PCIE_85D

PCIE

DMI_S2N

FDI_INT

CPU_AGTL

CPU_50S

DP_INT_ML

DP_85D

DISPLAYPORT

DP_INT_IG_ML_N<3:0>

PEG_D2RPEG_80DPEG_D2R

PEG_D2R_P<7..0>

DPLL_REF_CLK120M CLK_PCIE

DPLL_REF_CLKN

CLK_PCIE_90D

DP_INT_AUX

DP_85D

DISPLAYPORT

DP_INT_IG_AUX_P

XDP_CLK_PCH

CLK_PCIE

ITPXDP_CLK100M_P

CLK_PCIE_90D

FDI_DATA

PCIE

PCIE_85D

FDI_DATA_P<7:0>

DMI_N2S

DMI_N2S_N<3:0>

PCIE

PCIE_85D

PCIE

PCIE_85DFDI_DATA

FDI_DATA_N<7:0>

FDI_FSYNC

FDI_FSYNC<1..0>

CPU_AGTL

CPU_50S

FDI_LSYNC

CPU_AGTL

CPU_50S

FDI_LSYNC<1..0>

DMI_CLK100M

DMI_CLK100M_CPU_N

CLK_PCIE_90D

CLK_PCIE

DMI_S2N

DMI_S2N_N<3:0>

PCIE_85D

PCIE

DMI_N2S

DMI_N2S_P<3:0>

PCIE

PCIE_85D

051-9589

4.18.0

100 OF 132

89 OF 99

71 88

13 65

11 20 24

11 18 27

11 18

13

10 33

28 29 33

30 31 33

28 29 33

24

30 31 33

10 33

13 62

13 67

11 41 42 65

11 24

9

11

11 17

10 24

10

10 82

17 24

11 24

13 65

13 67

13

13 65

13

13 65

11

11 20 42

11 24

24

13 62

13

71 88

9

71

9

71

11 41

9

71 88

24

11 20 42

11 20

11 24

11 24 25

11 24

11 17

10 82

11 17

10 18

10 82

9

71 88

9

11

10 82

17 24

9

10

10 18

9

10

9

10

9

10

11 17

10 18

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.

.

SPACING

DDR3 (Memory Down):

Memory Bus Spacing Group Assignments

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.

DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].

SOURCE: Chief River SFF Platform DG, Rev 0.7 (#460452), Section 2.6.3

Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

DQ signals should be matched within 0.508mm of associated DQS pair

Memory Bus Constraints

Memory Net Properties

I101

I102

I103

I104

I105

I106

I107

I108

I109

I110

I111

Memory Constraints

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

=STANDARD =STANDARD

=37_OHM_SE=37_OHM_SE

*

MEM_37S

=37_OHM_SE=37_OHM_SE

MEM_72D

*=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF =72_OHM_DIFF

=72_OHM_DIFF=72_OHM_DIFF

=50_OHM_SE

*

=50_OHM_SE

=STANDARD =STANDARD

MEM_50S

=50_OHM_SE=50_OHM_SE

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF*=85_OHM_DIFF

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

=4:1_SPACING

*

MEM_CLK2MEM

?

MEM_CTRL2CTRL

?

*

=3:1_SPACING

MEM_2OTHER

25 MILS

?

*

MEM_CMD

*

MEM_CMD2MEM

MEM_*

MEM_CMD

MEM_CMD2CMD

*

MEM_CMD

MEM_CTRL2MEM

*

MEM_CTRL

MEM_*

MEM_CLK2MEM

*

MEM_CLK

=3:1_SPACING

*

?

MEM_DATA2MEM

MEM_CMD2CMD

*

?

=1.5:1_SPACING

*

?

MEM_CMD2MEM

=3:1_SPACING

MEM_*

* *

MEM_2OTHER

MEM_DQS2MEM

MEM_DQS

*

MEM_*

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2CTRL

25 MILS

*

?

MEM_DQCH2CH

=3:1_SPACING

*

?

MEM_DQS2MEM

MEM_B_DQ_BYTE* MEM_B_DQ_BYTE*

MEM_DQBL2BL

*

MEM_CTRL2MEM

=2.5:1_SPACING

*

?

16 MILS

*

?

MEM_DQBL2BL

?

*

MEM_DATA2DATA

=1.5:1_SPACING

MEM_*_DQ_BYTE*

=SAME

MEM_DATA2DATA

*

MEM_*_DQ_BYTE*

MEM_DATA2MEM

*

MEM_*

MEM_A_DQ_BYTE* MEM_B_DQ_BYTE*

MEM_DQCH2CH

*

MEM_A_DQ_BYTE*

MEM_DQBL2BL

MEM_A_DQ_BYTE*

*

MEM_40S

*=STANDARD =STANDARD

=40_OHM_SE =40_OHM_SE=40_OHM_SE=40_OHM_SE

MEM_DQS

MEM_B_DQS1

MEM_85D

MEM_B_DQS_N<1>

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7MEM_50SMEM_B_DQ_BYTE7

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6MEM_50SMEM_B_DQ_BYTE6

MEM_B_DQ<47..40>

MEM_50SMEM_B_DQ_BYTE5 MEM_B_DQ_BYTE5

MEM_B_DQ_BYTE4MEM_50SMEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_DQSMEM_85D

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_DQS

MEM_B_DQS3

MEM_85D

MEM_B_DQS_P<3>

MEM_DQSMEM_85D

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_B_DQS5

MEM_DQSMEM_85D

MEM_B_DQS_P<5>

MEM_DQSMEM_85D

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_DQSMEM_85D

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_DQS

MEM_B_DQS0

MEM_85D

MEM_B_DQS_P<0>

MEM_B_DQS5

MEM_DQSMEM_85D

MEM_B_DQS_N<5>

MEM_DQS

MEM_B_DQS4

MEM_85D

MEM_B_DQS_N<4>

MEM_DQS

MEM_B_DQS6

MEM_85D

MEM_B_DQS_P<6>

MEM_DQS

MEM_B_DQS7

MEM_85D

MEM_B_DQS_P<7>

MEM_B_DQS6

MEM_DQSMEM_85D

MEM_B_DQS_N<6>

MEM_DQS

MEM_B_DQS7

MEM_85D

MEM_B_DQS_N<7>

MEM_CLKMEM_72D

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_37S

MEM_CTRL

MEM_A_CKE<3..0>

MEM_A_CNTL

MEM_CTRL

MEM_37S

MEM_A_CNTL

MEM_A_CS_L<3..2>

MEM_CTRL

MEM_37S

MEM_A_CS_L<1>

MEM_A_CNTL1

MEM_A_ODT<1>

MEM_A_CNTL1

MEM_CTRL

MEM_37S

MEM_CLK

MEM_A_CLK_P<5..0>

MEM_72D

MEM_A_CLK

MEM_40S MEM_CMD

MEM_A_CMD

MEM_A_CAS_L

MEM_50SMEM_A_DQ_BYTE7 MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE6MEM_50SMEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE4MEM_50S

MEM_A_DQ<39..32>

MEM_A_DQ_BYTE4

MEM_A_DQ_BYTE5

MEM_A_DQ<47..40>

MEM_50SMEM_A_DQ_BYTE5

MEM_50S

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE2

MEM_50S

MEM_A_DQ<31..24>

MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE3

MEM_50S

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE1

MEM_DQS

MEM_A_DQS0

MEM_85D

MEM_A_DQS_P<0>

MEM_DQS

MEM_A_DQS0

MEM_85D

MEM_A_DQS_N<0>

MEM_DQS

MEM_A_DQS1

MEM_85D

MEM_A_DQS_N<1>

MEM_DQS

MEM_A_DQS1

MEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS2

MEM_DQSMEM_85D

MEM_A_DQS_P<2>

MEM_DQS

MEM_A_DQS2

MEM_85D

MEM_A_DQS_N<2>

MEM_DQS

MEM_A_DQS3

MEM_85D

MEM_A_DQS_P<3>

MEM_DQS

MEM_A_DQS3

MEM_85D

MEM_A_DQS_N<3>

MEM_85D

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_DQS

MEM_85D

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_DQS

MEM_A_DQS6

MEM_DQSMEM_85D

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_DQSMEM_85D

MEM_A_DQS_P<6>

MEM_DQS

MEM_A_DQS7

MEM_85D

MEM_A_DQS_N<7>

MEM_A_DQS4

MEM_85D

MEM_A_DQS_P<4>

MEM_DQS

MEM_A_DQS5

MEM_DQSMEM_85D

MEM_A_DQS_N<5>

MEM_A_DQS7

MEM_DQSMEM_85D

MEM_A_DQS_P<7>

MEM_B_DQ_BYTE2MEM_50S

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3MEM_50SMEM_B_DQ_BYTE3

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1MEM_50SMEM_B_DQ_BYTE1

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0MEM_50SMEM_B_DQ_BYTE0

MEM_B_CMD

MEM_CMDMEM_40S

MEM_B_A<15..7>

MEM_B_WE_L

MEM_B_CMD

MEM_CMDMEM_40S

MEM_B_CMD

MEM_40S MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_CMDMEM_40S

MEM_B_RAS_L

MEM_B_CMD

MEM_40S MEM_CMD

MEM_B_BA<2..0>

MEM_40S MEM_CMD

MEM_B_CMD

MEM_B_A<5..0>

MEM_40S MEM_CMD

MEM_B_A<6>

MEM_B_CMD6

MEM_37S

MEM_CTRL

MEM_B_ODT<0>

MEM_B_CNTL0

MEM_37S

MEM_B_CNTL

MEM_CTRL

MEM_B_ODT<3..1>

MEM_72D

MEM_B_CLK

MEM_CLK

MEM_B_CLK_N<5..0>

MEM_72D MEM_CLK

MEM_B_CLK_P<5..0>

MEM_B_CLK

MEM_37S

MEM_B_CNTL

MEM_CTRL

MEM_B_CS_L<3..0>

MEM_37S

MEM_B_CNTL

MEM_CTRL

MEM_B_CKE<3..2>

MEM_CTRL

MEM_37S

MEM_B_CKE<0>

MEM_B_CNTL0

MEM_CTRL

MEM_37S

MEM_B_CKE<1>

MEM_B_CNTL1

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0MEM_A_DQ_BYTE0 MEM_50S

MEM_40S MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_40S MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_40S

MEM_A_BA<2..0>

MEM_A_CMD

MEM_CMD

MEM_40S

MEM_A_CMD

MEM_A_A<15..0>

MEM_CMD

MEM_A_CNTL

MEM_CTRL

MEM_A_ODT<0>

MEM_37S

MEM_CTRL

MEM_A_CNTL

MEM_37S

MEM_A_ODT<3..2>

MEM_37S

MEM_CTRL

MEM_A_CNTL

MEM_A_CS_L<0>

MEM_DQS

MEM_B_DQS4

MEM_85D

MEM_B_DQS_P<4>

051-9589

4.18.0

101 OF 132

90 OF 99

12 30 31

12 28 29 32

12 29 32

12 28 29 32

12 28 29

12 30 31

12 30 31 32

12 30 32

12 31 32

12 30 31 32

12 30 32

12 31 32

12 28 29

12 28 29 32

12 28 32

12 30 31

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

System Clock Signal Constraints

NOTE: 25MHz system clocks very sensitive to noise.

Clock Net Properties

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

PCH Net Properties

SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

USB 3.0 INTERFACE CONSTRAINTS

Digital Video Signal Constraints

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

SATA Interface Constraints

USB 2.0 Interface Constraints

I213

I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I259

I260

=50_OHM_SE

*

SATA_50SE

=50_OHM_SE=50_OHM_SE

=50_OHM_SE

*

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD

CLK_SLOW_55S

?

*

CLK_25M =5x_DIELECTRIC

*

?

CLK_SLOW

=2x_DIELECTRIC

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

*

=85_OHM_DIFF

USB_85D

=85_OHM_DIFF

=4:1_SPACING

USB

TOP,BOTTOM

?

15 MIL

SATA_ICOMP

?*

TOP,BOTTOM

=4:1_SPACING

?

LVDS

PCH_DISPLAYPORT

TOP,BOTTOM

?

=4:1_SPACING

?

TOP,BOTTOM

=5:1_SPACING

SATA

=4:1_SPACING

?

USB

ISL3,ISL4,ISL9,ISL10

15 MIL

?*

USB_RBIAS

?

TOP,BOTTOM

USB3

=5:1_SPACING

ISL3,ISL4,ISL9,ISL10

?

USB3

=5:1_SPACING

PCH_DP_90D

=90_OHM_DIFF

*

=90_OHM_DIFF

*

=90_OHM_DIFF

LVDS_85D

=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

PCH_DISPLAYPORT

?

=4:1_SPACING

ISL3,ISL4,ISL9,ISL10

=4:1_SPACING

?

LVDS

ISL3,ISL4,ISL9,ISL10

=37_OHM_SE

SATA_37SE

*

=37_OHM_SE=37_OHM_SE

=5:1_SPACING

ISL3,ISL4,ISL9,ISL10

SATA

?

=STANDARD=STANDARD

=STANDARD

*

=STANDARD

PCH_USB_RBIAS

=90_OHM_DIFF

*

=90_OHM_DIFF

SATA_90D

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

=STANDARD=STANDARD

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

*

CLK_25M_55S

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

PCH Constraints 1

SYSCLK_CLK32K_RTC

CLK_SLOW_55S CLK_SLOW

SYSCLK_CLK32K_RTC

LVDS_85D

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK

LVDS

LVDS_85D

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK

LVDS

LVDS_IG_A_DATA

LVDS

LVDS_85D

LVDS_IG_A_DATA_P<2..0>

LVDS

LVDS_IG_A_DATA

LVDS_85D

LVDS_IG_A_DATA_N<2..0>

LVDS

LVDS_IG_A_DATA3

LVDS_85D

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA3

LVDS_85D

LVDS

LVDS_85D

LVDS

LVDS_IG_B_DATA

LVDS_IG_B_DATA_P<2..0>

LVDS_85D

LVDS

LVDS_IG_B_DATA_N<2..0>

LVDS_IG_B_DATA

SATA

SATA_90D

SATA_HDD_R2D_C_P

SATA_HDD_R2D

SATA_HDD_D2R

SATA

SATA_HDD_D2R_P

SATA_90D

SATA

SATA_HDD_R2D_C_N

SATA_90D

SATA_HDD_D2R_N

SATA

SATA_90D

SATA_SSD_D2R_MUX_OUT_P

SATA

SATA_HDD_D2R

SATA

SATA_90D

SATA_SSD_D2R_MUX_OUT_N

SATA_90D

SATA

SATA_SSD_R2D_MUX_IN_N

SATA

SATA_90D

SATA_HDD_R2D

SATA_SSD_R2D_MUX_IN_P

SATA_HDD_D2R

SATA_90D

SATA

SATA_SSD_D2R_P

SATA

SATA_90D

SATA_SSD_D2R_N

SATA_HDD_R2D

SATA_90D

SATA

SATA_SSD_R2D_P

SATA_HDD_R2D

SATA_90D

SATA

SATA_HDD_R2D_UF_P

SATA_90D

SATA_SSD_R2D_N

SATA

SATA_HDD_R2D_UF_N

SATA

SATA_90D

SATA_ODD_R2D

SATA

SATA_ODD_R2D_C_P

SATA_90D

SATA_ODD_R2D_P

SATA

SATA_ODD_R2D

SATA_ODD_R2D_C_N

SATA

SATA_90D

SATA_ODD_D2R_N

SATA

SATA_90D

SATA_ODD_R2D_N

SATA

SATA_90D

SATA

SATA_90D

SATA_ODD_D2R

SATA_ODD_D2R_P

SATA_90D

SATA

SATA_ODD_D2R_UF_N

SATA

SATA_90D

SATA_ODD_D2R

SATA_ODD_D2R_UF_P

SATA_ICOMP

SATA_50SE

PCH_SATA3COMP

PCH_SATA3_ICOMP

SATA_37SE

SATA_ICOMP

PCH_SATAICOMP

PCH_SATA_ICOMP

USB

USB_85D

USB_EXTB_EHCI_P

USB_HUB1_UP

USB

USB_EXTB_XHCI_P

USB_HUB1_UP

USB_85D

USB

USB_EXTB_XHCI_N

USB_EXTB_EHCI_N

USB_85D

USB

USB_HUB_UP_P

USB

USB_85D

USB_HUB2_UP

USB_EXTA_N

USB_85D

USB

USB_HUB_UP_N

USB_85D

USB

USB_EXTA_P

USB_EXTA

USB_85D

USB_EXTB

USB_85D

USB_EXTB_P

USB

USB_85D

USB

USB_EXTB_N

USB_CAMERA_CONN_P

USB_CAMERA

USB

USB_85D

USB_EXTC_P

USB

USB_85D

USB_EXTC

USB_EXTC_N

USB

USB_85D

USB

USB_85D

USB_BT_N

USB_CAMERA_CONN_N

USB

USB_85D

USB

USB_BT_P

USB_BT

USB

USB_85D

USB_BT_CONN_N

USB_85D

USB

USB_BT

USB_BT_CONN_P

USB_85D

USB

USB_TPAD_P

USB_TPAD

USB_BT

USB

USB_85D

USB_BT_WAKE_P

USB_85D

USB

USB_BT_WAKE_N

USB_IR

USB_SMC_P

USB

USB_85D

USB

USB_85D

USB_TPAD_N

PCH_USB_RBIAS

USB_RBIAS

USB_SMC_N

USB_85D

USB

USB_T29A

USB

USB_85D

USB_EXTD_XHCI_P

USB_EXTD_XHCI_N

USB_85D

USB

USB_EXTA_MUXED_P

USB_85D

USB

USB_EXTA

USB_85D

USB_EXTA_MUXED_N

USB

USB_CAMERA_N

USB

USB_85D

USB_CAMERA_P

USB_85D

USB

USB_CAMERA

USB3_EXTB_TX_P

USB_85D

USB3_EXTB_TX

USB3

USB_LT1_P

USB_85D

USB

USB_EXTA

USB_LT1_N

USB

USB_85D

USB3_EXTB_TX_N

USB_85D

USB3

USB_85D

USB3_EXTB_RX_P

USB3_EXTB_RX

USB3

USB3_EXTB_RX_N

USB_85D

USB3

USB3_EXTC_TX_P

USB_85D

USB3_EXTC_TX

USB3

USB3_EXTC_TX_N

USB3

USB_85D

USB3_EXTC_RX_P

USB3_EXTC_RX

USB3

USB_85D

USB3_EXTC_RX_N

USB_85D

USB3

USB3_EXTA_RX_P

USB_85D

USB3_EXTA_RX

USB3

USB3_EXTA_TX

USB_85D

USB3_EXTA_TX_P

USB3

USB3_EXTA_TX_N

USB_85D

USB3

USB3_EXTA_RX_N

USB3

USB_85D

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_SB_R

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_ENET

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_ENET_R

CLK_25M

CLK_25M_55S

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_TBT

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_TBT_R

051-9589

4.18.0

102 OF 132

91 OF 99

17 25

9

18

9

18

9

18

9

18

9

18

9

18

9

18

9

18

17 39

39

9

17

9

17

9

17

9

17

19 26

19 40

19 26

19 40

7

26 38

7

26 38

7

34

9

19

9

19

9

34

7

34

9

34

7

34

7

34

9

49

34

9

41

9

49

19

9

41

19 26

40

19 34

19 38

40

19 38

7

19 38

7

19 38

9

19

9

19

9

19

9

19

19 40

17 25

17

25 35

35

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SIO Signal Constraints

SPI Interface Constraints

SMBus Interface Constraints

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

PCH Net Properties

HD Audio Interface Constraints

LPC Bus Constraints

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I275

I276

I277

I278

I279

I280

I281

I282

PCH Constraints 2

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

LPC_50S

=50_OHM_SE =50_OHM_SE

*

=50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

6 MIL

LPC

?*

* ?

CLK_LPC

8 MIL

?

=2x_DIELECTRIC

SMB

*

8 MIL

?

SPI

*

=50_OHM_SE=50_OHM_SE

*

=STANDARD =STANDARD

SMB_50S

=50_OHM_SE=50_OHM_SE

CLK_LPC_50S

=50_OHM_SE=50_OHM_SE =50_OHM_SE

=STANDARD

*

=STANDARD

=50_OHM_SE

=50_OHM_SE=50_OHM_SE =50_OHM_SE

=STANDARD

*

=50_OHM_SE

HDA_50S

=STANDARD

*

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

SPI_55S

=STANDARD

8 MIL

*

CLK_SLOW

?

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SE

=STANDARD

*

CLK_SLOW_55S

*

=2x_DIELECTRIC

HDA

?

PCIE_CLK100M_PCH_N

CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_TBT_N

CLK_PCIE_90D

CLK_PCIE

PCH_CLK96M_DOT_P

CLK_PCIE_90D

PCIE_CLK100M_TBT_

CLK_PCIE

CLK_PCIE_90D

PCH_CLK100M_SATA_P

PCIE_TBT_R2D

PCIE_85D

PCIE

PCIE_SSD_R2D_MUX_IN_P

PCIE_TBT_D2R

PCIE_85D

PCIE

PCIE_SSD_D2R_MUX_OUT_P

PCIE_TBT_D2R

PCIE_SSD_D2R_P<1..0>

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_SSD_D2R_N<1..0>

PCIE_TBT_D2R

PCIE_SSD_D2R_C_P<1>

PCIE

PCIE_85D

PCIE_CLK100M_TBT_

CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_TBT_P

1:1_DIFFPAIR

PEX_TSTCLK_O_N

CLK_PCIE

PCIE_CLK100M 1:1_DIFFPAIR

PEX_TSTCLK_O_P

CLK_PCIE

PCIE_SSD_R2D_N<1>

PCIE_85D

PCIE

PCIE_CLK100M_SSD_N

CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_SSD_P

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_FW

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW

CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_FW_N

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_PCIE_90D

PCIE_CLK100M_EXCARD

CLK_PCIE

PCIE_CLK100M_EXCARD_P

CLK_PCIE_90D

PCIE_TBT_D2R_P<3..0>

PCIE

PCIE_85D

PCIE_TBT_D2R

PCIE

PCIE_85D

PCIE_TBT_D2R_C_P<3..0>

PCIE_TBT_D2R

PCIE

PCIE_85D

PCIE_TBT_D2R

PCIE_TBT_D2R_C_N<3..0>

PCIE_TBT_D2R_N<3..0>

PCIE

PCIE_85D

PCIE_TBT_D2R

PCIE_85D

PCIE

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D

PCIE_TBT_R2D_P<3..0>

PCIE

PCIE_85D

PCIE_TBT_R2D

PCIE_TBT_R2D_C_N<3..0>

PCIE

PCIE_85D

PCIE_TBT_R2D

PCIE_TBT_R2D_C_P<3..0>

PCIE

PCIE_85D

PCIE_TBT_R2D

PEG_CLK100M_P

PCIE_CLK100M

CLK_PCIE

CLK_PCIE_90D

SPI_55SSPI_CS0

SPI

SPI_CS0_R_L

PCIE_ENET_R2D_C_N

PCIE

PCIE_85D

PCIE_ENET_D2R_N

PCIE_85D

PCIE

PCIE_ENET_D2R_C_P

PCIE_85D

PCIE

PCIE_AP_R2D_PI_P

PCIE

PCIE_85D

PCIE_AP_D2R

PCIE_SSD_D2R_C_N<1>

PCIE

PCIE_85D

PCIE_TBT_R2D

PCIE_SSD_R2D_P<1>

PCIE

PCIE_85D

PCIE_CLK100M

PCIE_CLK100M_PCH_P

CLK_PCIE_90D

CLK_PCIE

PEG_CLK100M_N

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_AP_N

PCH_CLK96M_DOT_N

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CPU_50S

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

CPU_50S

CLK_PCIE

PCH_CLK100M_SATA_N

CLK_PCIE

CLK_PCIE_90D

SPI_CLK_R

SPI_55S

SPI

SPI_CLK

HDA

HDA_50S

HDA_SYNC_R

HDA_50S

HDA

HDA_BIT_CLK

HDA_50S

HDA

HDA_SDOUT

HDA

HDA_50S

HDA_BIT_CLK_R

SMBUS_PCH_DATA

SMB_50S

SMB

SMBUS_PCH_DATA

SMB_50S

SMB

SMBUS_PCH_1_DATA

SML_PCH_1_DATA

LPC_FRAME_L

LPC_50S

LPC

LPC_FRAME_L

SML_PCH_1_CLK

SMB_50S

SMB

SMBUS_PCH_1_CLK

SMB_50S

SMB

SML_PCH_0_CLK

SMBUS_PCH_0_CLK

HDA_RST_L

HDA_50S

HDA_RST_R_L

HDA

SPI_55S

SPI_MOSI

SPI

HDA_50S

HDA

HDA_RST_L

AUD_SDI_R

HDA

HDA_50S

HDA_SDIN0

HDA_50S

HDA

HDA_SDIN0

HDA_50S

HDA

HDA_SDOUT_R

SPI_MOSI

SPI_MOSI_R

SPI_55S

SPI

HDA_SYNC

HDA

HDA_50S

LPC_50S

LPC

LPC_AD<3..0>

LPC_AD

SMBUS_PCH_CLK

SMB_50S

SMB

SMBUS_PCH_CLK

SML_PCH_0_DATA

SMB

SMB_50S

SMBUS_PCH_0_DATA

SPI_CS0_L

SPI

SPI_55S

PCIE_ENET_R2D_P

PCIE_85D

PCIE

PCIE_ENET_R2D_N

PCIE_85D

PCIE

PCIE_ENET_R2D_C_P

PCIE

PCIE_85D

PCIE_ENET_R2D

PCIE_ENET_D2R_P

PCIE_85D

PCIE_ENET_D2R

PCIE

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_AP

PCIE_CLK100M_AP_P

CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_ENET_N

CLK_PCIE

PCIE_CLK100M_ENET

CLK_PCIE_90D

PCIE_CLK100M_ENET_P

SPI_55S

SPI_MISO

SPI

SPI_MISO

SPI_55S

SPI_CLK

SPI

PCIE_ENET_D2R_C_N

PCIE

PCIE_85D

PCIE_AP_R2D_P

PCIE_85D

PCIE

PCIE_AP_R2D_N

PCIE

PCIE_85D

PCIE_AP_R2D_C_P

PCIE_85D

PCIE

PCIE_AP_R2D

PCIE_AP_R2D_C_N

PCIE_85D

PCIE

PCIE_AP_D2R_P

PCIE_AP_D2R

PCIE

PCIE_85D

PCIE_AP_D2R_N

PCIE

PCIE_85D

PCIE_AP_R2D_PI_N

PCIE

PCIE_85D

PCIE_AP_D2R

PCIE_AP_D2R_PI_P

PCIE

PCIE_85D

PCIE_AP_D2R_PI_N

PCIE_85D

PCIE

PCIE_SSD_D2R_MUX_OUT_N

PCIE_85D

PCIE

PCIE_TBT_R2D

PCIE_85D

PCIE

PCIE_SSD_R2D_C_P<1..0>

PCIE_85D

PCIE

PCIE_SSD_R2D_C_N<1..0>

PCIE

PCIE_85D

PCIE_SSD_R2D_MUX_IN_N

LPC_CLK33M_LPCPLUS

CLK_LPC

CLK_LPC_50S

LPC_CLK33M_SMC

CLK_LPC

CLK_LPC_50S

PCH_LPC_CLK0

LPC_CLK33M_SMC_R

CLK_LPC

LPC_RESET_L

LPC

LPC_50S

LPC_RESET_L

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Thunderbolt IC Net Properties

PHYSICAL

Thunderbolt/DP Net Properties

PHYSICAL

NET_TYPE

SPACING

Proper differential impedance depends on mDP connector used.

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

Only used on hosts supporting Thunderbolt video-in

Thunderbolt/DP Connector Signal Constraints

Thunderbolt SPI Signal Constraints

DisplayPort Signal Constraints

TABLE_PHYSICAL_ASSIGNMENT symbols must be used to create the assignments.

For 514-0637: R2D nets (SMT pins) = 80D, D2R nets (TH pins) = 100D

NOTE: Thunderbolt high-speed nets are NOT directly assigned to TBTDP_*D physical rules.

Thunderbolt Constraints

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

TBTDP_85D

*

=5x_DIELECTRIC

TBTDP

* ?

=55_OHM_SE =55_OHM_SE

TBT_SPI_55S

=55_OHM_SE

=STANDARD=STANDARD

*

=55_OHM_SE

TBT_SPI

?*

=2x_DIELECTRIC

*

=80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF

TBTDP_80D

=80_OHM_DIFF

TOP,BOTTOM

=7x_DIELECTRIC

?

TBTDP

TBTDP_100D

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_C_P

TBT_A_AUXCH

DP_85D

DISPLAYPORT

DP_B_LSX_ML_N<1>

TBTDP_85D

TBTDP

TBT_A_D2R1_AUXDDC_N

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_C_N

TBT_A_AUXCH

DP_85D

DP_A_LSX_ML_P<1>

DISPLAYPORT

DP_85D

DP_TBTPA_ML_N<3..1:2>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTPA_ML_P<3..1:2>

DP_85D

DISPLAYPORT

DP_TBTPA_ML_C_N<3..1:2>

DP_TBTPA_ML

DP_85D

DP_A_LSX_ML_N<1>

DISPLAYPORT

TBTDP_85D

TBT_A_D2R_C_P<1..0>

TBTDP

TBT_SPI_55S

TBT_SPI_CS_L

TBT_SPI

TBT_SPI_55S

TBT_SPI_MISO

TBT_SPI

TBT_SPI_55S

TBT_SPI_MOSI

TBT_SPI

TBT_SPI_55S

TBT_SPI_CLK

TBT_SPI

DP_85D

DP_TBTSRC_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_TBTSRC_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSRC_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_TBTSRC_ML_C_P<3..0>

DISPLAYPORT

TBTDP_85D

TBTDP

TBT_B_D2R1_AUXDDC_N

DISPLAYPORT

DP_B_LSX_ML_P<1>

DP_85D

DISPLAYPORT

DP_TBTPB_ML_P<3..1:2>

DP_85D

TBTDP

TBT_B_R2D_P<1..0>

TBTDP_85D

DP_85D

DISPLAYPORT

DP_TBTPB_ML_N<3..1:2>

TBTDP_85D

TBTDP

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R

DP_85D

DISPLAYPORT

DP_B_AUXCH_DDC_N

TBTDP

TBT_B_D2R_C_N<1..0>

TBTDP_85D

TBTDP

TBT_B_D2R_P<1..0>

TBT_B_D2R TBTDP_85D

TBTDP_85D

TBTDP

TBT_B_D2R_C_P<1..0>

TBTDP_85D

TBTDP

TBT_B_R2D_N<1..0>

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_N<3..1:2>

DP_TBTPB_ML

TBTDP_85D

TBTDP

TBT_A_R2D_P<1..0>

TBTDP_85DTBT_A_R2D

TBTDP

TBT_A_R2D_C_N<1..0>

TBTDP_85D

TBT_A_D2R_N<1..0>

TBT_A_D2R

TBTDP

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_P

DP_85D

DISPLAYPORT

DP_A_AUXCH_DDC_P

DP_85D

DISPLAYPORT

DP_A_AUXCH_DDC_N

TBTDP_85D

TBTDP

TBT_A_D2R1_AUXDDC_P

TBTDP_85D

TBTDP

TBT_B_R2D_C_N<1..0>

TBT_B_R2D

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_N

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_P<3..1:2>

DP_TBTPB_ML

DP_85D

DP_TBTPA_ML_C_P<3..1:2>

DISPLAYPORTDP_TBTPA_ML

TBTDP_85D

TBTDP

TBT_A_R2D_N<1..0>

TBTDP_85DTBT_A_R2D

TBT_A_R2D_C_P<1..0>

TBTDP

TBTDP_85D

TBT_A_D2R_C_N<1..0>

TBTDP

TBTDP_85D

TBT_A_D2R_P<1..0>

TBT_A_D2R

TBTDP

DP_85D

DISPLAYPORT

DP_B_AUXCH_DDC_P

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_N

DP_85D

DP_TBTPB_AUXCH_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_C_N

TBT_B_AUXCH

TBTDP

TBT_B_D2R_N<1..0>

TBT_B_D2R TBTDP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_C_P

TBT_B_AUXCH

DP_85D

TBTDP

TBT_B_R2D_C_P<1..0>

TBTDP_85DTBT_B_R2D

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SMBus Charger Net Properties

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMC Constraints

SYNC_MASTER=D2_KEPLER

SYNC_DATE=01/13/2012

=STANDARD =STANDARD

0.1 MM 0.1 MM

*

=STANDARD=STANDARD

1TO1_DIFFPAIR

SMBUS_SMC_3_SDA

SMB

SMB_50S

SMBUS_SMC_3_SCL

SMB_50S

SMB

SMBUS_SMC_5_SDA

SMB

SMB_50S

SMBUS_SMC_5_SCL

SMB

SMB_50S

SMBUS_SMC_1_S0_SDA

SMB

SMB_50S

SMBUS_SMC_1_S0_SCL

SMB

SMB_50S

SMBUS_SMC_2_S3_SDA

SMB

SMB_50S

SMBUS_SMC_2_S3_SCL

SMB

SMB_50S

SMBUS_SMC_0_S0_SDA

SMB

SMB_50S

SMBUS_SMC_0_S0_SCL

SMB

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSO_N

1TO1_DIFFPAIR

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

GDDR5 Frame Buffer Signal Constraints

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

Kepler Net Properties

SPACING

NET_TYPE

PHYSICAL

GDDR5 FB B Net Properties

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

GDDR5 FB A Net Properties

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

ELECTRICAL_CONSTRAINT_SET

MUXGFX & DP AUX MUX NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

SPACING

PHYSICAL

NET_TYPE

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

Digital Video Signal Constraints

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

I344

I345

I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

I357

I358

I359

I360

I361

I362

I363

I364

I365

I366

I371

I372

I373

I374

I375

I376

I377

I378

I379

I380

I381

I382

I383

I384

I385

I386

I387

I388

I389

I390

I391

I392

I393

I394

I395

I396

I397

I398

I399

I400

I401

I402

I403

I404

I405

I406

I407

I408

I409

I410

I411

I412

I413

I414

I415

I416

I417

I418

I419

I420

I421

I422

I423

I424

I425

I426

I427

I428

I429

I430

I431

I432

I433

I434

I435

I436

I437

I438

I439

I440

I441

I442

I443

I444

I445

I446

I447

I448

I449

I450

I451

I452

I453

I454

I455

I456

I457

I458

I459

I460

I461

I462

I463

I464

I465

I466

I467

I468

I469

I470

I471

I472

I473

I474

GPU (Kepler) CONSTRAINTS

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

* ?

DISPLAYPORT

=3x_DIELECTRIC

*

?

GDDR5_EDC

=5x_DIELECTRIC

GDDR5_CLK

*

?

=80_OHM_DIFF

GDDR5_80D

*

=80_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

GDDR5_CLK

?

=5x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

TOP,BOTTOM

GDDR5_CMD

?

=5x_DIELECTRIC

GDDR5_DATA

?

TOP,BOTTOM

?

=3x_DIELECTRIC

HDMI

*

GDDR5_EDC

?

=5x_DIELECTRIC

TOP,BOTTOM

=85_OHM_DIFF

DP_85D

=85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

=4x_DIELECTRIC

?

HDMI

TOP,BOTTOM

=3x_DIELECTRIC

GDDR5_CMD

?

*

=3x_DIELECTRIC

GDDR5_DATA

?

*

HDMI_90D

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

?

DISPLAYPORT

=4x_DIELECTRIC

TOP,BOTTOM

=45_OHM_SE=45_OHM_SEGDDR5_45SE

=45_OHM_SE

*

=45_OHM_SE

=STANDARD=STANDARD

GDDR5_45R50SE

*

=50_OHM_SE

=STANDARD

=50_OHM_SE

12.7 MM

=50_OHM_SE

=STANDARD

1:1_DIFFPAIR

PEX_TSTCLK_O_N

1:1_DIFFPAIR

PEX_TSTCLK_O_P

DISPLAYPORT

DP_85D

DP_INT_ML

DP_INT_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_EG_AUXCH_N

DP_85D

DP_TBTSNK1_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_N<3..0>

DP_85D

DISPLAYPORT

DPB_IG_AUX_CH_N

DP_INT_AUXCH DP_85D

DP_TBTSNK0_EG_AUXCH_P

DISPLAYPORT

DP_TBTSNK0_ML_C_P<3..0>

DP_INT_ML

DISPLAYPORT

DP_85D

TBT_A_AUXCH DISPLAYPORT

DP_85D

DP_TBTSNK0_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_C_N<3..0>

TBT_B_AUXCH

DP_TBTSNK1_AUXCH_C_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_85D

DP_TBTSNK0_AUXCH_C_N

DISPLAYPORT

DP_85DDP_INT_AUXCH

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK0_EG_AUXCH_N

DP_85D

DISPLAYPORT

DP_85DDP_INT_AUXCH

DPB_IG_AUX_CH_P

DPA_IG_AUX_CH_N

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_ML_F_N<3..0>

HDMI_EG_DATA_C_P<2..0>

HDMI_DATA

HDMI

HDMI_90D

HDMI

HDMI_CLK

HDMI_EG_CLK_C_P

HDMI_90D

HDMI_EG_DATA_C_N<2..0>

HDMI_90D

HDMI

HDMI_EG_CLK_C_N

HDMI_90D

FB_A0_DQ<23..16>

FB_A0_DQ_BYTE2

GDDR5_45SE GDDR5_DATA

GDDR5_CMD

FB_A1_WCLK_N<0>

FB_A1_WCLK0

GDDR5_80D

FB_A1_WCLK_N<1>

GDDR5_CMD

FB_A1_WCLK1

GDDR5_80D

FB_A1_DQ_BYTE0

GDDR5_45SE GDDR5_DATA

FB_A1_DQ<7..0>

FB_A1_DQ_BYTE1

GDDR5_DATAGDDR5_45SE

FB_A1_DQ<15..8>

GDDR5_EDC

FB_A1_EDC2 GDDR5_45SE

FB_A1_EDC<2>

GDDR5_EDC

GDDR5_45SEFB_A1_EDC3

FB_A1_EDC<3>

GDDR5_DATAGDDR5_45SE

FB_A0_DBI_L0

FB_A0_DBI_L<0>

FB_A0_DQ<7..0>

GDDR5_45SE

FB_A0_DQ_BYTE0

GDDR5_DATA

FB_A1_CMD

GDDR5_45SE

FB_A1_WE_L

GDDR5_CMD

FB_A0_CMD

FB_A0_A<8..0>

GDDR5_45SE

GDDR5_CMD

FB_A1_A<8..0>

GDDR5_45SE

FB_A1_CMD GDDR5_CMD

GDDR5_CMD

FB_A1_CAS_L

GDDR5_45SE

FB_A1_CMD

GDDR5_CMD

GDDR5_45SE

FB_A0_RAS_L

FB_A0_CMD

FB_A0_CLK_P

GDDR5_CLKGDDR5_80DFB_A0_CLK

GDDR5_CMD

FB_A1_ABI_L

FB_A1_CMD

GDDR5_45SE

GDDR5_CLK

FB_A1_CLK_P

FB_A1_CLK GDDR5_80D

GDDR5_CLK

FB_A0_CLK_N

GDDR5_80DFB_A0_CLK

FB_A0_CMD GDDR5_CMD

FB_A0_CAS_L

GDDR5_45SE

FB_A1_CMD GDDR5_CMD

FB_A1_RAS_L

GDDR5_45SE

FB_A1_CLK_N

GDDR5_80DFB_A1_CLK GDDR5_CLK

FB_A0_CMD

FB_A0_WE_L

GDDR5_CMD

GDDR5_45SE

FB_B1_CMD_R

GDDR5_45SE

FB_B1_RESET_L

GDDR5_CMD

FB_B0_DBI_L<3>

GDDR5_DATAGDDR5_45SE

FB_B0_DBI_L3

FB_B1_DBI_L<0>

GDDR5_DATAGDDR5_45SE

FB_B1_DBI_L0

FB_B0_WCLK0

FB_B0_WCLK_P<0>

GDDR5_CMDGDDR5_80D

GDDR5_CMD

FB_B0_CAS_L

FB_B0_CMD

GDDR5_45SE

GDDR5_EDC

FB_B0_EDC1

FB_B0_EDC<1>

GDDR5_45SE

GDDR5_EDC

FB_B1_EDC2

FB_B1_EDC<2>

FB_B1_WCLK_P<0>

FB_B1_WCLK0

GDDR5_CMDGDDR5_80D

GDDR5_45SE

FB_B0_DQ<15..8>

GDDR5_DATA

FB_B0_DQ_BYTE1

FB_B1_CMD GDDR5_CMD

FB_B1_CAS_L

GDDR5_45SE

GDDR5_CMD

FB_B0_A<8..0>

FB_B0_CMD

GDDR5_45SE

FB_B1_A<8..0>

GDDR5_CMDFB_B1_CMD

GDDR5_45SE

GDDR5_80D GDDR5_CLK

FB_B1_CLK_N

FB_B1_CLK

GDDR5_80D GDDR5_CLK

FB_B1_CLK_P

FB_B1_CLK

GDDR5_80D GDDR5_CLK

FB_B0_CLK_N

FB_B0_CLK

FB_B0_CLK_P

GDDR5_80D GDDR5_CLKFB_B0_CLK

GDDR5_CMD

FB_B1_RAS_L

FB_B1_CMD

GDDR5_45SE

FB_B0_DQ<23..16>

GDDR5_45SE GDDR5_DATA

FB_B0_DQ_BYTE2

GDDR5_CMD

FB_B0_RAS_L

FB_B0_CMD

GDDR5_45SE

GDDR5_CMD

FB_B0_ABI_L

FB_B0_CMD

GDDR5_45SE

GDDR5_CMD

FB_B1_ABI_L

FB_B1_CMD

GDDR5_45SE

FB_B0_WCLK1

GDDR5_80D

FB_B0_WCLK_P<1>

GDDR5_CMD

FB_B1_WCLK_N<1>

GDDR5_CMDGDDR5_80D

FB_B1_WCLK1

FB_B0_DQ<31..24>

FB_B0_DQ_BYTE3

GDDR5_45SE GDDR5_DATA

FB_B0_DQ<7..0>

GDDR5_45SE GDDR5_DATA

FB_B0_DQ_BYTE0

FB_B1_WCLK_P<1>

FB_B1_WCLK1

GDDR5_CMDGDDR5_80D

FB_B1_WCLK_N<0>

GDDR5_CMDGDDR5_80D

FB_B1_WCLK0

GDDR5_DATA

FB_B1_DBI_L3

GDDR5_45SE

FB_B1_DBI_L<3>

FB_B0_DBI_L1

GDDR5_DATA

FB_B0_DBI_L<1>

GDDR5_45SE

GDDR5_EDC

FB_B1_EDC3

FB_B1_EDC<3>

FB_B1_EDC1

FB_B1_EDC<1>

GDDR5_45SE

GDDR5_EDC

FB_B0_WCLK_N<1>

FB_B0_WCLK1

GDDR5_CMDGDDR5_80D

GDDR5_45SE

FB_B1_DQ_BYTE3

GDDR5_DATA

FB_B1_DQ<31..24>

DP_TBTSNK0_AUXCH_P

DP_85D

TBT_A_AUXCH DISPLAYPORT

DP_TBTSNK1_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_C_P<3..0>

DP_TBTSNK1_AUXCH_N

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML_P<3..0>

DP_INT_ML

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_P<3..0>

DP_INT_ML

DP_85D

DISPLAYPORT

GPU_CLK27M

GPU_OSC_27M_XTALIN

CLK_SLOW

CLK_SLOW_55S

DP_TBTSNK0_AUXCH_N

DP_85D

DISPLAYPORT

DP_TBTSNK1_AUXCH_P

DP_85D

DISPLAYPORTTBT_B_AUXCH

DP_85D

DISPLAYPORT

DP_INT_ML_N<3..0>

DP_INT_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_INT_ML

DP_INT_EG_AUX_N

DISPLAYPORT

DP_85D

DP_INT_EG_AUX_P

DISPLAYPORT

DP_85DDP_INT_AUXCH

DISPLAYPORT

DP_INT_AUX_N

DP_85D

DP_INT_AUX_P

DP_INT_AUXCH DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_ML_C_N<3..0>

FB_B1_DQ<23..16>

FB_B1_DQ_BYTE2

GDDR5_DATAGDDR5_45SE

DISPLAYPORT

DP_85D

DP_INT_AUX_C_P

DP_INT_AUXCH

DP_INT_AUX_C_N

DISPLAYPORT

DP_85D

CLK_SLOW

CLK_SLOW_55S

GPU_CLK27M

GPU_OSC_27M_XTALOUT

DISPLAYPORT

DP_INT_AUXCH DP_85D

DPA_IG_AUX_CH_P

DISPLAYPORT

DP_85D

DP_INT_EG_ML_N<3..0>

CLK_SLOW_55S

CLK_SLOW

GPU_OSC_27M_XTAL_BUFFOUT

GPU_CLK27M

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML_N<3..0>

GPU_CLK27M

CLK_SLOW_55S

CLK_SLOW

GPU_OSC_27M_SSIN

DP_85D

DP_INT_ML

DISPLAYPORT

DP_INT_ML_F_P<3..0>

DISPLAYPORT

DP_85D

DP_INT_EG_ML_P<3..0>

DP_INT_ML

FB_A1_DQ_BYTE3

GDDR5_45SE GDDR5_DATA

FB_A1_DQ<31..24>

FB_A1_DQ<23..16>

FB_A1_DQ_BYTE2

GDDR5_DATAGDDR5_45SE

FB_A0_DQ<31..24>

GDDR5_DATA

FB_A0_DQ_BYTE3

GDDR5_45SE

GDDR5_CMD

FB_A0_ABI_L

FB_A0_CMD

GDDR5_45SE

GDDR5_EDC

FB_A0_EDC<2>

FB_A0_EDC2 GDDR5_45SE

GDDR5_EDC

FB_A0_EDC<1>

FB_A0_EDC1 GDDR5_45SE

FB_A1_CKE_L

FB_A1_CMD_R

GDDR5_45SE

GDDR5_CMD

FB_A0_CKE_L

FB_A0_CMD_R

GDDR5_CMD

GDDR5_45SE

FB_A0_CS_L

FB_A0_CMD

GDDR5_45SE

GDDR5_CMD

GDDR5_DATA

FB_A1_DBI_L<2>

GDDR5_45SE

FB_A1_DBI_L2

FB_A1_DBI_L<1>

FB_A1_DBI_L1

GDDR5_45SE GDDR5_DATA

FB_A1_DBI_L<0>

GDDR5_DATA

FB_A1_DBI_L0

GDDR5_45SE

FB_A0_RESET_L

FB_A0_CMD_R

GDDR5_45SE

GDDR5_CMD

FB_A0_DQ<15..8>

GDDR5_45SE

FB_A0_DQ_BYTE1

GDDR5_DATA

GDDR5_CMDGDDR5_80D

FB_A1_WCLK0

FB_A1_WCLK_P<0>

GDDR5_80D

FB_A0_WCLK1

GDDR5_CMD

FB_A0_WCLK_N<1>

GDDR5_80D

FB_A0_WCLK1

GDDR5_CMD

FB_A0_WCLK_P<1>

FB_A0_WCLK0

GDDR5_80D GDDR5_CMD

FB_A0_WCLK_N<0>

GDDR5_80D

FB_A0_WCLK0

GDDR5_CMD

FB_A0_WCLK_P<0>

FB_A1_DBI_L<3>

GDDR5_DATAGDDR5_45SE

FB_A1_DBI_L3

GDDR5_DATAGDDR5_45SE

FB_A0_DBI_L2

FB_A0_DBI_L<2>

FB_A0_DBI_L<3>

GDDR5_DATA

FB_A0_DBI_L3

GDDR5_45SE

GDDR5_DATA

FB_A0_DBI_L1

GDDR5_45SE

FB_A0_DBI_L<1>

FB_A1_EDC<1>

GDDR5_EDC

GDDR5_45SEFB_A1_EDC1

GDDR5_EDC

FB_A1_EDC0 GDDR5_45SE

FB_A1_EDC<0>

FB_A0_EDC<3>

GDDR5_EDC

FB_A0_EDC3 GDDR5_45SE

FB_A1_CS_L

GDDR5_CMDFB_A1_CMD

GDDR5_45SE

GDDR5_EDC

FB_A0_EDC<0>

FB_A0_EDC0 GDDR5_45SE

FB_A1_WCLK_P<1>

GDDR5_CMD

FB_A1_WCLK1

GDDR5_80D

FB_A1_RESET_L

FB_A1_CMD_R

GDDR5_45SE

GDDR5_CMD

FB_B0_CMD_R

FB_B0_RESET_L

GDDR5_CMD

GDDR5_45SE

FB_B1_DQ<7..0>

FB_B1_DQ_BYTE0

GDDR5_DATAGDDR5_45SE

FB_B1_DQ<15..8>

GDDR5_DATA

FB_B1_DQ_BYTE1

GDDR5_45SE

FB_B0_WCLK_N<0>

GDDR5_CMDGDDR5_80D

FB_B0_WCLK0

GDDR5_DATA

FB_B1_DBI_L<2>

GDDR5_45SE

FB_B1_DBI_L2

FB_B1_DBI_L1

GDDR5_DATA

FB_B1_DBI_L<1>

GDDR5_45SE

FB_B0_DBI_L2

GDDR5_DATAGDDR5_45SE

FB_B0_DBI_L<2>

GDDR5_DATAGDDR5_45SE

FB_B0_DBI_L<0>

FB_B0_DBI_L0

FB_B0_WE_L

FB_B0_CMD

GDDR5_45SE

GDDR5_CMD

GDDR5_45SEFB_B0_EDC3

FB_B0_EDC<3>

GDDR5_EDC

FB_B1_EDC0

FB_B1_EDC<0>

GDDR5_45SE

GDDR5_EDC

FB_B0_EDC2

GDDR5_EDC

FB_B0_EDC<2>

GDDR5_45SE

GDDR5_CMD

FB_B1_WE_L

FB_B1_CMD

GDDR5_45SE

GDDR5_EDC

FB_B0_EDC<0>

GDDR5_45SEFB_B0_EDC0

FB_B1_CS_L

GDDR5_CMD

GDDR5_45SE

FB_B1_CMD

GDDR5_CMDFB_B0_CMD

FB_B0_CS_L

GDDR5_45SE

GDDR5_CMD

FB_B1_CKE_L

GDDR5_45SE

FB_B1_CMD_R

GDDR5_CMD

FB_B0_CKE_L

GDDR5_45SE

FB_B0_CMD_R

051-9589

4.18.0

107 OF 132

95 OF 99

71 92

81 82

77 83

7

35 83

7

35

18 83

77 83

7

35 77

7

35 83

7

35 77

7

35 83

7

35 83

77 83

18 83

81

7

38 77

7

38 77

7

38 77

7

38 77

73 75

73 76

7

35

7

35 77

7

35 77

7

35

7

35

7

35

77 78

7

35

7

35

7

81

7

81

77 82

7

81

7

81

81 82

73 76

81 82

77 78

18 83

77 82

7

35

77

81

77 82

73 75

73 76

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

D2 Specific Net PropertiesD2 Specific Net Properties

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

Graphics ,SATA Constraint Relaxations

PHYSICAL

(USB_EXTA)

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

(USB_EXTA)

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

Memory Constraint Relaxations

I343

I344

I345

I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

I357

I358

I359

I360

I361

I362

I363

I364

I365

I366

I367

I368

I371

I372

I375

I376

I378

I379

I381

I382

I385

I386

I387

I388

I389

I390

I391

I392

I393

I394

I395

I396

I397

I398

I399

I400

I401

I402

I403

I404

I405

I406

I407

I408

I409

I410

I411

I412

I413

I414

I415

I416

I417

I418

MEM_*_DQ_BYTE*

GND

*

GND_P2MM

SYNC_MASTER=D2_CLEAN

Project Specific Constraints

SYNC_DATE=03/15/2012

CPU_27P4S

0.23 MM 100 MIL

BOTTOM

*

PWR_P2MMSB_POWERCLK_PCIE

GND_P2MM

0.20 MM

1000

*

0.09 MM 100 MILMEM_72D

*

0.09 MM

*

10 mm

PCIE_85D

TOP

500 MILUSB_85D

0.1 MM

CPU_COMP GND_P2MM

GND

*

GND_P2MM

CPU_VCCSENSE

GND

*

GND

*

GND_P2MMCLK_PCIE

GND

GND_P2MM

SATA

*

GND_P2MM

GNDUSB

SATA

PWR_P2MM

*

SB_POWER

PWR_P2MM

USB

*

SB_POWER

0.09 MMMEM_40S

*

100 MIL

=2:1_SPACING

AUDIO

?

*

?

*

=2:1_SPACING

THERM

BOTTOM

0.127 MM

6.35 MMMEM_72D

6.35 MMMEM_85D

TOP

0.1 MM

GND_P2MM

MEM_CLK

GND

*

GND_P2MM

MEM_CMD

GND

*

GND

*

GND_P2MM

PCIE

BGA

CLK_PCIE_90D 100_DIFF_BGA

100_DIFF_BGA

BGA

SATA_90D

100_DIFF_BGA

BGA

DP_85D

LVDS_85D

BGA

LVDS_85D

GND_P2MMMEM_CTRL

*

GND

1000

PWR_P2MM

0.20 MM

*

=STANDARD

*

GND

?

*

?

SENSE

=2:1_SPACING

AUDIODIFF

=1:1_DIFFPAIR

0.1 MM 0.1 MM

10 MM

0.1 MM

*

0.1 MM

=1:1_DIFFPAIR

*

DIFFPAIR

=1:1_DIFFPAIR

LVDS

GND

*

GND_P2MM

=55_OHM_SE

0.2 MM0.2 MM

THERM_55S_CPUIMVPISNS1

*

=1:1_DIFFPAIR

=55_OHM_SE =55_OHM_SE

=55_OHM_SE=55_OHM_SE

=1:1_DIFFPAIR

THERM_1TO1_55S

*

=55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=55_OHM_SE=55_OHM_SE

=1:1_DIFFPAIR

SENSE_1TO1_55S

MEM_DQS

GND_P2MM

GND

*

100 MILMEM_37S

*

0.09 MM

*

100 MILMEM_85D

USB2_LT1_N

USB

USB_85D

USB2_LT1_P

USB

USB_85D

USB2_EXTA_MUXED_N

USB

USB_85D

CONN_USB2_BT_N

USB_85D

USB

SPKRAMP_LIN_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

SPKRAMP_LIN_N

AUDIO

AUDIODIFF

SSM2375SR_N

AUDIO

AUDIODIFF

SPKRCONN_SR_OUT_N

DIFFPAIR

AUDIO

SPKRCONN_L_OUT_P

AUDIO

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

RSUBIN_P

AUDIO_DIFFPAIR

DIFFPAIR

RSUBIN_N

AUDIO

DIFFPAIR

LSUBIN_P

AUDIO_DIFFPAIR

DIFFPAIR

AUDIO

LSUBIN_N

DIFFPAIR

AUDIO

SSM4321SR_P

AUDIO_DIFFPAIR

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

SSM4321SL_P

AUDIO

DIFFPAIR

SSM4321SL_N

AUDIO

DIFFPAIR

SSM4321SR_N

DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

ISNS_LCDBKLT_P

RSPKR_INTIV_RSENSE_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_SPKRAMP_RSUBIN_N

AUDIO

AUD_SPKRAMP_RIN_N

AUDIO

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_SPKRAMP_RIN_P

AUDIO

AUD_SPKRAMP_LSUBIN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUD_SPKRAMP_LSUBIN_N

AUDIO

AUDIODIFF

AUD_SPKRAMP_RSUBIN_P

AUDIO

AUDIO_DIFFPAIR

AUD_MIC_INL_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_MIC_INL_P

AUD_SPKRAMP_LIN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_SPKRAMP_LIN_N

AUDIODIFF

AUDIO

LSPKR_INTIV_RSENSE_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

LSPKR_INTIV_RSENSE_N

AUDIODIFF

AUDIO

ISNS_TBT_R_P

AUDIODIFF

AUDIO

ISNS_TBT_P

AUDIODIFF

AUDIO

ISNS_TBT_R_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

ISNS_TBT_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

RSPKR_INTIV_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

RSPKR_INTIV_N

AUDIO

AUDIODIFF

LSPKR_INTIV_N

AUDIO

AUDIODIFF

RSPKR_INTIV_RSENSE_N

AUDIODIFF

AUDIO

LSPKR_INTIV_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO2_R_N

AUD_LO2_R_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO2_L_N

AUDIO

AUDIODIFF

AUD_LO2_L_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_N

AUD_LO1_R_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_L_N

AUD_LO1_L_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

SPKR_L_RSENSE_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

SPKR_L_RSENSE_P

SPKR_R_RSENSE_N

AUDIO

AUDIODIFF

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

SPKR_R_RSENSE_P

ADC2_ISENSE_N

AUDIODIFF

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

ADC2_ISENSE_P

ADC2_ISENSE_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

ADC2_ISENSE_P

AUDIODIFF

AUDIO

ADC2_VSENSE_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

ADC2_VSENSE_P

AUDIODIFF

AUDIO

ADC1_VSENSE_N

ADC1_VSENSE_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

CPUIMVP_ISNS_N

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_HS_COMPUTING_N

SENSE

SENSE_1TO1_55S

ISNS_HS_COMPUTING_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_HS_GPU_N

SENSE

SENSE_1TO1_55S

ISNS_HS_GPU_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_HS_OTHER_N

SENSE

SENSE_1TO1_55S

ISNS_HS_OTHER_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISNS1G_R_N

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS1G_R_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_1TO1_55S

CPUIMVP_ISNS1G_N

SENSE

SENSE_DIFFPAIR_42

CPUIMVP_ISNS1G_P

SENSE

SENSE_1TO1_55S

SENSE_DIFFPAIR_42

SENSE

SENSE_1TO1_55S

ISNS_PP1V5_S0GPU_R_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_PP1V5_S0GPU_R_P

SENSE

SENSE_1TO1_55S

P1V05_GPU_CS_N

SENSE

SENSE_1TO1_55S

P1V05_GPU_CS_P

SENSE

SENSE_1TO1_55S

ISNS_PP1V8_S0GPU_R_N

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_PP1V8_S0GPU_R_P

ISNS_PP1V8_S0GPU_N

SENSE

SENSE_1TO1_55S

ISNS_PP1V8_S0GPU_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_PP1V0_S0GPU_R_N

SENSE_1TO1_55S

SENSE

ISNS_PP1V0_S0GPU_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

GPUFB_CS_N

GPUFB_CS_P

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_R_P

SENSE

SENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_LCDBKLT_N

SENSE

USB_TPAD_R_N

USB

USB_85D

ISNS_AIRPORT_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_AIRPORT_N

SENSE_1TO1_55S

SENSE

SPKRCONN_S_OUT_P

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

LSPKR_VSENSE_FILT_P

AUDIO_DIFFPAIR

DIFFPAIR

AUDIO

RSPKR_ISENSE_FILT_N

DIFFPAIR

AUDIO

SPKRCONN_S_OUT_N

AUDIO

DIFFPAIR

SPKRCONN_L_OUT_N

AUDIO

DIFFPAIR

SPKRCONN_SR_OUT_P

AUDIO

DIFFPAIR

AUDIO_DIFFPAIR

RSPKR_VSENSE_FILT_N

DIFFPAIR

AUDIO

RSPKR_VSENSE_FILT_P

AUDIO_DIFFPAIR

DIFFPAIR

AUDIO

LSPKR_VSENSE_FILT_N

AUDIO

DIFFPAIR

SPKRCONN_SL_OUT_N

AUDIO

DIFFPAIR

SPKRCONN_SR_OUT_P_R

AUDIO_DIFFPAIR

DIFFPAIR

AUDIO

LSPKR_ISENSE_FILT_N

DIFFPAIR

SPKRCONN_SL_OUT_N_R

AUDIO

DIFFPAIR

CPUVCCIOS0_CS_N

SENSE_1TO1_55S

SENSE

CPUVCCIOISNS_R_P

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

GPUISENS_P

SENSE_1TO1_55S

SENSE

ISNS_1V5_MEM_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_1V5_MEM_P

SENSE_1TO1_55S

SENSE

CPUTHMSNS_D2_P

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

CHGR_CSI_R_N

1TO1_DIFFPAIR

CHGR_CSI_R_P

1TO1_DIFFPAIR

DDR3THMSNS_D1_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_55S

CPUTHMSNS_D2_N

THERM_1TO1_55S

THERM

DDR3THMSNS_D1_N

THERM

THERM_1TO1_55S

USB_LT2_N

USB

USB_85D

USB_LT2_P

USB

USB_85D

USB2_EXTA_MUXED_P

USB_85D

USB

CHGR_CSO_R_N

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

PCIE_CLK100M_AP_CONN_P

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_AP

SENSE_DIFFPAIR

GPUISENS_N

SENSE_1TO1_55S

SENSE

CPUVCCIOISNS_R_N

SENSE_1TO1_55S

SENSE

GPU_TDIODE_P

THERM

SENSE_DIFFPAIR THERM_1TO1_55S

GPUTHMSNS_D_P

THERM

SENSE_DIFFPAIR THERM_1TO1_55S

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

CPUVCCIOS0_CS_P

GPUTHMSNS_D_N

THERM_1TO1_55S

THERM

VCCSAS0_CS_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

VCCSAS0_CS_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

VCCSAISNS_R_P

LSPKR_VSENSE_IN_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

PP3V3_S5

SB_POWER

SPKRCONN_SR_OUT_N_R

DIFFPAIR

AUDIO

SSM2375SL_N

AUDIO

AUDIODIFF

SSM2375SR_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

SPKRCONN_SL_OUT_P_R

AUDIO

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

SPKRCONN_R_OUT_N

DIFFPAIR

LSPKR_ISENSE_FILT_P

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

RSPKR_ISENSE_FILT_P

AUDIO

AUDIO_DIFFPAIR

DIFFPAIR

PP3V3_S0

SB_POWER

USB_TPAD_R_P

USB_85D

USB

AUDIO_DIFFPAIR

AUDIODIFF

LSPKR_ISENSE_RDIVIDE_N

AUDIO

LSPKR_VSENSE_RDIVIDE_P

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

RSPKR_VSENSE_RDIVIDE_P

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_AIRPORT_R_N

THERM_1TO1_55S

THERM

GPU_TDIODE_N

SENSE_1TO1_55S

SENSE

VCCSAISNS_R_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_1V5_MEM_R_P

SENSE

SENSE_1TO1_55S

ISNS_1V5_MEM_R_N

PP1V5_S3RS0_CPUDDR

SB_POWER

AUDIODIFF

AUDIO

RSPKR_VSENSE_RDIVIDE_N

LSPKR_VSENSE_RDIVIDE_N

AUDIODIFF

AUDIO

AUDIODIFF

RSPKR_ISENSE_RDIVIDE_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

RSPKR_ISENSE_RDIVIDE_P

AUDIO_DIFFPAIR

AUDIODIFF

LSPKR_ISENSE_RDIVIDE_P

AUDIO

RSPKR_VSENSE_IN_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

RSPKR_VSENSE_IN_P

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

LSPKR_VSENSE_IN_N

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

SPKRCONN_R_OUT_P

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

CONN_USB2_BT_P

USB

USB_85D

SPKRAMP_RIN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SPKRAMP_RIN_N

AUDIO

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

SSM2375SL_P

SPKRCONN_SL_OUT_P

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

PCIE_CLK100M_AP_CONN_N

CLK_PCIE_90D

CLK_PCIE

ISNS_AIRPORT_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

GND

051-9589

4.18.0

108 OF 132

96 OF 99

57

7

57 59

7

57 59

57

53 58

57

99

53 57

96

46

46 66

99

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98

74 99

99

26 49

96

7

57 59

7

57 59

7

57 59

45 67

45

47

61

61 47

47

61

7

34

45

47 77

47

45 67

47

45 62

45

7 8

7

57 59

7 8

26 49

96

99

47 77

45

8

7

57 59

57

7

57 59

7

34

96

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

15" MBP BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

15" MBP Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

Note: Outer dielectric is 0.058 mm nominal,

Inner dielectric is 0.053 mm nominal.

Stackup-Defined Spacing Rules

PHYSICAL

NET_TYPE

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

SPACING

I1

I10

I11

I12

I13

I14

I15

I16

I17

I18

I19

I2

I20

I21

I22

I23

I24

I25

I26

I27

I28

I29

I3

I30

I31

I32

I33

I34

I35

I36

I37

I38

I39

I4

I40

I41

I42

I43

I44

I45

I46

I47

I48

I49

I5

I50

I53

I54

I55

I56

I57

I58

I59

I6

I60

I61

I62

I67

I68

I69

I7

I70

I8

I9

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

16.2

NO_TYPE,BGA

MM

SYNC_DATE=01/13/2012

SYNC_MASTER=D2_KEPLER

PCB Rule Definitions

Y

0.090 MM

TOP,BOTTOM

0.090 MM

55_OHM_SE

Y

TOP,BOTTOM

45_OHM_SE

0.116 MM 0.116 MM

45_OHM_SE

0.085 MM 0.085 MM

*=STANDARD=STANDARDY

=STANDARD

50_OHM_SE

Y

0.090 MM

TOP,BOTTOM

0.090 MM

3x_DIELECTRIC

ISL3,ISL4,ISL9,ISL10

?

0.159 MM

2x_DIELECTRIC

?

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

0.202 MM

3x_DIELECTRIC

0.303 MM

?

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

4x_DIELECTRIC

?

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

0.404 MM

27P4_OHM_SE

=STANDARD

0.1 MM

Y*

0.190 MM

=STANDARD

27P4_OHM_SE

Y

TOP,BOTTOM

0.265 MM 0.095 MM

37_OHM_SE =STANDARD

0.090 MM

Y=STANDARD

0.120 MM

*=STANDARD

10 MM=50_OHM_SE

*

0 MM0 MM

=50_OHM_SE

Y

DEFAULT

*

STANDARD =DEFAULT=DEFAULT

=DEFAULT

10 MM

=DEFAULT

Y

=STANDARD

=STANDARD55_OHM_SE

=STANDARD

0.076 MM 0.076 MM

Y*

TOP,BOTTOM

0.058 MM

1:1_SPACING

?

0.174 MM

TOP,BOTTOM

3:1_SPACING

?

0.232 MM

TOP,BOTTOM

4:1_SPACING

1X_DIELECTRIC

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

?

0.101 MM

5x_DIELECTRIC

ISL3,ISL4,ISL9,ISL10

?

0.265 MM

ISL3,ISL4,ISL9,ISL10

4x_DIELECTRIC

?

0.212 MM

1x_DIELECTRIC

?

ISL3,ISL4,ISL9,ISL10

0.053 MM

0.174 MM

TOP,BOTTOM

?

3x_DIELECTRIC

4x_DIELECTRIC

0.232 MM

?

TOP,BOTTOM

0.290 MM

?

TOP,BOTTOM

5x_DIELECTRIC

*

DEFAULT

?

0.1 MM

=DEFAULT

*

?

STANDARD

BGA

**

P072_SPACE

?

0.505 MM

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

5x_DIELECTRIC

0.116 MM

2x_DIELECTRIC

TOP,BOTTOM

?

1x_DIELECTRIC

0.058 MM

?

TOP,BOTTOM

5:1_SPACING

0.505 MM

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

?

0.404 MM

4:1_SPACING

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

?

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

?

3:1_SPACING

0.303 MM

ISL3,ISL4,ISL9,ISL10

0.212 MM

4:1_SPACING

?

0.159 MM

?

ISL3,ISL4,ISL9,ISL10

3:1_SPACING

0.265 MM

5:1_SPACING

?

ISL3,ISL4,ISL9,ISL10

2:1_SPACING

?

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

0.202 MM

0.101 MM

?

1:1_SPACING

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

0.116 MM

TOP,BOTTOM

2:1_SPACING

?

TOP,BOTTOM

0.290 MM

?

5:1_SPACING

?

0.106 MM

2:1_SPACING

ISL3,ISL4,ISL9,ISL10

0.053 MM

ISL3,ISL4,ISL9,ISL10

?

1:1_SPACING

50_OHM_SE

0.070 MM

Y

0.070 MM

*

=STANDARD

=STANDARD=STANDARD

ISL3,ISL4,ISL9,ISL10

0.200 MM

0.081 MM

Y

0.081 MM

0.200 MM

90_OHM_DIFF

0.200 MM

0.090 MM

Y

0.099 MM

TOP,BOTTOM

90_OHM_DIFF

0.200 MM

=STANDARD=STANDARD

=STANDARD =STANDARD

72_OHM_DIFF

N

=STANDARD

*

0.200 MM0.200 MM

0.079 MM

Y

0.079 MM

TOP,BOTTOM

100_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

0.200 MM0.200 MM

0.124 MM

Y

0.124 MM

72_OHM_DIFF

0.126 MM

ISL3,ISL4,ISL9,ISL10

0.126 MM

0.096 MM

80_OHM_DIFF

Y

0.096 MM

0.120 MM 0.120 MM

0.140 MM

72_OHM_DIFF

Y

0.140 MM

TOP,BOTTOM

=STANDARD=STANDARD

=STANDARD

85_OHM_DIFF

=STANDARD

* N

=STANDARD

100_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

0.200 MM0.200 MM

0.065 MM

Y

0.065 MM

0.200 MM0.200 MM

0.065 MM

100_OHM_DIFF

Y

0.065 MM

ISL2,ISL11

0.200 MM0.200 MM

0.081 MM

90_OHM_DIFF

Y

0.081 MM

ISL2,ISL11

*=STANDARD=STANDARD

=STANDARD =STANDARD

N

=STANDARD

90_OHM_DIFF

=STANDARD

1:1_DIFFPAIR

=STANDARD

0.1 MM 0.1 MM

=STANDARD

* Y

0.180 MM0.180 MM

0.110 MM

85_OHM_DIFF

Y

0.110 MM

TOP,BOTTOM

=STANDARD=STANDARD

=STANDARD =STANDARD

100_OHM_DIFF

N

=STANDARD

*

0.180 MM

ISL3,ISL4,ISL9,ISL10

0.180 MM

0.089 MM

85_OHM_DIFF

0.089 MM

Y

0.125 MM

ISL9,ISL10

0.075 MM

Y

100_DIFF_BGA

0.075 MM

0.125 MM

ISL3,ISL4

0.075 MM

Y

100_DIFF_BGA

0.125 MM 0.125 MM

0.075 MM

*

=100_OHM_DIFF

100_DIFF_BGA

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

0.200 MM 0.200 MM

0.124 MM

72_OHM_DIFF

Y

0.124 MM

ISL2,ISL11

80_OHM_DIFF

0.160 MM

0.120 MM

Y

TOP,BOTTOM

0.160 MM

0.120 MM

0.126 MM0.126 MM

0.096 MM

80_OHM_DIFF

Y

0.096 MM

ISL2,ISL11

*

0.2 MM

?

BGA_P2MM

*

BGA_P1MM

?

0.1 MM

P072_SPACE

0.071 MM

*

?

=STANDARD

=STANDARD =STANDARD

80_OHM_DIFF

N*

=STANDARD

0.180 MM 0.180 MM

0.089 MM

Y

0.089 MM

ISL2,ISL11

85_OHM_DIFF

0.095 MM

Y

37_OHM_SE

TOP,BOTTOM

0.165 MM

?

2x_DIELECTRIC

ISL3,ISL4,ISL9,ISL10

0.106 MM

=STANDARD =STANDARD

40_OHM_SE

Y*

=STANDARD

0.090 MM0.105 MM

40_OHM_SE

Y

0.145 MM 0.095 MM

TOP,BOTTOM

THERM_1TO1_55S

THERM

TBT_THERMD_N

THERM

SPKR_THMSNS_D2_N

THERM_1TO1_55S

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

SPKR_THMSNS_D2_P

CPUIMVP_ISUMG_R_N

THERM_1TO1_55S

THERM

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

ISNS_CPU_DDR_R_P

ISNS_LCD_PANEL_N

THERM_1TO1_55S

THERM

USB_85D

USB3

USB3_EXTA_RX_RC_N

USB_85D

USB3

USB3_EXTA_RX_RC_P

USB_85D

USB3_EXTB_RX_RC_P

USB3

USB_85D

USB3_EXTB_RX_RC_N

USB3

P1V0S0_VSNS

CLK_25M

P1V5_GPU_VSNS

CLK_25M

THERM_1TO1_55SSENSE_DIFFPAIR

THERM

CPUIMVP_ISUMG_R_P

THERM_1TO1_55S

VDDCIS0_CS_N

THERM

SENSE_DIFFPAIR

AUDIO_DIFFPAIR

AUDIODIFF

ADC1_ISENSE_P

AUDIO

ADC1_ISENSE_N

AUDIODIFF

AUDIO

THERM_55S_CPUIMVPISNS1

CPUIMVP_ISNS1_P

THERM

SENSE_DIFFPAIR_42

THERM_55S_CPUIMVPISNS1

THERM

CPUIMVP_ISNS3_N

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISUM_R_P

THERM

CPUIMVP_ISNS1_N

THERM_55S_CPUIMVPISNS1

USB3_EXTB_TX_C_N

USB_85D

USB3

USB_85D

USB3_EXTB_TX_C_P

USB3

USB3_EXTA_TX_C_N

USB_85D

USB3

USB_85D

USB3_EXTA_TX_F_N

USB3

THERM_1TO1_55S

THERM

GFXIMVP6_VSEN_P

SENSE_DIFFPAIR

THERM_1TO1_55S

THERM

GFXIMVP6_VSEN_N

SENSE_DIFFPAIR

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

TBT_THERMD_P

THERM

ISNS_P1V5R1V35_CPUDDR_P

THERM_1TO1_55SSENSE_DIFFPAIR

GFXIMVP_ISNS2_P

THERM

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

THERM_1TO1_55S

CPUIMVP_ISUM_R_N

THERM_55S_CPUIMVPISNS1

SENSE_DIFFPAIR

THERM

CPUIMVP_ISNS3_P

THERM

THERM_1TO1_55S

CPUIMVP_ISNS2_N

CPUIMVP_ISNS2_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_55S

CPUIMVP_ISNS2G_N

THERM

THERM_1TO1_55S

SENSE_DIFFPAIR

CPUIMVP_ISNS2G_P

THERM

THERM_1TO1_55S

X29THMSNS_D2_P

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

VDDCIS0_CS_P

USB3_EXTA_TX_C_P

USB_85D

USB3

USB_85D

USB3_EXTA_RX_F_N

USB3

USB_85D

USB3_EXTA_TX_F_P

USB3

THERM_1TO1_55S

THERM

X29THMSNS_D2_N

THERM

THERM_1TO1_55S

SPKRL_THMSNS_D2_N

SENSE_DIFFPAIR THERM_1TO1_55S

SPKRL_THMSNS_D2_P

THERM

THERM_1TO1_55S

P1V05_GPU_PEX_IOVDD_SNS_N

THERM

USB_85D

USB3_EXTA_RX_F_P

USB3

GFXIMVP_ISNS2_N

THERM_1TO1_55S

THERM

GFXIMVP_ISNS1_N

THERM_1TO1_55S

THERM

GFXIMVP_ISNS1_P

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

THERM

PCH_VCCIOSENSE_P

ISNS_LCD_PANEL_P

SENSE_DIFFPAIR THERM_1TO1_55S

THERM

ISNS_CPU_DDR_R_N

THERM_1TO1_55S

THERM

ISNS_P1V5R1V35_CPUDDR_N

THERM_1TO1_55S

THERM

ISNS_SSD_P

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

THERM_1TO1_55S

THERM

ISNS_SSD_N

ISNS_SSD_R_P

THERM_1TO1_55S

THERM

SENSE_DIFFPAIR

THERM_1TO1_55S

THERM

ISNS_SSD_R_N

THERM_1TO1_55S

THERM

PCHVCCIOS0_CS_P

SENSE_DIFFPAIR

THERM_1TO1_55S

PCHVCCIOS0_CS_N

THERM

THERM_1TO1_55S

THERM

PCH_VCCIOSENSE_N

40_OHM_SE

THERM

SENSE_DIFFPAIR

GPUVCORE_SENSE_P

THERM

THERM_1TO1_55S

GPU_FBVDDQ_SENSE

40_OHM_SE

THERM

SENSE_DIFFPAIR

GPUVCORE_SENSE_N

THERM_1TO1_55S

GPU_FBGND_SENSE

THERM

THERM_1TO1_55S

P1V05_GPU_PEX_IOVDD_SNS_P

THERM

051-9589

4.18.0

109 OF 132

97 OF 99

47

46

98

40

38

46

46 65 66

46 66

46

46 66

7

38

7

38

40

47

80

46

46 65 66

46 66

46 65 66

46 66

40

74 79

80

87

98

39 99

99

87 99

87

79 80

73 74

79 80

73 74

74 79

BI

IN

OUT

V+

V-

THRM

IN

OUT

IN-

IN+ REF

V+

GND

IN

NC

V-

V+

+

-

IN

V+

+

-

V- V+

+

-

V-

NC

COM

GND

THRM

DVDDAVDD

AD0

AD1

SDA

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

VREF

REFCOMP

PAD

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VCRP

Gain: 130x

CPU DDR CURRENT SENSE

EDP CURRENT: 5.0A

GAIN: 100X

ILDC

EDP Current: 2.846A

IG2C

IC3C

GAIN: 237X

GPU 1.0V CURRENT SENSE

EDP CURRENT: 1.0A

LCD PANEL CURRENT SENSE

ISNS_CPU_DDR_R_P

ISNS_CPU_DDR_R_N

ISNS_CPU_DDR_IOUT

=PP3V3_S0_ISNS

=PP5V_S3_DEBUG_ISNS

NO_TEST=TRUE

CPU_VCORE_RMCN

NO_TEST=TRUE

VSNS_CPU_VCORE_RMC_OUT

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.25MM

PP5V_S3_DEBUG_ADC_DVDD_FILT

CPU_VCORE_RMC_DIV

NO_TEST=TRUE

COMP_CPU_VCORE_RMC

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_RMC

PP5V_S0_RMC_FLT

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 MM

PP5V_S3_DEBUG_ADC_AVDD_FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.25MM

ADC_VREF

1V0_GPU_IOUT

ADC_CH4

CPU_VCORE_C

ISNS_PP1V0_S0GPU_R_P

=PP5V_S3_DEBUG_ADC_AVDD

=PPVCORE_S0_CPU

ADC_CH2

NC_ISNS_LCD_PANELN

ADC_CH1

ADC_CH3

=I2C_SMC_ADCS_SCL

LCD_DRV_IOUT

=PP5V_S3_DEBUG_ADC_DVDD

ADC_REFCOMP

ADC_SCL

ADC_SDA

=PP1V05_S0_RMC

NC_ISNS_LCD_PANELP

=I2C_SMC_ADCS_SDA

=PP5V_S3_DEBUG_ISNS

P1V05_GPU_CS_P

P1V05_GPU_CS_N

ADC_CH3

ADC_CH2

ADC_CH1

CPU_VCORE_RMCP

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_RMC_R

=PP5V_S0_RMC

ISNS_PP1V0_S0GPU_R_N

ADC_CH4

NO_TEST=TRUE

1V05_S0_RMC_DIV

SYNC_DATE=03/05/2012

SYNC_MASTER=D2_SEAN

DEBUG SENSORS AND ADC

44

SENSOR_NONPROD:Y

2.2UF

20%

6.3V

CERM

402-LF

X5R

SENSOR_NONPROD:Y

603

20%

6.3V

10UF

SENSOR_NONPROD:Y

1/16W

33

5%

402

MF-LF

PLACE_NEAR=U4900.E4:10mm

X5R

SENSOR_NONPROD:Y

10UF

20%

6.3V

603

0.1UF

SENSOR_NONPROD:Y

10V

20%

402

CERM

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.F1:10mm

MF-LF

402

1/16W

5%

33

0.1UF

SENSOR_NONPROD:Y

402

CERM

10V

20%

X5R

SENSOR_NONPROD:Y

6.3V

603

20%

10UF

SENSOR_NONPROD:Y

LTC2309

QFN

0.1UF

SENSOR_NONPROD:Y

402

20%

10V

CERM

402

10%

CERM

16V

PLACE_NEAR=UD000.4:5MM

0.22UF

SENSOR_NONPROD:Y

0402

SENSOR_NONPROD:Y

120OHM-0.3A

10%

0.1UF

0402

X7R-CERM

16V

SENSOR_NONPROD:Y

SOT23

OPA365

SENSOR_NONPROD:Y

OPA365

SOT23

NC_ISNS_P1V5R1V35_CPUDDRN

69

7

81

7

SENSOR_NONPROD:Y

SC70-5

OPA333DCKG4

81

7

SENSOR_NONPROD:Y

1%

402

1/16W

MF-LF

PLACE_NEAR=UD000.22:5MM

4.53K

0.1UF

SENSOR_NONPROD:Y

402

20%

10V

CERM

SENSOR_NONPROD:Y

X5R

20%

6.3V

0.22UF

402

PLACE_NEAR=UD000.22:5MM

SENSOR_NONPROD:Y

SC70

INA214

NC_ISNS_P1V5R1V35_CPUDDRP

69

7

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

1/16W

1%

402

MF-LF

1M

SENSOR_NONPROD:Y

MF-LF

1/16W

7.68K

402

1%

SENSOR_NONPROD:Y

1%

1/16W

7.68K

MF-LF

402

SENSOR_NONPROD:Y

SIGNAL_MODEL=EMPTY

1/16W

402

1M

1%

MF-LF

0.1UF

SENSOR_NONPROD:Y

CERM

10V

402

20%

SENSOR_NONPROD:Y

402

PLACE_NEAR=UD000.4:5MM

4.53K

1%

1/16W

MF-LF

X5R

SENSOR_NONPROD:Y

20%

402

6.3V

PLACE_NEAR=UD000.4:5MM

0.22UF

SENSOR_NONPROD:Y

1/16W

MF-LF

1%

4.22K

402

SENSOR_NONPROD:Y

1/16W

MF-LF

402

1M

1%

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

402

1/16W

4.22K

1%

MF-LF

SENSOR_NONPROD:Y

402

1%

MF-LF

1/16W

1M

SIGNAL_MODEL=EMPTY

0402

X7R-CERM

10V

20%

SENSOR_NONPROD:Y

0.1UF

SENSOR_NONPROD:Y

402

1/16W

MF-LF

1%

4.53K

PLACE_NEAR=UD000. 3:5MM

DFN

OPA2333

SENSOR_NONPROD:Y

98

10%

SENSOR_NONPROD:Y

CERM

10V

402

0.22UF

SENSOR_NONPROD:Y

402

MF-LF

1%

4.53K

1/16W

SENSOR_NONPROD:Y

BAT54XV2T1

SOD-523

SENSOR_NONPROD:Y

1%

MF-LF

402

1K

1/16W

SIGNAL_MODEL=EMPTY

SENSOR_NONPROD:Y

0.1%

10.2

402

1/16W

TF

SENSOR_NONPROD:Y

BAT54XV2T1

SOD-523

10%

0.1UF

0402

X7R-CERM

16V

SENSOR_NONPROD:Y

10UF

20%

6.3V

0402

CERM-X5R

SENSOR_NONPROD:Y

1/16W

TF

402

10.2

0.1%

SENSOR_NONPROD:Y

10

5%

MF-LF

402

1/16W

PLACE_NEAR=RD305.1:5MM

10%

X5R

16V

SENSOR_NONPROD:Y

402

1UF

PLACE_NEAR=RD305.1:5MM

SENSOR_NONPROD:Y

402

MF-LF

1/16W

100

5%

SENSOR_NONPROD:Y

1/16W

MF

1.00K

402

0.1%

SENSOR_NONPROD:Y

402

1/16W

0.1%

MF

11K

SENSOR_NONPROD:Y

MF

1.00K

402

1/16W

0.1%

SENSOR_NONPROD:Y

MF

11K

0.1%

1/16W

402

SENSOR_NONPROD:Y

CERM-X5R

6.3V

20%

0402

10UF

PLACE_NEAR=CD010.1:2MM

SM

45 15 13

8

10%

0.1UF

0402

X7R-CERM

16V

SENSOR_NONPROD:Y

10

5%

1/16W

402

MF-LF

SENSOR_NONPROD:Y

1/16W

5%

MF-LF

402

10

44

CD007

1

2

UD000

14

15

12

13

22

23

24

1

2

3

4

5

6

21

9

10

11

18

19

20

8

16

17

25

7

CD001

1

2

CD004

1

2

RD007

1 2

CD002

1

2

CD000

1

2

RD002

1 2

CD012

1

2

CD006

1

2

RD018

1 2

RD003

1 2

CD005

1

2

XWD000

12

CD003

1

2

RD004

1

2

RD006

1

2

RD011

1

2

RD001

1

2

RD000

1 2

CD010

1 2

RD008

1 2

RD005

1 2

CD009

1

2

CD008

1

2

DD000

A K

RD009

1 2

RD021

1 2

DD001

A K

RD020

1 2

CD020

1

2

UD080

3

2

1

9

4

8

RD044

1 2

CD043

1

2

RD043

1 2

RD040

1 2

RD042

1

2

RD041

1 2

CD081

1

2

RD085

1 2

CD082

1

2

RD084

1 2

RD081

1 2

RD082

1 2

RD083

1

2

UD070

2

5

4

6

1

3

CD071

1

2

CD070

1

2

RD071

1 2

UD082

1

3

4

2

5

UD001

4

3

2

5

1

UD002

4

3

2

5

1

CD018

1

2

LD000

1 2

CD042

1

2

051-9589

4.18.0

130 OF 132

98 OF 99

97

99 45

8

98

8

98

96

8

98

8

98

8

96 74

98

8

96

98

V+

V-

THRM

OUT

IN-

IN+ REF

V+

GND

V-

V+

+

-

V-

V+

+

-

V+

REFIN+

IN- OUT

GND

IN

V-

V+

+

-

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

CPU VCCSA VOLTAGE SENSE

SMC_ADC20

VC2C

LCD BKLT Voltage Sense

SSD CURRENT SENSE

EDP Current: 0.715A

Sense Resistor 0.005 Ohm

PCH VCORE CURRENT SENSE

TBT (T29) CURRENT SENSE

Gain: 130x

EDP Current: 1.06A

EDP CURRENT: 5A

IAPC

GAIN: 130X

IHDC

SMC_ADC6

IBLC

GAIN: 100X

IG3C

SMC_ADC22

SMC_ADC19

Gain:200x

GAIN: 383X

SMC_ADC23

IHSC

SMC_ADC17

Rsense(R8380)=0.002 Ohm

VBLC

SMC_ADC16

EDP CURRENT:6.0A

SMC_ADC21

ISBC

EDP Current: 7.8A

EDP CURRENT: 3.0 A

SENSE RESISTOR 0.001 OHM

GPU FB (1.35V/1.5V) CURRENT SENSE

GAIN: 1074.11X

LCD BKLT Current Sense

X29 AIRPORT CURRENT SENSE

1/16W

1%

402

MF-LF

1M

SIGNAL_MODEL=EMPTY

OPA2333

DFN

PLACE_NEAR=U4900.H2:5MM

4.53K

1%

1/16W

MF-LF

402

X5R

0.22UF

20%

6.3V

402

PLACE_NEAR=U4900.H2:5MM

10V

CERM

20%

0.1UF

402

SENSOR_NONPROD:Y

402

MF-LF

1%

1/16W

2.61K

SENSOR_NONPROD:Y

2.61K

402

1%

MF-LF

1/16W

1M

1/16W

402

1%

SIGNAL_MODEL=EMPTY

MF-LF

1/16W

MF-LF

402

1M

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.B8:5MM

SENSOR_NONPROD:Y

402

4.53K

1%

1/16W

MF-LF

10V

402

0.1UF

CERM

20%

SENSOR_NONPROD:Y

SC70

SENSOR_NONPROD:Y

INA214

SENSOR_NONPROD:Y

X5R

0.22UF

PLACE_NEAR=U4900.G1:5MM

402

6.3V

20%

SENSOR_NONPROD:Y

10V

20%

0.1UF

CERM

402

SENSOR_NONPROD:Y

1/16W

4.53K

MF-LF

1%

PLACE_NEAR=U4900.G1:5MM

402

CRITICAL

0612

1W

1%

MF

0.001

10V

0.1UF

CERM

20%

402

4.53K

402

1/16W

1%

MF-LF

PLACE_NEAR=UD4900.A8:5MM

OPA333DCKG4

SC70-5

OPA333DCKG4

SC70-5

SM

PLACE_NEAR=U4900.G2:5MM

MF-LF

1%

1/16W

402

4.53K

100K

MF-LF

1/16W

402

1%

MF-LF

1/16W

402

4.64K

SENSOR_NONPROD:Y

CRITICAL

SC70

INA210

SENSOR_NONPROD:Y

X5R

0.22UF

PLACE_NEAR=U4900.A7:5MM

402

20%

6.3V

SENSOR_NONPROD:Y

PLACE_NEAR=U4900.A7:5mm

1%

1/16W

MF-LF

402

4.53K

SENSOR_NONPROD:Y

10V

0.1UF

402

20%

CERM

87 97

SC70-5

SENSOR_NONPROD:Y

X5R

PLACE_NEAR=U4900.A8:5MM

6.3V

20%

0.22UF

402

X5R

0.22UF

PLACE_NEAR=U4900.A3:5MM

6.3V

20%

402

SENSOR_NONPROD:Y

X5R

0.22UF

402

20%

6.3V

PLACE_NEAR=U4900.B8:5MM

PLACE_NEAR=U4900.G2:5MM

X5R

0.22UF

20%

402

6.3V

201

931

1/20W

MF

1%

201

931

1/20W

MF

1%

201

1/20W

1M

1%

MF

201

1M

1%

1/20W

MF

402

4.53K

1/16W

MF-LF

PLACE_NEAR=U4900.7:5MM

1%

0.22UF

X5R

402

PLACE_NEAR=U4900.B7:5MM

6.3V

20%

PLACE_NEAR=R7140.1:2MM

SM

VCCSA_VSENSE_IN

SM

1%

SIGNAL_MODEL=EMPTY

1/16W

MF-LF

402

1M

1/16W

402

1%

MF-LF

7.68K

1/16W

1%

MF-LF

402

1/16W

MF-LF

1%

1M

SIGNAL_MODEL=EMPTY

10V

20%

402

0.1UF

CERM

PLACE_NEAR=U4900.A3:5MM

4.53K

MF-LF

1%

1/16W

402

7.68K

MF-LF

1%

1/16W

402

1/16W

1%

MF-LF

7.68K

SIGNAL_MODEL=EMPTY

1/16W

1%

MF-LF

1M

402

116S0114

SENSOR_NONPROD:N

RES,MTL FILM,100K,5,1/16W,0402,SMD,LF

4

SYNC_DATE=01/13/2012

SMC12 SENSORS EXTENDED

SYNC_MASTER=D2_KEPLER

NC_ISNS_LCDBKLTP

ISNS_TBT_N

ISNS_TBT_R_N

=PP5V_S3_ISNS

ISNS_TBT_P

ISNS_TBT_R_P

GND_SMC_AVSS

PCHVCCIOS0_CS_P

GND_SMC_AVSS

ISNS_SSD_IOUT

ISNS_PP1V5_S0GPU_R_P

PPVOUT_S0_LCDBKLT

P1V5_S0GPU_IOUT

SMC_PCH_CORE_ISENSE

GND_SMC_AVSS

NC_ISNS_LCDBKLTN

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

ISNS_PP1V5_S0GPU_R_N

SMC_LCDBKLT_VSENSE

PCHVCCIOS0_CS_N

VOUT_S0_LCDBKLT_XW

SMC_TBT_ISENSE

ISNS_SSD_N

SMC_GPU_P1V35_ISENSE

ISNS_SSD_R_P

=PP3V3_S0_ISNS

GPUFB_CS_N

SMC_X29_ISENSE

GND_SMC_AVSS

GPUFB_CS_P

ISNS_SSD_R_N

LCDBKLT_IOUT

SMC_SSD_ISENSE

=PPVCCSA_S0_REG

=PP3V3_S0_ISNS

=PP1V05_S0_P1V05TBTFET

=PP1V05_S0_P1V05TBTFET_R

ISNS_TBT_IOUT

=PP3V3_S3_ISNS

ISNS_AIRPORT_R_P

=PP5V_S3_ISNS

PCH_CORE_IOUT

GND_SMC_AVSS

ISNS_SSD_P

PPBUS_SW_LCDBKLT_PWR

=PPBUS_SW_BKL

PP3V3_WLAN_F

PP3V3_WLAN_R

NC_ISNS_AIRPORTP

NC_ISNS_AIRPORTN

VOUT_S0_LCDBKLT_DIV

SMC_CPU_SA_VSENSE

SENSOR_NONPROD:Y

1%

SIGNAL_MODEL=EMPTY

ISNS_AIRPORT_R_N

ISNS_AIRPORT_IOUT

OPA333DCKG4

CD201,CD222,CD231

RD262

1

2

RD261

1 2

RD260

1 2

RD263

1 2

CD258

1

2

RD264

1 2

RD282

1 2

RD281

1 2

RD283

1

2

RD284

1 2

UD280

3

2

1

9

4

8

RD285

1 2

CD281

1

2

CD282

1

2

RD231

1 2

RD230

1 2

RD232

1

2

RD233

1 2

RD234

1 2

CD230

1

2

UD200

2

5

4

6

1

3

CD201

1

2

CD200

1

2

RD201

1 2

RD259

2

1

4

3

CD251

1

2

RD255

1 2

UD240

1

3

4

2

5

UD250

1

3

4

2

5

XWD250

1 2

RD258

1 2

RD256

1

2

RD257

1

2

UD220

2

5

4

6

1

3

CD222

1

2

RD223

1 2

CD221

1

2

UD230

1

3

4

2

5

CD250

1

2

CD240

1

2

CD231

1

2

CD252

1

2

RD251

1 2

RD252

1 2

RD254

1 2

RD253

1

2

RD214

1 2

CD211

1

2

XWD245

12

XWD200

1

2

XWD235

1

2

051-9589

4.18.0

132 OF 132

99 OF 99

7

96

8

99

96

41 42 45 46 99

96

7

81 86

42

41 42 45 46 99

7

41 42 45 46

99

42

96

42

39 97

42

97

8

45 98 99

74 96

42

41 42 45 46 99

74 96

97

42

8

62

8

45 98 99

8

37

8

96

8

99

41 42 45 46 99

39 97

86

8

34

7

42

www.qdzbwx.com

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