STM32F0xxx Cortex M0 Programming Manual
Programming%20Manual
stm32f0%20Programming%20Manual
User Manual:
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Page Count: 91
- Table 1. Applicable products
- 1 About this document
- 2 The STM32 Cortex-M0 processor
- 2.1 Programmers model
- 2.1.1 Processor modes
- 2.1.2 Stacks
- 2.1.3 Core registers
- Figure 2. Processor core registers
- Table 3. Core register set summary
- Figure 3. APSR, IPSR and EPSR bit assignments
- Table 4. PSR register combinations and attributes
- Table 5. APSR bit definitions
- Table 6. IPSR bit definitions
- Table 7. EPSR bit definitions
- Figure 4. PRIMASK register bit assignments
- Table 8. PRIMASK register bit definitions
- Figure 5. CONTROL register bit assignments
- Table 9. CONTROL register bit definitions
- 2.1.4 Exceptions and interrupts
- 2.1.5 Data types
- 2.1.6 The Cortex microcontroller software interface standard (CMSIS)
- 2.2 Memory model
- 2.3 Exception model
- 2.4 Fault handling
- 2.5 Power management
- 2.1 Programmers model
- 3 The STM32 Cortex-M0 instruction set
- 3.1 Instruction set summary
- 3.2 CMSIS intrinsic functions
- 3.3 About the instruction descriptions
- 3.4 Memory access instructions
- 3.5 General data processing instructions
- 3.6 Branch and control instructions
- 3.7 Miscellaneous instructions
- 4 Core peripherals
- 4.1 About the STM32 Cortex-M0 core peripherals
- 4.2 Nested vectored interrupt controller (NVIC)
- Table 25. NVIC register summary
- 4.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
- 4.2.2 Interrupt set-enable register (ISER)
- 4.2.3 Interrupt clear-enable register (ICER)
- 4.2.4 Interrupt set-pending register (ISPR)
- 4.2.5 Interrupt clear-pending register (ICPR)
- 4.2.6 Interrupt priority register (IPR0-IPR7)
- 4.2.7 Level-sensitive and pulse interrupts
- 4.2.8 NVIC design hints and tips
- 4.2.9 NVIC register map
- 4.3 System control block (SCB)
- Table 30. Summary of the system control block registers
- 4.3.1 CPUID base register (CPUID)
- 4.3.2 Interrupt control and state register (ICSR)
- 4.3.3 Application interrupt and reset control register (AIRCR)
- 4.3.4 System control register (SCR)
- 4.3.5 Configuration and control register (CCR)
- 4.3.6 System handler priority registers (SHPRx)
- 4.3.7 SCB usage hints and tips
- 4.3.8 SCB register map
- 4.4 SysTick timer (STK)
- 5 Revision history