STM32F37xxx Advanced ARM® Based 32 Bit MCUs STM32F373XX Reference Manual
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- 1 Documentation conventions
- 2 System architecture and memory overview
- 3 Embedded Flash memory
- 3.1 Flash main features
- 3.2 Flash memory functional description
- 3.3 Memory protection
- 3.4 Flash interrupts
- 3.5 Flash register description
- 3.5.1 Flash access control register (FLASH_ACR)
- 3.5.2 Flash key register (FLASH_KEYR)
- 3.5.3 Flash option key register (FLASH_OPTKEYR)
- 3.5.4 Flash status register (FLASH_SR)
- 3.5.5 Flash control register (FLASH_CR)
- 3.5.6 Flash address register (FLASH_AR)
- 3.5.7 Option byte register (FLASH_OBR)
- 3.5.8 Write protection register (FLASH_WRPR)
- 3.6 Flash register map
- 4 Option byte description
- 5 Cyclic redundancy check calculation unit (CRC)
- 6 Power control (PWR)
- 7 Reset and clock control (RCC)
- 7.1 Reset
- 7.2 Clocks
- Figure 11. Clock tree part 1
- Figure 12. Clock tree part 2
- 7.2.1 HSE clock
- 7.2.2 HSI clock
- 7.2.3 PLL
- 7.2.4 LSE clock
- 7.2.5 LSI clock
- 7.2.6 System clock (SYSCLK) selection
- 7.2.7 Clock security system (CSS)
- 7.2.8 ADC clock
- 7.2.9 SDADC clock
- 7.2.10 RTC clock
- 7.2.11 Watchdog clock
- 7.2.12 Clock-out capability
- 7.2.13 Internal/external clock measurement using TIM14
- 7.3 Low-power modes
- 7.4 RCC registers
- 7.4.1 Clock control register (RCC_CR)
- 7.4.2 Clock configuration register (RCC_CFGR)
- 7.4.3 Clock interrupt register (RCC_CIR)
- 7.4.4 APB2 peripheral reset register (RCC_APB2RSTR)
- 7.4.5 APB1 peripheral reset register (RCC_APB1RSTR)
- 7.4.6 AHB peripheral clock enable register (RCC_AHBENR)
- 7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR)
- 7.4.8 APB1 peripheral clock enable register (RCC_APB1ENR)
- 7.4.9 RTC domain control register (RCC_BDCR)
- 7.4.10 Control/status register (RCC_CSR)
- 7.4.11 AHB peripheral reset register (RCC_AHBRSTR)
- 7.4.12 Clock configuration register 2 (RCC_CFGR2)
- 7.4.13 Clock configuration register 3 (RCC_CFGR3)
- 7.4.14 RCC register map
- 8 General-purpose I/Os (GPIO)
- 8.1 Introduction
- 8.2 GPIO main features
- 8.3 GPIO functional description
- Figure 15. Basic structure of an I/O port bit
- Figure 16. Basic structure of a five-volt tolerant I/O port bit
- Table 19. Port bit configuration table
- 8.3.1 General-purpose I/O (GPIO)
- 8.3.2 I/O pin alternate function multiplexer and mapping
- 8.3.3 I/O port control registers
- 8.3.4 I/O port data registers
- 8.3.5 I/O data bitwise handling
- 8.3.6 GPIO locking mechanism
- 8.3.7 I/O alternate function input/output
- 8.3.8 External interrupt/wakeup lines
- 8.3.9 Input configuration
- 8.3.10 Output configuration
- 8.3.11 Alternate function configuration
- 8.3.12 Analog configuration
- 8.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 8.3.14 Using the GPIO pins in the RTC supply domain
- 8.4 GPIO registers
- 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A..F)
- 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..F)
- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..F)
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..F)
- 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..F)
- 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..F)
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..F)
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A, B, and D)
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E)
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..F)
- 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..F)
- 8.4.12 GPIO register map
- 9 System configuration controller (SYSCFG)
- 9.1 SYSCFG registers
- 9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 9.1.7 SYSCFG register maps
- 9.1 SYSCFG registers
- 10 Direct memory access controller (DMA)
- 10.1 Introduction
- 10.2 DMA main features
- 10.3 DMA implementation
- 10.4 DMA functional description
- 10.5 DMA registers
- 10.5.1 DMA interrupt status register (DMA_ISR)
- 10.5.2 DMA interrupt flag clear register (DMA_IFCR)
- 10.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number)
- 10.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
- 10.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
- 10.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
- 10.5.7 DMA register map
- 11 Interrupts and events
- 11.1 Nested vectored interrupt controller (NVIC)
- 11.2 Extended interrupts and events controller (EXTI)
- 11.3 EXTI registers
- 12 Analog-to-digital converter (ADC)
- 12.1 ADC introduction
- 12.2 ADC main features
- 12.3 ADC functional description
- 12.4 Calibration
- 12.5 Data alignment
- 12.6 Channel-by-channel programmable sample time
- 12.7 Conversion on external trigger
- 12.8 DMA request
- 12.9 Temperature sensor and internal reference voltage
- 12.10 Battery voltage monitoring
- 12.11 ADC interrupts
- 12.12 ADC registers
- 12.12.1 ADC status register (ADC_SR)
- 12.12.2 ADC control register 1 (ADC_CR1)
- 12.12.3 ADC control register 2 (ADC_CR2)
- 12.12.4 ADC sample time register 1 (ADC_SMPR1)
- 12.12.5 ADC sample time register 2 (ADC_SMPR2)
- 12.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 12.12.7 ADC watchdog high threshold register (ADC_HTR)
- 12.12.8 ADC watchdog low threshold register (ADC_LTR)
- 12.12.9 ADC regular sequence register 1 (ADC_SQR1)
- 12.12.10 ADC regular sequence register 2 (ADC_SQR2)
- 12.12.11 ADC regular sequence register 3 (ADC_SQR3)
- 12.12.12 ADC injected sequence register (ADC_JSQR)
- 12.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 12.12.14 ADC regular data register (ADC_DR)
- 12.12.15 ADC register map
- 13 Sigma-delta analog-to-digital converter (SDADC)
- 13.1 Introduction
- 13.2 SDADC main features
- 13.3 SDADC pins
- 13.4 SDADC clock
- 13.5 SDADC functional description
- Figure 35. Single SDADC block diagram
- 13.5.1 SDADC on-off control
- 13.5.2 Power down and Standby low-power modes
- 13.5.3 SDADC clock
- 13.5.4 Channel selection
- 13.5.5 Differential and single-ended modes
- 13.5.6 Configuring the analog inputs
- 13.5.7 Launching calibration and determining the offset values
- 13.5.8 Launching conversions
- 13.5.9 Continuous and fast continuous modes
- 13.5.10 Request precedence
- 13.5.11 Launching conversions with deterministic timing
- 13.5.12 Reference voltage
- 13.5.13 Analog input signal ranges
- 13.5.14 Input impedance of SDADC analog input and VREFSD reference voltage
- 13.6 SDADC registers
- 13.6.1 Register write protection
- 13.6.2 SDADC control register 1 (SDADC_CR1)
- 13.6.3 SDADC control register 2 (SDADC_CR2)
- 13.6.4 SDADC interrupt and status register (SDADC_ISR)
- 13.6.5 SDADC interrupt and status clear register (SDADC_CLRISR)
- 13.6.6 SDADC injected channel group selection register (SDADC_JCHGR)
- 13.6.7 SDADC configuration 0 register (SDADC_CONF0R)
- 13.6.8 SDADC configuration 1 register (SDADC_CONF1R)
- 13.6.9 SDADC configuration 2 register (SDADC_CONF2R)
- 13.6.10 SDADC channel configuration register 1 (SDADC_CONFCHR1)
- 13.6.11 SDADC channel configuration register 2 (SDADC_CONFCHR2)
- 13.6.12 SDADC data register for injected group (SDADC_JDATAR)
- 13.6.13 SDADC data register for the regular channel (SDADC_RDATAR)
- 13.6.14 SDADC1 and SDADC2 injected data register (SDADC_JDATA12R)
- 13.6.15 SDADC1 and SDADC2 regular data register (SDADC_RDATA12R)
- 13.6.16 SDADC1 and SDADC3 injected data register (SDADC_JDATA13R)
- 13.6.17 SDADC1 and SDADC3 regular data register (SDADC_RDATA13R)
- 13.6.18 SDADC register map
- 14 Digital-to-analog converter (DAC1 and DAC2)
- 14.1 Introduction
- 14.2 DAC1/2 main features
- 14.3 DAC output buffer enable
- 14.4 DAC channel enable
- 14.5 Single mode functional description
- 14.6 Dual-mode functional description
- 14.7 Noise generation
- 14.8 Triangle-wave generation
- 14.9 DMA request
- 14.10 DAC registers
- 14.10.1 DAC control register (DAC_CR)
- 14.10.2 DAC software trigger register (DAC_SWTRIGR)
- 14.10.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 14.10.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1)
- 14.10.5 DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1)
- 14.10.6 DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2)
- 14.10.7 DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2)
- 14.10.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 14.10.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 14.10.10 Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD)
- 14.10.11 Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD)
- 14.10.12 DAC channel1 data output register (DAC_DOR1)
- 14.10.13 DAC channel2 data output register (DAC_DOR2)
- 14.10.14 DAC status register (DAC_SR)
- 14.10.15 DAC register map
- 15 Comparator (COMP)
- 16 General-purpose timers (TIM2 to TIM5, TIM19)
- 16.1 TIM2 to TIM5/TIM19 introduction
- 16.2 TIM2 to TIM5/TIM19 main features
- 16.3 TIM2 to TIM5/TIM19 functional description
- 16.3.1 Time-base unit
- 16.3.2 Counter modes
- Figure 56. Counter timing diagram, internal clock divided by 1
- Figure 57. Counter timing diagram, internal clock divided by 2
- Figure 58. Counter timing diagram, internal clock divided by 4
- Figure 59. Counter timing diagram, internal clock divided by N
- Figure 60. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 61. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 62. Counter timing diagram, internal clock divided by 1
- Figure 63. Counter timing diagram, internal clock divided by 2
- Figure 64. Counter timing diagram, internal clock divided by 4
- Figure 65. Counter timing diagram, internal clock divided by N
- Figure 66. Counter timing diagram, Update event when repetition counter is not used
- Figure 67. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 68. Counter timing diagram, internal clock divided by 2
- Figure 69. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 70. Counter timing diagram, internal clock divided by N
- Figure 71. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 72. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 16.3.3 Clock selection
- 16.3.4 Capture/compare channels
- 16.3.5 Input capture mode
- 16.3.6 PWM input mode
- 16.3.7 Forced output mode
- 16.3.8 Output compare mode
- 16.3.9 PWM mode
- 16.3.10 One-pulse mode
- 16.3.11 Clearing the OCxREF signal on an external event
- 16.3.12 Encoder interface mode
- 16.3.13 Timer input XOR function
- 16.3.14 Timers and external trigger synchronization
- 16.3.15 Timer synchronization
- 16.3.16 Debug mode
- 16.4 TIM2 to TIM5/TIM19 registers
- 16.4.1 TIMx control register 1 (TIMx_CR1)
- 16.4.2 TIMx control register 2 (TIMx_CR2)
- 16.4.3 TIMx slave mode control register (TIMx_SMCR)
- 16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 16.4.5 TIMx status register (TIMx_SR)
- 16.4.6 TIMx event generation register (TIMx_EGR)
- 16.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 16.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 16.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 16.4.10 TIMx counter (TIMx_CNT)
- 16.4.11 TIMx prescaler (TIMx_PSC)
- 16.4.12 TIMx auto-reload register (TIMx_ARR)
- 16.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 16.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 16.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 16.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 16.4.17 TIMx DMA control register (TIMx_DCR)
- 16.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 16.5 TIMx register map
- 17 General-purpose timers (TIM12/13/14)
- 17.1 TIM12/13/14 introduction
- 17.2 TIM12/13/14 main features
- 17.3 TIM13/TIM14 main features
- 17.4 TIM12/13/14 functional description
- 17.4.1 Time-base unit
- 17.4.2 Counter modes
- Figure 103. Counter timing diagram, internal clock divided by 1
- Figure 104. Counter timing diagram, internal clock divided by 2
- Figure 105. Counter timing diagram, internal clock divided by 4
- Figure 106. Counter timing diagram, internal clock divided by N
- Figure 107. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 108. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 17.4.3 Clock selection
- 17.4.4 Capture/compare channels
- 17.4.5 Input capture mode
- 17.4.6 PWM input mode (only for TIM12)
- 17.4.7 Forced output mode
- 17.4.8 Output compare mode
- 17.4.9 PWM mode
- 17.4.10 One-pulse mode (only for TIM12)
- 17.4.11 TIM12 external trigger synchronization
- 17.4.12 Timer synchronization (TIM12)
- 17.4.13 Debug mode
- 17.5 TIM12 registers
- 17.5.1 TIM12 control register 1 (TIMx_CR1)
- 17.5.2 TIM12 slave mode control register (TIMx_SMCR)
- 17.5.3 TIM12 Interrupt enable register (TIMx_DIER)
- 17.5.4 TIM12 status register (TIMx_SR)
- 17.5.5 TIM12 event generation register (TIMx_EGR)
- 17.5.6 TIM12 capture/compare mode register 1 (TIMx_CCMR1)
- 17.5.7 TIM12 capture/compare enable register (TIMx_CCER)
- 17.5.8 TIM12 counter (TIMx_CNT)
- 17.5.9 TIM12 prescaler (TIMx_PSC)
- 17.5.10 TIM12 auto-reload register (TIMx_ARR)
- 17.5.11 TIM12 capture/compare register 1 (TIMx_CCR1)
- 17.5.12 TIM12 capture/compare register 2 (TIMx_CCR2)
- 17.5.13 TIM12 register map
- 17.6 TIM13/14 registers
- 17.6.1 TIM13/14 control register 1 (TIMx_CR1)
- 17.6.2 TIM13/14 Interrupt enable register (TIMx_DIER)
- 17.6.3 TIM13/14 status register (TIMx_SR)
- 17.6.4 TIM13/14 event generation register (TIMx_EGR)
- 17.6.5 TIM13/14 capture/compare mode register 1 (TIMx_CCMR1)
- 17.6.6 TIM13/14 capture/compare enable register (TIMx_CCER)
- 17.6.7 TIM13/14 counter (TIMx_CNT)
- 17.6.8 TIM13/14 prescaler (TIMx_PSC)
- 17.6.9 TIM13/14 auto-reload register (TIMx_ARR)
- 17.6.10 TIM13/14 capture/compare register 1 (TIMx_CCR1)
- 17.6.11 TIM14 option register (TIM14_OR)
- 17.6.12 TIM13/14 register map
- 18 General-purpose timers (TIM15/16/17)
- 18.1 TIM15/16/17 introduction
- 18.2 TIM15 main features
- 18.3 TIM16 and TIM17 main features
- 18.4 TIM15/16/17 functional description
- 18.4.1 Time-base unit
- 18.4.2 Counter modes
- Figure 126. Counter timing diagram, internal clock divided by 1
- Figure 127. Counter timing diagram, internal clock divided by 2
- Figure 128. Counter timing diagram, internal clock divided by 4
- Figure 129. Counter timing diagram, internal clock divided by N
- Figure 130. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 131. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 18.4.3 Repetition counter
- 18.4.4 Clock selection
- 18.4.5 Capture/compare channels
- 18.4.6 Input capture mode
- 18.4.7 PWM input mode (only for TIM15)
- 18.4.8 Forced output mode
- 18.4.9 Output compare mode
- 18.4.10 PWM mode
- 18.4.11 Complementary outputs and dead-time insertion
- 18.4.12 Using the break function
- 18.4.13 One-pulse mode
- 18.4.14 TIM15 and external trigger synchronization (only for TIM15)
- 18.4.15 Timer synchronization
- 18.4.16 Debug mode
- 18.5 TIM15 registers
- 18.5.1 TIM15 control register 1 (TIM15_CR1)
- 18.5.2 TIM15 control register 2 (TIM15_CR2)
- 18.5.3 TIM15 slave mode control register (TIM15_SMCR)
- 18.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 18.5.5 TIM15 status register (TIM15_SR)
- 18.5.6 TIM15 event generation register (TIM15_EGR)
- 18.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 18.5.8 TIM15 capture/compare enable register (TIM15_CCER)
- 18.5.9 TIM15 counter (TIM15_CNT)
- 18.5.10 TIM15 prescaler (TIM15_PSC)
- 18.5.11 TIM15 auto-reload register (TIM15_ARR)
- 18.5.12 TIM15 repetition counter register (TIM15_RCR)
- 18.5.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 18.5.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 18.5.15 TIM15 break and dead-time register (TIM15_BDTR)
- 18.5.16 TIM15 DMA control register (TIM15_DCR)
- 18.5.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 18.5.18 TIM15 register map
- 18.6 TIM16&TIM17 registers
- 18.6.1 TIM16&TIM17 control register 1 (TIMx_CR1)
- 18.6.2 TIM16&TIM17 control register 2 (TIMx_CR2)
- 18.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER)
- 18.6.4 TIM16&TIM17 status register (TIMx_SR)
- 18.6.5 TIM16&TIM17 event generation register (TIMx_EGR)
- 18.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1)
- 18.6.7 TIM16&TIM17 capture/compare enable register (TIMx_CCER)
- 18.6.8 TIM16&TIM17 counter (TIMx_CNT)
- 18.6.9 TIM16&TIM17 prescaler (TIMx_PSC)
- 18.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR)
- 18.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR)
- 18.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1)
- 18.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR)
- 18.6.14 TIM16&TIM17 DMA control register (TIMx_DCR)
- 18.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR)
- 18.6.16 TIM16&TIM17 register map
- 19 Infrared interface (IRTIM)
- 20 Basic timers (TIM6/7/18)
- 20.1 Introduction
- 20.2 TIM6/7/18 main features
- 20.3 TIM6/7/18 functional description
- 20.3.1 Time-base unit
- 20.3.2 Counting mode
- Figure 155. Counter timing diagram, internal clock divided by 1
- Figure 156. Counter timing diagram, internal clock divided by 2
- Figure 157. Counter timing diagram, internal clock divided by 4
- Figure 158. Counter timing diagram, internal clock divided by N
- Figure 159. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
- Figure 160. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 20.3.3 Clock source
- 20.3.4 Debug mode
- 20.4 TIM6/7/18 registers
- 20.4.1 TIM6/7/18 control register 1 (TIMx_CR1)
- 20.4.2 TIM6/7/18 control register 2 (TIMx_CR2)
- 20.4.3 TIM6/7/18 DMA/Interrupt enable register (TIMx_DIER)
- 20.4.4 TIM6/7/18 status register (TIMx_SR)
- 20.4.5 TIM6/7/18 event generation register (TIMx_EGR)
- 20.4.6 TIM6/7/18 counter (TIMx_CNT)
- 20.4.7 TIM6/7/18 prescaler (TIMx_PSC)
- 20.4.8 TIM6/7/18 auto-reload register (TIMx_ARR)
- 20.4.9 TIM6/7/18 register map
- 21 Independent watchdog (IWDG)
- 22 System window watchdog (WWDG)
- 23 Real-time clock (RTC)
- 23.1 Introduction
- 23.2 RTC main features
- 23.3 RTC functional description
- 23.3.1 RTC block diagram
- 23.3.2 GPIOs controlled by the RTC
- 23.3.3 Clock and prescalers
- 23.3.4 Real-time clock and calendar
- 23.3.5 Programmable alarms
- 23.3.6 Periodic auto-wakeup
- 23.3.7 RTC initialization and configuration
- 23.3.8 Reading the calendar
- 23.3.9 Resetting the RTC
- 23.3.10 RTC synchronization
- 23.3.11 RTC reference clock detection
- 23.3.12 RTC smooth digital calibration
- 23.3.13 Time-stamp function
- 23.3.14 Tamper detection
- 23.3.15 Calibration clock output
- 23.3.16 Alarm output
- 23.4 RTC low-power modes
- 23.5 RTC interrupts
- 23.6 RTC registers
- 23.6.1 RTC time register (RTC_TR)
- 23.6.2 RTC date register (RTC_DR)
- 23.6.3 RTC control register (RTC_CR)
- 23.6.4 RTC initialization and status register (RTC_ISR)
- 23.6.5 RTC prescaler register (RTC_PRER)
- 23.6.6 RTC wakeup timer register (RTC_WUTR)
- 23.6.7 RTC alarm A register (RTC_ALRMAR)
- 23.6.8 RTC alarm B register (RTC_ALRMBR)
- 23.6.9 RTC write protection register (RTC_WPR)
- 23.6.10 RTC sub second register (RTC_SSR)
- 23.6.11 RTC shift control register (RTC_SHIFTR)
- 23.6.12 RTC timestamp time register (RTC_TSTR)
- 23.6.13 RTC timestamp date register (RTC_TSDR)
- 23.6.14 RTC time-stamp sub second register (RTC_TSSSR)
- 23.6.15 RTC calibration register (RTC_CALR)
- 23.6.16 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 23.6.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 23.6.18 RTC alarm B sub second register (RTC_ALRMBSSR)
- 23.6.19 RTC backup registers (RTC_BKPxR)
- 23.6.20 RTC register map
- 24 Inter-integrated circuit (I2C) interface
- 24.1 Introduction
- 24.2 I2C main features
- 24.3 I2C implementation
- 24.4 I2C functional description
- 24.4.1 I2C block diagram
- 24.4.2 I2C clock requirements
- 24.4.3 Mode selection
- 24.4.4 I2C initialization
- 24.4.5 Software reset
- 24.4.6 Data transfer
- 24.4.7 I2C slave mode
- Figure 172. Slave initialization flowchart
- Figure 173. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0
- Figure 174. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1
- Figure 175. Transfer bus diagrams for I2C slave transmitter
- Figure 176. Transfer sequence flowchart for slave receiver with NOSTRETCH=0
- Figure 177. Transfer sequence flowchart for slave receiver with NOSTRETCH=1
- Figure 178. Transfer bus diagrams for I2C slave receiver
- 24.4.8 I2C master mode
- Figure 179. Master clock generation
- Table 71. I2C-SMBUS specification clock timings
- Figure 180. Master initialization flowchart
- Figure 181. 10-bit address read access with HEAD10R=0
- Figure 182. 10-bit address read access with HEAD10R=1
- Figure 183. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes
- Figure 184. Transfer sequence flowchart for I2C master transmitter for N>255 bytes
- Figure 185. Transfer bus diagrams for I2C master transmitter
- Figure 186. Transfer sequence flowchart for I2C master receiver for N≤255 bytes
- Figure 187. Transfer sequence flowchart for I2C master receiver for N >255 bytes
- Figure 188. Transfer bus diagrams for I2C master receiver
- 24.4.9 I2C_TIMINGR register configuration examples
- 24.4.10 SMBus specific features
- 24.4.11 SMBus initialization
- 24.4.12 SMBus: I2C_TIMEOUTR register configuration examples
- 24.4.13 SMBus slave mode
- Figure 190. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC
- Figure 191. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
- Figure 192. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC
- Figure 193. Bus transfer diagrams for SMBus slave receiver (SBC=1)
- Figure 194. Bus transfer diagrams for SMBus master transmitter
- Figure 195. Bus transfer diagrams for SMBus master receiver
- 24.4.14 Wakeup from Stop mode on address match
- 24.4.15 Error conditions
- 24.4.16 DMA requests
- 24.4.17 Debug mode
- 24.5 I2C low-power modes
- 24.6 I2C interrupts
- 24.7 I2C registers
- 24.7.1 Control register 1 (I2C_CR1)
- 24.7.2 Control register 2 (I2C_CR2)
- 24.7.3 Own address 1 register (I2C_OAR1)
- 24.7.4 Own address 2 register (I2C_OAR2)
- 24.7.5 Timing register (I2C_TIMINGR)
- 24.7.6 Timeout register (I2C_TIMEOUTR)
- 24.7.7 Interrupt and status register (I2C_ISR)
- 24.7.8 Interrupt clear register (I2C_ICR)
- 24.7.9 PEC register (I2C_PECR)
- 24.7.10 Receive data register (I2C_RXDR)
- 24.7.11 Transmit data register (I2C_TXDR)
- 24.7.12 I2C register map
- 25 Universal synchronous asynchronous receiver transmitter (USART)
- 25.1 Introduction
- 25.2 USART main features
- 25.3 USART extended features
- 25.4 USART implementation
- 25.5 USART functional description
- Figure 197. USART block diagram
- 25.5.1 USART character description
- 25.5.2 USART transmitter
- 25.5.3 USART receiver
- 25.5.4 USART baud rate generation
- 25.5.5 Tolerance of the USART receiver to clock deviation
- 25.5.6 USART auto baud rate detection
- 25.5.7 Multiprocessor communication using USART
- 25.5.8 Modbus communication using USART
- 25.5.9 USART parity control
- 25.5.10 USART LIN (local interconnection network) mode
- 25.5.11 USART synchronous mode
- 25.5.12 USART Single-wire Half-duplex communication
- 25.5.13 USART Smartcard mode
- 25.5.14 USART IrDA SIR ENDEC block
- 25.5.15 USART continuous communication in DMA mode
- 25.5.16 RS232 hardware flow control and RS485 driver enable using USART
- 25.5.17 Wakeup from Stop mode using USART
- 25.6 USART low-power modes
- 25.7 USART interrupts
- 25.8 USART registers
- 25.8.1 Control register 1 (USART_CR1)
- 25.8.2 Control register 2 (USART_CR2)
- 25.8.3 Control register 3 (USART_CR3)
- 25.8.4 Baud rate register (USART_BRR)
- 25.8.5 Guard time and prescaler register (USART_GTPR)
- 25.8.6 Receiver timeout register (USART_RTOR)
- 25.8.7 Request register (USART_RQR)
- 25.8.8 Interrupt and status register (USART_ISR)
- 25.8.9 Interrupt flag clear register (USART_ICR)
- 25.8.10 Receive data register (USART_RDR)
- 25.8.11 Transmit data register (USART_TDR)
- 25.8.12 USART register map
- 26 Serial peripheral interface / inter-IC sound (SPI/I2S)
- 26.1 Introduction
- 26.2 SPI main features
- 26.3 I2S main features
- 26.4 SPI/I2S implementation
- 26.5 SPI functional description
- 26.5.1 General description
- 26.5.2 Communications between one master and one slave
- 26.5.3 Standard multi-slave communication
- 26.5.4 Multi-master communication
- 26.5.5 Slave select (NSS) pin management
- 26.5.6 Communication formats
- 26.5.7 Configuration of SPI
- 26.5.8 Procedure for enabling SPI
- 26.5.9 Data transmission and reception procedures
- 26.5.10 SPI status flags
- 26.5.11 SPI error flags
- 26.5.12 NSS pulse mode
- 26.5.13 TI mode
- 26.5.14 CRC calculation
- 26.6 SPI interrupts
- 26.7 I2S functional description
- 26.7.1 I2S general description
- 26.7.2 Supported audio protocols
- Figure 239. I2S Philips protocol waveforms (16/32-bit full accuracy)
- Figure 240. I2S Philips standard waveforms (24-bit frame)
- Figure 241. Transmitting 0x8EAA33
- Figure 242. Receiving 0x8EAA33
- Figure 243. I2S Philips standard (16-bit extended to 32-bit packet frame)
- Figure 244. Example of 16-bit data frame extended to 32-bit channel frame
- Figure 245. MSB Justified 16-bit or 32-bit full-accuracy length
- Figure 246. MSB justified 24-bit frame length
- Figure 247. MSB justified 16-bit extended to 32-bit packet frame
- Figure 248. LSB justified 16-bit or 32-bit full-accuracy
- Figure 249. LSB justified 24-bit frame length
- Figure 250. Operations required to transmit 0x3478AE
- Figure 251. Operations required to receive 0x3478AE
- Figure 252. LSB justified 16-bit extended to 32-bit packet frame
- Figure 253. Example of 16-bit data frame extended to 32-bit channel frame
- Figure 254. PCM standard waveforms (16-bit)
- Figure 255. PCM standard waveforms (16-bit extended to 32-bit packet frame)
- 26.7.3 Start-up description
- 26.7.4 Clock generator
- 26.7.5 I2S master mode
- 26.7.6 I2S slave mode
- 26.7.7 I2S status flags
- 26.7.8 I2S error flags
- 26.7.9 DMA features
- 26.8 I2S interrupts
- 26.9 SPI and I2S registers
- 26.9.1 SPI control register 1 (SPIx_CR1)
- 26.9.2 SPI control register 2 (SPIx_CR2)
- 26.9.3 SPI status register (SPIx_SR)
- 26.9.4 SPI data register (SPIx_DR)
- 26.9.5 SPI CRC polynomial register (SPIx_CRCPR)
- 26.9.6 SPI Rx CRC register (SPIx_RXCRCR)
- 26.9.7 SPI Tx CRC register (SPIx_TXCRCR)
- 26.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR)
- 26.9.9 SPIx_I2S prescaler register (SPIx_I2SPR)
- 26.9.10 SPI/I2S register map
- 27 Touch sensing controller (TSC)
- 27.1 Introduction
- 27.2 TSC main features
- 27.3 TSC functional description
- 27.3.1 TSC block diagram
- 27.3.2 Surface charge transfer acquisition overview
- 27.3.3 Reset and clocks
- 27.3.4 Charge transfer acquisition sequence
- 27.3.5 Spread spectrum feature
- 27.3.6 Max count error
- 27.3.7 Sampling capacitor I/O and channel I/O mode selection
- 27.3.8 Acquisition mode
- 27.3.9 I/O hysteresis and analog switch control
- 27.4 TSC low-power modes
- 27.5 TSC interrupts
- 27.6 TSC registers
- 27.6.1 TSC control register (TSC_CR)
- 27.6.2 TSC interrupt enable register (TSC_IER)
- 27.6.3 TSC interrupt clear register (TSC_ICR)
- 27.6.4 TSC interrupt status register (TSC_ISR)
- 27.6.5 TSC I/O hysteresis control register (TSC_IOHCR)
- 27.6.6 TSC I/O analog switch control register (TSC_IOASCR)
- 27.6.7 TSC I/O sampling control register (TSC_IOSCR)
- 27.6.8 TSC I/O channel control register (TSC_IOCCR)
- 27.6.9 TSC I/O group control status register (TSC_IOGCSR)
- 27.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8)
- 27.6.11 TSC register map
- 28 Controller area network (bxCAN)
- 28.1 Introduction
- 28.2 bxCAN main features
- 28.3 bxCAN general description
- 28.4 bxCAN operating modes
- 28.5 Test mode
- 28.6 Behavior in Debug mode
- 28.7 bxCAN functional description
- 28.8 bxCAN interrupts
- 28.9 CAN registers
- 29 Universal serial bus full-speed device interface (USB)
- 29.1 Introduction
- 29.2 USB main features
- 29.3 USB implementation
- 29.4 USB functional description
- 29.5 Programming considerations
- 29.6 USB registers
- 30 HDMI-CEC controller (HDMI-CEC)
- 30.1 Introduction
- 30.2 HDMI-CEC controller main features
- 30.3 HDMI-CEC functional description
- 30.4 Arbitration
- 30.5 Error handling
- 30.6 HDMI-CEC interrupts
- 30.7 HDMI-CEC registers
- 31 Debug support (DBG)
- 31.1 Overview
- 31.2 Reference ARM documentation
- 31.3 SWJ debug port (serial wire and JTAG)
- 31.4 Pinout and debug port pins
- 31.5 STM32F37xxx JTAG TAP connection
- 31.6 ID codes and locking mechanism
- 31.7 JTAG debug port
- 31.8 SW debug port
- 31.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 31.10 Core debug
- 31.11 Capability of the debugger host to connect under system reset
- 31.12 FPB (Flash patch breakpoint)
- 31.13 DWT (data watchpoint trigger)
- 31.14 ITM (instrumentation trace macrocell)
- 31.15 ETM (Embedded trace macrocell)
- 31.16 MCU debug component (DBGMCU)
- 31.17 TPIU (trace port interface unit)
- 31.17.1 Introduction
- 31.17.2 TRACE pin assignment
- 31.17.3 TPUI formatter
- 31.17.4 TPUI frame synchronization packets
- 31.17.5 Transmission of the synchronization frame packet
- 31.17.6 Synchronous mode
- 31.17.7 Asynchronous mode
- 31.17.8 TRACECLKIN connection inside the STM32F37xxx
- 31.17.9 TPIU registers
- 31.17.10 Example of configuration
- 31.18 DBG register map
- 32 Device electronic signature
- 33 Revision history