STM32F405/415, STM32F407/417, STM32F427/437 And STM32F429/439 Advanced Arm® Based 32 Bit MCUs Reference Manual STM32F4[05,15,07,17,27,37,29,39]xx
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- 1 Documentation conventions
- 2 Memory and bus architecture
- 3 Embedded Flash memory interface
- 3.1 Introduction
- 3.2 Main features
- 3.3 Embedded Flash memory in STM32F405xx/07xx and STM32F415xx/17xx
- 3.4 Embedded Flash memory in STM32F42xxx and STM32F43xxx
- Table 6. Flash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx)
- Table 7. 1 Mbyte Flash memory single bank vs dual bank organization (STM32F42xxx and STM32F43xxx)
- Table 8. 1 Mbyte single bank Flash memory organization (STM32F42xxx and STM32F43xxx)
- Table 9. 1 Mbyte dual bank Flash memory organization (STM32F42xxx and STM32F43xxx)
- 3.5 Read interface
- 3.6 Erase and program operations
- 3.7 Option bytes
- 3.8 One-time programmable bytes
- 3.9 Flash interface registers
- 3.9.1 Flash access control register (FLASH_ACR) for STM32F405xx/07xx and STM32F415xx/17xx
- 3.9.2 Flash access control register (FLASH_ACR) for STM32F42xxx and STM32F43xxx
- 3.9.3 Flash key register (FLASH_KEYR)
- 3.9.4 Flash option key register (FLASH_OPTKEYR)
- 3.9.5 Flash status register (FLASH_SR) for STM32F405xx/07xx and STM32F415xx/17xx
- 3.9.6 Flash status register (FLASH_SR) for STM32F42xxx and STM32F43xxx
- 3.9.7 Flash control register (FLASH_CR) for STM32F405xx/07xx and STM32F415xx/17xx
- 3.9.8 Flash control register (FLASH_CR) for STM32F42xxx and STM32F43xxx
- 3.9.9 Flash option control register (FLASH_OPTCR) for STM32F405xx/07xx and STM32F415xx/17xx
- 3.9.10 Flash option control register (FLASH_OPTCR) for STM32F42xxx and STM32F43xxx
- 3.9.11 Flash option control register (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx
- 3.9.12 Flash interface register map
- 4 CRC calculation unit
- 5 Power controller (PWR)
- 5.1 Power supplies
- 5.2 Power supply supervisor
- 5.3 Low-power modes
- Entering low-power mode
- Exiting low-power mode
- 5.3.1 Slowing down system clocks
- 5.3.2 Peripheral clock gating
- 5.3.3 Sleep mode
- 5.3.4 Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)
- 5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)
- 5.3.6 Standby mode
- 5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes
- 5.4 Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)
- 5.5 Power control registers (STM32F42xxx and STM32F43xxx)
- 5.6 PWR register map
- 6 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
- 6.1 Reset
- 6.2 Clocks
- 6.3 RCC registers
- 6.3.1 RCC clock control register (RCC_CR)
- 6.3.2 RCC PLL configuration register (RCC_PLLCFGR)
- 6.3.3 RCC clock configuration register (RCC_CFGR)
- 6.3.4 RCC clock interrupt register (RCC_CIR)
- 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
- 6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)
- 6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 6.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR)
- 6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
- 6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- 6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)
- 6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)
- 6.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)
- 6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)
- 6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)
- 6.3.20 RCC Backup domain control register (RCC_BDCR)
- 6.3.21 RCC clock control & status register (RCC_CSR)
- 6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)
- 6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
- 6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR)
- 6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
- 6.3.26 RCC register map
- 7 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
- 7.1 Reset
- 7.2 Clocks
- 7.3 RCC registers
- 7.3.1 RCC clock control register (RCC_CR)
- 7.3.2 RCC PLL configuration register (RCC_PLLCFGR)
- 7.3.3 RCC clock configuration register (RCC_CFGR)
- 7.3.4 RCC clock interrupt register (RCC_CIR)
- 7.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 7.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 7.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
- 7.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)
- 7.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 7.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 7.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 7.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
- 7.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- 7.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 7.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)
- 7.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)
- 7.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)
- 7.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)
- 7.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)
- 7.3.20 RCC Backup domain control register (RCC_BDCR)
- 7.3.21 RCC clock control & status register (RCC_CSR)
- 7.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)
- 7.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
- 7.3.24 RCC register map
- 8 General-purpose I/Os (GPIO)
- 8.1 GPIO introduction
- 8.2 GPIO main features
- 8.3 GPIO functional description
- 8.3.1 General-purpose I/O (GPIO)
- 8.3.2 I/O pin multiplexer and mapping
- 8.3.3 I/O port control registers
- 8.3.4 I/O port data registers
- 8.3.5 I/O data bitwise handling
- 8.3.6 GPIO locking mechanism
- 8.3.7 I/O alternate function input/output
- 8.3.8 External interrupt/wakeup lines
- 8.3.9 Input configuration
- 8.3.10 Output configuration
- 8.3.11 Alternate function configuration
- 8.3.12 Analog configuration
- 8.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
- 8.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
- 8.3.15 Selection of RTC_AF1 and RTC_AF2 alternate functions
- 8.4 GPIO registers
- 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..I/J/K)
- 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..I/J/K)
- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K)
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..I/J/K)
- 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I/J/K)
- 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..I/J/K)
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I/J/K)
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..I/J/K)
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K)
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..I/J)
- 8.4.11 GPIO register map
- 9 System configuration controller (SYSCFG)
- 9.1 I/O compensation cell
- 9.2 SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx
- 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 9.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
- 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 9.2.7 Compensation cell control register (SYSCFG_CMPCR)
- 9.2.8 SYSCFG register maps for STM32F405xx/07xx and STM32F415xx/17xx
- 9.3 SYSCFG registers for STM32F42xxx and STM32F43xxx
- 9.3.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 9.3.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
- 9.3.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 9.3.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 9.3.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 9.3.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 9.3.7 Compensation cell control register (SYSCFG_CMPCR)
- 9.3.8 SYSCFG register maps for STM32F42xxx and STM32F43xxx
- 10 DMA controller (DMA)
- 10.1 DMA introduction
- 10.2 DMA main features
- 10.3 DMA functional description
- 10.3.1 General description
- 10.3.2 DMA transactions
- 10.3.3 Channel selection
- 10.3.4 Arbiter
- 10.3.5 DMA streams
- 10.3.6 Source, destination and transfer modes
- 10.3.7 Pointer incrementation
- 10.3.8 Circular mode
- 10.3.9 Double buffer mode
- 10.3.10 Programmable data width, packing/unpacking, endianess
- 10.3.11 Single and burst transfers
- 10.3.12 FIFO
- 10.3.13 DMA transfer completion
- 10.3.14 DMA transfer suspension
- 10.3.15 Flow controller
- 10.3.16 Summary of the possible DMA configurations
- 10.3.17 Stream configuration procedure
- 10.3.18 Error management
- 10.4 DMA interrupts
- 10.5 DMA registers
- 10.5.1 DMA low interrupt status register (DMA_LISR)
- 10.5.2 DMA high interrupt status register (DMA_HISR)
- 10.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
- 10.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
- 10.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)
- 10.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)
- 10.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)
- 10.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
- 10.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
- 10.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)
- 10.5.11 DMA register map
- 11 Chrom-Art Accelerator™ controller (DMA2D)
- 11.1 DMA2D introduction
- 11.2 DMA2D main features
- 11.3 DMA2D functional description
- 11.3.1 General description
- 11.3.2 DMA2D control
- 11.3.3 DMA2D foreground and background FIFOs
- 11.3.4 DMA2D foreground and background pixel format converter (PFC)
- 11.3.5 DMA2D foreground and background CLUT interface
- 11.3.6 DMA2D blender
- 11.3.7 DMA2D output PFC
- 11.3.8 DMA2D output FIFO
- 11.3.9 DMA2D AHB master port timer
- 11.3.10 DMA2D transactions
- 11.3.11 DMA2D configuration
- 11.3.12 DMA2D transfer control (start, suspend, abort and completion)
- 11.3.13 Watermark
- 11.3.14 Error management
- 11.3.15 AHB dead time
- 11.4 DMA2D interrupts
- 11.5 DMA2D registers
- 11.5.1 DMA2D control register (DMA2D_CR)
- 11.5.2 DMA2D Interrupt Status Register (DMA2D_ISR)
- 11.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)
- 11.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)
- 11.5.5 DMA2D foreground offset register (DMA2D_FGOR)
- 11.5.6 DMA2D background memory address register (DMA2D_BGMAR)
- 11.5.7 DMA2D background offset register (DMA2D_BGOR)
- 11.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)
- 11.5.9 DMA2D foreground color register (DMA2D_FGCOLR)
- 11.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR)
- 11.5.11 DMA2D background color register (DMA2D_BGCOLR)
- 11.5.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR)
- 11.5.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR)
- 11.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)
- 11.5.15 DMA2D output color register (DMA2D_OCOLR)
- 11.5.16 DMA2D output memory address register (DMA2D_OMAR)
- 11.5.17 DMA2D output offset register (DMA2D_OOR)
- 11.5.18 DMA2D number of line register (DMA2D_NLR)
- 11.5.19 DMA2D line watermark register (DMA2D_LWR)
- 11.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)
- 11.5.21 DMA2D register map
- 12 Interrupts and events
- 12.1 Nested vectored interrupt controller (NVIC)
- 12.2 External interrupt/event controller (EXTI)
- 12.3 EXTI registers
- 13 Analog-to-digital converter (ADC)
- 13.1 ADC introduction
- 13.2 ADC main features
- 13.3 ADC functional description
- 13.4 Data alignment
- 13.5 Channel-wise programmable sampling time
- 13.6 Conversion on external trigger and trigger polarity
- 13.7 Fast conversion mode
- 13.8 Data management
- 13.9 Multi ADC mode
- 13.10 Temperature sensor
- 13.11 Battery charge monitoring
- 13.12 ADC interrupts
- 13.13 ADC registers
- 13.13.1 ADC status register (ADC_SR)
- 13.13.2 ADC control register 1 (ADC_CR1)
- 13.13.3 ADC control register 2 (ADC_CR2)
- 13.13.4 ADC sample time register 1 (ADC_SMPR1)
- 13.13.5 ADC sample time register 2 (ADC_SMPR2)
- 13.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 13.13.7 ADC watchdog higher threshold register (ADC_HTR)
- 13.13.8 ADC watchdog lower threshold register (ADC_LTR)
- 13.13.9 ADC regular sequence register 1 (ADC_SQR1)
- 13.13.10 ADC regular sequence register 2 (ADC_SQR2)
- 13.13.11 ADC regular sequence register 3 (ADC_SQR3)
- 13.13.12 ADC injected sequence register (ADC_JSQR)
- 13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 13.13.14 ADC regular data register (ADC_DR)
- 13.13.15 ADC Common status register (ADC_CSR)
- 13.13.16 ADC common control register (ADC_CCR)
- 13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR)
- 13.13.18 ADC register map
- 14 Digital-to-analog converter (DAC)
- 14.1 DAC introduction
- 14.2 DAC main features
- 14.3 DAC functional description
- 14.4 Dual DAC channel conversion
- 14.4.1 Independent trigger without wave generation
- 14.4.2 Independent trigger with single LFSR generation
- 14.4.3 Independent trigger with different LFSR generation
- 14.4.4 Independent trigger with single triangle generation
- 14.4.5 Independent trigger with different triangle generation
- 14.4.6 Simultaneous software start
- 14.4.7 Simultaneous trigger without wave generation
- 14.4.8 Simultaneous trigger with single LFSR generation
- 14.4.9 Simultaneous trigger with different LFSR generation
- 14.4.10 Simultaneous trigger with single triangle generation
- 14.4.11 Simultaneous trigger with different triangle generation
- 14.5 DAC registers
- 14.5.1 DAC control register (DAC_CR)
- 14.5.2 DAC software trigger register (DAC_SWTRIGR)
- 14.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 14.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 14.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 14.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 14.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 14.5.12 DAC channel1 data output register (DAC_DOR1)
- 14.5.13 DAC channel2 data output register (DAC_DOR2)
- 14.5.14 DAC status register (DAC_SR)
- 14.5.15 DAC register map
- 15 Digital camera interface (DCMI)
- 15.1 DCMI introduction
- 15.2 DCMI main features
- 15.3 DCMI pins
- 15.4 DCMI clocks
- 15.5 DCMI functional overview
- 15.6 Data format description
- 15.7 DCMI interrupts
- 15.8 DCMI register description
- 15.8.1 DCMI control register 1 (DCMI_CR)
- 15.8.2 DCMI status register (DCMI_SR)
- 15.8.3 DCMI raw interrupt status register (DCMI_RIS)
- 15.8.4 DCMI interrupt enable register (DCMI_IER)
- 15.8.5 DCMI masked interrupt status register (DCMI_MIS)
- 15.8.6 DCMI interrupt clear register (DCMI_ICR)
- 15.8.7 DCMI embedded synchronization code register (DCMI_ESCR)
- 15.8.8 DCMI embedded synchronization unmask register (DCMI_ESUR)
- 15.8.9 DCMI crop window start (DCMI_CWSTRT)
- 15.8.10 DCMI crop window size (DCMI_CWSIZE)
- 15.8.11 DCMI data register (DCMI_DR)
- 15.8.12 DCMI register map
- 16 LCD-TFT controller (LTDC)
- 16.1 Introduction
- 16.2 LTDC main features
- 16.3 LTDC functional description
- 16.4 LTDC programmable parameters
- 16.5 LTDC interrupts
- 16.6 LTDC programming procedure
- 16.7 LTDC registers
- 16.7.1 LTDC Synchronization Size Configuration Register (LTDC_SSCR)
- 16.7.2 LTDC Back Porch Configuration Register (LTDC_BPCR)
- 16.7.3 LTDC Active Width Configuration Register (LTDC_AWCR)
- 16.7.4 LTDC Total Width Configuration Register (LTDC_TWCR)
- 16.7.5 LTDC Global Control Register (LTDC_GCR)
- 16.7.6 LTDC Shadow Reload Configuration Register (LTDC_SRCR)
- 16.7.7 LTDC Background Color Configuration Register (LTDC_BCCR)
- 16.7.8 LTDC Interrupt Enable Register (LTDC_IER)
- 16.7.9 LTDC Interrupt Status Register (LTDC_ISR)
- 16.7.10 LTDC Interrupt Clear Register (LTDC_ICR)
- 16.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)
- 16.7.12 LTDC Current Position Status Register (LTDC_CPSR)
- 16.7.13 LTDC Current Display Status Register (LTDC_CDSR)
- 16.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2)
- 16.7.15 LTDC Layerx Window Horizontal Position Configuration Register (LTDC_LxWHPCR) (where x=1..2)
- 16.7.16 LTDC Layerx Window Vertical Position Configuration Register (LTDC_LxWVPCR) (where x=1..2)
- 16.7.17 LTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR) (where x=1..2)
- 16.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2)
- 16.7.19 LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR) (where x=1..2)
- 16.7.20 LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2)
- 16.7.21 LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2)
- 16.7.22 LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2)
- 16.7.23 LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2)
- 16.7.24 LTDC Layerx ColorFrame Buffer Line Number Register (LTDC_LxCFBLNR) (where x=1..2)
- 16.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2)
- 16.7.26 LTDC register map
- 17 Advanced-control timers (TIM1 and TIM8)
- 17.1 TIM1 and TIM8 introduction
- 17.2 TIM1 and TIM8 main features
- 17.3 TIM1 and TIM8 functional description
- 17.3.1 Time-base unit
- 17.3.2 Counter modes
- 17.3.3 Repetition counter
- 17.3.4 Clock selection
- 17.3.5 Capture/compare channels
- 17.3.6 Input capture mode
- 17.3.7 PWM input mode
- 17.3.8 Forced output mode
- 17.3.9 Output compare mode
- 17.3.10 PWM mode
- 17.3.11 Complementary outputs and dead-time insertion
- 17.3.12 Using the break function
- 17.3.13 Clearing the OCxREF signal on an external event
- 17.3.14 6-step PWM generation
- 17.3.15 One-pulse mode
- 17.3.16 Encoder interface mode
- 17.3.17 Timer input XOR function
- 17.3.18 Interfacing with Hall sensors
- 17.3.19 TIMx and external trigger synchronization
- 17.3.20 Timer synchronization
- 17.3.21 Debug mode
- 17.4 TIM1 and TIM8 registers
- 17.4.1 TIM1 and TIM8 control register 1 (TIMx_CR1)
- 17.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)
- 17.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR)
- 17.4.4 TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)
- 17.4.5 TIM1 and TIM8 status register (TIMx_SR)
- 17.4.6 TIM1 and TIM8 event generation register (TIMx_EGR)
- 17.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)
- 17.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)
- 17.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)
- 17.4.10 TIM1 and TIM8 counter (TIMx_CNT)
- 17.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)
- 17.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)
- 17.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR)
- 17.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)
- 17.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)
- 17.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)
- 17.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)
- 17.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR)
- 17.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR)
- 17.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)
- 17.4.21 TIM1 and TIM8 register map
- 18 General-purpose timers (TIM2 to TIM5)
- 18.1 TIM2 to TIM5 introduction
- 18.2 TIM2 to TIM5 main features
- 18.3 TIM2 to TIM5 functional description
- 18.3.1 Time-base unit
- 18.3.2 Counter modes
- 18.3.3 Clock selection
- 18.3.4 Capture/compare channels
- 18.3.5 Input capture mode
- 18.3.6 PWM input mode
- 18.3.7 Forced output mode
- 18.3.8 Output compare mode
- 18.3.9 PWM mode
- 18.3.10 One-pulse mode
- 18.3.11 Clearing the OCxREF signal on an external event
- 18.3.12 Encoder interface mode
- 18.3.13 Timer input XOR function
- 18.3.14 Timers and external trigger synchronization
- 18.3.15 Timer synchronization
- 18.3.16 Debug mode
- 18.4 TIM2 to TIM5 registers
- 18.4.1 TIMx control register 1 (TIMx_CR1)
- 18.4.2 TIMx control register 2 (TIMx_CR2)
- 18.4.3 TIMx slave mode control register (TIMx_SMCR)
- 18.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 18.4.5 TIMx status register (TIMx_SR)
- 18.4.6 TIMx event generation register (TIMx_EGR)
- 18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 18.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 18.4.10 TIMx counter (TIMx_CNT)
- 18.4.11 TIMx prescaler (TIMx_PSC)
- 18.4.12 TIMx auto-reload register (TIMx_ARR)
- 18.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 18.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 18.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 18.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 18.4.17 TIMx DMA control register (TIMx_DCR)
- 18.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 18.4.19 TIM2 option register (TIM2_OR)
- 18.4.20 TIM5 option register (TIM5_OR)
- 18.4.21 TIMx register map
- 19 General-purpose timers (TIM9 to TIM14)
- 19.1 TIM9 to TIM14 introduction
- 19.2 TIM9 to TIM14 main features
- 19.3 TIM9 to TIM14 functional description
- 19.3.1 Time-base unit
- 19.3.2 Counter modes
- 19.3.3 Clock selection
- 19.3.4 Capture/compare channels
- 19.3.5 Input capture mode
- 19.3.6 PWM input mode (only for TIM9/12)
- 19.3.7 Forced output mode
- 19.3.8 Output compare mode
- 19.3.9 PWM mode
- 19.3.10 One-pulse mode
- 19.3.11 TIM9/12 external trigger synchronization
- 19.3.12 Timer synchronization (TIM9/12)
- 19.3.13 Debug mode
- 19.4 TIM9 and TIM12 registers
- 19.4.1 TIM9/12 control register 1 (TIMx_CR1)
- 19.4.2 TIM9/12 slave mode control register (TIMx_SMCR)
- 19.4.3 TIM9/12 Interrupt enable register (TIMx_DIER)
- 19.4.4 TIM9/12 status register (TIMx_SR)
- 19.4.5 TIM9/12 event generation register (TIMx_EGR)
- 19.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)
- 19.4.7 TIM9/12 capture/compare enable register (TIMx_CCER)
- 19.4.8 TIM9/12 counter (TIMx_CNT)
- 19.4.9 TIM9/12 prescaler (TIMx_PSC)
- 19.4.10 TIM9/12 auto-reload register (TIMx_ARR)
- 19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1)
- 19.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2)
- 19.4.13 TIM9/12 register map
- 19.5 TIM10/11/13/14 registers
- 19.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1)
- 19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
- 19.5.3 TIM10/11/13/14 status register (TIMx_SR)
- 19.5.4 TIM10/11/13/14 event generation register (TIMx_EGR)
- 19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)
- 19.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER)
- 19.5.7 TIM10/11/13/14 counter (TIMx_CNT)
- 19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC)
- 19.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR)
- 19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)
- 19.5.11 TIM11 option register 1 (TIM11_OR)
- 19.5.12 TIM10/11/13/14 register map
- 20 Basic timers (TIM6 and TIM7)
- 20.1 TIM6 and TIM7 introduction
- 20.2 TIM6 and TIM7 main features
- 20.3 TIM6 and TIM7 functional description
- 20.4 TIM6 and TIM7 registers
- 20.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)
- 20.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)
- 20.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 20.4.4 TIM6 and TIM7 status register (TIMx_SR)
- 20.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)
- 20.4.6 TIM6 and TIM7 counter (TIMx_CNT)
- 20.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)
- 20.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)
- 20.4.9 TIM6 and TIM7 register map
- 21 Independent watchdog (IWDG)
- 22 Window watchdog (WWDG)
- 23 Cryptographic processor (CRYP)
- 23.1 CRYP introduction
- 23.2 CRYP main features
- 23.3 CRYP functional description
- 23.4 CRYP interrupts
- 23.5 CRYP DMA interface
- 23.6 CRYP registers
- 23.6.1 CRYP control register (CRYP_CR) for STM32F415/417xx
- 23.6.2 CRYP control register (CRYP_CR) for STM32F415/417xx
- 23.6.3 CRYP status register (CRYP_SR)
- 23.6.4 CRYP data input register (CRYP_DIN)
- 23.6.5 CRYP data output register (CRYP_DOUT)
- 23.6.6 CRYP DMA control register (CRYP_DMACR)
- 23.6.7 CRYP interrupt mask set/clear register (CRYP_IMSCR)
- 23.6.8 CRYP raw interrupt status register (CRYP_RISR)
- 23.6.9 CRYP masked interrupt status register (CRYP_MISR)
- 23.6.10 CRYP key registers (CRYP_K0...3(L/R)R)
- 23.6.11 CRYP initialization vector registers (CRYP_IV0...1(L/R)R)
- 23.6.12 CRYP context swap registers (CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx
- 23.6.13 CRYP register map
- 24 Random number generator (RNG)
- 25 Hash processor (HASH)
- 25.1 HASH introduction
- 25.2 HASH main features
- 25.3 HASH functional description
- 25.4 HASH registers
- 25.4.1 HASH control register (HASH_CR) for STM32F415/417xx
- 25.4.2 HASH control register (HASH_CR) for STM32F43xxx
- 25.4.3 HASH data input register (HASH_DIN)
- 25.4.4 HASH start register (HASH_STR)
- 25.4.5 HASH digest registers (HASH_HR0..4/5/6/7)
- 25.4.6 HASH interrupt enable register (HASH_IMR)
- 25.4.7 HASH status register (HASH_SR)
- 25.4.8 HASH context swap registers (HASH_CSRx)
- 25.4.9 HASH register map
- 26 Real-time clock (RTC)
- 26.1 Introduction
- 26.2 RTC main features
- 26.3 RTC functional description
- 26.3.1 Clock and prescalers
- 26.3.2 Real-time clock and calendar
- 26.3.3 Programmable alarms
- 26.3.4 Periodic auto-wakeup
- 26.3.5 RTC initialization and configuration
- 26.3.6 Reading the calendar
- 26.3.7 Resetting the RTC
- 26.3.8 RTC synchronization
- 26.3.9 RTC reference clock detection
- 26.3.10 RTC coarse digital calibration
- 26.3.11 RTC smooth digital calibration
- 26.3.12 Timestamp function
- 26.3.13 Tamper detection
- 26.3.14 Calibration clock output
- 26.3.15 Alarm output
- 26.4 RTC and low-power modes
- 26.5 RTC interrupts
- 26.6 RTC registers
- 26.6.1 RTC time register (RTC_TR)
- 26.6.2 RTC date register (RTC_DR)
- 26.6.3 RTC control register (RTC_CR)
- 26.6.4 RTC initialization and status register (RTC_ISR)
- 26.6.5 RTC prescaler register (RTC_PRER)
- 26.6.6 RTC wakeup timer register (RTC_WUTR)
- 26.6.7 RTC calibration register (RTC_CALIBR)
- 26.6.8 RTC alarm A register (RTC_ALRMAR)
- 26.6.9 RTC alarm B register (RTC_ALRMBR)
- 26.6.10 RTC write protection register (RTC_WPR)
- 26.6.11 RTC sub second register (RTC_SSR)
- 26.6.12 RTC shift control register (RTC_SHIFTR)
- 26.6.13 RTC time stamp time register (RTC_TSTR)
- 26.6.14 RTC time stamp date register (RTC_TSDR)
- 26.6.15 RTC timestamp sub second register (RTC_TSSSR)
- 26.6.16 RTC calibration register (RTC_CALR)
- 26.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 26.6.18 RTC alarm A sub second register (RTC_ALRMASSR)
- 26.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)
- 26.6.20 RTC backup registers (RTC_BKPxR)
- 26.6.21 RTC register map
- 27 Inter-integrated circuit (I2C) interface
- 27.1 I2C introduction
- 27.2 I2C main features
- 27.3 I2C functional description
- 27.4 I2C interrupts
- 27.5 I2C debug mode
- 27.6 I2C registers
- 27.6.1 I2C Control register 1 (I2C_CR1)
- 27.6.2 I2C Control register 2 (I2C_CR2)
- 27.6.3 I2C Own address register 1 (I2C_OAR1)
- 27.6.4 I2C Own address register 2 (I2C_OAR2)
- 27.6.5 I2C Data register (I2C_DR)
- 27.6.6 I2C Status register 1 (I2C_SR1)
- 27.6.7 I2C Status register 2 (I2C_SR2)
- 27.6.8 I2C Clock control register (I2C_CCR)
- 27.6.9 I2C TRISE register (I2C_TRISE)
- 27.6.10 I2C FLTR register (I2C_FLTR)
- 27.6.11 I2C register map
- 28 Serial peripheral interface (SPI)
- 28.1 SPI introduction
- 28.2 SPI and I2S main features
- 28.3 SPI functional description
- 28.3.1 General description
- 28.3.2 Configuring the SPI in slave mode
- 28.3.3 Configuring the SPI in master mode
- 28.3.4 Configuring the SPI for half-duplex communication
- 28.3.5 Data transmission and reception procedures
- Rx and Tx buffers
- Start sequence in slave mode
- Handling data transmission and reception
- Transmit-only procedure (BIDIMODE=0 RXONLY=0)
- Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)
- Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)
- Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)
- Continuous and discontinuous transfers
- 28.3.6 CRC calculation
- 28.3.7 Status flags
- 28.3.8 Disabling the SPI
- In master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)
- In master or slave unidirectional transmit-only mode (BIDIMODE=0, RXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)
- In master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)
- In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)
- 28.3.9 SPI communication using DMA (direct memory addressing)
- 28.3.10 Error flags
- 28.3.11 SPI interrupts
- 28.4 I2S functional description
- 28.5 SPI and I2S registers
- 28.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)
- 28.5.2 SPI control register 2 (SPI_CR2)
- 28.5.3 SPI status register (SPI_SR)
- 28.5.4 SPI data register (SPI_DR)
- 28.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)
- 28.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)
- 28.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)
- 28.5.8 SPI_I2S configuration register (SPI_I2SCFGR)
- 28.5.9 SPI_I2S prescaler register (SPI_I2SPR)
- 28.5.10 SPI register map
- 29 Serial audio interface (SAI)
- 29.1 Introduction
- 29.2 Main features
- 29.3 Functional block diagram
- 29.4 Main SAI modes
- 29.5 SAI synchronization mode
- 29.6 Audio data size
- 29.7 Frame synchronization
- 29.8 Slot configuration
- 29.9 SAI clock generator
- 29.10 Internal FIFOs
- 29.11 AC’97 link controller
- 29.12 Specific features
- 29.13 Error flags
- 29.14 Interrupt sources
- 29.15 Disabling the SAI
- 29.16 SAI DMA interface
- 29.17 SAI registers
- 29.17.1 SAI xConfiguration register 1 (SAI_xCR1) where x is A or B
- 29.17.2 SAI xConfiguration register 2 (SAI_xCR2) where x is A or B
- 29.17.3 SAI xFrame configuration register (SAI_XFRCR) where x is A or B
- 29.17.4 SAI xSlot register (SAI_xSLOTR) where x is A or B
- 29.17.5 SAI xInterrupt mask register2(SAI_xIM) where x is A or B
- 29.17.6 SAI xStatus register (SAI_xSR) where x is A or B
- 29.17.7 SAI xClear flag register (SAI_xCLRFR) where X is A or B
- 29.17.8 SAI xData register (SAI_xDR) where x is A or B
- 29.17.9 SAI register map
- 30 Universal synchronous asynchronous receiver transmitter (USART)
- 30.1 USART introduction
- 30.2 USART main features
- 30.3 USART functional description
- 30.3.1 USART character description
- 30.3.2 Transmitter
- 30.3.3 Receiver
- 30.3.4 Fractional baud rate generation
- 30.3.5 USART receiver tolerance to clock deviation
- 30.3.6 Multiprocessor communication
- 30.3.7 Parity control
- 30.3.8 LIN (local interconnection network) mode
- 30.3.9 USART synchronous mode
- 30.3.10 Single-wire half-duplex communication
- 30.3.11 Smartcard
- 30.3.12 IrDA SIR ENDEC block
- 30.3.13 Continuous communication using DMA
- 30.3.14 Hardware flow control
- 30.4 USART interrupts
- 30.5 USART mode configuration
- 30.6 USART registers
- 31 Secure digital input/output interface (SDIO)
- 31.1 SDIO main features
- 31.2 SDIO bus topology
- 31.3 SDIO functional description
- 31.4 Card functional description
- 31.4.1 Card identification mode
- 31.4.2 Card reset
- 31.4.3 Operating voltage range validation
- 31.4.4 Card identification process
- 31.4.5 Block write
- 31.4.6 Block read
- 31.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 31.4.8 Erase: group erase and sector erase
- 31.4.9 Wide bus selection or deselection
- 31.4.10 Protection management
- 31.4.11 Card status register
- 31.4.12 SD status register
- 31.4.13 SD I/O mode
- 31.4.14 Commands and responses
- 31.5 Response formats
- 31.6 SDIO I/O card-specific operations
- 31.7 CE-ATA specific operations
- 31.8 HW flow control
- 31.9 SDIO registers
- 31.9.1 SDIO power control register (SDIO_POWER)
- 31.9.2 SDI clock control register (SDIO_CLKCR)
- 31.9.3 SDIO argument register (SDIO_ARG)
- 31.9.4 SDIO command register (SDIO_CMD)
- 31.9.5 SDIO command response register (SDIO_RESPCMD)
- 31.9.6 SDIO response 1..4 register (SDIO_RESPx)
- 31.9.7 SDIO data timer register (SDIO_DTIMER)
- 31.9.8 SDIO data length register (SDIO_DLEN)
- 31.9.9 SDIO data control register (SDIO_DCTRL)
- 31.9.10 SDIO data counter register (SDIO_DCOUNT)
- 31.9.11 SDIO status register (SDIO_STA)
- 31.9.12 SDIO interrupt clear register (SDIO_ICR)
- 31.9.13 SDIO mask register (SDIO_MASK)
- 31.9.14 SDIO FIFO counter register (SDIO_FIFOCNT)
- 31.9.15 SDIO data FIFO register (SDIO_FIFO)
- 31.9.16 SDIO register map
- 32 Controller area network (bxCAN)
- 32.1 bxCAN introduction
- 32.2 bxCAN main features
- 32.3 bxCAN general description
- 32.4 bxCAN operating modes
- 32.5 Test mode
- 32.6 Debug mode
- 32.7 bxCAN functional description
- 32.8 bxCAN interrupts
- 32.9 CAN registers
- 32.9.1 Register access protection
- 32.9.2 CAN control and status registers
- 32.9.3 CAN mailbox registers
- CAN TX mailbox identifier register (CAN_TIxR) (x=0..2)
- CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2)
- CAN mailbox data low register (CAN_TDLxR) (x=0..2)
- CAN mailbox data high register (CAN_TDHxR) (x=0..2)
- CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1)
- CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1)
- CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)
- CAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)
- 32.9.4 CAN filter registers
- 32.9.5 bxCAN register map
- 33 Ethernet (ETH): media access control (MAC) with DMA controller
- 33.1 Ethernet introduction
- 33.2 Ethernet main features
- 33.3 Ethernet pins
- 33.4 Ethernet functional description: SMI, MII and RMII
- 33.5 Ethernet functional description: MAC 802.3
- 33.5.1 MAC 802.3 frame format
- 33.5.2 MAC frame transmission
- 33.5.3 MAC frame reception
- 33.5.4 MAC interrupts
- 33.5.5 MAC filtering
- 33.5.6 MAC loopback mode
- 33.5.7 MAC management counters: MMC
- 33.5.8 Power management: PMT
- 33.5.9 Precision time protocol (IEEE1588 PTP)
- Reference timing source
- Transmission of frames with the PTP feature
- Reception of frames with the PTP feature
- System Time correction methods
- Programming steps for system time generation initialization
- Programming steps for system time update in the Coarse correction method
- Programming steps for system time update in the Fine correction method
- PTP trigger internal connection with TIM2
- PTP pulse-per-second output signal
- 33.6 Ethernet functional description: DMA controller operation
- 33.7 Ethernet interrupts
- 33.8 Ethernet register descriptions
- 33.8.1 MAC register description
- Ethernet MAC configuration register (ETH_MACCR)
- Ethernet MAC frame filter register (ETH_MACFFR)
- Ethernet MAC hash table high register (ETH_MACHTHR)
- Ethernet MAC hash table low register (ETH_MACHTLR)
- Ethernet MAC MII address register (ETH_MACMIIAR)
- Ethernet MAC MII data register (ETH_MACMIIDR)
- Ethernet MAC flow control register (ETH_MACFCR)
- Ethernet MAC VLAN tag register (ETH_MACVLANTR)
- Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
- Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
- Ethernet MAC debug register (ETH_MACDBGR)
- Ethernet MAC interrupt status register (ETH_MACSR)
- Ethernet MAC interrupt mask register (ETH_MACIMR)
- Ethernet MAC address 0 high register (ETH_MACA0HR)
- Ethernet MAC address 0 low register (ETH_MACA0LR)
- Ethernet MAC address 1 high register (ETH_MACA1HR)
- Ethernet MAC address1 low register (ETH_MACA1LR)
- Ethernet MAC address 2 high register (ETH_MACA2HR)
- Ethernet MAC address 2 low register (ETH_MACA2LR)
- Ethernet MAC address 3 high register (ETH_MACA3HR)
- Ethernet MAC address 3 low register (ETH_MACA3LR)
- 33.8.2 MMC register description
- Ethernet MMC control register (ETH_MMCCR)
- Ethernet MMC receive interrupt register (ETH_MMCRIR)
- Ethernet MMC transmit interrupt register (ETH_MMCTIR)
- Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
- Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
- Ethernet MMC transmitted good frames after a single collision counter register (ETH_MMCTGFSCCR)
- Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR)
- Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
- Ethernet MMC received frames with CRC error counter register (ETH_MMCRFCECR)
- Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR)
- MMC received good unicast frames counter register (ETH_MMCRGUFCR)
- 33.8.3 IEEE 1588 time stamp registers
- Ethernet PTP time stamp control register (ETH_PTPTSCR)
- Ethernet PTP subsecond increment register (ETH_PTPSSIR)
- Ethernet PTP time stamp high register (ETH_PTPTSHR)
- Ethernet PTP time stamp low register (ETH_PTPTSLR)
- Ethernet PTP time stamp high update register (ETH_PTPTSHUR)
- Ethernet PTP time stamp low update register (ETH_PTPTSLUR)
- Ethernet PTP time stamp addend register (ETH_PTPTSAR)
- Ethernet PTP target time high register (ETH_PTPTTHR)
- Ethernet PTP target time low register (ETH_PTPTTLR)
- Ethernet PTP time stamp status register (ETH_PTPTSSR)
- Ethernet PTP PPS control register (ETH_PTPPPSCR)
- 33.8.4 DMA register description
- Ethernet DMA bus mode register (ETH_DMABMR)
- Ethernet DMA transmit poll demand register (ETH_DMATPDR)
- EHERNET DMA receive poll demand register (ETH_DMARPDR)
- Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)
- Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)
- Ethernet DMA status register (ETH_DMASR)
- Ethernet DMA operation mode register (ETH_DMAOMR)
- Ethernet DMA interrupt enable register (ETH_DMAIER)
- Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR)
- Ethernet DMA receive status watchdog timer register (ETH_DMARSWTR)
- Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)
- Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)
- Ethernet DMA current host transmit buffer address register (ETH_DMACHTBAR)
- Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR)
- 33.8.5 Ethernet register maps
- 33.8.1 MAC register description
- 34 USB on-the-go full-speed (OTG_FS)
- 34.1 OTG_FS introduction
- 34.2 OTG_FS main features
- 34.3 OTG_FS functional description
- 34.4 OTG dual role device (DRD)
- 34.5 USB peripheral
- 34.6 USB host
- 34.7 SOF trigger
- 34.8 OTG low-power modes
- 34.9 Dynamic update of the OTG_FS_HFIR register
- 34.10 USB data FIFOs
- 34.11 Peripheral FIFO architecture
- 34.12 Host FIFO architecture
- 34.13 FIFO RAM allocation
- 34.14 USB system performance
- 34.15 OTG_FS interrupts
- 34.16 OTG_FS control and status registers
- 34.16.1 CSR memory map
- 34.16.2 OTG_FS global registers
- OTG_FS control and status register (OTG_FS_GOTGCTL)
- OTG_FS interrupt register (OTG_FS_GOTGINT)
- OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
- OTG_FS USB configuration register (OTG_FS_GUSBCFG)
- OTG_FS reset register (OTG_FS_GRSTCTL)
- OTG_FS core interrupt register (OTG_FS_GINTSTS)
- OTG_FS interrupt mask register (OTG_FS_GINTMSK)
- OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)
- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
- OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)
- OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS)
- OTG_FS general core configuration register (OTG_FS_GCCFG)
- OTG_FS core ID register (OTG_FS_CID)
- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number)
- 34.16.3 Host-mode registers
- OTG_FS Host configuration register (OTG_FS_HCFG)
- OTG_FS Host frame interval register (OTG_FS_HFIR)
- OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)
- OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
- OTG_FS Host all channels interrupt register (OTG_FS_HAINT)
- OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)
- OTG_FS Host port control and status register (OTG_FS_HPRT)
- OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number)
- 34.16.4 Device-mode registers
- OTG_FS device configuration register (OTG_FS_DCFG)
- OTG_FS device control register (OTG_FS_DCTL)
- OTG_FS device status register (OTG_FS_DSTS)
- OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
- OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
- OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)
- OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)
- OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK)
- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
- OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0)
- OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)
- OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)
- OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number)
- 34.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
- 34.16.6 OTG_FS register map
- 34.17 OTG_FS programming model
- 35 USB on-the-go high-speed (OTG_HS)
- 35.1 OTG_HS introduction
- 35.2 OTG_HS main features
- 35.3 OTG_HS functional description
- 35.4 OTG dual-role device
- 35.5 USB functional description in peripheral mode
- 35.6 USB functional description on host mode
- 35.7 SOF trigger
- 35.8 OTG_HS low-power modes
- 35.9 Dynamic update of the OTG_HS_HFIR register
- 35.10 FIFO RAM allocation
- 35.11 OTG_HS interrupts
- 35.12 OTG_HS control and status registers
- 35.13 OTG_HS programming model
- 36 Flexible static memory controller (FSMC)
- 36.1 FSMC main features
- 36.2 Block diagram
- 36.3 AHB interface
- 36.4 External device address mapping
- 36.5 NOR Flash/PSRAM controller
- Table 220. Programmable NOR/PSRAM access parameters
- 36.5.1 External memory interface signals
- 36.5.2 Supported memories and transactions
- 36.5.3 General timing rules
- 36.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Asynchronous static memories (NOR Flash memory, PSRAM, SRAM)
- Mode 1 - SRAM/PSRAM (CRAM)
- Mode A - SRAM/PSRAM (CRAM) OE toggling
- Mode 2/B - NOR Flash
- Mode C - NOR Flash - OE toggling
- Mode D - asynchronous access with extended address
- Muxed mode - multiplexed asynchronous access to NOR Flash memory
- WAIT management in asynchronous accesses
- 36.5.5 Synchronous transactions
- 36.5.6 NOR/PSRAM control registers
- 36.6 NAND Flash/PC Card controller
- Table 246. Programmable NAND/PC Card access parameters
- 36.6.1 External memory interface signals
- 36.6.2 NAND Flash / PC Card supported memories and transactions
- 36.6.3 Timing diagrams for NAND and PC Card
- 36.6.4 NAND Flash operations
- 36.6.5 NAND Flash prewait functionality
- 36.6.6 Computation of the error correction code (ECC) in NAND Flash memory
- 36.6.7 PC Card/CompactFlash operations
- 36.6.8 NAND Flash/PC Card control registers
- PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)
- FIFO status and interrupt register 2..4 (FSMC_SR2..4)
- Common memory space timing register 2..4 (FSMC_PMEM2..4)
- Attribute memory space timing registers 2..4 (FSMC_PATT2..4)
- I/O space timing register 4 (FSMC_PIO4)
- ECC result registers 2/3 (FSMC_ECCR2/3)
- 36.6.9 FSMC register map
- 37 Flexible memory controller (FMC)
- 37.1 FMC main features
- 37.2 Block diagram
- 37.3 AHB interface
- 37.4 External device address mapping
- 37.5 NOR Flash/PSRAM controller
- Table 263. Programmable NOR/PSRAM access parameters
- 37.5.1 External memory interface signals
- 37.5.2 Supported memories and transactions
- 37.5.3 General timing rules
- 37.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Asynchronous static memories (NOR Flash, PSRAM, SRAM)
- Mode 1 - SRAM/PSRAM (CRAM)
- Mode A - SRAM/PSRAM (CRAM) OE toggling
- Mode 2/B - NOR Flash
- Mode C - NOR Flash - OE toggling
- Mode D - asynchronous access with extended address
- Muxed mode - multiplexed asynchronous access to NOR Flash memory
- WAIT management in asynchronous accesses
- 37.5.5 Synchronous transactions
- 37.5.6 NOR/PSRAM controller registers
- 37.6 NAND Flash/PC Card controller
- Table 289. Programmable NAND Flash/PC Card access parameters
- 37.6.1 External memory interface signals
- 37.6.2 NAND Flash / PC Card supported memories and transactions
- 37.6.3 Timing diagrams for NAND Flash memory and PC Card
- 37.6.4 NAND Flash operations
- 37.6.5 NAND Flash prewait functionality
- 37.6.6 Computation of the error correction code (ECC) in NAND Flash memory
- 37.6.7 PC Card/CompactFlash operations
- 37.6.8 NAND Flash/PC Card controller registers
- 37.7 SDRAM controller
- 37.8 FMC register map
- 38 Debug support (DBG)
- 38.1 Overview
- 38.2 Reference Arm® documentation
- 38.3 SWJ debug port (serial wire and JTAG)
- 38.4 Pinout and debug port pins
- 38.5 STM32F4xx JTAG TAP connection
- 38.6 ID codes and locking mechanism
- 38.7 JTAG debug port
- 38.8 SW debug port
- 38.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 38.10 Core debug
- 38.11 Capability of the debugger host to connect under system reset
- 38.12 FPB (Flash patch breakpoint)
- 38.13 DWT (data watchpoint trigger)
- 38.14 ITM (instrumentation trace macrocell)
- 38.15 ETM (Embedded trace macrocell)
- 38.16 MCU debug component (DBGMCU)
- 38.17 TPIU (trace port interface unit)
- 38.17.1 Introduction
- 38.17.2 TRACE pin assignment
- 38.17.3 TPUI formatter
- 38.17.4 TPUI frame synchronization packets
- 38.17.5 Transmission of the synchronization frame packet
- 38.17.6 Synchronous mode
- 38.17.7 Asynchronous mode
- 38.17.8 TRACECLKIN connection inside the STM32F4xx
- 38.17.9 TPIU registers
- 38.17.10 Example of configuration
- 38.18 DBG register map
- 39 Device electronic signature
- 40 Revision history